1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ALSA driver for ICEnsemble VT1724 (Envy24HT)
4 *
5 * Lowlevel functions for Infrasonic Quartet
6 *
7 * Copyright (c) 2009 Pavel Hofman <pavel.hofman@ivitera.com>
8 */
9
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/string.h>
15 #include <sound/core.h>
16 #include <sound/tlv.h>
17 #include <sound/info.h>
18
19 #include "ice1712.h"
20 #include "envy24ht.h"
21 #include <sound/ak4113.h>
22 #include "quartet.h"
23
24 struct qtet_spec {
25 struct ak4113 *ak4113;
26 unsigned int scr; /* system control register */
27 unsigned int mcr; /* monitoring control register */
28 unsigned int cpld; /* cpld register */
29 };
30
31 struct qtet_kcontrol_private {
32 unsigned int bit;
33 void (*set_register)(struct snd_ice1712 *ice, unsigned int val);
34 unsigned int (*get_register)(struct snd_ice1712 *ice);
35 const char * const texts[2];
36 };
37
38 enum {
39 IN12_SEL = 0,
40 IN34_SEL,
41 AIN34_SEL,
42 COAX_OUT,
43 IN12_MON12,
44 IN12_MON34,
45 IN34_MON12,
46 IN34_MON34,
47 OUT12_MON34,
48 OUT34_MON12,
49 };
50
51 static const char * const ext_clock_names[3] = {"IEC958 In", "Word Clock 1xFS",
52 "Word Clock 256xFS"};
53
54 /* chip address on I2C bus */
55 #define AK4113_ADDR 0x26 /* S/PDIF receiver */
56
57 /* chip address on SPI bus */
58 #define AK4620_ADDR 0x02 /* ADC/DAC */
59
60
61 /*
62 * GPIO pins
63 */
64
65 /* GPIO0 - O - DATA0, def. 0 */
66 #define GPIO_D0 (1<<0)
67 /* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */
68 #define GPIO_D1_JACKDTC0 (1<<1)
69 /* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */
70 #define GPIO_D2_JACKDTC1 (1<<2)
71 /* GPIO3 - I/O - DATA3, def. 1 */
72 #define GPIO_D3 (1<<3)
73 /* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */
74 #define GPIO_D4_SPI_CDTO (1<<4)
75 /* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */
76 #define GPIO_D5_SPI_CCLK (1<<5)
77 /* GPIO6 - I/O - DATA6, Cable Detect Input (0:detected, 1:not detected */
78 #define GPIO_D6_CD (1<<6)
79 /* GPIO7 - I/O - DATA7, Device Detect Input (0:detected, 1:not detected */
80 #define GPIO_D7_DD (1<<7)
81 /* GPIO8 - O - CPLD Chip Select, def. 1 */
82 #define GPIO_CPLD_CSN (1<<8)
83 /* GPIO9 - O - CPLD register read/write (0:write, 1:read), def. 0 */
84 #define GPIO_CPLD_RW (1<<9)
85 /* GPIO10 - O - SPI Chip Select for CODEC#0, def. 1 */
86 #define GPIO_SPI_CSN0 (1<<10)
87 /* GPIO11 - O - SPI Chip Select for CODEC#1, def. 1 */
88 #define GPIO_SPI_CSN1 (1<<11)
89 /* GPIO12 - O - Ex. Register Output Enable (0:enable, 1:disable), def. 1,
90 * init 0 */
91 #define GPIO_EX_GPIOE (1<<12)
92 /* GPIO13 - O - Ex. Register0 Chip Select for System Control Register,
93 * def. 1 */
94 #define GPIO_SCR (1<<13)
95 /* GPIO14 - O - Ex. Register1 Chip Select for Monitor Control Register,
96 * def. 1 */
97 #define GPIO_MCR (1<<14)
98
99 #define GPIO_SPI_ALL (GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK |\
100 GPIO_SPI_CSN0 | GPIO_SPI_CSN1)
101
102 #define GPIO_DATA_MASK (GPIO_D0 | GPIO_D1_JACKDTC0 | \
103 GPIO_D2_JACKDTC1 | GPIO_D3 | \
104 GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK | \
105 GPIO_D6_CD | GPIO_D7_DD)
106
107 /* System Control Register GPIO_SCR data bits */
108 /* Mic/Line select relay (0:line, 1:mic) */
109 #define SCR_RELAY GPIO_D0
110 /* Phantom power drive control (0:5V, 1:48V) */
111 #define SCR_PHP_V GPIO_D1_JACKDTC0
112 /* H/W mute control (0:Normal, 1:Mute) */
113 #define SCR_MUTE GPIO_D2_JACKDTC1
114 /* Phantom power control (0:Phantom on, 1:off) */
115 #define SCR_PHP GPIO_D3
116 /* Analog input 1/2 Source Select */
117 #define SCR_AIN12_SEL0 GPIO_D4_SPI_CDTO
118 #define SCR_AIN12_SEL1 GPIO_D5_SPI_CCLK
119 /* Analog input 3/4 Source Select (0:line, 1:hi-z) */
120 #define SCR_AIN34_SEL GPIO_D6_CD
121 /* Codec Power Down (0:power down, 1:normal) */
122 #define SCR_CODEC_PDN GPIO_D7_DD
123
124 #define SCR_AIN12_LINE (0)
125 #define SCR_AIN12_MIC (SCR_AIN12_SEL0)
126 #define SCR_AIN12_LOWCUT (SCR_AIN12_SEL1 | SCR_AIN12_SEL0)
127
128 /* Monitor Control Register GPIO_MCR data bits */
129 /* Input 1/2 to Monitor 1/2 (0:off, 1:on) */
130 #define MCR_IN12_MON12 GPIO_D0
131 /* Input 1/2 to Monitor 3/4 (0:off, 1:on) */
132 #define MCR_IN12_MON34 GPIO_D1_JACKDTC0
133 /* Input 3/4 to Monitor 1/2 (0:off, 1:on) */
134 #define MCR_IN34_MON12 GPIO_D2_JACKDTC1
135 /* Input 3/4 to Monitor 3/4 (0:off, 1:on) */
136 #define MCR_IN34_MON34 GPIO_D3
137 /* Output to Monitor 1/2 (0:off, 1:on) */
138 #define MCR_OUT34_MON12 GPIO_D4_SPI_CDTO
139 /* Output to Monitor 3/4 (0:off, 1:on) */
140 #define MCR_OUT12_MON34 GPIO_D5_SPI_CCLK
141
142 /* CPLD Register DATA bits */
143 /* Clock Rate Select */
144 #define CPLD_CKS0 GPIO_D0
145 #define CPLD_CKS1 GPIO_D1_JACKDTC0
146 #define CPLD_CKS2 GPIO_D2_JACKDTC1
147 /* Sync Source Select (0:Internal, 1:External) */
148 #define CPLD_SYNC_SEL GPIO_D3
149 /* Word Clock FS Select (0:FS, 1:256FS) */
150 #define CPLD_WORD_SEL GPIO_D4_SPI_CDTO
151 /* Coaxial Output Source (IS-Link) (0:SPDIF, 1:I2S) */
152 #define CPLD_COAX_OUT GPIO_D5_SPI_CCLK
153 /* Input 1/2 Source Select (0:Analog12, 1:An34) */
154 #define CPLD_IN12_SEL GPIO_D6_CD
155 /* Input 3/4 Source Select (0:Analog34, 1:Digital In) */
156 #define CPLD_IN34_SEL GPIO_D7_DD
157
158 /* internal clock (CPLD_SYNC_SEL = 0) options */
159 #define CPLD_CKS_44100HZ (0)
160 #define CPLD_CKS_48000HZ (CPLD_CKS0)
161 #define CPLD_CKS_88200HZ (CPLD_CKS1)
162 #define CPLD_CKS_96000HZ (CPLD_CKS1 | CPLD_CKS0)
163 #define CPLD_CKS_176400HZ (CPLD_CKS2)
164 #define CPLD_CKS_192000HZ (CPLD_CKS2 | CPLD_CKS0)
165
166 #define CPLD_CKS_MASK (CPLD_CKS0 | CPLD_CKS1 | CPLD_CKS2)
167
168 /* external clock (CPLD_SYNC_SEL = 1) options */
169 /* external clock - SPDIF */
170 #define CPLD_EXT_SPDIF (0 | CPLD_SYNC_SEL)
171 /* external clock - WordClock 1xfs */
172 #define CPLD_EXT_WORDCLOCK_1FS (CPLD_CKS1 | CPLD_SYNC_SEL)
173 /* external clock - WordClock 256xfs */
174 #define CPLD_EXT_WORDCLOCK_256FS (CPLD_CKS1 | CPLD_WORD_SEL |\
175 CPLD_SYNC_SEL)
176
177 #define EXT_SPDIF_TYPE 0
178 #define EXT_WORDCLOCK_1FS_TYPE 1
179 #define EXT_WORDCLOCK_256FS_TYPE 2
180
181 #define AK4620_DFS0 (1<<0)
182 #define AK4620_DFS1 (1<<1)
183 #define AK4620_CKS0 (1<<2)
184 #define AK4620_CKS1 (1<<3)
185 /* Clock and Format Control register */
186 #define AK4620_DFS_REG 0x02
187
188 /* Deem and Volume Control register */
189 #define AK4620_DEEMVOL_REG 0x03
190 #define AK4620_SMUTE (1<<7)
191
192 /*
193 * Conversion from int value to its binary form. Used for debugging.
194 * The output buffer must be allocated prior to calling the function.
195 */
get_binary(char * buffer,int value)196 static char *get_binary(char *buffer, int value)
197 {
198 int i, j, pos;
199 pos = 0;
200 for (i = 0; i < 4; ++i) {
201 for (j = 0; j < 8; ++j) {
202 if (value & (1 << (31-(i*8 + j))))
203 buffer[pos] = '1';
204 else
205 buffer[pos] = '0';
206 pos++;
207 }
208 if (i < 3) {
209 buffer[pos] = ' ';
210 pos++;
211 }
212 }
213 buffer[pos] = '\0';
214 return buffer;
215 }
216
217 /*
218 * Initial setup of the conversion array GPIO <-> rate
219 */
220 static const unsigned int qtet_rates[] = {
221 44100, 48000, 88200,
222 96000, 176400, 192000,
223 };
224
225 static const unsigned int cks_vals[] = {
226 CPLD_CKS_44100HZ, CPLD_CKS_48000HZ, CPLD_CKS_88200HZ,
227 CPLD_CKS_96000HZ, CPLD_CKS_176400HZ, CPLD_CKS_192000HZ,
228 };
229
230 static const struct snd_pcm_hw_constraint_list qtet_rates_info = {
231 .count = ARRAY_SIZE(qtet_rates),
232 .list = qtet_rates,
233 .mask = 0,
234 };
235
qtet_ak4113_write(void * private_data,unsigned char reg,unsigned char val)236 static void qtet_ak4113_write(void *private_data, unsigned char reg,
237 unsigned char val)
238 {
239 snd_vt1724_write_i2c((struct snd_ice1712 *)private_data, AK4113_ADDR,
240 reg, val);
241 }
242
qtet_ak4113_read(void * private_data,unsigned char reg)243 static unsigned char qtet_ak4113_read(void *private_data, unsigned char reg)
244 {
245 return snd_vt1724_read_i2c((struct snd_ice1712 *)private_data,
246 AK4113_ADDR, reg);
247 }
248
249
250 /*
251 * AK4620 section
252 */
253
254 /*
255 * Write data to addr register of ak4620
256 */
qtet_akm_write(struct snd_akm4xxx * ak,int chip,unsigned char addr,unsigned char data)257 static void qtet_akm_write(struct snd_akm4xxx *ak, int chip,
258 unsigned char addr, unsigned char data)
259 {
260 unsigned int tmp, orig_dir;
261 int idx;
262 unsigned int addrdata;
263 struct snd_ice1712 *ice = ak->private_data[0];
264
265 if (snd_BUG_ON(chip < 0 || chip >= 4))
266 return;
267 /*dev_dbg(ice->card->dev, "Writing to AK4620: chip=%d, addr=0x%x,
268 data=0x%x\n", chip, addr, data);*/
269 orig_dir = ice->gpio.get_dir(ice);
270 ice->gpio.set_dir(ice, orig_dir | GPIO_SPI_ALL);
271 /* set mask - only SPI bits */
272 ice->gpio.set_mask(ice, ~GPIO_SPI_ALL);
273
274 tmp = ice->gpio.get_data(ice);
275 /* high all */
276 tmp |= GPIO_SPI_ALL;
277 ice->gpio.set_data(ice, tmp);
278 udelay(100);
279 /* drop chip select */
280 if (chip)
281 /* CODEC 1 */
282 tmp &= ~GPIO_SPI_CSN1;
283 else
284 tmp &= ~GPIO_SPI_CSN0;
285 ice->gpio.set_data(ice, tmp);
286 udelay(100);
287
288 /* build I2C address + data byte */
289 addrdata = (AK4620_ADDR << 6) | 0x20 | (addr & 0x1f);
290 addrdata = (addrdata << 8) | data;
291 for (idx = 15; idx >= 0; idx--) {
292 /* drop clock */
293 tmp &= ~GPIO_D5_SPI_CCLK;
294 ice->gpio.set_data(ice, tmp);
295 udelay(100);
296 /* set data */
297 if (addrdata & (1 << idx))
298 tmp |= GPIO_D4_SPI_CDTO;
299 else
300 tmp &= ~GPIO_D4_SPI_CDTO;
301 ice->gpio.set_data(ice, tmp);
302 udelay(100);
303 /* raise clock */
304 tmp |= GPIO_D5_SPI_CCLK;
305 ice->gpio.set_data(ice, tmp);
306 udelay(100);
307 }
308 /* all back to 1 */
309 tmp |= GPIO_SPI_ALL;
310 ice->gpio.set_data(ice, tmp);
311 udelay(100);
312
313 /* return all gpios to non-writable */
314 ice->gpio.set_mask(ice, 0xffffff);
315 /* restore GPIOs direction */
316 ice->gpio.set_dir(ice, orig_dir);
317 }
318
qtet_akm_set_regs(struct snd_akm4xxx * ak,unsigned char addr,unsigned char mask,unsigned char value)319 static void qtet_akm_set_regs(struct snd_akm4xxx *ak, unsigned char addr,
320 unsigned char mask, unsigned char value)
321 {
322 unsigned char tmp;
323 int chip;
324 for (chip = 0; chip < ak->num_chips; chip++) {
325 tmp = snd_akm4xxx_get(ak, chip, addr);
326 /* clear the bits */
327 tmp &= ~mask;
328 /* set the new bits */
329 tmp |= value;
330 snd_akm4xxx_write(ak, chip, addr, tmp);
331 }
332 }
333
334 /*
335 * change the rate of AK4620
336 */
qtet_akm_set_rate_val(struct snd_akm4xxx * ak,unsigned int rate)337 static void qtet_akm_set_rate_val(struct snd_akm4xxx *ak, unsigned int rate)
338 {
339 unsigned char ak4620_dfs;
340
341 if (rate == 0) /* no hint - S/PDIF input is master or the new spdif
342 input rate undetected, simply return */
343 return;
344
345 /* adjust DFS on codecs - see datasheet */
346 if (rate > 108000)
347 ak4620_dfs = AK4620_DFS1 | AK4620_CKS1;
348 else if (rate > 54000)
349 ak4620_dfs = AK4620_DFS0 | AK4620_CKS0;
350 else
351 ak4620_dfs = 0;
352
353 /* set new value */
354 qtet_akm_set_regs(ak, AK4620_DFS_REG, AK4620_DFS0 | AK4620_DFS1 |
355 AK4620_CKS0 | AK4620_CKS1, ak4620_dfs);
356 }
357
358 #define AK_CONTROL(xname, xch) { .name = xname, .num_channels = xch }
359
360 #define PCM_12_PLAYBACK_VOLUME "PCM 1/2 Playback Volume"
361 #define PCM_34_PLAYBACK_VOLUME "PCM 3/4 Playback Volume"
362 #define PCM_12_CAPTURE_VOLUME "PCM 1/2 Capture Volume"
363 #define PCM_34_CAPTURE_VOLUME "PCM 3/4 Capture Volume"
364
365 static const struct snd_akm4xxx_dac_channel qtet_dac[] = {
366 AK_CONTROL(PCM_12_PLAYBACK_VOLUME, 2),
367 AK_CONTROL(PCM_34_PLAYBACK_VOLUME, 2),
368 };
369
370 static const struct snd_akm4xxx_adc_channel qtet_adc[] = {
371 AK_CONTROL(PCM_12_CAPTURE_VOLUME, 2),
372 AK_CONTROL(PCM_34_CAPTURE_VOLUME, 2),
373 };
374
375 static const struct snd_akm4xxx akm_qtet_dac = {
376 .type = SND_AK4620,
377 .num_dacs = 4, /* DAC1 - Output 12
378 */
379 .num_adcs = 4, /* ADC1 - Input 12
380 */
381 .ops = {
382 .write = qtet_akm_write,
383 .set_rate_val = qtet_akm_set_rate_val,
384 },
385 .dac_info = qtet_dac,
386 .adc_info = qtet_adc,
387 };
388
389 /* Communication routines with the CPLD */
390
391
392 /* Writes data to external register reg, both reg and data are
393 * GPIO representations */
reg_write(struct snd_ice1712 * ice,unsigned int reg,unsigned int data)394 static void reg_write(struct snd_ice1712 *ice, unsigned int reg,
395 unsigned int data)
396 {
397 unsigned int tmp;
398
399 guard(mutex)(&ice->gpio_mutex);
400 /* set direction of used GPIOs*/
401 /* all outputs */
402 tmp = 0x00ffff;
403 ice->gpio.set_dir(ice, tmp);
404 /* mask - writable bits */
405 ice->gpio.set_mask(ice, ~(tmp));
406 /* write the data */
407 tmp = ice->gpio.get_data(ice);
408 tmp &= ~GPIO_DATA_MASK;
409 tmp |= data;
410 ice->gpio.set_data(ice, tmp);
411 udelay(100);
412 /* drop output enable */
413 tmp &= ~GPIO_EX_GPIOE;
414 ice->gpio.set_data(ice, tmp);
415 udelay(100);
416 /* drop the register gpio */
417 tmp &= ~reg;
418 ice->gpio.set_data(ice, tmp);
419 udelay(100);
420 /* raise the register GPIO */
421 tmp |= reg;
422 ice->gpio.set_data(ice, tmp);
423 udelay(100);
424
425 /* raise all data gpios */
426 tmp |= GPIO_DATA_MASK;
427 ice->gpio.set_data(ice, tmp);
428 /* mask - immutable bits */
429 ice->gpio.set_mask(ice, 0xffffff);
430 /* outputs only 8-15 */
431 ice->gpio.set_dir(ice, 0x00ff00);
432 }
433
get_scr(struct snd_ice1712 * ice)434 static unsigned int get_scr(struct snd_ice1712 *ice)
435 {
436 struct qtet_spec *spec = ice->spec;
437 return spec->scr;
438 }
439
get_mcr(struct snd_ice1712 * ice)440 static unsigned int get_mcr(struct snd_ice1712 *ice)
441 {
442 struct qtet_spec *spec = ice->spec;
443 return spec->mcr;
444 }
445
get_cpld(struct snd_ice1712 * ice)446 static unsigned int get_cpld(struct snd_ice1712 *ice)
447 {
448 struct qtet_spec *spec = ice->spec;
449 return spec->cpld;
450 }
451
set_scr(struct snd_ice1712 * ice,unsigned int val)452 static void set_scr(struct snd_ice1712 *ice, unsigned int val)
453 {
454 struct qtet_spec *spec = ice->spec;
455 reg_write(ice, GPIO_SCR, val);
456 spec->scr = val;
457 }
458
set_mcr(struct snd_ice1712 * ice,unsigned int val)459 static void set_mcr(struct snd_ice1712 *ice, unsigned int val)
460 {
461 struct qtet_spec *spec = ice->spec;
462 reg_write(ice, GPIO_MCR, val);
463 spec->mcr = val;
464 }
465
set_cpld(struct snd_ice1712 * ice,unsigned int val)466 static void set_cpld(struct snd_ice1712 *ice, unsigned int val)
467 {
468 struct qtet_spec *spec = ice->spec;
469 reg_write(ice, GPIO_CPLD_CSN, val);
470 spec->cpld = val;
471 }
472
proc_regs_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)473 static void proc_regs_read(struct snd_info_entry *entry,
474 struct snd_info_buffer *buffer)
475 {
476 struct snd_ice1712 *ice = entry->private_data;
477 char bin_buffer[36];
478
479 snd_iprintf(buffer, "SCR: %s\n", get_binary(bin_buffer,
480 get_scr(ice)));
481 snd_iprintf(buffer, "MCR: %s\n", get_binary(bin_buffer,
482 get_mcr(ice)));
483 snd_iprintf(buffer, "CPLD: %s\n", get_binary(bin_buffer,
484 get_cpld(ice)));
485 }
486
proc_init(struct snd_ice1712 * ice)487 static void proc_init(struct snd_ice1712 *ice)
488 {
489 snd_card_ro_proc_new(ice->card, "quartet", ice, proc_regs_read);
490 }
491
qtet_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)492 static int qtet_mute_get(struct snd_kcontrol *kcontrol,
493 struct snd_ctl_elem_value *ucontrol)
494 {
495 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
496 unsigned int val;
497 val = get_scr(ice) & SCR_MUTE;
498 ucontrol->value.integer.value[0] = (val) ? 0 : 1;
499 return 0;
500 }
501
qtet_mute_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)502 static int qtet_mute_put(struct snd_kcontrol *kcontrol,
503 struct snd_ctl_elem_value *ucontrol)
504 {
505 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
506 unsigned int old, new, smute;
507 old = get_scr(ice) & SCR_MUTE;
508 if (ucontrol->value.integer.value[0]) {
509 /* unmute */
510 new = 0;
511 /* un-smuting DAC */
512 smute = 0;
513 } else {
514 /* mute */
515 new = SCR_MUTE;
516 /* smuting DAC */
517 smute = AK4620_SMUTE;
518 }
519 if (old != new) {
520 struct snd_akm4xxx *ak = ice->akm;
521 set_scr(ice, (get_scr(ice) & ~SCR_MUTE) | new);
522 /* set smute */
523 qtet_akm_set_regs(ak, AK4620_DEEMVOL_REG, AK4620_SMUTE, smute);
524 return 1;
525 }
526 /* no change */
527 return 0;
528 }
529
qtet_ain12_enum_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)530 static int qtet_ain12_enum_info(struct snd_kcontrol *kcontrol,
531 struct snd_ctl_elem_info *uinfo)
532 {
533 static const char * const texts[3] =
534 {"Line In 1/2", "Mic", "Mic + Low-cut"};
535 return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(texts), texts);
536 }
537
qtet_ain12_sw_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)538 static int qtet_ain12_sw_get(struct snd_kcontrol *kcontrol,
539 struct snd_ctl_elem_value *ucontrol)
540 {
541 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
542 unsigned int val, result;
543 val = get_scr(ice) & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
544 switch (val) {
545 case SCR_AIN12_LINE:
546 result = 0;
547 break;
548 case SCR_AIN12_MIC:
549 result = 1;
550 break;
551 case SCR_AIN12_LOWCUT:
552 result = 2;
553 break;
554 default:
555 /* BUG - no other combinations allowed */
556 snd_BUG();
557 result = 0;
558 }
559 ucontrol->value.integer.value[0] = result;
560 return 0;
561 }
562
qtet_ain12_sw_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)563 static int qtet_ain12_sw_put(struct snd_kcontrol *kcontrol,
564 struct snd_ctl_elem_value *ucontrol)
565 {
566 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
567 unsigned int old, new, tmp, masked_old;
568 old = get_scr(ice);
569 masked_old = old & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
570 tmp = ucontrol->value.integer.value[0];
571 if (tmp == 2)
572 tmp = 3; /* binary 10 is not supported */
573 tmp <<= 4; /* shifting to SCR_AIN12_SEL0 */
574 if (tmp != masked_old) {
575 /* change requested */
576 switch (tmp) {
577 case SCR_AIN12_LINE:
578 new = old & ~(SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
579 set_scr(ice, new);
580 /* turn off relay */
581 new &= ~SCR_RELAY;
582 set_scr(ice, new);
583 break;
584 case SCR_AIN12_MIC:
585 /* turn on relay */
586 new = old | SCR_RELAY;
587 set_scr(ice, new);
588 new = (new & ~SCR_AIN12_SEL1) | SCR_AIN12_SEL0;
589 set_scr(ice, new);
590 break;
591 case SCR_AIN12_LOWCUT:
592 /* turn on relay */
593 new = old | SCR_RELAY;
594 set_scr(ice, new);
595 new |= SCR_AIN12_SEL1 | SCR_AIN12_SEL0;
596 set_scr(ice, new);
597 break;
598 default:
599 snd_BUG();
600 }
601 return 1;
602 }
603 /* no change */
604 return 0;
605 }
606
qtet_php_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)607 static int qtet_php_get(struct snd_kcontrol *kcontrol,
608 struct snd_ctl_elem_value *ucontrol)
609 {
610 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
611 unsigned int val;
612 /* if phantom voltage =48V, phantom on */
613 val = get_scr(ice) & SCR_PHP_V;
614 ucontrol->value.integer.value[0] = val ? 1 : 0;
615 return 0;
616 }
617
qtet_php_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)618 static int qtet_php_put(struct snd_kcontrol *kcontrol,
619 struct snd_ctl_elem_value *ucontrol)
620 {
621 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
622 unsigned int old, new;
623 old = new = get_scr(ice);
624 if (ucontrol->value.integer.value[0] /* phantom on requested */
625 && (~old & SCR_PHP_V)) /* 0 = voltage 5V */ {
626 /* is off, turn on */
627 /* turn voltage on first, = 1 */
628 new = old | SCR_PHP_V;
629 set_scr(ice, new);
630 /* turn phantom on, = 0 */
631 new &= ~SCR_PHP;
632 set_scr(ice, new);
633 } else if (!ucontrol->value.integer.value[0] && (old & SCR_PHP_V)) {
634 /* phantom off requested and 1 = voltage 48V */
635 /* is on, turn off */
636 /* turn voltage off first, = 0 */
637 new = old & ~SCR_PHP_V;
638 set_scr(ice, new);
639 /* turn phantom off, = 1 */
640 new |= SCR_PHP;
641 set_scr(ice, new);
642 }
643 if (old != new)
644 return 1;
645 /* no change */
646 return 0;
647 }
648
649 #define PRIV_SW(xid, xbit, xreg) [xid] = {.bit = xbit,\
650 .set_register = set_##xreg,\
651 .get_register = get_##xreg, }
652
653
654 #define PRIV_ENUM2(xid, xbit, xreg, xtext1, xtext2) [xid] = {.bit = xbit,\
655 .set_register = set_##xreg,\
656 .get_register = get_##xreg,\
657 .texts = {xtext1, xtext2} }
658
659 static const struct qtet_kcontrol_private qtet_privates[] = {
660 PRIV_ENUM2(IN12_SEL, CPLD_IN12_SEL, cpld, "An In 1/2", "An In 3/4"),
661 PRIV_ENUM2(IN34_SEL, CPLD_IN34_SEL, cpld, "An In 3/4", "IEC958 In"),
662 PRIV_ENUM2(AIN34_SEL, SCR_AIN34_SEL, scr, "Line In 3/4", "Hi-Z"),
663 PRIV_ENUM2(COAX_OUT, CPLD_COAX_OUT, cpld, "IEC958", "I2S"),
664 PRIV_SW(IN12_MON12, MCR_IN12_MON12, mcr),
665 PRIV_SW(IN12_MON34, MCR_IN12_MON34, mcr),
666 PRIV_SW(IN34_MON12, MCR_IN34_MON12, mcr),
667 PRIV_SW(IN34_MON34, MCR_IN34_MON34, mcr),
668 PRIV_SW(OUT12_MON34, MCR_OUT12_MON34, mcr),
669 PRIV_SW(OUT34_MON12, MCR_OUT34_MON12, mcr),
670 };
671
qtet_enum_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)672 static int qtet_enum_info(struct snd_kcontrol *kcontrol,
673 struct snd_ctl_elem_info *uinfo)
674 {
675 struct qtet_kcontrol_private private =
676 qtet_privates[kcontrol->private_value];
677 return snd_ctl_enum_info(uinfo, 1, ARRAY_SIZE(private.texts),
678 private.texts);
679 }
680
qtet_sw_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)681 static int qtet_sw_get(struct snd_kcontrol *kcontrol,
682 struct snd_ctl_elem_value *ucontrol)
683 {
684 struct qtet_kcontrol_private private =
685 qtet_privates[kcontrol->private_value];
686 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
687 ucontrol->value.integer.value[0] =
688 (private.get_register(ice) & private.bit) ? 1 : 0;
689 return 0;
690 }
691
qtet_sw_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)692 static int qtet_sw_put(struct snd_kcontrol *kcontrol,
693 struct snd_ctl_elem_value *ucontrol)
694 {
695 struct qtet_kcontrol_private private =
696 qtet_privates[kcontrol->private_value];
697 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
698 unsigned int old, new;
699 old = private.get_register(ice);
700 if (ucontrol->value.integer.value[0])
701 new = old | private.bit;
702 else
703 new = old & ~private.bit;
704 if (old != new) {
705 private.set_register(ice, new);
706 return 1;
707 }
708 /* no change */
709 return 0;
710 }
711
712 #define qtet_sw_info snd_ctl_boolean_mono_info
713
714 #define QTET_CONTROL(xname, xtype, xpriv) \
715 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER,\
716 .name = xname,\
717 .info = qtet_##xtype##_info,\
718 .get = qtet_sw_get,\
719 .put = qtet_sw_put,\
720 .private_value = xpriv }
721
722 static const struct snd_kcontrol_new qtet_controls[] = {
723 {
724 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
725 .name = "Master Playback Switch",
726 .info = qtet_sw_info,
727 .get = qtet_mute_get,
728 .put = qtet_mute_put,
729 .private_value = 0
730 },
731 {
732 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
733 .name = "Phantom Power",
734 .info = qtet_sw_info,
735 .get = qtet_php_get,
736 .put = qtet_php_put,
737 .private_value = 0
738 },
739 {
740 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
741 .name = "Analog In 1/2 Capture Switch",
742 .info = qtet_ain12_enum_info,
743 .get = qtet_ain12_sw_get,
744 .put = qtet_ain12_sw_put,
745 .private_value = 0
746 },
747 QTET_CONTROL("Analog In 3/4 Capture Switch", enum, AIN34_SEL),
748 QTET_CONTROL("PCM In 1/2 Capture Switch", enum, IN12_SEL),
749 QTET_CONTROL("PCM In 3/4 Capture Switch", enum, IN34_SEL),
750 QTET_CONTROL("Coax Output Source", enum, COAX_OUT),
751 QTET_CONTROL("Analog In 1/2 to Monitor 1/2", sw, IN12_MON12),
752 QTET_CONTROL("Analog In 1/2 to Monitor 3/4", sw, IN12_MON34),
753 QTET_CONTROL("Analog In 3/4 to Monitor 1/2", sw, IN34_MON12),
754 QTET_CONTROL("Analog In 3/4 to Monitor 3/4", sw, IN34_MON34),
755 QTET_CONTROL("Output 1/2 to Monitor 3/4", sw, OUT12_MON34),
756 QTET_CONTROL("Output 3/4 to Monitor 1/2", sw, OUT34_MON12),
757 };
758
759 static const char * const follower_vols[] = {
760 PCM_12_PLAYBACK_VOLUME,
761 PCM_34_PLAYBACK_VOLUME,
762 NULL
763 };
764
765 static
766 DECLARE_TLV_DB_SCALE(qtet_master_db_scale, -6350, 50, 1);
767
qtet_add_controls(struct snd_ice1712 * ice)768 static int qtet_add_controls(struct snd_ice1712 *ice)
769 {
770 struct qtet_spec *spec = ice->spec;
771 int err, i;
772 struct snd_kcontrol *vmaster;
773 err = snd_ice1712_akm4xxx_build_controls(ice);
774 if (err < 0)
775 return err;
776 for (i = 0; i < ARRAY_SIZE(qtet_controls); i++) {
777 err = snd_ctl_add(ice->card,
778 snd_ctl_new1(&qtet_controls[i], ice));
779 if (err < 0)
780 return err;
781 }
782
783 /* Create virtual master control */
784 vmaster = snd_ctl_make_virtual_master("Master Playback Volume",
785 qtet_master_db_scale);
786 if (!vmaster)
787 return -ENOMEM;
788 err = snd_ctl_add(ice->card, vmaster);
789 if (err < 0)
790 return err;
791 err = snd_ctl_add_followers(ice->card, vmaster, follower_vols);
792 if (err < 0)
793 return err;
794 /* only capture SPDIF over AK4113 */
795 return snd_ak4113_build(spec->ak4113,
796 ice->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
797 }
798
qtet_is_spdif_master(struct snd_ice1712 * ice)799 static inline int qtet_is_spdif_master(struct snd_ice1712 *ice)
800 {
801 /* CPLD_SYNC_SEL: 0 = internal, 1 = external (i.e. spdif master) */
802 return (get_cpld(ice) & CPLD_SYNC_SEL) ? 1 : 0;
803 }
804
qtet_get_rate(struct snd_ice1712 * ice)805 static unsigned int qtet_get_rate(struct snd_ice1712 *ice)
806 {
807 int i;
808 unsigned char result;
809
810 result = get_cpld(ice) & CPLD_CKS_MASK;
811 for (i = 0; i < ARRAY_SIZE(cks_vals); i++)
812 if (cks_vals[i] == result)
813 return qtet_rates[i];
814 return 0;
815 }
816
get_cks_val(int rate)817 static int get_cks_val(int rate)
818 {
819 int i;
820 for (i = 0; i < ARRAY_SIZE(qtet_rates); i++)
821 if (qtet_rates[i] == rate)
822 return cks_vals[i];
823 return 0;
824 }
825
826 /* setting new rate */
qtet_set_rate(struct snd_ice1712 * ice,unsigned int rate)827 static void qtet_set_rate(struct snd_ice1712 *ice, unsigned int rate)
828 {
829 unsigned int new;
830 unsigned char val;
831 /* switching ice1724 to external clock - supplied by ext. circuits */
832 val = inb(ICEMT1724(ice, RATE));
833 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
834
835 new = (get_cpld(ice) & ~CPLD_CKS_MASK) | get_cks_val(rate);
836 /* switch to internal clock, drop CPLD_SYNC_SEL */
837 new &= ~CPLD_SYNC_SEL;
838 /* dev_dbg(ice->card->dev, "QT - set_rate: old %x, new %x\n",
839 get_cpld(ice), new); */
840 set_cpld(ice, new);
841 }
842
qtet_set_mclk(struct snd_ice1712 * ice,unsigned int rate)843 static inline unsigned char qtet_set_mclk(struct snd_ice1712 *ice,
844 unsigned int rate)
845 {
846 /* no change in master clock */
847 return 0;
848 }
849
850 /* setting clock to external - SPDIF */
qtet_set_spdif_clock(struct snd_ice1712 * ice,int type)851 static int qtet_set_spdif_clock(struct snd_ice1712 *ice, int type)
852 {
853 unsigned int old, new;
854
855 old = new = get_cpld(ice);
856 new &= ~(CPLD_CKS_MASK | CPLD_WORD_SEL);
857 switch (type) {
858 case EXT_SPDIF_TYPE:
859 new |= CPLD_EXT_SPDIF;
860 break;
861 case EXT_WORDCLOCK_1FS_TYPE:
862 new |= CPLD_EXT_WORDCLOCK_1FS;
863 break;
864 case EXT_WORDCLOCK_256FS_TYPE:
865 new |= CPLD_EXT_WORDCLOCK_256FS;
866 break;
867 default:
868 snd_BUG();
869 }
870 if (old != new) {
871 set_cpld(ice, new);
872 /* changed */
873 return 1;
874 }
875 return 0;
876 }
877
qtet_get_spdif_master_type(struct snd_ice1712 * ice)878 static int qtet_get_spdif_master_type(struct snd_ice1712 *ice)
879 {
880 unsigned int val;
881 int result;
882 val = get_cpld(ice);
883 /* checking only rate/clock-related bits */
884 val &= (CPLD_CKS_MASK | CPLD_WORD_SEL | CPLD_SYNC_SEL);
885 if (!(val & CPLD_SYNC_SEL)) {
886 /* switched to internal clock, is not any external type */
887 result = -1;
888 } else {
889 switch (val) {
890 case (CPLD_EXT_SPDIF):
891 result = EXT_SPDIF_TYPE;
892 break;
893 case (CPLD_EXT_WORDCLOCK_1FS):
894 result = EXT_WORDCLOCK_1FS_TYPE;
895 break;
896 case (CPLD_EXT_WORDCLOCK_256FS):
897 result = EXT_WORDCLOCK_256FS_TYPE;
898 break;
899 default:
900 /* undefined combination of external clock setup */
901 snd_BUG();
902 result = 0;
903 }
904 }
905 return result;
906 }
907
908 /* Called when ak4113 detects change in the input SPDIF stream */
qtet_ak4113_change(struct ak4113 * ak4113,unsigned char c0,unsigned char c1)909 static void qtet_ak4113_change(struct ak4113 *ak4113, unsigned char c0,
910 unsigned char c1)
911 {
912 struct snd_ice1712 *ice = ak4113->change_callback_private;
913 int rate;
914 if ((qtet_get_spdif_master_type(ice) == EXT_SPDIF_TYPE) &&
915 c1) {
916 /* only for SPDIF master mode, rate was changed */
917 rate = snd_ak4113_external_rate(ak4113);
918 /* dev_dbg(ice->card->dev, "ak4113 - input rate changed to %d\n",
919 rate); */
920 qtet_akm_set_rate_val(ice->akm, rate);
921 }
922 }
923
924 /*
925 * If clock slaved to SPDIF-IN, setting runtime rate
926 * to the detected external rate
927 */
qtet_spdif_in_open(struct snd_ice1712 * ice,struct snd_pcm_substream * substream)928 static void qtet_spdif_in_open(struct snd_ice1712 *ice,
929 struct snd_pcm_substream *substream)
930 {
931 struct qtet_spec *spec = ice->spec;
932 struct snd_pcm_runtime *runtime = substream->runtime;
933 int rate;
934
935 if (qtet_get_spdif_master_type(ice) != EXT_SPDIF_TYPE)
936 /* not external SPDIF, no rate limitation */
937 return;
938 /* only external SPDIF can detect incoming sample rate */
939 rate = snd_ak4113_external_rate(spec->ak4113);
940 if (rate >= runtime->hw.rate_min && rate <= runtime->hw.rate_max) {
941 runtime->hw.rate_min = rate;
942 runtime->hw.rate_max = rate;
943 }
944 }
945
946 /*
947 * initialize the chip
948 */
qtet_init(struct snd_ice1712 * ice)949 static int qtet_init(struct snd_ice1712 *ice)
950 {
951 static const unsigned char ak4113_init_vals[] = {
952 /* AK4113_REG_PWRDN */ AK4113_RST | AK4113_PWN |
953 AK4113_OCKS0 | AK4113_OCKS1,
954 /* AK4113_REQ_FORMAT */ AK4113_DIF_I24I2S | AK4113_VTX |
955 AK4113_DEM_OFF | AK4113_DEAU,
956 /* AK4113_REG_IO0 */ AK4113_OPS2 | AK4113_TXE |
957 AK4113_XTL_24_576M,
958 /* AK4113_REG_IO1 */ AK4113_EFH_1024LRCLK | AK4113_IPS(0),
959 /* AK4113_REG_INT0_MASK */ 0,
960 /* AK4113_REG_INT1_MASK */ 0,
961 /* AK4113_REG_DATDTS */ 0,
962 };
963 int err;
964 struct qtet_spec *spec;
965 struct snd_akm4xxx *ak;
966 unsigned char val;
967
968 /* switching ice1724 to external clock - supplied by ext. circuits */
969 val = inb(ICEMT1724(ice, RATE));
970 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
971
972 spec = kzalloc_obj(*spec);
973 if (!spec)
974 return -ENOMEM;
975 /* qtet is clocked by Xilinx array */
976 ice->hw_rates = &qtet_rates_info;
977 ice->is_spdif_master = qtet_is_spdif_master;
978 ice->get_rate = qtet_get_rate;
979 ice->set_rate = qtet_set_rate;
980 ice->set_mclk = qtet_set_mclk;
981 ice->set_spdif_clock = qtet_set_spdif_clock;
982 ice->get_spdif_master_type = qtet_get_spdif_master_type;
983 ice->ext_clock_names = ext_clock_names;
984 ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
985 /* since Qtet can detect correct SPDIF-in rate, all streams can be
986 * limited to this specific rate */
987 ice->spdif.ops.open = ice->pro_open = qtet_spdif_in_open;
988 ice->spec = spec;
989
990 /* Mute Off */
991 /* SCR Initialize*/
992 /* keep codec power down first */
993 set_scr(ice, SCR_PHP);
994 udelay(1);
995 /* codec power up */
996 set_scr(ice, SCR_PHP | SCR_CODEC_PDN);
997
998 /* MCR Initialize */
999 set_mcr(ice, 0);
1000
1001 /* CPLD Initialize */
1002 set_cpld(ice, 0);
1003
1004
1005 ice->num_total_dacs = 2;
1006 ice->num_total_adcs = 2;
1007
1008 ice->akm = kzalloc_objs(struct snd_akm4xxx, 2);
1009 ak = ice->akm;
1010 if (!ak)
1011 return -ENOMEM;
1012 /* only one codec with two chips */
1013 ice->akm_codecs = 1;
1014 err = snd_ice1712_akm4xxx_init(ak, &akm_qtet_dac, NULL, ice);
1015 if (err < 0)
1016 return err;
1017 err = snd_ak4113_create(ice->card,
1018 qtet_ak4113_read,
1019 qtet_ak4113_write,
1020 ak4113_init_vals,
1021 ice, &spec->ak4113);
1022 if (err < 0)
1023 return err;
1024 /* callback for codecs rate setting */
1025 spec->ak4113->change_callback = qtet_ak4113_change;
1026 spec->ak4113->change_callback_private = ice;
1027 /* AK41143 in Quartet can detect external rate correctly
1028 * (i.e. check_flags = 0) */
1029 spec->ak4113->check_flags = 0;
1030
1031 proc_init(ice);
1032
1033 qtet_set_rate(ice, 44100);
1034 return 0;
1035 }
1036
1037 static const unsigned char qtet_eeprom[] = {
1038 [ICE_EEP2_SYSCONF] = 0x28, /* clock 256(24MHz), mpu401, 1xADC,
1039 1xDACs, SPDIF in */
1040 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
1041 [ICE_EEP2_I2S] = 0x78, /* 96k, 24bit, 192k */
1042 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, in, out-ext */
1043 [ICE_EEP2_GPIO_DIR] = 0x00, /* 0-7 inputs, switched to output
1044 only during output operations */
1045 [ICE_EEP2_GPIO_DIR1] = 0xff, /* 8-15 outputs */
1046 [ICE_EEP2_GPIO_DIR2] = 0x00,
1047 [ICE_EEP2_GPIO_MASK] = 0xff, /* changed only for OUT operations */
1048 [ICE_EEP2_GPIO_MASK1] = 0x00,
1049 [ICE_EEP2_GPIO_MASK2] = 0xff,
1050
1051 [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */
1052 [ICE_EEP2_GPIO_STATE1] = 0x7d, /* all 1, but GPIO_CPLD_RW
1053 and GPIO15 always zero */
1054 [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
1055 };
1056
1057 /* entry point */
1058 struct snd_ice1712_card_info snd_vt1724_qtet_cards[] = {
1059 {
1060 .subvendor = VT1724_SUBDEVICE_QTET,
1061 .name = "Infrasonic Quartet",
1062 .model = "quartet",
1063 .chip_init = qtet_init,
1064 .build_controls = qtet_add_controls,
1065 .eeprom_size = sizeof(qtet_eeprom),
1066 .eeprom_data = qtet_eeprom,
1067 },
1068 { } /* terminator */
1069 };
1070