1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Clause 45 PHY support 4 */ 5 #include <linux/ethtool.h> 6 #include <linux/export.h> 7 #include <linux/mdio.h> 8 #include <linux/mii.h> 9 #include <linux/phy.h> 10 #include <linux/ethtool_netlink.h> 11 12 #include "mdio-open-alliance.h" 13 #include "phylib-internal.h" 14 15 /** 16 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities 17 * @phydev: target phy_device struct 18 */ 19 static bool genphy_c45_baset1_able(struct phy_device *phydev) 20 { 21 int val; 22 23 if (phydev->pma_extable == -ENODATA) { 24 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 25 if (val < 0) 26 return false; 27 28 phydev->pma_extable = val; 29 } 30 31 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); 32 } 33 34 /** 35 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support 36 * @phydev: target phy_device struct 37 */ 38 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) 39 { 40 int stat1; 41 42 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); 43 if (stat1 < 0) 44 return false; 45 46 return !!(stat1 & MDIO_STAT1_LPOWERABLE); 47 } 48 49 /** 50 * genphy_c45_pma_resume - wakes up the PMA module 51 * @phydev: target phy_device struct 52 */ 53 int genphy_c45_pma_resume(struct phy_device *phydev) 54 { 55 if (!genphy_c45_pma_can_sleep(phydev)) 56 return -EOPNOTSUPP; 57 58 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 59 MDIO_CTRL1_LPOWER); 60 } 61 EXPORT_SYMBOL_GPL(genphy_c45_pma_resume); 62 63 /** 64 * genphy_c45_pma_suspend - suspends the PMA module 65 * @phydev: target phy_device struct 66 */ 67 int genphy_c45_pma_suspend(struct phy_device *phydev) 68 { 69 if (!genphy_c45_pma_can_sleep(phydev)) 70 return -EOPNOTSUPP; 71 72 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 73 MDIO_CTRL1_LPOWER); 74 } 75 EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend); 76 77 /** 78 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave 79 * role of BaseT1 devices. 80 * @phydev: target phy_device struct 81 */ 82 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev) 83 { 84 int ctl = 0; 85 86 switch (phydev->master_slave_set) { 87 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 88 case MASTER_SLAVE_CFG_MASTER_FORCE: 89 ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST; 90 break; 91 case MASTER_SLAVE_CFG_SLAVE_FORCE: 92 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 93 break; 94 case MASTER_SLAVE_CFG_UNKNOWN: 95 case MASTER_SLAVE_CFG_UNSUPPORTED: 96 return 0; 97 default: 98 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 99 return -EOPNOTSUPP; 100 } 101 102 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 103 MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl); 104 } 105 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave); 106 107 /** 108 * genphy_c45_pma_setup_forced - configures a forced speed 109 * @phydev: target phy_device struct 110 */ 111 int genphy_c45_pma_setup_forced(struct phy_device *phydev) 112 { 113 int bt1_ctrl, ctrl1, ctrl2, ret; 114 115 /* Half duplex is not supported */ 116 if (phydev->duplex != DUPLEX_FULL) 117 return -EINVAL; 118 119 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 120 if (ctrl1 < 0) 121 return ctrl1; 122 123 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); 124 if (ctrl2 < 0) 125 return ctrl2; 126 127 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; 128 /* 129 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 130 * in 802.3-2012 and 802.3-2015. 131 */ 132 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); 133 134 switch (phydev->speed) { 135 case SPEED_10: 136 if (genphy_c45_baset1_able(phydev)) 137 ctrl2 |= MDIO_PMA_CTRL2_BASET1; 138 else 139 ctrl2 |= MDIO_PMA_CTRL2_10BT; 140 break; 141 case SPEED_100: 142 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; 143 ctrl2 |= MDIO_PMA_CTRL2_100BTX; 144 break; 145 case SPEED_1000: 146 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; 147 /* Assume 1000base-T */ 148 ctrl2 |= MDIO_PMA_CTRL2_1000BT; 149 break; 150 case SPEED_2500: 151 ctrl1 |= MDIO_PMA_CTRL1_SPEED2_5G; 152 /* Assume 2.5Gbase-T */ 153 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; 154 break; 155 case SPEED_5000: 156 ctrl1 |= MDIO_PMA_CTRL1_SPEED5G; 157 /* Assume 5Gbase-T */ 158 ctrl2 |= MDIO_PMA_CTRL2_5GBT; 159 break; 160 case SPEED_10000: 161 ctrl1 |= MDIO_CTRL1_SPEED10G; 162 /* Assume 10Gbase-T */ 163 ctrl2 |= MDIO_PMA_CTRL2_10GBT; 164 break; 165 default: 166 return -EINVAL; 167 } 168 169 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); 170 if (ret < 0) 171 return ret; 172 173 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); 174 if (ret < 0) 175 return ret; 176 177 if (genphy_c45_baset1_able(phydev)) { 178 ret = genphy_c45_pma_baset1_setup_master_slave(phydev); 179 if (ret < 0) 180 return ret; 181 182 bt1_ctrl = 0; 183 if (phydev->speed == SPEED_1000) 184 bt1_ctrl = MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000; 185 186 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 187 MDIO_PMA_PMD_BT1_CTRL_STRAP, bt1_ctrl); 188 if (ret < 0) 189 return ret; 190 } 191 192 return genphy_c45_an_disable_aneg(phydev); 193 } 194 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 195 196 /* Sets master/slave preference and supported technologies. 197 * The preference is set in the BIT(4) of BASE-T1 AN 198 * advertisement register 7.515 and whether the status 199 * is forced or not, it is set in the BIT(12) of BASE-T1 200 * AN advertisement register 7.514. 201 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation 202 * advertisement register [31:16] if supported. 203 */ 204 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev) 205 { 206 u16 adv_l_mask, adv_l = 0; 207 u16 adv_m_mask, adv_m = 0; 208 int changed = 0; 209 int ret; 210 211 adv_l_mask = MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP | 212 MDIO_AN_T1_ADV_L_PAUSE_ASYM; 213 adv_m_mask = MDIO_AN_T1_ADV_M_1000BT1 | MDIO_AN_T1_ADV_M_100BT1 | 214 MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L; 215 216 switch (phydev->master_slave_set) { 217 case MASTER_SLAVE_CFG_MASTER_FORCE: 218 adv_m |= MDIO_AN_T1_ADV_M_MST; 219 fallthrough; 220 case MASTER_SLAVE_CFG_SLAVE_FORCE: 221 adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS; 222 break; 223 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 224 adv_m |= MDIO_AN_T1_ADV_M_MST; 225 fallthrough; 226 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 227 break; 228 case MASTER_SLAVE_CFG_UNKNOWN: 229 case MASTER_SLAVE_CFG_UNSUPPORTED: 230 /* if master/slave role is not specified, do not overwrite it */ 231 adv_l_mask &= ~MDIO_AN_T1_ADV_L_FORCE_MS; 232 adv_m_mask &= ~MDIO_AN_T1_ADV_M_MST; 233 break; 234 default: 235 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 236 return -EOPNOTSUPP; 237 } 238 239 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); 240 241 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, 242 adv_l_mask, adv_l); 243 if (ret < 0) 244 return ret; 245 if (ret > 0) 246 changed = 1; 247 248 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); 249 250 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, 251 adv_m_mask, adv_m); 252 if (ret < 0) 253 return ret; 254 if (ret > 0) 255 changed = 1; 256 257 return changed; 258 } 259 260 /** 261 * genphy_c45_an_config_aneg - configure advertisement registers 262 * @phydev: target phy_device struct 263 * 264 * Configure advertisement registers based on modes set in phydev->advertising 265 * 266 * Returns negative errno code on failure, 0 if advertisement didn't change, 267 * or 1 if advertised modes changed. 268 */ 269 int genphy_c45_an_config_aneg(struct phy_device *phydev) 270 { 271 int changed = 0, ret; 272 u32 adv; 273 274 linkmode_and(phydev->advertising, phydev->advertising, 275 phydev->supported); 276 277 ret = genphy_c45_an_config_eee_aneg(phydev); 278 if (ret < 0) 279 return ret; 280 else if (ret) 281 changed = true; 282 283 if (genphy_c45_baset1_able(phydev)) 284 return genphy_c45_baset1_an_config_aneg(phydev); 285 286 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 287 288 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 289 ADVERTISE_ALL | ADVERTISE_100BASE4 | 290 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 291 adv); 292 if (ret < 0) 293 return ret; 294 if (ret > 0) 295 changed = 1; 296 297 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 298 299 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 300 MDIO_AN_10GBT_CTRL_ADV10G | 301 MDIO_AN_10GBT_CTRL_ADV5G | 302 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 303 if (ret < 0) 304 return ret; 305 if (ret > 0) 306 changed = 1; 307 308 return changed; 309 } 310 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 311 312 /** 313 * genphy_c45_an_disable_aneg - disable auto-negotiation 314 * @phydev: target phy_device struct 315 * 316 * Disable auto-negotiation in the Clause 45 PHY. The link parameters 317 * are controlled through the PMA/PMD MMD registers. 318 * 319 * Returns zero on success, negative errno code on failure. 320 */ 321 int genphy_c45_an_disable_aneg(struct phy_device *phydev) 322 { 323 u16 reg = MDIO_CTRL1; 324 325 if (genphy_c45_baset1_able(phydev)) 326 reg = MDIO_AN_T1_CTRL; 327 328 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, 329 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 330 } 331 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 332 333 /** 334 * genphy_c45_restart_aneg - Enable and restart auto-negotiation 335 * @phydev: target phy_device struct 336 * 337 * This assumes that the auto-negotiation MMD is present. 338 * 339 * Enable and restart auto-negotiation. 340 */ 341 int genphy_c45_restart_aneg(struct phy_device *phydev) 342 { 343 u16 reg = MDIO_CTRL1; 344 345 if (genphy_c45_baset1_able(phydev)) 346 reg = MDIO_AN_T1_CTRL; 347 348 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, 349 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 350 } 351 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 352 353 /** 354 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation 355 * @phydev: target phy_device struct 356 * @restart: whether aneg restart is requested 357 * 358 * This assumes that the auto-negotiation MMD is present. 359 * 360 * Check, and restart auto-negotiation if needed. 361 */ 362 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) 363 { 364 u16 reg = MDIO_CTRL1; 365 int ret; 366 367 if (genphy_c45_baset1_able(phydev)) 368 reg = MDIO_AN_T1_CTRL; 369 370 if (!restart) { 371 /* Configure and restart aneg if it wasn't set before */ 372 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 373 if (ret < 0) 374 return ret; 375 376 if (!(ret & MDIO_AN_CTRL1_ENABLE)) 377 restart = true; 378 } 379 380 if (restart) 381 return genphy_c45_restart_aneg(phydev); 382 383 return 0; 384 } 385 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg); 386 387 /** 388 * genphy_c45_aneg_done - return auto-negotiation complete status 389 * @phydev: target phy_device struct 390 * 391 * This assumes that the auto-negotiation MMD is present. 392 * 393 * Reads the status register from the auto-negotiation MMD, returning: 394 * - positive if auto-negotiation is complete 395 * - negative errno code on error 396 * - zero otherwise 397 */ 398 int genphy_c45_aneg_done(struct phy_device *phydev) 399 { 400 int reg = MDIO_STAT1; 401 int val; 402 403 if (genphy_c45_baset1_able(phydev)) 404 reg = MDIO_AN_T1_STAT; 405 406 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 407 408 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; 409 } 410 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); 411 412 /** 413 * genphy_c45_read_link - read the overall link status from the MMDs 414 * @phydev: target phy_device struct 415 * 416 * Read the link status from the specified MMDs, and if they all indicate 417 * that the link is up, set phydev->link to 1. If an error is encountered, 418 * a negative errno will be returned, otherwise zero. 419 */ 420 int genphy_c45_read_link(struct phy_device *phydev) 421 { 422 u32 mmd_mask = MDIO_DEVS_PMAPMD; 423 int val, devad; 424 bool link = true; 425 426 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 427 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 428 if (val < 0) 429 return val; 430 431 /* Autoneg is being started, therefore disregard current 432 * link status and report link as down. 433 */ 434 if (val & MDIO_AN_CTRL1_RESTART) { 435 phydev->link = 0; 436 return 0; 437 } 438 } 439 440 while (mmd_mask && link) { 441 devad = __ffs(mmd_mask); 442 mmd_mask &= ~BIT(devad); 443 444 /* The link state is latched low so that momentary link 445 * drops can be detected. Do not double-read the status 446 * in polling mode to detect such short link drops except 447 * the link was already down. 448 */ 449 if (!phy_polling_mode(phydev) || !phydev->link) { 450 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 451 if (val < 0) 452 return val; 453 else if (val & MDIO_STAT1_LSTATUS) 454 continue; 455 } 456 457 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 458 if (val < 0) 459 return val; 460 461 if (!(val & MDIO_STAT1_LSTATUS)) 462 link = false; 463 } 464 465 phydev->link = link; 466 467 return 0; 468 } 469 EXPORT_SYMBOL_GPL(genphy_c45_read_link); 470 471 /* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check 472 * if autoneg is complete. If so read the BASE-T1 Autonegotiation 473 * Advertisement registers filling in the link partner advertisement, 474 * pause and asym_pause members in phydev. 475 */ 476 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev) 477 { 478 int val; 479 480 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 481 if (val < 0) 482 return val; 483 484 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 485 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); 486 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); 487 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); 488 489 phydev->pause = false; 490 phydev->asym_pause = false; 491 492 return 0; 493 } 494 495 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); 496 497 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L); 498 if (val < 0) 499 return val; 500 501 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); 502 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP; 503 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM; 504 505 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M); 506 if (val < 0) 507 return val; 508 509 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); 510 511 return 0; 512 } 513 514 /** 515 * genphy_c45_read_lpa - read the link partner advertisement and pause 516 * @phydev: target phy_device struct 517 * 518 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers, 519 * filling in the link partner advertisement, pause and asym_pause members 520 * in @phydev. This assumes that the auto-negotiation MMD is present, and 521 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected 522 * to fill in the remainder of the link partner advert from vendor registers. 523 */ 524 int genphy_c45_read_lpa(struct phy_device *phydev) 525 { 526 int val; 527 528 if (genphy_c45_baset1_able(phydev)) 529 return genphy_c45_baset1_read_lpa(phydev); 530 531 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 532 if (val < 0) 533 return val; 534 535 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 536 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 537 phydev->lp_advertising); 538 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 539 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); 540 phydev->pause = false; 541 phydev->asym_pause = false; 542 543 return 0; 544 } 545 546 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 547 val & MDIO_AN_STAT1_LPABLE); 548 549 /* Read the link partner's base page advertisement */ 550 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); 551 if (val < 0) 552 return val; 553 554 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); 555 phydev->pause = val & LPA_PAUSE_CAP; 556 phydev->asym_pause = val & LPA_PAUSE_ASYM; 557 558 /* Read the link partner's 10G advertisement */ 559 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 560 if (val < 0) 561 return val; 562 563 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); 564 565 return 0; 566 } 567 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa); 568 569 /** 570 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave 571 * configuration 572 * @phydev: target phy_device struct 573 */ 574 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev) 575 { 576 int val; 577 578 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 579 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 580 581 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL); 582 if (val < 0) 583 return val; 584 585 if (val & MDIO_PMA_PMD_BT1_CTRL_CFG_MST) { 586 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 587 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 588 } else { 589 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 590 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 591 } 592 593 return 0; 594 } 595 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_master_slave); 596 597 /** 598 * genphy_c45_read_pma - read link speed etc from PMA 599 * @phydev: target phy_device struct 600 */ 601 int genphy_c45_read_pma(struct phy_device *phydev) 602 { 603 int val; 604 605 linkmode_zero(phydev->lp_advertising); 606 607 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 608 if (val < 0) 609 return val; 610 611 switch (val & MDIO_CTRL1_SPEEDSEL) { 612 case 0: 613 phydev->speed = SPEED_10; 614 break; 615 case MDIO_PMA_CTRL1_SPEED100: 616 phydev->speed = SPEED_100; 617 break; 618 case MDIO_PMA_CTRL1_SPEED1000: 619 phydev->speed = SPEED_1000; 620 break; 621 case MDIO_PMA_CTRL1_SPEED2_5G: 622 phydev->speed = SPEED_2500; 623 break; 624 case MDIO_PMA_CTRL1_SPEED5G: 625 phydev->speed = SPEED_5000; 626 break; 627 case MDIO_CTRL1_SPEED10G: 628 phydev->speed = SPEED_10000; 629 break; 630 default: 631 phydev->speed = SPEED_UNKNOWN; 632 break; 633 } 634 635 phydev->duplex = DUPLEX_FULL; 636 637 if (genphy_c45_baset1_able(phydev)) { 638 val = genphy_c45_pma_baset1_read_master_slave(phydev); 639 if (val < 0) 640 return val; 641 } 642 643 return 0; 644 } 645 EXPORT_SYMBOL_GPL(genphy_c45_read_pma); 646 647 /** 648 * genphy_c45_read_mdix - read mdix status from PMA 649 * @phydev: target phy_device struct 650 */ 651 int genphy_c45_read_mdix(struct phy_device *phydev) 652 { 653 int val; 654 655 if (phydev->speed == SPEED_10000) { 656 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 657 MDIO_PMA_10GBT_SWAPPOL); 658 if (val < 0) 659 return val; 660 661 switch (val) { 662 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: 663 phydev->mdix = ETH_TP_MDI; 664 break; 665 666 case 0: 667 phydev->mdix = ETH_TP_MDI_X; 668 break; 669 670 default: 671 phydev->mdix = ETH_TP_MDI_INVALID; 672 break; 673 } 674 } 675 676 return 0; 677 } 678 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); 679 680 /** 681 * genphy_c45_write_eee_adv - write advertised EEE link modes 682 * @phydev: target phy_device struct 683 * @adv: the linkmode advertisement settings 684 */ 685 static int genphy_c45_write_eee_adv(struct phy_device *phydev, 686 unsigned long *adv) 687 { 688 int val, changed = 0; 689 690 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 691 val = linkmode_to_mii_eee_cap1_t(adv); 692 693 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 694 * (Register 7.60) 695 */ 696 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 697 MDIO_AN_EEE_ADV, 698 MDIO_EEE_100TX | MDIO_EEE_1000T | 699 MDIO_EEE_10GT | MDIO_EEE_1000KX | 700 MDIO_EEE_10GKX4 | MDIO_EEE_10GKR, 701 val); 702 if (val < 0) 703 return val; 704 if (val > 0) 705 changed = 1; 706 } 707 708 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 709 val = linkmode_to_mii_eee_cap2_t(adv); 710 711 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 712 * (Register 7.62) 713 */ 714 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 715 MDIO_AN_EEE_ADV2, 716 MDIO_EEE_2_5GT | MDIO_EEE_5GT, 717 val); 718 if (val < 0) 719 return val; 720 if (val > 0) 721 changed = 1; 722 } 723 724 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 725 phydev->supported_eee)) { 726 val = linkmode_adv_to_mii_10base_t1_t(adv); 727 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register 728 * (Register 7.526) 729 */ 730 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, 731 MDIO_AN_10BT1_AN_CTRL, 732 MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L, 733 val); 734 if (val < 0) 735 return val; 736 if (val > 0) 737 changed = 1; 738 } 739 740 return changed; 741 } 742 743 /** 744 * genphy_c45_read_eee_adv - read advertised EEE link modes 745 * @phydev: target phy_device struct 746 * @adv: the linkmode advertisement status 747 */ 748 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv) 749 { 750 int val; 751 752 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 753 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 754 * (Register 7.60) 755 */ 756 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 757 if (val < 0) 758 return val; 759 760 mii_eee_cap1_mod_linkmode_t(adv, val); 761 } 762 763 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 764 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 765 * (Register 7.62) 766 */ 767 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2); 768 if (val < 0) 769 return val; 770 771 mii_eee_cap2_mod_linkmode_adv_t(adv, val); 772 } 773 774 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 775 phydev->supported_eee)) { 776 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register 777 * (Register 7.526) 778 */ 779 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL); 780 if (val < 0) 781 return val; 782 783 mii_10base_t1_adv_mod_linkmode_t(adv, val); 784 } 785 786 return 0; 787 } 788 789 /** 790 * genphy_c45_read_eee_lpa - read advertised LP EEE link modes 791 * @phydev: target phy_device struct 792 * @lpa: the linkmode LP advertisement status 793 */ 794 static int genphy_c45_read_eee_lpa(struct phy_device *phydev, 795 unsigned long *lpa) 796 { 797 int val; 798 799 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { 800 /* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1 801 * (Register 7.61) 802 */ 803 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 804 if (val < 0) 805 return val; 806 807 mii_eee_cap1_mod_linkmode_t(lpa, val); 808 } 809 810 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { 811 /* IEEE 802.3-2022 45.2.7.17 EEE link partner ability 2 812 * (Register 7.63) 813 */ 814 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2); 815 if (val < 0) 816 return val; 817 818 mii_eee_cap2_mod_linkmode_adv_t(lpa, val); 819 } 820 821 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 822 phydev->supported_eee)) { 823 /* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register 824 * (Register 7.527) 825 */ 826 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT); 827 if (val < 0) 828 return val; 829 830 mii_10base_t1_adv_mod_linkmode_t(lpa, val); 831 } 832 833 return 0; 834 } 835 836 /** 837 * genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20 838 * @phydev: target phy_device struct 839 */ 840 static int genphy_c45_read_eee_cap1(struct phy_device *phydev) 841 { 842 int val; 843 844 /* IEEE 802.3-2018 45.2.3.10 EEE control and capability 1 845 * (Register 3.20) 846 */ 847 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 848 if (val < 0) 849 return val; 850 851 /* The 802.3 2018 standard says the top 2 bits are reserved and should 852 * read as 0. Also, it seems unlikely anybody will build a PHY which 853 * supports 100GBASE-R deep sleep all the way down to 100BASE-TX EEE. 854 * If MDIO_PCS_EEE_ABLE is 0xffff assume EEE is not supported. 855 */ 856 if (val == 0xffff) 857 return 0; 858 859 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val); 860 861 /* Some buggy devices indicate EEE link modes in MDIO_PCS_EEE_ABLE 862 * which they don't support as indicated by BMSR, ESTATUS etc. 863 */ 864 linkmode_and(phydev->supported_eee, phydev->supported_eee, 865 phydev->supported); 866 867 return 0; 868 } 869 870 /** 871 * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21 872 * @phydev: target phy_device struct 873 */ 874 static int genphy_c45_read_eee_cap2(struct phy_device *phydev) 875 { 876 int val; 877 878 /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2 879 * (Register 3.21) 880 */ 881 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2); 882 if (val < 0) 883 return val; 884 885 /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */ 886 if (val == 0xffff) 887 return 0; 888 889 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); 890 891 return 0; 892 } 893 894 /** 895 * genphy_c45_read_eee_abilities - read supported EEE link modes 896 * @phydev: target phy_device struct 897 */ 898 int genphy_c45_read_eee_abilities(struct phy_device *phydev) 899 { 900 int val; 901 902 /* There is not indicator whether optional register 903 * "EEE control and capability 1" (3.20) is supported. Read it only 904 * on devices with appropriate linkmodes. 905 */ 906 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) { 907 val = genphy_c45_read_eee_cap1(phydev); 908 if (val) 909 return val; 910 } 911 912 /* Same for cap2 (3.21) */ 913 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { 914 val = genphy_c45_read_eee_cap2(phydev); 915 if (val) 916 return val; 917 } 918 919 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 920 phydev->supported)) { 921 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register 922 * (Register 1.2295) 923 */ 924 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT); 925 if (val < 0) 926 return val; 927 928 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 929 phydev->supported_eee, 930 val & MDIO_PMA_10T1L_STAT_EEE); 931 } 932 933 return 0; 934 } 935 EXPORT_SYMBOL_GPL(genphy_c45_read_eee_abilities); 936 937 /** 938 * genphy_c45_an_config_eee_aneg - configure EEE advertisement 939 * @phydev: target phy_device struct 940 */ 941 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev) 942 { 943 if (!phydev->eee_cfg.eee_enabled) { 944 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {}; 945 946 return genphy_c45_write_eee_adv(phydev, adv); 947 } 948 949 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee); 950 } 951 EXPORT_SYMBOL_GPL(genphy_c45_an_config_eee_aneg); 952 953 /** 954 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA 955 * @phydev: target phy_device struct 956 * 957 * Read the supported link modes from the extended BASE-T1 ability register 958 */ 959 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev) 960 { 961 int val; 962 963 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1); 964 if (val < 0) 965 return val; 966 967 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 968 phydev->supported, 969 val & MDIO_PMA_PMD_BT1_B10L_ABLE); 970 971 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 972 phydev->supported, 973 val & MDIO_PMA_PMD_BT1_B100_ABLE); 974 975 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT, 976 phydev->supported, 977 val & MDIO_PMA_PMD_BT1_B1000_ABLE); 978 979 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 980 if (val < 0) 981 return val; 982 983 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 984 phydev->supported, 985 val & MDIO_AN_STAT1_ABLE); 986 987 return 0; 988 } 989 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_abilities); 990 991 /** 992 * genphy_c45_pma_read_ext_abilities - read supported link modes from PMA 993 * @phydev: target phy_device struct 994 * 995 * Read the supported link modes from the PMA/PMD extended ability register 996 * (Register 1.11). 997 */ 998 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev) 999 { 1000 int val; 1001 1002 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 1003 if (val < 0) 1004 return val; 1005 1006 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 1007 phydev->supported, 1008 val & MDIO_PMA_EXTABLE_10GBLRM); 1009 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1010 phydev->supported, 1011 val & MDIO_PMA_EXTABLE_10GBT); 1012 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 1013 phydev->supported, 1014 val & MDIO_PMA_EXTABLE_10GBKX4); 1015 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1016 phydev->supported, 1017 val & MDIO_PMA_EXTABLE_10GBKR); 1018 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1019 phydev->supported, 1020 val & MDIO_PMA_EXTABLE_1000BT); 1021 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1022 phydev->supported, 1023 val & MDIO_PMA_EXTABLE_1000BKX); 1024 1025 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1026 phydev->supported, 1027 val & MDIO_PMA_EXTABLE_100BTX); 1028 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1029 phydev->supported, 1030 val & MDIO_PMA_EXTABLE_100BTX); 1031 1032 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 1033 phydev->supported, 1034 val & MDIO_PMA_EXTABLE_10BT); 1035 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 1036 phydev->supported, 1037 val & MDIO_PMA_EXTABLE_10BT); 1038 1039 if (val & MDIO_PMA_EXTABLE_NBT) { 1040 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 1041 MDIO_PMA_NG_EXTABLE); 1042 if (val < 0) 1043 return val; 1044 1045 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1046 phydev->supported, 1047 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 1048 1049 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1050 phydev->supported, 1051 val & MDIO_PMA_NG_EXTABLE_5GBT); 1052 } 1053 1054 if (val & MDIO_PMA_EXTABLE_BT1) { 1055 val = genphy_c45_pma_baset1_read_abilities(phydev); 1056 if (val < 0) 1057 return val; 1058 } 1059 1060 return 0; 1061 } 1062 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_ext_abilities); 1063 1064 /** 1065 * genphy_c45_pma_read_abilities - read supported link modes from PMA 1066 * @phydev: target phy_device struct 1067 * 1068 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit 1069 * 1.8.9 is set, the list of supported modes is build using the values in the 1070 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related 1071 * modes. If bit 1.11.14 is set, then the list is also extended with the modes 1072 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and 1073 * 5GBASET are supported. 1074 */ 1075 int genphy_c45_pma_read_abilities(struct phy_device *phydev) 1076 { 1077 int val; 1078 1079 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 1080 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 1081 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 1082 if (val < 0) 1083 return val; 1084 1085 if (val & MDIO_AN_STAT1_ABLE) 1086 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1087 phydev->supported); 1088 } 1089 1090 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 1091 if (val < 0) 1092 return val; 1093 1094 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1095 phydev->supported, 1096 val & MDIO_PMA_STAT2_10GBSR); 1097 1098 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1099 phydev->supported, 1100 val & MDIO_PMA_STAT2_10GBLR); 1101 1102 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 1103 phydev->supported, 1104 val & MDIO_PMA_STAT2_10GBER); 1105 1106 if (val & MDIO_PMA_STAT2_EXTABLE) { 1107 val = genphy_c45_pma_read_ext_abilities(phydev); 1108 if (val < 0) 1109 return val; 1110 } 1111 1112 /* This is optional functionality. If not supported, we may get an error 1113 * which should be ignored. 1114 */ 1115 genphy_c45_read_eee_abilities(phydev); 1116 1117 return 0; 1118 } 1119 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities); 1120 1121 /* Read master/slave preference from registers. 1122 * The preference is read from the BIT(4) of BASE-T1 AN 1123 * advertisement register 7.515 and whether the preference 1124 * is forced or not, it is read from BASE-T1 AN advertisement 1125 * register 7.514. 1126 */ 1127 int genphy_c45_baset1_read_status(struct phy_device *phydev) 1128 { 1129 int ret; 1130 int cfg; 1131 1132 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1133 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1134 1135 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L); 1136 if (ret < 0) 1137 return ret; 1138 1139 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M); 1140 if (cfg < 0) 1141 return cfg; 1142 1143 if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) { 1144 if (cfg & MDIO_AN_T1_ADV_M_MST) 1145 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1146 else 1147 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1148 } else { 1149 if (cfg & MDIO_AN_T1_ADV_M_MST) 1150 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; 1151 else 1152 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; 1153 } 1154 1155 return 0; 1156 } 1157 EXPORT_SYMBOL_GPL(genphy_c45_baset1_read_status); 1158 1159 /** 1160 * genphy_c45_read_status - read PHY status 1161 * @phydev: target phy_device struct 1162 * 1163 * Reads status from PHY and sets phy_device members accordingly. 1164 */ 1165 int genphy_c45_read_status(struct phy_device *phydev) 1166 { 1167 int ret; 1168 1169 ret = genphy_c45_read_link(phydev); 1170 if (ret) 1171 return ret; 1172 1173 phydev->speed = SPEED_UNKNOWN; 1174 phydev->duplex = DUPLEX_UNKNOWN; 1175 phydev->pause = false; 1176 phydev->asym_pause = false; 1177 1178 if (phydev->autoneg == AUTONEG_ENABLE) { 1179 ret = genphy_c45_read_lpa(phydev); 1180 if (ret) 1181 return ret; 1182 1183 if (genphy_c45_baset1_able(phydev)) { 1184 ret = genphy_c45_baset1_read_status(phydev); 1185 if (ret < 0) 1186 return ret; 1187 } 1188 1189 phy_resolve_aneg_linkmode(phydev); 1190 } else { 1191 ret = genphy_c45_read_pma(phydev); 1192 } 1193 1194 return ret; 1195 } 1196 EXPORT_SYMBOL_GPL(genphy_c45_read_status); 1197 1198 /** 1199 * genphy_c45_config_aneg - restart auto-negotiation or forced setup 1200 * @phydev: target phy_device struct 1201 * 1202 * Description: If auto-negotiation is enabled, we configure the 1203 * advertising, and then restart auto-negotiation. If it is not 1204 * enabled, then we force a configuration. 1205 */ 1206 int genphy_c45_config_aneg(struct phy_device *phydev) 1207 { 1208 bool changed = false; 1209 int ret; 1210 1211 if (phydev->autoneg == AUTONEG_DISABLE) 1212 return genphy_c45_pma_setup_forced(phydev); 1213 1214 ret = genphy_c45_an_config_aneg(phydev); 1215 if (ret < 0) 1216 return ret; 1217 if (ret > 0) 1218 changed = true; 1219 1220 return genphy_c45_check_and_restart_aneg(phydev, changed); 1221 } 1222 EXPORT_SYMBOL_GPL(genphy_c45_config_aneg); 1223 1224 /* The gen10g_* functions are the old Clause 45 stub */ 1225 1226 int gen10g_config_aneg(struct phy_device *phydev) 1227 { 1228 return 0; 1229 } 1230 EXPORT_SYMBOL_GPL(gen10g_config_aneg); 1231 1232 int genphy_c45_loopback(struct phy_device *phydev, bool enable, int speed) 1233 { 1234 if (enable && speed) 1235 return -EOPNOTSUPP; 1236 1237 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, 1238 MDIO_PCS_CTRL1_LOOPBACK, 1239 enable ? MDIO_PCS_CTRL1_LOOPBACK : 0); 1240 } 1241 EXPORT_SYMBOL_GPL(genphy_c45_loopback); 1242 1243 /** 1244 * genphy_c45_fast_retrain - configure fast retrain registers 1245 * @phydev: target phy_device struct 1246 * @enable: enable fast retrain or not 1247 * 1248 * Description: If fast-retrain is enabled, we configure PHY as 1249 * advertising fast retrain capable and THP Bypass Request, then 1250 * enable fast retrain. If it is not enabled, we configure fast 1251 * retrain disabled. 1252 */ 1253 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) 1254 { 1255 int ret; 1256 1257 if (!enable) 1258 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 1259 MDIO_PMA_10GBR_FSRT_ENABLE); 1260 1261 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { 1262 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1263 MDIO_AN_10GBT_CTRL_ADVFSRT2_5G); 1264 if (ret) 1265 return ret; 1266 1267 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, 1268 MDIO_AN_THP_BP2_5GT); 1269 if (ret) 1270 return ret; 1271 } 1272 1273 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 1274 MDIO_PMA_10GBR_FSRT_ENABLE); 1275 } 1276 EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain); 1277 1278 /** 1279 * genphy_c45_plca_get_cfg - get PLCA configuration from standard registers 1280 * @phydev: target phy_device struct 1281 * @plca_cfg: output structure to store the PLCA configuration 1282 * 1283 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1284 * Management Registers specifications, this function can be used to retrieve 1285 * the current PLCA configuration from the standard registers in MMD 31. 1286 */ 1287 int genphy_c45_plca_get_cfg(struct phy_device *phydev, 1288 struct phy_plca_cfg *plca_cfg) 1289 { 1290 int ret; 1291 1292 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); 1293 if (ret < 0) 1294 return ret; 1295 1296 if ((ret & MDIO_OATC14_PLCA_IDM) != OATC14_IDM) 1297 return -ENODEV; 1298 1299 plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM; 1300 1301 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); 1302 if (ret < 0) 1303 return ret; 1304 1305 plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN); 1306 1307 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); 1308 if (ret < 0) 1309 return ret; 1310 1311 plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8; 1312 plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID); 1313 1314 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); 1315 if (ret < 0) 1316 return ret; 1317 1318 plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT; 1319 1320 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); 1321 if (ret < 0) 1322 return ret; 1323 1324 plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8; 1325 plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR); 1326 1327 return 0; 1328 } 1329 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_cfg); 1330 1331 /** 1332 * genphy_c45_plca_set_cfg - set PLCA configuration using standard registers 1333 * @phydev: target phy_device struct 1334 * @plca_cfg: structure containing the PLCA configuration. Fields set to -1 are 1335 * not to be changed. 1336 * 1337 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1338 * Management Registers specifications, this function can be used to modify 1339 * the PLCA configuration using the standard registers in MMD 31. 1340 */ 1341 int genphy_c45_plca_set_cfg(struct phy_device *phydev, 1342 const struct phy_plca_cfg *plca_cfg) 1343 { 1344 u16 val = 0; 1345 int ret; 1346 1347 // PLCA IDVER is read-only 1348 if (plca_cfg->version >= 0) 1349 return -EINVAL; 1350 1351 // first of all, disable PLCA if required 1352 if (plca_cfg->enabled == 0) { 1353 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 1354 MDIO_OATC14_PLCA_CTRL0, 1355 MDIO_OATC14_PLCA_EN); 1356 1357 if (ret < 0) 1358 return ret; 1359 } 1360 1361 // check if we need to set the PLCA node count, node ID, or both 1362 if (plca_cfg->node_cnt >= 0 || plca_cfg->node_id >= 0) { 1363 /* if one between node count and node ID is -not- to be 1364 * changed, read the register to later perform merge/purge of 1365 * the configuration as appropriate 1366 */ 1367 if (plca_cfg->node_cnt < 0 || plca_cfg->node_id < 0) { 1368 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1369 MDIO_OATC14_PLCA_CTRL1); 1370 1371 if (ret < 0) 1372 return ret; 1373 1374 val = ret; 1375 } 1376 1377 if (plca_cfg->node_cnt >= 0) 1378 val = (val & ~MDIO_OATC14_PLCA_NCNT) | 1379 (plca_cfg->node_cnt << 8); 1380 1381 if (plca_cfg->node_id >= 0) 1382 val = (val & ~MDIO_OATC14_PLCA_ID) | 1383 (plca_cfg->node_id); 1384 1385 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1386 MDIO_OATC14_PLCA_CTRL1, val); 1387 1388 if (ret < 0) 1389 return ret; 1390 } 1391 1392 if (plca_cfg->to_tmr >= 0) { 1393 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1394 MDIO_OATC14_PLCA_TOTMR, 1395 plca_cfg->to_tmr); 1396 1397 if (ret < 0) 1398 return ret; 1399 } 1400 1401 // check if we need to set the PLCA burst count, burst timer, or both 1402 if (plca_cfg->burst_cnt >= 0 || plca_cfg->burst_tmr >= 0) { 1403 /* if one between burst count and burst timer is -not- to be 1404 * changed, read the register to later perform merge/purge of 1405 * the configuration as appropriate 1406 */ 1407 if (plca_cfg->burst_cnt < 0 || plca_cfg->burst_tmr < 0) { 1408 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1409 MDIO_OATC14_PLCA_BURST); 1410 1411 if (ret < 0) 1412 return ret; 1413 1414 val = ret; 1415 } 1416 1417 if (plca_cfg->burst_cnt >= 0) 1418 val = (val & ~MDIO_OATC14_PLCA_MAXBC) | 1419 (plca_cfg->burst_cnt << 8); 1420 1421 if (plca_cfg->burst_tmr >= 0) 1422 val = (val & ~MDIO_OATC14_PLCA_BTMR) | 1423 (plca_cfg->burst_tmr); 1424 1425 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1426 MDIO_OATC14_PLCA_BURST, val); 1427 1428 if (ret < 0) 1429 return ret; 1430 } 1431 1432 // if we need to enable PLCA, do it at the end 1433 if (plca_cfg->enabled > 0) { 1434 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 1435 MDIO_OATC14_PLCA_CTRL0, 1436 MDIO_OATC14_PLCA_EN); 1437 1438 if (ret < 0) 1439 return ret; 1440 } 1441 1442 return 0; 1443 } 1444 EXPORT_SYMBOL_GPL(genphy_c45_plca_set_cfg); 1445 1446 /** 1447 * genphy_c45_plca_get_status - get PLCA status from standard registers 1448 * @phydev: target phy_device struct 1449 * @plca_st: output structure to store the PLCA status 1450 * 1451 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA 1452 * Management Registers specifications, this function can be used to retrieve 1453 * the current PLCA status information from the standard registers in MMD 31. 1454 */ 1455 int genphy_c45_plca_get_status(struct phy_device *phydev, 1456 struct phy_plca_status *plca_st) 1457 { 1458 int ret; 1459 1460 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS); 1461 if (ret < 0) 1462 return ret; 1463 1464 plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST); 1465 return 0; 1466 } 1467 EXPORT_SYMBOL_GPL(genphy_c45_plca_get_status); 1468 1469 /** 1470 * genphy_c45_eee_is_active - get EEE status 1471 * @phydev: target phy_device struct 1472 * @lp: variable to store LP advertised linkmodes 1473 * 1474 * Description: this function will read link partner PHY advertisement 1475 * and compare it to local advertisement to return current EEE state. 1476 */ 1477 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *lp) 1478 { 1479 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_lp) = {}; 1480 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 1481 int ret; 1482 1483 if (!phydev->eee_cfg.eee_enabled) 1484 return 0; 1485 1486 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp); 1487 if (ret) 1488 return ret; 1489 1490 if (lp) 1491 linkmode_copy(lp, tmp_lp); 1492 1493 linkmode_and(common, phydev->advertising_eee, tmp_lp); 1494 if (linkmode_empty(common)) 1495 return 0; 1496 1497 return phy_check_valid(phydev->speed, phydev->duplex, common); 1498 } 1499 EXPORT_SYMBOL(genphy_c45_eee_is_active); 1500 1501 /** 1502 * genphy_c45_ethtool_get_eee - get EEE supported and status 1503 * @phydev: target phy_device struct 1504 * @data: ethtool_keee data 1505 * 1506 * Description: it reports the Supported/Advertisement/LP Advertisement 1507 * capabilities. 1508 */ 1509 int genphy_c45_ethtool_get_eee(struct phy_device *phydev, 1510 struct ethtool_keee *data) 1511 { 1512 int ret; 1513 1514 ret = genphy_c45_eee_is_active(phydev, data->lp_advertised); 1515 if (ret < 0) 1516 return ret; 1517 1518 data->eee_active = phydev->eee_active; 1519 linkmode_andnot(data->supported, phydev->supported_eee, 1520 phydev->eee_disabled_modes); 1521 linkmode_copy(data->advertised, phydev->advertising_eee); 1522 return 0; 1523 } 1524 EXPORT_SYMBOL(genphy_c45_ethtool_get_eee); 1525 1526 /** 1527 * genphy_c45_ethtool_set_eee - set EEE supported and status 1528 * @phydev: target phy_device struct 1529 * @data: ethtool_keee data 1530 * 1531 * Description: sets the Supported/Advertisement/LP Advertisement 1532 * capabilities. If eee_enabled is false, no links modes are 1533 * advertised, but the previously advertised link modes are 1534 * retained. This allows EEE to be enabled/disabled in a 1535 * non-destructive way. 1536 * Returns either error code, 0 if there was no change, or positive 1537 * value if there was a change which triggered auto-neg. 1538 */ 1539 int genphy_c45_ethtool_set_eee(struct phy_device *phydev, 1540 struct ethtool_keee *data) 1541 { 1542 int ret; 1543 1544 if (data->eee_enabled) { 1545 unsigned long *adv = data->advertised; 1546 1547 if (!linkmode_empty(adv)) { 1548 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); 1549 1550 if (linkmode_andnot(tmp, adv, phydev->supported_eee)) { 1551 phydev_warn(phydev, "At least some EEE link modes are not supported.\n"); 1552 return -EINVAL; 1553 } 1554 1555 linkmode_andnot(phydev->advertising_eee, adv, 1556 phydev->eee_disabled_modes); 1557 } else if (linkmode_empty(phydev->advertising_eee)) { 1558 phy_advertise_eee_all(phydev); 1559 } 1560 } 1561 1562 ret = genphy_c45_an_config_eee_aneg(phydev); 1563 if (ret > 0) { 1564 ret = phy_restart_aneg(phydev); 1565 if (ret < 0) 1566 return ret; 1567 1568 /* explicitly return 1, otherwise (ret > 0) value will be 1569 * overwritten by phy_restart_aneg(). 1570 */ 1571 return 1; 1572 } 1573 1574 return ret; 1575 } 1576 EXPORT_SYMBOL(genphy_c45_ethtool_set_eee); 1577 1578 /** 1579 * oatc14_cable_test_get_result_code - Convert hardware cable test status to 1580 * ethtool result code. 1581 * @status: The hardware-reported cable test status 1582 * 1583 * This helper function maps the OATC14 HDD cable test status to the 1584 * corresponding ethtool cable test result code. It provides a translation 1585 * between the device-specific status values and the standardized ethtool 1586 * result codes. 1587 * 1588 * Return: 1589 * * ETHTOOL_A_CABLE_RESULT_CODE_OK - Cable is OK 1590 * * ETHTOOL_A_CABLE_RESULT_CODE_OPEN - Open circuit detected 1591 * * ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT - Short circuit detected 1592 * * ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC - Status not detectable or invalid 1593 */ 1594 static int oatc14_cable_test_get_result_code(enum oatc14_hdd_status status) 1595 { 1596 switch (status) { 1597 case OATC14_HDD_STATUS_CABLE_OK: 1598 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1599 case OATC14_HDD_STATUS_OPEN: 1600 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1601 case OATC14_HDD_STATUS_SHORT: 1602 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1603 case OATC14_HDD_STATUS_NOT_DETECTABLE: 1604 default: 1605 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1606 } 1607 } 1608 1609 /** 1610 * genphy_c45_oatc14_cable_test_get_status - Get status of OATC14 10Base-T1S 1611 * PHY cable test. 1612 * @phydev: pointer to the PHY device structure 1613 * @finished: pointer to a boolean set true if the test is complete 1614 * 1615 * Retrieves the current status of the OATC14 10Base-T1S PHY cable test. 1616 * This function reads the OATC14 HDD register to determine whether the test 1617 * results are valid and whether the test has finished. 1618 * 1619 * If the test is complete, the function reports the cable test result via 1620 * the ethtool cable test interface using ethnl_cable_test_result(), and then 1621 * clears the test control bit in the PHY register to reset the test state. 1622 * 1623 * Return: 0 on success, or a negative error code on failure (e.g. register 1624 * read/write error). 1625 */ 1626 int genphy_c45_oatc14_cable_test_get_status(struct phy_device *phydev, 1627 bool *finished) 1628 { 1629 int ret; 1630 u8 sts; 1631 1632 *finished = false; 1633 1634 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD); 1635 if (ret < 0) 1636 return ret; 1637 1638 if (!(ret & OATC14_HDD_VALID)) 1639 return 0; 1640 1641 *finished = true; 1642 1643 sts = FIELD_GET(OATC14_HDD_SHORT_OPEN_STATUS, ret); 1644 1645 ret = ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 1646 oatc14_cable_test_get_result_code(sts)); 1647 if (ret) 1648 return ret; 1649 1650 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 1651 MDIO_OATC14_HDD, OATC14_HDD_CONTROL); 1652 } 1653 EXPORT_SYMBOL(genphy_c45_oatc14_cable_test_get_status); 1654 1655 /** 1656 * genphy_c45_oatc14_cable_test_start - Start a cable test on an OATC14 1657 * 10Base-T1S PHY. 1658 * @phydev: Pointer to the PHY device structure 1659 * 1660 * This function initiates a cable diagnostic test on a Clause 45 OATC14 1661 * 10Base-T1S capable PHY device. It first reads the PHY’s advanced diagnostic 1662 * capability register to check if High Definition Diagnostics (HDD) mode is 1663 * supported. If the PHY does not report HDD capability, cable testing is not 1664 * supported and the function returns -EOPNOTSUPP. 1665 * 1666 * For PHYs that support HDD, the function sets the appropriate control bits in 1667 * the OATC14_HDD register to enable and start the cable diagnostic test. 1668 * 1669 * Return: 1670 * * 0 on success 1671 * * -EOPNOTSUPP if the PHY does not support HDD capability 1672 * * A negative error code on I/O or register access failures 1673 */ 1674 int genphy_c45_oatc14_cable_test_start(struct phy_device *phydev) 1675 { 1676 int ret; 1677 1678 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_ADFCAP); 1679 if (ret < 0) 1680 return ret; 1681 1682 if (!(ret & OATC14_ADFCAP_HDD_CAPABILITY)) 1683 return -EOPNOTSUPP; 1684 1685 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD, 1686 OATC14_HDD_CONTROL); 1687 if (ret) 1688 return ret; 1689 1690 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD); 1691 if (ret < 0) 1692 return ret; 1693 1694 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD, 1695 OATC14_HDD_START_CONTROL); 1696 } 1697 EXPORT_SYMBOL(genphy_c45_oatc14_cable_test_start); 1698 1699 /** 1700 * oatc14_update_sqi_capability - Read and update OATC14 10Base-T1S PHY SQI/SQI+ 1701 * capability 1702 * @phydev: Pointer to the PHY device structure 1703 * 1704 * This helper reads the OATC14 ADFCAP capability register to determine whether 1705 * the PHY supports SQI or SQI+ reporting. 1706 * 1707 * SQI+ capability is detected first. The SQI+ field indicates the number of 1708 * valid MSBs (3–8), corresponding to 8–256 SQI+ levels. When present, the 1709 * function stores the number of SQI+ bits and computes the maximum SQI+ value 1710 * as (2^bits - 1). 1711 * 1712 * If SQI+ is not supported, the function checks for basic SQI capability, 1713 * which provides 0–7 SQI levels. 1714 * 1715 * On success, the capability information is stored in 1716 * @phydev->oatc14_sqi_capability and marked as updated. 1717 * 1718 * Return: 1719 * * 0 - capability successfully read and stored 1720 * * -EOPNOTSUPP - SQI/SQI+ not supported by this PHY 1721 * * Negative errno on read failure 1722 */ 1723 static int oatc14_update_sqi_capability(struct phy_device *phydev) 1724 { 1725 u8 bits; 1726 int ret; 1727 1728 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_ADFCAP); 1729 if (ret < 0) 1730 return ret; 1731 1732 /* Check for SQI+ capability 1733 * 0 - SQI+ is not supported 1734 * (3-8) bits for (8-256) SQI+ levels supported 1735 */ 1736 bits = FIELD_GET(OATC14_ADFCAP_SQIPLUS_CAPABILITY, ret); 1737 if (bits) { 1738 phydev->oatc14_sqi_capability.sqiplus_bits = bits; 1739 /* Max sqi+ level supported: (2 ^ bits) - 1 */ 1740 phydev->oatc14_sqi_capability.sqi_max = BIT(bits) - 1; 1741 goto update_done; 1742 } 1743 1744 /* Check for SQI capability 1745 * 0 - SQI is not supported 1746 * 1 - SQI is supported (0-7 levels) 1747 */ 1748 if (ret & OATC14_ADFCAP_SQI_CAPABILITY) { 1749 phydev->oatc14_sqi_capability.sqi_max = OATC14_SQI_MAX_LEVEL; 1750 goto update_done; 1751 } 1752 1753 return -EOPNOTSUPP; 1754 1755 update_done: 1756 phydev->oatc14_sqi_capability.updated = true; 1757 return 0; 1758 } 1759 1760 /** 1761 * genphy_c45_oatc14_get_sqi_max - Get maximum supported SQI or SQI+ level of 1762 * OATC14 10Base-T1S PHY 1763 * @phydev: pointer to the PHY device structure 1764 * 1765 * This function returns the maximum supported Signal Quality Indicator (SQI) or 1766 * SQI+ level. The SQI capability is updated on first invocation if it has not 1767 * already been updated. 1768 * 1769 * Return: 1770 * * Maximum SQI/SQI+ level supported 1771 * * Negative errno on capability read failure 1772 */ 1773 int genphy_c45_oatc14_get_sqi_max(struct phy_device *phydev) 1774 { 1775 int ret; 1776 1777 if (!phydev->oatc14_sqi_capability.updated) { 1778 ret = oatc14_update_sqi_capability(phydev); 1779 if (ret) 1780 return ret; 1781 } 1782 1783 return phydev->oatc14_sqi_capability.sqi_max; 1784 } 1785 EXPORT_SYMBOL(genphy_c45_oatc14_get_sqi_max); 1786 1787 /** 1788 * genphy_c45_oatc14_get_sqi - Get Signal Quality Indicator (SQI) from an OATC14 1789 * 10Base-T1S PHY 1790 * @phydev: pointer to the PHY device structure 1791 * 1792 * This function reads the SQI+ or SQI value from an OATC14-compatible 1793 * 10Base-T1S PHY. If SQI+ capability is supported, the function returns the 1794 * extended SQI+ value; otherwise, it returns the basic SQI value. The SQI 1795 * capability is updated on first invocation if it has not already been updated. 1796 * 1797 * Return: 1798 * * SQI/SQI+ value on success 1799 * * Negative errno on read failure 1800 */ 1801 int genphy_c45_oatc14_get_sqi(struct phy_device *phydev) 1802 { 1803 u8 shift; 1804 int ret; 1805 1806 if (!phydev->oatc14_sqi_capability.updated) { 1807 ret = oatc14_update_sqi_capability(phydev); 1808 if (ret) 1809 return ret; 1810 } 1811 1812 /* Calculate and return SQI+ value if supported */ 1813 if (phydev->oatc14_sqi_capability.sqiplus_bits) { 1814 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1815 MDIO_OATC14_DCQ_SQIPLUS); 1816 if (ret < 0) 1817 return ret; 1818 1819 /* SQI+ uses N MSBs out of 8 bits, left-aligned with padding 1's 1820 * Calculate the right-shift needed to isolate the N bits. 1821 */ 1822 shift = 8 - phydev->oatc14_sqi_capability.sqiplus_bits; 1823 1824 return (ret & OATC14_DCQ_SQIPLUS_VALUE) >> shift; 1825 } 1826 1827 /* Read and return SQI value if SQI+ capability is not supported */ 1828 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_DCQ_SQI); 1829 if (ret < 0) 1830 return ret; 1831 1832 return ret & OATC14_DCQ_SQI_VALUE; 1833 } 1834 EXPORT_SYMBOL(genphy_c45_oatc14_get_sqi); 1835