1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 #ifndef __ADRENO_GEN7_9_0_SNAPSHOT_H 7 #define __ADRENO_GEN7_9_0_SNAPSHOT_H 8 9 #include "a6xx_gpu_state.h" 10 11 static const u32 gen7_9_0_debugbus_blocks[] = { 12 A7XX_DBGBUS_CP_0_0, 13 A7XX_DBGBUS_CP_0_1, 14 A7XX_DBGBUS_RBBM, 15 A7XX_DBGBUS_HLSQ, 16 A7XX_DBGBUS_UCHE_0, 17 A7XX_DBGBUS_UCHE_1, 18 A7XX_DBGBUS_TESS_BR, 19 A7XX_DBGBUS_TESS_BV, 20 A7XX_DBGBUS_PC_BR, 21 A7XX_DBGBUS_PC_BV, 22 A7XX_DBGBUS_VFDP_BR, 23 A7XX_DBGBUS_VFDP_BV, 24 A7XX_DBGBUS_VPC_BR, 25 A7XX_DBGBUS_VPC_BV, 26 A7XX_DBGBUS_TSE_BR, 27 A7XX_DBGBUS_TSE_BV, 28 A7XX_DBGBUS_RAS_BR, 29 A7XX_DBGBUS_RAS_BV, 30 A7XX_DBGBUS_VSC, 31 A7XX_DBGBUS_COM_0, 32 A7XX_DBGBUS_LRZ_BR, 33 A7XX_DBGBUS_LRZ_BV, 34 A7XX_DBGBUS_UFC_0, 35 A7XX_DBGBUS_UFC_1, 36 A7XX_DBGBUS_GMU_GX, 37 A7XX_DBGBUS_DBGC, 38 A7XX_DBGBUS_GPC_BR, 39 A7XX_DBGBUS_GPC_BV, 40 A7XX_DBGBUS_LARC, 41 A7XX_DBGBUS_HLSQ_SPTP, 42 A7XX_DBGBUS_RB_0, 43 A7XX_DBGBUS_RB_1, 44 A7XX_DBGBUS_RB_2, 45 A7XX_DBGBUS_RB_3, 46 A7XX_DBGBUS_RB_4, 47 A7XX_DBGBUS_RB_5, 48 A7XX_DBGBUS_UCHE_WRAPPER, 49 A7XX_DBGBUS_CCU_0, 50 A7XX_DBGBUS_CCU_1, 51 A7XX_DBGBUS_CCU_2, 52 A7XX_DBGBUS_CCU_3, 53 A7XX_DBGBUS_CCU_4, 54 A7XX_DBGBUS_CCU_5, 55 A7XX_DBGBUS_VFD_BR_0, 56 A7XX_DBGBUS_VFD_BR_1, 57 A7XX_DBGBUS_VFD_BR_2, 58 A7XX_DBGBUS_VFD_BV_0, 59 A7XX_DBGBUS_VFD_BV_1, 60 A7XX_DBGBUS_VFD_BV_2, 61 A7XX_DBGBUS_USP_0, 62 A7XX_DBGBUS_USP_1, 63 A7XX_DBGBUS_USP_2, 64 A7XX_DBGBUS_USP_3, 65 A7XX_DBGBUS_USP_4, 66 A7XX_DBGBUS_USP_5, 67 A7XX_DBGBUS_TP_0, 68 A7XX_DBGBUS_TP_1, 69 A7XX_DBGBUS_TP_2, 70 A7XX_DBGBUS_TP_3, 71 A7XX_DBGBUS_TP_4, 72 A7XX_DBGBUS_TP_5, 73 A7XX_DBGBUS_TP_6, 74 A7XX_DBGBUS_TP_7, 75 A7XX_DBGBUS_TP_8, 76 A7XX_DBGBUS_TP_9, 77 A7XX_DBGBUS_TP_10, 78 A7XX_DBGBUS_TP_11, 79 A7XX_DBGBUS_USPTP_0, 80 A7XX_DBGBUS_USPTP_1, 81 A7XX_DBGBUS_USPTP_2, 82 A7XX_DBGBUS_USPTP_3, 83 A7XX_DBGBUS_USPTP_4, 84 A7XX_DBGBUS_USPTP_5, 85 A7XX_DBGBUS_USPTP_6, 86 A7XX_DBGBUS_USPTP_7, 87 A7XX_DBGBUS_USPTP_8, 88 A7XX_DBGBUS_USPTP_9, 89 A7XX_DBGBUS_USPTP_10, 90 A7XX_DBGBUS_USPTP_11, 91 A7XX_DBGBUS_CCHE_0, 92 A7XX_DBGBUS_CCHE_1, 93 A7XX_DBGBUS_CCHE_2, 94 A7XX_DBGBUS_VPC_DSTR_0, 95 A7XX_DBGBUS_VPC_DSTR_1, 96 A7XX_DBGBUS_VPC_DSTR_2, 97 A7XX_DBGBUS_HLSQ_DP_STR_0, 98 A7XX_DBGBUS_HLSQ_DP_STR_1, 99 A7XX_DBGBUS_HLSQ_DP_STR_2, 100 A7XX_DBGBUS_HLSQ_DP_STR_3, 101 A7XX_DBGBUS_HLSQ_DP_STR_4, 102 A7XX_DBGBUS_HLSQ_DP_STR_5, 103 A7XX_DBGBUS_UFC_DSTR_0, 104 A7XX_DBGBUS_UFC_DSTR_1, 105 A7XX_DBGBUS_UFC_DSTR_2, 106 A7XX_DBGBUS_CGC_SUBCORE, 107 A7XX_DBGBUS_CGC_CORE, 108 }; 109 110 static const u32 gen7_9_0_gbif_debugbus_blocks[] = { 111 A7XX_DBGBUS_GBIF_GX, 112 }; 113 114 static const u32 gen7_9_0_cx_debugbus_blocks[] = { 115 A7XX_DBGBUS_CX, 116 A7XX_DBGBUS_GMU_CX, 117 A7XX_DBGBUS_GBIF_CX, 118 }; 119 120 static struct gen7_shader_block gen7_9_0_shader_blocks[] = { 121 { A7XX_TP0_TMO_DATA, 0x0200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 122 { A7XX_TP0_SMO_DATA, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 123 { A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 124 { A7XX_SP_INST_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 125 { A7XX_SP_INST_DATA_1, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 126 { A7XX_SP_LB_0_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 127 { A7XX_SP_LB_1_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 128 { A7XX_SP_LB_2_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 129 { A7XX_SP_LB_3_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 130 { A7XX_SP_LB_4_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 131 { A7XX_SP_LB_5_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 132 { A7XX_SP_LB_6_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 133 { A7XX_SP_LB_7_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 134 { A7XX_SP_CB_RAM, 0x0390, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 135 { A7XX_SP_LB_13_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 136 { A7XX_SP_LB_14_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 137 { A7XX_SP_INST_TAG, 0x00C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 138 { A7XX_SP_INST_DATA_2, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 139 { A7XX_SP_TMO_TAG, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 140 { A7XX_SP_SMO_TAG, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 141 { A7XX_SP_STATE_DATA, 0x0040, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 142 { A7XX_SP_HWAVE_RAM, 0x0100, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 143 { A7XX_SP_L0_INST_BUF, 0x0050, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 144 { A7XX_SP_LB_8_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 145 { A7XX_SP_LB_9_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 146 { A7XX_SP_LB_10_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 147 { A7XX_SP_LB_11_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 148 { A7XX_SP_LB_12_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 149 { A7XX_HLSQ_DATAPATH_DSTR_META, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 150 { A7XX_HLSQ_DATAPATH_DSTR_META, 0x0010, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 151 { A7XX_HLSQ_L2STC_TAG_RAM, 0x0200, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 152 { A7XX_HLSQ_L2STC_INFO_CMD, 0x0474, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 153 { A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 154 { A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 155 { A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 156 { A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 157 { A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 158 { A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 159 { A7XX_HLSQ_CHUNK_CVS_RAM, 0x01C0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 160 { A7XX_HLSQ_CHUNK_CVS_RAM, 0x01C0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 161 { A7XX_HLSQ_CHUNK_CPS_RAM, 0x0300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 162 { A7XX_HLSQ_CHUNK_CPS_RAM, 0x0180, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, 163 { A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 164 { A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 165 { A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 166 { A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, 167 { A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 168 { A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 169 { A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 170 { A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, 171 { A7XX_HLSQ_CVS_MISC_RAM, 0x0540, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 172 { A7XX_HLSQ_CVS_MISC_RAM, 0x0540, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 173 { A7XX_HLSQ_CPS_MISC_RAM, 0x0640, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 174 { A7XX_HLSQ_CPS_MISC_RAM, 0x00B0, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, 175 { A7XX_HLSQ_CPS_MISC_RAM_1, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 176 { A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 177 { A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 178 { A7XX_HLSQ_INST_RAM, 0x0200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, 179 { A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 180 { A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 181 { A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 182 { A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, 183 { A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0050, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 184 { A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0050, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 185 { A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0050, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 186 { A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0008, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, 187 { A7XX_HLSQ_INST_RAM_TAG, 0x0014, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 188 { A7XX_HLSQ_INST_RAM_TAG, 0x0010, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 189 { A7XX_HLSQ_INST_RAM_TAG, 0x0004, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, 190 { A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 191 { A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 192 { A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 193 { A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0020, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, 194 { A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x03C0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 195 { A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x0280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 196 { A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x0050, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, 197 { A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 198 { A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG, 0x0008, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 199 { A7XX_HLSQ_INST_RAM_1, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 200 { A7XX_HLSQ_STPROC_META, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 201 { A7XX_HLSQ_BV_BE_META, 0x0018, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 202 { A7XX_HLSQ_BV_BE_META, 0x0018, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 203 { A7XX_HLSQ_INST_RAM_2, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 204 { A7XX_HLSQ_DATAPATH_META, 0x0020, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 205 { A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 206 { A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 207 { A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, 208 { A7XX_HLSQ_INDIRECT_META, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 209 { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE }, 210 { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE }, 211 { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE }, 212 }; 213 214 /* 215 * Block : ['PRE_CRASHDUMPER', 'GBIF'] 216 * pairs : 2 (Regs:5), 5 (Regs:38) 217 */ 218 static const u32 gen7_9_0_pre_crashdumper_gpu_registers[] = { 219 0x00210, 0x00213, 0x00536, 0x00536, 0x03c00, 0x03c0b, 0x03c40, 0x03c42, 220 0x03c45, 0x03c47, 0x03c49, 0x03c4a, 0x03cc0, 0x03cd1, 221 UINT_MAX, UINT_MAX, 222 }; 223 static_assert(IS_ALIGNED(sizeof(gen7_9_0_pre_crashdumper_gpu_registers), 8)); 224 225 /* 226 * Block : ['BROADCAST', 'CP', 'GRAS', 'GXCLKCTL'] 227 * Block : ['PC', 'RBBM', 'RDVM', 'UCHE'] 228 * Block : ['VFD', 'VPC', 'VSC'] 229 * Pipeline: A7XX_PIPE_NONE 230 * pairs : 196 (Regs:1778) 231 */ 232 static const u32 gen7_9_0_gpu_registers[] = { 233 0x00000, 0x00000, 0x00002, 0x00002, 0x00011, 0x00012, 0x00016, 0x0001b, 234 0x0001f, 0x00032, 0x00038, 0x0003c, 0x00044, 0x00044, 0x00047, 0x00047, 235 0x00049, 0x0004a, 0x0004c, 0x0004c, 0x00056, 0x00056, 0x00073, 0x0007d, 236 0x00090, 0x000a8, 0x000ad, 0x000ad, 0x00117, 0x00117, 0x00120, 0x00122, 237 0x00130, 0x0013f, 0x00142, 0x0015f, 0x00162, 0x00164, 0x00166, 0x00171, 238 0x00173, 0x00174, 0x00176, 0x0017b, 0x0017e, 0x00180, 0x00183, 0x00192, 239 0x00195, 0x00196, 0x00199, 0x0019a, 0x0019d, 0x001a2, 0x001aa, 0x001ae, 240 0x001b9, 0x001b9, 0x001bb, 0x001bb, 0x001be, 0x001be, 0x001c1, 0x001c2, 241 0x001c5, 0x001c5, 0x001c7, 0x001c7, 0x001c9, 0x001c9, 0x001cb, 0x001ce, 242 0x001d1, 0x001df, 0x001e1, 0x001e3, 0x001e5, 0x001e5, 0x001e7, 0x001e9, 243 0x00200, 0x0020d, 0x00215, 0x00253, 0x00260, 0x00260, 0x00264, 0x00270, 244 0x00272, 0x00274, 0x00281, 0x00281, 0x00283, 0x00283, 0x00289, 0x0028d, 245 0x00290, 0x002a2, 0x002c0, 0x002c1, 0x00300, 0x00401, 0x00410, 0x00451, 246 0x00460, 0x004a3, 0x004c0, 0x004d1, 0x00500, 0x00500, 0x00507, 0x0050b, 247 0x0050f, 0x0050f, 0x00511, 0x00511, 0x00533, 0x00535, 0x00540, 0x0055b, 248 0x00564, 0x00567, 0x00574, 0x00577, 0x00584, 0x0059b, 0x005fb, 0x005ff, 249 0x00800, 0x00808, 0x00810, 0x00813, 0x00820, 0x00821, 0x00823, 0x00827, 250 0x00830, 0x00834, 0x0083f, 0x00841, 0x00843, 0x00847, 0x0084f, 0x00886, 251 0x008a0, 0x008ab, 0x008c0, 0x008c0, 0x008c4, 0x008c4, 0x008c6, 0x008c6, 252 0x008d0, 0x008dd, 0x008e0, 0x008e6, 0x008f0, 0x008f3, 0x00900, 0x00903, 253 0x00908, 0x00911, 0x00928, 0x0093e, 0x00942, 0x0094d, 0x00980, 0x00984, 254 0x0098d, 0x0098f, 0x009b0, 0x009b4, 0x009c2, 0x009c9, 0x009ce, 0x009d7, 255 0x009e0, 0x009e7, 0x00a00, 0x00a00, 0x00a02, 0x00a03, 0x00a10, 0x00a4f, 256 0x00a61, 0x00a9f, 0x00ad0, 0x00adb, 0x00b00, 0x00b31, 0x00b35, 0x00b3c, 257 0x00b40, 0x00b40, 0x00b70, 0x00b73, 0x00b78, 0x00b79, 0x00b7c, 0x00b7d, 258 0x00b80, 0x00b81, 0x00b84, 0x00b85, 0x00b88, 0x00b89, 0x00b8c, 0x00b8d, 259 0x00b90, 0x00b93, 0x00b98, 0x00b99, 0x00b9c, 0x00b9d, 0x00ba0, 0x00ba1, 260 0x00ba4, 0x00ba5, 0x00ba8, 0x00ba9, 0x00bac, 0x00bad, 0x00bb0, 0x00bb1, 261 0x00bb4, 0x00bb5, 0x00bb8, 0x00bb9, 0x00bbc, 0x00bbd, 0x00bc0, 0x00bc1, 262 0x00c00, 0x00c00, 0x00c02, 0x00c04, 0x00c06, 0x00c06, 0x00c10, 0x00cd9, 263 0x00ce0, 0x00d0c, 0x00df0, 0x00df4, 0x00e01, 0x00e02, 0x00e07, 0x00e0e, 264 0x00e10, 0x00e13, 0x00e17, 0x00e19, 0x00e1c, 0x00e2b, 0x00e30, 0x00e32, 265 0x00e3a, 0x00e3d, 0x00e50, 0x00e5b, 0x02840, 0x0287f, 0x0ec00, 0x0ec01, 266 0x0ec05, 0x0ec05, 0x0ec07, 0x0ec07, 0x0ec0a, 0x0ec0a, 0x0ec12, 0x0ec12, 267 0x0ec26, 0x0ec28, 0x0ec2b, 0x0ec2d, 0x0ec2f, 0x0ec2f, 0x0ec40, 0x0ec41, 268 0x0ec45, 0x0ec45, 0x0ec47, 0x0ec47, 0x0ec4a, 0x0ec4a, 0x0ec52, 0x0ec52, 269 0x0ec66, 0x0ec68, 0x0ec6b, 0x0ec6d, 0x0ec6f, 0x0ec6f, 0x0ec80, 0x0ec81, 270 0x0ec85, 0x0ec85, 0x0ec87, 0x0ec87, 0x0ec8a, 0x0ec8a, 0x0ec92, 0x0ec92, 271 0x0eca6, 0x0eca8, 0x0ecab, 0x0ecad, 0x0ecaf, 0x0ecaf, 0x0ecc0, 0x0ecc1, 272 0x0ecc5, 0x0ecc5, 0x0ecc7, 0x0ecc7, 0x0ecca, 0x0ecca, 0x0ecd2, 0x0ecd2, 273 0x0ece6, 0x0ece8, 0x0eceb, 0x0eced, 0x0ecef, 0x0ecef, 0x0ed00, 0x0ed01, 274 0x0ed05, 0x0ed05, 0x0ed07, 0x0ed07, 0x0ed0a, 0x0ed0a, 0x0ed12, 0x0ed12, 275 0x0ed26, 0x0ed28, 0x0ed2b, 0x0ed2d, 0x0ed2f, 0x0ed2f, 0x0ed40, 0x0ed41, 276 0x0ed45, 0x0ed45, 0x0ed47, 0x0ed47, 0x0ed4a, 0x0ed4a, 0x0ed52, 0x0ed52, 277 0x0ed66, 0x0ed68, 0x0ed6b, 0x0ed6d, 0x0ed6f, 0x0ed6f, 0x0ed80, 0x0ed81, 278 0x0ed85, 0x0ed85, 0x0ed87, 0x0ed87, 0x0ed8a, 0x0ed8a, 0x0ed92, 0x0ed92, 279 0x0eda6, 0x0eda8, 0x0edab, 0x0edad, 0x0edaf, 0x0edaf, 280 UINT_MAX, UINT_MAX, 281 }; 282 static_assert(IS_ALIGNED(sizeof(gen7_9_0_gpu_registers), 8)); 283 284 static const u32 gen7_9_0_gxclkctl_registers[] = { 285 0x18800, 0x18800, 0x18808, 0x1880b, 0x18820, 0x18822, 0x18830, 0x18830, 286 0x18834, 0x1883b, 287 UINT_MAX, UINT_MAX, 288 }; 289 static_assert(IS_ALIGNED(sizeof(gen7_9_0_gxclkctl_registers), 8)); 290 291 /* 292 * Block : ['GMUAO', 'GMUCX', 'GMUCX_RAM'] 293 * Pipeline: A7XX_PIPE_NONE 294 * pairs : 134 (Regs:429) 295 */ 296 static const u32 gen7_9_0_gmu_registers[] = { 297 0x10001, 0x10001, 0x10003, 0x10003, 0x10401, 0x10401, 0x10403, 0x10403, 298 0x10801, 0x10801, 0x10803, 0x10803, 0x10c01, 0x10c01, 0x10c03, 0x10c03, 299 0x11001, 0x11001, 0x11003, 0x11003, 0x11401, 0x11401, 0x11403, 0x11403, 300 0x11801, 0x11801, 0x11803, 0x11803, 0x11c01, 0x11c01, 0x11c03, 0x11c03, 301 0x1f400, 0x1f40b, 0x1f40f, 0x1f411, 0x1f500, 0x1f500, 0x1f507, 0x1f507, 302 0x1f509, 0x1f50b, 0x1f700, 0x1f701, 0x1f704, 0x1f706, 0x1f708, 0x1f709, 303 0x1f70c, 0x1f70d, 0x1f710, 0x1f711, 0x1f713, 0x1f716, 0x1f718, 0x1f71d, 304 0x1f720, 0x1f724, 0x1f729, 0x1f729, 0x1f730, 0x1f747, 0x1f750, 0x1f756, 305 0x1f758, 0x1f759, 0x1f75c, 0x1f75c, 0x1f760, 0x1f761, 0x1f764, 0x1f76b, 306 0x1f770, 0x1f775, 0x1f780, 0x1f785, 0x1f790, 0x1f798, 0x1f7a0, 0x1f7a8, 307 0x1f7b0, 0x1f7b3, 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c, 308 0x1f80f, 0x1f80f, 0x1f811, 0x1f811, 0x1f813, 0x1f817, 0x1f819, 0x1f81c, 309 0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f860, 0x1f860, 310 0x1f862, 0x1f866, 0x1f868, 0x1f869, 0x1f870, 0x1f879, 0x1f87f, 0x1f881, 311 0x1f890, 0x1f896, 0x1f8a0, 0x1f8a2, 0x1f8a4, 0x1f8af, 0x1f8b8, 0x1f8b9, 312 0x1f8c0, 0x1f8c1, 0x1f8c3, 0x1f8c4, 0x1f8d0, 0x1f8d0, 0x1f8ec, 0x1f8ec, 313 0x1f8f0, 0x1f8f1, 0x1f910, 0x1f917, 0x1f920, 0x1f921, 0x1f924, 0x1f925, 314 0x1f928, 0x1f929, 0x1f92c, 0x1f92d, 0x1f942, 0x1f944, 0x1f948, 0x1f94a, 315 0x1f94f, 0x1f951, 0x1f954, 0x1f955, 0x1f95d, 0x1f95d, 0x1f962, 0x1f96b, 316 0x1f970, 0x1f971, 0x1f973, 0x1f977, 0x1f97c, 0x1f97c, 0x1f980, 0x1f981, 317 0x1f984, 0x1f986, 0x1f992, 0x1f993, 0x1f996, 0x1f99e, 0x1f9c5, 0x1f9d4, 318 0x1f9f0, 0x1f9f1, 0x1f9f8, 0x1f9fa, 0x1f9fc, 0x1f9fc, 0x1fa00, 0x1fa03, 319 0x20000, 0x20013, 0x20018, 0x2001a, 0x20020, 0x20021, 0x20024, 0x20025, 320 0x2002a, 0x2002c, 0x20030, 0x20031, 0x20034, 0x20036, 0x23801, 0x23801, 321 0x23803, 0x23803, 0x23805, 0x23805, 0x23807, 0x23807, 0x23809, 0x23809, 322 0x2380b, 0x2380b, 0x2380d, 0x2380d, 0x2380f, 0x2380f, 0x23811, 0x23811, 323 0x23813, 0x23813, 0x23815, 0x23815, 0x23817, 0x23817, 0x23819, 0x23819, 324 0x2381b, 0x2381b, 0x2381d, 0x2381d, 0x2381f, 0x23820, 0x23822, 0x23822, 325 0x23824, 0x23824, 0x23826, 0x23826, 0x23828, 0x23828, 0x2382a, 0x2382a, 326 0x2382c, 0x2382c, 0x2382e, 0x2382e, 0x23830, 0x23830, 0x23832, 0x23832, 327 0x23834, 0x23834, 0x23836, 0x23836, 0x23838, 0x23838, 0x2383a, 0x2383a, 328 0x2383c, 0x2383c, 0x2383e, 0x2383e, 0x23840, 0x23847, 0x23b00, 0x23b01, 329 0x23b03, 0x23b03, 0x23b05, 0x23b0e, 0x23b10, 0x23b13, 0x23b15, 0x23b16, 330 0x23b28, 0x23b28, 0x23b30, 0x23b30, 331 UINT_MAX, UINT_MAX, 332 }; 333 static_assert(IS_ALIGNED(sizeof(gen7_9_0_gmu_registers), 8)); 334 335 /* 336 * Block : ['GMUGX'] 337 * Pipeline: A7XX_PIPE_NONE 338 * pairs : 44 (Regs:454) 339 */ 340 static const u32 gen7_9_0_gmugx_registers[] = { 341 0x1a400, 0x1a41f, 0x1a440, 0x1a45f, 0x1a480, 0x1a49f, 0x1a4c0, 0x1a4df, 342 0x1a500, 0x1a51f, 0x1a540, 0x1a55f, 0x1a580, 0x1a59f, 0x1a600, 0x1a61f, 343 0x1a640, 0x1a65f, 0x1a780, 0x1a781, 0x1a783, 0x1a785, 0x1a787, 0x1a789, 344 0x1a78b, 0x1a78d, 0x1a78f, 0x1a791, 0x1a793, 0x1a795, 0x1a797, 0x1a799, 345 0x1a79b, 0x1a79d, 0x1a79f, 0x1a7a1, 0x1a7a3, 0x1a7a3, 0x1a7a8, 0x1a7b9, 346 0x1a7c0, 0x1a7c1, 0x1a7c4, 0x1a7c5, 0x1a7c8, 0x1a7c9, 0x1a7cc, 0x1a7cd, 347 0x1a7d0, 0x1a7d1, 0x1a7d4, 0x1a7d5, 0x1a7d8, 0x1a7d9, 0x1a7dc, 0x1a7dd, 348 0x1a7e0, 0x1a7e1, 0x1a7fc, 0x1a7fd, 0x1a800, 0x1a808, 0x1a816, 0x1a816, 349 0x1a81e, 0x1a81e, 0x1a826, 0x1a826, 0x1a82e, 0x1a82e, 0x1a836, 0x1a836, 350 0x1a83e, 0x1a83e, 0x1a846, 0x1a846, 0x1a84e, 0x1a84e, 0x1a856, 0x1a856, 351 0x1a883, 0x1a884, 0x1a890, 0x1a8b3, 0x1a900, 0x1a92b, 0x1a940, 0x1a940, 352 UINT_MAX, UINT_MAX, 353 }; 354 static_assert(IS_ALIGNED(sizeof(gen7_9_0_gmugx_registers), 8)); 355 356 /* 357 * Block : ['CX_MISC'] 358 * Pipeline: A7XX_PIPE_NONE 359 * pairs : 7 (Regs:56) 360 */ 361 static const u32 gen7_9_0_cx_misc_registers[] = { 362 0x27800, 0x27800, 0x27810, 0x27814, 0x27820, 0x27824, 0x27828, 0x2782a, 363 0x27832, 0x27857, 0x27880, 0x27881, 0x27c00, 0x27c01, 364 UINT_MAX, UINT_MAX, 365 }; 366 static_assert(IS_ALIGNED(sizeof(gen7_9_0_cx_misc_registers), 8)); 367 368 /* 369 * Block : ['DBGC'] 370 * Pipeline: A7XX_PIPE_NONE 371 * pairs : 19 (Regs:155) 372 */ 373 static const u32 gen7_9_0_dbgc_registers[] = { 374 0x00600, 0x0061c, 0x0061e, 0x00634, 0x00640, 0x00643, 0x0064e, 0x00652, 375 0x00654, 0x0065e, 0x00699, 0x00699, 0x0069b, 0x0069e, 0x006c2, 0x006e4, 376 0x006e6, 0x006e6, 0x006e9, 0x006e9, 0x006eb, 0x006eb, 0x006f1, 0x006f4, 377 0x00700, 0x00707, 0x00718, 0x00718, 0x00720, 0x00729, 0x00740, 0x0074a, 378 0x00758, 0x00758, 0x00760, 0x00762, 379 UINT_MAX, UINT_MAX, 380 }; 381 static_assert(IS_ALIGNED(sizeof(gen7_9_0_dbgc_registers), 8)); 382 383 /* 384 * Block : ['CX_DBGC'] 385 * Pipeline: A7XX_PIPE_NONE 386 * pairs : 7 (Regs:75) 387 */ 388 static const u32 gen7_9_0_cx_dbgc_registers[] = { 389 0x18400, 0x1841c, 0x1841e, 0x18434, 0x18440, 0x18443, 0x1844e, 0x18452, 390 0x18454, 0x1845e, 0x18520, 0x18520, 0x18580, 0x18581, 391 UINT_MAX, UINT_MAX, 392 }; 393 static_assert(IS_ALIGNED(sizeof(gen7_9_0_cx_dbgc_registers), 8)); 394 395 /* 396 * Block : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF'] 397 * Block : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC'] 398 * Block : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC'] 399 * Pipeline: A7XX_PIPE_BR 400 * Cluster : A7XX_CLUSTER_NONE 401 * pairs : 29 (Regs:573) 402 */ 403 static const u32 gen7_9_0_non_context_pipe_br_registers[] = { 404 0x00887, 0x0088c, 0x08600, 0x08602, 0x08610, 0x0861b, 0x08620, 0x08620, 405 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640, 0x09600, 0x09603, 406 0x0960a, 0x09616, 0x09624, 0x0963a, 0x09640, 0x09640, 0x09e00, 0x09e00, 407 0x09e02, 0x09e07, 0x09e0a, 0x09e16, 0x09e18, 0x09e1a, 0x09e1c, 0x09e1c, 408 0x09e20, 0x09e25, 0x09e30, 0x09e31, 0x09e40, 0x09e51, 0x09e64, 0x09e6c, 409 0x09e70, 0x09e72, 0x09e78, 0x09e79, 0x09e80, 0x09fff, 0x0a600, 0x0a600, 410 0x0a603, 0x0a603, 0x0a610, 0x0a61f, 0x0a630, 0x0a631, 0x0a638, 0x0a63c, 411 0x0a640, 0x0a65f, 412 UINT_MAX, UINT_MAX, 413 }; 414 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_pipe_br_registers), 8)); 415 416 /* 417 * Block : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF'] 418 * Block : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC'] 419 * Block : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC'] 420 * Pipeline: A7XX_PIPE_BV 421 * Cluster : A7XX_CLUSTER_NONE 422 * pairs : 29 (Regs:573) 423 */ 424 static const u32 gen7_9_0_non_context_pipe_bv_registers[] = { 425 0x00887, 0x0088c, 0x08600, 0x08602, 0x08610, 0x0861b, 0x08620, 0x08620, 426 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640, 0x09600, 0x09603, 427 0x0960a, 0x09616, 0x09624, 0x0963a, 0x09640, 0x09640, 0x09e00, 0x09e00, 428 0x09e02, 0x09e07, 0x09e0a, 0x09e16, 0x09e18, 0x09e1a, 0x09e1c, 0x09e1c, 429 0x09e20, 0x09e25, 0x09e30, 0x09e31, 0x09e40, 0x09e51, 0x09e64, 0x09e6c, 430 0x09e70, 0x09e72, 0x09e78, 0x09e79, 0x09e80, 0x09fff, 0x0a600, 0x0a600, 431 0x0a603, 0x0a603, 0x0a610, 0x0a61f, 0x0a630, 0x0a631, 0x0a638, 0x0a63c, 432 0x0a640, 0x0a65f, 433 UINT_MAX, UINT_MAX, 434 }; 435 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_pipe_bv_registers), 8)); 436 437 /* 438 * Block : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF'] 439 * Block : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC'] 440 * Block : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC'] 441 * Pipeline: A7XX_PIPE_LPAC 442 * Cluster : A7XX_CLUSTER_NONE 443 * pairs : 2 (Regs:7) 444 */ 445 static const u32 gen7_9_0_non_context_pipe_lpac_registers[] = { 446 0x00887, 0x0088c, 0x00f80, 0x00f80, 447 UINT_MAX, UINT_MAX, 448 }; 449 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_pipe_lpac_registers), 8)); 450 451 /* 452 * Block : ['RB'] 453 * Pipeline: A7XX_PIPE_BR 454 * Cluster : A7XX_CLUSTER_NONE 455 * pairs : 5 (Regs:37) 456 */ 457 static const u32 gen7_9_0_non_context_rb_pipe_br_rac_registers[] = { 458 0x08e10, 0x08e1c, 0x08e20, 0x08e25, 0x08e51, 0x08e5a, 0x08e6a, 0x08e6d, 459 0x08ea0, 0x08ea3, 460 UINT_MAX, UINT_MAX, 461 }; 462 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_rb_pipe_br_rac_registers), 8)); 463 464 /* 465 * Block : ['RB'] 466 * Pipeline: A7XX_PIPE_BR 467 * Cluster : A7XX_CLUSTER_NONE 468 * pairs : 15 (Regs:66) 469 */ 470 static const u32 gen7_9_0_non_context_rb_pipe_br_rbp_registers[] = { 471 0x08e01, 0x08e01, 0x08e04, 0x08e04, 0x08e06, 0x08e09, 0x08e0c, 0x08e0c, 472 0x08e28, 0x08e28, 0x08e2c, 0x08e35, 0x08e3b, 0x08e40, 0x08e50, 0x08e50, 473 0x08e5b, 0x08e5d, 0x08e5f, 0x08e5f, 0x08e61, 0x08e61, 0x08e63, 0x08e66, 474 0x08e68, 0x08e69, 0x08e70, 0x08e7d, 0x08e80, 0x08e8f, 475 UINT_MAX, UINT_MAX, 476 }; 477 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_rb_pipe_br_rbp_registers), 8)); 478 479 /* 480 * Block : ['SP'] 481 * Pipeline: A7XX_PIPE_BR 482 * Cluster : A7XX_CLUSTER_NONE 483 * Location: A7XX_HLSQ_STATE 484 * pairs : 4 (Regs:28) 485 */ 486 static const u32 gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers[] = { 487 0x0ae52, 0x0ae52, 0x0ae60, 0x0ae67, 0x0ae69, 0x0ae75, 0x0aec0, 0x0aec5, 488 UINT_MAX, UINT_MAX, 489 }; 490 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers), 8)); 491 492 /* 493 * Block : ['SP'] 494 * Pipeline: A7XX_PIPE_BR 495 * Cluster : A7XX_CLUSTER_NONE 496 * Location: A7XX_SP_TOP 497 * pairs : 10 (Regs:61) 498 */ 499 static const u32 gen7_9_0_non_context_sp_pipe_br_sp_top_registers[] = { 500 0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae0a, 0x0ae0c, 0x0ae0c, 501 0x0ae0f, 0x0ae0f, 0x0ae28, 0x0ae2b, 0x0ae35, 0x0ae35, 0x0ae3a, 0x0ae3f, 502 0x0ae50, 0x0ae52, 0x0ae80, 0x0aea3, 503 UINT_MAX, UINT_MAX, 504 }; 505 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_br_sp_top_registers), 8)); 506 507 /* 508 * Block : ['SP'] 509 * Pipeline: A7XX_PIPE_BR 510 * Cluster : A7XX_CLUSTER_NONE 511 * Location: A7XX_USPTP 512 * pairs : 12 (Regs:62) 513 */ 514 static const u32 gen7_9_0_non_context_sp_pipe_br_usptp_registers[] = { 515 0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae0a, 0x0ae0c, 0x0ae0c, 516 0x0ae0f, 0x0ae0f, 0x0ae28, 0x0ae2b, 0x0ae30, 0x0ae32, 0x0ae35, 0x0ae35, 517 0x0ae3a, 0x0ae3b, 0x0ae3e, 0x0ae3f, 0x0ae50, 0x0ae52, 0x0ae80, 0x0aea3, 518 UINT_MAX, UINT_MAX, 519 }; 520 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_br_usptp_registers), 8)); 521 522 /* 523 * Block : ['SP'] 524 * Pipeline: A7XX_PIPE_BR 525 * Cluster : A7XX_CLUSTER_NONE 526 * Location: A7XX_HLSQ_DP_STR 527 * pairs : 2 (Regs:5) 528 */ 529 static const u32 gen7_9_0_non_context_sp_pipe_br_hlsq_dp_str_registers[] = { 530 0x0ae6b, 0x0ae6c, 0x0ae73, 0x0ae75, 531 UINT_MAX, UINT_MAX, 532 }; 533 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_br_hlsq_dp_str_registers), 8)); 534 535 /* 536 * Block : ['SP'] 537 * Pipeline: A7XX_PIPE_LPAC 538 * Cluster : A7XX_CLUSTER_NONE 539 * Location: A7XX_HLSQ_STATE 540 * pairs : 1 (Regs:5) 541 */ 542 static const u32 gen7_9_0_non_context_sp_pipe_lpac_hlsq_state_registers[] = { 543 0x0af88, 0x0af8c, 544 UINT_MAX, UINT_MAX, 545 }; 546 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_lpac_hlsq_state_registers), 8)); 547 548 /* 549 * Block : ['SP'] 550 * Pipeline: A7XX_PIPE_LPAC 551 * Cluster : A7XX_CLUSTER_NONE 552 * Location: A7XX_SP_TOP 553 * pairs : 1 (Regs:6) 554 */ 555 static const u32 gen7_9_0_non_context_sp_pipe_lpac_sp_top_registers[] = { 556 0x0af80, 0x0af85, 557 UINT_MAX, UINT_MAX, 558 }; 559 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_lpac_sp_top_registers), 8)); 560 561 /* 562 * Block : ['SP'] 563 * Pipeline: A7XX_PIPE_LPAC 564 * Cluster : A7XX_CLUSTER_NONE 565 * Location: A7XX_USPTP 566 * pairs : 2 (Regs:9) 567 */ 568 static const u32 gen7_9_0_non_context_sp_pipe_lpac_usptp_registers[] = { 569 0x0af80, 0x0af85, 0x0af90, 0x0af92, 570 UINT_MAX, UINT_MAX, 571 }; 572 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_lpac_usptp_registers), 8)); 573 574 /* 575 * Block : ['TPL1'] 576 * Pipeline: A7XX_PIPE_NONE 577 * Cluster : A7XX_CLUSTER_NONE 578 * Location: A7XX_USPTP 579 * pairs : 5 (Regs:29) 580 */ 581 static const u32 gen7_9_0_non_context_tpl1_pipe_none_usptp_registers[] = { 582 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c, 0x0b610, 0x0b621, 583 0x0b630, 0x0b633, 584 UINT_MAX, UINT_MAX, 585 }; 586 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_tpl1_pipe_none_usptp_registers), 8)); 587 588 /* 589 * Block : ['TPL1'] 590 * Pipeline: A7XX_PIPE_BR 591 * Cluster : A7XX_CLUSTER_NONE 592 * Location: A7XX_USPTP 593 * pairs : 1 (Regs:1) 594 */ 595 static const u32 gen7_9_0_non_context_tpl1_pipe_br_usptp_registers[] = { 596 0x0b600, 0x0b600, 597 UINT_MAX, UINT_MAX, 598 }; 599 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_tpl1_pipe_br_usptp_registers), 8)); 600 601 /* 602 * Block : ['TPL1'] 603 * Pipeline: A7XX_PIPE_LPAC 604 * Cluster : A7XX_CLUSTER_NONE 605 * Location: A7XX_USPTP 606 * pairs : 1 (Regs:1) 607 */ 608 static const u32 gen7_9_0_non_context_tpl1_pipe_lpac_usptp_registers[] = { 609 0x0b780, 0x0b780, 610 UINT_MAX, UINT_MAX, 611 }; 612 static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_tpl1_pipe_lpac_usptp_registers), 8)); 613 614 /* 615 * Block : ['GRAS'] 616 * Pipeline: A7XX_PIPE_BR 617 * Cluster : A7XX_CLUSTER_GRAS 618 * pairs : 14 (Regs:293) 619 */ 620 static const u32 gen7_9_0_gras_pipe_br_cluster_gras_registers[] = { 621 0x08000, 0x0800c, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d, 622 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa, 623 0x08100, 0x08107, 0x08109, 0x0810b, 0x08110, 0x08116, 0x08120, 0x0813f, 624 0x08400, 0x08406, 0x0840a, 0x0840b, 625 UINT_MAX, UINT_MAX, 626 }; 627 static_assert(IS_ALIGNED(sizeof(gen7_9_0_gras_pipe_br_cluster_gras_registers), 8)); 628 629 /* 630 * Block : ['GRAS'] 631 * Pipeline: A7XX_PIPE_BV 632 * Cluster : A7XX_CLUSTER_GRAS 633 * pairs : 14 (Regs:293) 634 */ 635 static const u32 gen7_9_0_gras_pipe_bv_cluster_gras_registers[] = { 636 0x08000, 0x0800c, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d, 637 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa, 638 0x08100, 0x08107, 0x08109, 0x0810b, 0x08110, 0x08116, 0x08120, 0x0813f, 639 0x08400, 0x08406, 0x0840a, 0x0840b, 640 UINT_MAX, UINT_MAX, 641 }; 642 static_assert(IS_ALIGNED(sizeof(gen7_9_0_gras_pipe_bv_cluster_gras_registers), 8)); 643 644 /* 645 * Block : ['PC'] 646 * Pipeline: A7XX_PIPE_BR 647 * Cluster : A7XX_CLUSTER_FE 648 * pairs : 6 (Regs:31) 649 */ 650 static const u32 gen7_9_0_pc_pipe_br_cluster_fe_registers[] = { 651 0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886, 652 0x09970, 0x09972, 0x09b00, 0x09b0c, 653 UINT_MAX, UINT_MAX, 654 }; 655 static_assert(IS_ALIGNED(sizeof(gen7_9_0_pc_pipe_br_cluster_fe_registers), 8)); 656 657 /* 658 * Block : ['PC'] 659 * Pipeline: A7XX_PIPE_BV 660 * Cluster : A7XX_CLUSTER_FE 661 * pairs : 6 (Regs:31) 662 */ 663 static const u32 gen7_9_0_pc_pipe_bv_cluster_fe_registers[] = { 664 0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886, 665 0x09970, 0x09972, 0x09b00, 0x09b0c, 666 UINT_MAX, UINT_MAX, 667 }; 668 static_assert(IS_ALIGNED(sizeof(gen7_9_0_pc_pipe_bv_cluster_fe_registers), 8)); 669 670 /* 671 * Block : ['VFD'] 672 * Pipeline: A7XX_PIPE_BR 673 * Cluster : A7XX_CLUSTER_FE 674 * pairs : 2 (Regs:236) 675 */ 676 static const u32 gen7_9_0_vfd_pipe_br_cluster_fe_registers[] = { 677 0x0a000, 0x0a009, 0x0a00e, 0x0a0ef, 678 UINT_MAX, UINT_MAX, 679 }; 680 static_assert(IS_ALIGNED(sizeof(gen7_9_0_vfd_pipe_br_cluster_fe_registers), 8)); 681 682 /* 683 * Block : ['VFD'] 684 * Pipeline: A7XX_PIPE_BV 685 * Cluster : A7XX_CLUSTER_FE 686 * pairs : 2 (Regs:236) 687 */ 688 static const u32 gen7_9_0_vfd_pipe_bv_cluster_fe_registers[] = { 689 0x0a000, 0x0a009, 0x0a00e, 0x0a0ef, 690 UINT_MAX, UINT_MAX, 691 }; 692 static_assert(IS_ALIGNED(sizeof(gen7_9_0_vfd_pipe_bv_cluster_fe_registers), 8)); 693 694 /* 695 * Block : ['VPC'] 696 * Pipeline: A7XX_PIPE_BR 697 * Cluster : A7XX_CLUSTER_FE 698 * pairs : 2 (Regs:18) 699 */ 700 static const u32 gen7_9_0_vpc_pipe_br_cluster_fe_registers[] = { 701 0x09300, 0x0930a, 0x09311, 0x09317, 702 UINT_MAX, UINT_MAX, 703 }; 704 static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_br_cluster_fe_registers), 8)); 705 706 /* 707 * Block : ['VPC'] 708 * Pipeline: A7XX_PIPE_BR 709 * Cluster : A7XX_CLUSTER_PC_VS 710 * pairs : 3 (Regs:30) 711 */ 712 static const u32 gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers[] = { 713 0x09101, 0x0910c, 0x09300, 0x0930a, 0x09311, 0x09317, 714 UINT_MAX, UINT_MAX, 715 }; 716 static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers), 8)); 717 718 /* 719 * Block : ['VPC'] 720 * Pipeline: A7XX_PIPE_BR 721 * Cluster : A7XX_CLUSTER_VPC_PS 722 * pairs : 5 (Regs:76) 723 */ 724 static const u32 gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers[] = { 725 0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x0923c, 0x09300, 0x0930a, 726 0x09311, 0x09317, 727 UINT_MAX, UINT_MAX, 728 }; 729 static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers), 8)); 730 731 /* 732 * Block : ['VPC'] 733 * Pipeline: A7XX_PIPE_BV 734 * Cluster : A7XX_CLUSTER_FE 735 * pairs : 2 (Regs:18) 736 */ 737 static const u32 gen7_9_0_vpc_pipe_bv_cluster_fe_registers[] = { 738 0x09300, 0x0930a, 0x09311, 0x09317, 739 UINT_MAX, UINT_MAX, 740 }; 741 static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_bv_cluster_fe_registers), 8)); 742 743 /* 744 * Block : ['VPC'] 745 * Pipeline: A7XX_PIPE_BV 746 * Cluster : A7XX_CLUSTER_PC_VS 747 * pairs : 3 (Regs:30) 748 */ 749 static const u32 gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers[] = { 750 0x09101, 0x0910c, 0x09300, 0x0930a, 0x09311, 0x09317, 751 UINT_MAX, UINT_MAX, 752 }; 753 static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers), 8)); 754 755 /* 756 * Block : ['VPC'] 757 * Pipeline: A7XX_PIPE_BV 758 * Cluster : A7XX_CLUSTER_VPC_PS 759 * pairs : 5 (Regs:76) 760 */ 761 static const u32 gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers[] = { 762 0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x0923c, 0x09300, 0x0930a, 763 0x09311, 0x09317, 764 UINT_MAX, UINT_MAX, 765 }; 766 static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers), 8)); 767 768 /* 769 * Block : ['RB'] 770 * Pipeline: A7XX_PIPE_BR 771 * Cluster : A7XX_CLUSTER_PS 772 * pairs : 39 (Regs:133) 773 */ 774 static const u32 gen7_9_0_rb_pipe_br_cluster_ps_rac_registers[] = { 775 0x08802, 0x08802, 0x08804, 0x08806, 0x08809, 0x0880a, 0x0880e, 0x08811, 776 0x08818, 0x0881e, 0x08821, 0x08821, 0x08823, 0x08826, 0x08829, 0x08829, 777 0x0882b, 0x0882e, 0x08831, 0x08831, 0x08833, 0x08836, 0x08839, 0x08839, 778 0x0883b, 0x0883e, 0x08841, 0x08841, 0x08843, 0x08846, 0x08849, 0x08849, 779 0x0884b, 0x0884e, 0x08851, 0x08851, 0x08853, 0x08856, 0x08859, 0x08859, 780 0x0885b, 0x0885e, 0x08860, 0x08864, 0x08870, 0x08870, 0x08873, 0x08876, 781 0x08878, 0x08879, 0x08882, 0x08885, 0x08887, 0x08889, 0x08891, 0x08891, 782 0x08898, 0x08899, 0x088c0, 0x088c1, 0x088e5, 0x088e5, 0x088f4, 0x088f5, 783 0x08a00, 0x08a05, 0x08a10, 0x08a15, 0x08a20, 0x08a25, 0x08a30, 0x08a35, 784 0x08c00, 0x08c01, 0x08c18, 0x08c1f, 0x08c26, 0x08c34, 785 UINT_MAX, UINT_MAX, 786 }; 787 static_assert(IS_ALIGNED(sizeof(gen7_9_0_rb_pipe_br_cluster_ps_rac_registers), 8)); 788 789 /* 790 * Block : ['RB'] 791 * Pipeline: A7XX_PIPE_BR 792 * Cluster : A7XX_CLUSTER_PS 793 * pairs : 34 (Regs:100) 794 */ 795 static const u32 gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers[] = { 796 0x08800, 0x08801, 0x08803, 0x08803, 0x0880b, 0x0880d, 0x08812, 0x08812, 797 0x08820, 0x08820, 0x08822, 0x08822, 0x08827, 0x08828, 0x0882a, 0x0882a, 798 0x0882f, 0x08830, 0x08832, 0x08832, 0x08837, 0x08838, 0x0883a, 0x0883a, 799 0x0883f, 0x08840, 0x08842, 0x08842, 0x08847, 0x08848, 0x0884a, 0x0884a, 800 0x0884f, 0x08850, 0x08852, 0x08852, 0x08857, 0x08858, 0x0885a, 0x0885a, 801 0x0885f, 0x0885f, 0x08865, 0x08865, 0x08871, 0x08872, 0x08877, 0x08877, 802 0x08880, 0x08881, 0x08886, 0x08886, 0x08890, 0x08890, 0x088d0, 0x088e4, 803 0x088e8, 0x088ea, 0x088f0, 0x088f0, 0x08900, 0x0891a, 0x08927, 0x08928, 804 0x08c17, 0x08c17, 0x08c20, 0x08c25, 805 UINT_MAX, UINT_MAX, 806 }; 807 static_assert(IS_ALIGNED(sizeof(gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers), 8)); 808 809 /* 810 * Block : ['SP'] 811 * Pipeline: A7XX_PIPE_BR 812 * Cluster : A7XX_CLUSTER_SP_VS 813 * Location: A7XX_HLSQ_STATE 814 * pairs : 29 (Regs:215) 815 */ 816 static const u32 gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers[] = { 817 0x0a800, 0x0a801, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824, 818 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a832, 0x0a835, 0x0a83a, 0x0a83a, 819 0x0a83c, 0x0a83c, 0x0a83f, 0x0a841, 0x0a85b, 0x0a85d, 0x0a862, 0x0a862, 820 0x0a864, 0x0a864, 0x0a867, 0x0a867, 0x0a870, 0x0a870, 0x0a872, 0x0a872, 821 0x0a88c, 0x0a88e, 0x0a893, 0x0a893, 0x0a895, 0x0a895, 0x0a898, 0x0a898, 822 0x0a89a, 0x0a89d, 0x0a8a0, 0x0a8af, 0x0a8c0, 0x0a8c3, 0x0a974, 0x0a977, 823 0x0ab00, 0x0ab03, 0x0ab05, 0x0ab05, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 824 0x0ab40, 0x0abbf, 825 UINT_MAX, UINT_MAX, 826 }; 827 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers), 8)); 828 829 /* 830 * Block : ['SP'] 831 * Pipeline: A7XX_PIPE_BR 832 * Cluster : A7XX_CLUSTER_SP_VS 833 * Location: A7XX_SP_TOP 834 * pairs : 22 (Regs:73) 835 */ 836 static const u32 gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers[] = { 837 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a82d, 0x0a82d, 838 0x0a82f, 0x0a831, 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, 839 0x0a85c, 0x0a85d, 0x0a862, 0x0a864, 0x0a868, 0x0a868, 0x0a870, 0x0a871, 840 0x0a88d, 0x0a88e, 0x0a893, 0x0a895, 0x0a899, 0x0a899, 0x0a8a0, 0x0a8af, 841 0x0a974, 0x0a977, 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab04, 0x0ab05, 842 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 843 UINT_MAX, UINT_MAX, 844 }; 845 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers), 8)); 846 847 /* 848 * Block : ['SP'] 849 * Pipeline: A7XX_PIPE_BR 850 * Cluster : A7XX_CLUSTER_SP_VS 851 * Location: A7XX_USPTP 852 * pairs : 16 (Regs:269) 853 */ 854 static const u32 gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers[] = { 855 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a82d, 0x0a82d, 856 0x0a82f, 0x0a833, 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, 857 0x0a863, 0x0a868, 0x0a870, 0x0a88c, 0x0a88f, 0x0a892, 0x0a894, 0x0a899, 858 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab05, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf, 859 UINT_MAX, UINT_MAX, 860 }; 861 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers), 8)); 862 863 /* 864 * Block : ['SP'] 865 * Pipeline: A7XX_PIPE_BR 866 * Cluster : A7XX_CLUSTER_SP_PS 867 * Location: A7XX_HLSQ_STATE 868 * pairs : 21 (Regs:334) 869 */ 870 static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers[] = { 871 0x0a980, 0x0a984, 0x0a99e, 0x0a99e, 0x0a9a7, 0x0a9a7, 0x0a9aa, 0x0a9aa, 872 0x0a9ae, 0x0a9b0, 0x0a9b2, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc, 873 0x0a9c4, 0x0a9c4, 0x0a9c6, 0x0a9c6, 0x0a9cd, 0x0a9cd, 0x0a9e0, 0x0a9fc, 874 0x0aa00, 0x0aa00, 0x0aa30, 0x0aa31, 0x0aa40, 0x0aabf, 0x0aaf2, 0x0aaf3, 875 0x0ab00, 0x0ab03, 0x0ab05, 0x0ab05, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 876 0x0ab40, 0x0abbf, 877 UINT_MAX, UINT_MAX, 878 }; 879 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers), 8)); 880 881 /* 882 * Block : ['SP'] 883 * Pipeline: A7XX_PIPE_BR 884 * Cluster : A7XX_CLUSTER_SP_PS 885 * Location: A7XX_HLSQ_DP 886 * pairs : 3 (Regs:19) 887 */ 888 static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers[] = { 889 0x0a9b1, 0x0a9b1, 0x0a9c6, 0x0a9cb, 0x0a9d4, 0x0a9df, 890 UINT_MAX, UINT_MAX, 891 }; 892 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers), 8)); 893 894 /* 895 * Block : ['SP'] 896 * Pipeline: A7XX_PIPE_BR 897 * Cluster : A7XX_CLUSTER_SP_PS 898 * Location: A7XX_SP_TOP 899 * pairs : 18 (Regs:77) 900 */ 901 static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers[] = { 902 0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a9a2, 0x0a9a7, 0x0a9a8, 903 0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9ae, 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, 904 0x0a9ba, 0x0a9bc, 0x0a9c5, 0x0a9c5, 0x0a9e0, 0x0a9f9, 0x0aa00, 0x0aa03, 905 0x0aaf2, 0x0aaf3, 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab04, 0x0ab05, 906 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 907 UINT_MAX, UINT_MAX, 908 }; 909 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers), 8)); 910 911 /* 912 * Block : ['SP'] 913 * Pipeline: A7XX_PIPE_BR 914 * Cluster : A7XX_CLUSTER_SP_PS 915 * Location: A7XX_USPTP 916 * pairs : 17 (Regs:333) 917 */ 918 static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers[] = { 919 0x0a980, 0x0a982, 0x0a985, 0x0a9a6, 0x0a9a8, 0x0a9a9, 0x0a9ab, 0x0a9ae, 920 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9bf, 0x0a9c2, 0x0a9c3, 921 0x0a9c5, 0x0a9c5, 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa01, 0x0aa03, 922 0x0aa30, 0x0aa31, 0x0aa40, 0x0aabf, 0x0ab00, 0x0ab05, 0x0ab21, 0x0ab22, 923 0x0ab40, 0x0abbf, 924 UINT_MAX, UINT_MAX, 925 }; 926 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers), 8)); 927 928 /* 929 * Block : ['SP'] 930 * Pipeline: A7XX_PIPE_BR 931 * Cluster : A7XX_CLUSTER_SP_PS 932 * Location: A7XX_HLSQ_DP_STR 933 * pairs : 1 (Regs:6) 934 */ 935 static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers[] = { 936 0x0a9c6, 0x0a9cb, 937 UINT_MAX, UINT_MAX, 938 }; 939 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers), 8)); 940 941 /* 942 * Block : ['SP'] 943 * Pipeline: A7XX_PIPE_BV 944 * Cluster : A7XX_CLUSTER_SP_VS 945 * Location: A7XX_HLSQ_STATE 946 * pairs : 28 (Regs:213) 947 */ 948 static const u32 gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers[] = { 949 0x0a800, 0x0a801, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824, 950 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a832, 0x0a835, 0x0a83a, 0x0a83a, 951 0x0a83c, 0x0a83c, 0x0a83f, 0x0a841, 0x0a85b, 0x0a85d, 0x0a862, 0x0a862, 952 0x0a864, 0x0a864, 0x0a867, 0x0a867, 0x0a870, 0x0a870, 0x0a872, 0x0a872, 953 0x0a88c, 0x0a88e, 0x0a893, 0x0a893, 0x0a895, 0x0a895, 0x0a898, 0x0a898, 954 0x0a89a, 0x0a89d, 0x0a8a0, 0x0a8af, 0x0a8c0, 0x0a8c3, 0x0a974, 0x0a977, 955 0x0ab00, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf, 956 UINT_MAX, UINT_MAX, 957 }; 958 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers), 8)); 959 960 /* 961 * Block : ['SP'] 962 * Pipeline: A7XX_PIPE_BV 963 * Cluster : A7XX_CLUSTER_SP_VS 964 * Location: A7XX_SP_TOP 965 * pairs : 21 (Regs:71) 966 */ 967 static const u32 gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers[] = { 968 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a82d, 0x0a82d, 969 0x0a82f, 0x0a831, 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, 970 0x0a85c, 0x0a85d, 0x0a862, 0x0a864, 0x0a868, 0x0a868, 0x0a870, 0x0a871, 971 0x0a88d, 0x0a88e, 0x0a893, 0x0a895, 0x0a899, 0x0a899, 0x0a8a0, 0x0a8af, 972 0x0a974, 0x0a977, 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab0a, 0x0ab1b, 973 0x0ab20, 0x0ab20, 974 UINT_MAX, UINT_MAX, 975 }; 976 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers), 8)); 977 978 /* 979 * Block : ['SP'] 980 * Pipeline: A7XX_PIPE_BV 981 * Cluster : A7XX_CLUSTER_SP_VS 982 * Location: A7XX_USPTP 983 * pairs : 16 (Regs:266) 984 */ 985 static const u32 gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers[] = { 986 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a82d, 0x0a82d, 987 0x0a82f, 0x0a833, 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, 988 0x0a863, 0x0a868, 0x0a870, 0x0a88c, 0x0a88f, 0x0a892, 0x0a894, 0x0a899, 989 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab02, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf, 990 UINT_MAX, UINT_MAX, 991 }; 992 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers), 8)); 993 994 /* 995 * Block : ['SP'] 996 * Pipeline: A7XX_PIPE_LPAC 997 * Cluster : A7XX_CLUSTER_SP_PS 998 * Location: A7XX_HLSQ_STATE 999 * pairs : 14 (Regs:299) 1000 */ 1001 static const u32 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_state_registers[] = { 1002 0x0a9b0, 0x0a9b0, 0x0a9b2, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc, 1003 0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9fc, 1004 0x0aa00, 0x0aa00, 0x0aa31, 0x0aa35, 0x0aa40, 0x0aabf, 0x0aaf3, 0x0aaf3, 1005 0x0ab00, 0x0ab01, 0x0ab40, 0x0abbf, 1006 UINT_MAX, UINT_MAX, 1007 }; 1008 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_state_registers), 8)); 1009 1010 /* 1011 * Block : ['SP'] 1012 * Pipeline: A7XX_PIPE_LPAC 1013 * Cluster : A7XX_CLUSTER_SP_PS 1014 * Location: A7XX_HLSQ_DP 1015 * pairs : 2 (Regs:13) 1016 */ 1017 static const u32 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_dp_registers[] = { 1018 0x0a9b1, 0x0a9b1, 0x0a9d4, 0x0a9df, 1019 UINT_MAX, UINT_MAX, 1020 }; 1021 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_dp_registers), 8)); 1022 1023 /* 1024 * Block : ['SP'] 1025 * Pipeline: A7XX_PIPE_LPAC 1026 * Cluster : A7XX_CLUSTER_SP_PS 1027 * Location: A7XX_SP_TOP 1028 * pairs : 9 (Regs:34) 1029 */ 1030 static const u32 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_sp_top_registers[] = { 1031 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9bc, 0x0a9c5, 0x0a9c5, 1032 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9f9, 0x0aa00, 0x0aa00, 0x0aaf3, 0x0aaf3, 1033 0x0ab00, 0x0ab00, 1034 UINT_MAX, UINT_MAX, 1035 }; 1036 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_lpac_cluster_sp_ps_sp_top_registers), 8)); 1037 1038 /* 1039 * Block : ['SP'] 1040 * Pipeline: A7XX_PIPE_LPAC 1041 * Cluster : A7XX_CLUSTER_SP_PS 1042 * Location: A7XX_USPTP 1043 * pairs : 11 (Regs:279) 1044 */ 1045 static const u32 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_usptp_registers[] = { 1046 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9be, 0x0a9c2, 0x0a9c3, 1047 0x0a9c5, 0x0a9c5, 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa31, 0x0aa31, 1048 0x0aa40, 0x0aabf, 0x0ab00, 0x0ab01, 0x0ab40, 0x0abbf, 1049 UINT_MAX, UINT_MAX, 1050 }; 1051 static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_lpac_cluster_sp_ps_usptp_registers), 8)); 1052 1053 /* 1054 * Block : ['TPL1'] 1055 * Pipeline: A7XX_PIPE_BR 1056 * Cluster : A7XX_CLUSTER_SP_VS 1057 * Location: A7XX_USPTP 1058 * pairs : 3 (Regs:10) 1059 */ 1060 static const u32 gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers[] = { 1061 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310, 1062 UINT_MAX, UINT_MAX, 1063 }; 1064 static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers), 8)); 1065 1066 /* 1067 * Block : ['TPL1'] 1068 * Pipeline: A7XX_PIPE_BR 1069 * Cluster : A7XX_CLUSTER_SP_PS 1070 * Location: A7XX_USPTP 1071 * pairs : 6 (Regs:42) 1072 */ 1073 static const u32 gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers[] = { 1074 0x0b180, 0x0b183, 0x0b190, 0x0b195, 0x0b2c0, 0x0b2d5, 0x0b300, 0x0b307, 1075 0x0b309, 0x0b309, 0x0b310, 0x0b310, 1076 UINT_MAX, UINT_MAX, 1077 }; 1078 static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers), 8)); 1079 1080 /* 1081 * Block : ['TPL1'] 1082 * Pipeline: A7XX_PIPE_BV 1083 * Cluster : A7XX_CLUSTER_SP_VS 1084 * Location: A7XX_USPTP 1085 * pairs : 3 (Regs:10) 1086 */ 1087 static const u32 gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers[] = { 1088 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310, 1089 UINT_MAX, UINT_MAX, 1090 }; 1091 static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers), 8)); 1092 1093 /* 1094 * Block : ['TPL1'] 1095 * Pipeline: A7XX_PIPE_LPAC 1096 * Cluster : A7XX_CLUSTER_SP_PS 1097 * Location: A7XX_USPTP 1098 * pairs : 5 (Regs:7) 1099 */ 1100 static const u32 gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers[] = { 1101 0x0b180, 0x0b181, 0x0b300, 0x0b301, 0x0b307, 0x0b307, 0x0b309, 0x0b309, 1102 0x0b310, 0x0b310, 1103 UINT_MAX, UINT_MAX, 1104 }; 1105 static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers), 8)); 1106 1107 static const struct gen7_sel_reg gen7_9_0_rb_rac_sel = { 1108 .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, 1109 .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 1110 .val = 0, 1111 }; 1112 1113 static const struct gen7_sel_reg gen7_9_0_rb_rbp_sel = { 1114 .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, 1115 .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 1116 .val = 0x9, 1117 }; 1118 1119 static struct gen7_cluster_registers gen7_9_0_clusters[] = { 1120 { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, 1121 gen7_9_0_non_context_pipe_br_registers, }, 1122 { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT, 1123 gen7_9_0_non_context_pipe_bv_registers, }, 1124 { A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT, 1125 gen7_9_0_non_context_pipe_lpac_registers, }, 1126 { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, 1127 gen7_9_0_non_context_rb_pipe_br_rac_registers, &gen7_9_0_rb_rac_sel, }, 1128 { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, 1129 gen7_9_0_non_context_rb_pipe_br_rbp_registers, &gen7_9_0_rb_rbp_sel, }, 1130 { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, 1131 gen7_9_0_rb_pipe_br_cluster_ps_rac_registers, &gen7_9_0_rb_rac_sel, }, 1132 { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, 1133 gen7_9_0_rb_pipe_br_cluster_ps_rac_registers, &gen7_9_0_rb_rac_sel, }, 1134 { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, 1135 gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers, &gen7_9_0_rb_rbp_sel, }, 1136 { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, 1137 gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers, &gen7_9_0_rb_rbp_sel, }, 1138 { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, 1139 gen7_9_0_gras_pipe_br_cluster_gras_registers, }, 1140 { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, 1141 gen7_9_0_gras_pipe_br_cluster_gras_registers, }, 1142 { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, 1143 gen7_9_0_gras_pipe_bv_cluster_gras_registers, }, 1144 { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, 1145 gen7_9_0_gras_pipe_bv_cluster_gras_registers, }, 1146 { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, 1147 gen7_9_0_pc_pipe_br_cluster_fe_registers, }, 1148 { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, 1149 gen7_9_0_pc_pipe_br_cluster_fe_registers, }, 1150 { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, 1151 gen7_9_0_pc_pipe_bv_cluster_fe_registers, }, 1152 { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, 1153 gen7_9_0_pc_pipe_bv_cluster_fe_registers, }, 1154 { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, 1155 gen7_9_0_vfd_pipe_br_cluster_fe_registers, }, 1156 { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, 1157 gen7_9_0_vfd_pipe_br_cluster_fe_registers, }, 1158 { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, 1159 gen7_9_0_vfd_pipe_bv_cluster_fe_registers, }, 1160 { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, 1161 gen7_9_0_vfd_pipe_bv_cluster_fe_registers, }, 1162 { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, 1163 gen7_9_0_vpc_pipe_br_cluster_fe_registers, }, 1164 { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, 1165 gen7_9_0_vpc_pipe_br_cluster_fe_registers, }, 1166 { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, 1167 gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers, }, 1168 { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, 1169 gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers, }, 1170 { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, 1171 gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers, }, 1172 { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, 1173 gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers, }, 1174 { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, 1175 gen7_9_0_vpc_pipe_bv_cluster_fe_registers, }, 1176 { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, 1177 gen7_9_0_vpc_pipe_bv_cluster_fe_registers, }, 1178 { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, 1179 gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers, }, 1180 { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, 1181 gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers, }, 1182 { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, 1183 gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers, }, 1184 { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, 1185 gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers, }, 1186 }; 1187 1188 static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = { 1189 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, 1190 gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers, 0xae00}, 1191 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, 1192 gen7_9_0_non_context_sp_pipe_br_sp_top_registers, 0xae00}, 1193 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, 1194 gen7_9_0_non_context_sp_pipe_br_usptp_registers, 0xae00}, 1195 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP_STR, 1196 gen7_9_0_non_context_sp_pipe_br_hlsq_dp_str_registers, 0xae00}, 1197 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE, 1198 gen7_9_0_non_context_sp_pipe_lpac_hlsq_state_registers, 0xaf80}, 1199 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP, 1200 gen7_9_0_non_context_sp_pipe_lpac_sp_top_registers, 0xaf80}, 1201 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, 1202 gen7_9_0_non_context_sp_pipe_lpac_usptp_registers, 0xaf80}, 1203 { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_NONE, 0, A7XX_USPTP, 1204 gen7_9_0_non_context_tpl1_pipe_none_usptp_registers, 0xb600}, 1205 { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, 1206 gen7_9_0_non_context_tpl1_pipe_br_usptp_registers, 0xb600}, 1207 { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, 1208 gen7_9_0_non_context_tpl1_pipe_lpac_usptp_registers, 0xb780}, 1209 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, 1210 gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers, 0xa800}, 1211 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, 1212 gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers, 0xa800}, 1213 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, 1214 gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers, 0xa800}, 1215 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ_STATE, 1216 gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers, 0xa800}, 1217 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_TOP, 1218 gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers, 0xa800}, 1219 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP, 1220 gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers, 0xa800}, 1221 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE, 1222 gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers, 0xa800}, 1223 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP, 1224 gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers, 0xa800}, 1225 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP, 1226 gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers, 0xa800}, 1227 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ_STATE, 1228 gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers, 0xa800}, 1229 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_TOP, 1230 gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers, 0xa800}, 1231 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP, 1232 gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers, 0xa800}, 1233 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, 1234 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers, 0xa800}, 1235 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP, 1236 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800}, 1237 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, 1238 gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800}, 1239 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, 1240 gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800}, 1241 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP_STR, 1242 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800}, 1243 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE, 1244 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_state_registers, 0xa800}, 1245 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_DP, 1246 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_dp_registers, 0xa800}, 1247 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP, 1248 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_sp_top_registers, 0xa800}, 1249 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, 1250 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_usptp_registers, 0xa800}, 1251 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE, 1252 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers, 0xa800}, 1253 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP, 1254 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800}, 1255 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP, 1256 gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800}, 1257 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP, 1258 gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800}, 1259 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP_STR, 1260 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800}, 1261 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP, 1262 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800}, 1263 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_TOP, 1264 gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800}, 1265 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP, 1266 gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800}, 1267 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP_STR, 1268 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800}, 1269 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP, 1270 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800}, 1271 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_TOP, 1272 gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800}, 1273 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP, 1274 gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800}, 1275 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP_STR, 1276 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800}, 1277 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, 1278 gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers, 0xb000}, 1279 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP, 1280 gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers, 0xb000}, 1281 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP, 1282 gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers, 0xb000}, 1283 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP, 1284 gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers, 0xb000}, 1285 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, 1286 gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000}, 1287 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, 1288 gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers, 0xb000}, 1289 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP, 1290 gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000}, 1291 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP, 1292 gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000}, 1293 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP, 1294 gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000}, 1295 }; 1296 1297 static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = { 1298 { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR, 1299 REG_A6XX_CP_SQE_STAT_DATA, 0x00040}, 1300 { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR, 1301 REG_A6XX_CP_DRAW_STATE_DATA, 0x00200}, 1302 { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR, 1303 REG_A6XX_CP_ROQ_DBG_DATA, 0x00800}, 1304 { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 1305 REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x08000}, 1306 { "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR, 1307 REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x00200}, 1308 { "CP_BV_ROQ_DBG_ADDR", REG_A7XX_CP_BV_ROQ_DBG_ADDR, 1309 REG_A7XX_CP_BV_ROQ_DBG_DATA, 0x00800}, 1310 { "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR, 1311 REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x08000}, 1312 { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR, 1313 REG_A7XX_CP_BV_SQE_STAT_DATA, 0x00040}, 1314 { "CP_RESOURCE_TBL", REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR, 1315 REG_A7XX_CP_RESOURCE_TBL_DBG_DATA, 0x04100}, 1316 { "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, 1317 REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x00200}, 1318 { "CP_LPAC_ROQ", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR, 1319 REG_A7XX_CP_LPAC_ROQ_DBG_DATA, 0x00200}, 1320 { "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR, 1321 REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x08000}, 1322 { "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR, 1323 REG_A7XX_CP_SQE_AC_STAT_DATA, 0x00040}, 1324 { "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR, 1325 REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x00040}, 1326 { "CP_AQE_ROQ_0", REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0, 1327 REG_A7XX_CP_AQE_ROQ_DBG_DATA_0, 0x00100}, 1328 { "CP_AQE_ROQ_1", REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1, 1329 REG_A7XX_CP_AQE_ROQ_DBG_DATA_1, 0x00100}, 1330 { "CP_AQE_UCODE_DBG_0", REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0, 1331 REG_A7XX_CP_AQE_UCODE_DBG_DATA_0, 0x08000}, 1332 { "CP_AQE_UCODE_DBG_1", REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1, 1333 REG_A7XX_CP_AQE_UCODE_DBG_DATA_1, 0x08000}, 1334 { "CP_AQE_STAT_0", REG_A7XX_CP_AQE_STAT_ADDR_0, 1335 REG_A7XX_CP_AQE_STAT_DATA_0, 0x00040}, 1336 { "CP_AQE_STAT_1", REG_A7XX_CP_AQE_STAT_ADDR_1, 1337 REG_A7XX_CP_AQE_STAT_DATA_1, 0x00040}, 1338 }; 1339 1340 static struct gen7_reg_list gen7_9_0_reg_list[] = { 1341 { gen7_9_0_gpu_registers, NULL}, 1342 { gen7_9_0_cx_misc_registers, NULL}, 1343 { gen7_9_0_cx_dbgc_registers, NULL}, 1344 { gen7_9_0_dbgc_registers, NULL}, 1345 { NULL, NULL}, 1346 }; 1347 1348 static const u32 gen7_9_0_cpr_registers[] = { 1349 0x26800, 0x26805, 0x26808, 0x2680d, 0x26814, 0x26815, 0x2681c, 0x2681c, 1350 0x26820, 0x26839, 0x26840, 0x26841, 0x26848, 0x26849, 0x26850, 0x26851, 1351 0x26880, 0x268a1, 0x26980, 0x269b0, 0x269c0, 0x269c8, 0x269e0, 0x269ee, 1352 0x269fb, 0x269ff, 0x26a02, 0x26a07, 0x26a09, 0x26a0b, 0x26a10, 0x26b0f, 1353 0x27440, 0x27441, 0x27444, 0x27444, 0x27480, 0x274a2, 0x274ac, 0x274c4, 1354 UINT_MAX, UINT_MAX, 1355 }; 1356 static_assert(IS_ALIGNED(sizeof(gen7_9_0_cpr_registers), 8)); 1357 1358 static const u32 gen7_9_0_dpm_registers[] = { 1359 0x1aa00, 0x1aa06, 0x1aa09, 0x1aa0a, 0x1aa0c, 0x1aa0d, 0x1aa0f, 0x1aa12, 1360 0x1aa14, 0x1aa47, 0x1aa50, 0x1aa51, 1361 UINT_MAX, UINT_MAX, 1362 }; 1363 static_assert(IS_ALIGNED(sizeof(gen7_9_0_dpm_registers), 8)); 1364 1365 static const u32 gen7_9_0_dpm_leakage_registers[] = { 1366 0x21c00, 0x21c00, 0x21c08, 0x21c09, 0x21c0e, 0x21c0f, 0x21c4f, 0x21c50, 1367 0x21c52, 0x21c52, 0x21c54, 0x21c56, 0x21c58, 0x21c5a, 0x21c5c, 0x21c60, 1368 UINT_MAX, UINT_MAX, 1369 }; 1370 static_assert(IS_ALIGNED(sizeof(gen7_9_0_dpm_leakage_registers), 8)); 1371 1372 static const u32 gen7_9_0_gfx_gpu_acd_registers[] = { 1373 0x18c00, 0x18c16, 0x18c20, 0x18c2d, 0x18c30, 0x18c31, 0x18c35, 0x18c35, 1374 0x18c37, 0x18c37, 0x18c3a, 0x18c3a, 0x18c42, 0x18c42, 0x18c56, 0x18c58, 1375 0x18c5b, 0x18c5d, 0x18c5f, 0x18c62, 1376 UINT_MAX, UINT_MAX, 1377 }; 1378 static_assert(IS_ALIGNED(sizeof(gen7_9_0_gfx_gpu_acd_registers), 8)); 1379 1380 static const u32 gen7_9_0_gpucc_registers[] = { 1381 0x24000, 0x2400f, 0x24400, 0x2440f, 0x24800, 0x24805, 0x24c00, 0x24cff, 1382 0x25400, 0x25404, 0x25800, 0x25804, 0x25c00, 0x25c04, 0x26000, 0x26004, 1383 0x26400, 0x26405, 0x26414, 0x2641d, 0x2642a, 0x26430, 0x26432, 0x26434, 1384 0x26441, 0x2644b, 0x2644d, 0x26463, 0x26466, 0x26468, 0x26478, 0x2647a, 1385 0x26489, 0x2648a, 0x2649c, 0x2649e, 0x264a0, 0x264a6, 0x264c5, 0x264c7, 1386 0x264d6, 0x264d8, 0x264e8, 0x264e9, 0x264f9, 0x264fc, 0x2650b, 0x2650b, 1387 0x2651c, 0x2651e, 0x26540, 0x2654e, 0x26554, 0x26573, 0x26576, 0x2657a, 1388 UINT_MAX, UINT_MAX, 1389 1390 }; 1391 static_assert(IS_ALIGNED(sizeof(gen7_9_0_gpucc_registers), 8)); 1392 1393 static const u32 gen7_9_0_isense_registers[] = { 1394 0x22c3a, 0x22c3c, 0x22c41, 0x22c41, 0x22c46, 0x22c47, 0x22c4c, 0x22c4c, 1395 0x22c51, 0x22c51, 0x22c56, 0x22c56, 0x22c5b, 0x22c5b, 0x22c60, 0x22c60, 1396 0x22c65, 0x22c65, 0x22c6a, 0x22c70, 0x22c75, 0x22c75, 0x22c7a, 0x22c7a, 1397 0x22c7f, 0x22c7f, 0x22c84, 0x22c85, 0x22c8a, 0x22c8a, 0x22c8f, 0x22c8f, 1398 0x23000, 0x23009, 0x2300e, 0x2300e, 0x23013, 0x23013, 0x23018, 0x23018, 1399 0x2301d, 0x2301d, 0x23022, 0x23022, 0x23027, 0x23032, 0x23037, 0x23037, 1400 0x2303c, 0x2303c, 0x23041, 0x23041, 0x23046, 0x23046, 0x2304b, 0x2304b, 1401 0x23050, 0x23050, 0x23055, 0x23055, 0x2305a, 0x2305a, 0x2305f, 0x2305f, 1402 0x23064, 0x23064, 0x23069, 0x2306a, 0x2306f, 0x2306f, 0x23074, 0x23075, 1403 0x2307a, 0x2307e, 0x23083, 0x23083, 0x23088, 0x23088, 0x2308d, 0x2308d, 1404 0x23092, 0x23092, 0x230e2, 0x230e2, 1405 UINT_MAX, UINT_MAX, 1406 }; 1407 static_assert(IS_ALIGNED(sizeof(gen7_9_0_isense_registers), 8)); 1408 1409 static const u32 gen7_9_0_rscc_registers[] = { 1410 0x14000, 0x14036, 0x14040, 0x14047, 0x14080, 0x14084, 0x14089, 0x1408c, 1411 0x14091, 0x14094, 0x14099, 0x1409c, 0x140a1, 0x140a4, 0x140a9, 0x140ac, 1412 0x14100, 0x14104, 0x14114, 0x14119, 0x14124, 0x14132, 0x14154, 0x1416b, 1413 0x14340, 0x14342, 0x14344, 0x1437c, 0x143f0, 0x143f8, 0x143fa, 0x143fe, 1414 0x14400, 0x14404, 0x14406, 0x1440a, 0x1440c, 0x14410, 0x14412, 0x14416, 1415 0x14418, 0x1441c, 0x1441e, 0x14422, 0x14424, 0x14424, 0x14498, 0x144a0, 1416 0x144a2, 0x144a6, 0x144a8, 0x144ac, 0x144ae, 0x144b2, 0x144b4, 0x144b8, 1417 0x144ba, 0x144be, 0x144c0, 0x144c4, 0x144c6, 0x144ca, 0x144cc, 0x144cc, 1418 0x14540, 0x14548, 0x1454a, 0x1454e, 0x14550, 0x14554, 0x14556, 0x1455a, 1419 0x1455c, 0x14560, 0x14562, 0x14566, 0x14568, 0x1456c, 0x1456e, 0x14572, 1420 0x14574, 0x14574, 0x145e8, 0x145f0, 0x145f2, 0x145f6, 0x145f8, 0x145fc, 1421 0x145fe, 0x14602, 0x14604, 0x14608, 0x1460a, 0x1460e, 0x14610, 0x14614, 1422 0x14616, 0x1461a, 0x1461c, 0x1461c, 0x14690, 0x14698, 0x1469a, 0x1469e, 1423 0x146a0, 0x146a4, 0x146a6, 0x146aa, 0x146ac, 0x146b0, 0x146b2, 0x146b6, 1424 0x146b8, 0x146bc, 0x146be, 0x146c2, 0x146c4, 0x146c4, 0x14738, 0x14740, 1425 0x14742, 0x14746, 0x14748, 0x1474c, 0x1474e, 0x14752, 0x14754, 0x14758, 1426 0x1475a, 0x1475e, 0x14760, 0x14764, 0x14766, 0x1476a, 0x1476c, 0x1476c, 1427 0x147e0, 0x147e8, 0x147ea, 0x147ee, 0x147f0, 0x147f4, 0x147f6, 0x147fa, 1428 0x147fc, 0x14800, 0x14802, 0x14806, 0x14808, 0x1480c, 0x1480e, 0x14812, 1429 0x14814, 0x14814, 0x14888, 0x14890, 0x14892, 0x14896, 0x14898, 0x1489c, 1430 0x1489e, 0x148a2, 0x148a4, 0x148a8, 0x148aa, 0x148ae, 0x148b0, 0x148b4, 1431 0x148b6, 0x148ba, 0x148bc, 0x148bc, 0x14930, 0x14938, 0x1493a, 0x1493e, 1432 0x14940, 0x14944, 0x14946, 0x1494a, 0x1494c, 0x14950, 0x14952, 0x14956, 1433 0x14958, 0x1495c, 0x1495e, 0x14962, 0x14964, 0x14964, 1434 UINT_MAX, UINT_MAX, 1435 }; 1436 static_assert(IS_ALIGNED(sizeof(gen7_9_0_rscc_registers), 8)); 1437 1438 static const u32 *gen7_9_0_external_core_regs[] = { 1439 gen7_9_0_gpucc_registers, 1440 gen7_9_0_gxclkctl_registers, 1441 gen7_9_0_cpr_registers, 1442 gen7_9_0_dpm_registers, 1443 gen7_9_0_dpm_leakage_registers, 1444 gen7_9_0_gfx_gpu_acd_registers, 1445 }; 1446 #endif /*_ADRENO_GEN7_9_0_SNAPSHOT_H */ 1447