1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 /* Copyright(c) 2020 Intel Corporation. All rights reserved. */
3 #include <linux/debugfs.h>
4 #include <linux/delay.h>
5 #include <linux/init.h>
6 #include <linux/interrupt.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 #include <linux/random.h>
10 #include <linux/slab.h>
11 #include <linux/ntb.h>
12 #include <linux/log2.h>
13
14 #include "ntb_hw_intel.h"
15 #include "ntb_hw_gen1.h"
16 #include "ntb_hw_gen3.h"
17 #include "ntb_hw_gen4.h"
18
19 static int gen4_poll_link(struct intel_ntb_dev *ndev);
20 static int gen4_link_is_up(struct intel_ntb_dev *ndev);
21
22 static const struct intel_ntb_reg gen4_reg = {
23 .poll_link = gen4_poll_link,
24 .link_is_up = gen4_link_is_up,
25 .db_ioread = gen3_db_ioread,
26 .db_iowrite = gen3_db_iowrite,
27 .db_size = sizeof(u32),
28 .ntb_ctl = GEN4_NTBCNTL_OFFSET,
29 .mw_bar = {2, 4},
30 };
31
32 static const struct intel_ntb_alt_reg gen4_pri_reg = {
33 .db_clear = GEN4_IM_INT_STATUS_OFFSET,
34 .db_mask = GEN4_IM_INT_DISABLE_OFFSET,
35 .spad = GEN4_IM_SPAD_OFFSET,
36 };
37
38 static const struct intel_ntb_xlat_reg gen4_sec_xlat = {
39 .bar2_limit = GEN4_IM23XLMT_OFFSET,
40 .bar2_xlat = GEN4_IM23XBASE_OFFSET,
41 .bar2_idx = GEN4_IM23XBASEIDX_OFFSET,
42 };
43
44 static const struct intel_ntb_alt_reg gen4_b2b_reg = {
45 .db_bell = GEN4_IM_DOORBELL_OFFSET,
46 .spad = GEN4_EM_SPAD_OFFSET,
47 };
48
get_ppd0(struct pci_dev * pdev)49 static u64 get_ppd0(struct pci_dev *pdev)
50 {
51 if (pdev_is_gen4(pdev) || pdev_is_gen5(pdev))
52 return GEN4_PPD0_OFFSET;
53 else if (pdev_is_gen6(pdev))
54 return GEN6_PPD0_OFFSET;
55
56 return ULLONG_MAX;
57 }
58
gen4_poll_link(struct intel_ntb_dev * ndev)59 static int gen4_poll_link(struct intel_ntb_dev *ndev)
60 {
61 u16 reg_val;
62
63 /*
64 * We need to write to DLLSCS bit in the SLOTSTS before we
65 * can clear the hardware link interrupt on ICX NTB.
66 */
67 iowrite16(GEN4_SLOTSTS_DLLSCS, ndev->self_mmio + GEN4_SLOTSTS);
68 ndev->reg->db_iowrite(ndev->db_link_mask,
69 ndev->self_mmio +
70 ndev->self_reg->db_clear);
71
72 reg_val = ioread16(ndev->self_mmio + GEN4_LINK_STATUS_OFFSET);
73 if (reg_val == ndev->lnk_sta)
74 return 0;
75
76 ndev->lnk_sta = reg_val;
77
78 return 1;
79 }
80
gen4_link_is_up(struct intel_ntb_dev * ndev)81 static int gen4_link_is_up(struct intel_ntb_dev *ndev)
82 {
83 return NTB_LNK_STA_ACTIVE(ndev->lnk_sta);
84 }
85
gen4_init_isr(struct intel_ntb_dev * ndev)86 static int gen4_init_isr(struct intel_ntb_dev *ndev)
87 {
88 int i;
89
90 /*
91 * The MSIX vectors and the interrupt status bits are not lined up
92 * on Gen3 (Skylake) and Gen4. By default the link status bit is bit
93 * 32, however it is by default MSIX vector0. We need to fixup to
94 * line them up. The vectors at reset is 1-32,0. We need to reprogram
95 * to 0-32.
96 */
97 for (i = 0; i < GEN4_DB_MSIX_VECTOR_COUNT; i++)
98 iowrite8(i, ndev->self_mmio + GEN4_INTVEC_OFFSET + i);
99
100 return ndev_init_isr(ndev, GEN4_DB_MSIX_VECTOR_COUNT,
101 GEN4_DB_MSIX_VECTOR_COUNT,
102 GEN4_DB_MSIX_VECTOR_SHIFT,
103 GEN4_DB_TOTAL_SHIFT);
104 }
105
gen4_setup_b2b_mw(struct intel_ntb_dev * ndev,const struct intel_b2b_addr * addr,const struct intel_b2b_addr * peer_addr)106 static int gen4_setup_b2b_mw(struct intel_ntb_dev *ndev,
107 const struct intel_b2b_addr *addr,
108 const struct intel_b2b_addr *peer_addr)
109 {
110 struct pci_dev *pdev;
111 void __iomem *mmio;
112 phys_addr_t bar_addr;
113
114 pdev = ndev->ntb.pdev;
115 mmio = ndev->self_mmio;
116
117 /* setup incoming bar limits == base addrs (zero length windows) */
118 bar_addr = addr->bar2_addr64;
119 iowrite64(bar_addr, mmio + GEN4_IM23XLMT_OFFSET);
120 bar_addr = ioread64(mmio + GEN4_IM23XLMT_OFFSET);
121 dev_dbg(&pdev->dev, "IM23XLMT %#018llx\n", bar_addr);
122
123 bar_addr = addr->bar4_addr64;
124 iowrite64(bar_addr, mmio + GEN4_IM45XLMT_OFFSET);
125 bar_addr = ioread64(mmio + GEN4_IM45XLMT_OFFSET);
126 dev_dbg(&pdev->dev, "IM45XLMT %#018llx\n", bar_addr);
127
128 /* zero incoming translation addrs */
129 iowrite64(0, mmio + GEN4_IM23XBASE_OFFSET);
130 iowrite64(0, mmio + GEN4_IM45XBASE_OFFSET);
131
132 ndev->peer_mmio = ndev->self_mmio;
133
134 return 0;
135 }
136
gen4_init_ntb(struct intel_ntb_dev * ndev)137 static int gen4_init_ntb(struct intel_ntb_dev *ndev)
138 {
139 int rc;
140
141
142 ndev->mw_count = XEON_MW_COUNT;
143 ndev->spad_count = GEN4_SPAD_COUNT;
144 ndev->db_count = GEN4_DB_COUNT;
145 ndev->db_link_mask = GEN4_DB_LINK_BIT;
146
147 ndev->self_reg = &gen4_pri_reg;
148 ndev->xlat_reg = &gen4_sec_xlat;
149 ndev->peer_reg = &gen4_b2b_reg;
150
151 if (ndev->ntb.topo == NTB_TOPO_B2B_USD)
152 rc = gen4_setup_b2b_mw(ndev, &xeon_b2b_dsd_addr,
153 &xeon_b2b_usd_addr);
154 else
155 rc = gen4_setup_b2b_mw(ndev, &xeon_b2b_usd_addr,
156 &xeon_b2b_dsd_addr);
157 if (rc)
158 return rc;
159
160 ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
161
162 ndev->reg->db_iowrite(ndev->db_valid_mask,
163 ndev->self_mmio +
164 ndev->self_reg->db_mask);
165
166 return 0;
167 }
168
gen4_ppd_topo(struct intel_ntb_dev * ndev,u32 ppd)169 static enum ntb_topo gen4_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
170 {
171 switch (ppd & GEN4_PPD_TOPO_MASK) {
172 case GEN4_PPD_TOPO_B2B_USD:
173 return NTB_TOPO_B2B_USD;
174 case GEN4_PPD_TOPO_B2B_DSD:
175 return NTB_TOPO_B2B_DSD;
176 }
177
178 return NTB_TOPO_NONE;
179 }
180
spr_ppd_topo(struct intel_ntb_dev * ndev,u32 ppd)181 static enum ntb_topo spr_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
182 {
183 switch (ppd & SPR_PPD_TOPO_MASK) {
184 case SPR_PPD_TOPO_B2B_USD:
185 return NTB_TOPO_B2B_USD;
186 case SPR_PPD_TOPO_B2B_DSD:
187 return NTB_TOPO_B2B_DSD;
188 }
189
190 return NTB_TOPO_NONE;
191 }
192
gen4_init_dev(struct intel_ntb_dev * ndev)193 int gen4_init_dev(struct intel_ntb_dev *ndev)
194 {
195 struct pci_dev *pdev = ndev->ntb.pdev;
196 u32 ppd1;
197 u16 lnkctl;
198 int rc;
199
200 ndev->reg = &gen4_reg;
201
202 if (pdev_is_ICX(pdev)) {
203 ndev->hwerr_flags |= NTB_HWERR_BAR_ALIGN;
204 ndev->hwerr_flags |= NTB_HWERR_LTR_BAD;
205 }
206
207 ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET);
208 if (pdev_is_ICX(pdev))
209 ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1);
210 else if (pdev_is_SPR(pdev) || pdev_is_gen5(pdev) || pdev_is_gen6(pdev))
211 ndev->ntb.topo = spr_ppd_topo(ndev, ppd1);
212 dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd1,
213 ntb_topo_string(ndev->ntb.topo));
214 if (ndev->ntb.topo == NTB_TOPO_NONE)
215 return -EINVAL;
216
217 rc = gen4_init_ntb(ndev);
218 if (rc)
219 return rc;
220
221 /* init link setup */
222 lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
223 lnkctl |= GEN4_LINK_CTRL_LINK_DISABLE;
224 iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
225
226 return gen4_init_isr(ndev);
227 }
228
ndev_ntb4_debugfs_read(struct file * filp,char __user * ubuf,size_t count,loff_t * offp)229 ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
230 size_t count, loff_t *offp)
231 {
232 struct intel_ntb_dev *ndev;
233 void __iomem *mmio;
234 char *buf;
235 size_t buf_size;
236 ssize_t ret, off;
237 union { u64 v64; u32 v32; u16 v16; } u;
238
239 ndev = filp->private_data;
240 mmio = ndev->self_mmio;
241
242 buf_size = min(count, 0x800ul);
243
244 buf = kmalloc(buf_size, GFP_KERNEL);
245 if (!buf)
246 return -ENOMEM;
247
248 off = 0;
249
250 off += scnprintf(buf + off, buf_size - off,
251 "NTB Device Information:\n");
252
253 off += scnprintf(buf + off, buf_size - off,
254 "Connection Topology -\t%s\n",
255 ntb_topo_string(ndev->ntb.topo));
256
257 off += scnprintf(buf + off, buf_size - off,
258 "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl);
259 off += scnprintf(buf + off, buf_size - off,
260 "LNK STA (cached) -\t\t%#06x\n", ndev->lnk_sta);
261
262 if (!ndev->reg->link_is_up(ndev))
263 off += scnprintf(buf + off, buf_size - off,
264 "Link Status -\t\tDown\n");
265 else {
266 off += scnprintf(buf + off, buf_size - off,
267 "Link Status -\t\tUp\n");
268 off += scnprintf(buf + off, buf_size - off,
269 "Link Speed -\t\tPCI-E Gen %u\n",
270 NTB_LNK_STA_SPEED(ndev->lnk_sta));
271 off += scnprintf(buf + off, buf_size - off,
272 "Link Width -\t\tx%u\n",
273 NTB_LNK_STA_WIDTH(ndev->lnk_sta));
274 }
275
276 off += scnprintf(buf + off, buf_size - off,
277 "Memory Window Count -\t%u\n", ndev->mw_count);
278 off += scnprintf(buf + off, buf_size - off,
279 "Scratchpad Count -\t%u\n", ndev->spad_count);
280 off += scnprintf(buf + off, buf_size - off,
281 "Doorbell Count -\t%u\n", ndev->db_count);
282 off += scnprintf(buf + off, buf_size - off,
283 "Doorbell Vector Count -\t%u\n", ndev->db_vec_count);
284 off += scnprintf(buf + off, buf_size - off,
285 "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift);
286
287 off += scnprintf(buf + off, buf_size - off,
288 "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask);
289 off += scnprintf(buf + off, buf_size - off,
290 "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask);
291 off += scnprintf(buf + off, buf_size - off,
292 "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask);
293
294 u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask);
295 off += scnprintf(buf + off, buf_size - off,
296 "Doorbell Mask -\t\t%#llx\n", u.v64);
297
298 off += scnprintf(buf + off, buf_size - off,
299 "\nNTB Incoming XLAT:\n");
300
301 u.v64 = ioread64(mmio + GEN4_IM23XBASE_OFFSET);
302 off += scnprintf(buf + off, buf_size - off,
303 "IM23XBASE -\t\t%#018llx\n", u.v64);
304
305 u.v64 = ioread64(mmio + GEN4_IM45XBASE_OFFSET);
306 off += scnprintf(buf + off, buf_size - off,
307 "IM45XBASE -\t\t%#018llx\n", u.v64);
308
309 u.v64 = ioread64(mmio + GEN4_IM23XLMT_OFFSET);
310 off += scnprintf(buf + off, buf_size - off,
311 "IM23XLMT -\t\t\t%#018llx\n", u.v64);
312
313 u.v64 = ioread64(mmio + GEN4_IM45XLMT_OFFSET);
314 off += scnprintf(buf + off, buf_size - off,
315 "IM45XLMT -\t\t\t%#018llx\n", u.v64);
316
317 off += scnprintf(buf + off, buf_size - off,
318 "\nNTB Statistics:\n");
319
320 off += scnprintf(buf + off, buf_size - off,
321 "\nNTB Hardware Errors:\n");
322
323 if (!pci_read_config_word(ndev->ntb.pdev,
324 GEN4_DEVSTS_OFFSET, &u.v16))
325 off += scnprintf(buf + off, buf_size - off,
326 "DEVSTS -\t\t%#06x\n", u.v16);
327
328 u.v16 = ioread16(mmio + GEN4_LINK_STATUS_OFFSET);
329 off += scnprintf(buf + off, buf_size - off,
330 "LNKSTS -\t\t%#06x\n", u.v16);
331
332 if (!pci_read_config_dword(ndev->ntb.pdev,
333 GEN4_UNCERRSTS_OFFSET, &u.v32))
334 off += scnprintf(buf + off, buf_size - off,
335 "UNCERRSTS -\t\t%#06x\n", u.v32);
336
337 if (!pci_read_config_dword(ndev->ntb.pdev,
338 GEN4_CORERRSTS_OFFSET, &u.v32))
339 off += scnprintf(buf + off, buf_size - off,
340 "CORERRSTS -\t\t%#06x\n", u.v32);
341
342 ret = simple_read_from_buffer(ubuf, count, offp, buf, off);
343 kfree(buf);
344 return ret;
345 }
346
intel_ntb4_mw_set_trans(struct ntb_dev * ntb,int pidx,int idx,dma_addr_t addr,resource_size_t size)347 static int intel_ntb4_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
348 dma_addr_t addr, resource_size_t size)
349 {
350 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
351 unsigned long xlat_reg, limit_reg, idx_reg;
352 unsigned short base_idx, reg_val16;
353 resource_size_t bar_size, mw_size;
354 void __iomem *mmio;
355 u64 base, limit, reg_val;
356 int bar;
357
358 if (pidx != NTB_DEF_PEER_IDX)
359 return -EINVAL;
360
361 if (idx >= ndev->b2b_idx && !ndev->b2b_off)
362 idx += 1;
363
364 bar = ndev_mw_to_bar(ndev, idx);
365 if (bar < 0)
366 return bar;
367
368 bar_size = pci_resource_len(ndev->ntb.pdev, bar);
369
370 if (idx == ndev->b2b_idx)
371 mw_size = bar_size - ndev->b2b_off;
372 else
373 mw_size = bar_size;
374
375 if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) {
376 /* hardware requires that addr is aligned to bar size */
377 if (addr & (bar_size - 1))
378 return -EINVAL;
379 } else {
380 if (addr & (PAGE_SIZE - 1))
381 return -EINVAL;
382 }
383
384 /* make sure the range fits in the usable mw size */
385 if (size > mw_size)
386 return -EINVAL;
387
388 mmio = ndev->self_mmio;
389 xlat_reg = ndev->xlat_reg->bar2_xlat + (idx * 0x10);
390 limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10);
391 base = pci_resource_start(ndev->ntb.pdev, bar);
392
393 /* Set the limit if supported, if size is not mw_size */
394 if (limit_reg && size != mw_size) {
395 limit = base + size;
396 base_idx = __ilog2_u64(size);
397 } else {
398 limit = base + mw_size;
399 base_idx = __ilog2_u64(mw_size);
400 }
401
402
403 /* set and verify setting the translation address */
404 iowrite64(addr, mmio + xlat_reg);
405 reg_val = ioread64(mmio + xlat_reg);
406 if (reg_val != addr) {
407 iowrite64(0, mmio + xlat_reg);
408 return -EIO;
409 }
410
411 dev_dbg(&ntb->pdev->dev, "BAR %d IMXBASE: %#Lx\n", bar, reg_val);
412
413 /* set and verify setting the limit */
414 iowrite64(limit, mmio + limit_reg);
415 reg_val = ioread64(mmio + limit_reg);
416 if (reg_val != limit) {
417 iowrite64(base, mmio + limit_reg);
418 iowrite64(0, mmio + xlat_reg);
419 return -EIO;
420 }
421
422 dev_dbg(&ntb->pdev->dev, "BAR %d IMXLMT: %#Lx\n", bar, reg_val);
423
424 if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) {
425 idx_reg = ndev->xlat_reg->bar2_idx + (idx * 0x2);
426 iowrite16(base_idx, mmio + idx_reg);
427 reg_val16 = ioread16(mmio + idx_reg);
428 if (reg_val16 != base_idx) {
429 iowrite64(base, mmio + limit_reg);
430 iowrite64(0, mmio + xlat_reg);
431 iowrite16(0, mmio + idx_reg);
432 return -EIO;
433 }
434 dev_dbg(&ntb->pdev->dev, "BAR %d IMBASEIDX: %#x\n", bar, reg_val16);
435 }
436
437
438 return 0;
439 }
440
intel_ntb4_link_enable(struct ntb_dev * ntb,enum ntb_speed max_speed,enum ntb_width max_width)441 static int intel_ntb4_link_enable(struct ntb_dev *ntb,
442 enum ntb_speed max_speed, enum ntb_width max_width)
443 {
444 struct intel_ntb_dev *ndev;
445 struct pci_dev *pdev;
446 u32 ntb_ctl, ppd0;
447 u16 lnkctl;
448
449 ndev = container_of(ntb, struct intel_ntb_dev, ntb);
450 pdev = ntb->pdev;
451
452 dev_dbg(&ntb->pdev->dev,
453 "Enabling link with max_speed %d max_width %d\n",
454 max_speed, max_width);
455
456 if (max_speed != NTB_SPEED_AUTO)
457 dev_dbg(&ntb->pdev->dev,
458 "ignoring max_speed %d\n", max_speed);
459 if (max_width != NTB_WIDTH_AUTO)
460 dev_dbg(&ntb->pdev->dev,
461 "ignoring max_width %d\n", max_width);
462
463 if (!(ndev->hwerr_flags & NTB_HWERR_LTR_BAD)) {
464 u32 ltr;
465
466 /* Setup active snoop LTR values */
467 ltr = NTB_LTR_ACTIVE_REQMNT | NTB_LTR_ACTIVE_VAL | NTB_LTR_ACTIVE_LATSCALE;
468 /* Setup active non-snoop values */
469 ltr = (ltr << NTB_LTR_NS_SHIFT) | ltr;
470 iowrite32(ltr, ndev->self_mmio + GEN4_LTR_ACTIVE_OFFSET);
471
472 /* Setup idle snoop LTR values */
473 ltr = NTB_LTR_IDLE_VAL | NTB_LTR_IDLE_LATSCALE | NTB_LTR_IDLE_REQMNT;
474 /* Setup idle non-snoop values */
475 ltr = (ltr << NTB_LTR_NS_SHIFT) | ltr;
476 iowrite32(ltr, ndev->self_mmio + GEN4_LTR_IDLE_OFFSET);
477
478 /* setup PCIe LTR to active */
479 iowrite8(NTB_LTR_SWSEL_ACTIVE, ndev->self_mmio + GEN4_LTR_SWSEL_OFFSET);
480 }
481
482 ntb_ctl = NTB_CTL_E2I_BAR23_SNOOP | NTB_CTL_I2E_BAR23_SNOOP;
483 ntb_ctl |= NTB_CTL_E2I_BAR45_SNOOP | NTB_CTL_I2E_BAR45_SNOOP;
484 iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl);
485
486 lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
487 lnkctl &= ~GEN4_LINK_CTRL_LINK_DISABLE;
488 iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
489
490 /* start link training in PPD0 */
491 ppd0 = ioread32(ndev->self_mmio + get_ppd0(pdev));
492 ppd0 |= GEN4_PPD_LINKTRN;
493 iowrite32(ppd0, ndev->self_mmio + get_ppd0(pdev));
494
495 /* make sure link training has started */
496 ppd0 = ioread32(ndev->self_mmio + get_ppd0(pdev));
497 if (!(ppd0 & GEN4_PPD_LINKTRN)) {
498 dev_warn(&ntb->pdev->dev, "Link is not training\n");
499 return -ENXIO;
500 }
501
502 ndev->dev_up = 1;
503
504 return 0;
505 }
506
intel_ntb4_link_disable(struct ntb_dev * ntb)507 static int intel_ntb4_link_disable(struct ntb_dev *ntb)
508 {
509 struct intel_ntb_dev *ndev;
510 u32 ntb_cntl;
511 u16 lnkctl;
512
513 ndev = container_of(ntb, struct intel_ntb_dev, ntb);
514
515 dev_dbg(&ntb->pdev->dev, "Disabling link\n");
516
517 /* clear the snoop bits */
518 ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
519 ntb_cntl &= ~(NTB_CTL_E2I_BAR23_SNOOP | NTB_CTL_I2E_BAR23_SNOOP);
520 ntb_cntl &= ~(NTB_CTL_E2I_BAR45_SNOOP | NTB_CTL_I2E_BAR45_SNOOP);
521 iowrite32(ntb_cntl, ndev->self_mmio + ndev->reg->ntb_ctl);
522
523 lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
524 lnkctl |= GEN4_LINK_CTRL_LINK_DISABLE;
525 iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
526
527 /* set LTR to idle */
528 if (!(ndev->hwerr_flags & NTB_HWERR_LTR_BAD))
529 iowrite8(NTB_LTR_SWSEL_IDLE, ndev->self_mmio + GEN4_LTR_SWSEL_OFFSET);
530
531 ndev->dev_up = 0;
532
533 return 0;
534 }
535
intel_ntb4_mw_get_align(struct ntb_dev * ntb,int pidx,int idx,resource_size_t * addr_align,resource_size_t * size_align,resource_size_t * size_max)536 static int intel_ntb4_mw_get_align(struct ntb_dev *ntb, int pidx, int idx,
537 resource_size_t *addr_align,
538 resource_size_t *size_align,
539 resource_size_t *size_max)
540 {
541 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
542 resource_size_t bar_size, mw_size;
543 int bar;
544
545 if (pidx != NTB_DEF_PEER_IDX)
546 return -EINVAL;
547
548 if (idx >= ndev->b2b_idx && !ndev->b2b_off)
549 idx += 1;
550
551 bar = ndev_mw_to_bar(ndev, idx);
552 if (bar < 0)
553 return bar;
554
555 bar_size = pci_resource_len(ndev->ntb.pdev, bar);
556
557 if (idx == ndev->b2b_idx)
558 mw_size = bar_size - ndev->b2b_off;
559 else
560 mw_size = bar_size;
561
562 if (addr_align) {
563 if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN)
564 *addr_align = pci_resource_len(ndev->ntb.pdev, bar);
565 else
566 *addr_align = PAGE_SIZE;
567 }
568
569 if (size_align)
570 *size_align = 1;
571
572 if (size_max)
573 *size_max = mw_size;
574
575 return 0;
576 }
577
578 const struct ntb_dev_ops intel_ntb4_ops = {
579 .mw_count = intel_ntb_mw_count,
580 .mw_get_align = intel_ntb4_mw_get_align,
581 .mw_set_trans = intel_ntb4_mw_set_trans,
582 .peer_mw_count = intel_ntb_peer_mw_count,
583 .peer_mw_get_addr = intel_ntb_peer_mw_get_addr,
584 .link_is_up = intel_ntb_link_is_up,
585 .link_enable = intel_ntb4_link_enable,
586 .link_disable = intel_ntb4_link_disable,
587 .db_valid_mask = intel_ntb_db_valid_mask,
588 .db_vector_count = intel_ntb_db_vector_count,
589 .db_vector_mask = intel_ntb_db_vector_mask,
590 .db_read = intel_ntb3_db_read,
591 .db_clear = intel_ntb3_db_clear,
592 .db_set_mask = intel_ntb_db_set_mask,
593 .db_clear_mask = intel_ntb_db_clear_mask,
594 .peer_db_addr = intel_ntb3_peer_db_addr,
595 .peer_db_set = intel_ntb3_peer_db_set,
596 .spad_is_unsafe = intel_ntb_spad_is_unsafe,
597 .spad_count = intel_ntb_spad_count,
598 .spad_read = intel_ntb_spad_read,
599 .spad_write = intel_ntb_spad_write,
600 .peer_spad_addr = intel_ntb_peer_spad_addr,
601 .peer_spad_read = intel_ntb_peer_spad_read,
602 .peer_spad_write = intel_ntb_peer_spad_write,
603 };
604
605