1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/display/drm_dsc_helper.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_fixed.h> 31 #include <drm/drm_mipi_dsi.h> 32 #include <drm/drm_probe_helper.h> 33 34 #include "i915_reg.h" 35 #include "i915_utils.h" 36 #include "icl_dsi.h" 37 #include "icl_dsi_regs.h" 38 #include "intel_atomic.h" 39 #include "intel_backlight.h" 40 #include "intel_backlight_regs.h" 41 #include "intel_combo_phy.h" 42 #include "intel_combo_phy_regs.h" 43 #include "intel_connector.h" 44 #include "intel_crtc.h" 45 #include "intel_ddi.h" 46 #include "intel_de.h" 47 #include "intel_dsi.h" 48 #include "intel_dsi_vbt.h" 49 #include "intel_panel.h" 50 #include "intel_pfit.h" 51 #include "intel_vdsc.h" 52 #include "intel_vdsc_regs.h" 53 #include "skl_scaler.h" 54 #include "skl_universal_plane.h" 55 56 static int header_credits_available(struct intel_display *display, 57 enum transcoder dsi_trans) 58 { 59 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 60 >> FREE_HEADER_CREDIT_SHIFT; 61 } 62 63 static int payload_credits_available(struct intel_display *display, 64 enum transcoder dsi_trans) 65 { 66 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 67 >> FREE_PLOAD_CREDIT_SHIFT; 68 } 69 70 static bool wait_for_header_credits(struct intel_display *display, 71 enum transcoder dsi_trans, int hdr_credit) 72 { 73 if (wait_for_us(header_credits_available(display, dsi_trans) >= 74 hdr_credit, 100)) { 75 drm_err(display->drm, "DSI header credits not released\n"); 76 return false; 77 } 78 79 return true; 80 } 81 82 static bool wait_for_payload_credits(struct intel_display *display, 83 enum transcoder dsi_trans, int payld_credit) 84 { 85 if (wait_for_us(payload_credits_available(display, dsi_trans) >= 86 payld_credit, 100)) { 87 drm_err(display->drm, "DSI payload credits not released\n"); 88 return false; 89 } 90 91 return true; 92 } 93 94 static enum transcoder dsi_port_to_transcoder(enum port port) 95 { 96 if (port == PORT_A) 97 return TRANSCODER_DSI_0; 98 else 99 return TRANSCODER_DSI_1; 100 } 101 102 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 103 { 104 struct intel_display *display = to_intel_display(encoder); 105 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 106 struct mipi_dsi_device *dsi; 107 enum port port; 108 enum transcoder dsi_trans; 109 int ret; 110 111 /* wait for header/payload credits to be released */ 112 for_each_dsi_port(port, intel_dsi->ports) { 113 dsi_trans = dsi_port_to_transcoder(port); 114 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT); 115 wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT); 116 } 117 118 /* send nop DCS command */ 119 for_each_dsi_port(port, intel_dsi->ports) { 120 dsi = intel_dsi->dsi_hosts[port]->device; 121 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 122 dsi->channel = 0; 123 ret = mipi_dsi_dcs_nop(dsi); 124 if (ret < 0) 125 drm_err(display->drm, 126 "error sending DCS NOP command\n"); 127 } 128 129 /* wait for header credits to be released */ 130 for_each_dsi_port(port, intel_dsi->ports) { 131 dsi_trans = dsi_port_to_transcoder(port); 132 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT); 133 } 134 135 /* wait for LP TX in progress bit to be cleared */ 136 for_each_dsi_port(port, intel_dsi->ports) { 137 dsi_trans = dsi_port_to_transcoder(port); 138 if (wait_for_us(!(intel_de_read(display, DSI_LP_MSG(dsi_trans)) & 139 LPTX_IN_PROGRESS), 20)) 140 drm_err(display->drm, "LPTX bit not cleared\n"); 141 } 142 } 143 144 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 145 const struct mipi_dsi_packet *packet) 146 { 147 struct intel_dsi *intel_dsi = host->intel_dsi; 148 struct intel_display *display = to_intel_display(&intel_dsi->base); 149 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 150 const u8 *data = packet->payload; 151 u32 len = packet->payload_length; 152 int i, j; 153 154 /* payload queue can accept *256 bytes*, check limit */ 155 if (len > MAX_PLOAD_CREDIT * 4) { 156 drm_err(display->drm, "payload size exceeds max queue limit\n"); 157 return -EINVAL; 158 } 159 160 for (i = 0; i < len; i += 4) { 161 u32 tmp = 0; 162 163 if (!wait_for_payload_credits(display, dsi_trans, 1)) 164 return -EBUSY; 165 166 for (j = 0; j < min_t(u32, len - i, 4); j++) 167 tmp |= *data++ << 8 * j; 168 169 intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp); 170 } 171 172 return 0; 173 } 174 175 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 176 const struct mipi_dsi_packet *packet, 177 bool enable_lpdt) 178 { 179 struct intel_dsi *intel_dsi = host->intel_dsi; 180 struct intel_display *display = to_intel_display(&intel_dsi->base); 181 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 182 u32 tmp; 183 184 if (!wait_for_header_credits(display, dsi_trans, 1)) 185 return -EBUSY; 186 187 tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans)); 188 189 if (packet->payload) 190 tmp |= PAYLOAD_PRESENT; 191 else 192 tmp &= ~PAYLOAD_PRESENT; 193 194 tmp &= ~VBLANK_FENCE; 195 196 if (enable_lpdt) 197 tmp |= LP_DATA_TRANSFER; 198 else 199 tmp &= ~LP_DATA_TRANSFER; 200 201 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 202 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 203 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 204 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 205 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 206 intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp); 207 208 return 0; 209 } 210 211 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 212 { 213 struct intel_display *display = to_intel_display(crtc_state); 214 u32 mode_flags; 215 enum port port; 216 217 mode_flags = crtc_state->mode_flags; 218 219 /* 220 * case 1 also covers dual link 221 * In case of dual link, frame update should be set on 222 * DSI_0 223 */ 224 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 225 port = PORT_A; 226 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 227 port = PORT_B; 228 else 229 return; 230 231 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0, 232 DSI_FRAME_UPDATE_REQUEST); 233 } 234 235 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 236 { 237 struct intel_display *display = to_intel_display(encoder); 238 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 239 enum phy phy; 240 u32 tmp, mask, val; 241 int lane; 242 243 for_each_dsi_phy(phy, intel_dsi->phys) { 244 /* 245 * Program voltage swing and pre-emphasis level values as per 246 * table in BSPEC under DDI buffer programming. 247 */ 248 mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK; 249 val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE | 250 RTERM_SELECT(0x6); 251 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 252 tmp &= ~mask; 253 tmp |= val; 254 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 255 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val); 256 257 mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 258 RCOMP_SCALAR_MASK; 259 val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) | 260 RCOMP_SCALAR(0x98); 261 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy)); 262 tmp &= ~mask; 263 tmp |= val; 264 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); 265 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val); 266 267 mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 268 CURSOR_COEFF_MASK; 269 val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) | 270 CURSOR_COEFF(0x3f); 271 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val); 272 273 /* Bspec: must not use GRP register for write */ 274 for (lane = 0; lane <= 3; lane++) 275 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy), 276 mask, val); 277 } 278 } 279 280 static void configure_dual_link_mode(struct intel_encoder *encoder, 281 const struct intel_crtc_state *pipe_config) 282 { 283 struct intel_display *display = to_intel_display(encoder); 284 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 285 i915_reg_t dss_ctl1_reg, dss_ctl2_reg; 286 u32 dss_ctl1; 287 288 /* FIXME: Move all DSS handling to intel_vdsc.c */ 289 if (DISPLAY_VER(display) >= 12) { 290 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 291 292 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); 293 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); 294 } else { 295 dss_ctl1_reg = DSS_CTL1; 296 dss_ctl2_reg = DSS_CTL2; 297 } 298 299 dss_ctl1 = intel_de_read(display, dss_ctl1_reg); 300 dss_ctl1 |= SPLITTER_ENABLE; 301 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 302 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 303 304 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 305 const struct drm_display_mode *adjusted_mode = 306 &pipe_config->hw.adjusted_mode; 307 u16 hactive = adjusted_mode->crtc_hdisplay; 308 u16 dl_buffer_depth; 309 310 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 311 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 312 313 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 314 drm_err(display->drm, 315 "DL buffer depth exceed max value\n"); 316 317 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 318 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 319 intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, 320 RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth)); 321 } else { 322 /* Interleave */ 323 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 324 } 325 326 intel_de_write(display, dss_ctl1_reg, dss_ctl1); 327 } 328 329 /* aka DSI 8X clock */ 330 static int afe_clk(struct intel_encoder *encoder, 331 const struct intel_crtc_state *crtc_state) 332 { 333 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 334 int bpp; 335 336 if (crtc_state->dsc.compression_enable) 337 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 338 else 339 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 340 341 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 342 } 343 344 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 345 const struct intel_crtc_state *crtc_state) 346 { 347 struct intel_display *display = to_intel_display(encoder); 348 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 349 enum port port; 350 int afe_clk_khz; 351 int theo_word_clk, act_word_clk; 352 u32 esc_clk_div_m, esc_clk_div_m_phy; 353 354 afe_clk_khz = afe_clk(encoder, crtc_state); 355 356 if (display->platform.alderlake_s || display->platform.alderlake_p) { 357 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 358 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 359 esc_clk_div_m = act_word_clk * 8; 360 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 361 } else { 362 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 363 } 364 365 for_each_dsi_port(port, intel_dsi->ports) { 366 intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port), 367 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 368 intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port)); 369 } 370 371 for_each_dsi_port(port, intel_dsi->ports) { 372 intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port), 373 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 374 intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port)); 375 } 376 377 if (display->platform.alderlake_s || display->platform.alderlake_p) { 378 for_each_dsi_port(port, intel_dsi->ports) { 379 intel_de_write(display, ADL_MIPIO_DW(port, 8), 380 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 381 intel_de_posting_read(display, ADL_MIPIO_DW(port, 8)); 382 } 383 } 384 } 385 386 static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi) 387 { 388 struct intel_display *display = to_intel_display(&intel_dsi->base); 389 enum port port; 390 391 for_each_dsi_port(port, intel_dsi->ports) { 392 drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]); 393 intel_dsi->io_wakeref[port] = 394 intel_display_power_get(display, 395 port == PORT_A ? 396 POWER_DOMAIN_PORT_DDI_IO_A : 397 POWER_DOMAIN_PORT_DDI_IO_B); 398 } 399 } 400 401 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 402 { 403 struct intel_display *display = to_intel_display(encoder); 404 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 405 enum port port; 406 407 for_each_dsi_port(port, intel_dsi->ports) 408 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), 409 0, COMBO_PHY_MODE_DSI); 410 411 get_dsi_io_power_domains(intel_dsi); 412 } 413 414 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 415 { 416 struct intel_display *display = to_intel_display(encoder); 417 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 418 enum phy phy; 419 420 for_each_dsi_phy(phy, intel_dsi->phys) 421 intel_combo_phy_power_up_lanes(display, phy, true, 422 intel_dsi->lane_count, false); 423 } 424 425 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 426 { 427 struct intel_display *display = to_intel_display(encoder); 428 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 429 enum phy phy; 430 u32 tmp; 431 int lane; 432 433 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 434 for_each_dsi_phy(phy, intel_dsi->phys) { 435 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), 436 LOADGEN_SELECT, 0); 437 for (lane = 0; lane <= 3; lane++) 438 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy), 439 LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0); 440 } 441 442 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 443 for_each_dsi_phy(phy, intel_dsi->phys) { 444 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), 445 FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5)); 446 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy)); 447 tmp &= ~FRC_LATENCY_OPTIM_MASK; 448 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 449 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); 450 451 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 452 if (display->platform.jasperlake || display->platform.elkhartlake || 453 (DISPLAY_VER(display) >= 12)) { 454 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), 455 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0)); 456 457 tmp = intel_de_read(display, 458 ICL_PORT_PCS_DW1_LN(0, phy)); 459 tmp &= ~LATENCY_OPTIM_MASK; 460 tmp |= LATENCY_OPTIM_VAL(0x1); 461 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), 462 tmp); 463 } 464 } 465 466 } 467 468 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 469 { 470 struct intel_display *display = to_intel_display(encoder); 471 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 472 u32 tmp; 473 enum phy phy; 474 475 /* clear common keeper enable bit */ 476 for_each_dsi_phy(phy, intel_dsi->phys) { 477 tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 478 tmp &= ~COMMON_KEEPER_EN; 479 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp); 480 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0); 481 } 482 483 /* 484 * Set SUS Clock Config bitfield to 11b 485 * Note: loadgen select program is done 486 * as part of lane phy sequence configuration 487 */ 488 for_each_dsi_phy(phy, intel_dsi->phys) 489 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0, 490 SUS_CLOCK_CONFIG); 491 492 /* Clear training enable to change swing values */ 493 for_each_dsi_phy(phy, intel_dsi->phys) { 494 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 495 tmp &= ~TX_TRAINING_EN; 496 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 497 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0); 498 } 499 500 /* Program swing and de-emphasis */ 501 dsi_program_swing_and_deemphasis(encoder); 502 503 /* Set training enable to trigger update */ 504 for_each_dsi_phy(phy, intel_dsi->phys) { 505 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 506 tmp |= TX_TRAINING_EN; 507 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 508 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN); 509 } 510 } 511 512 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 513 { 514 struct intel_display *display = to_intel_display(encoder); 515 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 516 enum port port; 517 518 for_each_dsi_port(port, intel_dsi->ports) { 519 intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE); 520 521 if (wait_for_us(!(intel_de_read(display, DDI_BUF_CTL(port)) & 522 DDI_BUF_IS_IDLE), 523 500)) 524 drm_err(display->drm, "DDI port:%c buffer idle\n", 525 port_name(port)); 526 } 527 } 528 529 static void 530 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 531 const struct intel_crtc_state *crtc_state) 532 { 533 struct intel_display *display = to_intel_display(encoder); 534 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 535 enum port port; 536 enum phy phy; 537 538 /* Program DPHY clock lanes timings */ 539 for_each_dsi_port(port, intel_dsi->ports) 540 intel_de_write(display, DPHY_CLK_TIMING_PARAM(port), 541 intel_dsi->dphy_reg); 542 543 /* Program DPHY data lanes timings */ 544 for_each_dsi_port(port, intel_dsi->ports) 545 intel_de_write(display, DPHY_DATA_TIMING_PARAM(port), 546 intel_dsi->dphy_data_lane_reg); 547 548 /* 549 * If DSI link operating at or below an 800 MHz, 550 * TA_SURE should be override and programmed to 551 * a value '0' inside TA_PARAM_REGISTERS otherwise 552 * leave all fields at HW default values. 553 */ 554 if (DISPLAY_VER(display) == 11) { 555 if (afe_clk(encoder, crtc_state) <= 800000) { 556 for_each_dsi_port(port, intel_dsi->ports) 557 intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port), 558 TA_SURE_MASK, 559 TA_SURE_OVERRIDE | TA_SURE(0)); 560 } 561 } 562 563 if (display->platform.jasperlake || display->platform.elkhartlake) { 564 for_each_dsi_phy(phy, intel_dsi->phys) 565 intel_de_rmw(display, ICL_DPHY_CHKN(phy), 566 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP); 567 } 568 } 569 570 static void 571 gen11_dsi_setup_timings(struct intel_encoder *encoder, 572 const struct intel_crtc_state *crtc_state) 573 { 574 struct intel_display *display = to_intel_display(encoder); 575 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 576 enum port port; 577 578 /* Program T-INIT master registers */ 579 for_each_dsi_port(port, intel_dsi->ports) 580 intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port), 581 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count); 582 583 /* shadow register inside display core */ 584 for_each_dsi_port(port, intel_dsi->ports) 585 intel_de_write(display, DSI_CLK_TIMING_PARAM(port), 586 intel_dsi->dphy_reg); 587 588 /* shadow register inside display core */ 589 for_each_dsi_port(port, intel_dsi->ports) 590 intel_de_write(display, DSI_DATA_TIMING_PARAM(port), 591 intel_dsi->dphy_data_lane_reg); 592 593 /* shadow register inside display core */ 594 if (DISPLAY_VER(display) == 11) { 595 if (afe_clk(encoder, crtc_state) <= 800000) { 596 for_each_dsi_port(port, intel_dsi->ports) { 597 intel_de_rmw(display, DSI_TA_TIMING_PARAM(port), 598 TA_SURE_MASK, 599 TA_SURE_OVERRIDE | TA_SURE(0)); 600 } 601 } 602 } 603 } 604 605 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 606 { 607 struct intel_display *display = to_intel_display(encoder); 608 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 609 u32 tmp; 610 enum phy phy; 611 612 mutex_lock(&display->dpll.lock); 613 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 614 for_each_dsi_phy(phy, intel_dsi->phys) 615 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 616 617 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); 618 mutex_unlock(&display->dpll.lock); 619 } 620 621 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 622 { 623 struct intel_display *display = to_intel_display(encoder); 624 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 625 u32 tmp; 626 enum phy phy; 627 628 mutex_lock(&display->dpll.lock); 629 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 630 for_each_dsi_phy(phy, intel_dsi->phys) 631 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 632 633 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); 634 mutex_unlock(&display->dpll.lock); 635 } 636 637 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 638 { 639 struct intel_display *display = to_intel_display(encoder); 640 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 641 bool clock_enabled = false; 642 enum phy phy; 643 u32 tmp; 644 645 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 646 647 for_each_dsi_phy(phy, intel_dsi->phys) { 648 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 649 clock_enabled = true; 650 } 651 652 return clock_enabled; 653 } 654 655 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 656 const struct intel_crtc_state *crtc_state) 657 { 658 struct intel_display *display = to_intel_display(encoder); 659 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 660 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 661 enum phy phy; 662 u32 val; 663 664 mutex_lock(&display->dpll.lock); 665 666 val = intel_de_read(display, ICL_DPCLKA_CFGCR0); 667 for_each_dsi_phy(phy, intel_dsi->phys) { 668 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 669 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 670 } 671 intel_de_write(display, ICL_DPCLKA_CFGCR0, val); 672 673 for_each_dsi_phy(phy, intel_dsi->phys) { 674 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 675 } 676 intel_de_write(display, ICL_DPCLKA_CFGCR0, val); 677 678 intel_de_posting_read(display, ICL_DPCLKA_CFGCR0); 679 680 mutex_unlock(&display->dpll.lock); 681 } 682 683 static void 684 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 685 const struct intel_crtc_state *pipe_config) 686 { 687 struct intel_display *display = to_intel_display(encoder); 688 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 689 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 690 enum pipe pipe = crtc->pipe; 691 u32 tmp; 692 enum port port; 693 enum transcoder dsi_trans; 694 695 for_each_dsi_port(port, intel_dsi->ports) { 696 dsi_trans = dsi_port_to_transcoder(port); 697 tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); 698 699 if (intel_dsi->eotp_pkt) 700 tmp &= ~EOTP_DISABLED; 701 else 702 tmp |= EOTP_DISABLED; 703 704 /* enable link calibration if freq > 1.5Gbps */ 705 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 706 tmp &= ~LINK_CALIBRATION_MASK; 707 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 708 } 709 710 /* configure continuous clock */ 711 tmp &= ~CONTINUOUS_CLK_MASK; 712 if (intel_dsi->clock_stop) 713 tmp |= CLK_ENTER_LP_AFTER_DATA; 714 else 715 tmp |= CLK_HS_CONTINUOUS; 716 717 /* configure buffer threshold limit to minimum */ 718 tmp &= ~PIX_BUF_THRESHOLD_MASK; 719 tmp |= PIX_BUF_THRESHOLD_1_4; 720 721 /* set virtual channel to '0' */ 722 tmp &= ~PIX_VIRT_CHAN_MASK; 723 tmp |= PIX_VIRT_CHAN(0); 724 725 /* program BGR transmission */ 726 if (intel_dsi->bgr_enabled) 727 tmp |= BGR_TRANSMISSION; 728 729 /* select pixel format */ 730 tmp &= ~PIX_FMT_MASK; 731 if (pipe_config->dsc.compression_enable) { 732 tmp |= PIX_FMT_COMPRESSED; 733 } else { 734 switch (intel_dsi->pixel_format) { 735 default: 736 MISSING_CASE(intel_dsi->pixel_format); 737 fallthrough; 738 case MIPI_DSI_FMT_RGB565: 739 tmp |= PIX_FMT_RGB565; 740 break; 741 case MIPI_DSI_FMT_RGB666_PACKED: 742 tmp |= PIX_FMT_RGB666_PACKED; 743 break; 744 case MIPI_DSI_FMT_RGB666: 745 tmp |= PIX_FMT_RGB666_LOOSE; 746 break; 747 case MIPI_DSI_FMT_RGB888: 748 tmp |= PIX_FMT_RGB888; 749 break; 750 } 751 } 752 753 if (DISPLAY_VER(display) >= 12) { 754 if (is_vid_mode(intel_dsi)) 755 tmp |= BLANKING_PACKET_ENABLE; 756 } 757 758 /* program DSI operation mode */ 759 if (is_vid_mode(intel_dsi)) { 760 tmp &= ~OP_MODE_MASK; 761 switch (intel_dsi->video_mode) { 762 default: 763 MISSING_CASE(intel_dsi->video_mode); 764 fallthrough; 765 case NON_BURST_SYNC_EVENTS: 766 tmp |= VIDEO_MODE_SYNC_EVENT; 767 break; 768 case NON_BURST_SYNC_PULSE: 769 tmp |= VIDEO_MODE_SYNC_PULSE; 770 break; 771 } 772 } else { 773 /* 774 * FIXME: Retrieve this info from VBT. 775 * As per the spec when dsi transcoder is operating 776 * in TE GATE mode, TE comes from GPIO 777 * which is UTIL PIN for DSI 0. 778 * Also this GPIO would not be used for other 779 * purposes is an assumption. 780 */ 781 tmp &= ~OP_MODE_MASK; 782 tmp |= CMD_MODE_TE_GATE; 783 tmp |= TE_SOURCE_GPIO; 784 } 785 786 intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 787 } 788 789 /* enable port sync mode if dual link */ 790 if (intel_dsi->dual_link) { 791 for_each_dsi_port(port, intel_dsi->ports) { 792 dsi_trans = dsi_port_to_transcoder(port); 793 intel_de_rmw(display, 794 TRANS_DDI_FUNC_CTL2(display, dsi_trans), 795 0, PORT_SYNC_MODE_ENABLE); 796 } 797 798 /* configure stream splitting */ 799 configure_dual_link_mode(encoder, pipe_config); 800 } 801 802 for_each_dsi_port(port, intel_dsi->ports) { 803 dsi_trans = dsi_port_to_transcoder(port); 804 805 /* select data lane width */ 806 tmp = intel_de_read(display, 807 TRANS_DDI_FUNC_CTL(display, dsi_trans)); 808 tmp &= ~TRANS_DDI_PORT_WIDTH_MASK; 809 tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count); 810 811 /* select input pipe */ 812 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 813 switch (pipe) { 814 default: 815 MISSING_CASE(pipe); 816 fallthrough; 817 case PIPE_A: 818 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 819 break; 820 case PIPE_B: 821 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 822 break; 823 case PIPE_C: 824 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 825 break; 826 case PIPE_D: 827 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 828 break; 829 } 830 831 /* enable DDI buffer */ 832 tmp |= TRANS_DDI_FUNC_ENABLE; 833 intel_de_write(display, 834 TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp); 835 } 836 837 /* wait for link ready */ 838 for_each_dsi_port(port, intel_dsi->ports) { 839 dsi_trans = dsi_port_to_transcoder(port); 840 if (wait_for_us((intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)) & 841 LINK_READY), 2500)) 842 drm_err(display->drm, "DSI link not ready\n"); 843 } 844 } 845 846 static void 847 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 848 const struct intel_crtc_state *crtc_state) 849 { 850 struct intel_display *display = to_intel_display(encoder); 851 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 852 const struct drm_display_mode *adjusted_mode = 853 &crtc_state->hw.adjusted_mode; 854 enum port port; 855 enum transcoder dsi_trans; 856 /* horizontal timings */ 857 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 858 u16 hback_porch; 859 /* vertical timings */ 860 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 861 int mul = 1, div = 1; 862 863 /* 864 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 865 * for slower link speed if DSC is enabled. 866 * 867 * The compression frequency ratio is the ratio between compressed and 868 * non-compressed link speeds, and simplifies down to the ratio between 869 * compressed and non-compressed bpp. 870 */ 871 if (crtc_state->dsc.compression_enable) { 872 mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 873 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 874 } 875 876 hactive = adjusted_mode->crtc_hdisplay; 877 878 if (is_vid_mode(intel_dsi)) 879 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 880 else 881 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 882 883 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 884 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 885 hsync_size = hsync_end - hsync_start; 886 hback_porch = (adjusted_mode->crtc_htotal - 887 adjusted_mode->crtc_hsync_end); 888 vactive = adjusted_mode->crtc_vdisplay; 889 890 if (is_vid_mode(intel_dsi)) { 891 vtotal = adjusted_mode->crtc_vtotal; 892 } else { 893 int bpp, line_time_us, byte_clk_period_ns; 894 895 if (crtc_state->dsc.compression_enable) 896 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 897 else 898 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 899 900 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 901 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 902 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 903 } 904 vsync_start = adjusted_mode->crtc_vsync_start; 905 vsync_end = adjusted_mode->crtc_vsync_end; 906 vsync_shift = hsync_start - htotal / 2; 907 908 if (intel_dsi->dual_link) { 909 hactive /= 2; 910 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 911 hactive += intel_dsi->pixel_overlap; 912 htotal /= 2; 913 } 914 915 /* minimum hactive as per bspec: 256 pixels */ 916 if (adjusted_mode->crtc_hdisplay < 256) 917 drm_err(display->drm, "hactive is less then 256 pixels\n"); 918 919 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 920 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 921 drm_err(display->drm, 922 "hactive pixels are not multiple of 4\n"); 923 924 /* program TRANS_HTOTAL register */ 925 for_each_dsi_port(port, intel_dsi->ports) { 926 dsi_trans = dsi_port_to_transcoder(port); 927 intel_de_write(display, TRANS_HTOTAL(display, dsi_trans), 928 HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); 929 } 930 931 /* TRANS_HSYNC register to be programmed only for video mode */ 932 if (is_vid_mode(intel_dsi)) { 933 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { 934 /* BSPEC: hsync size should be atleast 16 pixels */ 935 if (hsync_size < 16) 936 drm_err(display->drm, 937 "hsync size < 16 pixels\n"); 938 } 939 940 if (hback_porch < 16) 941 drm_err(display->drm, "hback porch < 16 pixels\n"); 942 943 if (intel_dsi->dual_link) { 944 hsync_start /= 2; 945 hsync_end /= 2; 946 } 947 948 for_each_dsi_port(port, intel_dsi->ports) { 949 dsi_trans = dsi_port_to_transcoder(port); 950 intel_de_write(display, 951 TRANS_HSYNC(display, dsi_trans), 952 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); 953 } 954 } 955 956 /* program TRANS_VTOTAL register */ 957 for_each_dsi_port(port, intel_dsi->ports) { 958 dsi_trans = dsi_port_to_transcoder(port); 959 /* 960 * FIXME: Programming this by assuming progressive mode, since 961 * non-interlaced info from VBT is not saved inside 962 * struct drm_display_mode. 963 * For interlace mode: program required pixel minus 2 964 */ 965 intel_de_write(display, TRANS_VTOTAL(display, dsi_trans), 966 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); 967 } 968 969 if (vsync_end < vsync_start || vsync_end > vtotal) 970 drm_err(display->drm, "Invalid vsync_end value\n"); 971 972 if (vsync_start < vactive) 973 drm_err(display->drm, "vsync_start less than vactive\n"); 974 975 /* program TRANS_VSYNC register for video mode only */ 976 if (is_vid_mode(intel_dsi)) { 977 for_each_dsi_port(port, intel_dsi->ports) { 978 dsi_trans = dsi_port_to_transcoder(port); 979 intel_de_write(display, 980 TRANS_VSYNC(display, dsi_trans), 981 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); 982 } 983 } 984 985 /* 986 * FIXME: It has to be programmed only for video modes and interlaced 987 * modes. Put the check condition here once interlaced 988 * info available as described above. 989 * program TRANS_VSYNCSHIFT register 990 */ 991 if (is_vid_mode(intel_dsi)) { 992 for_each_dsi_port(port, intel_dsi->ports) { 993 dsi_trans = dsi_port_to_transcoder(port); 994 intel_de_write(display, 995 TRANS_VSYNCSHIFT(display, dsi_trans), 996 vsync_shift); 997 } 998 } 999 1000 /* 1001 * program TRANS_VBLANK register, should be same as vtotal programmed 1002 * 1003 * FIXME get rid of these local hacks and do it right, 1004 * this will not handle eg. delayed vblank correctly. 1005 */ 1006 if (DISPLAY_VER(display) >= 12) { 1007 for_each_dsi_port(port, intel_dsi->ports) { 1008 dsi_trans = dsi_port_to_transcoder(port); 1009 intel_de_write(display, 1010 TRANS_VBLANK(display, dsi_trans), 1011 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); 1012 } 1013 } 1014 } 1015 1016 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1017 { 1018 struct intel_display *display = to_intel_display(encoder); 1019 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1020 enum port port; 1021 enum transcoder dsi_trans; 1022 1023 for_each_dsi_port(port, intel_dsi->ports) { 1024 dsi_trans = dsi_port_to_transcoder(port); 1025 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0, 1026 TRANSCONF_ENABLE); 1027 1028 /* wait for transcoder to be enabled */ 1029 if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans), 1030 TRANSCONF_STATE_ENABLE, 10)) 1031 drm_err(display->drm, 1032 "DSI transcoder not enabled\n"); 1033 } 1034 } 1035 1036 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1037 const struct intel_crtc_state *crtc_state) 1038 { 1039 struct intel_display *display = to_intel_display(encoder); 1040 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1041 enum port port; 1042 enum transcoder dsi_trans; 1043 u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1044 1045 /* 1046 * escape clock count calculation: 1047 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1048 * UI (nsec) = (10^6)/Bitrate 1049 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1050 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1051 */ 1052 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1053 mul = 8 * 1000000; 1054 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1055 divisor); 1056 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1057 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1058 1059 for_each_dsi_port(port, intel_dsi->ports) { 1060 dsi_trans = dsi_port_to_transcoder(port); 1061 1062 /* program hst_tx_timeout */ 1063 intel_de_rmw(display, DSI_HSTX_TO(dsi_trans), 1064 HSTX_TIMEOUT_VALUE_MASK, 1065 HSTX_TIMEOUT_VALUE(hs_tx_timeout)); 1066 1067 /* FIXME: DSI_CALIB_TO */ 1068 1069 /* program lp_rx_host timeout */ 1070 intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans), 1071 LPRX_TIMEOUT_VALUE_MASK, 1072 LPRX_TIMEOUT_VALUE(lp_rx_timeout)); 1073 1074 /* FIXME: DSI_PWAIT_TO */ 1075 1076 /* program turn around timeout */ 1077 intel_de_rmw(display, DSI_TA_TO(dsi_trans), 1078 TA_TIMEOUT_VALUE_MASK, 1079 TA_TIMEOUT_VALUE(ta_timeout)); 1080 } 1081 } 1082 1083 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1084 bool enable) 1085 { 1086 struct intel_display *display = to_intel_display(encoder); 1087 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1088 u32 tmp; 1089 1090 /* 1091 * used as TE i/p for DSI0, 1092 * for dual link/DSI1 TE is from slave DSI1 1093 * through GPIO. 1094 */ 1095 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1096 return; 1097 1098 tmp = intel_de_read(display, UTIL_PIN_CTL); 1099 1100 if (enable) { 1101 tmp |= UTIL_PIN_DIRECTION_INPUT; 1102 tmp |= UTIL_PIN_ENABLE; 1103 } else { 1104 tmp &= ~UTIL_PIN_ENABLE; 1105 } 1106 intel_de_write(display, UTIL_PIN_CTL, tmp); 1107 } 1108 1109 static void 1110 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1111 const struct intel_crtc_state *crtc_state) 1112 { 1113 /* step 4a: power up all lanes of the DDI used by DSI */ 1114 gen11_dsi_power_up_lanes(encoder); 1115 1116 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1117 gen11_dsi_config_phy_lanes_sequence(encoder); 1118 1119 /* step 4c: configure voltage swing and skew */ 1120 gen11_dsi_voltage_swing_program_seq(encoder); 1121 1122 /* setup D-PHY timings */ 1123 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1124 1125 /* enable DDI buffer */ 1126 gen11_dsi_enable_ddi_buffer(encoder); 1127 1128 gen11_dsi_gate_clocks(encoder); 1129 1130 gen11_dsi_setup_timings(encoder, crtc_state); 1131 1132 /* Since transcoder is configured to take events from GPIO */ 1133 gen11_dsi_config_util_pin(encoder, true); 1134 1135 /* step 4h: setup DSI protocol timeouts */ 1136 gen11_dsi_setup_timeouts(encoder, crtc_state); 1137 1138 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1139 gen11_dsi_configure_transcoder(encoder, crtc_state); 1140 } 1141 1142 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1143 { 1144 struct intel_display *display = to_intel_display(encoder); 1145 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1146 struct mipi_dsi_device *dsi; 1147 enum port port; 1148 enum transcoder dsi_trans; 1149 u32 tmp; 1150 int ret; 1151 1152 /* set maximum return packet size */ 1153 for_each_dsi_port(port, intel_dsi->ports) { 1154 dsi_trans = dsi_port_to_transcoder(port); 1155 1156 /* 1157 * FIXME: This uses the number of DW's currently in the payload 1158 * receive queue. This is probably not what we want here. 1159 */ 1160 tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans)); 1161 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1162 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1163 tmp = tmp * 4; 1164 dsi = intel_dsi->dsi_hosts[port]->device; 1165 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1166 if (ret < 0) 1167 drm_err(display->drm, 1168 "error setting max return pkt size%d\n", tmp); 1169 } 1170 1171 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1172 1173 /* ensure all panel commands dispatched before enabling transcoder */ 1174 wait_for_cmds_dispatched_to_panel(encoder); 1175 } 1176 1177 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1178 struct intel_encoder *encoder, 1179 const struct intel_crtc_state *crtc_state, 1180 const struct drm_connector_state *conn_state) 1181 { 1182 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1183 1184 intel_dsi_wait_panel_power_cycle(intel_dsi); 1185 1186 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1187 msleep(intel_dsi->panel_on_delay); 1188 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1189 1190 /* step2: enable IO power */ 1191 gen11_dsi_enable_io_power(encoder); 1192 1193 /* step3: enable DSI PLL */ 1194 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1195 } 1196 1197 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1198 struct intel_encoder *encoder, 1199 const struct intel_crtc_state *pipe_config, 1200 const struct drm_connector_state *conn_state) 1201 { 1202 /* step3b */ 1203 gen11_dsi_map_pll(encoder, pipe_config); 1204 1205 /* step4: enable DSI port and DPHY */ 1206 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1207 1208 /* step5: program and powerup panel */ 1209 gen11_dsi_powerup_panel(encoder); 1210 1211 intel_dsc_dsi_pps_write(encoder, pipe_config); 1212 1213 /* step6c: configure transcoder timings */ 1214 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1215 } 1216 1217 /* 1218 * Wa_1409054076:icl,jsl,ehl 1219 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1220 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1221 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1222 * it set while DSI is enabled on pipe B 1223 */ 1224 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1225 enum pipe pipe, bool enable) 1226 { 1227 struct intel_display *display = to_intel_display(encoder); 1228 1229 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B) 1230 intel_de_rmw(display, CHICKEN_PAR1_1, 1231 IGNORE_KVMR_PIPE_A, 1232 enable ? IGNORE_KVMR_PIPE_A : 0); 1233 } 1234 1235 /* 1236 * Wa_16012360555:adl-p 1237 * SW will have to program the "LP to HS Wakeup Guardband" 1238 * to account for the repeaters on the HS Request/Ready 1239 * PPI signaling between the Display engine and the DPHY. 1240 */ 1241 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1242 { 1243 struct intel_display *display = to_intel_display(encoder); 1244 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1245 enum port port; 1246 1247 if (DISPLAY_VER(display) == 13) { 1248 for_each_dsi_port(port, intel_dsi->ports) 1249 intel_de_rmw(display, TGL_DSI_CHKN_REG(port), 1250 TGL_DSI_CHKN_LSHS_GB_MASK, 1251 TGL_DSI_CHKN_LSHS_GB(4)); 1252 } 1253 } 1254 1255 static void gen11_dsi_enable(struct intel_atomic_state *state, 1256 struct intel_encoder *encoder, 1257 const struct intel_crtc_state *crtc_state, 1258 const struct drm_connector_state *conn_state) 1259 { 1260 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1261 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1262 1263 /* Wa_1409054076:icl,jsl,ehl */ 1264 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1265 1266 /* Wa_16012360555:adl-p */ 1267 adlp_set_lp_hs_wakeup_gb(encoder); 1268 1269 /* step6d: enable dsi transcoder */ 1270 gen11_dsi_enable_transcoder(encoder); 1271 1272 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1273 1274 /* step7: enable backlight */ 1275 intel_backlight_enable(crtc_state, conn_state); 1276 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1277 1278 intel_crtc_vblank_on(crtc_state); 1279 } 1280 1281 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1282 { 1283 struct intel_display *display = to_intel_display(encoder); 1284 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1285 enum port port; 1286 enum transcoder dsi_trans; 1287 1288 for_each_dsi_port(port, intel_dsi->ports) { 1289 dsi_trans = dsi_port_to_transcoder(port); 1290 1291 /* disable transcoder */ 1292 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 1293 TRANSCONF_ENABLE, 0); 1294 1295 /* wait for transcoder to be disabled */ 1296 if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans), 1297 TRANSCONF_STATE_ENABLE, 50)) 1298 drm_err(display->drm, 1299 "DSI trancoder not disabled\n"); 1300 } 1301 } 1302 1303 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1304 { 1305 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1306 1307 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1308 1309 /* ensure cmds dispatched to panel */ 1310 wait_for_cmds_dispatched_to_panel(encoder); 1311 } 1312 1313 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1314 { 1315 struct intel_display *display = to_intel_display(encoder); 1316 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1317 enum port port; 1318 enum transcoder dsi_trans; 1319 u32 tmp; 1320 1321 /* disable periodic update mode */ 1322 if (is_cmd_mode(intel_dsi)) { 1323 for_each_dsi_port(port, intel_dsi->ports) 1324 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 1325 DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0); 1326 } 1327 1328 /* put dsi link in ULPS */ 1329 for_each_dsi_port(port, intel_dsi->ports) { 1330 dsi_trans = dsi_port_to_transcoder(port); 1331 tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans)); 1332 tmp |= LINK_ENTER_ULPS; 1333 tmp &= ~LINK_ULPS_TYPE_LP11; 1334 intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp); 1335 1336 if (wait_for_us((intel_de_read(display, DSI_LP_MSG(dsi_trans)) & 1337 LINK_IN_ULPS), 1338 10)) 1339 drm_err(display->drm, "DSI link not in ULPS\n"); 1340 } 1341 1342 /* disable ddi function */ 1343 for_each_dsi_port(port, intel_dsi->ports) { 1344 dsi_trans = dsi_port_to_transcoder(port); 1345 intel_de_rmw(display, 1346 TRANS_DDI_FUNC_CTL(display, dsi_trans), 1347 TRANS_DDI_FUNC_ENABLE, 0); 1348 } 1349 1350 /* disable port sync mode if dual link */ 1351 if (intel_dsi->dual_link) { 1352 for_each_dsi_port(port, intel_dsi->ports) { 1353 dsi_trans = dsi_port_to_transcoder(port); 1354 intel_de_rmw(display, 1355 TRANS_DDI_FUNC_CTL2(display, dsi_trans), 1356 PORT_SYNC_MODE_ENABLE, 0); 1357 } 1358 } 1359 } 1360 1361 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1362 { 1363 struct intel_display *display = to_intel_display(encoder); 1364 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1365 enum port port; 1366 1367 gen11_dsi_ungate_clocks(encoder); 1368 for_each_dsi_port(port, intel_dsi->ports) { 1369 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 1370 1371 if (wait_for_us((intel_de_read(display, DDI_BUF_CTL(port)) & 1372 DDI_BUF_IS_IDLE), 1373 8)) 1374 drm_err(display->drm, 1375 "DDI port:%c buffer not idle\n", 1376 port_name(port)); 1377 } 1378 gen11_dsi_gate_clocks(encoder); 1379 } 1380 1381 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1382 { 1383 struct intel_display *display = to_intel_display(encoder); 1384 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1385 enum port port; 1386 1387 for_each_dsi_port(port, intel_dsi->ports) { 1388 intel_wakeref_t wakeref; 1389 1390 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1391 intel_display_power_put(display, 1392 port == PORT_A ? 1393 POWER_DOMAIN_PORT_DDI_IO_A : 1394 POWER_DOMAIN_PORT_DDI_IO_B, 1395 wakeref); 1396 } 1397 1398 /* set mode to DDI */ 1399 for_each_dsi_port(port, intel_dsi->ports) 1400 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), 1401 COMBO_PHY_MODE_DSI, 0); 1402 } 1403 1404 static void gen11_dsi_disable(struct intel_atomic_state *state, 1405 struct intel_encoder *encoder, 1406 const struct intel_crtc_state *old_crtc_state, 1407 const struct drm_connector_state *old_conn_state) 1408 { 1409 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1410 1411 /* step1: turn off backlight */ 1412 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1413 intel_backlight_disable(old_conn_state); 1414 } 1415 1416 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1417 struct intel_encoder *encoder, 1418 const struct intel_crtc_state *old_crtc_state, 1419 const struct drm_connector_state *old_conn_state) 1420 { 1421 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1422 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1423 1424 intel_crtc_vblank_off(old_crtc_state); 1425 1426 /* step2d,e: disable transcoder and wait */ 1427 gen11_dsi_disable_transcoder(encoder); 1428 1429 /* Wa_1409054076:icl,jsl,ehl */ 1430 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1431 1432 /* step2f,g: powerdown panel */ 1433 gen11_dsi_powerdown_panel(encoder); 1434 1435 /* step2h,i,j: deconfig trancoder */ 1436 gen11_dsi_deconfigure_trancoder(encoder); 1437 1438 intel_dsc_disable(old_crtc_state); 1439 skl_scaler_disable(old_crtc_state); 1440 1441 /* step3: disable port */ 1442 gen11_dsi_disable_port(encoder); 1443 1444 gen11_dsi_config_util_pin(encoder, false); 1445 1446 /* step4: disable IO power */ 1447 gen11_dsi_disable_io_power(encoder); 1448 1449 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1450 1451 msleep(intel_dsi->panel_off_delay); 1452 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1453 1454 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1455 } 1456 1457 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1458 const struct drm_display_mode *mode) 1459 { 1460 struct intel_display *display = to_intel_display(connector->dev); 1461 enum drm_mode_status status; 1462 1463 status = intel_cpu_transcoder_mode_valid(display, mode); 1464 if (status != MODE_OK) 1465 return status; 1466 1467 /* FIXME: DSC? */ 1468 return intel_dsi_mode_valid(connector, mode); 1469 } 1470 1471 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1472 struct intel_crtc_state *pipe_config) 1473 { 1474 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1475 struct drm_display_mode *adjusted_mode = 1476 &pipe_config->hw.adjusted_mode; 1477 1478 if (pipe_config->dsc.compressed_bpp_x16) { 1479 int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); 1480 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1481 1482 adjusted_mode->crtc_htotal = 1483 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1484 adjusted_mode->crtc_hsync_start = 1485 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1486 adjusted_mode->crtc_hsync_end = 1487 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1488 } 1489 1490 if (intel_dsi->dual_link) { 1491 adjusted_mode->crtc_hdisplay *= 2; 1492 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1493 adjusted_mode->crtc_hdisplay -= 1494 intel_dsi->pixel_overlap; 1495 adjusted_mode->crtc_htotal *= 2; 1496 } 1497 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1498 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1499 1500 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1501 if (intel_dsi->dual_link) { 1502 adjusted_mode->crtc_hsync_start *= 2; 1503 adjusted_mode->crtc_hsync_end *= 2; 1504 } 1505 } 1506 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1507 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1508 } 1509 1510 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1511 { 1512 struct intel_display *display = to_intel_display(&intel_dsi->base); 1513 enum transcoder dsi_trans; 1514 u32 val; 1515 1516 if (intel_dsi->ports == BIT(PORT_B)) 1517 dsi_trans = TRANSCODER_DSI_1; 1518 else 1519 dsi_trans = TRANSCODER_DSI_0; 1520 1521 val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); 1522 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1523 } 1524 1525 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1526 struct intel_crtc_state *pipe_config) 1527 { 1528 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1529 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1530 I915_MODE_FLAG_DSI_USE_TE0; 1531 else if (intel_dsi->ports == BIT(PORT_B)) 1532 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1533 else 1534 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1535 } 1536 1537 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1538 struct intel_crtc_state *pipe_config) 1539 { 1540 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1541 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1542 1543 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1544 1545 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1546 if (intel_dsi->dual_link) 1547 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1548 1549 gen11_dsi_get_timings(encoder, pipe_config); 1550 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1551 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1552 1553 /* Get the details on which TE should be enabled */ 1554 if (is_cmd_mode(intel_dsi)) 1555 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1556 1557 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1558 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1559 } 1560 1561 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1562 const struct intel_crtc_state *crtc_state) 1563 { 1564 struct intel_display *display = to_intel_display(encoder); 1565 struct intel_crtc *intel_crtc; 1566 enum pipe pipe; 1567 1568 if (!crtc_state) 1569 return; 1570 1571 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1572 pipe = intel_crtc->pipe; 1573 1574 /* wa verify 1409054076:icl,jsl,ehl */ 1575 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B && 1576 !(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1577 drm_dbg_kms(display->drm, 1578 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1579 encoder->base.base.id, 1580 encoder->base.name); 1581 } 1582 1583 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1584 struct intel_crtc_state *crtc_state) 1585 { 1586 struct intel_display *display = to_intel_display(encoder); 1587 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1588 int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10; 1589 bool use_dsc; 1590 int ret; 1591 1592 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1593 if (!use_dsc) 1594 return 0; 1595 1596 if (crtc_state->pipe_bpp < 8 * 3) 1597 return -EINVAL; 1598 1599 /* FIXME: split only when necessary */ 1600 if (crtc_state->dsc.slice_count > 1) 1601 crtc_state->dsc.num_streams = 2; 1602 else 1603 crtc_state->dsc.num_streams = 1; 1604 1605 /* FIXME: initialize from VBT */ 1606 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1607 1608 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1609 1610 ret = intel_dsc_compute_params(crtc_state); 1611 if (ret) 1612 return ret; 1613 1614 /* DSI specific sanity checks on the common code */ 1615 drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable); 1616 drm_WARN_ON(display->drm, vdsc_cfg->simple_422); 1617 drm_WARN_ON(display->drm, 1618 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1619 drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8); 1620 drm_WARN_ON(display->drm, 1621 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1622 1623 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1624 if (ret) 1625 return ret; 1626 1627 crtc_state->dsc.compression_enable = true; 1628 1629 return 0; 1630 } 1631 1632 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1633 struct intel_crtc_state *pipe_config, 1634 struct drm_connector_state *conn_state) 1635 { 1636 struct intel_display *display = to_intel_display(encoder); 1637 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1638 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1639 struct drm_display_mode *adjusted_mode = 1640 &pipe_config->hw.adjusted_mode; 1641 int ret; 1642 1643 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1644 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1645 1646 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1647 if (ret) 1648 return ret; 1649 1650 ret = intel_pfit_compute_config(pipe_config, conn_state); 1651 if (ret) 1652 return ret; 1653 1654 adjusted_mode->flags = 0; 1655 1656 /* Dual link goes to trancoder DSI'0' */ 1657 if (intel_dsi->ports == BIT(PORT_B)) 1658 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1659 else 1660 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1661 1662 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1663 pipe_config->pipe_bpp = 24; 1664 else 1665 pipe_config->pipe_bpp = 18; 1666 1667 pipe_config->clock_set = true; 1668 1669 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1670 drm_dbg_kms(display->drm, "Attempting to use DSC failed\n"); 1671 1672 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1673 1674 /* 1675 * In case of TE GATE cmd mode, we 1676 * receive TE from the slave if 1677 * dual link is enabled 1678 */ 1679 if (is_cmd_mode(intel_dsi)) 1680 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1681 1682 return 0; 1683 } 1684 1685 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1686 struct intel_crtc_state *crtc_state) 1687 { 1688 get_dsi_io_power_domains(enc_to_intel_dsi(encoder)); 1689 } 1690 1691 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1692 enum pipe *pipe) 1693 { 1694 struct intel_display *display = to_intel_display(encoder); 1695 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1696 enum transcoder dsi_trans; 1697 intel_wakeref_t wakeref; 1698 enum port port; 1699 bool ret = false; 1700 u32 tmp; 1701 1702 wakeref = intel_display_power_get_if_enabled(display, 1703 encoder->power_domain); 1704 if (!wakeref) 1705 return false; 1706 1707 for_each_dsi_port(port, intel_dsi->ports) { 1708 dsi_trans = dsi_port_to_transcoder(port); 1709 tmp = intel_de_read(display, 1710 TRANS_DDI_FUNC_CTL(display, dsi_trans)); 1711 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1712 case TRANS_DDI_EDP_INPUT_A_ON: 1713 *pipe = PIPE_A; 1714 break; 1715 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1716 *pipe = PIPE_B; 1717 break; 1718 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1719 *pipe = PIPE_C; 1720 break; 1721 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1722 *pipe = PIPE_D; 1723 break; 1724 default: 1725 drm_err(display->drm, "Invalid PIPE input\n"); 1726 goto out; 1727 } 1728 1729 tmp = intel_de_read(display, TRANSCONF(display, dsi_trans)); 1730 ret = tmp & TRANSCONF_ENABLE; 1731 } 1732 out: 1733 intel_display_power_put(display, encoder->power_domain, wakeref); 1734 return ret; 1735 } 1736 1737 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1738 struct intel_crtc_state *crtc_state) 1739 { 1740 if (crtc_state->dsc.compression_enable) { 1741 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1742 crtc_state->uapi.mode_changed = true; 1743 1744 return false; 1745 } 1746 1747 return true; 1748 } 1749 1750 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1751 { 1752 intel_encoder_destroy(encoder); 1753 } 1754 1755 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1756 .destroy = gen11_dsi_encoder_destroy, 1757 }; 1758 1759 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1760 .detect = intel_panel_detect, 1761 .late_register = intel_connector_register, 1762 .early_unregister = intel_connector_unregister, 1763 .destroy = intel_connector_destroy, 1764 .fill_modes = drm_helper_probe_single_connector_modes, 1765 .atomic_get_property = intel_digital_connector_atomic_get_property, 1766 .atomic_set_property = intel_digital_connector_atomic_set_property, 1767 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1768 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1769 }; 1770 1771 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1772 .get_modes = intel_dsi_get_modes, 1773 .mode_valid = gen11_dsi_mode_valid, 1774 .atomic_check = intel_digital_connector_atomic_check, 1775 }; 1776 1777 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1778 struct mipi_dsi_device *dsi) 1779 { 1780 return 0; 1781 } 1782 1783 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1784 struct mipi_dsi_device *dsi) 1785 { 1786 return 0; 1787 } 1788 1789 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1790 const struct mipi_dsi_msg *msg) 1791 { 1792 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1793 struct mipi_dsi_packet dsi_pkt; 1794 ssize_t ret; 1795 bool enable_lpdt = false; 1796 1797 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1798 if (ret < 0) 1799 return ret; 1800 1801 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1802 enable_lpdt = true; 1803 1804 /* only long packet contains payload */ 1805 if (mipi_dsi_packet_format_is_long(msg->type)) { 1806 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1807 if (ret < 0) 1808 return ret; 1809 } 1810 1811 /* send packet header */ 1812 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1813 if (ret < 0) 1814 return ret; 1815 1816 //TODO: add payload receive code if needed 1817 1818 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1819 1820 return ret; 1821 } 1822 1823 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1824 .attach = gen11_dsi_host_attach, 1825 .detach = gen11_dsi_host_detach, 1826 .transfer = gen11_dsi_host_transfer, 1827 }; 1828 1829 #define ICL_PREPARE_CNT_MAX 0x7 1830 #define ICL_CLK_ZERO_CNT_MAX 0xf 1831 #define ICL_TRAIL_CNT_MAX 0x7 1832 #define ICL_TCLK_PRE_CNT_MAX 0x3 1833 #define ICL_TCLK_POST_CNT_MAX 0x7 1834 #define ICL_HS_ZERO_CNT_MAX 0xf 1835 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1836 1837 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1838 { 1839 struct intel_display *display = to_intel_display(&intel_dsi->base); 1840 struct intel_connector *connector = intel_dsi->attached_connector; 1841 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1842 u32 tlpx_ns; 1843 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1844 u32 ths_prepare_ns, tclk_trail_ns; 1845 u32 hs_zero_cnt; 1846 u32 tclk_pre_cnt; 1847 1848 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1849 1850 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1851 ths_prepare_ns = max(mipi_config->ths_prepare, 1852 mipi_config->tclk_prepare); 1853 1854 /* 1855 * prepare cnt in escape clocks 1856 * this field represents a hexadecimal value with a precision 1857 * of 1.2 – i.e. the most significant bit is the integer 1858 * and the least significant 2 bits are fraction bits. 1859 * so, the field can represent a range of 0.25 to 1.75 1860 */ 1861 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1862 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1863 drm_dbg_kms(display->drm, "prepare_cnt out of range (%d)\n", 1864 prepare_cnt); 1865 prepare_cnt = ICL_PREPARE_CNT_MAX; 1866 } 1867 1868 /* clk zero count in escape clocks */ 1869 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1870 ths_prepare_ns, tlpx_ns); 1871 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1872 drm_dbg_kms(display->drm, 1873 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1874 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1875 } 1876 1877 /* trail cnt in escape clocks*/ 1878 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1879 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1880 drm_dbg_kms(display->drm, "trail_cnt out of range (%d)\n", 1881 trail_cnt); 1882 trail_cnt = ICL_TRAIL_CNT_MAX; 1883 } 1884 1885 /* tclk pre count in escape clocks */ 1886 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1887 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1888 drm_dbg_kms(display->drm, 1889 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1890 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1891 } 1892 1893 /* hs zero cnt in escape clocks */ 1894 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1895 ths_prepare_ns, tlpx_ns); 1896 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1897 drm_dbg_kms(display->drm, "hs_zero_cnt out of range (%d)\n", 1898 hs_zero_cnt); 1899 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1900 } 1901 1902 /* hs exit zero cnt in escape clocks */ 1903 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1904 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1905 drm_dbg_kms(display->drm, 1906 "exit_zero_cnt out of range (%d)\n", 1907 exit_zero_cnt); 1908 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1909 } 1910 1911 /* clock lane dphy timings */ 1912 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1913 CLK_PREPARE(prepare_cnt) | 1914 CLK_ZERO_OVERRIDE | 1915 CLK_ZERO(clk_zero_cnt) | 1916 CLK_PRE_OVERRIDE | 1917 CLK_PRE(tclk_pre_cnt) | 1918 CLK_TRAIL_OVERRIDE | 1919 CLK_TRAIL(trail_cnt)); 1920 1921 /* data lanes dphy timings */ 1922 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1923 HS_PREPARE(prepare_cnt) | 1924 HS_ZERO_OVERRIDE | 1925 HS_ZERO(hs_zero_cnt) | 1926 HS_TRAIL_OVERRIDE | 1927 HS_TRAIL(trail_cnt) | 1928 HS_EXIT_OVERRIDE | 1929 HS_EXIT(exit_zero_cnt)); 1930 1931 intel_dsi_log_params(intel_dsi); 1932 } 1933 1934 static void icl_dsi_add_properties(struct intel_connector *connector) 1935 { 1936 const struct drm_display_mode *fixed_mode = 1937 intel_panel_preferred_fixed_mode(connector); 1938 1939 intel_attach_scaling_mode_property(&connector->base); 1940 1941 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1942 intel_dsi_get_panel_orientation(connector), 1943 fixed_mode->hdisplay, 1944 fixed_mode->vdisplay); 1945 } 1946 1947 void icl_dsi_init(struct intel_display *display, 1948 const struct intel_bios_encoder_data *devdata) 1949 { 1950 struct intel_dsi *intel_dsi; 1951 struct intel_encoder *encoder; 1952 struct intel_connector *intel_connector; 1953 struct drm_connector *connector; 1954 enum port port; 1955 1956 port = intel_bios_encoder_port(devdata); 1957 if (port == PORT_NONE) 1958 return; 1959 1960 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1961 if (!intel_dsi) 1962 return; 1963 1964 intel_connector = intel_connector_alloc(); 1965 if (!intel_connector) { 1966 kfree(intel_dsi); 1967 return; 1968 } 1969 1970 encoder = &intel_dsi->base; 1971 intel_dsi->attached_connector = intel_connector; 1972 connector = &intel_connector->base; 1973 1974 encoder->devdata = devdata; 1975 1976 /* register DSI encoder with DRM subsystem */ 1977 drm_encoder_init(display->drm, &encoder->base, 1978 &gen11_dsi_encoder_funcs, 1979 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1980 1981 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 1982 encoder->pre_enable = gen11_dsi_pre_enable; 1983 encoder->enable = gen11_dsi_enable; 1984 encoder->disable = gen11_dsi_disable; 1985 encoder->post_disable = gen11_dsi_post_disable; 1986 encoder->port = port; 1987 encoder->get_config = gen11_dsi_get_config; 1988 encoder->sync_state = gen11_dsi_sync_state; 1989 encoder->update_pipe = intel_backlight_update; 1990 encoder->compute_config = gen11_dsi_compute_config; 1991 encoder->get_hw_state = gen11_dsi_get_hw_state; 1992 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 1993 encoder->type = INTEL_OUTPUT_DSI; 1994 encoder->cloneable = 0; 1995 encoder->pipe_mask = ~0; 1996 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1997 encoder->get_power_domains = gen11_dsi_get_power_domains; 1998 encoder->disable_clock = gen11_dsi_gate_clocks; 1999 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 2000 encoder->shutdown = intel_dsi_shutdown; 2001 2002 /* register DSI connector with DRM subsystem */ 2003 drm_connector_init(display->drm, connector, 2004 &gen11_dsi_connector_funcs, 2005 DRM_MODE_CONNECTOR_DSI); 2006 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 2007 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2008 intel_connector->get_hw_state = intel_connector_get_hw_state; 2009 2010 /* attach connector to encoder */ 2011 intel_connector_attach_encoder(intel_connector, encoder); 2012 2013 intel_dsi->panel_power_off_time = ktime_get_boottime(); 2014 2015 intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL); 2016 2017 mutex_lock(&display->drm->mode_config.mutex); 2018 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 2019 mutex_unlock(&display->drm->mode_config.mutex); 2020 2021 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2022 drm_err(display->drm, "DSI fixed mode info missing\n"); 2023 goto err; 2024 } 2025 2026 intel_panel_init(intel_connector, NULL); 2027 2028 intel_backlight_setup(intel_connector, INVALID_PIPE); 2029 2030 if (intel_connector->panel.vbt.dsi.config->dual_link) 2031 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2032 else 2033 intel_dsi->ports = BIT(port); 2034 2035 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 2036 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 2037 2038 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 2039 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 2040 2041 for_each_dsi_port(port, intel_dsi->ports) { 2042 struct intel_dsi_host *host; 2043 2044 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2045 if (!host) 2046 goto err; 2047 2048 intel_dsi->dsi_hosts[port] = host; 2049 } 2050 2051 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2052 drm_dbg_kms(display->drm, "no device found\n"); 2053 goto err; 2054 } 2055 2056 icl_dphy_param_init(intel_dsi); 2057 2058 icl_dsi_add_properties(intel_connector); 2059 return; 2060 2061 err: 2062 drm_connector_cleanup(connector); 2063 drm_encoder_cleanup(&encoder->base); 2064 kfree(intel_dsi); 2065 kfree(intel_connector); 2066 } 2067