1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * 1588 PTP support for Cadence GEM device.
4 *
5 * Copyright (C) 2017 Cadence Design Systems - https://www.cadence.com
6 *
7 * Authors: Rafal Ozieblo <rafalo@cadence.com>
8 * Bartosz Folta <bfolta@cadence.com>
9 */
10 #include <linux/kernel.h>
11 #include <linux/types.h>
12 #include <linux/clk.h>
13 #include <linux/device.h>
14 #include <linux/etherdevice.h>
15 #include <linux/platform_device.h>
16 #include <linux/time64.h>
17 #include <linux/ptp_classify.h>
18 #include <linux/if_ether.h>
19 #include <linux/if_vlan.h>
20 #include <linux/net_tstamp.h>
21 #include <linux/circ_buf.h>
22 #include <linux/spinlock.h>
23
24 #include "macb.h"
25
26 #define GEM_PTP_TIMER_NAME "gem-ptp-timer"
27
macb_ptp_desc(struct macb * bp,struct macb_dma_desc * desc)28 static struct macb_dma_desc_ptp *macb_ptp_desc(struct macb *bp,
29 struct macb_dma_desc *desc)
30 {
31 if (!macb_dma_ptp(bp))
32 return NULL;
33
34 if (macb_dma64(bp))
35 return (struct macb_dma_desc_ptp *)
36 ((u8 *)desc + sizeof(struct macb_dma_desc)
37 + sizeof(struct macb_dma_desc_64));
38 else
39 return (struct macb_dma_desc_ptp *)
40 ((u8 *)desc + sizeof(struct macb_dma_desc));
41 }
42
gem_tsu_get_time(struct ptp_clock_info * ptp,struct timespec64 * ts,struct ptp_system_timestamp * sts)43 static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts,
44 struct ptp_system_timestamp *sts)
45 {
46 struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
47 unsigned long flags;
48 long first, second;
49 u32 secl, sech;
50
51 spin_lock_irqsave(&bp->tsu_clk_lock, flags);
52 ptp_read_system_prets(sts);
53 /* explicit barriers are needed because gem_readl() is relaxed */
54 if (sts)
55 rmb();
56 first = gem_readl(bp, TN);
57 if (sts)
58 rmb();
59 ptp_read_system_postts(sts);
60 secl = gem_readl(bp, TSL);
61 sech = gem_readl(bp, TSH);
62 second = gem_readl(bp, TN);
63
64 /* test for nsec rollover */
65 if (first > second) {
66 /* if so, use later read & re-read seconds
67 * (assume all done within 1s)
68 */
69 ptp_read_system_prets(sts);
70 if (sts)
71 rmb();
72 ts->tv_nsec = gem_readl(bp, TN);
73 if (sts)
74 rmb();
75 ptp_read_system_postts(sts);
76 secl = gem_readl(bp, TSL);
77 sech = gem_readl(bp, TSH);
78 } else {
79 ts->tv_nsec = first;
80 }
81
82 spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
83 ts->tv_sec = (((u64)sech << GEM_TSL_SIZE) | secl)
84 & TSU_SEC_MAX_VAL;
85 return 0;
86 }
87
gem_tsu_set_time(struct ptp_clock_info * ptp,const struct timespec64 * ts)88 static int gem_tsu_set_time(struct ptp_clock_info *ptp,
89 const struct timespec64 *ts)
90 {
91 struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
92 unsigned long flags;
93 u32 ns, sech, secl;
94
95 secl = (u32)ts->tv_sec;
96 sech = (ts->tv_sec >> GEM_TSL_SIZE) & ((1 << GEM_TSH_SIZE) - 1);
97 ns = ts->tv_nsec;
98
99 spin_lock_irqsave(&bp->tsu_clk_lock, flags);
100
101 /* TSH doesn't latch the time and no atomicity! */
102 gem_writel(bp, TN, 0); /* clear to avoid overflow */
103 gem_writel(bp, TSH, sech);
104 /* write lower bits 2nd, for synchronized secs update */
105 gem_writel(bp, TSL, secl);
106 gem_writel(bp, TN, ns);
107
108 spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
109
110 return 0;
111 }
112
gem_tsu_incr_set(struct macb * bp,struct tsu_incr * incr_spec)113 static int gem_tsu_incr_set(struct macb *bp, struct tsu_incr *incr_spec)
114 {
115 unsigned long flags;
116
117 /* tsu_timer_incr register must be written after
118 * the tsu_timer_incr_sub_ns register and the write operation
119 * will cause the value written to the tsu_timer_incr_sub_ns register
120 * to take effect.
121 */
122 spin_lock_irqsave(&bp->tsu_clk_lock, flags);
123 /* RegBit[15:0] = Subns[23:8]; RegBit[31:24] = Subns[7:0] */
124 gem_writel(bp, TISUBN, GEM_BF(SUBNSINCRL, incr_spec->sub_ns) |
125 GEM_BF(SUBNSINCRH, (incr_spec->sub_ns >>
126 GEM_SUBNSINCRL_SIZE)));
127 gem_writel(bp, TI, GEM_BF(NSINCR, incr_spec->ns));
128 spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
129
130 return 0;
131 }
132
gem_ptp_adjfine(struct ptp_clock_info * ptp,long scaled_ppm)133 static int gem_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
134 {
135 struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
136 struct tsu_incr incr_spec;
137 bool neg_adj = false;
138 u32 word;
139 u64 adj;
140
141 if (scaled_ppm < 0) {
142 neg_adj = true;
143 scaled_ppm = -scaled_ppm;
144 }
145
146 /* Adjustment is relative to base frequency */
147 incr_spec.sub_ns = bp->tsu_incr.sub_ns;
148 incr_spec.ns = bp->tsu_incr.ns;
149
150 /* scaling: unused(8bit) | ns(8bit) | fractions(16bit) */
151 word = ((u64)incr_spec.ns << GEM_SUBNSINCR_SIZE) + incr_spec.sub_ns;
152 adj = (u64)scaled_ppm * word;
153 /* Divide with rounding, equivalent to floating dividing:
154 * (temp / USEC_PER_SEC) + 0.5
155 */
156 adj += (USEC_PER_SEC >> 1);
157 adj >>= PPM_FRACTION; /* remove fractions */
158 adj = div_u64(adj, USEC_PER_SEC);
159 adj = neg_adj ? (word - adj) : (word + adj);
160
161 incr_spec.ns = (adj >> GEM_SUBNSINCR_SIZE)
162 & ((1 << GEM_NSINCR_SIZE) - 1);
163 incr_spec.sub_ns = adj & ((1 << GEM_SUBNSINCR_SIZE) - 1);
164 gem_tsu_incr_set(bp, &incr_spec);
165 return 0;
166 }
167
gem_ptp_adjtime(struct ptp_clock_info * ptp,s64 delta)168 static int gem_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
169 {
170 struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
171 struct timespec64 now, then = ns_to_timespec64(delta);
172 u32 adj, sign = 0;
173
174 if (delta < 0) {
175 sign = 1;
176 delta = -delta;
177 }
178
179 if (delta > TSU_NSEC_MAX_VAL) {
180 gem_tsu_get_time(&bp->ptp_clock_info, &now, NULL);
181 now = timespec64_add(now, then);
182
183 gem_tsu_set_time(&bp->ptp_clock_info,
184 (const struct timespec64 *)&now);
185 } else {
186 adj = (sign << GEM_ADDSUB_OFFSET) | delta;
187
188 gem_writel(bp, TA, adj);
189 }
190
191 return 0;
192 }
193
gem_ptp_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)194 static int gem_ptp_enable(struct ptp_clock_info *ptp,
195 struct ptp_clock_request *rq, int on)
196 {
197 return -EOPNOTSUPP;
198 }
199
200 static const struct ptp_clock_info gem_ptp_caps_template = {
201 .owner = THIS_MODULE,
202 .name = GEM_PTP_TIMER_NAME,
203 .max_adj = 0,
204 .n_alarm = 0,
205 .n_ext_ts = 0,
206 .n_per_out = 0,
207 .n_pins = 0,
208 .pps = 1,
209 .adjfine = gem_ptp_adjfine,
210 .adjtime = gem_ptp_adjtime,
211 .gettimex64 = gem_tsu_get_time,
212 .settime64 = gem_tsu_set_time,
213 .enable = gem_ptp_enable,
214 };
215
gem_ptp_init_timer(struct macb * bp)216 static void gem_ptp_init_timer(struct macb *bp)
217 {
218 u32 rem = 0;
219 u64 adj;
220
221 bp->tsu_incr.ns = div_u64_rem(NSEC_PER_SEC, bp->tsu_rate, &rem);
222 if (rem) {
223 adj = rem;
224 adj <<= GEM_SUBNSINCR_SIZE;
225 bp->tsu_incr.sub_ns = div_u64(adj, bp->tsu_rate);
226 } else {
227 bp->tsu_incr.sub_ns = 0;
228 }
229 }
230
gem_ptp_init_tsu(struct macb * bp)231 static void gem_ptp_init_tsu(struct macb *bp)
232 {
233 struct timespec64 ts;
234
235 /* 1. get current system time */
236 ts = ns_to_timespec64(ktime_to_ns(ktime_get_real()));
237
238 /* 2. set ptp timer */
239 gem_tsu_set_time(&bp->ptp_clock_info, &ts);
240
241 /* 3. set PTP timer increment value to BASE_INCREMENT */
242 gem_tsu_incr_set(bp, &bp->tsu_incr);
243
244 gem_writel(bp, TA, 0);
245 }
246
gem_ptp_clear_timer(struct macb * bp)247 static void gem_ptp_clear_timer(struct macb *bp)
248 {
249 bp->tsu_incr.sub_ns = 0;
250 bp->tsu_incr.ns = 0;
251
252 gem_writel(bp, TISUBN, GEM_BF(SUBNSINCR, 0));
253 gem_writel(bp, TI, GEM_BF(NSINCR, 0));
254 gem_writel(bp, TA, 0);
255 }
256
gem_hw_timestamp(struct macb * bp,u32 dma_desc_ts_1,u32 dma_desc_ts_2,struct timespec64 * ts)257 static int gem_hw_timestamp(struct macb *bp, u32 dma_desc_ts_1,
258 u32 dma_desc_ts_2, struct timespec64 *ts)
259 {
260 struct timespec64 tsu;
261
262 ts->tv_sec = (GEM_BFEXT(DMA_SECH, dma_desc_ts_2) << GEM_DMA_SECL_SIZE) |
263 GEM_BFEXT(DMA_SECL, dma_desc_ts_1);
264 ts->tv_nsec = GEM_BFEXT(DMA_NSEC, dma_desc_ts_1);
265
266 /* TSU overlapping workaround
267 * The timestamp only contains lower few bits of seconds,
268 * so add value from 1588 timer
269 */
270 gem_tsu_get_time(&bp->ptp_clock_info, &tsu, NULL);
271
272 ts->tv_sec |= ((~GEM_DMA_SEC_MASK) & tsu.tv_sec);
273
274 /* If the top bit is set in the timestamp,
275 * but not in 1588 timer, it has rolled over,
276 * so subtract max size
277 */
278 if ((ts->tv_sec & (GEM_DMA_SEC_TOP >> 1)) &&
279 !(tsu.tv_sec & (GEM_DMA_SEC_TOP >> 1)))
280 ts->tv_sec -= GEM_DMA_SEC_TOP;
281
282 return 0;
283 }
284
gem_ptp_rxstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)285 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb,
286 struct macb_dma_desc *desc)
287 {
288 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
289 struct macb_dma_desc_ptp *desc_ptp;
290 struct timespec64 ts;
291
292 if (GEM_BFEXT(DMA_RXVALID, desc->addr)) {
293 desc_ptp = macb_ptp_desc(bp, desc);
294 /* Unlikely but check */
295 if (!desc_ptp) {
296 dev_warn_ratelimited(&bp->pdev->dev,
297 "Timestamp not supported in BD\n");
298 return;
299 }
300 gem_hw_timestamp(bp, desc_ptp->ts_1, desc_ptp->ts_2, &ts);
301 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
302 shhwtstamps->hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
303 }
304 }
305
gem_ptp_txstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)306 void gem_ptp_txstamp(struct macb *bp, struct sk_buff *skb,
307 struct macb_dma_desc *desc)
308 {
309 struct skb_shared_hwtstamps shhwtstamps;
310 struct macb_dma_desc_ptp *desc_ptp;
311 struct timespec64 ts;
312
313 if (!GEM_BFEXT(DMA_TXVALID, desc->ctrl)) {
314 dev_warn_ratelimited(&bp->pdev->dev,
315 "Timestamp not set in TX BD as expected\n");
316 return;
317 }
318
319 desc_ptp = macb_ptp_desc(bp, desc);
320 /* Unlikely but check */
321 if (!desc_ptp) {
322 dev_warn_ratelimited(&bp->pdev->dev,
323 "Timestamp not supported in BD\n");
324 return;
325 }
326
327 /* ensure ts_1/ts_2 is loaded after ctrl (TX_USED check) */
328 dma_rmb();
329 gem_hw_timestamp(bp, desc_ptp->ts_1, desc_ptp->ts_2, &ts);
330
331 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
332 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
333 skb_tstamp_tx(skb, &shhwtstamps);
334 }
335
gem_ptp_init(struct net_device * netdev)336 void gem_ptp_init(struct net_device *netdev)
337 {
338 struct macb *bp = netdev_priv(netdev);
339
340 bp->ptp_clock_info = gem_ptp_caps_template;
341
342 /* nominal frequency and maximum adjustment in ppb */
343 bp->tsu_rate = bp->ptp_info->get_tsu_rate(bp);
344 bp->ptp_clock_info.max_adj = bp->ptp_info->get_ptp_max_adj();
345 gem_ptp_init_timer(bp);
346 gem_ptp_init_tsu(bp);
347 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &netdev->dev);
348 if (IS_ERR(bp->ptp_clock)) {
349 pr_err("ptp clock register failed: %ld\n",
350 PTR_ERR(bp->ptp_clock));
351 bp->ptp_clock = NULL;
352 return;
353 } else if (bp->ptp_clock == NULL) {
354 pr_err("ptp clock register failed\n");
355 return;
356 }
357
358 dev_info(&bp->pdev->dev, "%s ptp clock registered.\n",
359 GEM_PTP_TIMER_NAME);
360 }
361
gem_ptp_remove(struct net_device * netdev)362 void gem_ptp_remove(struct net_device *netdev)
363 {
364 struct macb *bp = netdev_priv(netdev);
365
366 if (bp->ptp_clock) {
367 ptp_clock_unregister(bp->ptp_clock);
368 bp->ptp_clock = NULL;
369 }
370
371 gem_ptp_clear_timer(bp);
372
373 dev_info(&bp->pdev->dev, "%s ptp clock unregistered.\n",
374 GEM_PTP_TIMER_NAME);
375 }
376
gem_ptp_set_ts_mode(struct macb * bp,enum macb_bd_control tx_bd_control,enum macb_bd_control rx_bd_control)377 static int gem_ptp_set_ts_mode(struct macb *bp,
378 enum macb_bd_control tx_bd_control,
379 enum macb_bd_control rx_bd_control)
380 {
381 gem_writel(bp, TXBDCTRL, GEM_BF(TXTSMODE, tx_bd_control));
382 gem_writel(bp, RXBDCTRL, GEM_BF(RXTSMODE, rx_bd_control));
383
384 return 0;
385 }
386
gem_get_hwtst(struct net_device * netdev,struct kernel_hwtstamp_config * tstamp_config)387 int gem_get_hwtst(struct net_device *netdev,
388 struct kernel_hwtstamp_config *tstamp_config)
389 {
390 struct macb *bp = netdev_priv(netdev);
391
392 *tstamp_config = bp->tstamp_config;
393 if (!macb_dma_ptp(bp))
394 return -EOPNOTSUPP;
395
396 return 0;
397 }
398
gem_ptp_set_one_step_sync(struct macb * bp,u8 enable)399 static void gem_ptp_set_one_step_sync(struct macb *bp, u8 enable)
400 {
401 u32 reg_val;
402
403 reg_val = macb_readl(bp, NCR);
404
405 if (enable)
406 macb_writel(bp, NCR, reg_val | MACB_BIT(OSSMODE));
407 else
408 macb_writel(bp, NCR, reg_val & ~MACB_BIT(OSSMODE));
409 }
410
gem_set_hwtst(struct net_device * netdev,struct kernel_hwtstamp_config * tstamp_config,struct netlink_ext_ack * extack)411 int gem_set_hwtst(struct net_device *netdev,
412 struct kernel_hwtstamp_config *tstamp_config,
413 struct netlink_ext_ack *extack)
414 {
415 enum macb_bd_control tx_bd_control = TSTAMP_DISABLED;
416 enum macb_bd_control rx_bd_control = TSTAMP_DISABLED;
417 struct macb *bp = netdev_priv(netdev);
418 u32 regval;
419
420 if (!macb_dma_ptp(bp))
421 return -EOPNOTSUPP;
422
423 switch (tstamp_config->tx_type) {
424 case HWTSTAMP_TX_OFF:
425 break;
426 case HWTSTAMP_TX_ONESTEP_SYNC:
427 gem_ptp_set_one_step_sync(bp, 1);
428 tx_bd_control = TSTAMP_ALL_FRAMES;
429 break;
430 case HWTSTAMP_TX_ON:
431 gem_ptp_set_one_step_sync(bp, 0);
432 tx_bd_control = TSTAMP_ALL_FRAMES;
433 break;
434 default:
435 return -ERANGE;
436 }
437
438 switch (tstamp_config->rx_filter) {
439 case HWTSTAMP_FILTER_NONE:
440 break;
441 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
442 break;
443 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
444 break;
445 case HWTSTAMP_FILTER_PTP_V2_EVENT:
446 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
447 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
448 case HWTSTAMP_FILTER_PTP_V2_SYNC:
449 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
450 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
451 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
452 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
453 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
454 rx_bd_control = TSTAMP_ALL_PTP_FRAMES;
455 tstamp_config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
456 regval = macb_readl(bp, NCR);
457 macb_writel(bp, NCR, (regval | MACB_BIT(SRTSM)));
458 break;
459 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
460 case HWTSTAMP_FILTER_ALL:
461 rx_bd_control = TSTAMP_ALL_FRAMES;
462 tstamp_config->rx_filter = HWTSTAMP_FILTER_ALL;
463 break;
464 default:
465 tstamp_config->rx_filter = HWTSTAMP_FILTER_NONE;
466 return -ERANGE;
467 }
468
469 bp->tstamp_config = *tstamp_config;
470
471 if (gem_ptp_set_ts_mode(bp, tx_bd_control, rx_bd_control) != 0)
472 return -ERANGE;
473
474 return 0;
475 }
476
477