1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cadence MACB/GEM Ethernet Controller driver 4 * 5 * Copyright (C) 2004-2006 Atmel Corporation 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 #include <linux/circ_buf.h> 10 #include <linux/clk-provider.h> 11 #include <linux/clk.h> 12 #include <linux/crc32.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/etherdevice.h> 16 #include <linux/firmware/xlnx-zynqmp.h> 17 #include <linux/inetdevice.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/ip.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/netdevice.h> 27 #include <linux/of.h> 28 #include <linux/of_mdio.h> 29 #include <linux/of_net.h> 30 #include <linux/phy/phy.h> 31 #include <linux/phylink.h> 32 #include <linux/platform_device.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/ptp_classify.h> 35 #include <linux/reset.h> 36 #include <linux/slab.h> 37 #include <linux/tcp.h> 38 #include <linux/types.h> 39 #include <linux/udp.h> 40 #include <linux/gcd.h> 41 #include <net/pkt_sched.h> 42 #include "macb.h" 43 44 /* This structure is only used for MACB on SiFive FU540 devices */ 45 struct sifive_fu540_macb_mgmt { 46 void __iomem *reg; 47 unsigned long rate; 48 struct clk_hw hw; 49 }; 50 51 #define MACB_RX_BUFFER_SIZE 128 52 #define RX_BUFFER_MULTIPLE 64 /* bytes */ 53 #define RX_BUFFER_MAX (0xFF * RX_BUFFER_MULTIPLE) /* 16320 bytes */ 54 55 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */ 56 #define MIN_RX_RING_SIZE 64 57 #define MAX_RX_RING_SIZE 8192 58 59 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */ 60 #define MIN_TX_RING_SIZE 64 61 #define MAX_TX_RING_SIZE 4096 62 63 /* level of occupied TX descriptors under which we wake up TX process */ 64 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4) 65 66 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR)) 67 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \ 68 | MACB_BIT(ISR_RLE) \ 69 | MACB_BIT(TXERR)) 70 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \ 71 | MACB_BIT(TXUBR)) 72 73 #define MACB_INT_MISC_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(RXUBR) | \ 74 MACB_BIT(ISR_ROVR) | MACB_BIT(HRESP) | \ 75 GEM_BIT(WOL) | MACB_BIT(WOL)) 76 77 /* Max length of transmit frame must be a multiple of 8 bytes */ 78 #define MACB_TX_LEN_ALIGN 8 79 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1))) 80 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a 81 * false amba_error in TX path from the DMA assuming there is not enough 82 * space in the SRAM (16KB) even when there is. 83 */ 84 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0) 85 86 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU 87 #define MACB_NETIF_LSO NETIF_F_TSO 88 89 #define MACB_WOL_ENABLED BIT(0) 90 91 #define HS_SPEED_10000M 4 92 #define MACB_SERDES_RATE_10G 1 93 94 /* Graceful stop timeouts in us. We should allow up to 95 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) 96 */ 97 #define MACB_HALT_TIMEOUT 14000 98 #define MACB_PM_TIMEOUT 100 /* ms */ 99 100 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */ 101 102 /* DMA buffer descriptor might be different size 103 * depends on hardware configuration: 104 * 105 * 1. dma address width 32 bits: 106 * word 1: 32 bit address of Data Buffer 107 * word 2: control 108 * 109 * 2. dma address width 64 bits: 110 * word 1: 32 bit address of Data Buffer 111 * word 2: control 112 * word 3: upper 32 bit address of Data Buffer 113 * word 4: unused 114 * 115 * 3. dma address width 32 bits with hardware timestamping: 116 * word 1: 32 bit address of Data Buffer 117 * word 2: control 118 * word 3: timestamp word 1 119 * word 4: timestamp word 2 120 * 121 * 4. dma address width 64 bits with hardware timestamping: 122 * word 1: 32 bit address of Data Buffer 123 * word 2: control 124 * word 3: upper 32 bit address of Data Buffer 125 * word 4: unused 126 * word 5: timestamp word 1 127 * word 6: timestamp word 2 128 */ 129 static unsigned int macb_dma_desc_get_size(struct macb *bp) 130 { 131 unsigned int desc_size = sizeof(struct macb_dma_desc); 132 133 if (macb_dma64(bp)) 134 desc_size += sizeof(struct macb_dma_desc_64); 135 if (macb_dma_ptp(bp)) 136 desc_size += sizeof(struct macb_dma_desc_ptp); 137 138 return desc_size; 139 } 140 141 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx) 142 { 143 return desc_idx * (1 + macb_dma64(bp) + macb_dma_ptp(bp)); 144 } 145 146 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc) 147 { 148 return (struct macb_dma_desc_64 *)((void *)desc 149 + sizeof(struct macb_dma_desc)); 150 } 151 152 /* Ring buffer accessors */ 153 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index) 154 { 155 return index & (bp->tx_ring_size - 1); 156 } 157 158 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue, 159 unsigned int index) 160 { 161 index = macb_tx_ring_wrap(queue->bp, index); 162 index = macb_adj_dma_desc_idx(queue->bp, index); 163 return &queue->tx_ring[index]; 164 } 165 166 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue, 167 unsigned int index) 168 { 169 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)]; 170 } 171 172 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index) 173 { 174 dma_addr_t offset; 175 176 offset = macb_tx_ring_wrap(queue->bp, index) * 177 macb_dma_desc_get_size(queue->bp); 178 179 return queue->tx_ring_dma + offset; 180 } 181 182 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index) 183 { 184 return index & (bp->rx_ring_size - 1); 185 } 186 187 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index) 188 { 189 index = macb_rx_ring_wrap(queue->bp, index); 190 index = macb_adj_dma_desc_idx(queue->bp, index); 191 return &queue->rx_ring[index]; 192 } 193 194 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index) 195 { 196 return queue->rx_buffers + queue->bp->rx_buffer_size * 197 macb_rx_ring_wrap(queue->bp, index); 198 } 199 200 /* I/O accessors */ 201 static u32 hw_readl_native(struct macb *bp, int offset) 202 { 203 return __raw_readl(bp->regs + offset); 204 } 205 206 static void hw_writel_native(struct macb *bp, int offset, u32 value) 207 { 208 __raw_writel(value, bp->regs + offset); 209 } 210 211 static u32 hw_readl(struct macb *bp, int offset) 212 { 213 return readl_relaxed(bp->regs + offset); 214 } 215 216 static void hw_writel(struct macb *bp, int offset, u32 value) 217 { 218 writel_relaxed(value, bp->regs + offset); 219 } 220 221 /* Find the CPU endianness by using the loopback bit of NCR register. When the 222 * CPU is in big endian we need to program swapped mode for management 223 * descriptor access. 224 */ 225 static bool hw_is_native_io(void __iomem *addr) 226 { 227 u32 value = MACB_BIT(LLB); 228 229 __raw_writel(value, addr + MACB_NCR); 230 value = __raw_readl(addr + MACB_NCR); 231 232 /* Write 0 back to disable everything */ 233 __raw_writel(0, addr + MACB_NCR); 234 235 return value == MACB_BIT(LLB); 236 } 237 238 static bool hw_is_gem(void __iomem *addr, bool native_io) 239 { 240 u32 id; 241 242 if (native_io) 243 id = __raw_readl(addr + MACB_MID); 244 else 245 id = readl_relaxed(addr + MACB_MID); 246 247 return MACB_BFEXT(IDNUM, id) >= 0x2; 248 } 249 250 static void macb_set_hwaddr(struct macb *bp) 251 { 252 u32 bottom; 253 u16 top; 254 255 bottom = get_unaligned_le32(bp->netdev->dev_addr); 256 macb_or_gem_writel(bp, SA1B, bottom); 257 top = get_unaligned_le16(bp->netdev->dev_addr + 4); 258 macb_or_gem_writel(bp, SA1T, top); 259 260 if (gem_has_ptp(bp)) { 261 gem_writel(bp, RXPTPUNI, bottom); 262 gem_writel(bp, TXPTPUNI, bottom); 263 } 264 265 /* Clear unused address register sets */ 266 macb_or_gem_writel(bp, SA2B, 0); 267 macb_or_gem_writel(bp, SA2T, 0); 268 macb_or_gem_writel(bp, SA3B, 0); 269 macb_or_gem_writel(bp, SA3T, 0); 270 macb_or_gem_writel(bp, SA4B, 0); 271 macb_or_gem_writel(bp, SA4T, 0); 272 } 273 274 static void macb_get_hwaddr(struct macb *bp) 275 { 276 u32 bottom; 277 u16 top; 278 u8 addr[6]; 279 int i; 280 281 /* Check all 4 address register for valid address */ 282 for (i = 0; i < 4; i++) { 283 bottom = macb_or_gem_readl(bp, SA1B + i * 8); 284 top = macb_or_gem_readl(bp, SA1T + i * 8); 285 286 addr[0] = bottom & 0xff; 287 addr[1] = (bottom >> 8) & 0xff; 288 addr[2] = (bottom >> 16) & 0xff; 289 addr[3] = (bottom >> 24) & 0xff; 290 addr[4] = top & 0xff; 291 addr[5] = (top >> 8) & 0xff; 292 293 if (is_valid_ether_addr(addr)) { 294 eth_hw_addr_set(bp->netdev, addr); 295 return; 296 } 297 } 298 299 dev_info(&bp->pdev->dev, "invalid hw address, using random\n"); 300 eth_hw_addr_random(bp->netdev); 301 } 302 303 static int macb_mdio_wait_for_idle(struct macb *bp) 304 { 305 u32 val; 306 307 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE), 308 1, MACB_MDIO_TIMEOUT); 309 } 310 311 static int macb_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 312 { 313 struct macb *bp = bus->priv; 314 int status; 315 316 status = pm_runtime_resume_and_get(&bp->pdev->dev); 317 if (status < 0) 318 goto mdio_pm_exit; 319 320 status = macb_mdio_wait_for_idle(bp); 321 if (status < 0) 322 goto mdio_read_exit; 323 324 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF) 325 | MACB_BF(RW, MACB_MAN_C22_READ) 326 | MACB_BF(PHYA, mii_id) 327 | MACB_BF(REGA, regnum) 328 | MACB_BF(CODE, MACB_MAN_C22_CODE))); 329 330 status = macb_mdio_wait_for_idle(bp); 331 if (status < 0) 332 goto mdio_read_exit; 333 334 status = MACB_BFEXT(DATA, macb_readl(bp, MAN)); 335 336 mdio_read_exit: 337 pm_runtime_put_autosuspend(&bp->pdev->dev); 338 mdio_pm_exit: 339 return status; 340 } 341 342 static int macb_mdio_read_c45(struct mii_bus *bus, int mii_id, int devad, 343 int regnum) 344 { 345 struct macb *bp = bus->priv; 346 int status; 347 348 status = pm_runtime_get_sync(&bp->pdev->dev); 349 if (status < 0) { 350 pm_runtime_put_noidle(&bp->pdev->dev); 351 goto mdio_pm_exit; 352 } 353 354 status = macb_mdio_wait_for_idle(bp); 355 if (status < 0) 356 goto mdio_read_exit; 357 358 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) 359 | MACB_BF(RW, MACB_MAN_C45_ADDR) 360 | MACB_BF(PHYA, mii_id) 361 | MACB_BF(REGA, devad & 0x1F) 362 | MACB_BF(DATA, regnum & 0xFFFF) 363 | MACB_BF(CODE, MACB_MAN_C45_CODE))); 364 365 status = macb_mdio_wait_for_idle(bp); 366 if (status < 0) 367 goto mdio_read_exit; 368 369 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) 370 | MACB_BF(RW, MACB_MAN_C45_READ) 371 | MACB_BF(PHYA, mii_id) 372 | MACB_BF(REGA, devad & 0x1F) 373 | MACB_BF(CODE, MACB_MAN_C45_CODE))); 374 375 status = macb_mdio_wait_for_idle(bp); 376 if (status < 0) 377 goto mdio_read_exit; 378 379 status = MACB_BFEXT(DATA, macb_readl(bp, MAN)); 380 381 mdio_read_exit: 382 pm_runtime_put_autosuspend(&bp->pdev->dev); 383 mdio_pm_exit: 384 return status; 385 } 386 387 static int macb_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 388 u16 value) 389 { 390 struct macb *bp = bus->priv; 391 int status; 392 393 status = pm_runtime_resume_and_get(&bp->pdev->dev); 394 if (status < 0) 395 goto mdio_pm_exit; 396 397 status = macb_mdio_wait_for_idle(bp); 398 if (status < 0) 399 goto mdio_write_exit; 400 401 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF) 402 | MACB_BF(RW, MACB_MAN_C22_WRITE) 403 | MACB_BF(PHYA, mii_id) 404 | MACB_BF(REGA, regnum) 405 | MACB_BF(CODE, MACB_MAN_C22_CODE) 406 | MACB_BF(DATA, value))); 407 408 status = macb_mdio_wait_for_idle(bp); 409 if (status < 0) 410 goto mdio_write_exit; 411 412 mdio_write_exit: 413 pm_runtime_put_autosuspend(&bp->pdev->dev); 414 mdio_pm_exit: 415 return status; 416 } 417 418 static int macb_mdio_write_c45(struct mii_bus *bus, int mii_id, 419 int devad, int regnum, 420 u16 value) 421 { 422 struct macb *bp = bus->priv; 423 int status; 424 425 status = pm_runtime_get_sync(&bp->pdev->dev); 426 if (status < 0) { 427 pm_runtime_put_noidle(&bp->pdev->dev); 428 goto mdio_pm_exit; 429 } 430 431 status = macb_mdio_wait_for_idle(bp); 432 if (status < 0) 433 goto mdio_write_exit; 434 435 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) 436 | MACB_BF(RW, MACB_MAN_C45_ADDR) 437 | MACB_BF(PHYA, mii_id) 438 | MACB_BF(REGA, devad & 0x1F) 439 | MACB_BF(DATA, regnum & 0xFFFF) 440 | MACB_BF(CODE, MACB_MAN_C45_CODE))); 441 442 status = macb_mdio_wait_for_idle(bp); 443 if (status < 0) 444 goto mdio_write_exit; 445 446 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) 447 | MACB_BF(RW, MACB_MAN_C45_WRITE) 448 | MACB_BF(PHYA, mii_id) 449 | MACB_BF(REGA, devad & 0x1F) 450 | MACB_BF(CODE, MACB_MAN_C45_CODE) 451 | MACB_BF(DATA, value))); 452 453 status = macb_mdio_wait_for_idle(bp); 454 if (status < 0) 455 goto mdio_write_exit; 456 457 mdio_write_exit: 458 pm_runtime_put_autosuspend(&bp->pdev->dev); 459 mdio_pm_exit: 460 return status; 461 } 462 463 static void macb_init_buffers(struct macb *bp) 464 { 465 struct macb_queue *queue; 466 unsigned int q; 467 468 /* Single register for all queues' high 32 bits. */ 469 if (macb_dma64(bp)) { 470 macb_writel(bp, RBQPH, 471 upper_32_bits(bp->queues[0].rx_ring_dma)); 472 macb_writel(bp, TBQPH, 473 upper_32_bits(bp->queues[0].tx_ring_dma)); 474 } 475 476 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 477 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma)); 478 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); 479 } 480 } 481 482 /** 483 * macb_set_tx_clk() - Set a clock to a new frequency 484 * @bp: pointer to struct macb 485 * @speed: New frequency in Hz 486 */ 487 static void macb_set_tx_clk(struct macb *bp, int speed) 488 { 489 long ferr, rate, rate_rounded; 490 491 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG)) 492 return; 493 494 /* In case of MII the PHY is the clock master */ 495 if (bp->phy_interface == PHY_INTERFACE_MODE_MII) 496 return; 497 498 rate = rgmii_clock(speed); 499 if (rate < 0) 500 return; 501 502 rate_rounded = clk_round_rate(bp->tx_clk, rate); 503 if (rate_rounded < 0) 504 return; 505 506 /* RGMII allows 50 ppm frequency error. Test and warn if this limit 507 * is not satisfied. 508 */ 509 ferr = abs(rate_rounded - rate); 510 ferr = DIV_ROUND_UP(ferr, rate / 100000); 511 if (ferr > 5) 512 netdev_warn(bp->netdev, 513 "unable to generate target frequency: %ld Hz\n", 514 rate); 515 516 if (clk_set_rate(bp->tx_clk, rate_rounded)) 517 netdev_err(bp->netdev, "adjusting tx_clk failed.\n"); 518 } 519 520 static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 521 phy_interface_t interface, int speed, 522 int duplex) 523 { 524 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs); 525 u32 config; 526 527 config = gem_readl(bp, USX_CONTROL); 528 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config); 529 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config); 530 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS)); 531 config |= GEM_BIT(TX_EN); 532 gem_writel(bp, USX_CONTROL, config); 533 } 534 535 static void macb_usx_pcs_get_state(struct phylink_pcs *pcs, 536 unsigned int neg_mode, 537 struct phylink_link_state *state) 538 { 539 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs); 540 u32 val; 541 542 state->speed = SPEED_10000; 543 state->duplex = 1; 544 state->an_complete = 1; 545 546 val = gem_readl(bp, USX_STATUS); 547 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK)); 548 val = gem_readl(bp, NCFGR); 549 if (val & GEM_BIT(PAE)) 550 state->pause = MLO_PAUSE_RX; 551 } 552 553 static int macb_usx_pcs_config(struct phylink_pcs *pcs, 554 unsigned int neg_mode, 555 phy_interface_t interface, 556 const unsigned long *advertising, 557 bool permit_pause_to_mac) 558 { 559 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs); 560 561 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) | 562 GEM_BIT(SIGNAL_OK)); 563 564 return 0; 565 } 566 567 static unsigned int macb_pcs_inband_caps(struct phylink_pcs *pcs, 568 phy_interface_t interface) 569 { 570 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 571 } 572 573 static void macb_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, 574 struct phylink_link_state *state) 575 { 576 struct macb *bp = container_of(pcs, struct macb, phylink_sgmii_pcs); 577 u16 bmsr, lpa; 578 579 bmsr = gem_readl(bp, PCSSTS); 580 lpa = gem_readl(bp, PCSANLPBASE); 581 phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa); 582 } 583 584 static void macb_pcs_an_restart(struct phylink_pcs *pcs) 585 { 586 /* Not supported */ 587 } 588 589 static int macb_pcs_config(struct phylink_pcs *pcs, 590 unsigned int neg_mode, 591 phy_interface_t interface, 592 const unsigned long *advertising, 593 bool permit_pause_to_mac) 594 { 595 struct macb *bp = container_of(pcs, struct macb, phylink_sgmii_pcs); 596 u32 old, new; 597 598 old = gem_readl(bp, PCSANADV); 599 new = phylink_mii_c22_pcs_encode_advertisement(interface, advertising); 600 if (new != -EINVAL && old != new) 601 gem_writel(bp, PCSANADV, new); 602 603 /* Disable AN if it's not to be used, enable otherwise. 604 * Must be written after PCSSEL is set in NCFGR which is done in 605 * macb_mac_config(), otherwise writes will not take effect. 606 */ 607 old = gem_readl(bp, PCSCNTRL); 608 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 609 new = old | BMCR_ANENABLE; 610 else 611 new = old & ~BMCR_ANENABLE; 612 if (old != new) 613 gem_writel(bp, PCSCNTRL, new); 614 615 return 0; 616 } 617 618 static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = { 619 .pcs_get_state = macb_usx_pcs_get_state, 620 .pcs_config = macb_usx_pcs_config, 621 .pcs_link_up = macb_usx_pcs_link_up, 622 }; 623 624 static const struct phylink_pcs_ops macb_phylink_pcs_ops = { 625 .pcs_inband_caps = macb_pcs_inband_caps, 626 .pcs_get_state = macb_pcs_get_state, 627 .pcs_an_restart = macb_pcs_an_restart, 628 .pcs_config = macb_pcs_config, 629 }; 630 631 static bool macb_tx_lpi_set(struct macb *bp, bool enable) 632 { 633 u32 old, ncr; 634 635 lockdep_assert_held(&bp->lock); 636 637 ncr = macb_readl(bp, NCR); 638 old = ncr; 639 if (enable) 640 ncr |= GEM_BIT(TXLPIEN); 641 else 642 ncr &= ~GEM_BIT(TXLPIEN); 643 if (old != ncr) 644 macb_writel(bp, NCR, ncr); 645 646 return old != ncr; 647 } 648 649 static bool macb_tx_all_queues_idle(struct macb *bp) 650 { 651 struct macb_queue *queue; 652 unsigned int q; 653 654 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 655 if (READ_ONCE(queue->tx_head) != READ_ONCE(queue->tx_tail)) 656 return false; 657 } 658 return true; 659 } 660 661 static void macb_tx_lpi_work_fn(struct work_struct *work) 662 { 663 struct macb *bp = container_of(work, struct macb, tx_lpi_work.work); 664 unsigned long flags; 665 666 spin_lock_irqsave(&bp->lock, flags); 667 if (bp->eee_active && macb_tx_all_queues_idle(bp)) 668 macb_tx_lpi_set(bp, true); 669 spin_unlock_irqrestore(&bp->lock, flags); 670 } 671 672 static void macb_tx_lpi_schedule(struct macb *bp) 673 { 674 if (bp->eee_active) 675 mod_delayed_work(system_wq, &bp->tx_lpi_work, 676 usecs_to_jiffies(bp->tx_lpi_timer)); 677 } 678 679 /* Wake from LPI before transmitting. The MAC must deassert TXLPIEN 680 * and wait for the PHY to exit LPI before any frame can be sent. 681 * IEEE 802.3az Tw_sys is ~17us for 1000BASE-T, ~30us for 100BASE-TX; 682 * we use a conservative 50us. 683 */ 684 static void macb_tx_lpi_wake(struct macb *bp) 685 { 686 lockdep_assert_held(&bp->lock); 687 688 if (!bp->eee_active) 689 return; 690 691 if (!macb_tx_lpi_set(bp, false)) 692 return; 693 694 cancel_delayed_work(&bp->tx_lpi_work); 695 udelay(50); 696 } 697 698 static void macb_mac_disable_tx_lpi(struct phylink_config *config) 699 { 700 struct net_device *netdev = to_net_dev(config->dev); 701 struct macb *bp = netdev_priv(netdev); 702 unsigned long flags; 703 704 cancel_delayed_work_sync(&bp->tx_lpi_work); 705 706 spin_lock_irqsave(&bp->lock, flags); 707 bp->eee_active = false; 708 macb_tx_lpi_set(bp, false); 709 spin_unlock_irqrestore(&bp->lock, flags); 710 } 711 712 static int macb_mac_enable_tx_lpi(struct phylink_config *config, u32 timer, 713 bool tx_clk_stop) 714 { 715 struct net_device *netdev = to_net_dev(config->dev); 716 struct macb *bp = netdev_priv(netdev); 717 unsigned long flags; 718 719 spin_lock_irqsave(&bp->lock, flags); 720 bp->tx_lpi_timer = timer; 721 bp->eee_active = true; 722 spin_unlock_irqrestore(&bp->lock, flags); 723 724 /* Defer initial LPI entry by 1 second after link-up per 725 * IEEE 802.3az section 22.7a. 726 */ 727 mod_delayed_work(system_wq, &bp->tx_lpi_work, msecs_to_jiffies(1000)); 728 729 return 0; 730 } 731 732 static void macb_mac_config(struct phylink_config *config, unsigned int mode, 733 const struct phylink_link_state *state) 734 { 735 struct net_device *netdev = to_net_dev(config->dev); 736 struct macb *bp = netdev_priv(netdev); 737 unsigned long flags; 738 u32 old_ctrl, ctrl; 739 u32 old_ncr, ncr; 740 741 spin_lock_irqsave(&bp->lock, flags); 742 743 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR); 744 old_ncr = ncr = macb_or_gem_readl(bp, NCR); 745 746 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) { 747 if (state->interface == PHY_INTERFACE_MODE_RMII) 748 ctrl |= MACB_BIT(RM9200_RMII); 749 } else if (macb_is_gem(bp)) { 750 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL)); 751 ncr &= ~GEM_BIT(ENABLE_HS_MAC); 752 753 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 754 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); 755 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) { 756 ctrl |= GEM_BIT(PCSSEL); 757 ncr |= GEM_BIT(ENABLE_HS_MAC); 758 } else if (bp->caps & MACB_CAPS_MIIONRGMII && 759 bp->phy_interface == PHY_INTERFACE_MODE_MII) { 760 ncr |= MACB_BIT(MIIONRGMII); 761 } 762 } 763 764 /* Apply the new configuration, if any */ 765 if (old_ctrl ^ ctrl) 766 macb_or_gem_writel(bp, NCFGR, ctrl); 767 768 if (old_ncr ^ ncr) 769 macb_or_gem_writel(bp, NCR, ncr); 770 771 spin_unlock_irqrestore(&bp->lock, flags); 772 } 773 774 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode, 775 phy_interface_t interface) 776 { 777 struct net_device *netdev = to_net_dev(config->dev); 778 struct macb *bp = netdev_priv(netdev); 779 struct macb_queue *queue; 780 unsigned int q; 781 u32 ctrl; 782 783 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) 784 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) 785 queue_writel(queue, IDR, 786 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP)); 787 788 /* Disable Rx and Tx */ 789 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE)); 790 macb_writel(bp, NCR, ctrl); 791 792 netif_tx_stop_all_queues(netdev); 793 } 794 795 /* Use juggling algorithm to left rotate tx ring and tx skb array */ 796 static void gem_shuffle_tx_one_ring(struct macb_queue *queue) 797 { 798 unsigned int head, tail, count, ring_size, desc_size; 799 struct macb_tx_skb tx_skb, *skb_curr, *skb_next; 800 struct macb_dma_desc *desc_curr, *desc_next; 801 unsigned int i, cycles, shift, curr, next; 802 struct macb *bp = queue->bp; 803 unsigned char desc[24]; 804 unsigned long flags; 805 806 desc_size = macb_dma_desc_get_size(bp); 807 808 if (WARN_ON_ONCE(desc_size > ARRAY_SIZE(desc))) 809 return; 810 811 spin_lock_irqsave(&queue->tx_ptr_lock, flags); 812 head = queue->tx_head; 813 tail = queue->tx_tail; 814 ring_size = bp->tx_ring_size; 815 count = CIRC_CNT(head, tail, ring_size); 816 817 if (!(tail % ring_size)) 818 goto unlock; 819 820 if (!count) { 821 queue->tx_head = 0; 822 queue->tx_tail = 0; 823 goto unlock; 824 } 825 826 shift = tail % ring_size; 827 cycles = gcd(ring_size, shift); 828 829 for (i = 0; i < cycles; i++) { 830 memcpy(&desc, macb_tx_desc(queue, i), desc_size); 831 memcpy(&tx_skb, macb_tx_skb(queue, i), 832 sizeof(struct macb_tx_skb)); 833 834 curr = i; 835 next = (curr + shift) % ring_size; 836 837 while (next != i) { 838 desc_curr = macb_tx_desc(queue, curr); 839 desc_next = macb_tx_desc(queue, next); 840 841 memcpy(desc_curr, desc_next, desc_size); 842 843 if (next == ring_size - 1) 844 desc_curr->ctrl &= ~MACB_BIT(TX_WRAP); 845 if (curr == ring_size - 1) 846 desc_curr->ctrl |= MACB_BIT(TX_WRAP); 847 848 skb_curr = macb_tx_skb(queue, curr); 849 skb_next = macb_tx_skb(queue, next); 850 memcpy(skb_curr, skb_next, sizeof(struct macb_tx_skb)); 851 852 curr = next; 853 next = (curr + shift) % ring_size; 854 } 855 856 desc_curr = macb_tx_desc(queue, curr); 857 memcpy(desc_curr, &desc, desc_size); 858 if (i == ring_size - 1) 859 desc_curr->ctrl &= ~MACB_BIT(TX_WRAP); 860 if (curr == ring_size - 1) 861 desc_curr->ctrl |= MACB_BIT(TX_WRAP); 862 memcpy(macb_tx_skb(queue, curr), &tx_skb, 863 sizeof(struct macb_tx_skb)); 864 } 865 866 queue->tx_head = count; 867 queue->tx_tail = 0; 868 869 /* Make descriptor updates visible to hardware */ 870 wmb(); 871 872 unlock: 873 spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 874 } 875 876 /* Rotate the queue so that the tail is at index 0 */ 877 static void gem_shuffle_tx_rings(struct macb *bp) 878 { 879 struct macb_queue *queue; 880 unsigned int q; 881 882 for (q = 0, queue = bp->queues; q < bp->num_queues; q++, queue++) 883 gem_shuffle_tx_one_ring(queue); 884 } 885 886 static void macb_mac_link_up(struct phylink_config *config, 887 struct phy_device *phydev, 888 unsigned int mode, phy_interface_t interface, 889 int speed, int duplex, 890 bool tx_pause, bool rx_pause) 891 { 892 struct net_device *netdev = to_net_dev(config->dev); 893 struct macb *bp = netdev_priv(netdev); 894 struct macb_queue *queue; 895 unsigned long flags; 896 unsigned int q; 897 u32 ctrl; 898 899 spin_lock_irqsave(&bp->lock, flags); 900 901 ctrl = macb_or_gem_readl(bp, NCFGR); 902 903 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 904 905 if (speed == SPEED_100) 906 ctrl |= MACB_BIT(SPD); 907 908 if (duplex) 909 ctrl |= MACB_BIT(FD); 910 911 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) { 912 ctrl &= ~MACB_BIT(PAE); 913 if (macb_is_gem(bp)) { 914 ctrl &= ~GEM_BIT(GBE); 915 916 if (speed == SPEED_1000) 917 ctrl |= GEM_BIT(GBE); 918 } 919 920 if (rx_pause) 921 ctrl |= MACB_BIT(PAE); 922 923 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 924 queue_writel(queue, IER, 925 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP)); 926 } 927 } 928 929 macb_or_gem_writel(bp, NCFGR, ctrl); 930 931 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER) 932 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M, 933 gem_readl(bp, HS_MAC_CONFIG))); 934 935 spin_unlock_irqrestore(&bp->lock, flags); 936 937 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) { 938 macb_set_tx_clk(bp, speed); 939 gem_shuffle_tx_rings(bp); 940 } 941 942 /* Enable Rx and Tx; Enable PTP unicast */ 943 ctrl = macb_readl(bp, NCR); 944 if (gem_has_ptp(bp)) 945 ctrl |= MACB_BIT(PTPUNI); 946 947 macb_writel(bp, NCR, ctrl | MACB_BIT(RE) | MACB_BIT(TE)); 948 949 netif_tx_wake_all_queues(netdev); 950 } 951 952 static struct phylink_pcs *macb_mac_select_pcs(struct phylink_config *config, 953 phy_interface_t interface) 954 { 955 struct net_device *netdev = to_net_dev(config->dev); 956 struct macb *bp = netdev_priv(netdev); 957 958 if (interface == PHY_INTERFACE_MODE_10GBASER) 959 return &bp->phylink_usx_pcs; 960 else if (interface == PHY_INTERFACE_MODE_SGMII) 961 return &bp->phylink_sgmii_pcs; 962 else 963 return NULL; 964 } 965 966 static const struct phylink_mac_ops macb_phylink_ops = { 967 .mac_select_pcs = macb_mac_select_pcs, 968 .mac_config = macb_mac_config, 969 .mac_link_down = macb_mac_link_down, 970 .mac_link_up = macb_mac_link_up, 971 .mac_disable_tx_lpi = macb_mac_disable_tx_lpi, 972 .mac_enable_tx_lpi = macb_mac_enable_tx_lpi, 973 }; 974 975 static bool macb_phy_handle_exists(struct device_node *dn) 976 { 977 dn = of_parse_phandle(dn, "phy-handle", 0); 978 of_node_put(dn); 979 return dn != NULL; 980 } 981 982 static int macb_phylink_connect(struct macb *bp) 983 { 984 struct device_node *dn = bp->pdev->dev.of_node; 985 struct net_device *netdev = bp->netdev; 986 struct phy_device *phydev; 987 int ret; 988 989 if (dn) 990 ret = phylink_of_phy_connect(bp->phylink, dn, 0); 991 992 if (!dn || (ret && !macb_phy_handle_exists(dn))) { 993 phydev = phy_find_first(bp->mii_bus); 994 if (!phydev) { 995 netdev_err(netdev, "no PHY found\n"); 996 return -ENXIO; 997 } 998 999 /* attach the mac to the phy */ 1000 ret = phylink_connect_phy(bp->phylink, phydev); 1001 } 1002 1003 if (ret) { 1004 netdev_err(netdev, "Could not attach PHY (%d)\n", ret); 1005 return ret; 1006 } 1007 1008 phylink_start(bp->phylink); 1009 1010 return 0; 1011 } 1012 1013 static void macb_get_pcs_fixed_state(struct phylink_config *config, 1014 struct phylink_link_state *state) 1015 { 1016 struct net_device *netdev = to_net_dev(config->dev); 1017 struct macb *bp = netdev_priv(netdev); 1018 1019 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0; 1020 } 1021 1022 /* based on au1000_eth. c*/ 1023 static int macb_mii_probe(struct net_device *netdev) 1024 { 1025 struct macb *bp = netdev_priv(netdev); 1026 1027 bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops; 1028 bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops; 1029 1030 bp->phylink_config.dev = &netdev->dev; 1031 bp->phylink_config.type = PHYLINK_NETDEV; 1032 bp->phylink_config.mac_managed_pm = true; 1033 1034 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1035 bp->phylink_config.poll_fixed_state = true; 1036 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state; 1037 /* The PCSAUTONEG bit in PCSCNTRL is on out of reset. Setting 1038 * default_an_inband to true tells phylink to turn it off only 1039 * if necessary (e.g. a fixed link or a PHY that doesn't support 1040 * inband). 1041 */ 1042 bp->phylink_config.default_an_inband = true; 1043 } 1044 1045 bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 1046 MAC_10 | MAC_100; 1047 1048 __set_bit(PHY_INTERFACE_MODE_MII, 1049 bp->phylink_config.supported_interfaces); 1050 __set_bit(PHY_INTERFACE_MODE_RMII, 1051 bp->phylink_config.supported_interfaces); 1052 1053 /* Determine what modes are supported */ 1054 if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) { 1055 bp->phylink_config.mac_capabilities |= MAC_1000FD; 1056 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) 1057 bp->phylink_config.mac_capabilities |= MAC_1000HD; 1058 1059 __set_bit(PHY_INTERFACE_MODE_GMII, 1060 bp->phylink_config.supported_interfaces); 1061 phy_interface_set_rgmii(bp->phylink_config.supported_interfaces); 1062 1063 if (bp->caps & MACB_CAPS_PCS) 1064 __set_bit(PHY_INTERFACE_MODE_SGMII, 1065 bp->phylink_config.supported_interfaces); 1066 1067 if (bp->caps & MACB_CAPS_HIGH_SPEED) { 1068 __set_bit(PHY_INTERFACE_MODE_10GBASER, 1069 bp->phylink_config.supported_interfaces); 1070 bp->phylink_config.mac_capabilities |= MAC_10000FD; 1071 } 1072 } 1073 1074 /* Configure EEE LPI if supported */ 1075 if (bp->caps & MACB_CAPS_EEE) { 1076 __set_bit(PHY_INTERFACE_MODE_MII, 1077 bp->phylink_config.lpi_interfaces); 1078 __set_bit(PHY_INTERFACE_MODE_GMII, 1079 bp->phylink_config.lpi_interfaces); 1080 phy_interface_set_rgmii(bp->phylink_config.lpi_interfaces); 1081 bp->phylink_config.lpi_capabilities = MAC_100FD | MAC_1000FD; 1082 bp->phylink_config.lpi_timer_default = 250000; 1083 bp->phylink_config.eee_enabled_default = true; 1084 } 1085 1086 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode, 1087 bp->phy_interface, &macb_phylink_ops); 1088 if (IS_ERR(bp->phylink)) { 1089 netdev_err(netdev, "Could not create a phylink instance (%ld)\n", 1090 PTR_ERR(bp->phylink)); 1091 return PTR_ERR(bp->phylink); 1092 } 1093 1094 return 0; 1095 } 1096 1097 static int macb_mdiobus_register(struct macb *bp, struct device_node *mdio_np) 1098 { 1099 struct device_node *child, *np = bp->pdev->dev.of_node; 1100 1101 /* If we have a child named mdio, probe it instead of looking for PHYs 1102 * directly under the MAC node 1103 */ 1104 if (mdio_np) 1105 return of_mdiobus_register(bp->mii_bus, mdio_np); 1106 1107 /* Only create the PHY from the device tree if at least one PHY is 1108 * described. Otherwise scan the entire MDIO bus. We do this to support 1109 * old device tree that did not follow the best practices and did not 1110 * describe their network PHYs. 1111 */ 1112 for_each_available_child_of_node(np, child) 1113 if (of_mdiobus_child_is_phy(child)) { 1114 /* The loop increments the child refcount, 1115 * decrement it before returning. 1116 */ 1117 of_node_put(child); 1118 1119 return of_mdiobus_register(bp->mii_bus, np); 1120 } 1121 1122 return mdiobus_register(bp->mii_bus); 1123 } 1124 1125 static int macb_mii_init(struct macb *bp) 1126 { 1127 struct device_node *mdio_np, *np = bp->pdev->dev.of_node; 1128 int err = -ENXIO; 1129 1130 /* With fixed-link, we don't need to register the MDIO bus, 1131 * except if we have a child named "mdio" in the device tree. 1132 * In that case, some devices may be attached to the MACB's MDIO bus. 1133 */ 1134 mdio_np = of_get_child_by_name(np, "mdio"); 1135 if (!mdio_np && of_phy_is_fixed_link(np)) 1136 return macb_mii_probe(bp->netdev); 1137 1138 /* Enable management port */ 1139 macb_writel(bp, NCR, MACB_BIT(MPE)); 1140 1141 bp->mii_bus = mdiobus_alloc(); 1142 if (!bp->mii_bus) { 1143 err = -ENOMEM; 1144 goto err_out; 1145 } 1146 1147 bp->mii_bus->name = "MACB_mii_bus"; 1148 bp->mii_bus->read = &macb_mdio_read_c22; 1149 bp->mii_bus->write = &macb_mdio_write_c22; 1150 bp->mii_bus->read_c45 = &macb_mdio_read_c45; 1151 bp->mii_bus->write_c45 = &macb_mdio_write_c45; 1152 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1153 bp->pdev->name, bp->pdev->id); 1154 bp->mii_bus->priv = bp; 1155 bp->mii_bus->parent = &bp->pdev->dev; 1156 1157 dev_set_drvdata(&bp->netdev->dev, bp->mii_bus); 1158 1159 err = macb_mdiobus_register(bp, mdio_np); 1160 if (err) 1161 goto err_out_free_mdiobus; 1162 1163 err = macb_mii_probe(bp->netdev); 1164 if (err) 1165 goto err_out_unregister_bus; 1166 1167 of_node_put(mdio_np); 1168 1169 return 0; 1170 1171 err_out_unregister_bus: 1172 mdiobus_unregister(bp->mii_bus); 1173 err_out_free_mdiobus: 1174 mdiobus_free(bp->mii_bus); 1175 err_out: 1176 of_node_put(mdio_np); 1177 1178 return err; 1179 } 1180 1181 static void macb_update_stats(struct macb *bp) 1182 { 1183 u64 *p = &bp->hw_stats.macb.rx_pause_frames; 1184 u64 *end = &bp->hw_stats.macb.tx_pause_frames + 1; 1185 int offset = MACB_PFR; 1186 1187 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); 1188 1189 for (; p < end; p++, offset += 4) 1190 *p += bp->macb_reg_readl(bp, offset); 1191 } 1192 1193 static int macb_halt_tx(struct macb *bp) 1194 { 1195 u32 status; 1196 1197 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT)); 1198 1199 /* Poll TSR until TGO is cleared or timeout. */ 1200 return read_poll_timeout_atomic(macb_readl, status, 1201 !(status & MACB_BIT(TGO)), 1202 250, MACB_HALT_TIMEOUT, false, 1203 bp, TSR); 1204 } 1205 1206 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb, int budget) 1207 { 1208 if (tx_skb->mapping) { 1209 if (tx_skb->mapped_as_page) 1210 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping, 1211 tx_skb->size, DMA_TO_DEVICE); 1212 else 1213 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, 1214 tx_skb->size, DMA_TO_DEVICE); 1215 tx_skb->mapping = 0; 1216 } 1217 1218 if (tx_skb->skb) { 1219 dev_consume_skb_any(tx_skb->skb); 1220 tx_skb->skb = NULL; 1221 } 1222 } 1223 1224 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr) 1225 { 1226 if (macb_dma64(bp)) { 1227 struct macb_dma_desc_64 *desc_64; 1228 1229 desc_64 = macb_64b_desc(bp, desc); 1230 desc_64->addrh = upper_32_bits(addr); 1231 /* The low bits of RX address contain the RX_USED bit, clearing 1232 * of which allows packet RX. Make sure the high bits are also 1233 * visible to HW at that point. 1234 */ 1235 dma_wmb(); 1236 } 1237 1238 desc->addr = lower_32_bits(addr); 1239 } 1240 1241 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc) 1242 { 1243 dma_addr_t addr = 0; 1244 1245 if (macb_dma64(bp)) { 1246 struct macb_dma_desc_64 *desc_64; 1247 1248 desc_64 = macb_64b_desc(bp, desc); 1249 addr = ((u64)(desc_64->addrh) << 32); 1250 } 1251 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr)); 1252 if (macb_dma_ptp(bp)) 1253 addr &= ~GEM_BIT(DMA_RXVALID); 1254 return addr; 1255 } 1256 1257 static void macb_tx_error_task(struct work_struct *work) 1258 { 1259 struct macb_queue *queue = container_of(work, struct macb_queue, 1260 tx_error_task); 1261 unsigned int q = queue - queue->bp->queues; 1262 struct macb *bp = queue->bp; 1263 struct macb_tx_skb *tx_skb; 1264 struct macb_dma_desc *desc; 1265 bool halt_timeout = false; 1266 struct sk_buff *skb; 1267 unsigned long flags; 1268 unsigned int tail; 1269 u32 packets = 0; 1270 u32 bytes = 0; 1271 1272 netdev_vdbg(bp->netdev, "%s: q = %u, t = %u, h = %u\n", 1273 __func__, q, queue->tx_tail, queue->tx_head); 1274 1275 /* Prevent the queue NAPI TX poll from running, as it calls 1276 * macb_tx_complete(), which in turn may call netif_wake_subqueue(). 1277 * As explained below, we have to halt the transmission before updating 1278 * TBQP registers so we call netif_tx_stop_all_queues() to notify the 1279 * network engine about the macb/gem being halted. 1280 */ 1281 napi_disable(&queue->napi_tx); 1282 spin_lock_irqsave(&bp->lock, flags); 1283 1284 /* Make sure nobody is trying to queue up new packets */ 1285 netif_tx_stop_all_queues(bp->netdev); 1286 1287 /* Stop transmission now 1288 * (in case we have just queued new packets) 1289 * macb/gem must be halted to write TBQP register 1290 */ 1291 if (macb_halt_tx(bp)) { 1292 netdev_err(bp->netdev, "BUG: halt tx timed out\n"); 1293 macb_writel(bp, NCR, macb_readl(bp, NCR) & (~MACB_BIT(TE))); 1294 halt_timeout = true; 1295 } 1296 1297 /* Treat frames in TX queue including the ones that caused the error. 1298 * Free transmit buffers in upper layer. 1299 */ 1300 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) { 1301 u32 ctrl; 1302 1303 desc = macb_tx_desc(queue, tail); 1304 ctrl = desc->ctrl; 1305 tx_skb = macb_tx_skb(queue, tail); 1306 skb = tx_skb->skb; 1307 1308 if (ctrl & MACB_BIT(TX_USED)) { 1309 /* skb is set for the last buffer of the frame */ 1310 while (!skb) { 1311 macb_tx_unmap(bp, tx_skb, 0); 1312 tail++; 1313 tx_skb = macb_tx_skb(queue, tail); 1314 skb = tx_skb->skb; 1315 } 1316 1317 /* ctrl still refers to the first buffer descriptor 1318 * since it's the only one written back by the hardware 1319 */ 1320 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) { 1321 netdev_vdbg(bp->netdev, "txerr skb %u (data %p) TX complete\n", 1322 macb_tx_ring_wrap(bp, tail), 1323 skb->data); 1324 bp->netdev->stats.tx_packets++; 1325 queue->stats.tx_packets++; 1326 packets++; 1327 bp->netdev->stats.tx_bytes += skb->len - tx_skb->fcs_len; 1328 queue->stats.tx_bytes += skb->len - tx_skb->fcs_len; 1329 bytes += skb->len; 1330 } 1331 } else { 1332 /* "Buffers exhausted mid-frame" errors may only happen 1333 * if the driver is buggy, so complain loudly about 1334 * those. Statistics are updated by hardware. 1335 */ 1336 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED)) 1337 netdev_err(bp->netdev, 1338 "BUG: TX buffers exhausted mid-frame\n"); 1339 1340 desc->ctrl = ctrl | MACB_BIT(TX_USED); 1341 } 1342 1343 macb_tx_unmap(bp, tx_skb, 0); 1344 } 1345 1346 netdev_tx_completed_queue(netdev_get_tx_queue(bp->netdev, q), 1347 packets, bytes); 1348 1349 /* Set end of TX queue */ 1350 desc = macb_tx_desc(queue, 0); 1351 macb_set_addr(bp, desc, 0); 1352 desc->ctrl = MACB_BIT(TX_USED); 1353 1354 /* Make descriptor updates visible to hardware */ 1355 wmb(); 1356 1357 /* Reinitialize the TX desc queue */ 1358 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); 1359 /* Make TX ring reflect state of hardware */ 1360 queue->tx_head = 0; 1361 queue->tx_tail = 0; 1362 1363 /* Housework before enabling TX IRQ */ 1364 macb_writel(bp, TSR, macb_readl(bp, TSR)); 1365 queue_writel(queue, IER, MACB_TX_INT_FLAGS); 1366 1367 if (halt_timeout) 1368 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE)); 1369 1370 /* Now we are ready to start transmission again */ 1371 netif_tx_start_all_queues(bp->netdev); 1372 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 1373 1374 spin_unlock_irqrestore(&bp->lock, flags); 1375 napi_enable(&queue->napi_tx); 1376 } 1377 1378 static bool ptp_one_step_sync(struct sk_buff *skb) 1379 { 1380 struct ptp_header *hdr; 1381 unsigned int ptp_class; 1382 u8 msgtype; 1383 1384 /* No need to parse packet if PTP TS is not involved */ 1385 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 1386 goto not_oss; 1387 1388 /* Identify and return whether PTP one step sync is being processed */ 1389 ptp_class = ptp_classify_raw(skb); 1390 if (ptp_class == PTP_CLASS_NONE) 1391 goto not_oss; 1392 1393 hdr = ptp_parse_header(skb, ptp_class); 1394 if (!hdr) 1395 goto not_oss; 1396 1397 if (hdr->flag_field[0] & PTP_FLAG_TWOSTEP) 1398 goto not_oss; 1399 1400 msgtype = ptp_get_msgtype(hdr, ptp_class); 1401 if (msgtype == PTP_MSGTYPE_SYNC) 1402 return true; 1403 1404 not_oss: 1405 return false; 1406 } 1407 1408 static int macb_tx_complete(struct macb_queue *queue, int budget) 1409 { 1410 struct macb *bp = queue->bp; 1411 unsigned int q = queue - bp->queues; 1412 unsigned long flags; 1413 unsigned int tail; 1414 unsigned int head; 1415 int packets = 0; 1416 u32 bytes = 0; 1417 1418 spin_lock_irqsave(&queue->tx_ptr_lock, flags); 1419 head = queue->tx_head; 1420 for (tail = queue->tx_tail; tail != head && packets < budget; tail++) { 1421 struct macb_tx_skb *tx_skb; 1422 struct sk_buff *skb; 1423 struct macb_dma_desc *desc; 1424 u32 ctrl; 1425 1426 desc = macb_tx_desc(queue, tail); 1427 1428 /* Make hw descriptor updates visible to CPU */ 1429 rmb(); 1430 1431 ctrl = desc->ctrl; 1432 1433 /* TX_USED bit is only set by hardware on the very first buffer 1434 * descriptor of the transmitted frame. 1435 */ 1436 if (!(ctrl & MACB_BIT(TX_USED))) 1437 break; 1438 1439 /* Process all buffers of the current transmitted frame */ 1440 for (;; tail++) { 1441 tx_skb = macb_tx_skb(queue, tail); 1442 skb = tx_skb->skb; 1443 1444 /* First, update TX stats if needed */ 1445 if (skb) { 1446 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1447 !ptp_one_step_sync(skb)) 1448 gem_ptp_do_txstamp(bp, skb, desc); 1449 1450 netdev_vdbg(bp->netdev, "skb %u (data %p) TX complete\n", 1451 macb_tx_ring_wrap(bp, tail), 1452 skb->data); 1453 bp->netdev->stats.tx_packets++; 1454 queue->stats.tx_packets++; 1455 bp->netdev->stats.tx_bytes += skb->len - tx_skb->fcs_len; 1456 queue->stats.tx_bytes += skb->len - tx_skb->fcs_len; 1457 packets++; 1458 bytes += skb->len; 1459 } 1460 1461 /* Now we can safely release resources */ 1462 macb_tx_unmap(bp, tx_skb, budget); 1463 1464 /* skb is set only for the last buffer of the frame. 1465 * WARNING: at this point skb has been freed by 1466 * macb_tx_unmap(). 1467 */ 1468 if (skb) 1469 break; 1470 } 1471 } 1472 1473 netdev_tx_completed_queue(netdev_get_tx_queue(bp->netdev, q), 1474 packets, bytes); 1475 1476 queue->tx_tail = tail; 1477 if (__netif_subqueue_stopped(bp->netdev, q) && 1478 CIRC_CNT(queue->tx_head, queue->tx_tail, 1479 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp)) 1480 netif_wake_subqueue(bp->netdev, q); 1481 spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 1482 1483 if (packets) 1484 macb_tx_lpi_schedule(bp); 1485 1486 return packets; 1487 } 1488 1489 static void gem_rx_refill(struct macb_queue *queue) 1490 { 1491 struct macb *bp = queue->bp; 1492 struct macb_dma_desc *desc; 1493 struct sk_buff *skb; 1494 unsigned int entry; 1495 dma_addr_t paddr; 1496 1497 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail, 1498 bp->rx_ring_size) > 0) { 1499 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head); 1500 1501 /* Make hw descriptor updates visible to CPU */ 1502 rmb(); 1503 1504 desc = macb_rx_desc(queue, entry); 1505 1506 if (!queue->rx_skbuff[entry]) { 1507 /* allocate sk_buff for this free entry in ring */ 1508 skb = netdev_alloc_skb(bp->netdev, bp->rx_buffer_size); 1509 if (unlikely(!skb)) { 1510 netdev_err(bp->netdev, 1511 "Unable to allocate sk_buff\n"); 1512 break; 1513 } 1514 1515 /* now fill corresponding descriptor entry */ 1516 paddr = dma_map_single(&bp->pdev->dev, skb->data, 1517 bp->rx_buffer_size, 1518 DMA_FROM_DEVICE); 1519 if (dma_mapping_error(&bp->pdev->dev, paddr)) { 1520 dev_kfree_skb(skb); 1521 break; 1522 } 1523 1524 queue->rx_skbuff[entry] = skb; 1525 1526 if (entry == bp->rx_ring_size - 1) 1527 paddr |= MACB_BIT(RX_WRAP); 1528 desc->ctrl = 0; 1529 /* Setting addr clears RX_USED and allows reception, 1530 * make sure ctrl is cleared first to avoid a race. 1531 */ 1532 dma_wmb(); 1533 macb_set_addr(bp, desc, paddr); 1534 1535 /* Properly align Ethernet header. 1536 * 1537 * Hardware can add dummy bytes if asked using the RBOF 1538 * field inside the NCFGR register. That feature isn't 1539 * available if hardware is RSC capable. 1540 * 1541 * We cannot fallback to doing the 2-byte shift before 1542 * DMA mapping because the address field does not allow 1543 * setting the low 2/3 bits. 1544 * It is 3 bits if HW_DMA_CAP_PTP, else 2 bits. 1545 */ 1546 if (!(bp->caps & MACB_CAPS_RSC)) 1547 skb_reserve(skb, NET_IP_ALIGN); 1548 } else { 1549 desc->ctrl = 0; 1550 dma_wmb(); 1551 desc->addr &= ~MACB_BIT(RX_USED); 1552 } 1553 queue->rx_prepared_head++; 1554 } 1555 1556 /* Make descriptor updates visible to hardware */ 1557 wmb(); 1558 1559 netdev_vdbg(bp->netdev, "rx ring: queue: %p, prepared head %d, tail %d\n", 1560 queue, queue->rx_prepared_head, queue->rx_tail); 1561 } 1562 1563 /* Mark DMA descriptors from begin up to and not including end as unused */ 1564 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin, 1565 unsigned int end) 1566 { 1567 unsigned int frag; 1568 1569 for (frag = begin; frag != end; frag++) { 1570 struct macb_dma_desc *desc = macb_rx_desc(queue, frag); 1571 1572 desc->addr &= ~MACB_BIT(RX_USED); 1573 } 1574 1575 /* Make descriptor updates visible to hardware */ 1576 wmb(); 1577 1578 /* When this happens, the hardware stats registers for 1579 * whatever caused this is updated, so we don't have to record 1580 * anything. 1581 */ 1582 } 1583 1584 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi, 1585 int budget) 1586 { 1587 struct macb *bp = queue->bp; 1588 struct macb_dma_desc *desc; 1589 struct sk_buff *skb; 1590 unsigned int entry; 1591 unsigned int len; 1592 int count = 0; 1593 1594 while (count < budget) { 1595 u32 ctrl; 1596 dma_addr_t addr; 1597 bool rxused; 1598 1599 entry = macb_rx_ring_wrap(bp, queue->rx_tail); 1600 desc = macb_rx_desc(queue, entry); 1601 1602 /* Make hw descriptor updates visible to CPU */ 1603 rmb(); 1604 1605 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false; 1606 addr = macb_get_addr(bp, desc); 1607 1608 if (!rxused) 1609 break; 1610 1611 /* Ensure ctrl is at least as up-to-date as rxused */ 1612 dma_rmb(); 1613 1614 ctrl = desc->ctrl; 1615 1616 queue->rx_tail++; 1617 count++; 1618 1619 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) { 1620 netdev_err(bp->netdev, 1621 "not whole frame pointed by descriptor\n"); 1622 bp->netdev->stats.rx_dropped++; 1623 queue->stats.rx_dropped++; 1624 break; 1625 } 1626 skb = queue->rx_skbuff[entry]; 1627 if (unlikely(!skb)) { 1628 netdev_err(bp->netdev, 1629 "inconsistent Rx descriptor chain\n"); 1630 bp->netdev->stats.rx_dropped++; 1631 queue->stats.rx_dropped++; 1632 break; 1633 } 1634 /* now everything is ready for receiving packet */ 1635 queue->rx_skbuff[entry] = NULL; 1636 len = ctrl & bp->rx_frm_len_mask; 1637 1638 netdev_vdbg(bp->netdev, "%s %u (len %u)\n", 1639 __func__, entry, len); 1640 1641 skb_put(skb, len); 1642 dma_unmap_single(&bp->pdev->dev, addr, 1643 bp->rx_buffer_size, DMA_FROM_DEVICE); 1644 1645 skb->protocol = eth_type_trans(skb, bp->netdev); 1646 skb_checksum_none_assert(skb); 1647 if (bp->netdev->features & NETIF_F_RXCSUM && 1648 !(bp->netdev->flags & IFF_PROMISC) && 1649 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK) 1650 skb->ip_summed = CHECKSUM_UNNECESSARY; 1651 1652 bp->netdev->stats.rx_packets++; 1653 queue->stats.rx_packets++; 1654 bp->netdev->stats.rx_bytes += skb->len; 1655 queue->stats.rx_bytes += skb->len; 1656 1657 gem_ptp_do_rxstamp(bp, skb, desc); 1658 1659 #if defined(DEBUG) && defined(VERBOSE_DEBUG) 1660 netdev_vdbg(bp->netdev, "received skb of length %u, csum: %08x\n", 1661 skb->len, skb->csum); 1662 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1, 1663 skb_mac_header(skb), 16, true); 1664 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1, 1665 skb->data, 32, true); 1666 #endif 1667 1668 napi_gro_receive(napi, skb); 1669 } 1670 1671 gem_rx_refill(queue); 1672 1673 return count; 1674 } 1675 1676 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi, 1677 unsigned int first_frag, unsigned int last_frag) 1678 { 1679 struct macb *bp = queue->bp; 1680 struct macb_dma_desc *desc; 1681 unsigned int offset; 1682 struct sk_buff *skb; 1683 unsigned int frag; 1684 unsigned int len; 1685 1686 desc = macb_rx_desc(queue, last_frag); 1687 len = desc->ctrl & bp->rx_frm_len_mask; 1688 1689 netdev_vdbg(bp->netdev, "%s frags %u - %u (len %u)\n", 1690 __func__, 1691 macb_rx_ring_wrap(bp, first_frag), 1692 macb_rx_ring_wrap(bp, last_frag), len); 1693 1694 /* The ethernet header starts NET_IP_ALIGN bytes into the 1695 * first buffer. Since the header is 14 bytes, this makes the 1696 * payload word-aligned. 1697 * 1698 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy 1699 * the two padding bytes into the skb so that we avoid hitting 1700 * the slowpath in memcpy(), and pull them off afterwards. 1701 */ 1702 skb = netdev_alloc_skb(bp->netdev, len + NET_IP_ALIGN); 1703 if (!skb) { 1704 bp->netdev->stats.rx_dropped++; 1705 for (frag = first_frag; ; frag++) { 1706 desc = macb_rx_desc(queue, frag); 1707 desc->addr &= ~MACB_BIT(RX_USED); 1708 if (frag == last_frag) 1709 break; 1710 } 1711 1712 /* Make descriptor updates visible to hardware */ 1713 wmb(); 1714 1715 return 1; 1716 } 1717 1718 offset = 0; 1719 len += NET_IP_ALIGN; 1720 skb_checksum_none_assert(skb); 1721 skb_put(skb, len); 1722 1723 for (frag = first_frag; ; frag++) { 1724 unsigned int frag_len = bp->rx_buffer_size; 1725 1726 if (offset + frag_len > len) { 1727 if (unlikely(frag != last_frag)) { 1728 dev_kfree_skb_any(skb); 1729 return -1; 1730 } 1731 frag_len = len - offset; 1732 } 1733 skb_copy_to_linear_data_offset(skb, offset, 1734 macb_rx_buffer(queue, frag), 1735 frag_len); 1736 offset += bp->rx_buffer_size; 1737 desc = macb_rx_desc(queue, frag); 1738 desc->addr &= ~MACB_BIT(RX_USED); 1739 1740 if (frag == last_frag) 1741 break; 1742 } 1743 1744 /* Make descriptor updates visible to hardware */ 1745 wmb(); 1746 1747 __skb_pull(skb, NET_IP_ALIGN); 1748 skb->protocol = eth_type_trans(skb, bp->netdev); 1749 1750 bp->netdev->stats.rx_packets++; 1751 bp->netdev->stats.rx_bytes += skb->len; 1752 netdev_vdbg(bp->netdev, "received skb of length %u, csum: %08x\n", 1753 skb->len, skb->csum); 1754 napi_gro_receive(napi, skb); 1755 1756 return 0; 1757 } 1758 1759 static inline void macb_init_rx_ring(struct macb_queue *queue) 1760 { 1761 struct macb_dma_desc *desc = NULL; 1762 struct macb *bp = queue->bp; 1763 dma_addr_t addr; 1764 int i; 1765 1766 addr = queue->rx_buffers_dma; 1767 for (i = 0; i < bp->rx_ring_size; i++) { 1768 desc = macb_rx_desc(queue, i); 1769 macb_set_addr(bp, desc, addr); 1770 desc->ctrl = 0; 1771 addr += bp->rx_buffer_size; 1772 } 1773 desc->addr |= MACB_BIT(RX_WRAP); 1774 queue->rx_tail = 0; 1775 } 1776 1777 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi, 1778 int budget) 1779 { 1780 struct macb *bp = queue->bp; 1781 bool reset_rx_queue = false; 1782 int first_frag = -1; 1783 unsigned int tail; 1784 int received = 0; 1785 1786 for (tail = queue->rx_tail; budget > 0; tail++) { 1787 struct macb_dma_desc *desc = macb_rx_desc(queue, tail); 1788 u32 ctrl; 1789 1790 /* Make hw descriptor updates visible to CPU */ 1791 rmb(); 1792 1793 if (!(desc->addr & MACB_BIT(RX_USED))) 1794 break; 1795 1796 /* Ensure ctrl is at least as up-to-date as addr */ 1797 dma_rmb(); 1798 1799 ctrl = desc->ctrl; 1800 1801 if (ctrl & MACB_BIT(RX_SOF)) { 1802 if (first_frag != -1) 1803 discard_partial_frame(queue, first_frag, tail); 1804 first_frag = tail; 1805 } 1806 1807 if (ctrl & MACB_BIT(RX_EOF)) { 1808 int dropped; 1809 1810 if (unlikely(first_frag == -1)) { 1811 reset_rx_queue = true; 1812 continue; 1813 } 1814 1815 dropped = macb_rx_frame(queue, napi, first_frag, tail); 1816 first_frag = -1; 1817 if (unlikely(dropped < 0)) { 1818 reset_rx_queue = true; 1819 continue; 1820 } 1821 if (!dropped) { 1822 received++; 1823 budget--; 1824 } 1825 } 1826 } 1827 1828 if (unlikely(reset_rx_queue)) { 1829 unsigned long flags; 1830 u32 ctrl; 1831 1832 netdev_err(bp->netdev, "RX queue corruption: reset it\n"); 1833 1834 spin_lock_irqsave(&bp->lock, flags); 1835 1836 ctrl = macb_readl(bp, NCR); 1837 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE)); 1838 1839 macb_init_rx_ring(queue); 1840 queue_writel(queue, RBQP, queue->rx_ring_dma); 1841 1842 macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); 1843 1844 spin_unlock_irqrestore(&bp->lock, flags); 1845 return received; 1846 } 1847 1848 if (first_frag != -1) 1849 queue->rx_tail = first_frag; 1850 else 1851 queue->rx_tail = tail; 1852 1853 return received; 1854 } 1855 1856 static bool macb_rx_pending(struct macb_queue *queue) 1857 { 1858 struct macb *bp = queue->bp; 1859 struct macb_dma_desc *desc; 1860 unsigned int entry; 1861 1862 entry = macb_rx_ring_wrap(bp, queue->rx_tail); 1863 desc = macb_rx_desc(queue, entry); 1864 1865 /* Make hw descriptor updates visible to CPU */ 1866 rmb(); 1867 1868 return (desc->addr & MACB_BIT(RX_USED)) != 0; 1869 } 1870 1871 static int macb_rx_poll(struct napi_struct *napi, int budget) 1872 { 1873 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_rx); 1874 struct macb *bp = queue->bp; 1875 int work_done; 1876 1877 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget); 1878 1879 netdev_vdbg(bp->netdev, "RX poll: queue = %u, work_done = %d, budget = %d\n", 1880 (unsigned int)(queue - bp->queues), work_done, budget); 1881 1882 if (work_done < budget && napi_complete_done(napi, work_done)) { 1883 queue_writel(queue, IER, bp->rx_intr_mask); 1884 1885 /* Packet completions only seem to propagate to raise 1886 * interrupts when interrupts are enabled at the time, so if 1887 * packets were received while interrupts were disabled, 1888 * they will not cause another interrupt to be generated when 1889 * interrupts are re-enabled. 1890 * Check for this case here to avoid losing a wakeup. This can 1891 * potentially race with the interrupt handler doing the same 1892 * actions if an interrupt is raised just after enabling them, 1893 * but this should be harmless. 1894 */ 1895 if (macb_rx_pending(queue)) { 1896 queue_writel(queue, IDR, bp->rx_intr_mask); 1897 macb_queue_isr_clear(bp, queue, MACB_BIT(RCOMP)); 1898 netdev_vdbg(bp->netdev, "poll: packets pending, reschedule\n"); 1899 napi_schedule(napi); 1900 } 1901 } 1902 1903 /* TODO: Handle errors */ 1904 1905 return work_done; 1906 } 1907 1908 static void macb_tx_restart(struct macb_queue *queue) 1909 { 1910 struct macb *bp = queue->bp; 1911 unsigned int head_idx, tbqp; 1912 unsigned long flags; 1913 1914 spin_lock_irqsave(&queue->tx_ptr_lock, flags); 1915 1916 if (queue->tx_head == queue->tx_tail) 1917 goto out_tx_ptr_unlock; 1918 1919 tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp); 1920 tbqp = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, tbqp)); 1921 head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, queue->tx_head)); 1922 1923 if (tbqp == head_idx) 1924 goto out_tx_ptr_unlock; 1925 1926 spin_lock(&bp->lock); 1927 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 1928 spin_unlock(&bp->lock); 1929 1930 out_tx_ptr_unlock: 1931 spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 1932 } 1933 1934 static bool macb_tx_complete_pending(struct macb_queue *queue) 1935 { 1936 bool retval = false; 1937 unsigned long flags; 1938 1939 spin_lock_irqsave(&queue->tx_ptr_lock, flags); 1940 if (queue->tx_head != queue->tx_tail) { 1941 /* Make hw descriptor updates visible to CPU */ 1942 rmb(); 1943 1944 if (macb_tx_desc(queue, queue->tx_tail)->ctrl & MACB_BIT(TX_USED)) 1945 retval = true; 1946 } 1947 spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 1948 return retval; 1949 } 1950 1951 static int macb_tx_poll(struct napi_struct *napi, int budget) 1952 { 1953 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_tx); 1954 struct macb *bp = queue->bp; 1955 int work_done; 1956 1957 work_done = macb_tx_complete(queue, budget); 1958 1959 rmb(); // ensure txubr_pending is up to date 1960 if (queue->txubr_pending) { 1961 queue->txubr_pending = false; 1962 netdev_vdbg(bp->netdev, "poll: tx restart\n"); 1963 macb_tx_restart(queue); 1964 } 1965 1966 netdev_vdbg(bp->netdev, "TX poll: queue = %u, work_done = %d, budget = %d\n", 1967 (unsigned int)(queue - bp->queues), work_done, budget); 1968 1969 if (work_done < budget && napi_complete_done(napi, work_done)) { 1970 queue_writel(queue, IER, MACB_BIT(TCOMP)); 1971 1972 /* Packet completions only seem to propagate to raise 1973 * interrupts when interrupts are enabled at the time, so if 1974 * packets were sent while interrupts were disabled, 1975 * they will not cause another interrupt to be generated when 1976 * interrupts are re-enabled. 1977 * Check for this case here to avoid losing a wakeup. This can 1978 * potentially race with the interrupt handler doing the same 1979 * actions if an interrupt is raised just after enabling them, 1980 * but this should be harmless. 1981 */ 1982 if (macb_tx_complete_pending(queue)) { 1983 queue_writel(queue, IDR, MACB_BIT(TCOMP)); 1984 macb_queue_isr_clear(bp, queue, MACB_BIT(TCOMP)); 1985 netdev_vdbg(bp->netdev, "TX poll: packets pending, reschedule\n"); 1986 napi_schedule(napi); 1987 } 1988 } 1989 1990 return work_done; 1991 } 1992 1993 static void macb_hresp_error_task(struct work_struct *work) 1994 { 1995 struct macb *bp = from_work(bp, work, hresp_err_bh_work); 1996 struct net_device *netdev = bp->netdev; 1997 struct macb_queue *queue; 1998 unsigned int q; 1999 u32 ctrl; 2000 2001 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2002 queue_writel(queue, IDR, bp->rx_intr_mask | 2003 MACB_TX_INT_FLAGS | 2004 MACB_BIT(HRESP)); 2005 } 2006 ctrl = macb_readl(bp, NCR); 2007 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE)); 2008 macb_writel(bp, NCR, ctrl); 2009 2010 netif_tx_stop_all_queues(netdev); 2011 netif_carrier_off(netdev); 2012 2013 bp->macbgem_ops.mog_init_rings(bp); 2014 2015 /* Initialize TX and RX buffers */ 2016 macb_init_buffers(bp); 2017 2018 /* Enable interrupts */ 2019 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) 2020 queue_writel(queue, IER, 2021 bp->rx_intr_mask | 2022 MACB_TX_INT_FLAGS | 2023 MACB_BIT(HRESP)); 2024 2025 ctrl |= MACB_BIT(RE) | MACB_BIT(TE); 2026 macb_writel(bp, NCR, ctrl); 2027 2028 netif_carrier_on(netdev); 2029 netif_tx_start_all_queues(netdev); 2030 } 2031 2032 static void macb_wol_interrupt(struct macb_queue *queue, u32 status) 2033 { 2034 struct macb *bp = queue->bp; 2035 2036 queue_writel(queue, IDR, MACB_BIT(WOL)); 2037 macb_writel(bp, WOL, 0); 2038 netdev_vdbg(bp->netdev, "MACB WoL: queue = %u, isr = 0x%08lx\n", 2039 (unsigned int)(queue - bp->queues), 2040 (unsigned long)status); 2041 macb_queue_isr_clear(bp, queue, MACB_BIT(WOL)); 2042 pm_wakeup_event(&bp->pdev->dev, 0); 2043 } 2044 2045 static void gem_wol_interrupt(struct macb_queue *queue, u32 status) 2046 { 2047 struct macb *bp = queue->bp; 2048 2049 queue_writel(queue, IDR, GEM_BIT(WOL)); 2050 gem_writel(bp, WOL, 0); 2051 netdev_vdbg(bp->netdev, "GEM WoL: queue = %u, isr = 0x%08lx\n", 2052 (unsigned int)(queue - bp->queues), 2053 (unsigned long)status); 2054 macb_queue_isr_clear(bp, queue, GEM_BIT(WOL)); 2055 pm_wakeup_event(&bp->pdev->dev, 0); 2056 } 2057 2058 static int macb_interrupt_misc(struct macb_queue *queue, u32 status) 2059 { 2060 struct macb *bp = queue->bp; 2061 struct net_device *netdev; 2062 u32 ctrl; 2063 2064 netdev = bp->netdev; 2065 2066 if (unlikely(status & (MACB_TX_ERR_FLAGS))) { 2067 queue_writel(queue, IDR, MACB_TX_INT_FLAGS); 2068 schedule_work(&queue->tx_error_task); 2069 macb_queue_isr_clear(bp, queue, MACB_TX_ERR_FLAGS); 2070 return -1; 2071 } 2072 2073 /* Link change detection isn't possible with RMII, so we'll 2074 * add that if/when we get our hands on a full-blown MII PHY. 2075 */ 2076 2077 /* There is a hardware issue under heavy load where DMA can 2078 * stop, this causes endless "used buffer descriptor read" 2079 * interrupts but it can be cleared by re-enabling RX. See 2080 * the at91rm9200 manual, section 41.3.1 or the Zynq manual 2081 * section 16.7.4 for details. RXUBR is only enabled for 2082 * these two versions. 2083 */ 2084 if (status & MACB_BIT(RXUBR)) { 2085 ctrl = macb_readl(bp, NCR); 2086 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE)); 2087 wmb(); 2088 macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); 2089 macb_queue_isr_clear(bp, queue, MACB_BIT(RXUBR)); 2090 } 2091 2092 if (status & MACB_BIT(ISR_ROVR)) { 2093 /* We missed at least one packet */ 2094 spin_lock(&bp->stats_lock); 2095 if (macb_is_gem(bp)) 2096 bp->hw_stats.gem.rx_overruns++; 2097 else 2098 bp->hw_stats.macb.rx_overruns++; 2099 spin_unlock(&bp->stats_lock); 2100 macb_queue_isr_clear(bp, queue, MACB_BIT(ISR_ROVR)); 2101 } 2102 2103 if (status & MACB_BIT(HRESP)) { 2104 queue_work(system_bh_wq, &bp->hresp_err_bh_work); 2105 netdev_err(netdev, "DMA bus error: HRESP not OK\n"); 2106 macb_queue_isr_clear(bp, queue, MACB_BIT(HRESP)); 2107 } 2108 2109 if (macb_is_gem(bp)) { 2110 if (status & GEM_BIT(WOL)) 2111 gem_wol_interrupt(queue, status); 2112 } else { 2113 if (status & MACB_BIT(WOL)) 2114 macb_wol_interrupt(queue, status); 2115 } 2116 2117 return 0; 2118 } 2119 2120 static irqreturn_t macb_interrupt(int irq, void *dev_id) 2121 { 2122 struct macb_queue *queue = dev_id; 2123 struct macb *bp = queue->bp; 2124 struct net_device *netdev = bp->netdev; 2125 u32 status; 2126 2127 status = queue_readl(queue, ISR); 2128 2129 if (unlikely(!status)) 2130 return IRQ_NONE; 2131 2132 spin_lock(&bp->lock); 2133 2134 while (status) { 2135 /* close possible race with dev_close */ 2136 if (unlikely(!netif_running(netdev))) { 2137 queue_writel(queue, IDR, -1); 2138 macb_queue_isr_clear(bp, queue, -1); 2139 break; 2140 } 2141 2142 netdev_vdbg(netdev, "queue = %u, isr = 0x%08lx\n", 2143 (unsigned int)(queue - bp->queues), 2144 (unsigned long)status); 2145 2146 if (status & bp->rx_intr_mask) { 2147 /* There's no point taking any more interrupts 2148 * until we have processed the buffers. The 2149 * scheduling call may fail if the poll routine 2150 * is already scheduled, so disable interrupts 2151 * now. 2152 */ 2153 queue_writel(queue, IDR, bp->rx_intr_mask); 2154 macb_queue_isr_clear(bp, queue, MACB_BIT(RCOMP)); 2155 napi_schedule_irqoff(&queue->napi_rx); 2156 } 2157 2158 if (status & (MACB_BIT(TCOMP) | 2159 MACB_BIT(TXUBR))) { 2160 queue_writel(queue, IDR, MACB_BIT(TCOMP)); 2161 macb_queue_isr_clear(bp, queue, MACB_BIT(TCOMP) | 2162 MACB_BIT(TXUBR)); 2163 if (status & MACB_BIT(TXUBR)) { 2164 queue->txubr_pending = true; 2165 wmb(); // ensure softirq can see update 2166 } 2167 2168 napi_schedule_irqoff(&queue->napi_tx); 2169 } 2170 2171 if (unlikely(status & MACB_INT_MISC_FLAGS)) 2172 if (macb_interrupt_misc(queue, status)) 2173 break; 2174 2175 status = queue_readl(queue, ISR); 2176 } 2177 2178 spin_unlock(&bp->lock); 2179 2180 return IRQ_HANDLED; 2181 } 2182 2183 #ifdef CONFIG_NET_POLL_CONTROLLER 2184 /* Polling receive - used by netconsole and other diagnostic tools 2185 * to allow network i/o with interrupts disabled. 2186 */ 2187 static void macb_poll_controller(struct net_device *netdev) 2188 { 2189 struct macb *bp = netdev_priv(netdev); 2190 struct macb_queue *queue; 2191 unsigned long flags; 2192 unsigned int q; 2193 2194 local_irq_save(flags); 2195 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) 2196 macb_interrupt(netdev->irq, queue); 2197 local_irq_restore(flags); 2198 } 2199 #endif 2200 2201 static unsigned int macb_tx_map(struct macb *bp, 2202 struct macb_queue *queue, 2203 struct sk_buff *skb, 2204 unsigned int hdrlen, 2205 u8 fcs_len) 2206 { 2207 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags; 2208 unsigned int len, i, tx_head = queue->tx_head; 2209 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0; 2210 unsigned int eof = 1, mss_mfs = 0; 2211 struct macb_tx_skb *tx_skb = NULL; 2212 struct macb_dma_desc *desc; 2213 unsigned int offset, size; 2214 dma_addr_t mapping; 2215 2216 /* LSO */ 2217 if (skb_shinfo(skb)->gso_size != 0) { 2218 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 2219 /* UDP - UFO */ 2220 lso_ctrl = MACB_LSO_UFO_ENABLE; 2221 else 2222 /* TCP - TSO */ 2223 lso_ctrl = MACB_LSO_TSO_ENABLE; 2224 } 2225 2226 /* First, map non-paged data */ 2227 len = skb_headlen(skb); 2228 2229 /* first buffer length */ 2230 size = hdrlen; 2231 2232 offset = 0; 2233 while (len) { 2234 tx_skb = macb_tx_skb(queue, tx_head); 2235 2236 mapping = dma_map_single(&bp->pdev->dev, 2237 skb->data + offset, 2238 size, DMA_TO_DEVICE); 2239 if (dma_mapping_error(&bp->pdev->dev, mapping)) 2240 goto dma_error; 2241 2242 /* Save info to properly release resources */ 2243 tx_skb->skb = NULL; 2244 tx_skb->mapping = mapping; 2245 tx_skb->size = size; 2246 tx_skb->mapped_as_page = false; 2247 2248 len -= size; 2249 offset += size; 2250 tx_head++; 2251 2252 size = umin(len, bp->max_tx_length); 2253 } 2254 2255 /* Then, map paged data from fragments */ 2256 for (f = 0; f < nr_frags; f++) { 2257 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 2258 2259 len = skb_frag_size(frag); 2260 offset = 0; 2261 while (len) { 2262 size = umin(len, bp->max_tx_length); 2263 tx_skb = macb_tx_skb(queue, tx_head); 2264 2265 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 2266 offset, size, DMA_TO_DEVICE); 2267 if (dma_mapping_error(&bp->pdev->dev, mapping)) 2268 goto dma_error; 2269 2270 /* Save info to properly release resources */ 2271 tx_skb->skb = NULL; 2272 tx_skb->mapping = mapping; 2273 tx_skb->size = size; 2274 tx_skb->mapped_as_page = true; 2275 2276 len -= size; 2277 offset += size; 2278 tx_head++; 2279 } 2280 } 2281 2282 /* Should never happen */ 2283 if (unlikely(!tx_skb)) { 2284 netdev_err(bp->netdev, "BUG! empty skb!\n"); 2285 return 0; 2286 } 2287 2288 /* This is the last buffer of the frame: save socket buffer */ 2289 tx_skb->skb = skb; 2290 tx_skb->fcs_len = fcs_len; 2291 2292 /* Update TX ring: update buffer descriptors in reverse order 2293 * to avoid race condition 2294 */ 2295 2296 /* Set 'TX_USED' bit in buffer descriptor at tx_head position 2297 * to set the end of TX queue 2298 */ 2299 i = tx_head; 2300 ctrl = MACB_BIT(TX_USED); 2301 desc = macb_tx_desc(queue, i); 2302 desc->ctrl = ctrl; 2303 2304 if (lso_ctrl) { 2305 if (lso_ctrl == MACB_LSO_UFO_ENABLE) 2306 /* include header and FCS in value given to h/w */ 2307 mss_mfs = skb_shinfo(skb)->gso_size + 2308 skb_transport_offset(skb) + 2309 ETH_FCS_LEN; 2310 else /* TSO */ { 2311 mss_mfs = skb_shinfo(skb)->gso_size; 2312 /* TCP Sequence Number Source Select 2313 * can be set only for TSO 2314 */ 2315 seq_ctrl = 0; 2316 } 2317 } 2318 2319 do { 2320 i--; 2321 tx_skb = macb_tx_skb(queue, i); 2322 desc = macb_tx_desc(queue, i); 2323 2324 ctrl = (u32)tx_skb->size; 2325 if (eof) { 2326 ctrl |= MACB_BIT(TX_LAST); 2327 eof = 0; 2328 } 2329 if (unlikely(macb_tx_ring_wrap(bp, i) == bp->tx_ring_size - 1)) 2330 ctrl |= MACB_BIT(TX_WRAP); 2331 2332 /* First descriptor is header descriptor */ 2333 if (i == queue->tx_head) { 2334 ctrl |= MACB_BF(TX_LSO, lso_ctrl); 2335 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl); 2336 if ((bp->netdev->features & NETIF_F_HW_CSUM) && 2337 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl && 2338 !ptp_one_step_sync(skb)) 2339 ctrl |= MACB_BIT(TX_NOCRC); 2340 } else 2341 /* Only set MSS/MFS on payload descriptors 2342 * (second or later descriptor) 2343 */ 2344 ctrl |= MACB_BF(MSS_MFS, mss_mfs); 2345 2346 /* Set TX buffer descriptor */ 2347 macb_set_addr(bp, desc, tx_skb->mapping); 2348 /* desc->addr must be visible to hardware before clearing 2349 * 'TX_USED' bit in desc->ctrl. 2350 */ 2351 wmb(); 2352 desc->ctrl = ctrl; 2353 } while (i != queue->tx_head); 2354 2355 queue->tx_head = tx_head; 2356 2357 return 0; 2358 2359 dma_error: 2360 netdev_err(bp->netdev, "TX DMA map failed\n"); 2361 2362 for (i = queue->tx_head; i != tx_head; i++) { 2363 tx_skb = macb_tx_skb(queue, i); 2364 2365 macb_tx_unmap(bp, tx_skb, 0); 2366 } 2367 2368 return -ENOMEM; 2369 } 2370 2371 static netdev_features_t macb_features_check(struct sk_buff *skb, 2372 struct net_device *netdev, 2373 netdev_features_t features) 2374 { 2375 unsigned int nr_frags, f; 2376 unsigned int hdrlen; 2377 2378 /* Validate LSO compatibility */ 2379 2380 /* there is only one buffer or protocol is not UDP */ 2381 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP)) 2382 return features; 2383 2384 /* length of header */ 2385 hdrlen = skb_transport_offset(skb); 2386 2387 /* For UFO only: 2388 * When software supplies two or more payload buffers all payload buffers 2389 * apart from the last must be a multiple of 8 bytes in size. 2390 */ 2391 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN)) 2392 return features & ~MACB_NETIF_LSO; 2393 2394 nr_frags = skb_shinfo(skb)->nr_frags; 2395 /* No need to check last fragment */ 2396 nr_frags--; 2397 for (f = 0; f < nr_frags; f++) { 2398 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 2399 2400 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN)) 2401 return features & ~MACB_NETIF_LSO; 2402 } 2403 return features; 2404 } 2405 2406 static inline int macb_clear_csum(struct sk_buff *skb) 2407 { 2408 /* no change for packets without checksum offloading */ 2409 if (skb->ip_summed != CHECKSUM_PARTIAL) 2410 return 0; 2411 2412 /* make sure we can modify the header */ 2413 if (unlikely(skb_cow_head(skb, 0))) 2414 return -1; 2415 2416 /* initialize checksum field 2417 * This is required - at least for Zynq, which otherwise calculates 2418 * wrong UDP header checksums for UDP packets with UDP data len <=2 2419 */ 2420 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0; 2421 return 0; 2422 } 2423 2424 /* Returns a negative errno, or the FCS bytes appended (0 or ETH_FCS_LEN). */ 2425 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *netdev) 2426 { 2427 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) || 2428 skb_is_nonlinear(*skb); 2429 int padlen = ETH_ZLEN - (*skb)->len; 2430 int tailroom = skb_tailroom(*skb); 2431 struct sk_buff *nskb; 2432 u32 fcs; 2433 2434 if (!(netdev->features & NETIF_F_HW_CSUM) || 2435 !((*skb)->ip_summed != CHECKSUM_PARTIAL) || 2436 skb_shinfo(*skb)->gso_size || ptp_one_step_sync(*skb)) 2437 return 0; 2438 2439 if (padlen <= 0) { 2440 /* FCS could be appeded to tailroom. */ 2441 if (tailroom >= ETH_FCS_LEN) 2442 goto add_fcs; 2443 /* No room for FCS, need to reallocate skb. */ 2444 else 2445 padlen = ETH_FCS_LEN; 2446 } else { 2447 /* Add room for FCS. */ 2448 padlen += ETH_FCS_LEN; 2449 } 2450 2451 if (cloned || tailroom < padlen) { 2452 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC); 2453 if (!nskb) 2454 return -ENOMEM; 2455 2456 dev_consume_skb_any(*skb); 2457 *skb = nskb; 2458 } 2459 2460 if (padlen > ETH_FCS_LEN) 2461 skb_put_zero(*skb, padlen - ETH_FCS_LEN); 2462 2463 add_fcs: 2464 /* set FCS to packet */ 2465 fcs = crc32_le(~0, (*skb)->data, (*skb)->len); 2466 fcs = ~fcs; 2467 2468 skb_put_u8(*skb, fcs & 0xff); 2469 skb_put_u8(*skb, (fcs >> 8) & 0xff); 2470 skb_put_u8(*skb, (fcs >> 16) & 0xff); 2471 skb_put_u8(*skb, (fcs >> 24) & 0xff); 2472 2473 return ETH_FCS_LEN; 2474 } 2475 2476 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, 2477 struct net_device *netdev) 2478 { 2479 struct macb *bp = netdev_priv(netdev); 2480 unsigned int q = skb_get_queue_mapping(skb); 2481 unsigned int desc_cnt, nr_frags, frag_size, f; 2482 struct macb_queue *queue = &bp->queues[q]; 2483 netdev_tx_t ret = NETDEV_TX_OK; 2484 unsigned int hdrlen; 2485 unsigned long flags; 2486 int fcs_len; 2487 bool is_lso; 2488 2489 if (macb_clear_csum(skb)) { 2490 dev_kfree_skb_any(skb); 2491 return ret; 2492 } 2493 2494 fcs_len = macb_pad_and_fcs(&skb, netdev); 2495 if (fcs_len < 0) { 2496 dev_kfree_skb_any(skb); 2497 return ret; 2498 } 2499 2500 if (macb_dma_ptp(bp) && 2501 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 2502 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2503 2504 is_lso = (skb_shinfo(skb)->gso_size != 0); 2505 2506 if (is_lso) { 2507 /* length of headers */ 2508 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 2509 /* only queue eth + ip headers separately for UDP */ 2510 hdrlen = skb_transport_offset(skb); 2511 else 2512 hdrlen = skb_tcp_all_headers(skb); 2513 if (skb_headlen(skb) < hdrlen) { 2514 netdev_err(bp->netdev, "Error - LSO headers fragmented!!!\n"); 2515 /* if this is required, would need to copy to single buffer */ 2516 return NETDEV_TX_BUSY; 2517 } 2518 } else 2519 hdrlen = umin(skb_headlen(skb), bp->max_tx_length); 2520 2521 #if defined(DEBUG) && defined(VERBOSE_DEBUG) 2522 netdev_vdbg(bp->netdev, 2523 "start_xmit: queue %u len %u head %p data %p tail %p end %p\n", 2524 q, skb->len, skb->head, skb->data, 2525 skb_tail_pointer(skb), skb_end_pointer(skb)); 2526 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, 2527 skb->data, 16, true); 2528 #endif 2529 2530 /* Count how many TX buffer descriptors are needed to send this 2531 * socket buffer: skb fragments of jumbo frames may need to be 2532 * split into many buffer descriptors. 2533 */ 2534 if (is_lso && (skb_headlen(skb) > hdrlen)) 2535 /* extra header descriptor if also payload in first buffer */ 2536 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1; 2537 else 2538 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length); 2539 nr_frags = skb_shinfo(skb)->nr_frags; 2540 for (f = 0; f < nr_frags; f++) { 2541 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); 2542 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length); 2543 } 2544 2545 spin_lock_irqsave(&queue->tx_ptr_lock, flags); 2546 2547 /* This is a hard error, log it. */ 2548 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, 2549 bp->tx_ring_size) < desc_cnt) { 2550 netif_stop_subqueue(netdev, q); 2551 netdev_dbg(netdev, "tx_head = %u, tx_tail = %u\n", 2552 queue->tx_head, queue->tx_tail); 2553 ret = NETDEV_TX_BUSY; 2554 goto unlock; 2555 } 2556 2557 /* Map socket buffer for DMA transfer */ 2558 if (macb_tx_map(bp, queue, skb, hdrlen, fcs_len)) { 2559 dev_kfree_skb_any(skb); 2560 goto unlock; 2561 } 2562 2563 /* Make newly initialized descriptor visible to hardware */ 2564 wmb(); 2565 skb_tx_timestamp(skb); 2566 netdev_tx_sent_queue(netdev_get_tx_queue(bp->netdev, q), 2567 skb->len); 2568 2569 spin_lock(&bp->lock); 2570 macb_tx_lpi_wake(bp); 2571 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 2572 spin_unlock(&bp->lock); 2573 2574 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1) 2575 netif_stop_subqueue(netdev, q); 2576 2577 unlock: 2578 spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 2579 2580 return ret; 2581 } 2582 2583 static void macb_init_rx_buffer_size(struct macb *bp, size_t size) 2584 { 2585 if (!macb_is_gem(bp)) { 2586 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE; 2587 } else { 2588 bp->rx_buffer_size = MIN(size, RX_BUFFER_MAX); 2589 2590 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) { 2591 netdev_dbg(bp->netdev, 2592 "RX buffer must be multiple of %d bytes, expanding\n", 2593 RX_BUFFER_MULTIPLE); 2594 bp->rx_buffer_size = 2595 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE); 2596 } 2597 } 2598 2599 netdev_dbg(bp->netdev, "mtu [%u] rx_buffer_size [%zu]\n", 2600 bp->netdev->mtu, bp->rx_buffer_size); 2601 } 2602 2603 static void gem_free_rx_buffers(struct macb *bp) 2604 { 2605 struct sk_buff *skb; 2606 struct macb_dma_desc *desc; 2607 struct macb_queue *queue; 2608 dma_addr_t addr; 2609 unsigned int q; 2610 int i; 2611 2612 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2613 if (!queue->rx_skbuff) 2614 continue; 2615 2616 for (i = 0; i < bp->rx_ring_size; i++) { 2617 skb = queue->rx_skbuff[i]; 2618 2619 if (!skb) 2620 continue; 2621 2622 desc = macb_rx_desc(queue, i); 2623 addr = macb_get_addr(bp, desc); 2624 2625 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size, 2626 DMA_FROM_DEVICE); 2627 dev_kfree_skb_any(skb); 2628 skb = NULL; 2629 } 2630 2631 kfree(queue->rx_skbuff); 2632 queue->rx_skbuff = NULL; 2633 } 2634 } 2635 2636 static void macb_free_rx_buffers(struct macb *bp) 2637 { 2638 struct macb_queue *queue = &bp->queues[0]; 2639 2640 if (queue->rx_buffers) { 2641 dma_free_coherent(&bp->pdev->dev, 2642 bp->rx_ring_size * bp->rx_buffer_size, 2643 queue->rx_buffers, queue->rx_buffers_dma); 2644 queue->rx_buffers = NULL; 2645 } 2646 } 2647 2648 static unsigned int macb_tx_ring_size_per_queue(struct macb *bp) 2649 { 2650 return macb_dma_desc_get_size(bp) * bp->tx_ring_size + bp->tx_bd_rd_prefetch; 2651 } 2652 2653 static unsigned int macb_rx_ring_size_per_queue(struct macb *bp) 2654 { 2655 return macb_dma_desc_get_size(bp) * bp->rx_ring_size + bp->rx_bd_rd_prefetch; 2656 } 2657 2658 static void macb_free(struct macb *bp) 2659 { 2660 struct device *dev = &bp->pdev->dev; 2661 struct macb_queue *queue; 2662 unsigned int q; 2663 size_t size; 2664 2665 bp->macbgem_ops.mog_free_rx_buffers(bp); 2666 2667 size = bp->num_queues * macb_tx_ring_size_per_queue(bp); 2668 dma_free_coherent(dev, size, bp->queues[0].tx_ring, bp->queues[0].tx_ring_dma); 2669 2670 size = bp->num_queues * macb_rx_ring_size_per_queue(bp); 2671 dma_free_coherent(dev, size, bp->queues[0].rx_ring, bp->queues[0].rx_ring_dma); 2672 2673 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2674 if (queue->tx_skb) { 2675 unsigned int dropped = 0, tail; 2676 2677 for (tail = queue->tx_tail; tail != queue->tx_head; 2678 tail++) { 2679 if (macb_tx_skb(queue, tail)->skb) 2680 dropped++; 2681 macb_tx_unmap(bp, macb_tx_skb(queue, tail), 0); 2682 } 2683 2684 queue->stats.tx_dropped += dropped; 2685 bp->netdev->stats.tx_dropped += dropped; 2686 2687 kfree(queue->tx_skb); 2688 queue->tx_skb = NULL; 2689 } 2690 2691 queue->tx_head = 0; 2692 queue->tx_tail = 0; 2693 queue->tx_ring = NULL; 2694 queue->rx_ring = NULL; 2695 } 2696 } 2697 2698 static int gem_alloc_rx_buffers(struct macb *bp) 2699 { 2700 struct macb_queue *queue; 2701 unsigned int q; 2702 int size; 2703 2704 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2705 size = bp->rx_ring_size * sizeof(struct sk_buff *); 2706 queue->rx_skbuff = kzalloc(size, GFP_KERNEL); 2707 if (!queue->rx_skbuff) 2708 return -ENOMEM; 2709 else 2710 netdev_dbg(bp->netdev, 2711 "Allocated %d RX struct sk_buff entries at %p\n", 2712 bp->rx_ring_size, queue->rx_skbuff); 2713 } 2714 return 0; 2715 } 2716 2717 static int macb_alloc_rx_buffers(struct macb *bp) 2718 { 2719 struct macb_queue *queue = &bp->queues[0]; 2720 int size; 2721 2722 size = bp->rx_ring_size * bp->rx_buffer_size; 2723 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, 2724 &queue->rx_buffers_dma, GFP_KERNEL); 2725 if (!queue->rx_buffers) 2726 return -ENOMEM; 2727 2728 netdev_dbg(bp->netdev, 2729 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", 2730 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers); 2731 return 0; 2732 } 2733 2734 static int macb_alloc(struct macb *bp) 2735 { 2736 struct device *dev = &bp->pdev->dev; 2737 dma_addr_t tx_dma, rx_dma; 2738 struct macb_queue *queue; 2739 unsigned int q; 2740 void *tx, *rx; 2741 size_t size; 2742 2743 /* 2744 * Upper 32-bits of Tx/Rx DMA descriptor for each queues much match! 2745 * We cannot enforce this guarantee, the best we can do is do a single 2746 * allocation and hope it will land into alloc_pages() that guarantees 2747 * natural alignment of physical addresses. 2748 */ 2749 2750 size = bp->num_queues * macb_tx_ring_size_per_queue(bp); 2751 tx = dma_alloc_coherent(dev, size, &tx_dma, GFP_KERNEL); 2752 if (!tx || upper_32_bits(tx_dma) != upper_32_bits(tx_dma + size - 1)) 2753 goto out_err; 2754 netdev_dbg(bp->netdev, "Allocated %zu bytes for %u TX rings at %08lx (mapped %p)\n", 2755 size, bp->num_queues, (unsigned long)tx_dma, tx); 2756 2757 size = bp->num_queues * macb_rx_ring_size_per_queue(bp); 2758 rx = dma_alloc_coherent(dev, size, &rx_dma, GFP_KERNEL); 2759 if (!rx || upper_32_bits(rx_dma) != upper_32_bits(rx_dma + size - 1)) 2760 goto out_err; 2761 netdev_dbg(bp->netdev, "Allocated %zu bytes for %u RX rings at %08lx (mapped %p)\n", 2762 size, bp->num_queues, (unsigned long)rx_dma, rx); 2763 2764 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2765 queue->tx_ring = tx + macb_tx_ring_size_per_queue(bp) * q; 2766 queue->tx_ring_dma = tx_dma + macb_tx_ring_size_per_queue(bp) * q; 2767 2768 queue->rx_ring = rx + macb_rx_ring_size_per_queue(bp) * q; 2769 queue->rx_ring_dma = rx_dma + macb_rx_ring_size_per_queue(bp) * q; 2770 2771 size = bp->tx_ring_size * sizeof(struct macb_tx_skb); 2772 queue->tx_skb = kmalloc(size, GFP_KERNEL); 2773 if (!queue->tx_skb) 2774 goto out_err; 2775 } 2776 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp)) 2777 goto out_err; 2778 2779 return 0; 2780 2781 out_err: 2782 macb_free(bp); 2783 return -ENOMEM; 2784 } 2785 2786 static void gem_init_rx_ring(struct macb_queue *queue) 2787 { 2788 queue->rx_tail = 0; 2789 queue->rx_prepared_head = 0; 2790 2791 gem_rx_refill(queue); 2792 } 2793 2794 static void gem_init_rings(struct macb *bp) 2795 { 2796 struct macb_queue *queue; 2797 struct macb_dma_desc *desc = NULL; 2798 unsigned int q; 2799 int i; 2800 2801 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2802 for (i = 0; i < bp->tx_ring_size; i++) { 2803 desc = macb_tx_desc(queue, i); 2804 macb_set_addr(bp, desc, 0); 2805 desc->ctrl = MACB_BIT(TX_USED); 2806 } 2807 desc->ctrl |= MACB_BIT(TX_WRAP); 2808 queue->tx_head = 0; 2809 queue->tx_tail = 0; 2810 2811 gem_init_rx_ring(queue); 2812 } 2813 } 2814 2815 static void macb_init_rings(struct macb *bp) 2816 { 2817 int i; 2818 struct macb_dma_desc *desc = NULL; 2819 2820 macb_init_rx_ring(&bp->queues[0]); 2821 2822 for (i = 0; i < bp->tx_ring_size; i++) { 2823 desc = macb_tx_desc(&bp->queues[0], i); 2824 macb_set_addr(bp, desc, 0); 2825 desc->ctrl = MACB_BIT(TX_USED); 2826 } 2827 bp->queues[0].tx_head = 0; 2828 bp->queues[0].tx_tail = 0; 2829 desc->ctrl |= MACB_BIT(TX_WRAP); 2830 } 2831 2832 static void macb_reset_hw(struct macb *bp) 2833 { 2834 struct macb_queue *queue; 2835 unsigned int q; 2836 u32 ctrl = macb_readl(bp, NCR); 2837 2838 /* Disable RX and TX (XXX: Should we halt the transmission 2839 * more gracefully?) 2840 */ 2841 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE)); 2842 2843 /* Clear the stats registers (XXX: Update stats first?) */ 2844 ctrl |= MACB_BIT(CLRSTAT); 2845 2846 macb_writel(bp, NCR, ctrl); 2847 2848 /* Clear all status flags */ 2849 macb_writel(bp, TSR, -1); 2850 macb_writel(bp, RSR, -1); 2851 2852 /* Disable RX partial store and forward and reset watermark value */ 2853 gem_writel(bp, PBUFRXCUT, 0); 2854 2855 /* Disable all interrupts */ 2856 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2857 queue_writel(queue, IDR, -1); 2858 queue_readl(queue, ISR); 2859 macb_queue_isr_clear(bp, queue, -1); 2860 } 2861 } 2862 2863 static u32 gem_mdc_clk_div(struct macb *bp) 2864 { 2865 u32 config; 2866 unsigned long pclk_hz = clk_get_rate(bp->pclk); 2867 2868 if (pclk_hz <= 20000000) 2869 config = GEM_BF(CLK, GEM_CLK_DIV8); 2870 else if (pclk_hz <= 40000000) 2871 config = GEM_BF(CLK, GEM_CLK_DIV16); 2872 else if (pclk_hz <= 80000000) 2873 config = GEM_BF(CLK, GEM_CLK_DIV32); 2874 else if (pclk_hz <= 120000000) 2875 config = GEM_BF(CLK, GEM_CLK_DIV48); 2876 else if (pclk_hz <= 160000000) 2877 config = GEM_BF(CLK, GEM_CLK_DIV64); 2878 else if (pclk_hz <= 240000000) 2879 config = GEM_BF(CLK, GEM_CLK_DIV96); 2880 else if (pclk_hz <= 320000000) 2881 config = GEM_BF(CLK, GEM_CLK_DIV128); 2882 else 2883 config = GEM_BF(CLK, GEM_CLK_DIV224); 2884 2885 return config; 2886 } 2887 2888 static u32 macb_mdc_clk_div(struct macb *bp) 2889 { 2890 u32 config; 2891 unsigned long pclk_hz; 2892 2893 if (macb_is_gem(bp)) 2894 return gem_mdc_clk_div(bp); 2895 2896 pclk_hz = clk_get_rate(bp->pclk); 2897 if (pclk_hz <= 20000000) 2898 config = MACB_BF(CLK, MACB_CLK_DIV8); 2899 else if (pclk_hz <= 40000000) 2900 config = MACB_BF(CLK, MACB_CLK_DIV16); 2901 else if (pclk_hz <= 80000000) 2902 config = MACB_BF(CLK, MACB_CLK_DIV32); 2903 else 2904 config = MACB_BF(CLK, MACB_CLK_DIV64); 2905 2906 return config; 2907 } 2908 2909 /* Get the DMA bus width field of the network configuration register that we 2910 * should program. We find the width from decoding the design configuration 2911 * register to find the maximum supported data bus width. 2912 */ 2913 static u32 macb_dbw(struct macb *bp) 2914 { 2915 if (!macb_is_gem(bp)) 2916 return 0; 2917 2918 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { 2919 case 4: 2920 return GEM_BF(DBW, GEM_DBW128); 2921 case 2: 2922 return GEM_BF(DBW, GEM_DBW64); 2923 case 1: 2924 default: 2925 return GEM_BF(DBW, GEM_DBW32); 2926 } 2927 } 2928 2929 /* Configure the receive DMA engine 2930 * - use the correct receive buffer size 2931 * - set best burst length for DMA operations 2932 * (if not supported by FIFO, it will fallback to default) 2933 * - set both rx/tx packet buffers to full memory size 2934 * These are configurable parameters for GEM. 2935 */ 2936 static void macb_configure_dma(struct macb *bp) 2937 { 2938 struct macb_queue *queue; 2939 u32 buffer_size; 2940 unsigned int q; 2941 u32 dmacfg; 2942 2943 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE; 2944 if (macb_is_gem(bp)) { 2945 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); 2946 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2947 if (q) 2948 queue_writel(queue, RBQS, buffer_size); 2949 else 2950 dmacfg |= GEM_BF(RXBS, buffer_size); 2951 } 2952 if (bp->dma_burst_length) 2953 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg); 2954 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); 2955 dmacfg &= ~GEM_BIT(ENDIA_PKT); 2956 2957 if (bp->native_io) 2958 dmacfg &= ~GEM_BIT(ENDIA_DESC); 2959 else 2960 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */ 2961 2962 if (bp->netdev->features & NETIF_F_HW_CSUM) 2963 dmacfg |= GEM_BIT(TXCOEN); 2964 else 2965 dmacfg &= ~GEM_BIT(TXCOEN); 2966 2967 dmacfg &= ~GEM_BIT(ADDR64); 2968 if (macb_dma64(bp)) 2969 dmacfg |= GEM_BIT(ADDR64); 2970 if (macb_dma_ptp(bp)) 2971 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT); 2972 netdev_dbg(bp->netdev, "Cadence configure DMA with 0x%08x\n", 2973 dmacfg); 2974 gem_writel(bp, DMACFG, dmacfg); 2975 } 2976 } 2977 2978 static void macb_init_hw(struct macb *bp) 2979 { 2980 u32 config; 2981 2982 macb_reset_hw(bp); 2983 macb_set_hwaddr(bp); 2984 2985 config = macb_mdc_clk_div(bp); 2986 /* Make eth data aligned. 2987 * If RSC capable, that offset is ignored by HW. 2988 */ 2989 if (!(bp->caps & MACB_CAPS_RSC)) 2990 config |= MACB_BF(RBOF, NET_IP_ALIGN); 2991 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ 2992 if (bp->caps & MACB_CAPS_JUMBO) 2993 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */ 2994 else 2995 config |= MACB_BIT(BIG); /* Receive oversized frames */ 2996 if (bp->netdev->flags & IFF_PROMISC) 2997 config |= MACB_BIT(CAF); /* Copy All Frames */ 2998 else if (macb_is_gem(bp) && bp->netdev->features & NETIF_F_RXCSUM) 2999 config |= GEM_BIT(RXCOEN); 3000 if (!(bp->netdev->flags & IFF_BROADCAST)) 3001 config |= MACB_BIT(NBC); /* No BroadCast */ 3002 config |= macb_dbw(bp); 3003 macb_writel(bp, NCFGR, config); 3004 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len) 3005 gem_writel(bp, JML, bp->jumbo_max_len); 3006 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK; 3007 if (bp->caps & MACB_CAPS_JUMBO) 3008 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK; 3009 3010 macb_configure_dma(bp); 3011 3012 /* Enable RX partial store and forward and set watermark */ 3013 if (bp->rx_watermark) 3014 gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU))); 3015 } 3016 3017 /* The hash address register is 64 bits long and takes up two 3018 * locations in the memory map. The least significant bits are stored 3019 * in EMAC_HSL and the most significant bits in EMAC_HSH. 3020 * 3021 * The unicast hash enable and the multicast hash enable bits in the 3022 * network configuration register enable the reception of hash matched 3023 * frames. The destination address is reduced to a 6 bit index into 3024 * the 64 bit hash register using the following hash function. The 3025 * hash function is an exclusive or of every sixth bit of the 3026 * destination address. 3027 * 3028 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] 3029 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] 3030 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] 3031 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] 3032 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] 3033 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] 3034 * 3035 * da[0] represents the least significant bit of the first byte 3036 * received, that is, the multicast/unicast indicator, and da[47] 3037 * represents the most significant bit of the last byte received. If 3038 * the hash index, hi[n], points to a bit that is set in the hash 3039 * register then the frame will be matched according to whether the 3040 * frame is multicast or unicast. A multicast match will be signalled 3041 * if the multicast hash enable bit is set, da[0] is 1 and the hash 3042 * index points to a bit set in the hash register. A unicast match 3043 * will be signalled if the unicast hash enable bit is set, da[0] is 0 3044 * and the hash index points to a bit set in the hash register. To 3045 * receive all multicast frames, the hash register should be set with 3046 * all ones and the multicast hash enable bit should be set in the 3047 * network configuration register. 3048 */ 3049 3050 static inline int hash_bit_value(int bitnr, __u8 *addr) 3051 { 3052 if (addr[bitnr / 8] & (1 << (bitnr % 8))) 3053 return 1; 3054 return 0; 3055 } 3056 3057 /* Return the hash index value for the specified address. */ 3058 static int hash_get_index(__u8 *addr) 3059 { 3060 int i, j, bitval; 3061 int hash_index = 0; 3062 3063 for (j = 0; j < 6; j++) { 3064 for (i = 0, bitval = 0; i < 8; i++) 3065 bitval ^= hash_bit_value(i * 6 + j, addr); 3066 3067 hash_index |= (bitval << j); 3068 } 3069 3070 return hash_index; 3071 } 3072 3073 /* Add multicast addresses to the internal multicast-hash table. */ 3074 static void macb_sethashtable(struct net_device *netdev) 3075 { 3076 struct netdev_hw_addr *ha; 3077 unsigned long mc_filter[2]; 3078 unsigned int bitnr; 3079 struct macb *bp = netdev_priv(netdev); 3080 3081 mc_filter[0] = 0; 3082 mc_filter[1] = 0; 3083 3084 netdev_for_each_mc_addr(ha, netdev) { 3085 bitnr = hash_get_index(ha->addr); 3086 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); 3087 } 3088 3089 macb_or_gem_writel(bp, HRB, mc_filter[0]); 3090 macb_or_gem_writel(bp, HRT, mc_filter[1]); 3091 } 3092 3093 /* Enable/Disable promiscuous and multicast modes. */ 3094 static void macb_set_rx_mode(struct net_device *netdev) 3095 { 3096 unsigned long cfg; 3097 struct macb *bp = netdev_priv(netdev); 3098 3099 cfg = macb_readl(bp, NCFGR); 3100 3101 if (netdev->flags & IFF_PROMISC) { 3102 /* Enable promiscuous mode */ 3103 cfg |= MACB_BIT(CAF); 3104 3105 /* Disable RX checksum offload */ 3106 if (macb_is_gem(bp)) 3107 cfg &= ~GEM_BIT(RXCOEN); 3108 } else { 3109 /* Disable promiscuous mode */ 3110 cfg &= ~MACB_BIT(CAF); 3111 3112 /* Enable RX checksum offload only if requested */ 3113 if (macb_is_gem(bp) && netdev->features & NETIF_F_RXCSUM) 3114 cfg |= GEM_BIT(RXCOEN); 3115 } 3116 3117 if (netdev->flags & IFF_ALLMULTI) { 3118 /* Enable all multicast mode */ 3119 macb_or_gem_writel(bp, HRB, -1); 3120 macb_or_gem_writel(bp, HRT, -1); 3121 cfg |= MACB_BIT(NCFGR_MTI); 3122 } else if (!netdev_mc_empty(netdev)) { 3123 /* Enable specific multicasts */ 3124 macb_sethashtable(netdev); 3125 cfg |= MACB_BIT(NCFGR_MTI); 3126 } else if (netdev->flags & (~IFF_ALLMULTI)) { 3127 /* Disable all multicast mode */ 3128 macb_or_gem_writel(bp, HRB, 0); 3129 macb_or_gem_writel(bp, HRT, 0); 3130 cfg &= ~MACB_BIT(NCFGR_MTI); 3131 } 3132 3133 macb_writel(bp, NCFGR, cfg); 3134 } 3135 3136 static int macb_open(struct net_device *netdev) 3137 { 3138 size_t bufsz = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN; 3139 struct macb *bp = netdev_priv(netdev); 3140 struct macb_queue *queue; 3141 unsigned int q; 3142 int err; 3143 3144 netdev_dbg(bp->netdev, "open\n"); 3145 3146 err = pm_runtime_resume_and_get(&bp->pdev->dev); 3147 if (err < 0) 3148 return err; 3149 3150 /* RX buffers initialization */ 3151 macb_init_rx_buffer_size(bp, bufsz); 3152 3153 err = macb_alloc(bp); 3154 if (err) { 3155 netdev_err(netdev, "Unable to allocate DMA memory (error %d)\n", 3156 err); 3157 goto pm_exit; 3158 } 3159 3160 bp->macbgem_ops.mog_init_rings(bp); 3161 macb_init_buffers(bp); 3162 3163 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 3164 napi_enable(&queue->napi_rx); 3165 napi_enable(&queue->napi_tx); 3166 } 3167 3168 macb_init_hw(bp); 3169 3170 err = phy_set_mode_ext(bp->phy, PHY_MODE_ETHERNET, bp->phy_interface); 3171 if (err) 3172 goto reset_hw; 3173 3174 err = phy_power_on(bp->phy); 3175 if (err) 3176 goto reset_hw; 3177 3178 err = macb_phylink_connect(bp); 3179 if (err) 3180 goto phy_off; 3181 3182 netif_tx_start_all_queues(netdev); 3183 3184 if (bp->ptp_info) 3185 bp->ptp_info->ptp_init(netdev); 3186 3187 return 0; 3188 3189 phy_off: 3190 phy_power_off(bp->phy); 3191 3192 reset_hw: 3193 macb_reset_hw(bp); 3194 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 3195 napi_disable(&queue->napi_rx); 3196 napi_disable(&queue->napi_tx); 3197 } 3198 macb_free(bp); 3199 pm_exit: 3200 pm_runtime_put_sync(&bp->pdev->dev); 3201 return err; 3202 } 3203 3204 static int macb_close(struct net_device *netdev) 3205 { 3206 struct macb *bp = netdev_priv(netdev); 3207 struct macb_queue *queue; 3208 unsigned long flags; 3209 unsigned int q; 3210 3211 netif_tx_stop_all_queues(netdev); 3212 3213 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 3214 napi_disable(&queue->napi_rx); 3215 napi_disable(&queue->napi_tx); 3216 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, q)); 3217 } 3218 3219 cancel_delayed_work_sync(&bp->tx_lpi_work); 3220 3221 phylink_stop(bp->phylink); 3222 phylink_disconnect_phy(bp->phylink); 3223 3224 phy_power_off(bp->phy); 3225 3226 spin_lock_irqsave(&bp->lock, flags); 3227 macb_reset_hw(bp); 3228 netif_carrier_off(netdev); 3229 spin_unlock_irqrestore(&bp->lock, flags); 3230 3231 macb_free(bp); 3232 3233 if (bp->ptp_info) 3234 bp->ptp_info->ptp_remove(netdev); 3235 3236 pm_runtime_put(&bp->pdev->dev); 3237 3238 return 0; 3239 } 3240 3241 static int macb_change_mtu(struct net_device *netdev, int new_mtu) 3242 { 3243 if (netif_running(netdev)) 3244 return -EBUSY; 3245 3246 WRITE_ONCE(netdev->mtu, new_mtu); 3247 3248 return 0; 3249 } 3250 3251 static int macb_set_mac_addr(struct net_device *netdev, void *addr) 3252 { 3253 int err; 3254 3255 err = eth_mac_addr(netdev, addr); 3256 if (err < 0) 3257 return err; 3258 3259 macb_set_hwaddr(netdev_priv(netdev)); 3260 return 0; 3261 } 3262 3263 static void gem_update_stats(struct macb *bp) 3264 { 3265 struct macb_queue *queue; 3266 unsigned int i, q, idx; 3267 unsigned long *stat; 3268 3269 u64 *p = &bp->hw_stats.gem.tx_octets; 3270 3271 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { 3272 u32 offset = gem_statistics[i].offset; 3273 u64 val = bp->macb_reg_readl(bp, offset); 3274 3275 bp->ethtool_stats[i] += val; 3276 *p += val; 3277 3278 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { 3279 /* Add GEM_OCTTXH, GEM_OCTRXH */ 3280 val = bp->macb_reg_readl(bp, offset + 4); 3281 bp->ethtool_stats[i] += ((u64)val) << 32; 3282 *p += ((u64)val) << 32; 3283 } 3284 } 3285 3286 idx = GEM_STATS_LEN; 3287 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) 3288 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat) 3289 bp->ethtool_stats[idx++] = *stat; 3290 } 3291 3292 static void gem_get_stats(struct macb *bp, struct rtnl_link_stats64 *nstat) 3293 { 3294 struct gem_stats *hwstat = &bp->hw_stats.gem; 3295 3296 spin_lock_irq(&bp->stats_lock); 3297 if (netif_running(bp->netdev)) 3298 gem_update_stats(bp); 3299 3300 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + 3301 hwstat->rx_alignment_errors + 3302 hwstat->rx_resource_errors + 3303 hwstat->rx_overruns + 3304 hwstat->rx_oversize_frames + 3305 hwstat->rx_jabbers + 3306 hwstat->rx_undersized_frames + 3307 hwstat->rx_length_field_frame_errors); 3308 nstat->tx_errors = (hwstat->tx_late_collisions + 3309 hwstat->tx_excessive_collisions + 3310 hwstat->tx_underrun + 3311 hwstat->tx_carrier_sense_errors); 3312 nstat->multicast = hwstat->rx_multicast_frames; 3313 nstat->collisions = (hwstat->tx_single_collision_frames + 3314 hwstat->tx_multiple_collision_frames + 3315 hwstat->tx_excessive_collisions); 3316 nstat->rx_length_errors = (hwstat->rx_oversize_frames + 3317 hwstat->rx_jabbers + 3318 hwstat->rx_undersized_frames + 3319 hwstat->rx_length_field_frame_errors); 3320 nstat->rx_over_errors = hwstat->rx_resource_errors; 3321 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; 3322 nstat->rx_frame_errors = hwstat->rx_alignment_errors; 3323 nstat->rx_fifo_errors = hwstat->rx_overruns; 3324 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; 3325 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; 3326 nstat->tx_fifo_errors = hwstat->tx_underrun; 3327 spin_unlock_irq(&bp->stats_lock); 3328 } 3329 3330 static void gem_get_ethtool_stats(struct net_device *netdev, 3331 struct ethtool_stats *stats, u64 *data) 3332 { 3333 struct macb *bp = netdev_priv(netdev); 3334 3335 spin_lock_irq(&bp->stats_lock); 3336 gem_update_stats(bp); 3337 memcpy(data, &bp->ethtool_stats, sizeof(u64) 3338 * (GEM_STATS_LEN + QUEUE_STATS_LEN * bp->num_queues)); 3339 spin_unlock_irq(&bp->stats_lock); 3340 } 3341 3342 static int gem_get_sset_count(struct net_device *netdev, int sset) 3343 { 3344 struct macb *bp = netdev_priv(netdev); 3345 3346 switch (sset) { 3347 case ETH_SS_STATS: 3348 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN; 3349 default: 3350 return -EOPNOTSUPP; 3351 } 3352 } 3353 3354 static void gem_get_ethtool_strings(struct net_device *netdev, u32 sset, u8 *p) 3355 { 3356 struct macb *bp = netdev_priv(netdev); 3357 struct macb_queue *queue; 3358 unsigned int i; 3359 unsigned int q; 3360 3361 switch (sset) { 3362 case ETH_SS_STATS: 3363 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN) 3364 memcpy(p, gem_statistics[i].stat_string, 3365 ETH_GSTRING_LEN); 3366 3367 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 3368 for (i = 0; i < QUEUE_STATS_LEN; i++) 3369 ethtool_sprintf(&p, "q%u_%s", q, queue_statistics[i].stat_string); 3370 } 3371 break; 3372 } 3373 } 3374 3375 static void macb_get_stats(struct net_device *netdev, 3376 struct rtnl_link_stats64 *nstat) 3377 { 3378 struct macb *bp = netdev_priv(netdev); 3379 struct macb_stats *hwstat = &bp->hw_stats.macb; 3380 3381 netdev_stats_to_stats64(nstat, &bp->netdev->stats); 3382 if (macb_is_gem(bp)) { 3383 gem_get_stats(bp, nstat); 3384 return; 3385 } 3386 3387 /* read stats from hardware */ 3388 spin_lock_irq(&bp->stats_lock); 3389 macb_update_stats(bp); 3390 3391 /* Convert HW stats into netdevice stats */ 3392 nstat->rx_errors = (hwstat->rx_fcs_errors + 3393 hwstat->rx_align_errors + 3394 hwstat->rx_resource_errors + 3395 hwstat->rx_overruns + 3396 hwstat->rx_oversize_pkts + 3397 hwstat->rx_jabbers + 3398 hwstat->rx_undersize_pkts + 3399 hwstat->rx_length_mismatch); 3400 nstat->tx_errors = (hwstat->tx_late_cols + 3401 hwstat->tx_excessive_cols + 3402 hwstat->tx_underruns + 3403 hwstat->tx_carrier_errors + 3404 hwstat->sqe_test_errors); 3405 nstat->collisions = (hwstat->tx_single_cols + 3406 hwstat->tx_multiple_cols + 3407 hwstat->tx_excessive_cols); 3408 nstat->rx_length_errors = (hwstat->rx_oversize_pkts + 3409 hwstat->rx_jabbers + 3410 hwstat->rx_undersize_pkts + 3411 hwstat->rx_length_mismatch); 3412 nstat->rx_over_errors = hwstat->rx_resource_errors + 3413 hwstat->rx_overruns; 3414 nstat->rx_crc_errors = hwstat->rx_fcs_errors; 3415 nstat->rx_frame_errors = hwstat->rx_align_errors; 3416 nstat->rx_fifo_errors = hwstat->rx_overruns; 3417 /* XXX: What does "missed" mean? */ 3418 nstat->tx_aborted_errors = hwstat->tx_excessive_cols; 3419 nstat->tx_carrier_errors = hwstat->tx_carrier_errors; 3420 nstat->tx_fifo_errors = hwstat->tx_underruns; 3421 /* Don't know about heartbeat or window errors... */ 3422 spin_unlock_irq(&bp->stats_lock); 3423 } 3424 3425 static void macb_get_pause_stats(struct net_device *netdev, 3426 struct ethtool_pause_stats *pause_stats) 3427 { 3428 struct macb *bp = netdev_priv(netdev); 3429 struct macb_stats *hwstat = &bp->hw_stats.macb; 3430 3431 spin_lock_irq(&bp->stats_lock); 3432 macb_update_stats(bp); 3433 pause_stats->tx_pause_frames = hwstat->tx_pause_frames; 3434 pause_stats->rx_pause_frames = hwstat->rx_pause_frames; 3435 spin_unlock_irq(&bp->stats_lock); 3436 } 3437 3438 static void gem_get_pause_stats(struct net_device *netdev, 3439 struct ethtool_pause_stats *pause_stats) 3440 { 3441 struct macb *bp = netdev_priv(netdev); 3442 struct gem_stats *hwstat = &bp->hw_stats.gem; 3443 3444 spin_lock_irq(&bp->stats_lock); 3445 gem_update_stats(bp); 3446 pause_stats->tx_pause_frames = hwstat->tx_pause_frames; 3447 pause_stats->rx_pause_frames = hwstat->rx_pause_frames; 3448 spin_unlock_irq(&bp->stats_lock); 3449 } 3450 3451 static void macb_get_eth_mac_stats(struct net_device *netdev, 3452 struct ethtool_eth_mac_stats *mac_stats) 3453 { 3454 struct macb *bp = netdev_priv(netdev); 3455 struct macb_stats *hwstat = &bp->hw_stats.macb; 3456 3457 spin_lock_irq(&bp->stats_lock); 3458 macb_update_stats(bp); 3459 mac_stats->FramesTransmittedOK = hwstat->tx_ok; 3460 mac_stats->SingleCollisionFrames = hwstat->tx_single_cols; 3461 mac_stats->MultipleCollisionFrames = hwstat->tx_multiple_cols; 3462 mac_stats->FramesReceivedOK = hwstat->rx_ok; 3463 mac_stats->FrameCheckSequenceErrors = hwstat->rx_fcs_errors; 3464 mac_stats->AlignmentErrors = hwstat->rx_align_errors; 3465 mac_stats->FramesWithDeferredXmissions = hwstat->tx_deferred; 3466 mac_stats->LateCollisions = hwstat->tx_late_cols; 3467 mac_stats->FramesAbortedDueToXSColls = hwstat->tx_excessive_cols; 3468 mac_stats->FramesLostDueToIntMACXmitError = hwstat->tx_underruns; 3469 mac_stats->CarrierSenseErrors = hwstat->tx_carrier_errors; 3470 mac_stats->FramesLostDueToIntMACRcvError = hwstat->rx_overruns; 3471 mac_stats->InRangeLengthErrors = hwstat->rx_length_mismatch; 3472 mac_stats->FrameTooLongErrors = hwstat->rx_oversize_pkts; 3473 spin_unlock_irq(&bp->stats_lock); 3474 } 3475 3476 static void gem_get_eth_mac_stats(struct net_device *netdev, 3477 struct ethtool_eth_mac_stats *mac_stats) 3478 { 3479 struct macb *bp = netdev_priv(netdev); 3480 struct gem_stats *hwstat = &bp->hw_stats.gem; 3481 3482 spin_lock_irq(&bp->stats_lock); 3483 gem_update_stats(bp); 3484 mac_stats->FramesTransmittedOK = hwstat->tx_frames; 3485 mac_stats->SingleCollisionFrames = hwstat->tx_single_collision_frames; 3486 mac_stats->MultipleCollisionFrames = 3487 hwstat->tx_multiple_collision_frames; 3488 mac_stats->FramesReceivedOK = hwstat->rx_frames; 3489 mac_stats->FrameCheckSequenceErrors = 3490 hwstat->rx_frame_check_sequence_errors; 3491 mac_stats->AlignmentErrors = hwstat->rx_alignment_errors; 3492 mac_stats->OctetsTransmittedOK = hwstat->tx_octets; 3493 mac_stats->FramesWithDeferredXmissions = hwstat->tx_deferred_frames; 3494 mac_stats->LateCollisions = hwstat->tx_late_collisions; 3495 mac_stats->FramesAbortedDueToXSColls = hwstat->tx_excessive_collisions; 3496 mac_stats->FramesLostDueToIntMACXmitError = hwstat->tx_underrun; 3497 mac_stats->CarrierSenseErrors = hwstat->tx_carrier_sense_errors; 3498 mac_stats->OctetsReceivedOK = hwstat->rx_octets; 3499 mac_stats->MulticastFramesXmittedOK = hwstat->tx_multicast_frames; 3500 mac_stats->BroadcastFramesXmittedOK = hwstat->tx_broadcast_frames; 3501 mac_stats->MulticastFramesReceivedOK = hwstat->rx_multicast_frames; 3502 mac_stats->BroadcastFramesReceivedOK = hwstat->rx_broadcast_frames; 3503 mac_stats->InRangeLengthErrors = hwstat->rx_length_field_frame_errors; 3504 mac_stats->FrameTooLongErrors = hwstat->rx_oversize_frames; 3505 spin_unlock_irq(&bp->stats_lock); 3506 } 3507 3508 /* TODO: Report SQE test errors when added to phy_stats */ 3509 static void macb_get_eth_phy_stats(struct net_device *netdev, 3510 struct ethtool_eth_phy_stats *phy_stats) 3511 { 3512 struct macb *bp = netdev_priv(netdev); 3513 struct macb_stats *hwstat = &bp->hw_stats.macb; 3514 3515 spin_lock_irq(&bp->stats_lock); 3516 macb_update_stats(bp); 3517 phy_stats->SymbolErrorDuringCarrier = hwstat->rx_symbol_errors; 3518 spin_unlock_irq(&bp->stats_lock); 3519 } 3520 3521 static void gem_get_eth_phy_stats(struct net_device *netdev, 3522 struct ethtool_eth_phy_stats *phy_stats) 3523 { 3524 struct macb *bp = netdev_priv(netdev); 3525 struct gem_stats *hwstat = &bp->hw_stats.gem; 3526 3527 spin_lock_irq(&bp->stats_lock); 3528 gem_update_stats(bp); 3529 phy_stats->SymbolErrorDuringCarrier = hwstat->rx_symbol_errors; 3530 spin_unlock_irq(&bp->stats_lock); 3531 } 3532 3533 static void macb_get_rmon_stats(struct net_device *netdev, 3534 struct ethtool_rmon_stats *rmon_stats, 3535 const struct ethtool_rmon_hist_range **ranges) 3536 { 3537 struct macb *bp = netdev_priv(netdev); 3538 struct macb_stats *hwstat = &bp->hw_stats.macb; 3539 3540 spin_lock_irq(&bp->stats_lock); 3541 macb_update_stats(bp); 3542 rmon_stats->undersize_pkts = hwstat->rx_undersize_pkts; 3543 rmon_stats->oversize_pkts = hwstat->rx_oversize_pkts; 3544 rmon_stats->jabbers = hwstat->rx_jabbers; 3545 spin_unlock_irq(&bp->stats_lock); 3546 } 3547 3548 static const struct ethtool_rmon_hist_range gem_rmon_ranges[] = { 3549 { 64, 64 }, 3550 { 65, 127 }, 3551 { 128, 255 }, 3552 { 256, 511 }, 3553 { 512, 1023 }, 3554 { 1024, 1518 }, 3555 { 1519, 16384 }, 3556 { }, 3557 }; 3558 3559 static void gem_get_rmon_stats(struct net_device *netdev, 3560 struct ethtool_rmon_stats *rmon_stats, 3561 const struct ethtool_rmon_hist_range **ranges) 3562 { 3563 struct macb *bp = netdev_priv(netdev); 3564 struct gem_stats *hwstat = &bp->hw_stats.gem; 3565 3566 spin_lock_irq(&bp->stats_lock); 3567 gem_update_stats(bp); 3568 rmon_stats->undersize_pkts = hwstat->rx_undersized_frames; 3569 rmon_stats->oversize_pkts = hwstat->rx_oversize_frames; 3570 rmon_stats->jabbers = hwstat->rx_jabbers; 3571 rmon_stats->hist[0] = hwstat->rx_64_byte_frames; 3572 rmon_stats->hist[1] = hwstat->rx_65_127_byte_frames; 3573 rmon_stats->hist[2] = hwstat->rx_128_255_byte_frames; 3574 rmon_stats->hist[3] = hwstat->rx_256_511_byte_frames; 3575 rmon_stats->hist[4] = hwstat->rx_512_1023_byte_frames; 3576 rmon_stats->hist[5] = hwstat->rx_1024_1518_byte_frames; 3577 rmon_stats->hist[6] = hwstat->rx_greater_than_1518_byte_frames; 3578 rmon_stats->hist_tx[0] = hwstat->tx_64_byte_frames; 3579 rmon_stats->hist_tx[1] = hwstat->tx_65_127_byte_frames; 3580 rmon_stats->hist_tx[2] = hwstat->tx_128_255_byte_frames; 3581 rmon_stats->hist_tx[3] = hwstat->tx_256_511_byte_frames; 3582 rmon_stats->hist_tx[4] = hwstat->tx_512_1023_byte_frames; 3583 rmon_stats->hist_tx[5] = hwstat->tx_1024_1518_byte_frames; 3584 rmon_stats->hist_tx[6] = hwstat->tx_greater_than_1518_byte_frames; 3585 spin_unlock_irq(&bp->stats_lock); 3586 *ranges = gem_rmon_ranges; 3587 } 3588 3589 static int macb_get_regs_len(struct net_device *netdev) 3590 { 3591 return MACB_GREGS_NBR * sizeof(u32); 3592 } 3593 3594 static void macb_get_regs(struct net_device *netdev, struct ethtool_regs *regs, 3595 void *p) 3596 { 3597 struct macb *bp = netdev_priv(netdev); 3598 unsigned int tail, head; 3599 u32 *regs_buff = p; 3600 3601 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1)) 3602 | MACB_GREGS_VERSION; 3603 3604 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail); 3605 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head); 3606 3607 regs_buff[0] = macb_readl(bp, NCR); 3608 regs_buff[1] = macb_or_gem_readl(bp, NCFGR); 3609 regs_buff[2] = macb_readl(bp, NSR); 3610 regs_buff[3] = macb_readl(bp, TSR); 3611 regs_buff[4] = macb_readl(bp, RBQP); 3612 regs_buff[5] = macb_readl(bp, TBQP); 3613 regs_buff[6] = macb_readl(bp, RSR); 3614 regs_buff[7] = macb_readl(bp, IMR); 3615 3616 regs_buff[8] = tail; 3617 regs_buff[9] = head; 3618 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail); 3619 regs_buff[11] = macb_tx_dma(&bp->queues[0], head); 3620 3621 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) 3622 regs_buff[12] = macb_or_gem_readl(bp, USRIO); 3623 if (macb_is_gem(bp)) 3624 regs_buff[13] = gem_readl(bp, DMACFG); 3625 } 3626 3627 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 3628 { 3629 struct macb *bp = netdev_priv(netdev); 3630 3631 phylink_ethtool_get_wol(bp->phylink, wol); 3632 wol->supported |= (WAKE_MAGIC | WAKE_ARP); 3633 3634 /* Add macb wolopts to phy wolopts */ 3635 wol->wolopts |= bp->wolopts; 3636 } 3637 3638 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 3639 { 3640 struct macb *bp = netdev_priv(netdev); 3641 int ret; 3642 3643 /* Pass the order to phylink layer */ 3644 ret = phylink_ethtool_set_wol(bp->phylink, wol); 3645 /* Don't manage WoL on MAC, if PHY set_wol() fails */ 3646 if (ret && ret != -EOPNOTSUPP) 3647 return ret; 3648 3649 bp->wolopts = (wol->wolopts & WAKE_MAGIC) ? WAKE_MAGIC : 0; 3650 bp->wolopts |= (wol->wolopts & WAKE_ARP) ? WAKE_ARP : 0; 3651 bp->wol = (wol->wolopts) ? MACB_WOL_ENABLED : 0; 3652 3653 device_set_wakeup_enable(&bp->pdev->dev, bp->wol); 3654 3655 return 0; 3656 } 3657 3658 static int macb_get_link_ksettings(struct net_device *netdev, 3659 struct ethtool_link_ksettings *kset) 3660 { 3661 struct macb *bp = netdev_priv(netdev); 3662 3663 return phylink_ethtool_ksettings_get(bp->phylink, kset); 3664 } 3665 3666 static int macb_set_link_ksettings(struct net_device *netdev, 3667 const struct ethtool_link_ksettings *kset) 3668 { 3669 struct macb *bp = netdev_priv(netdev); 3670 3671 return phylink_ethtool_ksettings_set(bp->phylink, kset); 3672 } 3673 3674 static void macb_get_ringparam(struct net_device *netdev, 3675 struct ethtool_ringparam *ring, 3676 struct kernel_ethtool_ringparam *kernel_ring, 3677 struct netlink_ext_ack *extack) 3678 { 3679 struct macb *bp = netdev_priv(netdev); 3680 3681 ring->rx_max_pending = MAX_RX_RING_SIZE; 3682 ring->tx_max_pending = MAX_TX_RING_SIZE; 3683 3684 ring->rx_pending = bp->rx_ring_size; 3685 ring->tx_pending = bp->tx_ring_size; 3686 } 3687 3688 static int macb_set_ringparam(struct net_device *netdev, 3689 struct ethtool_ringparam *ring, 3690 struct kernel_ethtool_ringparam *kernel_ring, 3691 struct netlink_ext_ack *extack) 3692 { 3693 struct macb *bp = netdev_priv(netdev); 3694 u32 new_rx_size, new_tx_size; 3695 unsigned int reset = 0; 3696 3697 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) 3698 return -EOPNOTSUPP; 3699 3700 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 3701 return -EINVAL; 3702 3703 new_rx_size = clamp_t(u32, ring->rx_pending, 3704 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE); 3705 new_rx_size = roundup_pow_of_two(new_rx_size); 3706 3707 new_tx_size = clamp_t(u32, ring->tx_pending, 3708 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE); 3709 new_tx_size = roundup_pow_of_two(new_tx_size); 3710 3711 if ((new_tx_size == bp->tx_ring_size) && 3712 (new_rx_size == bp->rx_ring_size)) { 3713 /* nothing to do */ 3714 return 0; 3715 } 3716 3717 if (netif_running(bp->netdev)) { 3718 reset = 1; 3719 macb_close(bp->netdev); 3720 } 3721 3722 bp->rx_ring_size = new_rx_size; 3723 bp->tx_ring_size = new_tx_size; 3724 3725 if (reset) 3726 macb_open(bp->netdev); 3727 3728 return 0; 3729 } 3730 3731 #ifdef CONFIG_MACB_USE_HWSTAMP 3732 static unsigned int gem_get_tsu_rate(struct macb *bp) 3733 { 3734 struct clk *tsu_clk; 3735 unsigned int tsu_rate; 3736 3737 if (!IS_ERR_OR_NULL(bp->tsu_clk)) { 3738 tsu_rate = clk_get_rate(bp->tsu_clk); 3739 } else { 3740 tsu_clk = bp->pclk; 3741 tsu_rate = clk_get_rate(tsu_clk); 3742 dev_warn(&bp->pdev->dev, "devicetree missing tsu_clk, using pclk as fallback\n"); 3743 } 3744 3745 return tsu_rate; 3746 } 3747 3748 static s32 gem_get_ptp_max_adj(void) 3749 { 3750 return 64000000; 3751 } 3752 3753 static int gem_get_ts_info(struct net_device *netdev, 3754 struct kernel_ethtool_ts_info *info) 3755 { 3756 struct macb *bp = netdev_priv(netdev); 3757 3758 if (!macb_dma_ptp(bp)) { 3759 ethtool_op_get_ts_info(netdev, info); 3760 return 0; 3761 } 3762 3763 info->so_timestamping = 3764 SOF_TIMESTAMPING_TX_SOFTWARE | 3765 SOF_TIMESTAMPING_TX_HARDWARE | 3766 SOF_TIMESTAMPING_RX_HARDWARE | 3767 SOF_TIMESTAMPING_RAW_HARDWARE; 3768 info->tx_types = 3769 (1 << HWTSTAMP_TX_ONESTEP_SYNC) | 3770 (1 << HWTSTAMP_TX_OFF) | 3771 (1 << HWTSTAMP_TX_ON); 3772 info->rx_filters = 3773 (1 << HWTSTAMP_FILTER_NONE) | 3774 (1 << HWTSTAMP_FILTER_ALL); 3775 3776 if (bp->ptp_clock) 3777 info->phc_index = ptp_clock_index(bp->ptp_clock); 3778 3779 return 0; 3780 } 3781 3782 static struct macb_ptp_info gem_ptp_info = { 3783 .ptp_init = gem_ptp_init, 3784 .ptp_remove = gem_ptp_remove, 3785 .get_ptp_max_adj = gem_get_ptp_max_adj, 3786 .get_tsu_rate = gem_get_tsu_rate, 3787 .get_ts_info = gem_get_ts_info, 3788 .get_hwtst = gem_get_hwtst, 3789 .set_hwtst = gem_set_hwtst, 3790 }; 3791 #endif 3792 3793 static int macb_get_ts_info(struct net_device *netdev, 3794 struct kernel_ethtool_ts_info *info) 3795 { 3796 struct macb *bp = netdev_priv(netdev); 3797 3798 if (bp->ptp_info) 3799 return bp->ptp_info->get_ts_info(netdev, info); 3800 3801 return ethtool_op_get_ts_info(netdev, info); 3802 } 3803 3804 static void gem_enable_flow_filters(struct macb *bp, bool enable) 3805 { 3806 struct net_device *netdev = bp->netdev; 3807 struct ethtool_rx_fs_item *item; 3808 u32 t2_scr; 3809 int num_t2_scr; 3810 3811 if (!(netdev->features & NETIF_F_NTUPLE)) 3812 return; 3813 3814 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8)); 3815 3816 list_for_each_entry(item, &bp->rx_fs_list.list, list) { 3817 struct ethtool_rx_flow_spec *fs = &item->fs; 3818 struct ethtool_tcpip4_spec *tp4sp_m; 3819 3820 if (fs->location >= num_t2_scr) 3821 continue; 3822 3823 t2_scr = gem_readl_n(bp, SCRT2, fs->location); 3824 3825 /* enable/disable screener regs for the flow entry */ 3826 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr); 3827 3828 /* only enable fields with no masking */ 3829 tp4sp_m = &(fs->m_u.tcp_ip4_spec); 3830 3831 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF)) 3832 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr); 3833 else 3834 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr); 3835 3836 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF)) 3837 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr); 3838 else 3839 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr); 3840 3841 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF))) 3842 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr); 3843 else 3844 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr); 3845 3846 gem_writel_n(bp, SCRT2, fs->location, t2_scr); 3847 } 3848 } 3849 3850 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs) 3851 { 3852 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m; 3853 uint16_t index = fs->location; 3854 u32 w0, w1, t2_scr; 3855 bool cmp_a = false; 3856 bool cmp_b = false; 3857 bool cmp_c = false; 3858 3859 if (!macb_is_gem(bp)) 3860 return; 3861 3862 tp4sp_v = &(fs->h_u.tcp_ip4_spec); 3863 tp4sp_m = &(fs->m_u.tcp_ip4_spec); 3864 3865 /* ignore field if any masking set */ 3866 if (tp4sp_m->ip4src == 0xFFFFFFFF) { 3867 /* 1st compare reg - IP source address */ 3868 w0 = 0; 3869 w1 = 0; 3870 w0 = tp4sp_v->ip4src; 3871 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ 3872 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1); 3873 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1); 3874 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0); 3875 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1); 3876 cmp_a = true; 3877 } 3878 3879 /* ignore field if any masking set */ 3880 if (tp4sp_m->ip4dst == 0xFFFFFFFF) { 3881 /* 2nd compare reg - IP destination address */ 3882 w0 = 0; 3883 w1 = 0; 3884 w0 = tp4sp_v->ip4dst; 3885 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ 3886 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1); 3887 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1); 3888 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0); 3889 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1); 3890 cmp_b = true; 3891 } 3892 3893 /* ignore both port fields if masking set in both */ 3894 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) { 3895 /* 3rd compare reg - source port, destination port */ 3896 w0 = 0; 3897 w1 = 0; 3898 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1); 3899 if (tp4sp_m->psrc == tp4sp_m->pdst) { 3900 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0); 3901 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0); 3902 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ 3903 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1); 3904 } else { 3905 /* only one port definition */ 3906 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */ 3907 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0); 3908 if (tp4sp_m->psrc == 0xFFFF) { /* src port */ 3909 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0); 3910 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1); 3911 } else { /* dst port */ 3912 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0); 3913 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1); 3914 } 3915 } 3916 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0); 3917 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1); 3918 cmp_c = true; 3919 } 3920 3921 t2_scr = 0; 3922 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr); 3923 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr); 3924 if (cmp_a) 3925 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr); 3926 if (cmp_b) 3927 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr); 3928 if (cmp_c) 3929 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr); 3930 gem_writel_n(bp, SCRT2, index, t2_scr); 3931 } 3932 3933 static int gem_add_flow_filter(struct net_device *netdev, 3934 struct ethtool_rxnfc *cmd) 3935 { 3936 struct macb *bp = netdev_priv(netdev); 3937 struct ethtool_rx_flow_spec *fs = &cmd->fs; 3938 struct ethtool_rx_fs_item *item, *newfs; 3939 unsigned long flags; 3940 int ret = -EINVAL; 3941 bool added = false; 3942 3943 newfs = kmalloc_obj(*newfs); 3944 if (newfs == NULL) 3945 return -ENOMEM; 3946 memcpy(&newfs->fs, fs, sizeof(newfs->fs)); 3947 3948 netdev_dbg(netdev, 3949 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n", 3950 fs->flow_type, (int)fs->ring_cookie, fs->location, 3951 htonl(fs->h_u.tcp_ip4_spec.ip4src), 3952 htonl(fs->h_u.tcp_ip4_spec.ip4dst), 3953 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc), 3954 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst)); 3955 3956 spin_lock_irqsave(&bp->rx_fs_lock, flags); 3957 3958 /* find correct place to add in list */ 3959 list_for_each_entry(item, &bp->rx_fs_list.list, list) { 3960 if (item->fs.location > newfs->fs.location) { 3961 list_add_tail(&newfs->list, &item->list); 3962 added = true; 3963 break; 3964 } else if (item->fs.location == fs->location) { 3965 netdev_err(netdev, "Rule not added: location %d not free!\n", 3966 fs->location); 3967 ret = -EBUSY; 3968 goto err; 3969 } 3970 } 3971 if (!added) 3972 list_add_tail(&newfs->list, &bp->rx_fs_list.list); 3973 3974 gem_prog_cmp_regs(bp, fs); 3975 bp->rx_fs_list.count++; 3976 /* enable filtering if NTUPLE on */ 3977 gem_enable_flow_filters(bp, 1); 3978 3979 spin_unlock_irqrestore(&bp->rx_fs_lock, flags); 3980 return 0; 3981 3982 err: 3983 spin_unlock_irqrestore(&bp->rx_fs_lock, flags); 3984 kfree(newfs); 3985 return ret; 3986 } 3987 3988 static int gem_del_flow_filter(struct net_device *netdev, 3989 struct ethtool_rxnfc *cmd) 3990 { 3991 struct macb *bp = netdev_priv(netdev); 3992 struct ethtool_rx_fs_item *item; 3993 struct ethtool_rx_flow_spec *fs; 3994 unsigned long flags; 3995 3996 spin_lock_irqsave(&bp->rx_fs_lock, flags); 3997 3998 list_for_each_entry(item, &bp->rx_fs_list.list, list) { 3999 if (item->fs.location == cmd->fs.location) { 4000 /* disable screener regs for the flow entry */ 4001 fs = &(item->fs); 4002 netdev_dbg(netdev, 4003 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n", 4004 fs->flow_type, (int)fs->ring_cookie, fs->location, 4005 htonl(fs->h_u.tcp_ip4_spec.ip4src), 4006 htonl(fs->h_u.tcp_ip4_spec.ip4dst), 4007 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc), 4008 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst)); 4009 4010 gem_writel_n(bp, SCRT2, fs->location, 0); 4011 4012 list_del(&item->list); 4013 bp->rx_fs_list.count--; 4014 spin_unlock_irqrestore(&bp->rx_fs_lock, flags); 4015 kfree(item); 4016 return 0; 4017 } 4018 } 4019 4020 spin_unlock_irqrestore(&bp->rx_fs_lock, flags); 4021 return -EINVAL; 4022 } 4023 4024 static int gem_get_flow_entry(struct net_device *netdev, 4025 struct ethtool_rxnfc *cmd) 4026 { 4027 struct macb *bp = netdev_priv(netdev); 4028 struct ethtool_rx_fs_item *item; 4029 4030 list_for_each_entry(item, &bp->rx_fs_list.list, list) { 4031 if (item->fs.location == cmd->fs.location) { 4032 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs)); 4033 return 0; 4034 } 4035 } 4036 return -EINVAL; 4037 } 4038 4039 static int gem_get_all_flow_entries(struct net_device *netdev, 4040 struct ethtool_rxnfc *cmd, u32 *rule_locs) 4041 { 4042 struct macb *bp = netdev_priv(netdev); 4043 struct ethtool_rx_fs_item *item; 4044 uint32_t cnt = 0; 4045 4046 list_for_each_entry(item, &bp->rx_fs_list.list, list) { 4047 if (cnt == cmd->rule_cnt) 4048 return -EMSGSIZE; 4049 rule_locs[cnt] = item->fs.location; 4050 cnt++; 4051 } 4052 cmd->data = bp->max_tuples; 4053 cmd->rule_cnt = cnt; 4054 4055 return 0; 4056 } 4057 4058 static u32 gem_get_rx_ring_count(struct net_device *netdev) 4059 { 4060 struct macb *bp = netdev_priv(netdev); 4061 4062 return bp->num_queues; 4063 } 4064 4065 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd, 4066 u32 *rule_locs) 4067 { 4068 struct macb *bp = netdev_priv(netdev); 4069 int ret = 0; 4070 4071 switch (cmd->cmd) { 4072 case ETHTOOL_GRXCLSRLCNT: 4073 cmd->rule_cnt = bp->rx_fs_list.count; 4074 break; 4075 case ETHTOOL_GRXCLSRULE: 4076 ret = gem_get_flow_entry(netdev, cmd); 4077 break; 4078 case ETHTOOL_GRXCLSRLALL: 4079 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs); 4080 break; 4081 default: 4082 netdev_err(netdev, 4083 "Command parameter %d is not supported\n", cmd->cmd); 4084 ret = -EOPNOTSUPP; 4085 } 4086 4087 return ret; 4088 } 4089 4090 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd) 4091 { 4092 struct macb *bp = netdev_priv(netdev); 4093 int ret; 4094 4095 if (!(netdev->hw_features & NETIF_F_NTUPLE)) 4096 return -EOPNOTSUPP; 4097 4098 switch (cmd->cmd) { 4099 case ETHTOOL_SRXCLSRLINS: 4100 if ((cmd->fs.location >= bp->max_tuples) 4101 || (cmd->fs.ring_cookie >= bp->num_queues)) { 4102 ret = -EINVAL; 4103 break; 4104 } 4105 ret = gem_add_flow_filter(netdev, cmd); 4106 break; 4107 case ETHTOOL_SRXCLSRLDEL: 4108 ret = gem_del_flow_filter(netdev, cmd); 4109 break; 4110 default: 4111 netdev_err(netdev, 4112 "Command parameter %d is not supported\n", cmd->cmd); 4113 ret = -EOPNOTSUPP; 4114 } 4115 4116 return ret; 4117 } 4118 4119 static const struct ethtool_ops macb_ethtool_ops = { 4120 .get_regs_len = macb_get_regs_len, 4121 .get_regs = macb_get_regs, 4122 .get_link = ethtool_op_get_link, 4123 .get_ts_info = ethtool_op_get_ts_info, 4124 .get_pause_stats = macb_get_pause_stats, 4125 .get_eth_mac_stats = macb_get_eth_mac_stats, 4126 .get_eth_phy_stats = macb_get_eth_phy_stats, 4127 .get_rmon_stats = macb_get_rmon_stats, 4128 .get_wol = macb_get_wol, 4129 .set_wol = macb_set_wol, 4130 .get_link_ksettings = macb_get_link_ksettings, 4131 .set_link_ksettings = macb_set_link_ksettings, 4132 .get_ringparam = macb_get_ringparam, 4133 .set_ringparam = macb_set_ringparam, 4134 }; 4135 4136 static int macb_get_eee(struct net_device *netdev, struct ethtool_keee *eee) 4137 { 4138 struct macb *bp = netdev_priv(netdev); 4139 4140 return phylink_ethtool_get_eee(bp->phylink, eee); 4141 } 4142 4143 static int macb_set_eee(struct net_device *netdev, struct ethtool_keee *eee) 4144 { 4145 struct macb *bp = netdev_priv(netdev); 4146 4147 return phylink_ethtool_set_eee(bp->phylink, eee); 4148 } 4149 4150 static const struct ethtool_ops gem_ethtool_ops = { 4151 .get_regs_len = macb_get_regs_len, 4152 .get_regs = macb_get_regs, 4153 .get_wol = macb_get_wol, 4154 .set_wol = macb_set_wol, 4155 .get_link = ethtool_op_get_link, 4156 .get_ts_info = macb_get_ts_info, 4157 .get_ethtool_stats = gem_get_ethtool_stats, 4158 .get_strings = gem_get_ethtool_strings, 4159 .get_sset_count = gem_get_sset_count, 4160 .get_pause_stats = gem_get_pause_stats, 4161 .get_eth_mac_stats = gem_get_eth_mac_stats, 4162 .get_eth_phy_stats = gem_get_eth_phy_stats, 4163 .get_rmon_stats = gem_get_rmon_stats, 4164 .get_link_ksettings = macb_get_link_ksettings, 4165 .set_link_ksettings = macb_set_link_ksettings, 4166 .get_ringparam = macb_get_ringparam, 4167 .set_ringparam = macb_set_ringparam, 4168 .get_rxnfc = gem_get_rxnfc, 4169 .set_rxnfc = gem_set_rxnfc, 4170 .get_rx_ring_count = gem_get_rx_ring_count, 4171 .nway_reset = phy_ethtool_nway_reset, 4172 .get_eee = macb_get_eee, 4173 .set_eee = macb_set_eee, 4174 }; 4175 4176 static int macb_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 4177 { 4178 struct macb *bp = netdev_priv(netdev); 4179 4180 if (!netif_running(netdev)) 4181 return -EINVAL; 4182 4183 return phylink_mii_ioctl(bp->phylink, rq, cmd); 4184 } 4185 4186 static int macb_hwtstamp_get(struct net_device *netdev, 4187 struct kernel_hwtstamp_config *cfg) 4188 { 4189 struct macb *bp = netdev_priv(netdev); 4190 4191 if (!netif_running(netdev)) 4192 return -EINVAL; 4193 4194 if (!bp->ptp_info) 4195 return -EOPNOTSUPP; 4196 4197 return bp->ptp_info->get_hwtst(netdev, cfg); 4198 } 4199 4200 static int macb_hwtstamp_set(struct net_device *netdev, 4201 struct kernel_hwtstamp_config *cfg, 4202 struct netlink_ext_ack *extack) 4203 { 4204 struct macb *bp = netdev_priv(netdev); 4205 4206 if (!netif_running(netdev)) 4207 return -EINVAL; 4208 4209 if (!bp->ptp_info) 4210 return -EOPNOTSUPP; 4211 4212 return bp->ptp_info->set_hwtst(netdev, cfg, extack); 4213 } 4214 4215 static inline void macb_set_txcsum_feature(struct macb *bp, 4216 netdev_features_t features) 4217 { 4218 u32 val; 4219 4220 if (!macb_is_gem(bp)) 4221 return; 4222 4223 val = gem_readl(bp, DMACFG); 4224 if (features & NETIF_F_HW_CSUM) 4225 val |= GEM_BIT(TXCOEN); 4226 else 4227 val &= ~GEM_BIT(TXCOEN); 4228 4229 gem_writel(bp, DMACFG, val); 4230 } 4231 4232 static inline void macb_set_rxcsum_feature(struct macb *bp, 4233 netdev_features_t features) 4234 { 4235 struct net_device *netdev = bp->netdev; 4236 u32 val; 4237 4238 if (!macb_is_gem(bp)) 4239 return; 4240 4241 val = gem_readl(bp, NCFGR); 4242 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC)) 4243 val |= GEM_BIT(RXCOEN); 4244 else 4245 val &= ~GEM_BIT(RXCOEN); 4246 4247 gem_writel(bp, NCFGR, val); 4248 } 4249 4250 static inline void macb_set_rxflow_feature(struct macb *bp, 4251 netdev_features_t features) 4252 { 4253 if (!macb_is_gem(bp)) 4254 return; 4255 4256 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE)); 4257 } 4258 4259 static int macb_set_features(struct net_device *netdev, 4260 netdev_features_t features) 4261 { 4262 struct macb *bp = netdev_priv(netdev); 4263 netdev_features_t changed = features ^ netdev->features; 4264 4265 /* TX checksum offload */ 4266 if (changed & NETIF_F_HW_CSUM) 4267 macb_set_txcsum_feature(bp, features); 4268 4269 /* RX checksum offload */ 4270 if (changed & NETIF_F_RXCSUM) 4271 macb_set_rxcsum_feature(bp, features); 4272 4273 /* RX Flow Filters */ 4274 if (changed & NETIF_F_NTUPLE) 4275 macb_set_rxflow_feature(bp, features); 4276 4277 return 0; 4278 } 4279 4280 static void macb_restore_features(struct macb *bp) 4281 { 4282 struct net_device *netdev = bp->netdev; 4283 netdev_features_t features = netdev->features; 4284 struct ethtool_rx_fs_item *item; 4285 4286 /* TX checksum offload */ 4287 macb_set_txcsum_feature(bp, features); 4288 4289 /* RX checksum offload */ 4290 macb_set_rxcsum_feature(bp, features); 4291 4292 /* RX Flow Filters */ 4293 list_for_each_entry(item, &bp->rx_fs_list.list, list) 4294 gem_prog_cmp_regs(bp, &item->fs); 4295 4296 macb_set_rxflow_feature(bp, features); 4297 } 4298 4299 static int macb_taprio_setup_replace(struct net_device *netdev, 4300 struct tc_taprio_qopt_offload *conf) 4301 { 4302 u64 total_on_time = 0, start_time_sec = 0, start_time = conf->base_time; 4303 u32 configured_queues = 0, speed = 0, start_time_nsec; 4304 struct macb_queue_enst_config *enst_queue; 4305 struct ethtool_link_ksettings kset = {}; 4306 struct macb *bp = netdev_priv(netdev); 4307 struct tc_taprio_sched_entry *entry; 4308 struct macb_queue *queue; 4309 u32 queue_mask; 4310 u8 queue_id; 4311 size_t i; 4312 int err; 4313 4314 if (conf->num_entries > bp->num_queues) { 4315 netdev_err(netdev, "Too many TAPRIO entries: %zu > %d queues\n", 4316 conf->num_entries, bp->num_queues); 4317 return -EINVAL; 4318 } 4319 4320 if (conf->base_time < 0) { 4321 netdev_err(netdev, "Invalid base_time: must be 0 or positive, got %lld\n", 4322 conf->base_time); 4323 return -ERANGE; 4324 } 4325 4326 /* Get the current link speed */ 4327 err = phylink_ethtool_ksettings_get(bp->phylink, &kset); 4328 if (unlikely(err)) { 4329 netdev_err(netdev, "Failed to get link settings: %d\n", err); 4330 return err; 4331 } 4332 4333 speed = kset.base.speed; 4334 if (unlikely(speed == SPEED_UNKNOWN || !speed)) { 4335 netdev_err(netdev, "Invalid speed %d, link-down?\n", speed); 4336 return -EINVAL; 4337 } 4338 4339 enst_queue = kzalloc_objs(*enst_queue, conf->num_entries); 4340 if (unlikely(!enst_queue)) 4341 return -ENOMEM; 4342 4343 /* Pre-validate all entries before making any hardware changes */ 4344 for (i = 0; i < conf->num_entries; i++) { 4345 entry = &conf->entries[i]; 4346 4347 if (entry->command != TC_TAPRIO_CMD_SET_GATES) { 4348 netdev_err(netdev, "Entry %zu: unsupported command %d\n", 4349 i, entry->command); 4350 err = -EOPNOTSUPP; 4351 goto cleanup; 4352 } 4353 4354 /* Validate gate_mask: must be nonzero, single queue, and within range */ 4355 if (!is_power_of_2(entry->gate_mask)) { 4356 netdev_err(netdev, "Entry %zu: gate_mask 0x%x is not a power of 2 (only one queue per entry allowed)\n", 4357 i, entry->gate_mask); 4358 err = -EINVAL; 4359 goto cleanup; 4360 } 4361 4362 /* gate_mask must not select queues outside the valid queues */ 4363 queue_id = order_base_2(entry->gate_mask); 4364 if (queue_id >= bp->num_queues) { 4365 netdev_err(netdev, "Entry %zu: gate_mask 0x%x exceeds queue range (max_queues=%d)\n", 4366 i, entry->gate_mask, bp->num_queues); 4367 err = -EINVAL; 4368 goto cleanup; 4369 } 4370 4371 /* Check for start time limits */ 4372 start_time_sec = start_time; 4373 start_time_nsec = do_div(start_time_sec, NSEC_PER_SEC); 4374 if (start_time_sec > GENMASK(GEM_START_TIME_SEC_SIZE - 1, 0)) { 4375 netdev_err(netdev, "Entry %zu: Start time %llu s exceeds hardware limit\n", 4376 i, start_time_sec); 4377 err = -ERANGE; 4378 goto cleanup; 4379 } 4380 4381 /* Check for on time limit */ 4382 if (entry->interval > enst_max_hw_interval(speed)) { 4383 netdev_err(netdev, "Entry %zu: interval %u ns exceeds hardware limit %llu ns\n", 4384 i, entry->interval, enst_max_hw_interval(speed)); 4385 err = -ERANGE; 4386 goto cleanup; 4387 } 4388 4389 /* Check for off time limit*/ 4390 if ((conf->cycle_time - entry->interval) > enst_max_hw_interval(speed)) { 4391 netdev_err(netdev, "Entry %zu: off_time %llu ns exceeds hardware limit %llu ns\n", 4392 i, conf->cycle_time - entry->interval, 4393 enst_max_hw_interval(speed)); 4394 err = -ERANGE; 4395 goto cleanup; 4396 } 4397 4398 enst_queue[i].queue_id = queue_id; 4399 enst_queue[i].start_time_mask = 4400 (start_time_sec << GEM_START_TIME_SEC_OFFSET) | 4401 start_time_nsec; 4402 enst_queue[i].on_time_bytes = 4403 enst_ns_to_hw_units(entry->interval, speed); 4404 enst_queue[i].off_time_bytes = 4405 enst_ns_to_hw_units(conf->cycle_time - entry->interval, speed); 4406 4407 configured_queues |= entry->gate_mask; 4408 total_on_time += entry->interval; 4409 start_time += entry->interval; 4410 } 4411 4412 /* Check total interval doesn't exceed cycle time */ 4413 if (total_on_time > conf->cycle_time) { 4414 netdev_err(netdev, "Total ON %llu ns exceeds cycle time %llu ns\n", 4415 total_on_time, conf->cycle_time); 4416 err = -EINVAL; 4417 goto cleanup; 4418 } 4419 4420 netdev_dbg(netdev, "TAPRIO setup: %zu entries, base_time=%lld ns, cycle_time=%llu ns\n", 4421 conf->num_entries, conf->base_time, conf->cycle_time); 4422 4423 /* All validations passed - proceed with hardware configuration */ 4424 scoped_guard(spinlock_irqsave, &bp->lock) { 4425 /* Disable ENST queues if running before configuring */ 4426 queue_mask = BIT_U32(bp->num_queues) - 1; 4427 gem_writel(bp, ENST_CONTROL, 4428 queue_mask << GEM_ENST_DISABLE_QUEUE_OFFSET); 4429 4430 for (i = 0; i < conf->num_entries; i++) { 4431 queue = &bp->queues[enst_queue[i].queue_id]; 4432 /* Configure queue timing registers */ 4433 queue_writel(queue, ENST_START_TIME, 4434 enst_queue[i].start_time_mask); 4435 queue_writel(queue, ENST_ON_TIME, 4436 enst_queue[i].on_time_bytes); 4437 queue_writel(queue, ENST_OFF_TIME, 4438 enst_queue[i].off_time_bytes); 4439 } 4440 4441 /* Enable ENST for all configured queues in one write */ 4442 gem_writel(bp, ENST_CONTROL, configured_queues); 4443 } 4444 4445 netdev_info(netdev, "TAPRIO configuration completed successfully: %zu entries, %d queues configured\n", 4446 conf->num_entries, hweight32(configured_queues)); 4447 4448 cleanup: 4449 kfree(enst_queue); 4450 return err; 4451 } 4452 4453 static void macb_taprio_destroy(struct net_device *netdev) 4454 { 4455 struct macb *bp = netdev_priv(netdev); 4456 struct macb_queue *queue; 4457 u32 queue_mask; 4458 unsigned int q; 4459 4460 netdev_reset_tc(netdev); 4461 queue_mask = BIT_U32(bp->num_queues) - 1; 4462 4463 scoped_guard(spinlock_irqsave, &bp->lock) { 4464 /* Single disable command for all queues */ 4465 gem_writel(bp, ENST_CONTROL, 4466 queue_mask << GEM_ENST_DISABLE_QUEUE_OFFSET); 4467 4468 /* Clear all queue ENST registers in batch */ 4469 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 4470 queue_writel(queue, ENST_START_TIME, 0); 4471 queue_writel(queue, ENST_ON_TIME, 0); 4472 queue_writel(queue, ENST_OFF_TIME, 0); 4473 } 4474 } 4475 netdev_info(netdev, "TAPRIO destroy: All gates disabled\n"); 4476 } 4477 4478 static int macb_setup_taprio(struct net_device *netdev, 4479 struct tc_taprio_qopt_offload *taprio) 4480 { 4481 struct macb *bp = netdev_priv(netdev); 4482 int err = 0; 4483 4484 if (unlikely(!(netdev->hw_features & NETIF_F_HW_TC))) 4485 return -EOPNOTSUPP; 4486 4487 /* Check if Device is in runtime suspend */ 4488 if (unlikely(pm_runtime_suspended(&bp->pdev->dev))) { 4489 netdev_err(netdev, "Device is in runtime suspend\n"); 4490 return -EOPNOTSUPP; 4491 } 4492 4493 switch (taprio->cmd) { 4494 case TAPRIO_CMD_REPLACE: 4495 err = macb_taprio_setup_replace(netdev, taprio); 4496 break; 4497 case TAPRIO_CMD_DESTROY: 4498 macb_taprio_destroy(netdev); 4499 break; 4500 default: 4501 err = -EOPNOTSUPP; 4502 } 4503 4504 return err; 4505 } 4506 4507 static int macb_setup_tc(struct net_device *netdev, enum tc_setup_type type, 4508 void *type_data) 4509 { 4510 if (!netdev || !type_data) 4511 return -EINVAL; 4512 4513 switch (type) { 4514 case TC_SETUP_QDISC_TAPRIO: 4515 return macb_setup_taprio(netdev, type_data); 4516 default: 4517 return -EOPNOTSUPP; 4518 } 4519 } 4520 4521 static void macb_tx_timeout(struct net_device *netdev, unsigned int q) 4522 { 4523 struct macb *bp = netdev_priv(netdev); 4524 4525 macb_tx_restart(&bp->queues[q]); 4526 } 4527 4528 static const struct net_device_ops macb_netdev_ops = { 4529 .ndo_open = macb_open, 4530 .ndo_stop = macb_close, 4531 .ndo_start_xmit = macb_start_xmit, 4532 .ndo_set_rx_mode = macb_set_rx_mode, 4533 .ndo_get_stats64 = macb_get_stats, 4534 .ndo_eth_ioctl = macb_ioctl, 4535 .ndo_validate_addr = eth_validate_addr, 4536 .ndo_change_mtu = macb_change_mtu, 4537 .ndo_set_mac_address = macb_set_mac_addr, 4538 #ifdef CONFIG_NET_POLL_CONTROLLER 4539 .ndo_poll_controller = macb_poll_controller, 4540 #endif 4541 .ndo_set_features = macb_set_features, 4542 .ndo_features_check = macb_features_check, 4543 .ndo_hwtstamp_set = macb_hwtstamp_set, 4544 .ndo_hwtstamp_get = macb_hwtstamp_get, 4545 .ndo_setup_tc = macb_setup_tc, 4546 .ndo_tx_timeout = macb_tx_timeout, 4547 }; 4548 4549 /* Configure peripheral capabilities according to device tree 4550 * and integration options used 4551 */ 4552 static void macb_configure_caps(struct macb *bp, 4553 const struct macb_config *dt_conf) 4554 { 4555 u32 dcfg; 4556 4557 bp->caps = dt_conf->caps; 4558 4559 if (!dt_conf->usrio) 4560 bp->caps |= MACB_CAPS_USRIO_DISABLED; 4561 4562 if (hw_is_gem(bp->regs, bp->native_io)) { 4563 bp->caps |= MACB_CAPS_MACB_IS_GEM; 4564 4565 dcfg = gem_readl(bp, DCFG1); 4566 if (GEM_BFEXT(IRQCOR, dcfg) == 0) 4567 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE; 4568 if (GEM_BFEXT(NO_PCS, dcfg) == 0) 4569 bp->caps |= MACB_CAPS_PCS; 4570 if (!(dcfg & GEM_BIT(USERIO))) 4571 bp->caps |= MACB_CAPS_USRIO_DISABLED; 4572 dcfg = gem_readl(bp, DCFG12); 4573 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1) 4574 bp->caps |= MACB_CAPS_HIGH_SPEED; 4575 dcfg = gem_readl(bp, DCFG2); 4576 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) 4577 bp->caps |= MACB_CAPS_FIFO_MODE; 4578 if (GEM_BFEXT(PBUF_RSC, gem_readl(bp, DCFG6))) 4579 bp->caps |= MACB_CAPS_RSC; 4580 if (gem_has_ptp(bp)) { 4581 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5))) 4582 dev_err(&bp->pdev->dev, 4583 "GEM doesn't support hardware ptp.\n"); 4584 else { 4585 #ifdef CONFIG_MACB_USE_HWSTAMP 4586 bp->caps |= MACB_CAPS_DMA_PTP; 4587 bp->ptp_info = &gem_ptp_info; 4588 #endif 4589 } 4590 } 4591 } 4592 4593 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps); 4594 } 4595 4596 static int macb_probe_queues(struct device *dev, void __iomem *mem, bool native_io) 4597 { 4598 /* BIT(0) is never set but queue 0 always exists. */ 4599 unsigned int queue_mask = 0x1; 4600 4601 /* Use hw_is_gem() as MACB_CAPS_MACB_IS_GEM is not yet positioned. */ 4602 if (hw_is_gem(mem, native_io)) { 4603 if (native_io) 4604 queue_mask |= __raw_readl(mem + GEM_DCFG6) & 0xFF; 4605 else 4606 queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xFF; 4607 4608 if (fls(queue_mask) != ffz(queue_mask)) { 4609 dev_err(dev, "queue mask %#x has a hole\n", queue_mask); 4610 return -EINVAL; 4611 } 4612 } 4613 4614 return hweight32(queue_mask); 4615 } 4616 4617 static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk, 4618 struct clk *rx_clk, struct clk *tsu_clk) 4619 { 4620 struct clk_bulk_data clks[] = { 4621 { .clk = tsu_clk, }, 4622 { .clk = rx_clk, }, 4623 { .clk = pclk, }, 4624 { .clk = hclk, }, 4625 { .clk = tx_clk }, 4626 }; 4627 4628 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks); 4629 } 4630 4631 static int macb_clk_init_dflt(struct platform_device *pdev, struct clk **pclk, 4632 struct clk **hclk, struct clk **tx_clk, 4633 struct clk **rx_clk, struct clk **tsu_clk) 4634 { 4635 struct macb_platform_data *pdata; 4636 int err; 4637 4638 pdata = dev_get_platdata(&pdev->dev); 4639 if (pdata) { 4640 *pclk = pdata->pclk; 4641 *hclk = pdata->hclk; 4642 } else { 4643 *pclk = devm_clk_get(&pdev->dev, "pclk"); 4644 *hclk = devm_clk_get(&pdev->dev, "hclk"); 4645 } 4646 4647 if (IS_ERR_OR_NULL(*pclk)) 4648 return dev_err_probe(&pdev->dev, 4649 IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV, 4650 "failed to get pclk\n"); 4651 4652 if (IS_ERR_OR_NULL(*hclk)) 4653 return dev_err_probe(&pdev->dev, 4654 IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV, 4655 "failed to get hclk\n"); 4656 4657 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk"); 4658 if (IS_ERR(*tx_clk)) 4659 return PTR_ERR(*tx_clk); 4660 4661 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk"); 4662 if (IS_ERR(*rx_clk)) 4663 return PTR_ERR(*rx_clk); 4664 4665 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk"); 4666 if (IS_ERR(*tsu_clk)) 4667 return PTR_ERR(*tsu_clk); 4668 4669 err = clk_prepare_enable(*pclk); 4670 if (err) { 4671 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err); 4672 return err; 4673 } 4674 4675 err = clk_prepare_enable(*hclk); 4676 if (err) { 4677 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err); 4678 goto err_disable_pclk; 4679 } 4680 4681 err = clk_prepare_enable(*tx_clk); 4682 if (err) { 4683 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); 4684 goto err_disable_hclk; 4685 } 4686 4687 err = clk_prepare_enable(*rx_clk); 4688 if (err) { 4689 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); 4690 goto err_disable_txclk; 4691 } 4692 4693 err = clk_prepare_enable(*tsu_clk); 4694 if (err) { 4695 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err); 4696 goto err_disable_rxclk; 4697 } 4698 4699 return 0; 4700 4701 err_disable_rxclk: 4702 clk_disable_unprepare(*rx_clk); 4703 4704 err_disable_txclk: 4705 clk_disable_unprepare(*tx_clk); 4706 4707 err_disable_hclk: 4708 clk_disable_unprepare(*hclk); 4709 4710 err_disable_pclk: 4711 clk_disable_unprepare(*pclk); 4712 4713 return err; 4714 } 4715 4716 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk, 4717 struct clk **hclk, struct clk **tx_clk, 4718 struct clk **rx_clk, struct clk **tsu_clk, 4719 const struct macb_config *config) 4720 { 4721 if (config->clk_init) 4722 return config->clk_init(pdev, pclk, hclk, tx_clk, rx_clk, 4723 tsu_clk); 4724 else 4725 return macb_clk_init_dflt(pdev, pclk, hclk, tx_clk, rx_clk, 4726 tsu_clk); 4727 } 4728 4729 static int macb_init_dflt(struct platform_device *pdev) 4730 { 4731 struct net_device *netdev = platform_get_drvdata(pdev); 4732 unsigned int hw_q, q; 4733 struct macb *bp = netdev_priv(netdev); 4734 struct macb_queue *queue; 4735 int err; 4736 u32 val, reg; 4737 4738 bp->tx_ring_size = DEFAULT_TX_RING_SIZE; 4739 bp->rx_ring_size = DEFAULT_RX_RING_SIZE; 4740 4741 /* set the queue register mapping once for all: queue0 has a special 4742 * register mapping but we don't want to test the queue index then 4743 * compute the corresponding register offset at run time. 4744 */ 4745 for (hw_q = 0, q = 0; hw_q < bp->num_queues; ++hw_q) { 4746 queue = &bp->queues[q]; 4747 queue->bp = bp; 4748 spin_lock_init(&queue->tx_ptr_lock); 4749 netif_napi_add(netdev, &queue->napi_rx, macb_rx_poll); 4750 netif_napi_add_tx(netdev, &queue->napi_tx, macb_tx_poll); 4751 if (hw_q) { 4752 queue->ISR = GEM_ISR(hw_q - 1); 4753 queue->IER = GEM_IER(hw_q - 1); 4754 queue->IDR = GEM_IDR(hw_q - 1); 4755 queue->IMR = GEM_IMR(hw_q - 1); 4756 queue->TBQP = GEM_TBQP(hw_q - 1); 4757 queue->RBQP = GEM_RBQP(hw_q - 1); 4758 queue->RBQS = GEM_RBQS(hw_q - 1); 4759 } else { 4760 /* queue0 uses legacy registers */ 4761 queue->ISR = MACB_ISR; 4762 queue->IER = MACB_IER; 4763 queue->IDR = MACB_IDR; 4764 queue->IMR = MACB_IMR; 4765 queue->TBQP = MACB_TBQP; 4766 queue->RBQP = MACB_RBQP; 4767 } 4768 4769 queue->ENST_START_TIME = GEM_ENST_START_TIME(hw_q); 4770 queue->ENST_ON_TIME = GEM_ENST_ON_TIME(hw_q); 4771 queue->ENST_OFF_TIME = GEM_ENST_OFF_TIME(hw_q); 4772 4773 /* get irq: here we use the linux queue index, not the hardware 4774 * queue index. the queue irq definitions in the device tree 4775 * must remove the optional gaps that could exist in the 4776 * hardware queue mask. 4777 */ 4778 queue->irq = platform_get_irq(pdev, q); 4779 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt, 4780 IRQF_SHARED, netdev->name, queue); 4781 if (err) { 4782 dev_err(&pdev->dev, 4783 "Unable to request IRQ %d (error %d)\n", 4784 queue->irq, err); 4785 return err; 4786 } 4787 4788 INIT_WORK(&queue->tx_error_task, macb_tx_error_task); 4789 q++; 4790 } 4791 4792 netdev->netdev_ops = &macb_netdev_ops; 4793 4794 /* setup appropriated routines according to adapter type */ 4795 if (macb_is_gem(bp)) { 4796 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers; 4797 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers; 4798 bp->macbgem_ops.mog_init_rings = gem_init_rings; 4799 bp->macbgem_ops.mog_rx = gem_rx; 4800 netdev->ethtool_ops = &gem_ethtool_ops; 4801 } else { 4802 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers; 4803 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers; 4804 bp->macbgem_ops.mog_init_rings = macb_init_rings; 4805 bp->macbgem_ops.mog_rx = macb_rx; 4806 netdev->ethtool_ops = &macb_ethtool_ops; 4807 } 4808 4809 netdev_sw_irq_coalesce_default_on(netdev); 4810 4811 netdev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 4812 4813 /* Set features */ 4814 netdev->hw_features = NETIF_F_SG; 4815 4816 /* Check LSO capability; runtime detection can be overridden by a cap 4817 * flag if the hardware is known to be buggy 4818 */ 4819 if (!(bp->caps & MACB_CAPS_NO_LSO) && 4820 GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6))) 4821 netdev->hw_features |= MACB_NETIF_LSO; 4822 4823 /* Checksum offload is only available on gem with packet buffer */ 4824 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE)) 4825 netdev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM; 4826 if (bp->caps & MACB_CAPS_SG_DISABLED) 4827 netdev->hw_features &= ~NETIF_F_SG; 4828 /* Enable HW_TC if hardware supports QBV */ 4829 if (bp->caps & MACB_CAPS_QBV) 4830 netdev->hw_features |= NETIF_F_HW_TC; 4831 4832 netdev->features = netdev->hw_features; 4833 4834 /* Check RX Flow Filters support. 4835 * Max Rx flows set by availability of screeners & compare regs: 4836 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs 4837 */ 4838 reg = gem_readl(bp, DCFG8); 4839 bp->max_tuples = umin((GEM_BFEXT(SCR2CMP, reg) / 3), 4840 GEM_BFEXT(T2SCR, reg)); 4841 INIT_LIST_HEAD(&bp->rx_fs_list.list); 4842 if (bp->max_tuples > 0) { 4843 /* also needs one ethtype match to check IPv4 */ 4844 if (GEM_BFEXT(SCR2ETH, reg) > 0) { 4845 /* program this reg now */ 4846 reg = 0; 4847 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg); 4848 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg); 4849 /* Filtering is supported in hw but don't enable it in kernel now */ 4850 netdev->hw_features |= NETIF_F_NTUPLE; 4851 /* init Rx flow definitions */ 4852 bp->rx_fs_list.count = 0; 4853 spin_lock_init(&bp->rx_fs_lock); 4854 } else 4855 bp->max_tuples = 0; 4856 } 4857 4858 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) { 4859 val = 0; 4860 if (bp->caps & MACB_CAPS_USRIO_HAS_MII) { 4861 if (phy_interface_mode_is_rgmii(bp->phy_interface)) 4862 val = bp->usrio->rgmii; 4863 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII && 4864 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) 4865 val = bp->usrio->rmii; 4866 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) 4867 val = bp->usrio->mii; 4868 } 4869 4870 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN) 4871 val |= bp->usrio->clken; 4872 4873 if (bp->caps & MACB_CAPS_USRIO_HAS_REFCLK_SOURCE) { 4874 const char *prop; 4875 bool refclk_ext; 4876 int ret; 4877 4878 /* Default to whatever was set in the match data for 4879 * this device. There's two properties for refclk 4880 * control, but the boolean one is deprecated so is 4881 * a lower priority to check, no device should have 4882 * both. 4883 */ 4884 refclk_ext = bp->usrio->refclk_default_external; 4885 4886 ret = of_property_read_string(pdev->dev.of_node, 4887 "cdns,refclk-source", &prop); 4888 if (!ret) { 4889 if (!strcmp(prop, "external")) 4890 refclk_ext = true; 4891 else 4892 refclk_ext = false; 4893 } else { 4894 ret = of_property_read_bool(pdev->dev.of_node, 4895 "cdns,refclk-ext"); 4896 if (ret) 4897 refclk_ext = true; 4898 } 4899 4900 if (refclk_ext) 4901 val |= bp->usrio->refclk; 4902 } 4903 4904 if (bp->caps & MACB_CAPS_USRIO_HAS_TSUCLK_SOURCE) 4905 val |= bp->usrio->tsu_source; 4906 4907 macb_or_gem_writel(bp, USRIO, val); 4908 } 4909 4910 /* Set MII management clock divider */ 4911 val = macb_mdc_clk_div(bp); 4912 val |= macb_dbw(bp); 4913 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) 4914 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); 4915 macb_writel(bp, NCFGR, val); 4916 4917 return 0; 4918 } 4919 4920 static int macb_init(struct platform_device *pdev, 4921 const struct macb_config *config) 4922 { 4923 if (config->init) 4924 return config->init(pdev); 4925 else 4926 return macb_init_dflt(pdev); 4927 } 4928 4929 static const struct macb_usrio_config at91_default_usrio = { 4930 .mii = MACB_BIT(MII), 4931 .rmii = MACB_BIT(RMII), 4932 .rgmii = GEM_BIT(RGMII), 4933 .clken = MACB_BIT(CLKEN), 4934 }; 4935 4936 /* 1518 rounded up */ 4937 #define AT91ETHER_MAX_RBUFF_SZ 0x600 4938 /* max number of receive buffers */ 4939 #define AT91ETHER_MAX_RX_DESCR 9 4940 4941 static struct sifive_fu540_macb_mgmt *mgmt; 4942 4943 static int at91ether_alloc_coherent(struct macb *bp) 4944 { 4945 struct macb_queue *queue = &bp->queues[0]; 4946 4947 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, 4948 (AT91ETHER_MAX_RX_DESCR * 4949 macb_dma_desc_get_size(bp)), 4950 &queue->rx_ring_dma, GFP_KERNEL); 4951 if (!queue->rx_ring) 4952 return -ENOMEM; 4953 4954 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, 4955 AT91ETHER_MAX_RX_DESCR * 4956 AT91ETHER_MAX_RBUFF_SZ, 4957 &queue->rx_buffers_dma, 4958 GFP_KERNEL); 4959 if (!queue->rx_buffers) { 4960 dma_free_coherent(&bp->pdev->dev, 4961 AT91ETHER_MAX_RX_DESCR * 4962 macb_dma_desc_get_size(bp), 4963 queue->rx_ring, queue->rx_ring_dma); 4964 queue->rx_ring = NULL; 4965 return -ENOMEM; 4966 } 4967 4968 return 0; 4969 } 4970 4971 static void at91ether_free_coherent(struct macb *bp) 4972 { 4973 struct macb_queue *queue = &bp->queues[0]; 4974 4975 if (queue->rx_ring) { 4976 dma_free_coherent(&bp->pdev->dev, 4977 AT91ETHER_MAX_RX_DESCR * 4978 macb_dma_desc_get_size(bp), 4979 queue->rx_ring, queue->rx_ring_dma); 4980 queue->rx_ring = NULL; 4981 } 4982 4983 if (queue->rx_buffers) { 4984 dma_free_coherent(&bp->pdev->dev, 4985 AT91ETHER_MAX_RX_DESCR * 4986 AT91ETHER_MAX_RBUFF_SZ, 4987 queue->rx_buffers, queue->rx_buffers_dma); 4988 queue->rx_buffers = NULL; 4989 } 4990 } 4991 4992 /* Initialize and start the Receiver and Transmit subsystems */ 4993 static int at91ether_start(struct macb *bp) 4994 { 4995 struct macb_queue *queue = &bp->queues[0]; 4996 struct macb_dma_desc *desc; 4997 dma_addr_t addr; 4998 u32 ctl; 4999 int i, ret; 5000 5001 ret = at91ether_alloc_coherent(bp); 5002 if (ret) 5003 return ret; 5004 5005 addr = queue->rx_buffers_dma; 5006 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) { 5007 desc = macb_rx_desc(queue, i); 5008 macb_set_addr(bp, desc, addr); 5009 desc->ctrl = 0; 5010 addr += AT91ETHER_MAX_RBUFF_SZ; 5011 } 5012 5013 /* Set the Wrap bit on the last descriptor */ 5014 desc->addr |= MACB_BIT(RX_WRAP); 5015 5016 /* Reset buffer index */ 5017 queue->rx_tail = 0; 5018 5019 /* Program address of descriptor list in Rx Buffer Queue register */ 5020 macb_writel(bp, RBQP, queue->rx_ring_dma); 5021 5022 /* Enable Receive and Transmit */ 5023 ctl = macb_readl(bp, NCR); 5024 macb_writel(bp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE)); 5025 5026 /* Enable MAC interrupts */ 5027 macb_writel(bp, IER, MACB_BIT(RCOMP) | 5028 MACB_BIT(RXUBR) | 5029 MACB_BIT(ISR_TUND) | 5030 MACB_BIT(ISR_RLE) | 5031 MACB_BIT(TCOMP) | 5032 MACB_BIT(ISR_ROVR) | 5033 MACB_BIT(HRESP)); 5034 5035 return 0; 5036 } 5037 5038 static void at91ether_stop(struct macb *bp) 5039 { 5040 u32 ctl; 5041 5042 /* Disable MAC interrupts */ 5043 macb_writel(bp, IDR, MACB_BIT(RCOMP) | 5044 MACB_BIT(RXUBR) | 5045 MACB_BIT(ISR_TUND) | 5046 MACB_BIT(ISR_RLE) | 5047 MACB_BIT(TCOMP) | 5048 MACB_BIT(ISR_ROVR) | 5049 MACB_BIT(HRESP)); 5050 5051 /* Disable Receiver and Transmitter */ 5052 ctl = macb_readl(bp, NCR); 5053 macb_writel(bp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE))); 5054 5055 /* Free resources. */ 5056 at91ether_free_coherent(bp); 5057 } 5058 5059 /* Open the ethernet interface */ 5060 static int at91ether_open(struct net_device *netdev) 5061 { 5062 struct macb *bp = netdev_priv(netdev); 5063 u32 ctl; 5064 int ret; 5065 5066 ret = pm_runtime_resume_and_get(&bp->pdev->dev); 5067 if (ret < 0) 5068 return ret; 5069 5070 /* Clear internal statistics */ 5071 ctl = macb_readl(bp, NCR); 5072 macb_writel(bp, NCR, ctl | MACB_BIT(CLRSTAT)); 5073 5074 macb_set_hwaddr(bp); 5075 5076 ret = at91ether_start(bp); 5077 if (ret) 5078 goto pm_exit; 5079 5080 ret = macb_phylink_connect(bp); 5081 if (ret) 5082 goto stop; 5083 5084 netif_start_queue(netdev); 5085 5086 return 0; 5087 5088 stop: 5089 at91ether_stop(bp); 5090 pm_exit: 5091 pm_runtime_put_sync(&bp->pdev->dev); 5092 return ret; 5093 } 5094 5095 /* Close the interface */ 5096 static int at91ether_close(struct net_device *netdev) 5097 { 5098 struct macb *bp = netdev_priv(netdev); 5099 5100 netif_stop_queue(netdev); 5101 5102 phylink_stop(bp->phylink); 5103 phylink_disconnect_phy(bp->phylink); 5104 5105 at91ether_stop(bp); 5106 5107 pm_runtime_put(&bp->pdev->dev); 5108 5109 return 0; 5110 } 5111 5112 /* Transmit packet */ 5113 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb, 5114 struct net_device *netdev) 5115 { 5116 struct macb *bp = netdev_priv(netdev); 5117 struct device *dev = &bp->pdev->dev; 5118 5119 if (macb_readl(bp, TSR) & MACB_BIT(RM9200_BNQ)) { 5120 int desc = 0; 5121 5122 netif_stop_queue(netdev); 5123 5124 /* Store packet information (to free when Tx completed) */ 5125 bp->rm9200_txq[desc].skb = skb; 5126 bp->rm9200_txq[desc].size = skb->len; 5127 bp->rm9200_txq[desc].mapping = dma_map_single(dev, skb->data, 5128 skb->len, 5129 DMA_TO_DEVICE); 5130 if (dma_mapping_error(dev, bp->rm9200_txq[desc].mapping)) { 5131 dev_kfree_skb_any(skb); 5132 netdev->stats.tx_dropped++; 5133 netdev_err(netdev, "%s: DMA mapping error\n", __func__); 5134 return NETDEV_TX_OK; 5135 } 5136 5137 /* Set address of the data in the Transmit Address register */ 5138 macb_writel(bp, TAR, bp->rm9200_txq[desc].mapping); 5139 /* Set length of the packet in the Transmit Control register */ 5140 macb_writel(bp, TCR, skb->len); 5141 5142 } else { 5143 netdev_err(netdev, "%s called, but device is busy!\n", 5144 __func__); 5145 return NETDEV_TX_BUSY; 5146 } 5147 5148 return NETDEV_TX_OK; 5149 } 5150 5151 /* Extract received frame from buffer descriptors and sent to upper layers. 5152 * (Called from interrupt context) 5153 */ 5154 static void at91ether_rx(struct net_device *netdev) 5155 { 5156 struct macb *bp = netdev_priv(netdev); 5157 struct macb_queue *queue = &bp->queues[0]; 5158 struct macb_dma_desc *desc; 5159 unsigned char *p_recv; 5160 struct sk_buff *skb; 5161 unsigned int pktlen; 5162 5163 desc = macb_rx_desc(queue, queue->rx_tail); 5164 while (desc->addr & MACB_BIT(RX_USED)) { 5165 p_recv = queue->rx_buffers + 5166 queue->rx_tail * AT91ETHER_MAX_RBUFF_SZ; 5167 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl); 5168 skb = netdev_alloc_skb(netdev, pktlen + 2); 5169 if (skb) { 5170 skb_reserve(skb, 2); 5171 skb_put_data(skb, p_recv, pktlen); 5172 5173 skb->protocol = eth_type_trans(skb, netdev); 5174 netdev->stats.rx_packets++; 5175 netdev->stats.rx_bytes += pktlen; 5176 netif_rx(skb); 5177 } else { 5178 netdev->stats.rx_dropped++; 5179 } 5180 5181 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH)) 5182 netdev->stats.multicast++; 5183 5184 /* reset ownership bit */ 5185 desc->addr &= ~MACB_BIT(RX_USED); 5186 5187 /* wrap after last buffer */ 5188 if (queue->rx_tail == AT91ETHER_MAX_RX_DESCR - 1) 5189 queue->rx_tail = 0; 5190 else 5191 queue->rx_tail++; 5192 5193 desc = macb_rx_desc(queue, queue->rx_tail); 5194 } 5195 } 5196 5197 /* MAC interrupt handler */ 5198 static irqreturn_t at91ether_interrupt(int irq, void *dev_id) 5199 { 5200 struct net_device *netdev = dev_id; 5201 struct macb *bp = netdev_priv(netdev); 5202 u32 intstatus, ctl; 5203 unsigned int desc; 5204 5205 /* MAC Interrupt Status register indicates what interrupts are pending. 5206 * It is automatically cleared once read. 5207 */ 5208 intstatus = macb_readl(bp, ISR); 5209 5210 /* Receive complete */ 5211 if (intstatus & MACB_BIT(RCOMP)) 5212 at91ether_rx(netdev); 5213 5214 /* Transmit complete */ 5215 if (intstatus & MACB_BIT(TCOMP)) { 5216 /* The TCOM bit is set even if the transmission failed */ 5217 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE))) 5218 netdev->stats.tx_errors++; 5219 5220 desc = 0; 5221 if (bp->rm9200_txq[desc].skb) { 5222 dev_consume_skb_irq(bp->rm9200_txq[desc].skb); 5223 bp->rm9200_txq[desc].skb = NULL; 5224 dma_unmap_single(&bp->pdev->dev, 5225 bp->rm9200_txq[desc].mapping, 5226 bp->rm9200_txq[desc].size, 5227 DMA_TO_DEVICE); 5228 netdev->stats.tx_packets++; 5229 netdev->stats.tx_bytes += bp->rm9200_txq[desc].size; 5230 } 5231 netif_wake_queue(netdev); 5232 } 5233 5234 /* Work-around for EMAC Errata section 41.3.1 */ 5235 if (intstatus & MACB_BIT(RXUBR)) { 5236 ctl = macb_readl(bp, NCR); 5237 macb_writel(bp, NCR, ctl & ~MACB_BIT(RE)); 5238 wmb(); 5239 macb_writel(bp, NCR, ctl | MACB_BIT(RE)); 5240 } 5241 5242 if (intstatus & MACB_BIT(ISR_ROVR)) 5243 netdev_err(netdev, "ROVR error\n"); 5244 5245 return IRQ_HANDLED; 5246 } 5247 5248 #ifdef CONFIG_NET_POLL_CONTROLLER 5249 static void at91ether_poll_controller(struct net_device *netdev) 5250 { 5251 unsigned long flags; 5252 5253 local_irq_save(flags); 5254 at91ether_interrupt(netdev->irq, netdev); 5255 local_irq_restore(flags); 5256 } 5257 #endif 5258 5259 static const struct net_device_ops at91ether_netdev_ops = { 5260 .ndo_open = at91ether_open, 5261 .ndo_stop = at91ether_close, 5262 .ndo_start_xmit = at91ether_start_xmit, 5263 .ndo_get_stats64 = macb_get_stats, 5264 .ndo_set_rx_mode = macb_set_rx_mode, 5265 .ndo_set_mac_address = eth_mac_addr, 5266 .ndo_eth_ioctl = macb_ioctl, 5267 .ndo_validate_addr = eth_validate_addr, 5268 #ifdef CONFIG_NET_POLL_CONTROLLER 5269 .ndo_poll_controller = at91ether_poll_controller, 5270 #endif 5271 .ndo_hwtstamp_set = macb_hwtstamp_set, 5272 .ndo_hwtstamp_get = macb_hwtstamp_get, 5273 }; 5274 5275 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk, 5276 struct clk **hclk, struct clk **tx_clk, 5277 struct clk **rx_clk, struct clk **tsu_clk) 5278 { 5279 int err; 5280 5281 *hclk = NULL; 5282 *tx_clk = NULL; 5283 *rx_clk = NULL; 5284 *tsu_clk = NULL; 5285 5286 *pclk = devm_clk_get(&pdev->dev, "ether_clk"); 5287 if (IS_ERR(*pclk)) 5288 return PTR_ERR(*pclk); 5289 5290 err = clk_prepare_enable(*pclk); 5291 if (err) { 5292 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err); 5293 return err; 5294 } 5295 5296 return 0; 5297 } 5298 5299 static int at91ether_init(struct platform_device *pdev) 5300 { 5301 struct net_device *netdev = platform_get_drvdata(pdev); 5302 struct macb *bp = netdev_priv(netdev); 5303 int err; 5304 5305 bp->queues[0].bp = bp; 5306 5307 netdev->netdev_ops = &at91ether_netdev_ops; 5308 netdev->ethtool_ops = &macb_ethtool_ops; 5309 5310 err = devm_request_irq(&pdev->dev, netdev->irq, at91ether_interrupt, 5311 0, netdev->name, netdev); 5312 if (err) 5313 return err; 5314 5315 macb_writel(bp, NCR, 0); 5316 5317 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG)); 5318 5319 return 0; 5320 } 5321 5322 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw, 5323 unsigned long parent_rate) 5324 { 5325 return mgmt->rate; 5326 } 5327 5328 static int fu540_macb_tx_determine_rate(struct clk_hw *hw, 5329 struct clk_rate_request *req) 5330 { 5331 if (WARN_ON(req->rate < 2500000)) 5332 req->rate = 2500000; 5333 else if (req->rate == 2500000) 5334 req->rate = 2500000; 5335 else if (WARN_ON(req->rate < 13750000)) 5336 req->rate = 2500000; 5337 else if (WARN_ON(req->rate < 25000000)) 5338 req->rate = 25000000; 5339 else if (req->rate == 25000000) 5340 req->rate = 25000000; 5341 else if (WARN_ON(req->rate < 75000000)) 5342 req->rate = 25000000; 5343 else if (WARN_ON(req->rate < 125000000)) 5344 req->rate = 125000000; 5345 else if (req->rate == 125000000) 5346 req->rate = 125000000; 5347 else if (WARN_ON(req->rate > 125000000)) 5348 req->rate = 125000000; 5349 else 5350 req->rate = 125000000; 5351 5352 return 0; 5353 } 5354 5355 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate, 5356 unsigned long parent_rate) 5357 { 5358 struct clk_rate_request req; 5359 int ret; 5360 5361 clk_hw_init_rate_request(hw, &req, rate); 5362 ret = fu540_macb_tx_determine_rate(hw, &req); 5363 if (ret != 0) 5364 return ret; 5365 5366 if (req.rate != 125000000) 5367 iowrite32(1, mgmt->reg); 5368 else 5369 iowrite32(0, mgmt->reg); 5370 mgmt->rate = rate; 5371 5372 return 0; 5373 } 5374 5375 static const struct clk_ops fu540_c000_ops = { 5376 .recalc_rate = fu540_macb_tx_recalc_rate, 5377 .determine_rate = fu540_macb_tx_determine_rate, 5378 .set_rate = fu540_macb_tx_set_rate, 5379 }; 5380 5381 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk, 5382 struct clk **hclk, struct clk **tx_clk, 5383 struct clk **rx_clk, struct clk **tsu_clk) 5384 { 5385 struct clk_init_data init; 5386 int err = 0; 5387 5388 err = macb_clk_init_dflt(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk); 5389 if (err) 5390 return err; 5391 5392 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL); 5393 if (!mgmt) { 5394 err = -ENOMEM; 5395 goto err_disable_clks; 5396 } 5397 5398 init.name = "sifive-gemgxl-mgmt"; 5399 init.ops = &fu540_c000_ops; 5400 init.flags = 0; 5401 init.num_parents = 0; 5402 5403 mgmt->rate = 0; 5404 mgmt->hw.init = &init; 5405 5406 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw); 5407 if (IS_ERR(*tx_clk)) { 5408 err = PTR_ERR(*tx_clk); 5409 goto err_disable_clks; 5410 } 5411 5412 err = clk_prepare_enable(*tx_clk); 5413 if (err) { 5414 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); 5415 *tx_clk = NULL; 5416 goto err_disable_clks; 5417 } else { 5418 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name); 5419 } 5420 5421 return 0; 5422 5423 err_disable_clks: 5424 macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk); 5425 5426 return err; 5427 } 5428 5429 static int fu540_c000_init(struct platform_device *pdev) 5430 { 5431 mgmt->reg = devm_platform_ioremap_resource(pdev, 1); 5432 if (IS_ERR(mgmt->reg)) 5433 return PTR_ERR(mgmt->reg); 5434 5435 return macb_init_dflt(pdev); 5436 } 5437 5438 static int init_reset_optional(struct platform_device *pdev) 5439 { 5440 struct net_device *netdev = platform_get_drvdata(pdev); 5441 struct macb *bp = netdev_priv(netdev); 5442 int ret; 5443 5444 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { 5445 /* Ensure PHY device used in SGMII mode is ready */ 5446 bp->phy = devm_phy_optional_get(&pdev->dev, NULL); 5447 5448 if (IS_ERR(bp->phy)) 5449 return dev_err_probe(&pdev->dev, PTR_ERR(bp->phy), 5450 "failed to get SGMII PHY\n"); 5451 5452 ret = phy_init(bp->phy); 5453 if (ret) 5454 return dev_err_probe(&pdev->dev, ret, 5455 "failed to init SGMII PHY\n"); 5456 5457 ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_GEM_CONFIG); 5458 if (!ret) { 5459 u32 pm_info[2]; 5460 5461 ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains", 5462 pm_info, ARRAY_SIZE(pm_info)); 5463 if (ret) { 5464 dev_err(&pdev->dev, "Failed to read power management information\n"); 5465 goto err_out_phy_exit; 5466 } 5467 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_FIXED, 0); 5468 if (ret) 5469 goto err_out_phy_exit; 5470 5471 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_SGMII_MODE, 1); 5472 if (ret) 5473 goto err_out_phy_exit; 5474 } 5475 5476 } 5477 5478 /* Fully reset controller at hardware level if mapped in device tree */ 5479 ret = device_reset_optional(&pdev->dev); 5480 if (ret) { 5481 phy_exit(bp->phy); 5482 return dev_err_probe(&pdev->dev, ret, "failed to reset controller"); 5483 } 5484 5485 ret = macb_init_dflt(pdev); 5486 5487 err_out_phy_exit: 5488 if (ret) 5489 phy_exit(bp->phy); 5490 5491 return ret; 5492 } 5493 5494 static int eyeq5_init(struct platform_device *pdev) 5495 { 5496 struct net_device *netdev = platform_get_drvdata(pdev); 5497 struct macb *bp = netdev_priv(netdev); 5498 struct device *dev = &pdev->dev; 5499 int ret; 5500 5501 bp->phy = devm_phy_get(dev, NULL); 5502 if (IS_ERR(bp->phy)) 5503 return dev_err_probe(dev, PTR_ERR(bp->phy), 5504 "failed to get PHY\n"); 5505 5506 ret = phy_init(bp->phy); 5507 if (ret) 5508 return dev_err_probe(dev, ret, "failed to init PHY\n"); 5509 5510 ret = macb_init_dflt(pdev); 5511 if (ret) 5512 phy_exit(bp->phy); 5513 return ret; 5514 } 5515 5516 static int macb_alloc_tieoff(struct macb *bp) 5517 { 5518 /* Tieoff is a workaround in case HW cannot disable queues, for PM. */ 5519 if (bp->caps & MACB_CAPS_QUEUE_DISABLE) 5520 return 0; 5521 5522 bp->rx_ring_tieoff = dma_alloc_coherent(&bp->pdev->dev, 5523 macb_dma_desc_get_size(bp), 5524 &bp->rx_ring_tieoff_dma, 5525 GFP_KERNEL); 5526 if (!bp->rx_ring_tieoff) 5527 return -ENOMEM; 5528 5529 macb_set_addr(bp, bp->rx_ring_tieoff, 5530 MACB_BIT(RX_WRAP) | MACB_BIT(RX_USED)); 5531 5532 bp->rx_ring_tieoff->ctrl = 0; 5533 5534 return 0; 5535 } 5536 5537 static void macb_free_tieoff(struct macb *bp) 5538 { 5539 if (!bp->rx_ring_tieoff) 5540 return; 5541 5542 dma_free_coherent(&bp->pdev->dev, macb_dma_desc_get_size(bp), 5543 bp->rx_ring_tieoff, 5544 bp->rx_ring_tieoff_dma); 5545 bp->rx_ring_tieoff = NULL; 5546 } 5547 5548 static const struct macb_usrio_config mpfs_usrio = { 5549 .tsu_source = 0, 5550 }; 5551 5552 static const struct macb_usrio_config sama7g5_gem_usrio = { 5553 .mii = 0, 5554 .rmii = 1, 5555 .rgmii = 2, 5556 .refclk = BIT(2), 5557 .refclk_default_external = false, 5558 .hdfctlen = BIT(6), 5559 }; 5560 5561 static const struct macb_usrio_config sama7g5_emac_usrio = { 5562 .mii = 0, 5563 .rmii = 1, 5564 .rgmii = 2, 5565 .refclk = BIT(2), 5566 .refclk_default_external = true, 5567 .hdfctlen = BIT(6), 5568 }; 5569 5570 static const struct macb_config fu540_c000_config = { 5571 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | 5572 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_USRIO_HAS_MII, 5573 .dma_burst_length = 16, 5574 .clk_init = fu540_c000_clk_init, 5575 .init = fu540_c000_init, 5576 .jumbo_max_len = 10240, 5577 .usrio = &at91_default_usrio, 5578 }; 5579 5580 static const struct macb_config at91sam9260_config = { 5581 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | 5582 MACB_CAPS_USRIO_HAS_MII, 5583 .usrio = &at91_default_usrio, 5584 }; 5585 5586 static const struct macb_config sama5d3macb_config = { 5587 .caps = MACB_CAPS_SG_DISABLED | 5588 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | 5589 MACB_CAPS_USRIO_HAS_MII, 5590 .usrio = &at91_default_usrio, 5591 }; 5592 5593 static const struct macb_config pc302gem_config = { 5594 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE | 5595 MACB_CAPS_USRIO_HAS_MII, 5596 .dma_burst_length = 16, 5597 .usrio = &at91_default_usrio, 5598 }; 5599 5600 static const struct macb_config sama5d2_config = { 5601 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO | 5602 MACB_CAPS_USRIO_HAS_MII, 5603 .dma_burst_length = 16, 5604 .jumbo_max_len = 10240, 5605 .usrio = &at91_default_usrio, 5606 }; 5607 5608 static const struct macb_config sama5d29_config = { 5609 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP | 5610 MACB_CAPS_USRIO_HAS_MII, 5611 .dma_burst_length = 16, 5612 .usrio = &at91_default_usrio, 5613 }; 5614 5615 static const struct macb_config sama5d3_config = { 5616 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE | 5617 MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO | 5618 MACB_CAPS_USRIO_HAS_MII, 5619 .dma_burst_length = 16, 5620 .jumbo_max_len = 10240, 5621 .usrio = &at91_default_usrio, 5622 }; 5623 5624 static const struct macb_config sama5d4_config = { 5625 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | 5626 MACB_CAPS_USRIO_HAS_MII, 5627 .dma_burst_length = 4, 5628 .usrio = &at91_default_usrio, 5629 }; 5630 5631 static const struct macb_config emac_config = { 5632 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC | 5633 MACB_CAPS_USRIO_HAS_MII, 5634 .clk_init = at91ether_clk_init, 5635 .init = at91ether_init, 5636 .usrio = &at91_default_usrio, 5637 }; 5638 5639 static const struct macb_config np4_config = { 5640 .caps = MACB_CAPS_USRIO_DISABLED, 5641 }; 5642 5643 static const struct macb_config zynqmp_config = { 5644 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | 5645 MACB_CAPS_JUMBO | 5646 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | 5647 MACB_CAPS_USRIO_HAS_MII, 5648 .dma_burst_length = 16, 5649 .init = init_reset_optional, 5650 .jumbo_max_len = 10240, 5651 .usrio = &at91_default_usrio, 5652 }; 5653 5654 static const struct macb_config zynq_config = { 5655 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF | 5656 MACB_CAPS_NEEDS_RSTONUBR | 5657 MACB_CAPS_USRIO_HAS_MII, 5658 .dma_burst_length = 16, 5659 .usrio = &at91_default_usrio, 5660 }; 5661 5662 static const struct macb_config mpfs_config = { 5663 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | 5664 MACB_CAPS_JUMBO | 5665 MACB_CAPS_GEM_HAS_PTP | 5666 MACB_CAPS_USRIO_HAS_TSUCLK_SOURCE, 5667 .dma_burst_length = 16, 5668 .init = init_reset_optional, 5669 .usrio = &mpfs_usrio, 5670 .max_tx_length = 4040, /* Cadence Erratum 1686 */ 5671 .jumbo_max_len = 4040, 5672 }; 5673 5674 static const struct macb_config sama7g5_gem_config = { 5675 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG | 5676 MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | 5677 MACB_CAPS_USRIO_HAS_REFCLK_SOURCE | 5678 MACB_CAPS_MIIONRGMII | MACB_CAPS_GEM_HAS_PTP | 5679 MACB_CAPS_USRIO_HAS_MII, 5680 .dma_burst_length = 16, 5681 .usrio = &sama7g5_gem_usrio, 5682 }; 5683 5684 static const struct macb_config sama7g5_emac_config = { 5685 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | 5686 MACB_CAPS_MIIONRGMII | 5687 MACB_CAPS_USRIO_HAS_REFCLK_SOURCE | 5688 MACB_CAPS_GEM_HAS_PTP | 5689 MACB_CAPS_USRIO_HAS_MII, 5690 .dma_burst_length = 16, 5691 .usrio = &sama7g5_emac_usrio, 5692 }; 5693 5694 static const struct macb_config versal_config = { 5695 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | 5696 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | 5697 MACB_CAPS_NEED_TSUCLK | MACB_CAPS_QUEUE_DISABLE | 5698 MACB_CAPS_QBV | 5699 MACB_CAPS_USRIO_HAS_MII, 5700 .dma_burst_length = 16, 5701 .init = init_reset_optional, 5702 .jumbo_max_len = 10240, 5703 .usrio = &at91_default_usrio, 5704 }; 5705 5706 static const struct macb_config eyeq5_config = { 5707 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | 5708 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_QUEUE_DISABLE | 5709 MACB_CAPS_NO_LSO | MACB_CAPS_EEE, 5710 .dma_burst_length = 16, 5711 .init = eyeq5_init, 5712 .jumbo_max_len = 10240, 5713 }; 5714 5715 static const struct macb_config raspberrypi_rp1_config = { 5716 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG | 5717 MACB_CAPS_JUMBO | 5718 MACB_CAPS_GEM_HAS_PTP | 5719 MACB_CAPS_EEE | 5720 MACB_CAPS_USRIO_HAS_MII, 5721 .dma_burst_length = 16, 5722 .usrio = &at91_default_usrio, 5723 .jumbo_max_len = 10240, 5724 }; 5725 5726 static const struct macb_config pic64hpsc_config = { 5727 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | 5728 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_USRIO_DISABLED, 5729 .dma_burst_length = 16, 5730 .init = init_reset_optional, 5731 .jumbo_max_len = 16383, 5732 }; 5733 5734 static const struct of_device_id macb_dt_ids[] = { 5735 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, 5736 { .compatible = "cdns,macb" }, 5737 { .compatible = "cdns,np4-macb", .data = &np4_config }, 5738 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config }, 5739 { .compatible = "cdns,gem", .data = &pc302gem_config }, 5740 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config }, 5741 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config }, 5742 { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config }, 5743 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config }, 5744 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config }, 5745 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config }, 5746 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config }, 5747 { .compatible = "cdns,emac", .data = &emac_config }, 5748 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */ 5749 { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */ 5750 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, 5751 { .compatible = "microchip,mpfs-macb", .data = &mpfs_config }, 5752 { .compatible = "microchip,pic64hpsc-gem", .data = &pic64hpsc_config}, 5753 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, 5754 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config }, 5755 { .compatible = "mobileye,eyeq5-gem", .data = &eyeq5_config }, 5756 { .compatible = "raspberrypi,rp1-gem", .data = &raspberrypi_rp1_config }, 5757 { .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config}, 5758 { .compatible = "xlnx,zynq-gem", .data = &zynq_config }, 5759 { .compatible = "xlnx,versal-gem", .data = &versal_config}, 5760 { /* sentinel */ } 5761 }; 5762 MODULE_DEVICE_TABLE(of, macb_dt_ids); 5763 5764 static const struct macb_config default_gem_config = { 5765 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | 5766 MACB_CAPS_JUMBO | 5767 MACB_CAPS_GEM_HAS_PTP, 5768 .dma_burst_length = 16, 5769 .usrio = &at91_default_usrio, 5770 .jumbo_max_len = 10240, 5771 }; 5772 5773 static int macb_probe(struct platform_device *pdev) 5774 { 5775 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL; 5776 struct device_node *np = pdev->dev.of_node; 5777 const struct macb_config *macb_config; 5778 struct clk *tsu_clk = NULL; 5779 phy_interface_t interface; 5780 struct net_device *netdev; 5781 struct resource *regs; 5782 u32 wtrmrk_rst_val; 5783 void __iomem *mem; 5784 struct macb *bp; 5785 int num_queues; 5786 bool native_io; 5787 int err, val; 5788 5789 mem = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); 5790 if (IS_ERR(mem)) 5791 return PTR_ERR(mem); 5792 5793 macb_config = of_device_get_match_data(&pdev->dev); 5794 if (!macb_config) 5795 macb_config = &default_gem_config; 5796 5797 err = macb_clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk, 5798 macb_config); 5799 if (err) 5800 return err; 5801 5802 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT); 5803 pm_runtime_use_autosuspend(&pdev->dev); 5804 pm_runtime_get_noresume(&pdev->dev); 5805 pm_runtime_set_active(&pdev->dev); 5806 pm_runtime_enable(&pdev->dev); 5807 native_io = hw_is_native_io(mem); 5808 5809 num_queues = macb_probe_queues(&pdev->dev, mem, native_io); 5810 if (num_queues < 0) { 5811 err = num_queues; 5812 goto err_disable_clocks; 5813 } 5814 5815 netdev = alloc_etherdev_mq(sizeof(*bp), num_queues); 5816 if (!netdev) { 5817 err = -ENOMEM; 5818 goto err_disable_clocks; 5819 } 5820 5821 netdev->base_addr = regs->start; 5822 5823 SET_NETDEV_DEV(netdev, &pdev->dev); 5824 5825 bp = netdev_priv(netdev); 5826 bp->pdev = pdev; 5827 bp->netdev = netdev; 5828 bp->regs = mem; 5829 bp->native_io = native_io; 5830 if (native_io) { 5831 bp->macb_reg_readl = hw_readl_native; 5832 bp->macb_reg_writel = hw_writel_native; 5833 } else { 5834 bp->macb_reg_readl = hw_readl; 5835 bp->macb_reg_writel = hw_writel; 5836 } 5837 bp->num_queues = num_queues; 5838 bp->dma_burst_length = macb_config->dma_burst_length; 5839 bp->pclk = pclk; 5840 bp->hclk = hclk; 5841 bp->tx_clk = tx_clk; 5842 bp->rx_clk = rx_clk; 5843 bp->tsu_clk = tsu_clk; 5844 bp->jumbo_max_len = macb_config->jumbo_max_len; 5845 5846 if (!hw_is_gem(bp->regs, bp->native_io)) 5847 bp->max_tx_length = MACB_MAX_TX_LEN; 5848 else if (macb_config->max_tx_length) 5849 bp->max_tx_length = macb_config->max_tx_length; 5850 else 5851 bp->max_tx_length = GEM_MAX_TX_LEN; 5852 5853 bp->wol = 0; 5854 device_set_wakeup_capable(&pdev->dev, 1); 5855 5856 bp->usrio = macb_config->usrio; 5857 5858 if (of_property_read_bool(bp->pdev->dev.of_node, "cdns,timer-adjust") && 5859 IS_ENABLED(CONFIG_MACB_USE_HWSTAMP)) { 5860 dev_err(&pdev->dev, "Timer adjust mode is not supported\n"); 5861 err = -EINVAL; 5862 goto err_out_free_netdev; 5863 } 5864 5865 /* By default we set to partial store and forward mode for zynqmp. 5866 * Disable if not set in devicetree. 5867 */ 5868 if (GEM_BFEXT(PBUF_CUTTHRU, gem_readl(bp, DCFG6))) { 5869 err = of_property_read_u32(bp->pdev->dev.of_node, 5870 "cdns,rx-watermark", 5871 &bp->rx_watermark); 5872 5873 if (!err) { 5874 /* Disable partial store and forward in case of error or 5875 * invalid watermark value 5876 */ 5877 wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1; 5878 if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) { 5879 dev_info(&bp->pdev->dev, "Invalid watermark value\n"); 5880 bp->rx_watermark = 0; 5881 } 5882 } 5883 } 5884 spin_lock_init(&bp->lock); 5885 spin_lock_init(&bp->stats_lock); 5886 spin_lock_init(&bp->tsu_clk_lock); 5887 5888 /* setup capabilities */ 5889 macb_configure_caps(bp, macb_config); 5890 5891 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 5892 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) { 5893 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 5894 if (err) { 5895 dev_err(&pdev->dev, "failed to set DMA mask\n"); 5896 goto err_out_free_netdev; 5897 } 5898 bp->caps |= MACB_CAPS_DMA_64B; 5899 } 5900 #endif 5901 platform_set_drvdata(pdev, netdev); 5902 5903 netdev->irq = platform_get_irq(pdev, 0); 5904 if (netdev->irq < 0) { 5905 err = netdev->irq; 5906 goto err_out_free_netdev; 5907 } 5908 5909 /* MTU range: 68 - 1518 or 10240 */ 5910 netdev->min_mtu = GEM_MTU_MIN_SIZE; 5911 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len) 5912 netdev->max_mtu = MIN(bp->jumbo_max_len, RX_BUFFER_MAX) - 5913 ETH_HLEN - ETH_FCS_LEN; 5914 else 5915 netdev->max_mtu = 1536 - ETH_HLEN - ETH_FCS_LEN; 5916 5917 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) { 5918 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10)); 5919 if (val) 5920 bp->rx_bd_rd_prefetch = (2 << (val - 1)) * 5921 macb_dma_desc_get_size(bp); 5922 5923 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10)); 5924 if (val) 5925 bp->tx_bd_rd_prefetch = (2 << (val - 1)) * 5926 macb_dma_desc_get_size(bp); 5927 } 5928 5929 bp->rx_intr_mask = MACB_RX_INT_FLAGS; 5930 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR) 5931 bp->rx_intr_mask |= MACB_BIT(RXUBR); 5932 5933 err = of_get_ethdev_address(np, bp->netdev); 5934 if (err == -EPROBE_DEFER) 5935 goto err_out_free_netdev; 5936 else if (err) 5937 macb_get_hwaddr(bp); 5938 5939 err = of_get_phy_mode(np, &interface); 5940 if (err) 5941 /* not found in DT, MII by default */ 5942 bp->phy_interface = PHY_INTERFACE_MODE_MII; 5943 else 5944 bp->phy_interface = interface; 5945 5946 /* IP specific init */ 5947 err = macb_init(pdev, macb_config); 5948 if (err) 5949 goto err_out_free_netdev; 5950 5951 err = macb_mii_init(bp); 5952 if (err) 5953 goto err_out_phy_exit; 5954 5955 netif_carrier_off(netdev); 5956 5957 err = macb_alloc_tieoff(bp); 5958 if (err) 5959 goto err_out_unregister_mdio; 5960 5961 err = register_netdev(netdev); 5962 if (err) { 5963 dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); 5964 goto err_out_free_tieoff; 5965 } 5966 5967 INIT_WORK(&bp->hresp_err_bh_work, macb_hresp_error_task); 5968 INIT_DELAYED_WORK(&bp->tx_lpi_work, macb_tx_lpi_work_fn); 5969 5970 netdev_info(netdev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n", 5971 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID), 5972 netdev->base_addr, netdev->irq, netdev->dev_addr); 5973 5974 pm_runtime_put_autosuspend(&bp->pdev->dev); 5975 5976 return 0; 5977 5978 err_out_free_tieoff: 5979 macb_free_tieoff(bp); 5980 5981 err_out_unregister_mdio: 5982 if (bp->mii_bus) { 5983 mdiobus_unregister(bp->mii_bus); 5984 mdiobus_free(bp->mii_bus); 5985 } 5986 phylink_destroy(bp->phylink); 5987 5988 err_out_phy_exit: 5989 phy_exit(bp->phy); 5990 5991 err_out_free_netdev: 5992 free_netdev(netdev); 5993 5994 err_disable_clocks: 5995 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk); 5996 pm_runtime_disable(&pdev->dev); 5997 pm_runtime_set_suspended(&pdev->dev); 5998 pm_runtime_dont_use_autosuspend(&pdev->dev); 5999 6000 return err; 6001 } 6002 6003 static void macb_remove(struct platform_device *pdev) 6004 { 6005 struct net_device *netdev; 6006 struct macb *bp; 6007 6008 netdev = platform_get_drvdata(pdev); 6009 6010 if (netdev) { 6011 bp = netdev_priv(netdev); 6012 unregister_netdev(netdev); 6013 macb_free_tieoff(bp); 6014 phy_exit(bp->phy); 6015 if (bp->mii_bus) { 6016 mdiobus_unregister(bp->mii_bus); 6017 mdiobus_free(bp->mii_bus); 6018 } 6019 6020 device_set_wakeup_enable(&bp->pdev->dev, 0); 6021 cancel_delayed_work_sync(&bp->tx_lpi_work); 6022 cancel_work_sync(&bp->hresp_err_bh_work); 6023 pm_runtime_disable(&pdev->dev); 6024 pm_runtime_dont_use_autosuspend(&pdev->dev); 6025 pm_runtime_set_suspended(&pdev->dev); 6026 phylink_destroy(bp->phylink); 6027 free_netdev(netdev); 6028 } 6029 } 6030 6031 static int __maybe_unused macb_suspend(struct device *dev) 6032 { 6033 struct net_device *netdev = dev_get_drvdata(dev); 6034 struct macb *bp = netdev_priv(netdev); 6035 struct in_ifaddr *ifa = NULL; 6036 struct macb_queue *queue; 6037 struct in_device *idev; 6038 unsigned long flags; 6039 u32 tmp, ifa_local; 6040 unsigned int q; 6041 6042 if (!device_may_wakeup(&bp->netdev->dev)) 6043 phy_exit(bp->phy); 6044 6045 if (!netif_running(netdev)) 6046 return 0; 6047 6048 if (bp->wol & MACB_WOL_ENABLED) { 6049 if (bp->wolopts & WAKE_ARP) { 6050 /* Check for IP address in WOL ARP mode */ 6051 rcu_read_lock(); 6052 idev = __in_dev_get_rcu(bp->netdev); 6053 if (idev) 6054 ifa = rcu_dereference(idev->ifa_list); 6055 if (!ifa) { 6056 rcu_read_unlock(); 6057 netdev_err(netdev, "IP address not assigned as required by WoL walk ARP\n"); 6058 return -EOPNOTSUPP; 6059 } 6060 ifa_local = be32_to_cpu(ifa->ifa_local); 6061 rcu_read_unlock(); 6062 } 6063 6064 spin_lock_irqsave(&bp->lock, flags); 6065 6066 /* Disable Tx and Rx engines before disabling the queues, 6067 * this is mandatory as per the IP spec sheet 6068 */ 6069 tmp = macb_readl(bp, NCR); 6070 macb_writel(bp, NCR, tmp & ~(MACB_BIT(TE) | MACB_BIT(RE))); 6071 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 6072 if (!(bp->caps & MACB_CAPS_QUEUE_DISABLE)) 6073 macb_writel(bp, RBQPH, 6074 upper_32_bits(bp->rx_ring_tieoff_dma)); 6075 #endif 6076 for (q = 0, queue = bp->queues; q < bp->num_queues; 6077 ++q, ++queue) { 6078 /* Disable RX queues */ 6079 if (bp->caps & MACB_CAPS_QUEUE_DISABLE) { 6080 queue_writel(queue, RBQP, MACB_BIT(QUEUE_DISABLE)); 6081 } else { 6082 /* Tie off RX queues */ 6083 queue_writel(queue, RBQP, 6084 lower_32_bits(bp->rx_ring_tieoff_dma)); 6085 } 6086 /* Disable all interrupts */ 6087 queue_writel(queue, IDR, -1); 6088 queue_readl(queue, ISR); 6089 macb_queue_isr_clear(bp, queue, -1); 6090 } 6091 /* Enable Receive engine */ 6092 macb_writel(bp, NCR, tmp | MACB_BIT(RE)); 6093 /* Flush all status bits */ 6094 macb_writel(bp, TSR, -1); 6095 macb_writel(bp, RSR, -1); 6096 6097 tmp = (bp->wolopts & WAKE_MAGIC) ? MACB_BIT(MAG) : 0; 6098 if (bp->wolopts & WAKE_ARP) { 6099 tmp |= MACB_BIT(ARP); 6100 /* write IP address into register */ 6101 tmp |= MACB_BFEXT(IP, ifa_local); 6102 } 6103 6104 if (macb_is_gem(bp)) { 6105 queue_writel(bp->queues, IER, GEM_BIT(WOL)); 6106 gem_writel(bp, WOL, tmp); 6107 } else { 6108 queue_writel(bp->queues, IER, MACB_BIT(WOL)); 6109 macb_writel(bp, WOL, tmp); 6110 } 6111 spin_unlock_irqrestore(&bp->lock, flags); 6112 6113 enable_irq_wake(bp->queues[0].irq); 6114 } 6115 6116 netif_device_detach(netdev); 6117 for (q = 0, queue = bp->queues; q < bp->num_queues; 6118 ++q, ++queue) { 6119 napi_disable(&queue->napi_rx); 6120 napi_disable(&queue->napi_tx); 6121 } 6122 6123 if (!(bp->wol & MACB_WOL_ENABLED)) { 6124 rtnl_lock(); 6125 phylink_stop(bp->phylink); 6126 rtnl_unlock(); 6127 spin_lock_irqsave(&bp->lock, flags); 6128 macb_reset_hw(bp); 6129 spin_unlock_irqrestore(&bp->lock, flags); 6130 } 6131 6132 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) 6133 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO); 6134 6135 if (netdev->hw_features & NETIF_F_NTUPLE) 6136 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT); 6137 6138 if (bp->ptp_info) 6139 bp->ptp_info->ptp_remove(netdev); 6140 if (!device_may_wakeup(dev)) 6141 pm_runtime_force_suspend(dev); 6142 6143 return 0; 6144 } 6145 6146 static int __maybe_unused macb_resume(struct device *dev) 6147 { 6148 struct net_device *netdev = dev_get_drvdata(dev); 6149 struct macb *bp = netdev_priv(netdev); 6150 struct macb_queue *queue; 6151 unsigned long flags; 6152 unsigned int q; 6153 6154 if (!device_may_wakeup(&bp->netdev->dev)) 6155 phy_init(bp->phy); 6156 6157 if (!netif_running(netdev)) 6158 return 0; 6159 6160 if (!device_may_wakeup(dev)) 6161 pm_runtime_force_resume(dev); 6162 6163 if (bp->wol & MACB_WOL_ENABLED) { 6164 spin_lock_irqsave(&bp->lock, flags); 6165 /* Disable WoL */ 6166 if (macb_is_gem(bp)) { 6167 queue_writel(bp->queues, IDR, GEM_BIT(WOL)); 6168 gem_writel(bp, WOL, 0); 6169 } else { 6170 queue_writel(bp->queues, IDR, MACB_BIT(WOL)); 6171 macb_writel(bp, WOL, 0); 6172 } 6173 /* Clear ISR on queue 0 */ 6174 queue_readl(bp->queues, ISR); 6175 macb_queue_isr_clear(bp, bp->queues, -1); 6176 spin_unlock_irqrestore(&bp->lock, flags); 6177 6178 disable_irq_wake(bp->queues[0].irq); 6179 6180 /* Now make sure we disable phy before moving 6181 * to common restore path 6182 */ 6183 rtnl_lock(); 6184 phylink_stop(bp->phylink); 6185 rtnl_unlock(); 6186 } 6187 6188 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) 6189 macb_init_buffers(bp); 6190 6191 for (q = 0, queue = bp->queues; q < bp->num_queues; 6192 ++q, ++queue) { 6193 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) { 6194 if (macb_is_gem(bp)) 6195 gem_init_rx_ring(queue); 6196 else 6197 macb_init_rx_ring(queue); 6198 } 6199 6200 napi_enable(&queue->napi_rx); 6201 napi_enable(&queue->napi_tx); 6202 } 6203 6204 if (netdev->hw_features & NETIF_F_NTUPLE) 6205 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2); 6206 6207 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) 6208 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio); 6209 6210 macb_writel(bp, NCR, MACB_BIT(MPE)); 6211 macb_init_hw(bp); 6212 macb_set_rx_mode(netdev); 6213 macb_restore_features(bp); 6214 rtnl_lock(); 6215 6216 phylink_start(bp->phylink); 6217 rtnl_unlock(); 6218 6219 netif_device_attach(netdev); 6220 if (bp->ptp_info) 6221 bp->ptp_info->ptp_init(netdev); 6222 6223 return 0; 6224 } 6225 6226 static int __maybe_unused macb_runtime_suspend(struct device *dev) 6227 { 6228 struct net_device *netdev = dev_get_drvdata(dev); 6229 struct macb *bp = netdev_priv(netdev); 6230 6231 if (!(device_may_wakeup(dev))) 6232 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk); 6233 else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) 6234 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk); 6235 6236 return 0; 6237 } 6238 6239 static int __maybe_unused macb_runtime_resume(struct device *dev) 6240 { 6241 struct net_device *netdev = dev_get_drvdata(dev); 6242 struct macb *bp = netdev_priv(netdev); 6243 6244 if (!(device_may_wakeup(dev))) { 6245 clk_prepare_enable(bp->pclk); 6246 clk_prepare_enable(bp->hclk); 6247 clk_prepare_enable(bp->tx_clk); 6248 clk_prepare_enable(bp->rx_clk); 6249 clk_prepare_enable(bp->tsu_clk); 6250 } else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) { 6251 clk_prepare_enable(bp->tsu_clk); 6252 } 6253 6254 return 0; 6255 } 6256 6257 static void macb_shutdown(struct platform_device *pdev) 6258 { 6259 struct net_device *netdev = platform_get_drvdata(pdev); 6260 6261 rtnl_lock(); 6262 6263 if (netif_running(netdev)) 6264 dev_close(netdev); 6265 6266 netif_device_detach(netdev); 6267 6268 rtnl_unlock(); 6269 } 6270 6271 static const struct dev_pm_ops macb_pm_ops = { 6272 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume) 6273 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL) 6274 }; 6275 6276 static struct platform_driver macb_driver = { 6277 .probe = macb_probe, 6278 .remove = macb_remove, 6279 .driver = { 6280 .name = "macb", 6281 .of_match_table = macb_dt_ids, 6282 .pm = &macb_pm_ops, 6283 }, 6284 .shutdown = macb_shutdown, 6285 }; 6286 6287 module_platform_driver(macb_driver); 6288 6289 MODULE_LICENSE("GPL"); 6290 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); 6291 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 6292 MODULE_ALIAS("platform:macb"); 6293