xref: /linux/drivers/clk/qcom/gcc-qcs404.c (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/platform_device.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/clk-provider.h>
11 #include <linux/regmap.h>
12 #include <linux/reset-controller.h>
13 
14 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
15 
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-pll.h"
19 #include "clk-rcg.h"
20 #include "clk-regmap.h"
21 #include "common.h"
22 #include "gdsc.h"
23 #include "reset.h"
24 
25 enum {
26 	DT_XO,
27 	DT_SLEEP_CLK,
28 	DT_PCIE_0_PIPE_CLK,
29 	DT_DSI0_PHY_PLL_OUT_DSICLK,
30 	DT_DSI0_PHY_PLL_OUT_BYTECLK,
31 	DT_HDMI_PHY_PLL_CLK,
32 };
33 
34 enum {
35 	P_DSI0_PHY_PLL_OUT_BYTECLK,
36 	P_DSI0_PHY_PLL_OUT_DSICLK,
37 	P_GPLL0_OUT_MAIN,
38 	P_GPLL1_OUT_MAIN,
39 	P_GPLL3_OUT_MAIN,
40 	P_GPLL4_OUT_MAIN,
41 	P_GPLL6_OUT_AUX,
42 	P_HDMI_PHY_PLL_CLK,
43 	P_PCIE_0_PIPE_CLK,
44 	P_SLEEP_CLK,
45 	P_XO,
46 };
47 
48 static const struct parent_map gcc_parent_map_1[] = {
49 	{ P_XO, 0 },
50 };
51 
52 static const struct clk_parent_data gcc_parent_data_1[] = {
53 	{ .index = DT_XO, .name = "xo-board" },
54 };
55 
56 static struct clk_fixed_factor cxo = {
57 	.mult = 1,
58 	.div = 1,
59 	.hw.init = &(struct clk_init_data){
60 		.name = "cxo",
61 		.parent_data = gcc_parent_data_1,
62 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
63 		.ops = &clk_fixed_factor_ops,
64 	},
65 };
66 
67 static struct clk_alpha_pll gpll0_sleep_clk_src = {
68 	.offset = 0x21000,
69 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
70 	.clkr = {
71 		.enable_reg = 0x45008,
72 		.enable_mask = BIT(23),
73 		.enable_is_inverted = true,
74 		.hw.init = &(struct clk_init_data){
75 			.name = "gpll0_sleep_clk_src",
76 			.parent_data = gcc_parent_data_1,
77 			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
78 			.ops = &clk_alpha_pll_ops,
79 		},
80 	},
81 };
82 
83 static struct clk_alpha_pll gpll0_out_main = {
84 	.offset = 0x21000,
85 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
86 	.flags = SUPPORTS_FSM_MODE,
87 	.clkr = {
88 		.enable_reg = 0x45000,
89 		.enable_mask = BIT(0),
90 		.hw.init = &(struct clk_init_data){
91 			.name = "gpll0_out_main",
92 			.parent_data = gcc_parent_data_1,
93 			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
94 			.ops = &clk_alpha_pll_ops,
95 		},
96 	},
97 };
98 
99 static struct clk_alpha_pll gpll0_ao_out_main = {
100 	.offset = 0x21000,
101 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
102 	.flags = SUPPORTS_FSM_MODE,
103 	.clkr = {
104 		.enable_reg = 0x45000,
105 		.enable_mask = BIT(0),
106 		.hw.init = &(struct clk_init_data){
107 			.name = "gpll0_ao_out_main",
108 			.parent_data = gcc_parent_data_1,
109 			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
110 			.flags = CLK_IS_CRITICAL,
111 			.ops = &clk_alpha_pll_fixed_ops,
112 		},
113 	},
114 };
115 
116 static struct clk_alpha_pll gpll1_out_main = {
117 	.offset = 0x20000,
118 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
119 	.clkr = {
120 		.enable_reg = 0x45000,
121 		.enable_mask = BIT(1),
122 		.hw.init = &(struct clk_init_data){
123 			.name = "gpll1_out_main",
124 			.parent_data = gcc_parent_data_1,
125 			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
126 			.ops = &clk_alpha_pll_ops,
127 		},
128 	},
129 };
130 
131 /* 930MHz configuration */
132 static const struct alpha_pll_config gpll3_config = {
133 	.l = 48,
134 	.alpha = 0x0,
135 	.alpha_en_mask = BIT(24),
136 	.post_div_mask = 0xf << 8,
137 	.post_div_val = 0x1 << 8,
138 	.vco_mask = 0x3 << 20,
139 	.main_output_mask = 0x1,
140 	.config_ctl_val = 0x4001055b,
141 };
142 
143 static const struct pll_vco gpll3_vco[] = {
144 	{ 700000000, 1400000000, 0 },
145 };
146 
147 static struct clk_alpha_pll gpll3_out_main = {
148 	.offset = 0x22000,
149 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
150 	.vco_table = gpll3_vco,
151 	.num_vco = ARRAY_SIZE(gpll3_vco),
152 	.clkr = {
153 		.hw.init = &(struct clk_init_data){
154 			.name = "gpll3_out_main",
155 			.parent_data = gcc_parent_data_1,
156 			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
157 			.ops = &clk_alpha_pll_ops,
158 		},
159 	},
160 };
161 
162 static struct clk_alpha_pll gpll4_out_main = {
163 	.offset = 0x24000,
164 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
165 	.clkr = {
166 		.enable_reg = 0x45000,
167 		.enable_mask = BIT(5),
168 		.hw.init = &(struct clk_init_data){
169 			.name = "gpll4_out_main",
170 			.parent_data = gcc_parent_data_1,
171 			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
172 			.ops = &clk_alpha_pll_ops,
173 		},
174 	},
175 };
176 
177 static struct clk_pll gpll6 = {
178 	.l_reg = 0x37004,
179 	.m_reg = 0x37008,
180 	.n_reg = 0x3700C,
181 	.config_reg = 0x37014,
182 	.mode_reg = 0x37000,
183 	.status_reg = 0x3701C,
184 	.status_bit = 17,
185 	.clkr.hw.init = &(struct clk_init_data){
186 		.name = "gpll6",
187 		.parent_data = gcc_parent_data_1,
188 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
189 		.ops = &clk_pll_ops,
190 	},
191 };
192 
193 static struct clk_regmap gpll6_out_aux = {
194 	.enable_reg = 0x45000,
195 	.enable_mask = BIT(7),
196 	.hw.init = &(struct clk_init_data){
197 		.name = "gpll6_out_aux",
198 		.parent_hws = (const struct clk_hw*[]) {
199 			&gpll6.clkr.hw,
200 		},
201 		.num_parents = 1,
202 		.ops = &clk_pll_vote_ops,
203 	},
204 };
205 
206 static const struct parent_map gcc_parent_map_0[] = {
207 	{ P_XO, 0 },
208 	{ P_GPLL0_OUT_MAIN, 1 },
209 };
210 
211 static const struct clk_parent_data gcc_parent_data_0[] = {
212 	{ .index = DT_XO, .name = "xo-board" },
213 	{ .hw = &gpll0_out_main.clkr.hw },
214 };
215 
216 static const struct clk_parent_data gcc_parent_data_ao_0[] = {
217 	{ .index = DT_XO, .name = "xo-board" },
218 	{ .hw = &gpll0_ao_out_main.clkr.hw },
219 };
220 
221 static const struct parent_map gcc_parent_map_2[] = {
222 	{ P_XO, 0 },
223 	{ P_GPLL0_OUT_MAIN, 1 },
224 	{ P_GPLL6_OUT_AUX, 2 },
225 	{ P_SLEEP_CLK, 6 },
226 };
227 
228 static const struct clk_parent_data gcc_parent_data_2[] = {
229 	{ .index = DT_XO, .name = "xo-board" },
230 	{ .hw = &gpll0_out_main.clkr.hw },
231 	{ .hw = &gpll6_out_aux.hw },
232 	{ .index = DT_SLEEP_CLK, .name = "sleep_clk" },
233 };
234 
235 static const struct parent_map gcc_parent_map_3[] = {
236 	{ P_XO, 0 },
237 	{ P_GPLL0_OUT_MAIN, 1 },
238 	{ P_GPLL6_OUT_AUX, 2 },
239 };
240 
241 static const struct clk_parent_data gcc_parent_data_3[] = {
242 	{ .index = DT_XO, .name = "xo-board" },
243 	{ .hw = &gpll0_out_main.clkr.hw },
244 	{ .hw = &gpll6_out_aux.hw },
245 };
246 
247 static const struct parent_map gcc_parent_map_4[] = {
248 	{ P_XO, 0 },
249 	{ P_GPLL1_OUT_MAIN, 1 },
250 };
251 
252 static const struct clk_parent_data gcc_parent_data_4[] = {
253 	{ .index = DT_XO, .name = "xo-board" },
254 	{ .hw = &gpll1_out_main.clkr.hw },
255 };
256 
257 static const struct parent_map gcc_parent_map_5[] = {
258 	{ P_XO, 0 },
259 	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
260 };
261 
262 static const struct clk_parent_data gcc_parent_data_5[] = {
263 	{ .index = DT_XO, .name = "xo-board" },
264 	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" },
265 };
266 
267 static const struct parent_map gcc_parent_map_6[] = {
268 	{ P_XO, 0 },
269 	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
270 };
271 
272 static const struct clk_parent_data gcc_parent_data_6[] = {
273 	{ .index = DT_XO, .name = "xo-board" },
274 	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" },
275 };
276 
277 static const struct parent_map gcc_parent_map_7[] = {
278 	{ P_XO, 0 },
279 	{ P_GPLL0_OUT_MAIN, 1 },
280 	{ P_GPLL3_OUT_MAIN, 2 },
281 	{ P_GPLL6_OUT_AUX, 3 },
282 };
283 
284 static const struct clk_parent_data gcc_parent_data_7[] = {
285 	{ .index = DT_XO, .name = "xo-board" },
286 	{ .hw = &gpll0_out_main.clkr.hw },
287 	{ .hw = &gpll3_out_main.clkr.hw },
288 	{ .hw = &gpll6_out_aux.hw },
289 };
290 
291 static const struct parent_map gcc_parent_map_8[] = {
292 	{ P_XO, 0 },
293 	{ P_HDMI_PHY_PLL_CLK, 1 },
294 };
295 
296 static const struct clk_parent_data gcc_parent_data_8[] = {
297 	{ .index = DT_XO, .name = "xo-board" },
298 	{ .index = DT_HDMI_PHY_PLL_CLK, .name = "hdmi_pll" },
299 };
300 
301 static const struct parent_map gcc_parent_map_9[] = {
302 	{ P_XO, 0 },
303 	{ P_GPLL0_OUT_MAIN, 1 },
304 	{ P_DSI0_PHY_PLL_OUT_DSICLK, 2 },
305 	{ P_GPLL6_OUT_AUX, 3 },
306 };
307 
308 static const struct clk_parent_data gcc_parent_data_9[] = {
309 	{ .index = DT_XO, .name = "xo-board" },
310 	{ .hw = &gpll0_out_main.clkr.hw },
311 	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" },
312 	{ .hw = &gpll6_out_aux.hw },
313 };
314 
315 static const struct parent_map gcc_parent_map_10[] = {
316 	{ P_XO, 0 },
317 	{ P_SLEEP_CLK, 1 },
318 };
319 
320 static const struct clk_parent_data gcc_parent_data_10[] = {
321 	{ .index = DT_XO, .name = "xo-board" },
322 	{ .index = DT_SLEEP_CLK, .name = "sleep_clk" },
323 };
324 
325 static const struct parent_map gcc_parent_map_11[] = {
326 	{ P_XO, 0 },
327 	{ P_PCIE_0_PIPE_CLK, 1 },
328 };
329 
330 static const struct clk_parent_data gcc_parent_data_11[] = {
331 	{ .index = DT_XO, .name = "xo-board" },
332 	{ .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
333 };
334 
335 static const struct parent_map gcc_parent_map_12[] = {
336 	{ P_XO, 0 },
337 	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
338 };
339 
340 static const struct clk_parent_data gcc_parent_data_12[] = {
341 	{ .index = DT_XO, .name = "xo-board" },
342 	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" },
343 };
344 
345 static const struct parent_map gcc_parent_map_13[] = {
346 	{ P_XO, 0 },
347 	{ P_GPLL0_OUT_MAIN, 1 },
348 	{ P_GPLL4_OUT_MAIN, 2 },
349 	{ P_GPLL6_OUT_AUX, 3 },
350 };
351 
352 static const struct clk_parent_data gcc_parent_data_13[] = {
353 	{ .index = DT_XO, .name = "xo-board" },
354 	{ .hw = &gpll0_out_main.clkr.hw },
355 	{ .hw = &gpll4_out_main.clkr.hw },
356 	{ .hw = &gpll6_out_aux.hw },
357 };
358 
359 static const struct parent_map gcc_parent_map_14[] = {
360 	{ P_XO, 0 },
361 	{ P_GPLL0_OUT_MAIN, 1 },
362 };
363 
364 static const struct clk_parent_data gcc_parent_data_14[] = {
365 	{ .index = DT_XO, .name = "xo-board" },
366 	{ .hw = &gpll0_out_main.clkr.hw },
367 };
368 
369 static const struct parent_map gcc_parent_map_15[] = {
370 	{ P_XO, 0 },
371 };
372 
373 static const struct clk_parent_data gcc_parent_data_15[] = {
374 	{ .index = DT_XO, .name = "xo-board" },
375 };
376 
377 static const struct parent_map gcc_parent_map_16[] = {
378 	{ P_XO, 0 },
379 	{ P_GPLL0_OUT_MAIN, 1 },
380 };
381 
382 static const struct clk_parent_data gcc_parent_data_16[] = {
383 	{ .index = DT_XO, .name = "xo-board" },
384 	{ .hw = &gpll0_out_main.clkr.hw },
385 };
386 
387 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
388 	F(19200000, P_XO, 1, 0, 0),
389 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
390 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
391 	F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
392 	{ }
393 };
394 
395 static struct clk_rcg2 apss_ahb_clk_src = {
396 	.cmd_rcgr = 0x46000,
397 	.mnd_width = 0,
398 	.hid_width = 5,
399 	.parent_map = gcc_parent_map_0,
400 	.freq_tbl = ftbl_apss_ahb_clk_src,
401 	.clkr.hw.init = &(struct clk_init_data){
402 		.name = "apss_ahb_clk_src",
403 		.parent_data = gcc_parent_data_ao_0,
404 		.num_parents = ARRAY_SIZE(gcc_parent_data_ao_0),
405 		.flags = CLK_IS_CRITICAL,
406 		.ops = &clk_rcg2_ops,
407 	},
408 };
409 
410 static const struct freq_tbl ftbl_blsp1_qup0_i2c_apps_clk_src[] = {
411 	F(19200000, P_XO, 1, 0, 0),
412 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
413 	{ }
414 };
415 
416 static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = {
417 	.cmd_rcgr = 0x602c,
418 	.mnd_width = 0,
419 	.hid_width = 5,
420 	.parent_map = gcc_parent_map_0,
421 	.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
422 	.clkr.hw.init = &(struct clk_init_data){
423 		.name = "blsp1_qup0_i2c_apps_clk_src",
424 		.parent_data = gcc_parent_data_0,
425 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
426 		.ops = &clk_rcg2_ops,
427 	},
428 };
429 
430 static const struct freq_tbl ftbl_blsp1_qup0_spi_apps_clk_src[] = {
431 	F(960000, P_XO, 10, 1, 2),
432 	F(4800000, P_XO, 4, 0, 0),
433 	F(9600000, P_XO, 2, 0, 0),
434 	F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
435 	F(19200000, P_XO, 1, 0, 0),
436 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
437 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
438 	{ }
439 };
440 
441 static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = {
442 	.cmd_rcgr = 0x6034,
443 	.mnd_width = 8,
444 	.hid_width = 5,
445 	.parent_map = gcc_parent_map_0,
446 	.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
447 	.clkr.hw.init = &(struct clk_init_data){
448 		.name = "blsp1_qup0_spi_apps_clk_src",
449 		.parent_data = gcc_parent_data_0,
450 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
451 		.ops = &clk_rcg2_ops,
452 	},
453 };
454 
455 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
456 	.cmd_rcgr = 0x200c,
457 	.mnd_width = 0,
458 	.hid_width = 5,
459 	.parent_map = gcc_parent_map_0,
460 	.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
461 	.clkr.hw.init = &(struct clk_init_data){
462 		.name = "blsp1_qup1_i2c_apps_clk_src",
463 		.parent_data = gcc_parent_data_0,
464 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
465 		.ops = &clk_rcg2_ops,
466 	},
467 };
468 
469 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
470 	F(960000,   P_XO, 10, 1, 2),
471 	F(4800000,  P_XO, 4, 0, 0),
472 	F(9600000,  P_XO, 2, 0, 0),
473 	F(10480000, P_GPLL0_OUT_MAIN, 1, 3, 229),
474 	F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
475 	F(19200000, P_XO, 1, 0, 0),
476 	F(20961000, P_GPLL0_OUT_MAIN, 1, 6, 229),
477 	{ }
478 };
479 
480 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
481 	.cmd_rcgr = 0x2024,
482 	.mnd_width = 8,
483 	.hid_width = 5,
484 	.parent_map = gcc_parent_map_0,
485 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
486 	.clkr.hw.init = &(struct clk_init_data){
487 		.name = "blsp1_qup1_spi_apps_clk_src",
488 		.parent_data = gcc_parent_data_0,
489 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
490 		.ops = &clk_rcg2_ops,
491 	},
492 };
493 
494 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
495 	.cmd_rcgr = 0x3000,
496 	.mnd_width = 0,
497 	.hid_width = 5,
498 	.parent_map = gcc_parent_map_0,
499 	.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
500 	.clkr.hw.init = &(struct clk_init_data){
501 		.name = "blsp1_qup2_i2c_apps_clk_src",
502 		.parent_data = gcc_parent_data_0,
503 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
504 		.ops = &clk_rcg2_ops,
505 	},
506 };
507 
508 static const struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
509 	F(960000,   P_XO, 10, 1, 2),
510 	F(4800000,  P_XO, 4, 0, 0),
511 	F(9600000,  P_XO, 2, 0, 0),
512 	F(15000000, P_GPLL0_OUT_MAIN, 1,  3, 160),
513 	F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
514 	F(19200000, P_XO, 1, 0, 0),
515 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
516 	F(30000000, P_GPLL0_OUT_MAIN, 1,  3, 80),
517 	{ }
518 };
519 
520 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
521 	.cmd_rcgr = 0x3014,
522 	.mnd_width = 8,
523 	.hid_width = 5,
524 	.parent_map = gcc_parent_map_0,
525 	.freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
526 	.clkr.hw.init = &(struct clk_init_data){
527 		.name = "blsp1_qup2_spi_apps_clk_src",
528 		.parent_data = gcc_parent_data_0,
529 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
530 		.ops = &clk_rcg2_ops,
531 	},
532 };
533 
534 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
535 	.cmd_rcgr = 0x4000,
536 	.mnd_width = 0,
537 	.hid_width = 5,
538 	.parent_map = gcc_parent_map_0,
539 	.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
540 	.clkr.hw.init = &(struct clk_init_data){
541 		.name = "blsp1_qup3_i2c_apps_clk_src",
542 		.parent_data = gcc_parent_data_0,
543 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
544 		.ops = &clk_rcg2_ops,
545 	},
546 };
547 
548 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
549 	.cmd_rcgr = 0x4024,
550 	.mnd_width = 8,
551 	.hid_width = 5,
552 	.parent_map = gcc_parent_map_0,
553 	.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
554 	.clkr.hw.init = &(struct clk_init_data){
555 		.name = "blsp1_qup3_spi_apps_clk_src",
556 		.parent_data = gcc_parent_data_0,
557 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
558 		.ops = &clk_rcg2_ops,
559 	},
560 };
561 
562 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
563 	.cmd_rcgr = 0x5000,
564 	.mnd_width = 0,
565 	.hid_width = 5,
566 	.parent_map = gcc_parent_map_0,
567 	.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
568 	.clkr.hw.init = &(struct clk_init_data){
569 		.name = "blsp1_qup4_i2c_apps_clk_src",
570 		.parent_data = gcc_parent_data_0,
571 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
572 		.ops = &clk_rcg2_ops,
573 	},
574 };
575 
576 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
577 	.cmd_rcgr = 0x5024,
578 	.mnd_width = 8,
579 	.hid_width = 5,
580 	.parent_map = gcc_parent_map_0,
581 	.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
582 	.clkr.hw.init = &(struct clk_init_data){
583 		.name = "blsp1_qup4_spi_apps_clk_src",
584 		.parent_data = gcc_parent_data_0,
585 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
586 		.ops = &clk_rcg2_ops,
587 	},
588 };
589 
590 static const struct freq_tbl ftbl_blsp1_uart0_apps_clk_src[] = {
591 	F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),
592 	F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),
593 	F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),
594 	F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
595 	F(19200000, P_XO, 1, 0, 0),
596 	F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),
597 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
598 	F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
599 	F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
600 	F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
601 	F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
602 	F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
603 	F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
604 	F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
605 	F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
606 	F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
607 	{ }
608 };
609 
610 static struct clk_rcg2 blsp1_uart0_apps_clk_src = {
611 	.cmd_rcgr = 0x600c,
612 	.mnd_width = 16,
613 	.hid_width = 5,
614 	.parent_map = gcc_parent_map_0,
615 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
616 	.clkr.hw.init = &(struct clk_init_data){
617 		.name = "blsp1_uart0_apps_clk_src",
618 		.parent_data = gcc_parent_data_0,
619 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
620 		.ops = &clk_rcg2_ops,
621 	},
622 };
623 
624 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
625 	.cmd_rcgr = 0x2044,
626 	.mnd_width = 16,
627 	.hid_width = 5,
628 	.parent_map = gcc_parent_map_0,
629 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
630 	.clkr.hw.init = &(struct clk_init_data){
631 		.name = "blsp1_uart1_apps_clk_src",
632 		.parent_data = gcc_parent_data_0,
633 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
634 		.ops = &clk_rcg2_ops,
635 	},
636 };
637 
638 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
639 	.cmd_rcgr = 0x3034,
640 	.mnd_width = 16,
641 	.hid_width = 5,
642 	.parent_map = gcc_parent_map_0,
643 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
644 	.clkr.hw.init = &(struct clk_init_data){
645 		.name = "blsp1_uart2_apps_clk_src",
646 		.parent_data = gcc_parent_data_0,
647 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
648 		.ops = &clk_rcg2_ops,
649 	},
650 };
651 
652 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
653 	.cmd_rcgr = 0x4014,
654 	.mnd_width = 16,
655 	.hid_width = 5,
656 	.cfg_off = 0x20,
657 	.parent_map = gcc_parent_map_0,
658 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
659 	.clkr.hw.init = &(struct clk_init_data){
660 		.name = "blsp1_uart3_apps_clk_src",
661 		.parent_data = gcc_parent_data_0,
662 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
663 		.ops = &clk_rcg2_ops,
664 	},
665 };
666 
667 static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = {
668 	.cmd_rcgr = 0xc00c,
669 	.mnd_width = 0,
670 	.hid_width = 5,
671 	.parent_map = gcc_parent_map_0,
672 	.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
673 	.clkr.hw.init = &(struct clk_init_data){
674 		.name = "blsp2_qup0_i2c_apps_clk_src",
675 		.parent_data = gcc_parent_data_0,
676 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
677 		.ops = &clk_rcg2_ops,
678 	},
679 };
680 
681 static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = {
682 	.cmd_rcgr = 0xc024,
683 	.mnd_width = 8,
684 	.hid_width = 5,
685 	.parent_map = gcc_parent_map_0,
686 	.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
687 	.clkr.hw.init = &(struct clk_init_data){
688 		.name = "blsp2_qup0_spi_apps_clk_src",
689 		.parent_data = gcc_parent_data_0,
690 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
691 		.ops = &clk_rcg2_ops,
692 	},
693 };
694 
695 static struct clk_rcg2 blsp2_uart0_apps_clk_src = {
696 	.cmd_rcgr = 0xc044,
697 	.mnd_width = 16,
698 	.hid_width = 5,
699 	.parent_map = gcc_parent_map_0,
700 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
701 	.clkr.hw.init = &(struct clk_init_data){
702 		.name = "blsp2_uart0_apps_clk_src",
703 		.parent_data = gcc_parent_data_0,
704 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
705 		.ops = &clk_rcg2_ops,
706 	},
707 };
708 
709 static struct clk_rcg2 byte0_clk_src = {
710 	.cmd_rcgr = 0x4d044,
711 	.mnd_width = 0,
712 	.hid_width = 5,
713 	.parent_map = gcc_parent_map_5,
714 	.clkr.hw.init = &(struct clk_init_data){
715 		.name = "byte0_clk_src",
716 		.parent_data = gcc_parent_data_5,
717 		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
718 		.flags = CLK_SET_RATE_PARENT,
719 		.ops = &clk_byte2_ops,
720 	},
721 };
722 
723 static const struct freq_tbl ftbl_emac_clk_src[] = {
724 	F(5000000,   P_GPLL1_OUT_MAIN, 2, 1, 50),
725 	F(50000000,  P_GPLL1_OUT_MAIN, 10, 0, 0),
726 	F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
727 	F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
728 	{ }
729 };
730 
731 static struct clk_rcg2 emac_clk_src = {
732 	.cmd_rcgr = 0x4e01c,
733 	.mnd_width = 8,
734 	.hid_width = 5,
735 	.parent_map = gcc_parent_map_4,
736 	.freq_tbl = ftbl_emac_clk_src,
737 	.clkr.hw.init = &(struct clk_init_data){
738 		.name = "emac_clk_src",
739 		.parent_data = gcc_parent_data_4,
740 		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
741 		.ops = &clk_rcg2_ops,
742 	},
743 };
744 
745 static const struct freq_tbl ftbl_emac_ptp_clk_src[] = {
746 	F(50000000,  P_GPLL1_OUT_MAIN, 10, 0, 0),
747 	F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
748 	F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
749 	{ }
750 };
751 
752 static struct clk_rcg2 emac_ptp_clk_src = {
753 	.cmd_rcgr = 0x4e014,
754 	.mnd_width = 0,
755 	.hid_width = 5,
756 	.parent_map = gcc_parent_map_4,
757 	.freq_tbl = ftbl_emac_ptp_clk_src,
758 	.clkr.hw.init = &(struct clk_init_data){
759 		.name = "emac_ptp_clk_src",
760 		.parent_data = gcc_parent_data_4,
761 		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
762 		.ops = &clk_rcg2_ops,
763 	},
764 };
765 
766 static const struct freq_tbl ftbl_esc0_clk_src[] = {
767 	F(19200000, P_XO, 1, 0, 0),
768 	{ }
769 };
770 
771 static struct clk_rcg2 esc0_clk_src = {
772 	.cmd_rcgr = 0x4d05c,
773 	.mnd_width = 0,
774 	.hid_width = 5,
775 	.parent_map = gcc_parent_map_6,
776 	.freq_tbl = ftbl_esc0_clk_src,
777 	.clkr.hw.init = &(struct clk_init_data){
778 		.name = "esc0_clk_src",
779 		.parent_data = gcc_parent_data_6,
780 		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
781 		.ops = &clk_rcg2_ops,
782 	},
783 };
784 
785 static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
786 	F(19200000,  P_XO, 1, 0, 0),
787 	F(50000000,  P_GPLL0_OUT_MAIN, 16, 0, 0),
788 	F(80000000,  P_GPLL0_OUT_MAIN, 10, 0, 0),
789 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
790 	F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
791 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
792 	F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
793 	F(240000000, P_GPLL6_OUT_AUX,  4.5, 0, 0),
794 	F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
795 	F(270000000, P_GPLL6_OUT_AUX,  4, 0, 0),
796 	F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
797 	F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
798 	F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0),
799 	F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0),
800 	F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
801 	F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
802 	{ }
803 };
804 
805 static struct clk_rcg2 gfx3d_clk_src = {
806 	.cmd_rcgr = 0x59000,
807 	.mnd_width = 0,
808 	.hid_width = 5,
809 	.parent_map = gcc_parent_map_7,
810 	.freq_tbl = ftbl_gfx3d_clk_src,
811 	.clkr.hw.init = &(struct clk_init_data){
812 		.name = "gfx3d_clk_src",
813 		.parent_data = gcc_parent_data_7,
814 		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
815 		.ops = &clk_rcg2_ops,
816 	},
817 };
818 
819 static const struct freq_tbl ftbl_gp1_clk_src[] = {
820 	F(19200000, P_XO, 1, 0, 0),
821 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
822 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
823 	{ }
824 };
825 
826 static struct clk_rcg2 gp1_clk_src = {
827 	.cmd_rcgr = 0x8004,
828 	.mnd_width = 8,
829 	.hid_width = 5,
830 	.parent_map = gcc_parent_map_2,
831 	.freq_tbl = ftbl_gp1_clk_src,
832 	.clkr.hw.init = &(struct clk_init_data){
833 		.name = "gp1_clk_src",
834 		.parent_data = gcc_parent_data_2,
835 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
836 		.ops = &clk_rcg2_ops,
837 	},
838 };
839 
840 static struct clk_rcg2 gp2_clk_src = {
841 	.cmd_rcgr = 0x9004,
842 	.mnd_width = 8,
843 	.hid_width = 5,
844 	.parent_map = gcc_parent_map_2,
845 	.freq_tbl = ftbl_gp1_clk_src,
846 	.clkr.hw.init = &(struct clk_init_data){
847 		.name = "gp2_clk_src",
848 		.parent_data = gcc_parent_data_2,
849 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
850 		.ops = &clk_rcg2_ops,
851 	},
852 };
853 
854 static struct clk_rcg2 gp3_clk_src = {
855 	.cmd_rcgr = 0xa004,
856 	.mnd_width = 8,
857 	.hid_width = 5,
858 	.parent_map = gcc_parent_map_2,
859 	.freq_tbl = ftbl_gp1_clk_src,
860 	.clkr.hw.init = &(struct clk_init_data){
861 		.name = "gp3_clk_src",
862 		.parent_data = gcc_parent_data_2,
863 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
864 		.ops = &clk_rcg2_ops,
865 	},
866 };
867 
868 static struct clk_rcg2 hdmi_app_clk_src = {
869 	.cmd_rcgr = 0x4d0e4,
870 	.mnd_width = 0,
871 	.hid_width = 5,
872 	.parent_map = gcc_parent_map_1,
873 	.freq_tbl = ftbl_esc0_clk_src,
874 	.clkr.hw.init = &(struct clk_init_data){
875 		.name = "hdmi_app_clk_src",
876 		.parent_data = gcc_parent_data_1,
877 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
878 		.ops = &clk_rcg2_ops,
879 	},
880 };
881 
882 static struct clk_rcg2 hdmi_pclk_clk_src = {
883 	.cmd_rcgr = 0x4d0dc,
884 	.mnd_width = 0,
885 	.hid_width = 5,
886 	.parent_map = gcc_parent_map_8,
887 	.freq_tbl = ftbl_esc0_clk_src,
888 	.clkr.hw.init = &(struct clk_init_data){
889 		.name = "hdmi_pclk_clk_src",
890 		.parent_data = gcc_parent_data_8,
891 		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
892 		.ops = &clk_rcg2_ops,
893 	},
894 };
895 
896 static const struct freq_tbl ftbl_mdp_clk_src[] = {
897 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
898 	F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
899 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
900 	F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0),
901 	F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
902 	F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
903 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
904 	F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
905 	F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
906 	{ }
907 };
908 
909 static struct clk_rcg2 mdp_clk_src = {
910 	.cmd_rcgr = 0x4d014,
911 	.mnd_width = 0,
912 	.hid_width = 5,
913 	.parent_map = gcc_parent_map_9,
914 	.freq_tbl = ftbl_mdp_clk_src,
915 	.clkr.hw.init = &(struct clk_init_data){
916 		.name = "mdp_clk_src",
917 		.parent_data = gcc_parent_data_9,
918 		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
919 		.ops = &clk_rcg2_ops,
920 	},
921 };
922 
923 static const struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
924 	F(1200000, P_XO, 16, 0, 0),
925 	{ }
926 };
927 
928 static struct clk_rcg2 pcie_0_aux_clk_src = {
929 	.cmd_rcgr = 0x3e024,
930 	.mnd_width = 16,
931 	.hid_width = 5,
932 	.parent_map = gcc_parent_map_10,
933 	.freq_tbl = ftbl_pcie_0_aux_clk_src,
934 	.clkr.hw.init = &(struct clk_init_data){
935 		.name = "pcie_0_aux_clk_src",
936 		.parent_data = gcc_parent_data_10,
937 		.num_parents = ARRAY_SIZE(gcc_parent_data_10),
938 		.ops = &clk_rcg2_ops,
939 	},
940 };
941 
942 static const struct freq_tbl ftbl_pcie_0_pipe_clk_src[] = {
943 	F(19200000, P_XO, 1, 0, 0),
944 	F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0),
945 	F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0),
946 	{ }
947 };
948 
949 static struct clk_rcg2 pcie_0_pipe_clk_src = {
950 	.cmd_rcgr = 0x3e01c,
951 	.mnd_width = 0,
952 	.hid_width = 5,
953 	.parent_map = gcc_parent_map_11,
954 	.freq_tbl = ftbl_pcie_0_pipe_clk_src,
955 	.clkr.hw.init = &(struct clk_init_data){
956 		.name = "pcie_0_pipe_clk_src",
957 		.parent_data = gcc_parent_data_11,
958 		.num_parents = ARRAY_SIZE(gcc_parent_data_11),
959 		.ops = &clk_rcg2_ops,
960 	},
961 };
962 
963 static struct clk_rcg2 pclk0_clk_src = {
964 	.cmd_rcgr = 0x4d000,
965 	.mnd_width = 8,
966 	.hid_width = 5,
967 	.parent_map = gcc_parent_map_12,
968 	.clkr.hw.init = &(struct clk_init_data){
969 		.name = "pclk0_clk_src",
970 		.parent_data = gcc_parent_data_12,
971 		.num_parents = ARRAY_SIZE(gcc_parent_data_12),
972 		.flags = CLK_SET_RATE_PARENT,
973 		.ops = &clk_pixel_ops,
974 	},
975 };
976 
977 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
978 	F(19200000, P_XO, 1, 0, 0),
979 	F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
980 	{ }
981 };
982 
983 static struct clk_rcg2 pdm2_clk_src = {
984 	.cmd_rcgr = 0x44010,
985 	.mnd_width = 0,
986 	.hid_width = 5,
987 	.parent_map = gcc_parent_map_0,
988 	.freq_tbl = ftbl_pdm2_clk_src,
989 	.clkr.hw.init = &(struct clk_init_data){
990 		.name = "pdm2_clk_src",
991 		.parent_data = gcc_parent_data_0,
992 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
993 		.ops = &clk_rcg2_ops,
994 	},
995 };
996 
997 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
998 	F(144000, P_XO, 16, 3, 25),
999 	F(400000, P_XO, 12, 1, 4),
1000 	F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1001 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1002 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1003 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1004 	F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1005 	F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
1006 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1007 	F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0),
1008 	{ }
1009 };
1010 
1011 static struct clk_rcg2 sdcc1_apps_clk_src = {
1012 	.cmd_rcgr = 0x42004,
1013 	.mnd_width = 8,
1014 	.hid_width = 5,
1015 	.parent_map = gcc_parent_map_13,
1016 	.freq_tbl = ftbl_sdcc1_apps_clk_src,
1017 	.clkr.hw.init = &(struct clk_init_data){
1018 		.name = "sdcc1_apps_clk_src",
1019 		.parent_data = gcc_parent_data_13,
1020 		.num_parents = ARRAY_SIZE(gcc_parent_data_13),
1021 		.ops = &clk_rcg2_floor_ops,
1022 	},
1023 };
1024 
1025 static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1026 	F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1027 	F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1028 	{ }
1029 };
1030 
1031 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1032 	.cmd_rcgr = 0x5d000,
1033 	.mnd_width = 8,
1034 	.hid_width = 5,
1035 	.parent_map = gcc_parent_map_3,
1036 	.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1037 	.clkr.hw.init = &(struct clk_init_data){
1038 		.name = "sdcc1_ice_core_clk_src",
1039 		.parent_data = gcc_parent_data_3,
1040 		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1041 		.ops = &clk_rcg2_ops,
1042 	},
1043 };
1044 
1045 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1046 	F(144000, P_XO, 16, 3, 25),
1047 	F(400000, P_XO, 12, 1, 4),
1048 	F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1049 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1050 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1051 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1052 	F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1053 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1054 	{ }
1055 };
1056 
1057 static struct clk_rcg2 sdcc2_apps_clk_src = {
1058 	.cmd_rcgr = 0x43004,
1059 	.mnd_width = 8,
1060 	.hid_width = 5,
1061 	.parent_map = gcc_parent_map_14,
1062 	.freq_tbl = ftbl_sdcc2_apps_clk_src,
1063 	.clkr.hw.init = &(struct clk_init_data){
1064 		.name = "sdcc2_apps_clk_src",
1065 		.parent_data = gcc_parent_data_14,
1066 		.num_parents = ARRAY_SIZE(gcc_parent_data_14),
1067 		.ops = &clk_rcg2_floor_ops,
1068 	},
1069 };
1070 
1071 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
1072 	.cmd_rcgr = 0x41048,
1073 	.mnd_width = 0,
1074 	.hid_width = 5,
1075 	.parent_map = gcc_parent_map_1,
1076 	.freq_tbl = ftbl_esc0_clk_src,
1077 	.clkr.hw.init = &(struct clk_init_data){
1078 		.name = "usb20_mock_utmi_clk_src",
1079 		.parent_data = gcc_parent_data_1,
1080 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1081 		.ops = &clk_rcg2_ops,
1082 	},
1083 };
1084 
1085 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1086 	F(19200000, P_XO, 1, 0, 0),
1087 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1088 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1089 	F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1090 	{ }
1091 };
1092 
1093 static struct clk_rcg2 usb30_master_clk_src = {
1094 	.cmd_rcgr = 0x39028,
1095 	.mnd_width = 8,
1096 	.hid_width = 5,
1097 	.parent_map = gcc_parent_map_0,
1098 	.freq_tbl = ftbl_usb30_master_clk_src,
1099 	.clkr.hw.init = &(struct clk_init_data){
1100 		.name = "usb30_master_clk_src",
1101 		.parent_data = gcc_parent_data_0,
1102 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1103 		.ops = &clk_rcg2_ops,
1104 	},
1105 };
1106 
1107 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1108 	.cmd_rcgr = 0x3901c,
1109 	.mnd_width = 0,
1110 	.hid_width = 5,
1111 	.parent_map = gcc_parent_map_1,
1112 	.freq_tbl = ftbl_esc0_clk_src,
1113 	.clkr.hw.init = &(struct clk_init_data){
1114 		.name = "usb30_mock_utmi_clk_src",
1115 		.parent_data = gcc_parent_data_1,
1116 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1117 		.ops = &clk_rcg2_ops,
1118 	},
1119 };
1120 
1121 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1122 	.cmd_rcgr = 0x3903c,
1123 	.mnd_width = 0,
1124 	.hid_width = 5,
1125 	.parent_map = gcc_parent_map_1,
1126 	.freq_tbl = ftbl_pcie_0_aux_clk_src,
1127 	.clkr.hw.init = &(struct clk_init_data){
1128 		.name = "usb3_phy_aux_clk_src",
1129 		.parent_data = gcc_parent_data_1,
1130 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1131 		.ops = &clk_rcg2_ops,
1132 	},
1133 };
1134 
1135 static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1136 	F(19200000, P_XO, 1, 0, 0),
1137 	F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1138 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1139 	F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1140 	F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1141 	{ }
1142 };
1143 
1144 static struct clk_rcg2 usb_hs_system_clk_src = {
1145 	.cmd_rcgr = 0x41010,
1146 	.mnd_width = 0,
1147 	.hid_width = 5,
1148 	.parent_map = gcc_parent_map_3,
1149 	.freq_tbl = ftbl_usb_hs_system_clk_src,
1150 	.clkr.hw.init = &(struct clk_init_data){
1151 		.name = "usb_hs_system_clk_src",
1152 		.parent_data = gcc_parent_data_3,
1153 		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1154 		.ops = &clk_rcg2_ops,
1155 	},
1156 };
1157 
1158 static struct clk_rcg2 vsync_clk_src = {
1159 	.cmd_rcgr = 0x4d02c,
1160 	.mnd_width = 0,
1161 	.hid_width = 5,
1162 	.parent_map = gcc_parent_map_15,
1163 	.freq_tbl = ftbl_esc0_clk_src,
1164 	.clkr.hw.init = &(struct clk_init_data){
1165 		.name = "vsync_clk_src",
1166 		.parent_data = gcc_parent_data_15,
1167 		.num_parents = ARRAY_SIZE(gcc_parent_data_15),
1168 		.ops = &clk_rcg2_ops,
1169 	},
1170 };
1171 
1172 static const struct freq_tbl ftbl_cdsp_bimc_clk_src[] = {
1173 	F(19200000, P_XO, 1, 0, 0),
1174 	F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1175 	F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1176 	F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1177 	{ }
1178 };
1179 
1180 static struct clk_rcg2 cdsp_bimc_clk_src = {
1181 	.cmd_rcgr = 0x5e010,
1182 	.mnd_width = 0,
1183 	.hid_width = 5,
1184 	.parent_map = gcc_parent_map_16,
1185 	.freq_tbl = ftbl_cdsp_bimc_clk_src,
1186 	.clkr.hw.init = &(struct clk_init_data) {
1187 		.name = "cdsp_bimc_clk_src",
1188 		.parent_data = gcc_parent_data_16,
1189 		.num_parents = ARRAY_SIZE(gcc_parent_data_16),
1190 		.ops = &clk_rcg2_ops,
1191 	},
1192 };
1193 
1194 static struct clk_branch gcc_apss_ahb_clk = {
1195 	.halt_reg = 0x4601c,
1196 	.halt_check = BRANCH_HALT_VOTED,
1197 	.clkr = {
1198 		.enable_reg = 0x45004,
1199 		.enable_mask = BIT(14),
1200 		.hw.init = &(struct clk_init_data){
1201 			.name = "gcc_apss_ahb_clk",
1202 			.parent_hws = (const struct clk_hw*[]) {
1203 				&apss_ahb_clk_src.clkr.hw,
1204 			},
1205 			.num_parents = 1,
1206 			.flags = CLK_SET_RATE_PARENT,
1207 			.ops = &clk_branch2_ops,
1208 		},
1209 	},
1210 };
1211 
1212 static struct clk_branch gcc_apss_tcu_clk = {
1213 	.halt_reg = 0x5b004,
1214 	.halt_check = BRANCH_VOTED,
1215 	.clkr = {
1216 		.enable_reg = 0x4500c,
1217 		.enable_mask = BIT(1),
1218 		.hw.init = &(struct clk_init_data){
1219 			.name = "gcc_apss_tcu_clk",
1220 			.ops = &clk_branch2_ops,
1221 		},
1222 	},
1223 };
1224 
1225 static struct clk_branch gcc_bimc_gfx_clk = {
1226 	.halt_reg = 0x59034,
1227 	.halt_check = BRANCH_HALT,
1228 	.clkr = {
1229 		.enable_reg = 0x59034,
1230 		.enable_mask = BIT(0),
1231 		.hw.init = &(struct clk_init_data){
1232 			.name = "gcc_bimc_gfx_clk",
1233 			.ops = &clk_branch2_ops,
1234 			.parent_hws = (const struct clk_hw*[]) {
1235 				&gcc_apss_tcu_clk.clkr.hw,
1236 			},
1237 
1238 		},
1239 	},
1240 };
1241 
1242 static struct clk_branch gcc_bimc_gpu_clk = {
1243 	.halt_reg = 0x59030,
1244 	.halt_check = BRANCH_HALT,
1245 	.clkr = {
1246 		.enable_reg = 0x59030,
1247 		.enable_mask = BIT(0),
1248 		.hw.init = &(struct clk_init_data){
1249 			.name = "gcc_bimc_gpu_clk",
1250 			.ops = &clk_branch2_ops,
1251 		},
1252 	},
1253 };
1254 
1255 static struct clk_branch gcc_bimc_cdsp_clk = {
1256 	.halt_reg = 0x31030,
1257 	.halt_check = BRANCH_HALT,
1258 	.clkr = {
1259 		.enable_reg = 0x31030,
1260 		.enable_mask = BIT(0),
1261 		.hw.init = &(struct clk_init_data) {
1262 			.name = "gcc_bimc_cdsp_clk",
1263 			.parent_hws = (const struct clk_hw*[]) {
1264 				&cdsp_bimc_clk_src.clkr.hw
1265 			},
1266 			.num_parents = 1,
1267 			.flags = CLK_SET_RATE_PARENT,
1268 			.ops = &clk_branch2_ops,
1269 		},
1270 	},
1271 };
1272 
1273 static struct clk_branch gcc_bimc_mdss_clk = {
1274 	.halt_reg = 0x31038,
1275 	.halt_check = BRANCH_HALT,
1276 	.clkr = {
1277 		.enable_reg = 0x31038,
1278 		.enable_mask = BIT(0),
1279 		.hw.init = &(struct clk_init_data){
1280 			.name = "gcc_bimc_mdss_clk",
1281 			.ops = &clk_branch2_ops,
1282 		},
1283 	},
1284 };
1285 
1286 static struct clk_branch gcc_blsp1_ahb_clk = {
1287 	.halt_reg = 0x1008,
1288 	.halt_check = BRANCH_HALT_VOTED,
1289 	.clkr = {
1290 		.enable_reg = 0x45004,
1291 		.enable_mask = BIT(10),
1292 		.hw.init = &(struct clk_init_data){
1293 			.name = "gcc_blsp1_ahb_clk",
1294 			.ops = &clk_branch2_ops,
1295 		},
1296 	},
1297 };
1298 
1299 static struct clk_branch gcc_dcc_clk = {
1300 	.halt_reg = 0x77004,
1301 	.halt_check = BRANCH_HALT,
1302 	.clkr = {
1303 		.enable_reg = 0x77004,
1304 		.enable_mask = BIT(0),
1305 		.hw.init = &(struct clk_init_data){
1306 			.name = "gcc_dcc_clk",
1307 			.ops = &clk_branch2_ops,
1308 		},
1309 	},
1310 };
1311 
1312 static struct clk_branch gcc_dcc_xo_clk = {
1313 	.halt_reg = 0x77008,
1314 	.halt_check = BRANCH_HALT,
1315 	.clkr = {
1316 		.enable_reg = 0x77008,
1317 		.enable_mask = BIT(0),
1318 		.hw.init = &(struct clk_init_data){
1319 			.name = "gcc_dcc_xo_clk",
1320 			.ops = &clk_branch2_ops,
1321 		},
1322 	},
1323 };
1324 
1325 static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = {
1326 	.halt_reg = 0x6028,
1327 	.halt_check = BRANCH_HALT,
1328 	.clkr = {
1329 		.enable_reg = 0x6028,
1330 		.enable_mask = BIT(0),
1331 		.hw.init = &(struct clk_init_data){
1332 			.name = "gcc_blsp1_qup0_i2c_apps_clk",
1333 			.parent_hws = (const struct clk_hw*[]) {
1334 				&blsp1_qup0_i2c_apps_clk_src.clkr.hw,
1335 			},
1336 			.num_parents = 1,
1337 			.flags = CLK_SET_RATE_PARENT,
1338 			.ops = &clk_branch2_ops,
1339 		},
1340 	},
1341 };
1342 
1343 static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = {
1344 	.halt_reg = 0x6024,
1345 	.halt_check = BRANCH_HALT,
1346 	.clkr = {
1347 		.enable_reg = 0x6024,
1348 		.enable_mask = BIT(0),
1349 		.hw.init = &(struct clk_init_data){
1350 			.name = "gcc_blsp1_qup0_spi_apps_clk",
1351 			.parent_hws = (const struct clk_hw*[]) {
1352 				&blsp1_qup0_spi_apps_clk_src.clkr.hw,
1353 			},
1354 			.num_parents = 1,
1355 			.flags = CLK_SET_RATE_PARENT,
1356 			.ops = &clk_branch2_ops,
1357 		},
1358 	},
1359 };
1360 
1361 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1362 	.halt_reg = 0x2008,
1363 	.halt_check = BRANCH_HALT,
1364 	.clkr = {
1365 		.enable_reg = 0x2008,
1366 		.enable_mask = BIT(0),
1367 		.hw.init = &(struct clk_init_data){
1368 			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1369 			.parent_hws = (const struct clk_hw*[]) {
1370 				&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1371 			},
1372 			.num_parents = 1,
1373 			.flags = CLK_SET_RATE_PARENT,
1374 			.ops = &clk_branch2_ops,
1375 		},
1376 	},
1377 };
1378 
1379 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1380 	.halt_reg = 0x2004,
1381 	.halt_check = BRANCH_HALT,
1382 	.clkr = {
1383 		.enable_reg = 0x2004,
1384 		.enable_mask = BIT(0),
1385 		.hw.init = &(struct clk_init_data){
1386 			.name = "gcc_blsp1_qup1_spi_apps_clk",
1387 			.parent_hws = (const struct clk_hw*[]) {
1388 				&blsp1_qup1_spi_apps_clk_src.clkr.hw,
1389 			},
1390 			.num_parents = 1,
1391 			.flags = CLK_SET_RATE_PARENT,
1392 			.ops = &clk_branch2_ops,
1393 		},
1394 	},
1395 };
1396 
1397 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1398 	.halt_reg = 0x3010,
1399 	.halt_check = BRANCH_HALT,
1400 	.clkr = {
1401 		.enable_reg = 0x3010,
1402 		.enable_mask = BIT(0),
1403 		.hw.init = &(struct clk_init_data){
1404 			.name = "gcc_blsp1_qup2_i2c_apps_clk",
1405 			.parent_hws = (const struct clk_hw*[]) {
1406 				&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1407 			},
1408 			.num_parents = 1,
1409 			.flags = CLK_SET_RATE_PARENT,
1410 			.ops = &clk_branch2_ops,
1411 		},
1412 	},
1413 };
1414 
1415 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1416 	.halt_reg = 0x300c,
1417 	.halt_check = BRANCH_HALT,
1418 	.clkr = {
1419 		.enable_reg = 0x300c,
1420 		.enable_mask = BIT(0),
1421 		.hw.init = &(struct clk_init_data){
1422 			.name = "gcc_blsp1_qup2_spi_apps_clk",
1423 			.parent_hws = (const struct clk_hw*[]) {
1424 				&blsp1_qup2_spi_apps_clk_src.clkr.hw,
1425 			},
1426 			.num_parents = 1,
1427 			.flags = CLK_SET_RATE_PARENT,
1428 			.ops = &clk_branch2_ops,
1429 		},
1430 	},
1431 };
1432 
1433 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1434 	.halt_reg = 0x4020,
1435 	.halt_check = BRANCH_HALT,
1436 	.clkr = {
1437 		.enable_reg = 0x4020,
1438 		.enable_mask = BIT(0),
1439 		.hw.init = &(struct clk_init_data){
1440 			.name = "gcc_blsp1_qup3_i2c_apps_clk",
1441 			.parent_hws = (const struct clk_hw*[]) {
1442 				&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1443 			},
1444 			.num_parents = 1,
1445 			.flags = CLK_SET_RATE_PARENT,
1446 			.ops = &clk_branch2_ops,
1447 		},
1448 	},
1449 };
1450 
1451 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1452 	.halt_reg = 0x401c,
1453 	.halt_check = BRANCH_HALT,
1454 	.clkr = {
1455 		.enable_reg = 0x401c,
1456 		.enable_mask = BIT(0),
1457 		.hw.init = &(struct clk_init_data){
1458 			.name = "gcc_blsp1_qup3_spi_apps_clk",
1459 			.parent_hws = (const struct clk_hw*[]) {
1460 				&blsp1_qup3_spi_apps_clk_src.clkr.hw,
1461 			},
1462 			.num_parents = 1,
1463 			.flags = CLK_SET_RATE_PARENT,
1464 			.ops = &clk_branch2_ops,
1465 		},
1466 	},
1467 };
1468 
1469 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1470 	.halt_reg = 0x5020,
1471 	.halt_check = BRANCH_HALT,
1472 	.clkr = {
1473 		.enable_reg = 0x5020,
1474 		.enable_mask = BIT(0),
1475 		.hw.init = &(struct clk_init_data){
1476 			.name = "gcc_blsp1_qup4_i2c_apps_clk",
1477 			.parent_hws = (const struct clk_hw*[]) {
1478 				&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1479 			},
1480 			.num_parents = 1,
1481 			.flags = CLK_SET_RATE_PARENT,
1482 			.ops = &clk_branch2_ops,
1483 		},
1484 	},
1485 };
1486 
1487 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1488 	.halt_reg = 0x501c,
1489 	.halt_check = BRANCH_HALT,
1490 	.clkr = {
1491 		.enable_reg = 0x501c,
1492 		.enable_mask = BIT(0),
1493 		.hw.init = &(struct clk_init_data){
1494 			.name = "gcc_blsp1_qup4_spi_apps_clk",
1495 			.parent_hws = (const struct clk_hw*[]) {
1496 				&blsp1_qup4_spi_apps_clk_src.clkr.hw,
1497 			},
1498 			.num_parents = 1,
1499 			.flags = CLK_SET_RATE_PARENT,
1500 			.ops = &clk_branch2_ops,
1501 		},
1502 	},
1503 };
1504 
1505 static struct clk_branch gcc_blsp1_uart0_apps_clk = {
1506 	.halt_reg = 0x6004,
1507 	.halt_check = BRANCH_HALT,
1508 	.clkr = {
1509 		.enable_reg = 0x6004,
1510 		.enable_mask = BIT(0),
1511 		.hw.init = &(struct clk_init_data){
1512 			.name = "gcc_blsp1_uart0_apps_clk",
1513 			.parent_hws = (const struct clk_hw*[]) {
1514 				&blsp1_uart0_apps_clk_src.clkr.hw,
1515 			},
1516 			.num_parents = 1,
1517 			.flags = CLK_SET_RATE_PARENT,
1518 			.ops = &clk_branch2_ops,
1519 		},
1520 	},
1521 };
1522 
1523 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1524 	.halt_reg = 0x203c,
1525 	.halt_check = BRANCH_HALT,
1526 	.clkr = {
1527 		.enable_reg = 0x203c,
1528 		.enable_mask = BIT(0),
1529 		.hw.init = &(struct clk_init_data){
1530 			.name = "gcc_blsp1_uart1_apps_clk",
1531 			.parent_hws = (const struct clk_hw*[]) {
1532 				&blsp1_uart1_apps_clk_src.clkr.hw,
1533 			},
1534 			.num_parents = 1,
1535 			.flags = CLK_SET_RATE_PARENT,
1536 			.ops = &clk_branch2_ops,
1537 		},
1538 	},
1539 };
1540 
1541 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1542 	.halt_reg = 0x302c,
1543 	.halt_check = BRANCH_HALT,
1544 	.clkr = {
1545 		.enable_reg = 0x302c,
1546 		.enable_mask = BIT(0),
1547 		.hw.init = &(struct clk_init_data){
1548 			.name = "gcc_blsp1_uart2_apps_clk",
1549 			.parent_hws = (const struct clk_hw*[]) {
1550 				&blsp1_uart2_apps_clk_src.clkr.hw,
1551 			},
1552 			.num_parents = 1,
1553 			.flags = CLK_SET_RATE_PARENT,
1554 			.ops = &clk_branch2_ops,
1555 		},
1556 	},
1557 };
1558 
1559 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1560 	.halt_reg = 0x400c,
1561 	.halt_check = BRANCH_HALT,
1562 	.clkr = {
1563 		.enable_reg = 0x400c,
1564 		.enable_mask = BIT(0),
1565 		.hw.init = &(struct clk_init_data){
1566 			.name = "gcc_blsp1_uart3_apps_clk",
1567 			.parent_hws = (const struct clk_hw*[]) {
1568 				&blsp1_uart3_apps_clk_src.clkr.hw,
1569 			},
1570 			.num_parents = 1,
1571 			.flags = CLK_SET_RATE_PARENT,
1572 			.ops = &clk_branch2_ops,
1573 		},
1574 	},
1575 };
1576 
1577 static struct clk_branch gcc_blsp2_ahb_clk = {
1578 	.halt_reg = 0xb008,
1579 	.halt_check = BRANCH_HALT_VOTED,
1580 	.clkr = {
1581 		.enable_reg = 0x45004,
1582 		.enable_mask = BIT(20),
1583 		.hw.init = &(struct clk_init_data){
1584 			.name = "gcc_blsp2_ahb_clk",
1585 			.ops = &clk_branch2_ops,
1586 		},
1587 	},
1588 };
1589 
1590 static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = {
1591 	.halt_reg = 0xc008,
1592 	.halt_check = BRANCH_HALT,
1593 	.clkr = {
1594 		.enable_reg = 0xc008,
1595 		.enable_mask = BIT(0),
1596 		.hw.init = &(struct clk_init_data){
1597 			.name = "gcc_blsp2_qup0_i2c_apps_clk",
1598 			.parent_hws = (const struct clk_hw*[]) {
1599 				&blsp2_qup0_i2c_apps_clk_src.clkr.hw,
1600 			},
1601 			.num_parents = 1,
1602 			.flags = CLK_SET_RATE_PARENT,
1603 			.ops = &clk_branch2_ops,
1604 		},
1605 	},
1606 };
1607 
1608 static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = {
1609 	.halt_reg = 0xc004,
1610 	.halt_check = BRANCH_HALT,
1611 	.clkr = {
1612 		.enable_reg = 0xc004,
1613 		.enable_mask = BIT(0),
1614 		.hw.init = &(struct clk_init_data){
1615 			.name = "gcc_blsp2_qup0_spi_apps_clk",
1616 			.parent_hws = (const struct clk_hw*[]) {
1617 				&blsp2_qup0_spi_apps_clk_src.clkr.hw,
1618 			},
1619 			.num_parents = 1,
1620 			.flags = CLK_SET_RATE_PARENT,
1621 			.ops = &clk_branch2_ops,
1622 		},
1623 	},
1624 };
1625 
1626 static struct clk_branch gcc_blsp2_uart0_apps_clk = {
1627 	.halt_reg = 0xc03c,
1628 	.halt_check = BRANCH_HALT,
1629 	.clkr = {
1630 		.enable_reg = 0xc03c,
1631 		.enable_mask = BIT(0),
1632 		.hw.init = &(struct clk_init_data){
1633 			.name = "gcc_blsp2_uart0_apps_clk",
1634 			.parent_hws = (const struct clk_hw*[]) {
1635 				&blsp2_uart0_apps_clk_src.clkr.hw,
1636 			},
1637 			.num_parents = 1,
1638 			.flags = CLK_SET_RATE_PARENT,
1639 			.ops = &clk_branch2_ops,
1640 		},
1641 	},
1642 };
1643 
1644 static struct clk_branch gcc_boot_rom_ahb_clk = {
1645 	.halt_reg = 0x1300c,
1646 	.halt_check = BRANCH_HALT_VOTED,
1647 	.clkr = {
1648 		.enable_reg = 0x45004,
1649 		.enable_mask = BIT(7),
1650 		.hw.init = &(struct clk_init_data){
1651 			.name = "gcc_boot_rom_ahb_clk",
1652 			.ops = &clk_branch2_ops,
1653 		},
1654 	},
1655 };
1656 
1657 static struct clk_branch gcc_crypto_ahb_clk = {
1658 	.halt_reg = 0x16024,
1659 	.halt_check = BRANCH_VOTED,
1660 	.clkr = {
1661 		.enable_reg = 0x45004,
1662 		.enable_mask = BIT(0),
1663 		.hw.init = &(struct clk_init_data){
1664 			.name = "gcc_crypto_ahb_clk",
1665 			.ops = &clk_branch2_ops,
1666 		},
1667 	},
1668 };
1669 
1670 static struct clk_branch gcc_crypto_axi_clk = {
1671 	.halt_reg = 0x16020,
1672 	.halt_check = BRANCH_VOTED,
1673 	.clkr = {
1674 		.enable_reg = 0x45004,
1675 		.enable_mask = BIT(1),
1676 		.hw.init = &(struct clk_init_data){
1677 			.name = "gcc_crypto_axi_clk",
1678 			.ops = &clk_branch2_ops,
1679 		},
1680 	},
1681 };
1682 
1683 static struct clk_branch gcc_crypto_clk = {
1684 	.halt_reg = 0x1601c,
1685 	.halt_check = BRANCH_VOTED,
1686 	.clkr = {
1687 		.enable_reg = 0x45004,
1688 		.enable_mask = BIT(2),
1689 		.hw.init = &(struct clk_init_data){
1690 			.name = "gcc_crypto_clk",
1691 			.ops = &clk_branch2_ops,
1692 		},
1693 	},
1694 };
1695 
1696 static struct clk_branch gcc_eth_axi_clk = {
1697 	.halt_reg = 0x4e010,
1698 	.halt_check = BRANCH_HALT,
1699 	.clkr = {
1700 		.enable_reg = 0x4e010,
1701 		.enable_mask = BIT(0),
1702 		.hw.init = &(struct clk_init_data){
1703 			.name = "gcc_eth_axi_clk",
1704 			.ops = &clk_branch2_ops,
1705 		},
1706 	},
1707 };
1708 
1709 static struct clk_branch gcc_eth_ptp_clk = {
1710 	.halt_reg = 0x4e004,
1711 	.halt_check = BRANCH_HALT,
1712 	.clkr = {
1713 		.enable_reg = 0x4e004,
1714 		.enable_mask = BIT(0),
1715 		.hw.init = &(struct clk_init_data){
1716 			.name = "gcc_eth_ptp_clk",
1717 			.parent_hws = (const struct clk_hw*[]) {
1718 				&emac_ptp_clk_src.clkr.hw,
1719 			},
1720 			.num_parents = 1,
1721 			.flags = CLK_SET_RATE_PARENT,
1722 			.ops = &clk_branch2_ops,
1723 		},
1724 	},
1725 };
1726 
1727 static struct clk_branch gcc_eth_rgmii_clk = {
1728 	.halt_reg = 0x4e008,
1729 	.halt_check = BRANCH_HALT,
1730 	.clkr = {
1731 		.enable_reg = 0x4e008,
1732 		.enable_mask = BIT(0),
1733 		.hw.init = &(struct clk_init_data){
1734 			.name = "gcc_eth_rgmii_clk",
1735 			.parent_hws = (const struct clk_hw*[]) {
1736 				&emac_clk_src.clkr.hw,
1737 			},
1738 			.num_parents = 1,
1739 			.flags = CLK_SET_RATE_PARENT,
1740 			.ops = &clk_branch2_ops,
1741 		},
1742 	},
1743 };
1744 
1745 static struct clk_branch gcc_eth_slave_ahb_clk = {
1746 	.halt_reg = 0x4e00c,
1747 	.halt_check = BRANCH_HALT,
1748 	.clkr = {
1749 		.enable_reg = 0x4e00c,
1750 		.enable_mask = BIT(0),
1751 		.hw.init = &(struct clk_init_data){
1752 			.name = "gcc_eth_slave_ahb_clk",
1753 			.ops = &clk_branch2_ops,
1754 		},
1755 	},
1756 };
1757 
1758 static struct clk_branch gcc_geni_ir_s_clk = {
1759 	.halt_reg = 0xf008,
1760 	.halt_check = BRANCH_HALT,
1761 	.clkr = {
1762 		.enable_reg = 0xf008,
1763 		.enable_mask = BIT(0),
1764 		.hw.init = &(struct clk_init_data){
1765 			.name = "gcc_geni_ir_s_clk",
1766 			.ops = &clk_branch2_ops,
1767 		},
1768 	},
1769 };
1770 
1771 static struct clk_branch gcc_geni_ir_h_clk = {
1772 	.halt_reg = 0xf004,
1773 	.halt_check = BRANCH_HALT,
1774 	.clkr = {
1775 		.enable_reg = 0xf004,
1776 		.enable_mask = BIT(0),
1777 		.hw.init = &(struct clk_init_data){
1778 			.name = "gcc_geni_ir_h_clk",
1779 			.ops = &clk_branch2_ops,
1780 		},
1781 	},
1782 };
1783 
1784 static struct clk_branch gcc_gfx_tcu_clk = {
1785 	.halt_reg = 0x12020,
1786 	.halt_check = BRANCH_VOTED,
1787 	.clkr = {
1788 		.enable_reg = 0x4500C,
1789 		.enable_mask = BIT(2),
1790 		.hw.init = &(struct clk_init_data){
1791 			.name = "gcc_gfx_tcu_clk",
1792 			.ops = &clk_branch2_ops,
1793 		},
1794 	},
1795 };
1796 
1797 static struct clk_branch gcc_gfx_tbu_clk = {
1798 	.halt_reg = 0x12010,
1799 	.halt_check = BRANCH_VOTED,
1800 	.clkr = {
1801 		.enable_reg = 0x4500C,
1802 		.enable_mask = BIT(3),
1803 		.hw.init = &(struct clk_init_data){
1804 			.name = "gcc_gfx_tbu_clk",
1805 			.ops = &clk_branch2_ops,
1806 		},
1807 	},
1808 };
1809 
1810 static struct clk_branch gcc_cdsp_tbu_clk = {
1811 	.halt_reg = 0x1203c,
1812 	.halt_check = BRANCH_VOTED,
1813 	.clkr = {
1814 		.enable_reg = 0x13020,
1815 		.enable_mask = BIT(9),
1816 		.hw.init = &(struct clk_init_data) {
1817 			.name = "gcc_cdsp_tbu_clk",
1818 			.parent_hws = (const struct clk_hw*[]) {
1819 				&cdsp_bimc_clk_src.clkr.hw
1820 			},
1821 			.num_parents = 1,
1822 			.flags = CLK_SET_RATE_PARENT,
1823 			.ops = &clk_branch2_ops,
1824 		},
1825 	},
1826 };
1827 
1828 static struct clk_branch gcc_gp1_clk = {
1829 	.halt_reg = 0x8000,
1830 	.halt_check = BRANCH_HALT,
1831 	.clkr = {
1832 		.enable_reg = 0x8000,
1833 		.enable_mask = BIT(0),
1834 		.hw.init = &(struct clk_init_data){
1835 			.name = "gcc_gp1_clk",
1836 			.parent_hws = (const struct clk_hw*[]) {
1837 				&gp1_clk_src.clkr.hw,
1838 			},
1839 			.num_parents = 1,
1840 			.flags = CLK_SET_RATE_PARENT,
1841 			.ops = &clk_branch2_ops,
1842 		},
1843 	},
1844 };
1845 
1846 static struct clk_branch gcc_gp2_clk = {
1847 	.halt_reg = 0x9000,
1848 	.halt_check = BRANCH_HALT,
1849 	.clkr = {
1850 		.enable_reg = 0x9000,
1851 		.enable_mask = BIT(0),
1852 		.hw.init = &(struct clk_init_data){
1853 			.name = "gcc_gp2_clk",
1854 			.parent_hws = (const struct clk_hw*[]) {
1855 				&gp2_clk_src.clkr.hw,
1856 			},
1857 			.num_parents = 1,
1858 			.flags = CLK_SET_RATE_PARENT,
1859 			.ops = &clk_branch2_ops,
1860 		},
1861 	},
1862 };
1863 
1864 static struct clk_branch gcc_gp3_clk = {
1865 	.halt_reg = 0xa000,
1866 	.halt_check = BRANCH_HALT,
1867 	.clkr = {
1868 		.enable_reg = 0xa000,
1869 		.enable_mask = BIT(0),
1870 		.hw.init = &(struct clk_init_data){
1871 			.name = "gcc_gp3_clk",
1872 			.parent_hws = (const struct clk_hw*[]) {
1873 				&gp3_clk_src.clkr.hw,
1874 			},
1875 			.num_parents = 1,
1876 			.flags = CLK_SET_RATE_PARENT,
1877 			.ops = &clk_branch2_ops,
1878 		},
1879 	},
1880 };
1881 
1882 static struct clk_branch gcc_gtcu_ahb_clk = {
1883 	.halt_reg = 0x12044,
1884 	.halt_check = BRANCH_VOTED,
1885 	.clkr = {
1886 		.enable_reg = 0x4500c,
1887 		.enable_mask = BIT(13),
1888 		.hw.init = &(struct clk_init_data){
1889 			.name = "gcc_gtcu_ahb_clk",
1890 			.ops = &clk_branch2_ops,
1891 		},
1892 	},
1893 };
1894 
1895 static struct clk_branch gcc_mdp_tbu_clk = {
1896 	.halt_reg = 0x1201c,
1897 	.halt_check = BRANCH_VOTED,
1898 	.clkr = {
1899 		.enable_reg = 0x4500c,
1900 		.enable_mask = BIT(4),
1901 		.hw.init = &(struct clk_init_data){
1902 			.name = "gcc_mdp_tbu_clk",
1903 			.ops = &clk_branch2_ops,
1904 		},
1905 	},
1906 };
1907 
1908 static struct clk_branch gcc_mdss_ahb_clk = {
1909 	.halt_reg = 0x4d07c,
1910 	.halt_check = BRANCH_HALT,
1911 	.clkr = {
1912 		.enable_reg = 0x4d07c,
1913 		.enable_mask = BIT(0),
1914 		.hw.init = &(struct clk_init_data){
1915 			.name = "gcc_mdss_ahb_clk",
1916 			.ops = &clk_branch2_ops,
1917 		},
1918 	},
1919 };
1920 
1921 static struct clk_branch gcc_mdss_axi_clk = {
1922 	.halt_reg = 0x4d080,
1923 	.halt_check = BRANCH_HALT,
1924 	.clkr = {
1925 		.enable_reg = 0x4d080,
1926 		.enable_mask = BIT(0),
1927 		.hw.init = &(struct clk_init_data){
1928 			.name = "gcc_mdss_axi_clk",
1929 			.ops = &clk_branch2_ops,
1930 		},
1931 	},
1932 };
1933 
1934 static struct clk_branch gcc_mdss_byte0_clk = {
1935 	.halt_reg = 0x4d094,
1936 	.halt_check = BRANCH_HALT,
1937 	.clkr = {
1938 		.enable_reg = 0x4d094,
1939 		.enable_mask = BIT(0),
1940 		.hw.init = &(struct clk_init_data){
1941 			.name = "gcc_mdss_byte0_clk",
1942 			.parent_hws = (const struct clk_hw*[]) {
1943 				&byte0_clk_src.clkr.hw,
1944 			},
1945 			.num_parents = 1,
1946 			.flags = CLK_SET_RATE_PARENT,
1947 			.ops = &clk_branch2_ops,
1948 		},
1949 	},
1950 };
1951 
1952 static struct clk_branch gcc_mdss_esc0_clk = {
1953 	.halt_reg = 0x4d098,
1954 	.halt_check = BRANCH_HALT,
1955 	.clkr = {
1956 		.enable_reg = 0x4d098,
1957 		.enable_mask = BIT(0),
1958 		.hw.init = &(struct clk_init_data){
1959 			.name = "gcc_mdss_esc0_clk",
1960 			.parent_hws = (const struct clk_hw*[]) {
1961 				&esc0_clk_src.clkr.hw,
1962 			},
1963 			.num_parents = 1,
1964 			.flags = CLK_SET_RATE_PARENT,
1965 			.ops = &clk_branch2_ops,
1966 		},
1967 	},
1968 };
1969 
1970 static struct clk_branch gcc_mdss_hdmi_app_clk = {
1971 	.halt_reg = 0x4d0d8,
1972 	.halt_check = BRANCH_HALT,
1973 	.clkr = {
1974 		.enable_reg = 0x4d0d8,
1975 		.enable_mask = BIT(0),
1976 		.hw.init = &(struct clk_init_data){
1977 			.name = "gcc_mdss_hdmi_app_clk",
1978 			.parent_hws = (const struct clk_hw*[]) {
1979 				&hdmi_app_clk_src.clkr.hw,
1980 			},
1981 			.num_parents = 1,
1982 			.flags = CLK_SET_RATE_PARENT,
1983 			.ops = &clk_branch2_ops,
1984 		},
1985 	},
1986 };
1987 
1988 static struct clk_branch gcc_mdss_hdmi_pclk_clk = {
1989 	.halt_reg = 0x4d0d4,
1990 	.halt_check = BRANCH_HALT,
1991 	.clkr = {
1992 		.enable_reg = 0x4d0d4,
1993 		.enable_mask = BIT(0),
1994 		.hw.init = &(struct clk_init_data){
1995 			.name = "gcc_mdss_hdmi_pclk_clk",
1996 			.parent_hws = (const struct clk_hw*[]) {
1997 				&hdmi_pclk_clk_src.clkr.hw,
1998 			},
1999 			.num_parents = 1,
2000 			.flags = CLK_SET_RATE_PARENT,
2001 			.ops = &clk_branch2_ops,
2002 		},
2003 	},
2004 };
2005 
2006 static struct clk_branch gcc_mdss_mdp_clk = {
2007 	.halt_reg = 0x4d088,
2008 	.halt_check = BRANCH_HALT,
2009 	.clkr = {
2010 		.enable_reg = 0x4d088,
2011 		.enable_mask = BIT(0),
2012 		.hw.init = &(struct clk_init_data){
2013 			.name = "gcc_mdss_mdp_clk",
2014 			.parent_hws = (const struct clk_hw*[]) {
2015 				&mdp_clk_src.clkr.hw,
2016 			},
2017 			.num_parents = 1,
2018 			.flags = CLK_SET_RATE_PARENT,
2019 			.ops = &clk_branch2_ops,
2020 		},
2021 	},
2022 };
2023 
2024 static struct clk_branch gcc_mdss_pclk0_clk = {
2025 	.halt_reg = 0x4d084,
2026 	.halt_check = BRANCH_HALT,
2027 	.clkr = {
2028 		.enable_reg = 0x4d084,
2029 		.enable_mask = BIT(0),
2030 		.hw.init = &(struct clk_init_data){
2031 			.name = "gcc_mdss_pclk0_clk",
2032 			.parent_hws = (const struct clk_hw*[]) {
2033 				&pclk0_clk_src.clkr.hw,
2034 			},
2035 			.num_parents = 1,
2036 			.flags = CLK_SET_RATE_PARENT,
2037 			.ops = &clk_branch2_ops,
2038 		},
2039 	},
2040 };
2041 
2042 static struct clk_branch gcc_mdss_vsync_clk = {
2043 	.halt_reg = 0x4d090,
2044 	.halt_check = BRANCH_HALT,
2045 	.clkr = {
2046 		.enable_reg = 0x4d090,
2047 		.enable_mask = BIT(0),
2048 		.hw.init = &(struct clk_init_data){
2049 			.name = "gcc_mdss_vsync_clk",
2050 			.parent_hws = (const struct clk_hw*[]) {
2051 				&vsync_clk_src.clkr.hw,
2052 			},
2053 			.num_parents = 1,
2054 			.flags = CLK_SET_RATE_PARENT,
2055 			.ops = &clk_branch2_ops,
2056 		},
2057 	},
2058 };
2059 
2060 static struct clk_branch gcc_oxili_ahb_clk = {
2061 	.halt_reg = 0x59028,
2062 	.halt_check = BRANCH_HALT,
2063 	.clkr = {
2064 		.enable_reg = 0x59028,
2065 		.enable_mask = BIT(0),
2066 		.hw.init = &(struct clk_init_data){
2067 			.name = "gcc_oxili_ahb_clk",
2068 			.ops = &clk_branch2_ops,
2069 		},
2070 	},
2071 };
2072 
2073 static struct clk_branch gcc_oxili_gfx3d_clk = {
2074 	.halt_reg = 0x59020,
2075 	.halt_check = BRANCH_HALT,
2076 	.clkr = {
2077 		.enable_reg = 0x59020,
2078 		.enable_mask = BIT(0),
2079 		.hw.init = &(struct clk_init_data){
2080 			.name = "gcc_oxili_gfx3d_clk",
2081 			.parent_hws = (const struct clk_hw*[]) {
2082 				&gfx3d_clk_src.clkr.hw,
2083 			},
2084 			.num_parents = 1,
2085 			.flags = CLK_SET_RATE_PARENT,
2086 			.ops = &clk_branch2_ops,
2087 		},
2088 	},
2089 };
2090 
2091 static struct clk_branch gcc_pcie_0_aux_clk = {
2092 	.halt_reg = 0x3e014,
2093 	.halt_check = BRANCH_HALT_VOTED,
2094 	.clkr = {
2095 		.enable_reg = 0x45004,
2096 		.enable_mask = BIT(27),
2097 		.hw.init = &(struct clk_init_data){
2098 			.name = "gcc_pcie_0_aux_clk",
2099 			.parent_hws = (const struct clk_hw*[]) {
2100 				&pcie_0_aux_clk_src.clkr.hw,
2101 			},
2102 			.num_parents = 1,
2103 			.flags = CLK_SET_RATE_PARENT,
2104 			.ops = &clk_branch2_ops,
2105 		},
2106 	},
2107 };
2108 
2109 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2110 	.halt_reg = 0x3e008,
2111 	.halt_check = BRANCH_HALT_VOTED,
2112 	.clkr = {
2113 		.enable_reg = 0x45004,
2114 		.enable_mask = BIT(11),
2115 		.hw.init = &(struct clk_init_data){
2116 			.name = "gcc_pcie_0_cfg_ahb_clk",
2117 			.ops = &clk_branch2_ops,
2118 		},
2119 	},
2120 };
2121 
2122 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2123 	.halt_reg = 0x3e018,
2124 	.halt_check = BRANCH_HALT_VOTED,
2125 	.clkr = {
2126 		.enable_reg = 0x45004,
2127 		.enable_mask = BIT(18),
2128 		.hw.init = &(struct clk_init_data){
2129 			.name = "gcc_pcie_0_mstr_axi_clk",
2130 			.ops = &clk_branch2_ops,
2131 		},
2132 	},
2133 };
2134 
2135 static struct clk_branch gcc_pcie_0_pipe_clk = {
2136 	.halt_reg = 0x3e00c,
2137 	.halt_check = BRANCH_HALT_VOTED,
2138 	.clkr = {
2139 		.enable_reg = 0x45004,
2140 		.enable_mask = BIT(28),
2141 		.hw.init = &(struct clk_init_data){
2142 			.name = "gcc_pcie_0_pipe_clk",
2143 			.parent_hws = (const struct clk_hw*[]) {
2144 				&pcie_0_pipe_clk_src.clkr.hw,
2145 			},
2146 			.num_parents = 1,
2147 			.flags = CLK_SET_RATE_PARENT,
2148 			.ops = &clk_branch2_ops,
2149 		},
2150 	},
2151 };
2152 
2153 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2154 	.halt_reg = 0x3e010,
2155 	.halt_check = BRANCH_HALT_VOTED,
2156 	.clkr = {
2157 		.enable_reg = 0x45004,
2158 		.enable_mask = BIT(22),
2159 		.hw.init = &(struct clk_init_data){
2160 			.name = "gcc_pcie_0_slv_axi_clk",
2161 			.ops = &clk_branch2_ops,
2162 		},
2163 	},
2164 };
2165 
2166 static struct clk_branch gcc_pcnoc_usb2_clk = {
2167 	.halt_reg = 0x27008,
2168 	.halt_check = BRANCH_HALT,
2169 	.clkr = {
2170 		.enable_reg = 0x27008,
2171 		.enable_mask = BIT(0),
2172 		.hw.init = &(struct clk_init_data){
2173 			.name = "gcc_pcnoc_usb2_clk",
2174 			.flags = CLK_IS_CRITICAL,
2175 			.ops = &clk_branch2_ops,
2176 		},
2177 	},
2178 };
2179 
2180 static struct clk_branch gcc_pcnoc_usb3_clk = {
2181 	.halt_reg = 0x2700c,
2182 	.halt_check = BRANCH_HALT,
2183 	.clkr = {
2184 		.enable_reg = 0x2700c,
2185 		.enable_mask = BIT(0),
2186 		.hw.init = &(struct clk_init_data){
2187 			.name = "gcc_pcnoc_usb3_clk",
2188 			.flags = CLK_IS_CRITICAL,
2189 			.ops = &clk_branch2_ops,
2190 		},
2191 	},
2192 };
2193 
2194 static struct clk_branch gcc_pdm2_clk = {
2195 	.halt_reg = 0x4400c,
2196 	.halt_check = BRANCH_HALT,
2197 	.clkr = {
2198 		.enable_reg = 0x4400c,
2199 		.enable_mask = BIT(0),
2200 		.hw.init = &(struct clk_init_data){
2201 			.name = "gcc_pdm2_clk",
2202 			.parent_hws = (const struct clk_hw*[]) {
2203 				&pdm2_clk_src.clkr.hw,
2204 			},
2205 			.num_parents = 1,
2206 			.flags = CLK_SET_RATE_PARENT,
2207 			.ops = &clk_branch2_ops,
2208 		},
2209 	},
2210 };
2211 
2212 static struct clk_branch gcc_pdm_ahb_clk = {
2213 	.halt_reg = 0x44004,
2214 	.halt_check = BRANCH_HALT,
2215 	.clkr = {
2216 		.enable_reg = 0x44004,
2217 		.enable_mask = BIT(0),
2218 		.hw.init = &(struct clk_init_data){
2219 			.name = "gcc_pdm_ahb_clk",
2220 			.ops = &clk_branch2_ops,
2221 		},
2222 	},
2223 };
2224 
2225 static struct clk_branch gcc_prng_ahb_clk = {
2226 	.halt_reg = 0x13004,
2227 	.halt_check = BRANCH_HALT_VOTED,
2228 	.clkr = {
2229 		.enable_reg = 0x45004,
2230 		.enable_mask = BIT(8),
2231 		.hw.init = &(struct clk_init_data){
2232 			.name = "gcc_prng_ahb_clk",
2233 			.ops = &clk_branch2_ops,
2234 		},
2235 	},
2236 };
2237 
2238 /* PWM clks do not have XO as parent as src clk is a balance root */
2239 static struct clk_branch gcc_pwm0_xo512_clk = {
2240 	.halt_reg = 0x44018,
2241 	.halt_check = BRANCH_HALT,
2242 	.clkr = {
2243 		.enable_reg = 0x44018,
2244 		.enable_mask = BIT(0),
2245 		.hw.init = &(struct clk_init_data){
2246 			.name = "gcc_pwm0_xo512_clk",
2247 			.ops = &clk_branch2_ops,
2248 		},
2249 	},
2250 };
2251 
2252 static struct clk_branch gcc_pwm1_xo512_clk = {
2253 	.halt_reg = 0x49004,
2254 	.halt_check = BRANCH_HALT,
2255 	.clkr = {
2256 		.enable_reg = 0x49004,
2257 		.enable_mask = BIT(0),
2258 		.hw.init = &(struct clk_init_data){
2259 			.name = "gcc_pwm1_xo512_clk",
2260 			.ops = &clk_branch2_ops,
2261 		},
2262 	},
2263 };
2264 
2265 static struct clk_branch gcc_pwm2_xo512_clk = {
2266 	.halt_reg = 0x4a004,
2267 	.halt_check = BRANCH_HALT,
2268 	.clkr = {
2269 		.enable_reg = 0x4a004,
2270 		.enable_mask = BIT(0),
2271 		.hw.init = &(struct clk_init_data){
2272 			.name = "gcc_pwm2_xo512_clk",
2273 			.ops = &clk_branch2_ops,
2274 		},
2275 	},
2276 };
2277 
2278 static struct clk_branch gcc_qdss_dap_clk = {
2279 	.halt_reg = 0x29084,
2280 	.halt_check = BRANCH_VOTED,
2281 	.clkr = {
2282 		.enable_reg = 0x45004,
2283 		.enable_mask = BIT(21),
2284 		.hw.init = &(struct clk_init_data){
2285 			.name = "gcc_qdss_dap_clk",
2286 			.ops = &clk_branch2_ops,
2287 		},
2288 	},
2289 };
2290 
2291 static struct clk_branch gcc_sdcc1_ahb_clk = {
2292 	.halt_reg = 0x4201c,
2293 	.halt_check = BRANCH_HALT,
2294 	.clkr = {
2295 		.enable_reg = 0x4201c,
2296 		.enable_mask = BIT(0),
2297 		.hw.init = &(struct clk_init_data){
2298 			.name = "gcc_sdcc1_ahb_clk",
2299 			.ops = &clk_branch2_ops,
2300 		},
2301 	},
2302 };
2303 
2304 static struct clk_branch gcc_sdcc1_apps_clk = {
2305 	.halt_reg = 0x42018,
2306 	.halt_check = BRANCH_HALT,
2307 	.clkr = {
2308 		.enable_reg = 0x42018,
2309 		.enable_mask = BIT(0),
2310 		.hw.init = &(struct clk_init_data){
2311 			.name = "gcc_sdcc1_apps_clk",
2312 			.parent_hws = (const struct clk_hw*[]) {
2313 				&sdcc1_apps_clk_src.clkr.hw,
2314 			},
2315 			.num_parents = 1,
2316 			.flags = CLK_SET_RATE_PARENT,
2317 			.ops = &clk_branch2_ops,
2318 		},
2319 	},
2320 };
2321 
2322 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2323 	.halt_reg = 0x5d014,
2324 	.halt_check = BRANCH_HALT,
2325 	.clkr = {
2326 		.enable_reg = 0x5d014,
2327 		.enable_mask = BIT(0),
2328 		.hw.init = &(struct clk_init_data){
2329 			.name = "gcc_sdcc1_ice_core_clk",
2330 			.parent_hws = (const struct clk_hw*[]) {
2331 				&sdcc1_ice_core_clk_src.clkr.hw,
2332 			},
2333 			.num_parents = 1,
2334 			.flags = CLK_SET_RATE_PARENT,
2335 			.ops = &clk_branch2_ops,
2336 		},
2337 	},
2338 };
2339 
2340 static struct clk_branch gcc_cdsp_cfg_ahb_clk = {
2341 	.halt_reg = 0x5e004,
2342 	.halt_check = BRANCH_HALT,
2343 	.clkr = {
2344 		.enable_reg = 0x5e004,
2345 		.enable_mask = BIT(0),
2346 		.hw.init = &(struct clk_init_data) {
2347 			.name = "gcc_cdsp_cfg_ahb_cbcr",
2348 			.ops = &clk_branch2_ops,
2349 		},
2350 	},
2351 };
2352 
2353 static struct clk_branch gcc_sdcc2_ahb_clk = {
2354 	.halt_reg = 0x4301c,
2355 	.halt_check = BRANCH_HALT,
2356 	.clkr = {
2357 		.enable_reg = 0x4301c,
2358 		.enable_mask = BIT(0),
2359 		.hw.init = &(struct clk_init_data){
2360 			.name = "gcc_sdcc2_ahb_clk",
2361 			.ops = &clk_branch2_ops,
2362 		},
2363 	},
2364 };
2365 
2366 static struct clk_branch gcc_sdcc2_apps_clk = {
2367 	.halt_reg = 0x43018,
2368 	.halt_check = BRANCH_HALT,
2369 	.clkr = {
2370 		.enable_reg = 0x43018,
2371 		.enable_mask = BIT(0),
2372 		.hw.init = &(struct clk_init_data){
2373 			.name = "gcc_sdcc2_apps_clk",
2374 			.parent_hws = (const struct clk_hw*[]) {
2375 				&sdcc2_apps_clk_src.clkr.hw,
2376 			},
2377 			.num_parents = 1,
2378 			.flags = CLK_SET_RATE_PARENT,
2379 			.ops = &clk_branch2_ops,
2380 		},
2381 	},
2382 };
2383 
2384 static struct clk_branch gcc_smmu_cfg_clk = {
2385 	.halt_reg = 0x12038,
2386 	.halt_check = BRANCH_VOTED,
2387 	.clkr = {
2388 		.enable_reg = 0x3600C,
2389 		.enable_mask = BIT(12),
2390 		.hw.init = &(struct clk_init_data){
2391 			.name = "gcc_smmu_cfg_clk",
2392 			.ops = &clk_branch2_ops,
2393 		},
2394 	},
2395 };
2396 
2397 static struct clk_branch gcc_sys_noc_usb3_clk = {
2398 	.halt_reg = 0x26014,
2399 	.halt_check = BRANCH_HALT,
2400 	.clkr = {
2401 		.enable_reg = 0x26014,
2402 		.enable_mask = BIT(0),
2403 		.hw.init = &(struct clk_init_data){
2404 			.name = "gcc_sys_noc_usb3_clk",
2405 			.parent_hws = (const struct clk_hw*[]) {
2406 				&usb30_master_clk_src.clkr.hw,
2407 			},
2408 			.num_parents = 1,
2409 			.ops = &clk_branch2_ops,
2410 		},
2411 	},
2412 };
2413 
2414 static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
2415 	.halt_reg = 0x4100C,
2416 	.halt_check = BRANCH_HALT,
2417 	.clkr = {
2418 		.enable_reg = 0x4100C,
2419 		.enable_mask = BIT(0),
2420 		.hw.init = &(struct clk_init_data){
2421 			.name = "gcc_usb_hs_inactivity_timers_clk",
2422 			.ops = &clk_branch2_ops,
2423 		},
2424 	},
2425 };
2426 
2427 static struct clk_branch gcc_usb20_mock_utmi_clk = {
2428 	.halt_reg = 0x41044,
2429 	.halt_check = BRANCH_HALT,
2430 	.clkr = {
2431 		.enable_reg = 0x41044,
2432 		.enable_mask = BIT(0),
2433 		.hw.init = &(struct clk_init_data){
2434 			.name = "gcc_usb20_mock_utmi_clk",
2435 			.parent_hws = (const struct clk_hw*[]) {
2436 				&usb20_mock_utmi_clk_src.clkr.hw,
2437 			},
2438 			.num_parents = 1,
2439 			.flags = CLK_SET_RATE_PARENT,
2440 			.ops = &clk_branch2_ops,
2441 		},
2442 	},
2443 };
2444 
2445 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2446 	.halt_reg = 0x4102c,
2447 	.halt_check = BRANCH_HALT,
2448 	.clkr = {
2449 		.enable_reg = 0x4102c,
2450 		.enable_mask = BIT(0),
2451 		.hw.init = &(struct clk_init_data){
2452 			.name = "gcc_usb2a_phy_sleep_clk",
2453 			.ops = &clk_branch2_ops,
2454 		},
2455 	},
2456 };
2457 
2458 static struct clk_branch gcc_usb30_master_clk = {
2459 	.halt_reg = 0x3900c,
2460 	.halt_check = BRANCH_HALT,
2461 	.clkr = {
2462 		.enable_reg = 0x3900c,
2463 		.enable_mask = BIT(0),
2464 		.hw.init = &(struct clk_init_data){
2465 			.name = "gcc_usb30_master_clk",
2466 			.parent_hws = (const struct clk_hw*[]) {
2467 				&usb30_master_clk_src.clkr.hw,
2468 			},
2469 			.num_parents = 1,
2470 			.flags = CLK_SET_RATE_PARENT,
2471 			.ops = &clk_branch2_ops,
2472 		},
2473 	},
2474 };
2475 
2476 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2477 	.halt_reg = 0x39014,
2478 	.halt_check = BRANCH_HALT,
2479 	.clkr = {
2480 		.enable_reg = 0x39014,
2481 		.enable_mask = BIT(0),
2482 		.hw.init = &(struct clk_init_data){
2483 			.name = "gcc_usb30_mock_utmi_clk",
2484 			.parent_hws = (const struct clk_hw*[]) {
2485 				&usb30_mock_utmi_clk_src.clkr.hw,
2486 			},
2487 			.num_parents = 1,
2488 			.flags = CLK_SET_RATE_PARENT,
2489 			.ops = &clk_branch2_ops,
2490 		},
2491 	},
2492 };
2493 
2494 static struct clk_branch gcc_usb30_sleep_clk = {
2495 	.halt_reg = 0x39010,
2496 	.halt_check = BRANCH_HALT,
2497 	.clkr = {
2498 		.enable_reg = 0x39010,
2499 		.enable_mask = BIT(0),
2500 		.hw.init = &(struct clk_init_data){
2501 			.name = "gcc_usb30_sleep_clk",
2502 			.ops = &clk_branch2_ops,
2503 		},
2504 	},
2505 };
2506 
2507 static struct clk_branch gcc_usb3_phy_aux_clk = {
2508 	.halt_reg = 0x39044,
2509 	.halt_check = BRANCH_HALT,
2510 	.clkr = {
2511 		.enable_reg = 0x39044,
2512 		.enable_mask = BIT(0),
2513 		.hw.init = &(struct clk_init_data){
2514 			.name = "gcc_usb3_phy_aux_clk",
2515 			.parent_hws = (const struct clk_hw*[]) {
2516 				&usb3_phy_aux_clk_src.clkr.hw,
2517 			},
2518 			.num_parents = 1,
2519 			.flags = CLK_SET_RATE_PARENT,
2520 			.ops = &clk_branch2_ops,
2521 		},
2522 	},
2523 };
2524 
2525 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2526 	.halt_check = BRANCH_HALT_SKIP,
2527 	.clkr = {
2528 		.enable_reg = 0x39018,
2529 		.enable_mask = BIT(0),
2530 		.hw.init = &(struct clk_init_data){
2531 			.name = "gcc_usb3_phy_pipe_clk",
2532 			.ops = &clk_branch2_ops,
2533 		},
2534 	},
2535 };
2536 
2537 static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
2538 	.halt_reg = 0x41030,
2539 	.halt_check = BRANCH_HALT,
2540 	.clkr = {
2541 		.enable_reg = 0x41030,
2542 		.enable_mask = BIT(0),
2543 		.hw.init = &(struct clk_init_data){
2544 			.name = "gcc_usb_hs_phy_cfg_ahb_clk",
2545 			.ops = &clk_branch2_ops,
2546 		},
2547 	},
2548 };
2549 
2550 static struct clk_branch gcc_usb_hs_system_clk = {
2551 	.halt_reg = 0x41004,
2552 	.halt_check = BRANCH_HALT,
2553 	.clkr = {
2554 		.enable_reg = 0x41004,
2555 		.enable_mask = BIT(0),
2556 		.hw.init = &(struct clk_init_data){
2557 			.name = "gcc_usb_hs_system_clk",
2558 			.parent_hws = (const struct clk_hw*[]) {
2559 				&usb_hs_system_clk_src.clkr.hw,
2560 			},
2561 			.num_parents = 1,
2562 			.flags = CLK_SET_RATE_PARENT,
2563 			.ops = &clk_branch2_ops,
2564 		},
2565 	},
2566 };
2567 
2568 static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
2569 	.halt_reg = 0x1e004,
2570 	.halt_check = BRANCH_HALT,
2571 	.clkr = {
2572 		.enable_reg = 0x1e004,
2573 		.enable_mask = BIT(0),
2574 		.hw.init = &(struct clk_init_data){
2575 			.name = "gcc_wdsp_q6ss_ahbs_clk",
2576 			.ops = &clk_branch2_ops,
2577 		},
2578 	},
2579 };
2580 
2581 static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
2582 	.halt_reg = 0x1e008,
2583 	.halt_check = BRANCH_HALT,
2584 	.clkr = {
2585 		.enable_reg = 0x1e008,
2586 		.enable_mask = BIT(0),
2587 		.hw.init = &(struct clk_init_data){
2588 			.name = "gcc_wdsp_q6ss_axim_clk",
2589 			.ops = &clk_branch2_ops,
2590 		},
2591 	},
2592 };
2593 
2594 static struct gdsc mdss_gdsc = {
2595 	.gdscr = 0x4d078,
2596 	.pd = {
2597 		.name = "mdss",
2598 	},
2599 	.pwrsts = PWRSTS_OFF_ON,
2600 };
2601 
2602 static struct gdsc oxili_gdsc = {
2603 	.gdscr = 0x5901c,
2604 	.pd = {
2605 		.name = "oxili",
2606 	},
2607 	.pwrsts = PWRSTS_OFF_ON,
2608 };
2609 
2610 static struct clk_hw *gcc_qcs404_hws[] = {
2611 	&cxo.hw,
2612 };
2613 
2614 static struct clk_regmap *gcc_qcs404_clocks[] = {
2615 	[GCC_APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
2616 	[GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC] = &blsp1_qup0_i2c_apps_clk_src.clkr,
2617 	[GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC] = &blsp1_qup0_spi_apps_clk_src.clkr,
2618 	[GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2619 	[GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2620 	[GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2621 	[GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2622 	[GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2623 	[GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2624 	[GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2625 	[GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2626 	[GCC_BLSP1_UART0_APPS_CLK_SRC] = &blsp1_uart0_apps_clk_src.clkr,
2627 	[GCC_BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2628 	[GCC_BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2629 	[GCC_BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2630 	[GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC] = &blsp2_qup0_i2c_apps_clk_src.clkr,
2631 	[GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC] = &blsp2_qup0_spi_apps_clk_src.clkr,
2632 	[GCC_BLSP2_UART0_APPS_CLK_SRC] = &blsp2_uart0_apps_clk_src.clkr,
2633 	[GCC_BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2634 	[GCC_EMAC_CLK_SRC] = &emac_clk_src.clkr,
2635 	[GCC_EMAC_PTP_CLK_SRC] = &emac_ptp_clk_src.clkr,
2636 	[GCC_ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2637 	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
2638 	[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2639 	[GCC_BIMC_CDSP_CLK] = &gcc_bimc_cdsp_clk.clkr,
2640 	[GCC_BIMC_MDSS_CLK] = &gcc_bimc_mdss_clk.clkr,
2641 	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2642 	[GCC_BLSP1_QUP0_I2C_APPS_CLK] = &gcc_blsp1_qup0_i2c_apps_clk.clkr,
2643 	[GCC_BLSP1_QUP0_SPI_APPS_CLK] = &gcc_blsp1_qup0_spi_apps_clk.clkr,
2644 	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2645 	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2646 	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2647 	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2648 	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2649 	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2650 	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2651 	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2652 	[GCC_BLSP1_UART0_APPS_CLK] = &gcc_blsp1_uart0_apps_clk.clkr,
2653 	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2654 	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2655 	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2656 	[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2657 	[GCC_BLSP2_QUP0_I2C_APPS_CLK] = &gcc_blsp2_qup0_i2c_apps_clk.clkr,
2658 	[GCC_BLSP2_QUP0_SPI_APPS_CLK] = &gcc_blsp2_qup0_spi_apps_clk.clkr,
2659 	[GCC_BLSP2_UART0_APPS_CLK] = &gcc_blsp2_uart0_apps_clk.clkr,
2660 	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2661 	[GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr,
2662 	[GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr,
2663 	[GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
2664 	[GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
2665 	[GCC_GENI_IR_S_CLK] = &gcc_geni_ir_s_clk.clkr,
2666 	[GCC_GENI_IR_H_CLK] = &gcc_geni_ir_h_clk.clkr,
2667 	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2668 	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2669 	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2670 	[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
2671 	[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
2672 	[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
2673 	[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
2674 	[GCC_MDSS_HDMI_APP_CLK] = &gcc_mdss_hdmi_app_clk.clkr,
2675 	[GCC_MDSS_HDMI_PCLK_CLK] = &gcc_mdss_hdmi_pclk_clk.clkr,
2676 	[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
2677 	[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
2678 	[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
2679 	[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
2680 	[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
2681 	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2682 	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2683 	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2684 	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2685 	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2686 	[GCC_PCNOC_USB2_CLK] = &gcc_pcnoc_usb2_clk.clkr,
2687 	[GCC_PCNOC_USB3_CLK] = &gcc_pcnoc_usb3_clk.clkr,
2688 	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2689 	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2690 	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2691 	[GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
2692 	[GCC_PWM1_XO512_CLK] = &gcc_pwm1_xo512_clk.clkr,
2693 	[GCC_PWM2_XO512_CLK] = &gcc_pwm2_xo512_clk.clkr,
2694 	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2695 	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2696 	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2697 	[GCC_CDSP_CFG_AHB_CLK] = &gcc_cdsp_cfg_ahb_clk.clkr,
2698 	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2699 	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2700 	[GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr,
2701 	[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
2702 	[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2703 	[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2704 	[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2705 	[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2706 	[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2707 	[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2708 	[GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
2709 	[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2710 	[GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2711 	[GCC_GP1_CLK_SRC] = &gp1_clk_src.clkr,
2712 	[GCC_GP2_CLK_SRC] = &gp2_clk_src.clkr,
2713 	[GCC_GP3_CLK_SRC] = &gp3_clk_src.clkr,
2714 	[GCC_GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2715 	[GCC_GPLL0_AO_OUT_MAIN] = &gpll0_ao_out_main.clkr,
2716 	[GCC_GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
2717 	[GCC_GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2718 	[GCC_GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2719 	[GCC_GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2720 	[GCC_GPLL6] = &gpll6.clkr,
2721 	[GCC_GPLL6_OUT_AUX] = &gpll6_out_aux,
2722 	[GCC_HDMI_APP_CLK_SRC] = &hdmi_app_clk_src.clkr,
2723 	[GCC_HDMI_PCLK_CLK_SRC] = &hdmi_pclk_clk_src.clkr,
2724 	[GCC_MDP_CLK_SRC] = &mdp_clk_src.clkr,
2725 	[GCC_PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2726 	[GCC_PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2727 	[GCC_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2728 	[GCC_PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2729 	[GCC_SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2730 	[GCC_SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
2731 	[GCC_SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2732 	[GCC_USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
2733 	[GCC_USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2734 	[GCC_USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2735 	[GCC_USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2736 	[GCC_USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2737 	[GCC_VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2738 	[GCC_CDSP_BIMC_CLK_SRC] = &cdsp_bimc_clk_src.clkr,
2739 	[GCC_USB_HS_INACTIVITY_TIMERS_CLK] =
2740 			&gcc_usb_hs_inactivity_timers_clk.clkr,
2741 	[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
2742 	[GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
2743 	[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
2744 	[GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
2745 	[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
2746 	[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
2747 	[GCC_CDSP_TBU_CLK] = &gcc_cdsp_tbu_clk.clkr,
2748 	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
2749 	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
2750 	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
2751 	[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
2752 	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
2753 	[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
2754 	[GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
2755 	[GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
2756 	[GCC_WCSS_Q6_AXIM_CLK] =  &gcc_wdsp_q6ss_axim_clk.clkr,
2757 
2758 };
2759 
2760 static struct gdsc *gcc_qcs404_gdscs[] = {
2761 	[MDSS_GDSC] = &mdss_gdsc,
2762 	[OXILI_GDSC] = &oxili_gdsc,
2763 };
2764 
2765 static const struct qcom_reset_map gcc_qcs404_resets[] = {
2766 	[GCC_GENI_IR_BCR] = { 0x0F000 },
2767 	[GCC_CDSP_RESTART] = { 0x18000 },
2768 	[GCC_USB_HS_BCR] = { 0x41000 },
2769 	[GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
2770 	[GCC_QUSB2_PHY_BCR] = { 0x4103c },
2771 	[GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
2772 	[GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
2773 	[GCC_USB3_PHY_BCR] = { 0x39004 },
2774 	[GCC_USB_30_BCR] = { 0x39000 },
2775 	[GCC_USB3PHY_PHY_BCR] = { 0x39008 },
2776 	[GCC_PCIE_0_BCR] = { 0x3e000 },
2777 	[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
2778 	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
2779 	[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
2780 	[GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
2781 	[GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
2782 	[GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
2783 	[GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
2784 	[GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
2785 	[GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
2786 	[GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
2787 	[GCC_EMAC_BCR] = { 0x4e000 },
2788 	[GCC_WDSP_RESTART] = {0x19000},
2789 };
2790 
2791 static const struct regmap_config gcc_qcs404_regmap_config = {
2792 	.reg_bits	= 32,
2793 	.reg_stride	= 4,
2794 	.val_bits	= 32,
2795 	.max_register	= 0x7f000,
2796 	.fast_io	= true,
2797 };
2798 
2799 static const struct qcom_cc_desc gcc_qcs404_desc = {
2800 	.config = &gcc_qcs404_regmap_config,
2801 	.clks = gcc_qcs404_clocks,
2802 	.num_clks = ARRAY_SIZE(gcc_qcs404_clocks),
2803 	.resets = gcc_qcs404_resets,
2804 	.num_resets = ARRAY_SIZE(gcc_qcs404_resets),
2805 	.clk_hws = gcc_qcs404_hws,
2806 	.num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws),
2807 	.gdscs = gcc_qcs404_gdscs,
2808 	.num_gdscs = ARRAY_SIZE(gcc_qcs404_gdscs),
2809 };
2810 
2811 static const struct of_device_id gcc_qcs404_match_table[] = {
2812 	{ .compatible = "qcom,gcc-qcs404" },
2813 	{ }
2814 };
2815 MODULE_DEVICE_TABLE(of, gcc_qcs404_match_table);
2816 
gcc_qcs404_probe(struct platform_device * pdev)2817 static int gcc_qcs404_probe(struct platform_device *pdev)
2818 {
2819 	struct regmap *regmap;
2820 
2821 	regmap = qcom_cc_map(pdev, &gcc_qcs404_desc);
2822 	if (IS_ERR(regmap))
2823 		return PTR_ERR(regmap);
2824 
2825 	clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
2826 
2827 	return qcom_cc_really_probe(&pdev->dev, &gcc_qcs404_desc, regmap);
2828 }
2829 
2830 static struct platform_driver gcc_qcs404_driver = {
2831 	.probe = gcc_qcs404_probe,
2832 	.driver = {
2833 		.name = "gcc-qcs404",
2834 		.of_match_table = gcc_qcs404_match_table,
2835 	},
2836 };
2837 
gcc_qcs404_init(void)2838 static int __init gcc_qcs404_init(void)
2839 {
2840 	return platform_driver_register(&gcc_qcs404_driver);
2841 }
2842 core_initcall(gcc_qcs404_init);
2843 
gcc_qcs404_exit(void)2844 static void __exit gcc_qcs404_exit(void)
2845 {
2846 	platform_driver_unregister(&gcc_qcs404_driver);
2847 }
2848 module_exit(gcc_qcs404_exit);
2849 
2850 MODULE_DESCRIPTION("Qualcomm GCC QCS404 Driver");
2851 MODULE_LICENSE("GPL v2");
2852