xref: /linux/drivers/clk/qcom/gcc-qcs404.c (revision 9f3a2ba62c7226a6604b8aaeb92b5ff906fa4e6b)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/platform_device.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/clk-provider.h>
11 #include <linux/regmap.h>
12 #include <linux/reset-controller.h>
13 
14 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
15 
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-pll.h"
19 #include "clk-rcg.h"
20 #include "clk-regmap.h"
21 #include "common.h"
22 #include "gdsc.h"
23 #include "reset.h"
24 
25 enum {
26 	DT_XO,
27 	DT_SLEEP_CLK,
28 	DT_PCIE_0_PIPE_CLK,
29 	DT_DSI0_PHY_PLL_OUT_DSICLK,
30 	DT_DSI0_PHY_PLL_OUT_BYTECLK,
31 	DT_HDMI_PHY_PLL_CLK,
32 };
33 
34 enum {
35 	P_DSI0_PHY_PLL_OUT_BYTECLK,
36 	P_DSI0_PHY_PLL_OUT_DSICLK,
37 	P_GPLL0_OUT_MAIN,
38 	P_GPLL1_OUT_MAIN,
39 	P_GPLL3_OUT_MAIN,
40 	P_GPLL4_OUT_MAIN,
41 	P_GPLL6_OUT_AUX,
42 	P_HDMI_PHY_PLL_CLK,
43 	P_PCIE_0_PIPE_CLK,
44 	P_SLEEP_CLK,
45 	P_XO,
46 };
47 
48 static const struct parent_map gcc_parent_map_1[] = {
49 	{ P_XO, 0 },
50 };
51 
52 static const struct clk_parent_data gcc_parent_data_1[] = {
53 	{ .index = DT_XO, .name = "xo-board" },
54 };
55 
56 static struct clk_fixed_factor cxo = {
57 	.mult = 1,
58 	.div = 1,
59 	.hw.init = &(struct clk_init_data){
60 		.name = "cxo",
61 		.parent_data = gcc_parent_data_1,
62 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
63 		.ops = &clk_fixed_factor_ops,
64 	},
65 };
66 
67 static struct clk_alpha_pll gpll0_sleep_clk_src = {
68 	.offset = 0x21000,
69 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
70 	.clkr = {
71 		.enable_reg = 0x45008,
72 		.enable_mask = BIT(23),
73 		.enable_is_inverted = true,
74 		.hw.init = &(struct clk_init_data){
75 			.name = "gpll0_sleep_clk_src",
76 			.parent_data = gcc_parent_data_1,
77 			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
78 			.ops = &clk_alpha_pll_ops,
79 		},
80 	},
81 };
82 
83 static struct clk_alpha_pll gpll0_out_main = {
84 	.offset = 0x21000,
85 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
86 	.flags = SUPPORTS_FSM_MODE,
87 	.clkr = {
88 		.enable_reg = 0x45000,
89 		.enable_mask = BIT(0),
90 		.hw.init = &(struct clk_init_data){
91 			.name = "gpll0_out_main",
92 			.parent_data = gcc_parent_data_1,
93 			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
94 			.ops = &clk_alpha_pll_ops,
95 		},
96 	},
97 };
98 
99 static struct clk_alpha_pll gpll0_ao_out_main = {
100 	.offset = 0x21000,
101 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
102 	.flags = SUPPORTS_FSM_MODE,
103 	.clkr = {
104 		.enable_reg = 0x45000,
105 		.enable_mask = BIT(0),
106 		.hw.init = &(struct clk_init_data){
107 			.name = "gpll0_ao_out_main",
108 			.parent_data = gcc_parent_data_1,
109 			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
110 			.flags = CLK_IS_CRITICAL,
111 			.ops = &clk_alpha_pll_fixed_ops,
112 		},
113 	},
114 };
115 
116 static struct clk_alpha_pll gpll1_out_main = {
117 	.offset = 0x20000,
118 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
119 	.clkr = {
120 		.enable_reg = 0x45000,
121 		.enable_mask = BIT(1),
122 		.hw.init = &(struct clk_init_data){
123 			.name = "gpll1_out_main",
124 			.parent_data = gcc_parent_data_1,
125 			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
126 			.ops = &clk_alpha_pll_ops,
127 		},
128 	},
129 };
130 
131 /* 930MHz configuration */
132 static const struct alpha_pll_config gpll3_config = {
133 	.l = 48,
134 	.alpha_hi = 0x70,
135 	.alpha = 0x0,
136 	.alpha_en_mask = BIT(24),
137 	.post_div_mask = 0xf << 8,
138 	.post_div_val = 0x1 << 8,
139 	.vco_mask = 0x3 << 20,
140 	.main_output_mask = 0x1,
141 	.config_ctl_val = 0x4001055b,
142 };
143 
144 static const struct pll_vco gpll3_vco[] = {
145 	{ 700000000, 1400000000, 0 },
146 };
147 
148 static struct clk_alpha_pll gpll3_out_main = {
149 	.offset = 0x22000,
150 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
151 	.vco_table = gpll3_vco,
152 	.num_vco = ARRAY_SIZE(gpll3_vco),
153 	.clkr = {
154 		.hw.init = &(struct clk_init_data){
155 			.name = "gpll3_out_main",
156 			.parent_data = gcc_parent_data_1,
157 			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
158 			.ops = &clk_alpha_pll_ops,
159 		},
160 	},
161 };
162 
163 static struct clk_alpha_pll gpll4_out_main = {
164 	.offset = 0x24000,
165 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
166 	.clkr = {
167 		.enable_reg = 0x45000,
168 		.enable_mask = BIT(5),
169 		.hw.init = &(struct clk_init_data){
170 			.name = "gpll4_out_main",
171 			.parent_data = gcc_parent_data_1,
172 			.num_parents = ARRAY_SIZE(gcc_parent_data_1),
173 			.ops = &clk_alpha_pll_ops,
174 		},
175 	},
176 };
177 
178 static struct clk_pll gpll6 = {
179 	.l_reg = 0x37004,
180 	.m_reg = 0x37008,
181 	.n_reg = 0x3700C,
182 	.config_reg = 0x37014,
183 	.mode_reg = 0x37000,
184 	.status_reg = 0x3701C,
185 	.status_bit = 17,
186 	.clkr.hw.init = &(struct clk_init_data){
187 		.name = "gpll6",
188 		.parent_data = gcc_parent_data_1,
189 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
190 		.ops = &clk_pll_ops,
191 	},
192 };
193 
194 static struct clk_regmap gpll6_out_aux = {
195 	.enable_reg = 0x45000,
196 	.enable_mask = BIT(7),
197 	.hw.init = &(struct clk_init_data){
198 		.name = "gpll6_out_aux",
199 		.parent_hws = (const struct clk_hw*[]) {
200 			&gpll6.clkr.hw,
201 		},
202 		.num_parents = 1,
203 		.ops = &clk_pll_vote_ops,
204 	},
205 };
206 
207 static const struct parent_map gcc_parent_map_0[] = {
208 	{ P_XO, 0 },
209 	{ P_GPLL0_OUT_MAIN, 1 },
210 };
211 
212 static const struct clk_parent_data gcc_parent_data_0[] = {
213 	{ .index = DT_XO, .name = "xo-board" },
214 	{ .hw = &gpll0_out_main.clkr.hw },
215 };
216 
217 static const struct clk_parent_data gcc_parent_data_ao_0[] = {
218 	{ .index = DT_XO, .name = "xo-board" },
219 	{ .hw = &gpll0_ao_out_main.clkr.hw },
220 };
221 
222 static const struct parent_map gcc_parent_map_2[] = {
223 	{ P_XO, 0 },
224 	{ P_GPLL0_OUT_MAIN, 1 },
225 	{ P_GPLL6_OUT_AUX, 2 },
226 	{ P_SLEEP_CLK, 6 },
227 };
228 
229 static const struct clk_parent_data gcc_parent_data_2[] = {
230 	{ .index = DT_XO, .name = "xo-board" },
231 	{ .hw = &gpll0_out_main.clkr.hw },
232 	{ .hw = &gpll6_out_aux.hw },
233 	{ .index = DT_SLEEP_CLK, .name = "sleep_clk" },
234 };
235 
236 static const struct parent_map gcc_parent_map_3[] = {
237 	{ P_XO, 0 },
238 	{ P_GPLL0_OUT_MAIN, 1 },
239 	{ P_GPLL6_OUT_AUX, 2 },
240 };
241 
242 static const struct clk_parent_data gcc_parent_data_3[] = {
243 	{ .index = DT_XO, .name = "xo-board" },
244 	{ .hw = &gpll0_out_main.clkr.hw },
245 	{ .hw = &gpll6_out_aux.hw },
246 };
247 
248 static const struct parent_map gcc_parent_map_4[] = {
249 	{ P_XO, 0 },
250 	{ P_GPLL1_OUT_MAIN, 1 },
251 };
252 
253 static const struct clk_parent_data gcc_parent_data_4[] = {
254 	{ .index = DT_XO, .name = "xo-board" },
255 	{ .hw = &gpll1_out_main.clkr.hw },
256 };
257 
258 static const struct parent_map gcc_parent_map_5[] = {
259 	{ P_XO, 0 },
260 	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
261 };
262 
263 static const struct clk_parent_data gcc_parent_data_5[] = {
264 	{ .index = DT_XO, .name = "xo-board" },
265 	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" },
266 };
267 
268 static const struct parent_map gcc_parent_map_6[] = {
269 	{ P_XO, 0 },
270 	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
271 };
272 
273 static const struct clk_parent_data gcc_parent_data_6[] = {
274 	{ .index = DT_XO, .name = "xo-board" },
275 	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" },
276 };
277 
278 static const struct parent_map gcc_parent_map_7[] = {
279 	{ P_XO, 0 },
280 	{ P_GPLL0_OUT_MAIN, 1 },
281 	{ P_GPLL3_OUT_MAIN, 2 },
282 	{ P_GPLL6_OUT_AUX, 3 },
283 };
284 
285 static const struct clk_parent_data gcc_parent_data_7[] = {
286 	{ .index = DT_XO, .name = "xo-board" },
287 	{ .hw = &gpll0_out_main.clkr.hw },
288 	{ .hw = &gpll3_out_main.clkr.hw },
289 	{ .hw = &gpll6_out_aux.hw },
290 };
291 
292 static const struct parent_map gcc_parent_map_8[] = {
293 	{ P_XO, 0 },
294 	{ P_HDMI_PHY_PLL_CLK, 1 },
295 };
296 
297 static const struct clk_parent_data gcc_parent_data_8[] = {
298 	{ .index = DT_XO, .name = "xo-board" },
299 	{ .index = DT_HDMI_PHY_PLL_CLK, .name = "hdmi_pll" },
300 };
301 
302 static const struct parent_map gcc_parent_map_9[] = {
303 	{ P_XO, 0 },
304 	{ P_GPLL0_OUT_MAIN, 1 },
305 	{ P_DSI0_PHY_PLL_OUT_DSICLK, 2 },
306 	{ P_GPLL6_OUT_AUX, 3 },
307 };
308 
309 static const struct clk_parent_data gcc_parent_data_9[] = {
310 	{ .index = DT_XO, .name = "xo-board" },
311 	{ .hw = &gpll0_out_main.clkr.hw },
312 	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" },
313 	{ .hw = &gpll6_out_aux.hw },
314 };
315 
316 static const struct parent_map gcc_parent_map_10[] = {
317 	{ P_XO, 0 },
318 	{ P_SLEEP_CLK, 1 },
319 };
320 
321 static const struct clk_parent_data gcc_parent_data_10[] = {
322 	{ .index = DT_XO, .name = "xo-board" },
323 	{ .index = DT_SLEEP_CLK, .name = "sleep_clk" },
324 };
325 
326 static const struct parent_map gcc_parent_map_11[] = {
327 	{ P_XO, 0 },
328 	{ P_PCIE_0_PIPE_CLK, 1 },
329 };
330 
331 static const struct clk_parent_data gcc_parent_data_11[] = {
332 	{ .index = DT_XO, .name = "xo-board" },
333 	{ .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
334 };
335 
336 static const struct parent_map gcc_parent_map_12[] = {
337 	{ P_XO, 0 },
338 	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
339 };
340 
341 static const struct clk_parent_data gcc_parent_data_12[] = {
342 	{ .index = DT_XO, .name = "xo-board" },
343 	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" },
344 };
345 
346 static const struct parent_map gcc_parent_map_13[] = {
347 	{ P_XO, 0 },
348 	{ P_GPLL0_OUT_MAIN, 1 },
349 	{ P_GPLL4_OUT_MAIN, 2 },
350 	{ P_GPLL6_OUT_AUX, 3 },
351 };
352 
353 static const struct clk_parent_data gcc_parent_data_13[] = {
354 	{ .index = DT_XO, .name = "xo-board" },
355 	{ .hw = &gpll0_out_main.clkr.hw },
356 	{ .hw = &gpll4_out_main.clkr.hw },
357 	{ .hw = &gpll6_out_aux.hw },
358 };
359 
360 static const struct parent_map gcc_parent_map_14[] = {
361 	{ P_XO, 0 },
362 	{ P_GPLL0_OUT_MAIN, 1 },
363 };
364 
365 static const struct clk_parent_data gcc_parent_data_14[] = {
366 	{ .index = DT_XO, .name = "xo-board" },
367 	{ .hw = &gpll0_out_main.clkr.hw },
368 };
369 
370 static const struct parent_map gcc_parent_map_15[] = {
371 	{ P_XO, 0 },
372 };
373 
374 static const struct clk_parent_data gcc_parent_data_15[] = {
375 	{ .index = DT_XO, .name = "xo-board" },
376 };
377 
378 static const struct parent_map gcc_parent_map_16[] = {
379 	{ P_XO, 0 },
380 	{ P_GPLL0_OUT_MAIN, 1 },
381 };
382 
383 static const struct clk_parent_data gcc_parent_data_16[] = {
384 	{ .index = DT_XO, .name = "xo-board" },
385 	{ .hw = &gpll0_out_main.clkr.hw },
386 };
387 
388 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
389 	F(19200000, P_XO, 1, 0, 0),
390 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
391 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
392 	F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
393 	{ }
394 };
395 
396 static struct clk_rcg2 apss_ahb_clk_src = {
397 	.cmd_rcgr = 0x46000,
398 	.mnd_width = 0,
399 	.hid_width = 5,
400 	.parent_map = gcc_parent_map_0,
401 	.freq_tbl = ftbl_apss_ahb_clk_src,
402 	.clkr.hw.init = &(struct clk_init_data){
403 		.name = "apss_ahb_clk_src",
404 		.parent_data = gcc_parent_data_ao_0,
405 		.num_parents = ARRAY_SIZE(gcc_parent_data_ao_0),
406 		.flags = CLK_IS_CRITICAL,
407 		.ops = &clk_rcg2_ops,
408 	},
409 };
410 
411 static const struct freq_tbl ftbl_blsp1_qup0_i2c_apps_clk_src[] = {
412 	F(19200000, P_XO, 1, 0, 0),
413 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
414 	{ }
415 };
416 
417 static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = {
418 	.cmd_rcgr = 0x602c,
419 	.mnd_width = 0,
420 	.hid_width = 5,
421 	.parent_map = gcc_parent_map_0,
422 	.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
423 	.clkr.hw.init = &(struct clk_init_data){
424 		.name = "blsp1_qup0_i2c_apps_clk_src",
425 		.parent_data = gcc_parent_data_0,
426 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
427 		.ops = &clk_rcg2_ops,
428 	},
429 };
430 
431 static const struct freq_tbl ftbl_blsp1_qup0_spi_apps_clk_src[] = {
432 	F(960000, P_XO, 10, 1, 2),
433 	F(4800000, P_XO, 4, 0, 0),
434 	F(9600000, P_XO, 2, 0, 0),
435 	F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
436 	F(19200000, P_XO, 1, 0, 0),
437 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
438 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
439 	{ }
440 };
441 
442 static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = {
443 	.cmd_rcgr = 0x6034,
444 	.mnd_width = 8,
445 	.hid_width = 5,
446 	.parent_map = gcc_parent_map_0,
447 	.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
448 	.clkr.hw.init = &(struct clk_init_data){
449 		.name = "blsp1_qup0_spi_apps_clk_src",
450 		.parent_data = gcc_parent_data_0,
451 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
452 		.ops = &clk_rcg2_ops,
453 	},
454 };
455 
456 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
457 	.cmd_rcgr = 0x200c,
458 	.mnd_width = 0,
459 	.hid_width = 5,
460 	.parent_map = gcc_parent_map_0,
461 	.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
462 	.clkr.hw.init = &(struct clk_init_data){
463 		.name = "blsp1_qup1_i2c_apps_clk_src",
464 		.parent_data = gcc_parent_data_0,
465 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
466 		.ops = &clk_rcg2_ops,
467 	},
468 };
469 
470 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
471 	F(960000,   P_XO, 10, 1, 2),
472 	F(4800000,  P_XO, 4, 0, 0),
473 	F(9600000,  P_XO, 2, 0, 0),
474 	F(10480000, P_GPLL0_OUT_MAIN, 1, 3, 229),
475 	F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
476 	F(19200000, P_XO, 1, 0, 0),
477 	F(20961000, P_GPLL0_OUT_MAIN, 1, 6, 229),
478 	{ }
479 };
480 
481 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
482 	.cmd_rcgr = 0x2024,
483 	.mnd_width = 8,
484 	.hid_width = 5,
485 	.parent_map = gcc_parent_map_0,
486 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
487 	.clkr.hw.init = &(struct clk_init_data){
488 		.name = "blsp1_qup1_spi_apps_clk_src",
489 		.parent_data = gcc_parent_data_0,
490 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
491 		.ops = &clk_rcg2_ops,
492 	},
493 };
494 
495 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
496 	.cmd_rcgr = 0x3000,
497 	.mnd_width = 0,
498 	.hid_width = 5,
499 	.parent_map = gcc_parent_map_0,
500 	.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
501 	.clkr.hw.init = &(struct clk_init_data){
502 		.name = "blsp1_qup2_i2c_apps_clk_src",
503 		.parent_data = gcc_parent_data_0,
504 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
505 		.ops = &clk_rcg2_ops,
506 	},
507 };
508 
509 static const struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
510 	F(960000,   P_XO, 10, 1, 2),
511 	F(4800000,  P_XO, 4, 0, 0),
512 	F(9600000,  P_XO, 2, 0, 0),
513 	F(15000000, P_GPLL0_OUT_MAIN, 1,  3, 160),
514 	F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
515 	F(19200000, P_XO, 1, 0, 0),
516 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
517 	F(30000000, P_GPLL0_OUT_MAIN, 1,  3, 80),
518 	{ }
519 };
520 
521 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
522 	.cmd_rcgr = 0x3014,
523 	.mnd_width = 8,
524 	.hid_width = 5,
525 	.parent_map = gcc_parent_map_0,
526 	.freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
527 	.clkr.hw.init = &(struct clk_init_data){
528 		.name = "blsp1_qup2_spi_apps_clk_src",
529 		.parent_data = gcc_parent_data_0,
530 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
531 		.ops = &clk_rcg2_ops,
532 	},
533 };
534 
535 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
536 	.cmd_rcgr = 0x4000,
537 	.mnd_width = 0,
538 	.hid_width = 5,
539 	.parent_map = gcc_parent_map_0,
540 	.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
541 	.clkr.hw.init = &(struct clk_init_data){
542 		.name = "blsp1_qup3_i2c_apps_clk_src",
543 		.parent_data = gcc_parent_data_0,
544 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
545 		.ops = &clk_rcg2_ops,
546 	},
547 };
548 
549 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
550 	.cmd_rcgr = 0x4024,
551 	.mnd_width = 8,
552 	.hid_width = 5,
553 	.parent_map = gcc_parent_map_0,
554 	.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
555 	.clkr.hw.init = &(struct clk_init_data){
556 		.name = "blsp1_qup3_spi_apps_clk_src",
557 		.parent_data = gcc_parent_data_0,
558 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
559 		.ops = &clk_rcg2_ops,
560 	},
561 };
562 
563 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
564 	.cmd_rcgr = 0x5000,
565 	.mnd_width = 0,
566 	.hid_width = 5,
567 	.parent_map = gcc_parent_map_0,
568 	.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
569 	.clkr.hw.init = &(struct clk_init_data){
570 		.name = "blsp1_qup4_i2c_apps_clk_src",
571 		.parent_data = gcc_parent_data_0,
572 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
573 		.ops = &clk_rcg2_ops,
574 	},
575 };
576 
577 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
578 	.cmd_rcgr = 0x5024,
579 	.mnd_width = 8,
580 	.hid_width = 5,
581 	.parent_map = gcc_parent_map_0,
582 	.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
583 	.clkr.hw.init = &(struct clk_init_data){
584 		.name = "blsp1_qup4_spi_apps_clk_src",
585 		.parent_data = gcc_parent_data_0,
586 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
587 		.ops = &clk_rcg2_ops,
588 	},
589 };
590 
591 static const struct freq_tbl ftbl_blsp1_uart0_apps_clk_src[] = {
592 	F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),
593 	F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),
594 	F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),
595 	F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
596 	F(19200000, P_XO, 1, 0, 0),
597 	F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),
598 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
599 	F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
600 	F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
601 	F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
602 	F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
603 	F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
604 	F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
605 	F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
606 	F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
607 	F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
608 	{ }
609 };
610 
611 static struct clk_rcg2 blsp1_uart0_apps_clk_src = {
612 	.cmd_rcgr = 0x600c,
613 	.mnd_width = 16,
614 	.hid_width = 5,
615 	.parent_map = gcc_parent_map_0,
616 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
617 	.clkr.hw.init = &(struct clk_init_data){
618 		.name = "blsp1_uart0_apps_clk_src",
619 		.parent_data = gcc_parent_data_0,
620 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
621 		.ops = &clk_rcg2_ops,
622 	},
623 };
624 
625 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
626 	.cmd_rcgr = 0x2044,
627 	.mnd_width = 16,
628 	.hid_width = 5,
629 	.parent_map = gcc_parent_map_0,
630 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
631 	.clkr.hw.init = &(struct clk_init_data){
632 		.name = "blsp1_uart1_apps_clk_src",
633 		.parent_data = gcc_parent_data_0,
634 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
635 		.ops = &clk_rcg2_ops,
636 	},
637 };
638 
639 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
640 	.cmd_rcgr = 0x3034,
641 	.mnd_width = 16,
642 	.hid_width = 5,
643 	.parent_map = gcc_parent_map_0,
644 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
645 	.clkr.hw.init = &(struct clk_init_data){
646 		.name = "blsp1_uart2_apps_clk_src",
647 		.parent_data = gcc_parent_data_0,
648 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
649 		.ops = &clk_rcg2_ops,
650 	},
651 };
652 
653 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
654 	.cmd_rcgr = 0x4014,
655 	.mnd_width = 16,
656 	.hid_width = 5,
657 	.cfg_off = 0x20,
658 	.parent_map = gcc_parent_map_0,
659 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
660 	.clkr.hw.init = &(struct clk_init_data){
661 		.name = "blsp1_uart3_apps_clk_src",
662 		.parent_data = gcc_parent_data_0,
663 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
664 		.ops = &clk_rcg2_ops,
665 	},
666 };
667 
668 static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = {
669 	.cmd_rcgr = 0xc00c,
670 	.mnd_width = 0,
671 	.hid_width = 5,
672 	.parent_map = gcc_parent_map_0,
673 	.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
674 	.clkr.hw.init = &(struct clk_init_data){
675 		.name = "blsp2_qup0_i2c_apps_clk_src",
676 		.parent_data = gcc_parent_data_0,
677 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
678 		.ops = &clk_rcg2_ops,
679 	},
680 };
681 
682 static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = {
683 	.cmd_rcgr = 0xc024,
684 	.mnd_width = 8,
685 	.hid_width = 5,
686 	.parent_map = gcc_parent_map_0,
687 	.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
688 	.clkr.hw.init = &(struct clk_init_data){
689 		.name = "blsp2_qup0_spi_apps_clk_src",
690 		.parent_data = gcc_parent_data_0,
691 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
692 		.ops = &clk_rcg2_ops,
693 	},
694 };
695 
696 static struct clk_rcg2 blsp2_uart0_apps_clk_src = {
697 	.cmd_rcgr = 0xc044,
698 	.mnd_width = 16,
699 	.hid_width = 5,
700 	.parent_map = gcc_parent_map_0,
701 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
702 	.clkr.hw.init = &(struct clk_init_data){
703 		.name = "blsp2_uart0_apps_clk_src",
704 		.parent_data = gcc_parent_data_0,
705 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
706 		.ops = &clk_rcg2_ops,
707 	},
708 };
709 
710 static struct clk_rcg2 byte0_clk_src = {
711 	.cmd_rcgr = 0x4d044,
712 	.mnd_width = 0,
713 	.hid_width = 5,
714 	.parent_map = gcc_parent_map_5,
715 	.clkr.hw.init = &(struct clk_init_data){
716 		.name = "byte0_clk_src",
717 		.parent_data = gcc_parent_data_5,
718 		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
719 		.flags = CLK_SET_RATE_PARENT,
720 		.ops = &clk_byte2_ops,
721 	},
722 };
723 
724 static const struct freq_tbl ftbl_emac_clk_src[] = {
725 	F(5000000,   P_GPLL1_OUT_MAIN, 2, 1, 50),
726 	F(50000000,  P_GPLL1_OUT_MAIN, 10, 0, 0),
727 	F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
728 	F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
729 	{ }
730 };
731 
732 static struct clk_rcg2 emac_clk_src = {
733 	.cmd_rcgr = 0x4e01c,
734 	.mnd_width = 8,
735 	.hid_width = 5,
736 	.parent_map = gcc_parent_map_4,
737 	.freq_tbl = ftbl_emac_clk_src,
738 	.clkr.hw.init = &(struct clk_init_data){
739 		.name = "emac_clk_src",
740 		.parent_data = gcc_parent_data_4,
741 		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
742 		.ops = &clk_rcg2_ops,
743 	},
744 };
745 
746 static const struct freq_tbl ftbl_emac_ptp_clk_src[] = {
747 	F(50000000,  P_GPLL1_OUT_MAIN, 10, 0, 0),
748 	F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
749 	F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
750 	{ }
751 };
752 
753 static struct clk_rcg2 emac_ptp_clk_src = {
754 	.cmd_rcgr = 0x4e014,
755 	.mnd_width = 0,
756 	.hid_width = 5,
757 	.parent_map = gcc_parent_map_4,
758 	.freq_tbl = ftbl_emac_ptp_clk_src,
759 	.clkr.hw.init = &(struct clk_init_data){
760 		.name = "emac_ptp_clk_src",
761 		.parent_data = gcc_parent_data_4,
762 		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
763 		.ops = &clk_rcg2_ops,
764 	},
765 };
766 
767 static const struct freq_tbl ftbl_esc0_clk_src[] = {
768 	F(19200000, P_XO, 1, 0, 0),
769 	{ }
770 };
771 
772 static struct clk_rcg2 esc0_clk_src = {
773 	.cmd_rcgr = 0x4d05c,
774 	.mnd_width = 0,
775 	.hid_width = 5,
776 	.parent_map = gcc_parent_map_6,
777 	.freq_tbl = ftbl_esc0_clk_src,
778 	.clkr.hw.init = &(struct clk_init_data){
779 		.name = "esc0_clk_src",
780 		.parent_data = gcc_parent_data_6,
781 		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
782 		.ops = &clk_rcg2_ops,
783 	},
784 };
785 
786 static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
787 	F(19200000,  P_XO, 1, 0, 0),
788 	F(50000000,  P_GPLL0_OUT_MAIN, 16, 0, 0),
789 	F(80000000,  P_GPLL0_OUT_MAIN, 10, 0, 0),
790 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
791 	F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
792 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
793 	F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
794 	F(240000000, P_GPLL6_OUT_AUX,  4.5, 0, 0),
795 	F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
796 	F(270000000, P_GPLL6_OUT_AUX,  4, 0, 0),
797 	F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
798 	F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
799 	F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0),
800 	F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0),
801 	F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
802 	F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
803 	{ }
804 };
805 
806 static struct clk_rcg2 gfx3d_clk_src = {
807 	.cmd_rcgr = 0x59000,
808 	.mnd_width = 0,
809 	.hid_width = 5,
810 	.parent_map = gcc_parent_map_7,
811 	.freq_tbl = ftbl_gfx3d_clk_src,
812 	.clkr.hw.init = &(struct clk_init_data){
813 		.name = "gfx3d_clk_src",
814 		.parent_data = gcc_parent_data_7,
815 		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
816 		.ops = &clk_rcg2_ops,
817 	},
818 };
819 
820 static const struct freq_tbl ftbl_gp1_clk_src[] = {
821 	F(19200000, P_XO, 1, 0, 0),
822 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
823 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
824 	{ }
825 };
826 
827 static struct clk_rcg2 gp1_clk_src = {
828 	.cmd_rcgr = 0x8004,
829 	.mnd_width = 8,
830 	.hid_width = 5,
831 	.parent_map = gcc_parent_map_2,
832 	.freq_tbl = ftbl_gp1_clk_src,
833 	.clkr.hw.init = &(struct clk_init_data){
834 		.name = "gp1_clk_src",
835 		.parent_data = gcc_parent_data_2,
836 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
837 		.ops = &clk_rcg2_ops,
838 	},
839 };
840 
841 static struct clk_rcg2 gp2_clk_src = {
842 	.cmd_rcgr = 0x9004,
843 	.mnd_width = 8,
844 	.hid_width = 5,
845 	.parent_map = gcc_parent_map_2,
846 	.freq_tbl = ftbl_gp1_clk_src,
847 	.clkr.hw.init = &(struct clk_init_data){
848 		.name = "gp2_clk_src",
849 		.parent_data = gcc_parent_data_2,
850 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
851 		.ops = &clk_rcg2_ops,
852 	},
853 };
854 
855 static struct clk_rcg2 gp3_clk_src = {
856 	.cmd_rcgr = 0xa004,
857 	.mnd_width = 8,
858 	.hid_width = 5,
859 	.parent_map = gcc_parent_map_2,
860 	.freq_tbl = ftbl_gp1_clk_src,
861 	.clkr.hw.init = &(struct clk_init_data){
862 		.name = "gp3_clk_src",
863 		.parent_data = gcc_parent_data_2,
864 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
865 		.ops = &clk_rcg2_ops,
866 	},
867 };
868 
869 static struct clk_rcg2 hdmi_app_clk_src = {
870 	.cmd_rcgr = 0x4d0e4,
871 	.mnd_width = 0,
872 	.hid_width = 5,
873 	.parent_map = gcc_parent_map_1,
874 	.freq_tbl = ftbl_esc0_clk_src,
875 	.clkr.hw.init = &(struct clk_init_data){
876 		.name = "hdmi_app_clk_src",
877 		.parent_data = gcc_parent_data_1,
878 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
879 		.ops = &clk_rcg2_ops,
880 	},
881 };
882 
883 static struct clk_rcg2 hdmi_pclk_clk_src = {
884 	.cmd_rcgr = 0x4d0dc,
885 	.mnd_width = 0,
886 	.hid_width = 5,
887 	.parent_map = gcc_parent_map_8,
888 	.freq_tbl = ftbl_esc0_clk_src,
889 	.clkr.hw.init = &(struct clk_init_data){
890 		.name = "hdmi_pclk_clk_src",
891 		.parent_data = gcc_parent_data_8,
892 		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
893 		.ops = &clk_rcg2_ops,
894 	},
895 };
896 
897 static const struct freq_tbl ftbl_mdp_clk_src[] = {
898 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
899 	F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
900 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
901 	F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0),
902 	F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
903 	F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
904 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
905 	F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
906 	F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
907 	{ }
908 };
909 
910 static struct clk_rcg2 mdp_clk_src = {
911 	.cmd_rcgr = 0x4d014,
912 	.mnd_width = 0,
913 	.hid_width = 5,
914 	.parent_map = gcc_parent_map_9,
915 	.freq_tbl = ftbl_mdp_clk_src,
916 	.clkr.hw.init = &(struct clk_init_data){
917 		.name = "mdp_clk_src",
918 		.parent_data = gcc_parent_data_9,
919 		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
920 		.ops = &clk_rcg2_ops,
921 	},
922 };
923 
924 static const struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
925 	F(1200000, P_XO, 16, 0, 0),
926 	{ }
927 };
928 
929 static struct clk_rcg2 pcie_0_aux_clk_src = {
930 	.cmd_rcgr = 0x3e024,
931 	.mnd_width = 16,
932 	.hid_width = 5,
933 	.parent_map = gcc_parent_map_10,
934 	.freq_tbl = ftbl_pcie_0_aux_clk_src,
935 	.clkr.hw.init = &(struct clk_init_data){
936 		.name = "pcie_0_aux_clk_src",
937 		.parent_data = gcc_parent_data_10,
938 		.num_parents = ARRAY_SIZE(gcc_parent_data_10),
939 		.ops = &clk_rcg2_ops,
940 	},
941 };
942 
943 static const struct freq_tbl ftbl_pcie_0_pipe_clk_src[] = {
944 	F(19200000, P_XO, 1, 0, 0),
945 	F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0),
946 	F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0),
947 	{ }
948 };
949 
950 static struct clk_rcg2 pcie_0_pipe_clk_src = {
951 	.cmd_rcgr = 0x3e01c,
952 	.mnd_width = 0,
953 	.hid_width = 5,
954 	.parent_map = gcc_parent_map_11,
955 	.freq_tbl = ftbl_pcie_0_pipe_clk_src,
956 	.clkr.hw.init = &(struct clk_init_data){
957 		.name = "pcie_0_pipe_clk_src",
958 		.parent_data = gcc_parent_data_11,
959 		.num_parents = ARRAY_SIZE(gcc_parent_data_11),
960 		.ops = &clk_rcg2_ops,
961 	},
962 };
963 
964 static struct clk_rcg2 pclk0_clk_src = {
965 	.cmd_rcgr = 0x4d000,
966 	.mnd_width = 8,
967 	.hid_width = 5,
968 	.parent_map = gcc_parent_map_12,
969 	.clkr.hw.init = &(struct clk_init_data){
970 		.name = "pclk0_clk_src",
971 		.parent_data = gcc_parent_data_12,
972 		.num_parents = ARRAY_SIZE(gcc_parent_data_12),
973 		.flags = CLK_SET_RATE_PARENT,
974 		.ops = &clk_pixel_ops,
975 	},
976 };
977 
978 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
979 	F(19200000, P_XO, 1, 0, 0),
980 	F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
981 	{ }
982 };
983 
984 static struct clk_rcg2 pdm2_clk_src = {
985 	.cmd_rcgr = 0x44010,
986 	.mnd_width = 0,
987 	.hid_width = 5,
988 	.parent_map = gcc_parent_map_0,
989 	.freq_tbl = ftbl_pdm2_clk_src,
990 	.clkr.hw.init = &(struct clk_init_data){
991 		.name = "pdm2_clk_src",
992 		.parent_data = gcc_parent_data_0,
993 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
994 		.ops = &clk_rcg2_ops,
995 	},
996 };
997 
998 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
999 	F(144000, P_XO, 16, 3, 25),
1000 	F(400000, P_XO, 12, 1, 4),
1001 	F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1002 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1003 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1004 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1005 	F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1006 	F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
1007 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1008 	F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0),
1009 	{ }
1010 };
1011 
1012 static struct clk_rcg2 sdcc1_apps_clk_src = {
1013 	.cmd_rcgr = 0x42004,
1014 	.mnd_width = 8,
1015 	.hid_width = 5,
1016 	.parent_map = gcc_parent_map_13,
1017 	.freq_tbl = ftbl_sdcc1_apps_clk_src,
1018 	.clkr.hw.init = &(struct clk_init_data){
1019 		.name = "sdcc1_apps_clk_src",
1020 		.parent_data = gcc_parent_data_13,
1021 		.num_parents = ARRAY_SIZE(gcc_parent_data_13),
1022 		.ops = &clk_rcg2_floor_ops,
1023 	},
1024 };
1025 
1026 static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1027 	F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1028 	F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1029 	{ }
1030 };
1031 
1032 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1033 	.cmd_rcgr = 0x5d000,
1034 	.mnd_width = 8,
1035 	.hid_width = 5,
1036 	.parent_map = gcc_parent_map_3,
1037 	.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1038 	.clkr.hw.init = &(struct clk_init_data){
1039 		.name = "sdcc1_ice_core_clk_src",
1040 		.parent_data = gcc_parent_data_3,
1041 		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1042 		.ops = &clk_rcg2_ops,
1043 	},
1044 };
1045 
1046 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1047 	F(144000, P_XO, 16, 3, 25),
1048 	F(400000, P_XO, 12, 1, 4),
1049 	F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1050 	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1051 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1052 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1053 	F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1054 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1055 	{ }
1056 };
1057 
1058 static struct clk_rcg2 sdcc2_apps_clk_src = {
1059 	.cmd_rcgr = 0x43004,
1060 	.mnd_width = 8,
1061 	.hid_width = 5,
1062 	.parent_map = gcc_parent_map_14,
1063 	.freq_tbl = ftbl_sdcc2_apps_clk_src,
1064 	.clkr.hw.init = &(struct clk_init_data){
1065 		.name = "sdcc2_apps_clk_src",
1066 		.parent_data = gcc_parent_data_14,
1067 		.num_parents = ARRAY_SIZE(gcc_parent_data_14),
1068 		.ops = &clk_rcg2_floor_ops,
1069 	},
1070 };
1071 
1072 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
1073 	.cmd_rcgr = 0x41048,
1074 	.mnd_width = 0,
1075 	.hid_width = 5,
1076 	.parent_map = gcc_parent_map_1,
1077 	.freq_tbl = ftbl_esc0_clk_src,
1078 	.clkr.hw.init = &(struct clk_init_data){
1079 		.name = "usb20_mock_utmi_clk_src",
1080 		.parent_data = gcc_parent_data_1,
1081 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1082 		.ops = &clk_rcg2_ops,
1083 	},
1084 };
1085 
1086 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1087 	F(19200000, P_XO, 1, 0, 0),
1088 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1089 	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1090 	F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1091 	{ }
1092 };
1093 
1094 static struct clk_rcg2 usb30_master_clk_src = {
1095 	.cmd_rcgr = 0x39028,
1096 	.mnd_width = 8,
1097 	.hid_width = 5,
1098 	.parent_map = gcc_parent_map_0,
1099 	.freq_tbl = ftbl_usb30_master_clk_src,
1100 	.clkr.hw.init = &(struct clk_init_data){
1101 		.name = "usb30_master_clk_src",
1102 		.parent_data = gcc_parent_data_0,
1103 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1104 		.ops = &clk_rcg2_ops,
1105 	},
1106 };
1107 
1108 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1109 	.cmd_rcgr = 0x3901c,
1110 	.mnd_width = 0,
1111 	.hid_width = 5,
1112 	.parent_map = gcc_parent_map_1,
1113 	.freq_tbl = ftbl_esc0_clk_src,
1114 	.clkr.hw.init = &(struct clk_init_data){
1115 		.name = "usb30_mock_utmi_clk_src",
1116 		.parent_data = gcc_parent_data_1,
1117 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1118 		.ops = &clk_rcg2_ops,
1119 	},
1120 };
1121 
1122 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1123 	.cmd_rcgr = 0x3903c,
1124 	.mnd_width = 0,
1125 	.hid_width = 5,
1126 	.parent_map = gcc_parent_map_1,
1127 	.freq_tbl = ftbl_pcie_0_aux_clk_src,
1128 	.clkr.hw.init = &(struct clk_init_data){
1129 		.name = "usb3_phy_aux_clk_src",
1130 		.parent_data = gcc_parent_data_1,
1131 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1132 		.ops = &clk_rcg2_ops,
1133 	},
1134 };
1135 
1136 static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1137 	F(19200000, P_XO, 1, 0, 0),
1138 	F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1139 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1140 	F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1141 	F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1142 	{ }
1143 };
1144 
1145 static struct clk_rcg2 usb_hs_system_clk_src = {
1146 	.cmd_rcgr = 0x41010,
1147 	.mnd_width = 0,
1148 	.hid_width = 5,
1149 	.parent_map = gcc_parent_map_3,
1150 	.freq_tbl = ftbl_usb_hs_system_clk_src,
1151 	.clkr.hw.init = &(struct clk_init_data){
1152 		.name = "usb_hs_system_clk_src",
1153 		.parent_data = gcc_parent_data_3,
1154 		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1155 		.ops = &clk_rcg2_ops,
1156 	},
1157 };
1158 
1159 static struct clk_rcg2 vsync_clk_src = {
1160 	.cmd_rcgr = 0x4d02c,
1161 	.mnd_width = 0,
1162 	.hid_width = 5,
1163 	.parent_map = gcc_parent_map_15,
1164 	.freq_tbl = ftbl_esc0_clk_src,
1165 	.clkr.hw.init = &(struct clk_init_data){
1166 		.name = "vsync_clk_src",
1167 		.parent_data = gcc_parent_data_15,
1168 		.num_parents = ARRAY_SIZE(gcc_parent_data_15),
1169 		.ops = &clk_rcg2_ops,
1170 	},
1171 };
1172 
1173 static const struct freq_tbl ftbl_cdsp_bimc_clk_src[] = {
1174 	F(19200000, P_XO, 1, 0, 0),
1175 	F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1176 	F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1177 	F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1178 	{ }
1179 };
1180 
1181 static struct clk_rcg2 cdsp_bimc_clk_src = {
1182 	.cmd_rcgr = 0x5e010,
1183 	.mnd_width = 0,
1184 	.hid_width = 5,
1185 	.parent_map = gcc_parent_map_16,
1186 	.freq_tbl = ftbl_cdsp_bimc_clk_src,
1187 	.clkr.hw.init = &(struct clk_init_data) {
1188 		.name = "cdsp_bimc_clk_src",
1189 		.parent_data = gcc_parent_data_16,
1190 		.num_parents = ARRAY_SIZE(gcc_parent_data_16),
1191 		.ops = &clk_rcg2_ops,
1192 	},
1193 };
1194 
1195 static struct clk_branch gcc_apss_ahb_clk = {
1196 	.halt_reg = 0x4601c,
1197 	.halt_check = BRANCH_HALT_VOTED,
1198 	.clkr = {
1199 		.enable_reg = 0x45004,
1200 		.enable_mask = BIT(14),
1201 		.hw.init = &(struct clk_init_data){
1202 			.name = "gcc_apss_ahb_clk",
1203 			.parent_hws = (const struct clk_hw*[]) {
1204 				&apss_ahb_clk_src.clkr.hw,
1205 			},
1206 			.num_parents = 1,
1207 			.flags = CLK_SET_RATE_PARENT,
1208 			.ops = &clk_branch2_ops,
1209 		},
1210 	},
1211 };
1212 
1213 static struct clk_branch gcc_apss_tcu_clk = {
1214 	.halt_reg = 0x5b004,
1215 	.halt_check = BRANCH_VOTED,
1216 	.clkr = {
1217 		.enable_reg = 0x4500c,
1218 		.enable_mask = BIT(1),
1219 		.hw.init = &(struct clk_init_data){
1220 			.name = "gcc_apss_tcu_clk",
1221 			.ops = &clk_branch2_ops,
1222 		},
1223 	},
1224 };
1225 
1226 static struct clk_branch gcc_bimc_gfx_clk = {
1227 	.halt_reg = 0x59034,
1228 	.halt_check = BRANCH_HALT,
1229 	.clkr = {
1230 		.enable_reg = 0x59034,
1231 		.enable_mask = BIT(0),
1232 		.hw.init = &(struct clk_init_data){
1233 			.name = "gcc_bimc_gfx_clk",
1234 			.ops = &clk_branch2_ops,
1235 			.parent_hws = (const struct clk_hw*[]) {
1236 				&gcc_apss_tcu_clk.clkr.hw,
1237 			},
1238 
1239 		},
1240 	},
1241 };
1242 
1243 static struct clk_branch gcc_bimc_gpu_clk = {
1244 	.halt_reg = 0x59030,
1245 	.halt_check = BRANCH_HALT,
1246 	.clkr = {
1247 		.enable_reg = 0x59030,
1248 		.enable_mask = BIT(0),
1249 		.hw.init = &(struct clk_init_data){
1250 			.name = "gcc_bimc_gpu_clk",
1251 			.ops = &clk_branch2_ops,
1252 		},
1253 	},
1254 };
1255 
1256 static struct clk_branch gcc_bimc_cdsp_clk = {
1257 	.halt_reg = 0x31030,
1258 	.halt_check = BRANCH_HALT,
1259 	.clkr = {
1260 		.enable_reg = 0x31030,
1261 		.enable_mask = BIT(0),
1262 		.hw.init = &(struct clk_init_data) {
1263 			.name = "gcc_bimc_cdsp_clk",
1264 			.parent_hws = (const struct clk_hw*[]) {
1265 				&cdsp_bimc_clk_src.clkr.hw
1266 			},
1267 			.num_parents = 1,
1268 			.flags = CLK_SET_RATE_PARENT,
1269 			.ops = &clk_branch2_ops,
1270 		},
1271 	},
1272 };
1273 
1274 static struct clk_branch gcc_bimc_mdss_clk = {
1275 	.halt_reg = 0x31038,
1276 	.halt_check = BRANCH_HALT,
1277 	.clkr = {
1278 		.enable_reg = 0x31038,
1279 		.enable_mask = BIT(0),
1280 		.hw.init = &(struct clk_init_data){
1281 			.name = "gcc_bimc_mdss_clk",
1282 			.ops = &clk_branch2_ops,
1283 		},
1284 	},
1285 };
1286 
1287 static struct clk_branch gcc_blsp1_ahb_clk = {
1288 	.halt_reg = 0x1008,
1289 	.halt_check = BRANCH_HALT_VOTED,
1290 	.clkr = {
1291 		.enable_reg = 0x45004,
1292 		.enable_mask = BIT(10),
1293 		.hw.init = &(struct clk_init_data){
1294 			.name = "gcc_blsp1_ahb_clk",
1295 			.ops = &clk_branch2_ops,
1296 		},
1297 	},
1298 };
1299 
1300 static struct clk_branch gcc_dcc_clk = {
1301 	.halt_reg = 0x77004,
1302 	.halt_check = BRANCH_HALT,
1303 	.clkr = {
1304 		.enable_reg = 0x77004,
1305 		.enable_mask = BIT(0),
1306 		.hw.init = &(struct clk_init_data){
1307 			.name = "gcc_dcc_clk",
1308 			.ops = &clk_branch2_ops,
1309 		},
1310 	},
1311 };
1312 
1313 static struct clk_branch gcc_dcc_xo_clk = {
1314 	.halt_reg = 0x77008,
1315 	.halt_check = BRANCH_HALT,
1316 	.clkr = {
1317 		.enable_reg = 0x77008,
1318 		.enable_mask = BIT(0),
1319 		.hw.init = &(struct clk_init_data){
1320 			.name = "gcc_dcc_xo_clk",
1321 			.ops = &clk_branch2_ops,
1322 		},
1323 	},
1324 };
1325 
1326 static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = {
1327 	.halt_reg = 0x6028,
1328 	.halt_check = BRANCH_HALT,
1329 	.clkr = {
1330 		.enable_reg = 0x6028,
1331 		.enable_mask = BIT(0),
1332 		.hw.init = &(struct clk_init_data){
1333 			.name = "gcc_blsp1_qup0_i2c_apps_clk",
1334 			.parent_hws = (const struct clk_hw*[]) {
1335 				&blsp1_qup0_i2c_apps_clk_src.clkr.hw,
1336 			},
1337 			.num_parents = 1,
1338 			.flags = CLK_SET_RATE_PARENT,
1339 			.ops = &clk_branch2_ops,
1340 		},
1341 	},
1342 };
1343 
1344 static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = {
1345 	.halt_reg = 0x6024,
1346 	.halt_check = BRANCH_HALT,
1347 	.clkr = {
1348 		.enable_reg = 0x6024,
1349 		.enable_mask = BIT(0),
1350 		.hw.init = &(struct clk_init_data){
1351 			.name = "gcc_blsp1_qup0_spi_apps_clk",
1352 			.parent_hws = (const struct clk_hw*[]) {
1353 				&blsp1_qup0_spi_apps_clk_src.clkr.hw,
1354 			},
1355 			.num_parents = 1,
1356 			.flags = CLK_SET_RATE_PARENT,
1357 			.ops = &clk_branch2_ops,
1358 		},
1359 	},
1360 };
1361 
1362 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1363 	.halt_reg = 0x2008,
1364 	.halt_check = BRANCH_HALT,
1365 	.clkr = {
1366 		.enable_reg = 0x2008,
1367 		.enable_mask = BIT(0),
1368 		.hw.init = &(struct clk_init_data){
1369 			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1370 			.parent_hws = (const struct clk_hw*[]) {
1371 				&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1372 			},
1373 			.num_parents = 1,
1374 			.flags = CLK_SET_RATE_PARENT,
1375 			.ops = &clk_branch2_ops,
1376 		},
1377 	},
1378 };
1379 
1380 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1381 	.halt_reg = 0x2004,
1382 	.halt_check = BRANCH_HALT,
1383 	.clkr = {
1384 		.enable_reg = 0x2004,
1385 		.enable_mask = BIT(0),
1386 		.hw.init = &(struct clk_init_data){
1387 			.name = "gcc_blsp1_qup1_spi_apps_clk",
1388 			.parent_hws = (const struct clk_hw*[]) {
1389 				&blsp1_qup1_spi_apps_clk_src.clkr.hw,
1390 			},
1391 			.num_parents = 1,
1392 			.flags = CLK_SET_RATE_PARENT,
1393 			.ops = &clk_branch2_ops,
1394 		},
1395 	},
1396 };
1397 
1398 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1399 	.halt_reg = 0x3010,
1400 	.halt_check = BRANCH_HALT,
1401 	.clkr = {
1402 		.enable_reg = 0x3010,
1403 		.enable_mask = BIT(0),
1404 		.hw.init = &(struct clk_init_data){
1405 			.name = "gcc_blsp1_qup2_i2c_apps_clk",
1406 			.parent_hws = (const struct clk_hw*[]) {
1407 				&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1408 			},
1409 			.num_parents = 1,
1410 			.flags = CLK_SET_RATE_PARENT,
1411 			.ops = &clk_branch2_ops,
1412 		},
1413 	},
1414 };
1415 
1416 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1417 	.halt_reg = 0x300c,
1418 	.halt_check = BRANCH_HALT,
1419 	.clkr = {
1420 		.enable_reg = 0x300c,
1421 		.enable_mask = BIT(0),
1422 		.hw.init = &(struct clk_init_data){
1423 			.name = "gcc_blsp1_qup2_spi_apps_clk",
1424 			.parent_hws = (const struct clk_hw*[]) {
1425 				&blsp1_qup2_spi_apps_clk_src.clkr.hw,
1426 			},
1427 			.num_parents = 1,
1428 			.flags = CLK_SET_RATE_PARENT,
1429 			.ops = &clk_branch2_ops,
1430 		},
1431 	},
1432 };
1433 
1434 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1435 	.halt_reg = 0x4020,
1436 	.halt_check = BRANCH_HALT,
1437 	.clkr = {
1438 		.enable_reg = 0x4020,
1439 		.enable_mask = BIT(0),
1440 		.hw.init = &(struct clk_init_data){
1441 			.name = "gcc_blsp1_qup3_i2c_apps_clk",
1442 			.parent_hws = (const struct clk_hw*[]) {
1443 				&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1444 			},
1445 			.num_parents = 1,
1446 			.flags = CLK_SET_RATE_PARENT,
1447 			.ops = &clk_branch2_ops,
1448 		},
1449 	},
1450 };
1451 
1452 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1453 	.halt_reg = 0x401c,
1454 	.halt_check = BRANCH_HALT,
1455 	.clkr = {
1456 		.enable_reg = 0x401c,
1457 		.enable_mask = BIT(0),
1458 		.hw.init = &(struct clk_init_data){
1459 			.name = "gcc_blsp1_qup3_spi_apps_clk",
1460 			.parent_hws = (const struct clk_hw*[]) {
1461 				&blsp1_qup3_spi_apps_clk_src.clkr.hw,
1462 			},
1463 			.num_parents = 1,
1464 			.flags = CLK_SET_RATE_PARENT,
1465 			.ops = &clk_branch2_ops,
1466 		},
1467 	},
1468 };
1469 
1470 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1471 	.halt_reg = 0x5020,
1472 	.halt_check = BRANCH_HALT,
1473 	.clkr = {
1474 		.enable_reg = 0x5020,
1475 		.enable_mask = BIT(0),
1476 		.hw.init = &(struct clk_init_data){
1477 			.name = "gcc_blsp1_qup4_i2c_apps_clk",
1478 			.parent_hws = (const struct clk_hw*[]) {
1479 				&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1480 			},
1481 			.num_parents = 1,
1482 			.flags = CLK_SET_RATE_PARENT,
1483 			.ops = &clk_branch2_ops,
1484 		},
1485 	},
1486 };
1487 
1488 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1489 	.halt_reg = 0x501c,
1490 	.halt_check = BRANCH_HALT,
1491 	.clkr = {
1492 		.enable_reg = 0x501c,
1493 		.enable_mask = BIT(0),
1494 		.hw.init = &(struct clk_init_data){
1495 			.name = "gcc_blsp1_qup4_spi_apps_clk",
1496 			.parent_hws = (const struct clk_hw*[]) {
1497 				&blsp1_qup4_spi_apps_clk_src.clkr.hw,
1498 			},
1499 			.num_parents = 1,
1500 			.flags = CLK_SET_RATE_PARENT,
1501 			.ops = &clk_branch2_ops,
1502 		},
1503 	},
1504 };
1505 
1506 static struct clk_branch gcc_blsp1_uart0_apps_clk = {
1507 	.halt_reg = 0x6004,
1508 	.halt_check = BRANCH_HALT,
1509 	.clkr = {
1510 		.enable_reg = 0x6004,
1511 		.enable_mask = BIT(0),
1512 		.hw.init = &(struct clk_init_data){
1513 			.name = "gcc_blsp1_uart0_apps_clk",
1514 			.parent_hws = (const struct clk_hw*[]) {
1515 				&blsp1_uart0_apps_clk_src.clkr.hw,
1516 			},
1517 			.num_parents = 1,
1518 			.flags = CLK_SET_RATE_PARENT,
1519 			.ops = &clk_branch2_ops,
1520 		},
1521 	},
1522 };
1523 
1524 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1525 	.halt_reg = 0x203c,
1526 	.halt_check = BRANCH_HALT,
1527 	.clkr = {
1528 		.enable_reg = 0x203c,
1529 		.enable_mask = BIT(0),
1530 		.hw.init = &(struct clk_init_data){
1531 			.name = "gcc_blsp1_uart1_apps_clk",
1532 			.parent_hws = (const struct clk_hw*[]) {
1533 				&blsp1_uart1_apps_clk_src.clkr.hw,
1534 			},
1535 			.num_parents = 1,
1536 			.flags = CLK_SET_RATE_PARENT,
1537 			.ops = &clk_branch2_ops,
1538 		},
1539 	},
1540 };
1541 
1542 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1543 	.halt_reg = 0x302c,
1544 	.halt_check = BRANCH_HALT,
1545 	.clkr = {
1546 		.enable_reg = 0x302c,
1547 		.enable_mask = BIT(0),
1548 		.hw.init = &(struct clk_init_data){
1549 			.name = "gcc_blsp1_uart2_apps_clk",
1550 			.parent_hws = (const struct clk_hw*[]) {
1551 				&blsp1_uart2_apps_clk_src.clkr.hw,
1552 			},
1553 			.num_parents = 1,
1554 			.flags = CLK_SET_RATE_PARENT,
1555 			.ops = &clk_branch2_ops,
1556 		},
1557 	},
1558 };
1559 
1560 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1561 	.halt_reg = 0x400c,
1562 	.halt_check = BRANCH_HALT,
1563 	.clkr = {
1564 		.enable_reg = 0x400c,
1565 		.enable_mask = BIT(0),
1566 		.hw.init = &(struct clk_init_data){
1567 			.name = "gcc_blsp1_uart3_apps_clk",
1568 			.parent_hws = (const struct clk_hw*[]) {
1569 				&blsp1_uart3_apps_clk_src.clkr.hw,
1570 			},
1571 			.num_parents = 1,
1572 			.flags = CLK_SET_RATE_PARENT,
1573 			.ops = &clk_branch2_ops,
1574 		},
1575 	},
1576 };
1577 
1578 static struct clk_branch gcc_blsp2_ahb_clk = {
1579 	.halt_reg = 0xb008,
1580 	.halt_check = BRANCH_HALT_VOTED,
1581 	.clkr = {
1582 		.enable_reg = 0x45004,
1583 		.enable_mask = BIT(20),
1584 		.hw.init = &(struct clk_init_data){
1585 			.name = "gcc_blsp2_ahb_clk",
1586 			.ops = &clk_branch2_ops,
1587 		},
1588 	},
1589 };
1590 
1591 static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = {
1592 	.halt_reg = 0xc008,
1593 	.halt_check = BRANCH_HALT,
1594 	.clkr = {
1595 		.enable_reg = 0xc008,
1596 		.enable_mask = BIT(0),
1597 		.hw.init = &(struct clk_init_data){
1598 			.name = "gcc_blsp2_qup0_i2c_apps_clk",
1599 			.parent_hws = (const struct clk_hw*[]) {
1600 				&blsp2_qup0_i2c_apps_clk_src.clkr.hw,
1601 			},
1602 			.num_parents = 1,
1603 			.flags = CLK_SET_RATE_PARENT,
1604 			.ops = &clk_branch2_ops,
1605 		},
1606 	},
1607 };
1608 
1609 static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = {
1610 	.halt_reg = 0xc004,
1611 	.halt_check = BRANCH_HALT,
1612 	.clkr = {
1613 		.enable_reg = 0xc004,
1614 		.enable_mask = BIT(0),
1615 		.hw.init = &(struct clk_init_data){
1616 			.name = "gcc_blsp2_qup0_spi_apps_clk",
1617 			.parent_hws = (const struct clk_hw*[]) {
1618 				&blsp2_qup0_spi_apps_clk_src.clkr.hw,
1619 			},
1620 			.num_parents = 1,
1621 			.flags = CLK_SET_RATE_PARENT,
1622 			.ops = &clk_branch2_ops,
1623 		},
1624 	},
1625 };
1626 
1627 static struct clk_branch gcc_blsp2_uart0_apps_clk = {
1628 	.halt_reg = 0xc03c,
1629 	.halt_check = BRANCH_HALT,
1630 	.clkr = {
1631 		.enable_reg = 0xc03c,
1632 		.enable_mask = BIT(0),
1633 		.hw.init = &(struct clk_init_data){
1634 			.name = "gcc_blsp2_uart0_apps_clk",
1635 			.parent_hws = (const struct clk_hw*[]) {
1636 				&blsp2_uart0_apps_clk_src.clkr.hw,
1637 			},
1638 			.num_parents = 1,
1639 			.flags = CLK_SET_RATE_PARENT,
1640 			.ops = &clk_branch2_ops,
1641 		},
1642 	},
1643 };
1644 
1645 static struct clk_branch gcc_boot_rom_ahb_clk = {
1646 	.halt_reg = 0x1300c,
1647 	.halt_check = BRANCH_HALT_VOTED,
1648 	.clkr = {
1649 		.enable_reg = 0x45004,
1650 		.enable_mask = BIT(7),
1651 		.hw.init = &(struct clk_init_data){
1652 			.name = "gcc_boot_rom_ahb_clk",
1653 			.ops = &clk_branch2_ops,
1654 		},
1655 	},
1656 };
1657 
1658 static struct clk_branch gcc_crypto_ahb_clk = {
1659 	.halt_reg = 0x16024,
1660 	.halt_check = BRANCH_VOTED,
1661 	.clkr = {
1662 		.enable_reg = 0x45004,
1663 		.enable_mask = BIT(0),
1664 		.hw.init = &(struct clk_init_data){
1665 			.name = "gcc_crypto_ahb_clk",
1666 			.ops = &clk_branch2_ops,
1667 		},
1668 	},
1669 };
1670 
1671 static struct clk_branch gcc_crypto_axi_clk = {
1672 	.halt_reg = 0x16020,
1673 	.halt_check = BRANCH_VOTED,
1674 	.clkr = {
1675 		.enable_reg = 0x45004,
1676 		.enable_mask = BIT(1),
1677 		.hw.init = &(struct clk_init_data){
1678 			.name = "gcc_crypto_axi_clk",
1679 			.ops = &clk_branch2_ops,
1680 		},
1681 	},
1682 };
1683 
1684 static struct clk_branch gcc_crypto_clk = {
1685 	.halt_reg = 0x1601c,
1686 	.halt_check = BRANCH_VOTED,
1687 	.clkr = {
1688 		.enable_reg = 0x45004,
1689 		.enable_mask = BIT(2),
1690 		.hw.init = &(struct clk_init_data){
1691 			.name = "gcc_crypto_clk",
1692 			.ops = &clk_branch2_ops,
1693 		},
1694 	},
1695 };
1696 
1697 static struct clk_branch gcc_eth_axi_clk = {
1698 	.halt_reg = 0x4e010,
1699 	.halt_check = BRANCH_HALT,
1700 	.clkr = {
1701 		.enable_reg = 0x4e010,
1702 		.enable_mask = BIT(0),
1703 		.hw.init = &(struct clk_init_data){
1704 			.name = "gcc_eth_axi_clk",
1705 			.ops = &clk_branch2_ops,
1706 		},
1707 	},
1708 };
1709 
1710 static struct clk_branch gcc_eth_ptp_clk = {
1711 	.halt_reg = 0x4e004,
1712 	.halt_check = BRANCH_HALT,
1713 	.clkr = {
1714 		.enable_reg = 0x4e004,
1715 		.enable_mask = BIT(0),
1716 		.hw.init = &(struct clk_init_data){
1717 			.name = "gcc_eth_ptp_clk",
1718 			.parent_hws = (const struct clk_hw*[]) {
1719 				&emac_ptp_clk_src.clkr.hw,
1720 			},
1721 			.num_parents = 1,
1722 			.flags = CLK_SET_RATE_PARENT,
1723 			.ops = &clk_branch2_ops,
1724 		},
1725 	},
1726 };
1727 
1728 static struct clk_branch gcc_eth_rgmii_clk = {
1729 	.halt_reg = 0x4e008,
1730 	.halt_check = BRANCH_HALT,
1731 	.clkr = {
1732 		.enable_reg = 0x4e008,
1733 		.enable_mask = BIT(0),
1734 		.hw.init = &(struct clk_init_data){
1735 			.name = "gcc_eth_rgmii_clk",
1736 			.parent_hws = (const struct clk_hw*[]) {
1737 				&emac_clk_src.clkr.hw,
1738 			},
1739 			.num_parents = 1,
1740 			.flags = CLK_SET_RATE_PARENT,
1741 			.ops = &clk_branch2_ops,
1742 		},
1743 	},
1744 };
1745 
1746 static struct clk_branch gcc_eth_slave_ahb_clk = {
1747 	.halt_reg = 0x4e00c,
1748 	.halt_check = BRANCH_HALT,
1749 	.clkr = {
1750 		.enable_reg = 0x4e00c,
1751 		.enable_mask = BIT(0),
1752 		.hw.init = &(struct clk_init_data){
1753 			.name = "gcc_eth_slave_ahb_clk",
1754 			.ops = &clk_branch2_ops,
1755 		},
1756 	},
1757 };
1758 
1759 static struct clk_branch gcc_geni_ir_s_clk = {
1760 	.halt_reg = 0xf008,
1761 	.halt_check = BRANCH_HALT,
1762 	.clkr = {
1763 		.enable_reg = 0xf008,
1764 		.enable_mask = BIT(0),
1765 		.hw.init = &(struct clk_init_data){
1766 			.name = "gcc_geni_ir_s_clk",
1767 			.ops = &clk_branch2_ops,
1768 		},
1769 	},
1770 };
1771 
1772 static struct clk_branch gcc_geni_ir_h_clk = {
1773 	.halt_reg = 0xf004,
1774 	.halt_check = BRANCH_HALT,
1775 	.clkr = {
1776 		.enable_reg = 0xf004,
1777 		.enable_mask = BIT(0),
1778 		.hw.init = &(struct clk_init_data){
1779 			.name = "gcc_geni_ir_h_clk",
1780 			.ops = &clk_branch2_ops,
1781 		},
1782 	},
1783 };
1784 
1785 static struct clk_branch gcc_gfx_tcu_clk = {
1786 	.halt_reg = 0x12020,
1787 	.halt_check = BRANCH_VOTED,
1788 	.clkr = {
1789 		.enable_reg = 0x4500C,
1790 		.enable_mask = BIT(2),
1791 		.hw.init = &(struct clk_init_data){
1792 			.name = "gcc_gfx_tcu_clk",
1793 			.ops = &clk_branch2_ops,
1794 		},
1795 	},
1796 };
1797 
1798 static struct clk_branch gcc_gfx_tbu_clk = {
1799 	.halt_reg = 0x12010,
1800 	.halt_check = BRANCH_VOTED,
1801 	.clkr = {
1802 		.enable_reg = 0x4500C,
1803 		.enable_mask = BIT(3),
1804 		.hw.init = &(struct clk_init_data){
1805 			.name = "gcc_gfx_tbu_clk",
1806 			.ops = &clk_branch2_ops,
1807 		},
1808 	},
1809 };
1810 
1811 static struct clk_branch gcc_cdsp_tbu_clk = {
1812 	.halt_reg = 0x1203c,
1813 	.halt_check = BRANCH_VOTED,
1814 	.clkr = {
1815 		.enable_reg = 0x13020,
1816 		.enable_mask = BIT(9),
1817 		.hw.init = &(struct clk_init_data) {
1818 			.name = "gcc_cdsp_tbu_clk",
1819 			.parent_hws = (const struct clk_hw*[]) {
1820 				&cdsp_bimc_clk_src.clkr.hw
1821 			},
1822 			.num_parents = 1,
1823 			.flags = CLK_SET_RATE_PARENT,
1824 			.ops = &clk_branch2_ops,
1825 		},
1826 	},
1827 };
1828 
1829 static struct clk_branch gcc_gp1_clk = {
1830 	.halt_reg = 0x8000,
1831 	.halt_check = BRANCH_HALT,
1832 	.clkr = {
1833 		.enable_reg = 0x8000,
1834 		.enable_mask = BIT(0),
1835 		.hw.init = &(struct clk_init_data){
1836 			.name = "gcc_gp1_clk",
1837 			.parent_hws = (const struct clk_hw*[]) {
1838 				&gp1_clk_src.clkr.hw,
1839 			},
1840 			.num_parents = 1,
1841 			.flags = CLK_SET_RATE_PARENT,
1842 			.ops = &clk_branch2_ops,
1843 		},
1844 	},
1845 };
1846 
1847 static struct clk_branch gcc_gp2_clk = {
1848 	.halt_reg = 0x9000,
1849 	.halt_check = BRANCH_HALT,
1850 	.clkr = {
1851 		.enable_reg = 0x9000,
1852 		.enable_mask = BIT(0),
1853 		.hw.init = &(struct clk_init_data){
1854 			.name = "gcc_gp2_clk",
1855 			.parent_hws = (const struct clk_hw*[]) {
1856 				&gp2_clk_src.clkr.hw,
1857 			},
1858 			.num_parents = 1,
1859 			.flags = CLK_SET_RATE_PARENT,
1860 			.ops = &clk_branch2_ops,
1861 		},
1862 	},
1863 };
1864 
1865 static struct clk_branch gcc_gp3_clk = {
1866 	.halt_reg = 0xa000,
1867 	.halt_check = BRANCH_HALT,
1868 	.clkr = {
1869 		.enable_reg = 0xa000,
1870 		.enable_mask = BIT(0),
1871 		.hw.init = &(struct clk_init_data){
1872 			.name = "gcc_gp3_clk",
1873 			.parent_hws = (const struct clk_hw*[]) {
1874 				&gp3_clk_src.clkr.hw,
1875 			},
1876 			.num_parents = 1,
1877 			.flags = CLK_SET_RATE_PARENT,
1878 			.ops = &clk_branch2_ops,
1879 		},
1880 	},
1881 };
1882 
1883 static struct clk_branch gcc_gtcu_ahb_clk = {
1884 	.halt_reg = 0x12044,
1885 	.halt_check = BRANCH_VOTED,
1886 	.clkr = {
1887 		.enable_reg = 0x4500c,
1888 		.enable_mask = BIT(13),
1889 		.hw.init = &(struct clk_init_data){
1890 			.name = "gcc_gtcu_ahb_clk",
1891 			.ops = &clk_branch2_ops,
1892 		},
1893 	},
1894 };
1895 
1896 static struct clk_branch gcc_mdp_tbu_clk = {
1897 	.halt_reg = 0x1201c,
1898 	.halt_check = BRANCH_VOTED,
1899 	.clkr = {
1900 		.enable_reg = 0x4500c,
1901 		.enable_mask = BIT(4),
1902 		.hw.init = &(struct clk_init_data){
1903 			.name = "gcc_mdp_tbu_clk",
1904 			.ops = &clk_branch2_ops,
1905 		},
1906 	},
1907 };
1908 
1909 static struct clk_branch gcc_mdss_ahb_clk = {
1910 	.halt_reg = 0x4d07c,
1911 	.halt_check = BRANCH_HALT,
1912 	.clkr = {
1913 		.enable_reg = 0x4d07c,
1914 		.enable_mask = BIT(0),
1915 		.hw.init = &(struct clk_init_data){
1916 			.name = "gcc_mdss_ahb_clk",
1917 			.ops = &clk_branch2_ops,
1918 		},
1919 	},
1920 };
1921 
1922 static struct clk_branch gcc_mdss_axi_clk = {
1923 	.halt_reg = 0x4d080,
1924 	.halt_check = BRANCH_HALT,
1925 	.clkr = {
1926 		.enable_reg = 0x4d080,
1927 		.enable_mask = BIT(0),
1928 		.hw.init = &(struct clk_init_data){
1929 			.name = "gcc_mdss_axi_clk",
1930 			.ops = &clk_branch2_ops,
1931 		},
1932 	},
1933 };
1934 
1935 static struct clk_branch gcc_mdss_byte0_clk = {
1936 	.halt_reg = 0x4d094,
1937 	.halt_check = BRANCH_HALT,
1938 	.clkr = {
1939 		.enable_reg = 0x4d094,
1940 		.enable_mask = BIT(0),
1941 		.hw.init = &(struct clk_init_data){
1942 			.name = "gcc_mdss_byte0_clk",
1943 			.parent_hws = (const struct clk_hw*[]) {
1944 				&byte0_clk_src.clkr.hw,
1945 			},
1946 			.num_parents = 1,
1947 			.flags = CLK_SET_RATE_PARENT,
1948 			.ops = &clk_branch2_ops,
1949 		},
1950 	},
1951 };
1952 
1953 static struct clk_branch gcc_mdss_esc0_clk = {
1954 	.halt_reg = 0x4d098,
1955 	.halt_check = BRANCH_HALT,
1956 	.clkr = {
1957 		.enable_reg = 0x4d098,
1958 		.enable_mask = BIT(0),
1959 		.hw.init = &(struct clk_init_data){
1960 			.name = "gcc_mdss_esc0_clk",
1961 			.parent_hws = (const struct clk_hw*[]) {
1962 				&esc0_clk_src.clkr.hw,
1963 			},
1964 			.num_parents = 1,
1965 			.flags = CLK_SET_RATE_PARENT,
1966 			.ops = &clk_branch2_ops,
1967 		},
1968 	},
1969 };
1970 
1971 static struct clk_branch gcc_mdss_hdmi_app_clk = {
1972 	.halt_reg = 0x4d0d8,
1973 	.halt_check = BRANCH_HALT,
1974 	.clkr = {
1975 		.enable_reg = 0x4d0d8,
1976 		.enable_mask = BIT(0),
1977 		.hw.init = &(struct clk_init_data){
1978 			.name = "gcc_mdss_hdmi_app_clk",
1979 			.parent_hws = (const struct clk_hw*[]) {
1980 				&hdmi_app_clk_src.clkr.hw,
1981 			},
1982 			.num_parents = 1,
1983 			.flags = CLK_SET_RATE_PARENT,
1984 			.ops = &clk_branch2_ops,
1985 		},
1986 	},
1987 };
1988 
1989 static struct clk_branch gcc_mdss_hdmi_pclk_clk = {
1990 	.halt_reg = 0x4d0d4,
1991 	.halt_check = BRANCH_HALT,
1992 	.clkr = {
1993 		.enable_reg = 0x4d0d4,
1994 		.enable_mask = BIT(0),
1995 		.hw.init = &(struct clk_init_data){
1996 			.name = "gcc_mdss_hdmi_pclk_clk",
1997 			.parent_hws = (const struct clk_hw*[]) {
1998 				&hdmi_pclk_clk_src.clkr.hw,
1999 			},
2000 			.num_parents = 1,
2001 			.flags = CLK_SET_RATE_PARENT,
2002 			.ops = &clk_branch2_ops,
2003 		},
2004 	},
2005 };
2006 
2007 static struct clk_branch gcc_mdss_mdp_clk = {
2008 	.halt_reg = 0x4d088,
2009 	.halt_check = BRANCH_HALT,
2010 	.clkr = {
2011 		.enable_reg = 0x4d088,
2012 		.enable_mask = BIT(0),
2013 		.hw.init = &(struct clk_init_data){
2014 			.name = "gcc_mdss_mdp_clk",
2015 			.parent_hws = (const struct clk_hw*[]) {
2016 				&mdp_clk_src.clkr.hw,
2017 			},
2018 			.num_parents = 1,
2019 			.flags = CLK_SET_RATE_PARENT,
2020 			.ops = &clk_branch2_ops,
2021 		},
2022 	},
2023 };
2024 
2025 static struct clk_branch gcc_mdss_pclk0_clk = {
2026 	.halt_reg = 0x4d084,
2027 	.halt_check = BRANCH_HALT,
2028 	.clkr = {
2029 		.enable_reg = 0x4d084,
2030 		.enable_mask = BIT(0),
2031 		.hw.init = &(struct clk_init_data){
2032 			.name = "gcc_mdss_pclk0_clk",
2033 			.parent_hws = (const struct clk_hw*[]) {
2034 				&pclk0_clk_src.clkr.hw,
2035 			},
2036 			.num_parents = 1,
2037 			.flags = CLK_SET_RATE_PARENT,
2038 			.ops = &clk_branch2_ops,
2039 		},
2040 	},
2041 };
2042 
2043 static struct clk_branch gcc_mdss_vsync_clk = {
2044 	.halt_reg = 0x4d090,
2045 	.halt_check = BRANCH_HALT,
2046 	.clkr = {
2047 		.enable_reg = 0x4d090,
2048 		.enable_mask = BIT(0),
2049 		.hw.init = &(struct clk_init_data){
2050 			.name = "gcc_mdss_vsync_clk",
2051 			.parent_hws = (const struct clk_hw*[]) {
2052 				&vsync_clk_src.clkr.hw,
2053 			},
2054 			.num_parents = 1,
2055 			.flags = CLK_SET_RATE_PARENT,
2056 			.ops = &clk_branch2_ops,
2057 		},
2058 	},
2059 };
2060 
2061 static struct clk_branch gcc_oxili_ahb_clk = {
2062 	.halt_reg = 0x59028,
2063 	.halt_check = BRANCH_HALT,
2064 	.clkr = {
2065 		.enable_reg = 0x59028,
2066 		.enable_mask = BIT(0),
2067 		.hw.init = &(struct clk_init_data){
2068 			.name = "gcc_oxili_ahb_clk",
2069 			.ops = &clk_branch2_ops,
2070 		},
2071 	},
2072 };
2073 
2074 static struct clk_branch gcc_oxili_gfx3d_clk = {
2075 	.halt_reg = 0x59020,
2076 	.halt_check = BRANCH_HALT,
2077 	.clkr = {
2078 		.enable_reg = 0x59020,
2079 		.enable_mask = BIT(0),
2080 		.hw.init = &(struct clk_init_data){
2081 			.name = "gcc_oxili_gfx3d_clk",
2082 			.parent_hws = (const struct clk_hw*[]) {
2083 				&gfx3d_clk_src.clkr.hw,
2084 			},
2085 			.num_parents = 1,
2086 			.flags = CLK_SET_RATE_PARENT,
2087 			.ops = &clk_branch2_ops,
2088 		},
2089 	},
2090 };
2091 
2092 static struct clk_branch gcc_pcie_0_aux_clk = {
2093 	.halt_reg = 0x3e014,
2094 	.halt_check = BRANCH_HALT_VOTED,
2095 	.clkr = {
2096 		.enable_reg = 0x45004,
2097 		.enable_mask = BIT(27),
2098 		.hw.init = &(struct clk_init_data){
2099 			.name = "gcc_pcie_0_aux_clk",
2100 			.parent_hws = (const struct clk_hw*[]) {
2101 				&pcie_0_aux_clk_src.clkr.hw,
2102 			},
2103 			.num_parents = 1,
2104 			.flags = CLK_SET_RATE_PARENT,
2105 			.ops = &clk_branch2_ops,
2106 		},
2107 	},
2108 };
2109 
2110 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2111 	.halt_reg = 0x3e008,
2112 	.halt_check = BRANCH_HALT_VOTED,
2113 	.clkr = {
2114 		.enable_reg = 0x45004,
2115 		.enable_mask = BIT(11),
2116 		.hw.init = &(struct clk_init_data){
2117 			.name = "gcc_pcie_0_cfg_ahb_clk",
2118 			.ops = &clk_branch2_ops,
2119 		},
2120 	},
2121 };
2122 
2123 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2124 	.halt_reg = 0x3e018,
2125 	.halt_check = BRANCH_HALT_VOTED,
2126 	.clkr = {
2127 		.enable_reg = 0x45004,
2128 		.enable_mask = BIT(18),
2129 		.hw.init = &(struct clk_init_data){
2130 			.name = "gcc_pcie_0_mstr_axi_clk",
2131 			.ops = &clk_branch2_ops,
2132 		},
2133 	},
2134 };
2135 
2136 static struct clk_branch gcc_pcie_0_pipe_clk = {
2137 	.halt_reg = 0x3e00c,
2138 	.halt_check = BRANCH_HALT_VOTED,
2139 	.clkr = {
2140 		.enable_reg = 0x45004,
2141 		.enable_mask = BIT(28),
2142 		.hw.init = &(struct clk_init_data){
2143 			.name = "gcc_pcie_0_pipe_clk",
2144 			.parent_hws = (const struct clk_hw*[]) {
2145 				&pcie_0_pipe_clk_src.clkr.hw,
2146 			},
2147 			.num_parents = 1,
2148 			.flags = CLK_SET_RATE_PARENT,
2149 			.ops = &clk_branch2_ops,
2150 		},
2151 	},
2152 };
2153 
2154 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2155 	.halt_reg = 0x3e010,
2156 	.halt_check = BRANCH_HALT_VOTED,
2157 	.clkr = {
2158 		.enable_reg = 0x45004,
2159 		.enable_mask = BIT(22),
2160 		.hw.init = &(struct clk_init_data){
2161 			.name = "gcc_pcie_0_slv_axi_clk",
2162 			.ops = &clk_branch2_ops,
2163 		},
2164 	},
2165 };
2166 
2167 static struct clk_branch gcc_pcnoc_usb2_clk = {
2168 	.halt_reg = 0x27008,
2169 	.halt_check = BRANCH_HALT,
2170 	.clkr = {
2171 		.enable_reg = 0x27008,
2172 		.enable_mask = BIT(0),
2173 		.hw.init = &(struct clk_init_data){
2174 			.name = "gcc_pcnoc_usb2_clk",
2175 			.flags = CLK_IS_CRITICAL,
2176 			.ops = &clk_branch2_ops,
2177 		},
2178 	},
2179 };
2180 
2181 static struct clk_branch gcc_pcnoc_usb3_clk = {
2182 	.halt_reg = 0x2700c,
2183 	.halt_check = BRANCH_HALT,
2184 	.clkr = {
2185 		.enable_reg = 0x2700c,
2186 		.enable_mask = BIT(0),
2187 		.hw.init = &(struct clk_init_data){
2188 			.name = "gcc_pcnoc_usb3_clk",
2189 			.flags = CLK_IS_CRITICAL,
2190 			.ops = &clk_branch2_ops,
2191 		},
2192 	},
2193 };
2194 
2195 static struct clk_branch gcc_pdm2_clk = {
2196 	.halt_reg = 0x4400c,
2197 	.halt_check = BRANCH_HALT,
2198 	.clkr = {
2199 		.enable_reg = 0x4400c,
2200 		.enable_mask = BIT(0),
2201 		.hw.init = &(struct clk_init_data){
2202 			.name = "gcc_pdm2_clk",
2203 			.parent_hws = (const struct clk_hw*[]) {
2204 				&pdm2_clk_src.clkr.hw,
2205 			},
2206 			.num_parents = 1,
2207 			.flags = CLK_SET_RATE_PARENT,
2208 			.ops = &clk_branch2_ops,
2209 		},
2210 	},
2211 };
2212 
2213 static struct clk_branch gcc_pdm_ahb_clk = {
2214 	.halt_reg = 0x44004,
2215 	.halt_check = BRANCH_HALT,
2216 	.clkr = {
2217 		.enable_reg = 0x44004,
2218 		.enable_mask = BIT(0),
2219 		.hw.init = &(struct clk_init_data){
2220 			.name = "gcc_pdm_ahb_clk",
2221 			.ops = &clk_branch2_ops,
2222 		},
2223 	},
2224 };
2225 
2226 static struct clk_branch gcc_prng_ahb_clk = {
2227 	.halt_reg = 0x13004,
2228 	.halt_check = BRANCH_HALT_VOTED,
2229 	.clkr = {
2230 		.enable_reg = 0x45004,
2231 		.enable_mask = BIT(8),
2232 		.hw.init = &(struct clk_init_data){
2233 			.name = "gcc_prng_ahb_clk",
2234 			.ops = &clk_branch2_ops,
2235 		},
2236 	},
2237 };
2238 
2239 /* PWM clks do not have XO as parent as src clk is a balance root */
2240 static struct clk_branch gcc_pwm0_xo512_clk = {
2241 	.halt_reg = 0x44018,
2242 	.halt_check = BRANCH_HALT,
2243 	.clkr = {
2244 		.enable_reg = 0x44018,
2245 		.enable_mask = BIT(0),
2246 		.hw.init = &(struct clk_init_data){
2247 			.name = "gcc_pwm0_xo512_clk",
2248 			.ops = &clk_branch2_ops,
2249 		},
2250 	},
2251 };
2252 
2253 static struct clk_branch gcc_pwm1_xo512_clk = {
2254 	.halt_reg = 0x49004,
2255 	.halt_check = BRANCH_HALT,
2256 	.clkr = {
2257 		.enable_reg = 0x49004,
2258 		.enable_mask = BIT(0),
2259 		.hw.init = &(struct clk_init_data){
2260 			.name = "gcc_pwm1_xo512_clk",
2261 			.ops = &clk_branch2_ops,
2262 		},
2263 	},
2264 };
2265 
2266 static struct clk_branch gcc_pwm2_xo512_clk = {
2267 	.halt_reg = 0x4a004,
2268 	.halt_check = BRANCH_HALT,
2269 	.clkr = {
2270 		.enable_reg = 0x4a004,
2271 		.enable_mask = BIT(0),
2272 		.hw.init = &(struct clk_init_data){
2273 			.name = "gcc_pwm2_xo512_clk",
2274 			.ops = &clk_branch2_ops,
2275 		},
2276 	},
2277 };
2278 
2279 static struct clk_branch gcc_qdss_dap_clk = {
2280 	.halt_reg = 0x29084,
2281 	.halt_check = BRANCH_VOTED,
2282 	.clkr = {
2283 		.enable_reg = 0x45004,
2284 		.enable_mask = BIT(21),
2285 		.hw.init = &(struct clk_init_data){
2286 			.name = "gcc_qdss_dap_clk",
2287 			.ops = &clk_branch2_ops,
2288 		},
2289 	},
2290 };
2291 
2292 static struct clk_branch gcc_sdcc1_ahb_clk = {
2293 	.halt_reg = 0x4201c,
2294 	.halt_check = BRANCH_HALT,
2295 	.clkr = {
2296 		.enable_reg = 0x4201c,
2297 		.enable_mask = BIT(0),
2298 		.hw.init = &(struct clk_init_data){
2299 			.name = "gcc_sdcc1_ahb_clk",
2300 			.ops = &clk_branch2_ops,
2301 		},
2302 	},
2303 };
2304 
2305 static struct clk_branch gcc_sdcc1_apps_clk = {
2306 	.halt_reg = 0x42018,
2307 	.halt_check = BRANCH_HALT,
2308 	.clkr = {
2309 		.enable_reg = 0x42018,
2310 		.enable_mask = BIT(0),
2311 		.hw.init = &(struct clk_init_data){
2312 			.name = "gcc_sdcc1_apps_clk",
2313 			.parent_hws = (const struct clk_hw*[]) {
2314 				&sdcc1_apps_clk_src.clkr.hw,
2315 			},
2316 			.num_parents = 1,
2317 			.flags = CLK_SET_RATE_PARENT,
2318 			.ops = &clk_branch2_ops,
2319 		},
2320 	},
2321 };
2322 
2323 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2324 	.halt_reg = 0x5d014,
2325 	.halt_check = BRANCH_HALT,
2326 	.clkr = {
2327 		.enable_reg = 0x5d014,
2328 		.enable_mask = BIT(0),
2329 		.hw.init = &(struct clk_init_data){
2330 			.name = "gcc_sdcc1_ice_core_clk",
2331 			.parent_hws = (const struct clk_hw*[]) {
2332 				&sdcc1_ice_core_clk_src.clkr.hw,
2333 			},
2334 			.num_parents = 1,
2335 			.flags = CLK_SET_RATE_PARENT,
2336 			.ops = &clk_branch2_ops,
2337 		},
2338 	},
2339 };
2340 
2341 static struct clk_branch gcc_cdsp_cfg_ahb_clk = {
2342 	.halt_reg = 0x5e004,
2343 	.halt_check = BRANCH_HALT,
2344 	.clkr = {
2345 		.enable_reg = 0x5e004,
2346 		.enable_mask = BIT(0),
2347 		.hw.init = &(struct clk_init_data) {
2348 			.name = "gcc_cdsp_cfg_ahb_cbcr",
2349 			.ops = &clk_branch2_ops,
2350 		},
2351 	},
2352 };
2353 
2354 static struct clk_branch gcc_sdcc2_ahb_clk = {
2355 	.halt_reg = 0x4301c,
2356 	.halt_check = BRANCH_HALT,
2357 	.clkr = {
2358 		.enable_reg = 0x4301c,
2359 		.enable_mask = BIT(0),
2360 		.hw.init = &(struct clk_init_data){
2361 			.name = "gcc_sdcc2_ahb_clk",
2362 			.ops = &clk_branch2_ops,
2363 		},
2364 	},
2365 };
2366 
2367 static struct clk_branch gcc_sdcc2_apps_clk = {
2368 	.halt_reg = 0x43018,
2369 	.halt_check = BRANCH_HALT,
2370 	.clkr = {
2371 		.enable_reg = 0x43018,
2372 		.enable_mask = BIT(0),
2373 		.hw.init = &(struct clk_init_data){
2374 			.name = "gcc_sdcc2_apps_clk",
2375 			.parent_hws = (const struct clk_hw*[]) {
2376 				&sdcc2_apps_clk_src.clkr.hw,
2377 			},
2378 			.num_parents = 1,
2379 			.flags = CLK_SET_RATE_PARENT,
2380 			.ops = &clk_branch2_ops,
2381 		},
2382 	},
2383 };
2384 
2385 static struct clk_branch gcc_smmu_cfg_clk = {
2386 	.halt_reg = 0x12038,
2387 	.halt_check = BRANCH_VOTED,
2388 	.clkr = {
2389 		.enable_reg = 0x3600C,
2390 		.enable_mask = BIT(12),
2391 		.hw.init = &(struct clk_init_data){
2392 			.name = "gcc_smmu_cfg_clk",
2393 			.ops = &clk_branch2_ops,
2394 		},
2395 	},
2396 };
2397 
2398 static struct clk_branch gcc_sys_noc_usb3_clk = {
2399 	.halt_reg = 0x26014,
2400 	.halt_check = BRANCH_HALT,
2401 	.clkr = {
2402 		.enable_reg = 0x26014,
2403 		.enable_mask = BIT(0),
2404 		.hw.init = &(struct clk_init_data){
2405 			.name = "gcc_sys_noc_usb3_clk",
2406 			.parent_hws = (const struct clk_hw*[]) {
2407 				&usb30_master_clk_src.clkr.hw,
2408 			},
2409 			.num_parents = 1,
2410 			.ops = &clk_branch2_ops,
2411 		},
2412 	},
2413 };
2414 
2415 static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
2416 	.halt_reg = 0x4100C,
2417 	.halt_check = BRANCH_HALT,
2418 	.clkr = {
2419 		.enable_reg = 0x4100C,
2420 		.enable_mask = BIT(0),
2421 		.hw.init = &(struct clk_init_data){
2422 			.name = "gcc_usb_hs_inactivity_timers_clk",
2423 			.ops = &clk_branch2_ops,
2424 		},
2425 	},
2426 };
2427 
2428 static struct clk_branch gcc_usb20_mock_utmi_clk = {
2429 	.halt_reg = 0x41044,
2430 	.halt_check = BRANCH_HALT,
2431 	.clkr = {
2432 		.enable_reg = 0x41044,
2433 		.enable_mask = BIT(0),
2434 		.hw.init = &(struct clk_init_data){
2435 			.name = "gcc_usb20_mock_utmi_clk",
2436 			.parent_hws = (const struct clk_hw*[]) {
2437 				&usb20_mock_utmi_clk_src.clkr.hw,
2438 			},
2439 			.num_parents = 1,
2440 			.flags = CLK_SET_RATE_PARENT,
2441 			.ops = &clk_branch2_ops,
2442 		},
2443 	},
2444 };
2445 
2446 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2447 	.halt_reg = 0x4102c,
2448 	.halt_check = BRANCH_HALT,
2449 	.clkr = {
2450 		.enable_reg = 0x4102c,
2451 		.enable_mask = BIT(0),
2452 		.hw.init = &(struct clk_init_data){
2453 			.name = "gcc_usb2a_phy_sleep_clk",
2454 			.ops = &clk_branch2_ops,
2455 		},
2456 	},
2457 };
2458 
2459 static struct clk_branch gcc_usb30_master_clk = {
2460 	.halt_reg = 0x3900c,
2461 	.halt_check = BRANCH_HALT,
2462 	.clkr = {
2463 		.enable_reg = 0x3900c,
2464 		.enable_mask = BIT(0),
2465 		.hw.init = &(struct clk_init_data){
2466 			.name = "gcc_usb30_master_clk",
2467 			.parent_hws = (const struct clk_hw*[]) {
2468 				&usb30_master_clk_src.clkr.hw,
2469 			},
2470 			.num_parents = 1,
2471 			.flags = CLK_SET_RATE_PARENT,
2472 			.ops = &clk_branch2_ops,
2473 		},
2474 	},
2475 };
2476 
2477 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2478 	.halt_reg = 0x39014,
2479 	.halt_check = BRANCH_HALT,
2480 	.clkr = {
2481 		.enable_reg = 0x39014,
2482 		.enable_mask = BIT(0),
2483 		.hw.init = &(struct clk_init_data){
2484 			.name = "gcc_usb30_mock_utmi_clk",
2485 			.parent_hws = (const struct clk_hw*[]) {
2486 				&usb30_mock_utmi_clk_src.clkr.hw,
2487 			},
2488 			.num_parents = 1,
2489 			.flags = CLK_SET_RATE_PARENT,
2490 			.ops = &clk_branch2_ops,
2491 		},
2492 	},
2493 };
2494 
2495 static struct clk_branch gcc_usb30_sleep_clk = {
2496 	.halt_reg = 0x39010,
2497 	.halt_check = BRANCH_HALT,
2498 	.clkr = {
2499 		.enable_reg = 0x39010,
2500 		.enable_mask = BIT(0),
2501 		.hw.init = &(struct clk_init_data){
2502 			.name = "gcc_usb30_sleep_clk",
2503 			.ops = &clk_branch2_ops,
2504 		},
2505 	},
2506 };
2507 
2508 static struct clk_branch gcc_usb3_phy_aux_clk = {
2509 	.halt_reg = 0x39044,
2510 	.halt_check = BRANCH_HALT,
2511 	.clkr = {
2512 		.enable_reg = 0x39044,
2513 		.enable_mask = BIT(0),
2514 		.hw.init = &(struct clk_init_data){
2515 			.name = "gcc_usb3_phy_aux_clk",
2516 			.parent_hws = (const struct clk_hw*[]) {
2517 				&usb3_phy_aux_clk_src.clkr.hw,
2518 			},
2519 			.num_parents = 1,
2520 			.flags = CLK_SET_RATE_PARENT,
2521 			.ops = &clk_branch2_ops,
2522 		},
2523 	},
2524 };
2525 
2526 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2527 	.halt_check = BRANCH_HALT_SKIP,
2528 	.clkr = {
2529 		.enable_reg = 0x39018,
2530 		.enable_mask = BIT(0),
2531 		.hw.init = &(struct clk_init_data){
2532 			.name = "gcc_usb3_phy_pipe_clk",
2533 			.ops = &clk_branch2_ops,
2534 		},
2535 	},
2536 };
2537 
2538 static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
2539 	.halt_reg = 0x41030,
2540 	.halt_check = BRANCH_HALT,
2541 	.clkr = {
2542 		.enable_reg = 0x41030,
2543 		.enable_mask = BIT(0),
2544 		.hw.init = &(struct clk_init_data){
2545 			.name = "gcc_usb_hs_phy_cfg_ahb_clk",
2546 			.ops = &clk_branch2_ops,
2547 		},
2548 	},
2549 };
2550 
2551 static struct clk_branch gcc_usb_hs_system_clk = {
2552 	.halt_reg = 0x41004,
2553 	.halt_check = BRANCH_HALT,
2554 	.clkr = {
2555 		.enable_reg = 0x41004,
2556 		.enable_mask = BIT(0),
2557 		.hw.init = &(struct clk_init_data){
2558 			.name = "gcc_usb_hs_system_clk",
2559 			.parent_hws = (const struct clk_hw*[]) {
2560 				&usb_hs_system_clk_src.clkr.hw,
2561 			},
2562 			.num_parents = 1,
2563 			.flags = CLK_SET_RATE_PARENT,
2564 			.ops = &clk_branch2_ops,
2565 		},
2566 	},
2567 };
2568 
2569 static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
2570 	.halt_reg = 0x1e004,
2571 	.halt_check = BRANCH_HALT,
2572 	.clkr = {
2573 		.enable_reg = 0x1e004,
2574 		.enable_mask = BIT(0),
2575 		.hw.init = &(struct clk_init_data){
2576 			.name = "gcc_wdsp_q6ss_ahbs_clk",
2577 			.ops = &clk_branch2_ops,
2578 		},
2579 	},
2580 };
2581 
2582 static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
2583 	.halt_reg = 0x1e008,
2584 	.halt_check = BRANCH_HALT,
2585 	.clkr = {
2586 		.enable_reg = 0x1e008,
2587 		.enable_mask = BIT(0),
2588 		.hw.init = &(struct clk_init_data){
2589 			.name = "gcc_wdsp_q6ss_axim_clk",
2590 			.ops = &clk_branch2_ops,
2591 		},
2592 	},
2593 };
2594 
2595 static struct gdsc mdss_gdsc = {
2596 	.gdscr = 0x4d078,
2597 	.pd = {
2598 		.name = "mdss",
2599 	},
2600 	.pwrsts = PWRSTS_OFF_ON,
2601 };
2602 
2603 static struct gdsc oxili_gdsc = {
2604 	.gdscr = 0x5901c,
2605 	.pd = {
2606 		.name = "oxili",
2607 	},
2608 	.pwrsts = PWRSTS_OFF_ON,
2609 };
2610 
2611 static struct clk_hw *gcc_qcs404_hws[] = {
2612 	&cxo.hw,
2613 };
2614 
2615 static struct clk_regmap *gcc_qcs404_clocks[] = {
2616 	[GCC_APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
2617 	[GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC] = &blsp1_qup0_i2c_apps_clk_src.clkr,
2618 	[GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC] = &blsp1_qup0_spi_apps_clk_src.clkr,
2619 	[GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2620 	[GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2621 	[GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2622 	[GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2623 	[GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2624 	[GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2625 	[GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2626 	[GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2627 	[GCC_BLSP1_UART0_APPS_CLK_SRC] = &blsp1_uart0_apps_clk_src.clkr,
2628 	[GCC_BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2629 	[GCC_BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2630 	[GCC_BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2631 	[GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC] = &blsp2_qup0_i2c_apps_clk_src.clkr,
2632 	[GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC] = &blsp2_qup0_spi_apps_clk_src.clkr,
2633 	[GCC_BLSP2_UART0_APPS_CLK_SRC] = &blsp2_uart0_apps_clk_src.clkr,
2634 	[GCC_BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2635 	[GCC_EMAC_CLK_SRC] = &emac_clk_src.clkr,
2636 	[GCC_EMAC_PTP_CLK_SRC] = &emac_ptp_clk_src.clkr,
2637 	[GCC_ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2638 	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
2639 	[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2640 	[GCC_BIMC_CDSP_CLK] = &gcc_bimc_cdsp_clk.clkr,
2641 	[GCC_BIMC_MDSS_CLK] = &gcc_bimc_mdss_clk.clkr,
2642 	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2643 	[GCC_BLSP1_QUP0_I2C_APPS_CLK] = &gcc_blsp1_qup0_i2c_apps_clk.clkr,
2644 	[GCC_BLSP1_QUP0_SPI_APPS_CLK] = &gcc_blsp1_qup0_spi_apps_clk.clkr,
2645 	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2646 	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2647 	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2648 	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2649 	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2650 	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2651 	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2652 	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2653 	[GCC_BLSP1_UART0_APPS_CLK] = &gcc_blsp1_uart0_apps_clk.clkr,
2654 	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2655 	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2656 	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2657 	[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2658 	[GCC_BLSP2_QUP0_I2C_APPS_CLK] = &gcc_blsp2_qup0_i2c_apps_clk.clkr,
2659 	[GCC_BLSP2_QUP0_SPI_APPS_CLK] = &gcc_blsp2_qup0_spi_apps_clk.clkr,
2660 	[GCC_BLSP2_UART0_APPS_CLK] = &gcc_blsp2_uart0_apps_clk.clkr,
2661 	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2662 	[GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr,
2663 	[GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr,
2664 	[GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
2665 	[GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
2666 	[GCC_GENI_IR_S_CLK] = &gcc_geni_ir_s_clk.clkr,
2667 	[GCC_GENI_IR_H_CLK] = &gcc_geni_ir_h_clk.clkr,
2668 	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2669 	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2670 	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2671 	[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
2672 	[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
2673 	[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
2674 	[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
2675 	[GCC_MDSS_HDMI_APP_CLK] = &gcc_mdss_hdmi_app_clk.clkr,
2676 	[GCC_MDSS_HDMI_PCLK_CLK] = &gcc_mdss_hdmi_pclk_clk.clkr,
2677 	[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
2678 	[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
2679 	[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
2680 	[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
2681 	[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
2682 	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2683 	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2684 	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2685 	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2686 	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2687 	[GCC_PCNOC_USB2_CLK] = &gcc_pcnoc_usb2_clk.clkr,
2688 	[GCC_PCNOC_USB3_CLK] = &gcc_pcnoc_usb3_clk.clkr,
2689 	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2690 	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2691 	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2692 	[GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
2693 	[GCC_PWM1_XO512_CLK] = &gcc_pwm1_xo512_clk.clkr,
2694 	[GCC_PWM2_XO512_CLK] = &gcc_pwm2_xo512_clk.clkr,
2695 	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2696 	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2697 	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2698 	[GCC_CDSP_CFG_AHB_CLK] = &gcc_cdsp_cfg_ahb_clk.clkr,
2699 	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2700 	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2701 	[GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr,
2702 	[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
2703 	[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2704 	[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2705 	[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2706 	[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2707 	[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2708 	[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2709 	[GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
2710 	[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2711 	[GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2712 	[GCC_GP1_CLK_SRC] = &gp1_clk_src.clkr,
2713 	[GCC_GP2_CLK_SRC] = &gp2_clk_src.clkr,
2714 	[GCC_GP3_CLK_SRC] = &gp3_clk_src.clkr,
2715 	[GCC_GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2716 	[GCC_GPLL0_AO_OUT_MAIN] = &gpll0_ao_out_main.clkr,
2717 	[GCC_GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
2718 	[GCC_GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2719 	[GCC_GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2720 	[GCC_GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2721 	[GCC_GPLL6] = &gpll6.clkr,
2722 	[GCC_GPLL6_OUT_AUX] = &gpll6_out_aux,
2723 	[GCC_HDMI_APP_CLK_SRC] = &hdmi_app_clk_src.clkr,
2724 	[GCC_HDMI_PCLK_CLK_SRC] = &hdmi_pclk_clk_src.clkr,
2725 	[GCC_MDP_CLK_SRC] = &mdp_clk_src.clkr,
2726 	[GCC_PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2727 	[GCC_PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2728 	[GCC_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2729 	[GCC_PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2730 	[GCC_SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2731 	[GCC_SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
2732 	[GCC_SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2733 	[GCC_USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
2734 	[GCC_USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2735 	[GCC_USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2736 	[GCC_USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2737 	[GCC_USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2738 	[GCC_VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2739 	[GCC_CDSP_BIMC_CLK_SRC] = &cdsp_bimc_clk_src.clkr,
2740 	[GCC_USB_HS_INACTIVITY_TIMERS_CLK] =
2741 			&gcc_usb_hs_inactivity_timers_clk.clkr,
2742 	[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
2743 	[GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
2744 	[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
2745 	[GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
2746 	[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
2747 	[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
2748 	[GCC_CDSP_TBU_CLK] = &gcc_cdsp_tbu_clk.clkr,
2749 	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
2750 	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
2751 	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
2752 	[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
2753 	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
2754 	[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
2755 	[GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
2756 	[GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
2757 	[GCC_WCSS_Q6_AXIM_CLK] =  &gcc_wdsp_q6ss_axim_clk.clkr,
2758 
2759 };
2760 
2761 static struct gdsc *gcc_qcs404_gdscs[] = {
2762 	[MDSS_GDSC] = &mdss_gdsc,
2763 	[OXILI_GDSC] = &oxili_gdsc,
2764 };
2765 
2766 static const struct qcom_reset_map gcc_qcs404_resets[] = {
2767 	[GCC_GENI_IR_BCR] = { 0x0F000 },
2768 	[GCC_CDSP_RESTART] = { 0x18000 },
2769 	[GCC_USB_HS_BCR] = { 0x41000 },
2770 	[GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
2771 	[GCC_QUSB2_PHY_BCR] = { 0x4103c },
2772 	[GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
2773 	[GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
2774 	[GCC_USB3_PHY_BCR] = { 0x39004 },
2775 	[GCC_USB_30_BCR] = { 0x39000 },
2776 	[GCC_USB3PHY_PHY_BCR] = { 0x39008 },
2777 	[GCC_PCIE_0_BCR] = { 0x3e000 },
2778 	[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
2779 	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
2780 	[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
2781 	[GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
2782 	[GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
2783 	[GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
2784 	[GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
2785 	[GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
2786 	[GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
2787 	[GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
2788 	[GCC_EMAC_BCR] = { 0x4e000 },
2789 	[GCC_WDSP_RESTART] = {0x19000},
2790 };
2791 
2792 static const struct regmap_config gcc_qcs404_regmap_config = {
2793 	.reg_bits	= 32,
2794 	.reg_stride	= 4,
2795 	.val_bits	= 32,
2796 	.max_register	= 0x7f000,
2797 	.fast_io	= true,
2798 };
2799 
2800 static const struct qcom_cc_desc gcc_qcs404_desc = {
2801 	.config = &gcc_qcs404_regmap_config,
2802 	.clks = gcc_qcs404_clocks,
2803 	.num_clks = ARRAY_SIZE(gcc_qcs404_clocks),
2804 	.resets = gcc_qcs404_resets,
2805 	.num_resets = ARRAY_SIZE(gcc_qcs404_resets),
2806 	.clk_hws = gcc_qcs404_hws,
2807 	.num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws),
2808 	.gdscs = gcc_qcs404_gdscs,
2809 	.num_gdscs = ARRAY_SIZE(gcc_qcs404_gdscs),
2810 };
2811 
2812 static const struct of_device_id gcc_qcs404_match_table[] = {
2813 	{ .compatible = "qcom,gcc-qcs404" },
2814 	{ }
2815 };
2816 MODULE_DEVICE_TABLE(of, gcc_qcs404_match_table);
2817 
gcc_qcs404_probe(struct platform_device * pdev)2818 static int gcc_qcs404_probe(struct platform_device *pdev)
2819 {
2820 	struct regmap *regmap;
2821 
2822 	regmap = qcom_cc_map(pdev, &gcc_qcs404_desc);
2823 	if (IS_ERR(regmap))
2824 		return PTR_ERR(regmap);
2825 
2826 	clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
2827 
2828 	return qcom_cc_really_probe(&pdev->dev, &gcc_qcs404_desc, regmap);
2829 }
2830 
2831 static struct platform_driver gcc_qcs404_driver = {
2832 	.probe = gcc_qcs404_probe,
2833 	.driver = {
2834 		.name = "gcc-qcs404",
2835 		.of_match_table = gcc_qcs404_match_table,
2836 	},
2837 };
2838 
gcc_qcs404_init(void)2839 static int __init gcc_qcs404_init(void)
2840 {
2841 	return platform_driver_register(&gcc_qcs404_driver);
2842 }
2843 core_initcall(gcc_qcs404_init);
2844 
gcc_qcs404_exit(void)2845 static void __exit gcc_qcs404_exit(void)
2846 {
2847 	platform_driver_unregister(&gcc_qcs404_driver);
2848 }
2849 module_exit(gcc_qcs404_exit);
2850 
2851 MODULE_DESCRIPTION("Qualcomm GCC QCS404 Driver");
2852 MODULE_LICENSE("GPL v2");
2853