1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/interconnect-provider.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12
13 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
14 #include <dt-bindings/interconnect/qcom,ipq5332.h>
15
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
20 #include "clk-regmap-divider.h"
21 #include "clk-regmap-mux.h"
22 #include "clk-regmap-phy-mux.h"
23 #include "reset.h"
24
25 enum {
26 DT_XO,
27 DT_SLEEP_CLK,
28 DT_PCIE_2LANE_PHY_PIPE_CLK,
29 DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
30 DT_USB_PCIE_WRAPPER_PIPE_CLK,
31 };
32
33 enum {
34 P_PCIE3X2_PIPE,
35 P_PCIE3X1_0_PIPE,
36 P_PCIE3X1_1_PIPE,
37 P_USB3PHY_0_PIPE,
38 P_CORE_BI_PLL_TEST_SE,
39 P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
40 P_GPLL0_OUT_AUX,
41 P_GPLL0_OUT_MAIN,
42 P_GPLL2_OUT_AUX,
43 P_GPLL2_OUT_MAIN,
44 P_GPLL4_OUT_AUX,
45 P_GPLL4_OUT_MAIN,
46 P_SLEEP_CLK,
47 P_XO,
48 };
49
50 static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
51
52 static struct clk_alpha_pll gpll0_main = {
53 .offset = 0x20000,
54 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
55 .clkr = {
56 .enable_reg = 0xb000,
57 .enable_mask = BIT(0),
58 .hw.init = &(const struct clk_init_data) {
59 .name = "gpll0_main",
60 .parent_data = &gcc_parent_data_xo,
61 .num_parents = 1,
62 .ops = &clk_alpha_pll_stromer_ops,
63 },
64 },
65 };
66
67 static struct clk_fixed_factor gpll0_div2 = {
68 .mult = 1,
69 .div = 2,
70 .hw.init = &(struct clk_init_data) {
71 .name = "gpll0_div2",
72 .parent_hws = (const struct clk_hw *[]) {
73 &gpll0_main.clkr.hw },
74 .num_parents = 1,
75 .ops = &clk_fixed_factor_ops,
76 },
77 };
78
79 static struct clk_alpha_pll_postdiv gpll0 = {
80 .offset = 0x20000,
81 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
82 .width = 4,
83 .clkr.hw.init = &(struct clk_init_data) {
84 .name = "gpll0",
85 .parent_hws = (const struct clk_hw *[]) {
86 &gpll0_main.clkr.hw },
87 .num_parents = 1,
88 .ops = &clk_alpha_pll_postdiv_ro_ops,
89 },
90 };
91
92 static struct clk_alpha_pll gpll2_main = {
93 .offset = 0x21000,
94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
95 .clkr = {
96 .enable_reg = 0xb000,
97 .enable_mask = BIT(1),
98 .hw.init = &(const struct clk_init_data) {
99 .name = "gpll2",
100 .parent_data = &gcc_parent_data_xo,
101 .num_parents = 1,
102 .ops = &clk_alpha_pll_stromer_ops,
103 },
104 },
105 };
106
107 static struct clk_alpha_pll_postdiv gpll2 = {
108 .offset = 0x21000,
109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
110 .width = 4,
111 .clkr.hw.init = &(struct clk_init_data) {
112 .name = "gpll2_main",
113 .parent_hws = (const struct clk_hw *[]) {
114 &gpll2_main.clkr.hw },
115 .num_parents = 1,
116 .ops = &clk_alpha_pll_postdiv_ro_ops,
117 },
118 };
119
120 static struct clk_alpha_pll gpll4_main = {
121 .offset = 0x22000,
122 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
123 .clkr = {
124 .enable_reg = 0xb000,
125 .enable_mask = BIT(2),
126 .hw.init = &(const struct clk_init_data) {
127 .name = "gpll4_main",
128 .parent_data = &gcc_parent_data_xo,
129 .num_parents = 1,
130 .ops = &clk_alpha_pll_stromer_ops,
131 },
132 },
133 };
134
135 static struct clk_alpha_pll_postdiv gpll4 = {
136 .offset = 0x22000,
137 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
138 .width = 4,
139 .clkr.hw.init = &(struct clk_init_data) {
140 .name = "gpll4",
141 .parent_hws = (const struct clk_hw *[]) {
142 &gpll4_main.clkr.hw },
143 .num_parents = 1,
144 .ops = &clk_alpha_pll_postdiv_ro_ops,
145 },
146 };
147
148 static const struct parent_map gcc_parent_map_xo[] = {
149 { P_XO, 0 },
150 };
151
152 static const struct parent_map gcc_parent_map_0[] = {
153 { P_XO, 0 },
154 { P_GPLL0_OUT_MAIN, 1 },
155 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
156 };
157
158 static const struct clk_parent_data gcc_parent_data_0[] = {
159 { .index = DT_XO },
160 { .hw = &gpll0.clkr.hw },
161 { .hw = &gpll0_div2.hw },
162 };
163
164 static const struct parent_map gcc_parent_map_1[] = {
165 { P_XO, 0 },
166 { P_GPLL0_OUT_MAIN, 1 },
167 };
168
169 static const struct clk_parent_data gcc_parent_data_1[] = {
170 { .index = DT_XO },
171 { .hw = &gpll0.clkr.hw },
172 };
173
174 static const struct parent_map gcc_parent_map_2[] = {
175 { P_XO, 0 },
176 { P_GPLL0_OUT_MAIN, 1 },
177 { P_GPLL4_OUT_MAIN, 2 },
178 };
179
180 static const struct clk_parent_data gcc_parent_data_2[] = {
181 { .index = DT_XO },
182 { .hw = &gpll0.clkr.hw },
183 { .hw = &gpll4.clkr.hw },
184 };
185
186 static const struct parent_map gcc_parent_map_3[] = {
187 { P_XO, 0 },
188 { P_GPLL0_OUT_MAIN, 1 },
189 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
190 { P_SLEEP_CLK, 6 },
191 };
192
193 static const struct clk_parent_data gcc_parent_data_3[] = {
194 { .index = DT_XO },
195 { .hw = &gpll0.clkr.hw },
196 { .hw = &gpll0_div2.hw },
197 { .index = DT_SLEEP_CLK },
198 };
199
200 static const struct parent_map gcc_parent_map_4[] = {
201 { P_XO, 0 },
202 { P_GPLL4_OUT_MAIN, 1 },
203 { P_GPLL0_OUT_AUX, 2 },
204 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
205 };
206
207 static const struct clk_parent_data gcc_parent_data_4[] = {
208 { .index = DT_XO },
209 { .hw = &gpll4.clkr.hw },
210 { .hw = &gpll0.clkr.hw },
211 { .hw = &gpll0_div2.hw },
212 };
213
214 static const struct parent_map gcc_parent_map_5[] = {
215 { P_XO, 0 },
216 { P_GPLL0_OUT_MAIN, 1 },
217 { P_GPLL0_OUT_AUX, 2 },
218 { P_SLEEP_CLK, 6 },
219 };
220
221 static const struct clk_parent_data gcc_parent_data_5[] = {
222 { .index = DT_XO },
223 { .hw = &gpll0.clkr.hw },
224 { .hw = &gpll0.clkr.hw },
225 { .index = DT_SLEEP_CLK },
226 };
227
228 static const struct parent_map gcc_parent_map_6[] = {
229 { P_XO, 0 },
230 { P_GPLL0_OUT_MAIN, 1 },
231 { P_GPLL2_OUT_AUX, 2 },
232 { P_GPLL4_OUT_AUX, 3 },
233 { P_SLEEP_CLK, 6 },
234 };
235
236 static const struct clk_parent_data gcc_parent_data_6[] = {
237 { .index = DT_XO },
238 { .hw = &gpll0.clkr.hw },
239 { .hw = &gpll2.clkr.hw },
240 { .hw = &gpll4.clkr.hw },
241 { .index = DT_SLEEP_CLK },
242 };
243
244 static const struct parent_map gcc_parent_map_7[] = {
245 { P_XO, 0 },
246 { P_GPLL0_OUT_MAIN, 1 },
247 { P_GPLL2_OUT_AUX, 2 },
248 };
249
250 static const struct clk_parent_data gcc_parent_data_7[] = {
251 { .index = DT_XO },
252 { .hw = &gpll0.clkr.hw },
253 { .hw = &gpll2.clkr.hw },
254 };
255
256 static const struct parent_map gcc_parent_map_8[] = {
257 { P_XO, 0 },
258 { P_GPLL0_OUT_MAIN, 1 },
259 { P_GPLL2_OUT_MAIN, 2 },
260 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
261 };
262
263 static const struct clk_parent_data gcc_parent_data_8[] = {
264 { .index = DT_XO },
265 { .hw = &gpll0.clkr.hw },
266 { .hw = &gpll2.clkr.hw },
267 { .hw = &gpll0_div2.hw },
268 };
269
270 static const struct parent_map gcc_parent_map_9[] = {
271 { P_SLEEP_CLK, 6 },
272 };
273
274 static const struct clk_parent_data gcc_parent_data_9[] = {
275 { .index = DT_SLEEP_CLK },
276 };
277
278 static const struct parent_map gcc_parent_map_10[] = {
279 { P_XO, 0 },
280 { P_GPLL0_OUT_MAIN, 1 },
281 { P_GPLL4_OUT_MAIN, 2 },
282 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 },
283 };
284
285 static const struct clk_parent_data gcc_parent_data_10[] = {
286 { .index = DT_XO },
287 { .hw = &gpll0.clkr.hw },
288 { .hw = &gpll4.clkr.hw },
289 { .hw = &gpll0_div2.hw },
290 };
291
292 static const struct parent_map gcc_parent_map_11[] = {
293 { P_XO, 0 },
294 { P_GPLL0_OUT_AUX, 2 },
295 { P_SLEEP_CLK, 6 },
296 };
297
298 static const struct clk_parent_data gcc_parent_data_11[] = {
299 { .index = DT_XO },
300 { .hw = &gpll0.clkr.hw },
301 { .index = DT_SLEEP_CLK },
302 };
303
304 static const struct parent_map gcc_parent_map_12[] = {
305 { P_XO, 0 },
306 { P_GPLL4_OUT_AUX, 1 },
307 { P_GPLL0_OUT_MAIN, 3 },
308 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
309 };
310
311 static const struct clk_parent_data gcc_parent_data_12[] = {
312 { .index = DT_XO },
313 { .hw = &gpll4.clkr.hw },
314 { .hw = &gpll0.clkr.hw },
315 { .hw = &gpll0_div2.hw },
316 };
317
318 static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = {
319 F(24000000, P_XO, 1, 0, 0),
320 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
321 { }
322 };
323
324 static struct clk_rcg2 gcc_adss_pwm_clk_src = {
325 .cmd_rcgr = 0x1c004,
326 .mnd_width = 0,
327 .hid_width = 5,
328 .parent_map = gcc_parent_map_1,
329 .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
330 .clkr.hw.init = &(const struct clk_init_data) {
331 .name = "gcc_adss_pwm_clk_src",
332 .parent_data = gcc_parent_data_1,
333 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
334 .ops = &clk_rcg2_ops,
335 },
336 };
337
338 static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = {
339 F(480000000, P_GPLL4_OUT_AUX, 2.5, 0, 0),
340 F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
341 { }
342 };
343
344 static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
345 F(960000, P_XO, 1, 1, 25),
346 F(4800000, P_XO, 5, 0, 0),
347 F(9600000, P_XO, 2.5, 0, 0),
348 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
349 F(24000000, P_XO, 1, 0, 0),
350 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
351 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
352 { }
353 };
354
355 static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
356 .cmd_rcgr = 0x2004,
357 .mnd_width = 8,
358 .hid_width = 5,
359 .parent_map = gcc_parent_map_0,
360 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
361 .clkr.hw.init = &(const struct clk_init_data) {
362 .name = "gcc_blsp1_qup1_spi_apps_clk_src",
363 .parent_data = gcc_parent_data_0,
364 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
365 .ops = &clk_rcg2_ops,
366 },
367 };
368
369 static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
370 .cmd_rcgr = 0x3004,
371 .mnd_width = 8,
372 .hid_width = 5,
373 .parent_map = gcc_parent_map_0,
374 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
375 .clkr.hw.init = &(const struct clk_init_data) {
376 .name = "gcc_blsp1_qup2_spi_apps_clk_src",
377 .parent_data = gcc_parent_data_0,
378 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
379 .ops = &clk_rcg2_ops,
380 },
381 };
382
383 static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
384 .cmd_rcgr = 0x4004,
385 .mnd_width = 8,
386 .hid_width = 5,
387 .parent_map = gcc_parent_map_0,
388 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
389 .clkr.hw.init = &(const struct clk_init_data) {
390 .name = "gcc_blsp1_qup3_spi_apps_clk_src",
391 .parent_data = gcc_parent_data_0,
392 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
393 .ops = &clk_rcg2_ops,
394 },
395 };
396
397 static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
398 F(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625),
399 F(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625),
400 F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625),
401 F(24000000, P_XO, 1, 0, 0),
402 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
403 F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
404 F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
405 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
406 F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
407 F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
408 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
409 F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
410 F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
411 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
412 { }
413 };
414
415 static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
416 .cmd_rcgr = 0x202c,
417 .mnd_width = 16,
418 .hid_width = 5,
419 .parent_map = gcc_parent_map_0,
420 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
421 .clkr.hw.init = &(const struct clk_init_data) {
422 .name = "gcc_blsp1_uart1_apps_clk_src",
423 .parent_data = gcc_parent_data_0,
424 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
425 .ops = &clk_rcg2_ops,
426 },
427 };
428
429 static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
430 .cmd_rcgr = 0x302c,
431 .mnd_width = 16,
432 .hid_width = 5,
433 .parent_map = gcc_parent_map_0,
434 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
435 .clkr.hw.init = &(const struct clk_init_data) {
436 .name = "gcc_blsp1_uart2_apps_clk_src",
437 .parent_data = gcc_parent_data_0,
438 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
439 .ops = &clk_rcg2_ops,
440 },
441 };
442
443 static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
444 .cmd_rcgr = 0x402c,
445 .mnd_width = 16,
446 .hid_width = 5,
447 .parent_map = gcc_parent_map_0,
448 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
449 .clkr.hw.init = &(const struct clk_init_data) {
450 .name = "gcc_blsp1_uart3_apps_clk_src",
451 .parent_data = gcc_parent_data_0,
452 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
453 .ops = &clk_rcg2_ops,
454 },
455 };
456
457 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
458 F(24000000, P_XO, 1, 0, 0),
459 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
460 { }
461 };
462
463 static struct clk_rcg2 gcc_gp1_clk_src = {
464 .cmd_rcgr = 0x8004,
465 .mnd_width = 8,
466 .hid_width = 5,
467 .parent_map = gcc_parent_map_3,
468 .freq_tbl = ftbl_gcc_gp1_clk_src,
469 .clkr.hw.init = &(const struct clk_init_data) {
470 .name = "gcc_gp1_clk_src",
471 .parent_data = gcc_parent_data_3,
472 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
473 .ops = &clk_rcg2_ops,
474 },
475 };
476
477 static struct clk_rcg2 gcc_gp2_clk_src = {
478 .cmd_rcgr = 0x9004,
479 .mnd_width = 8,
480 .hid_width = 5,
481 .parent_map = gcc_parent_map_3,
482 .freq_tbl = ftbl_gcc_gp1_clk_src,
483 .clkr.hw.init = &(const struct clk_init_data) {
484 .name = "gcc_gp2_clk_src",
485 .parent_data = gcc_parent_data_3,
486 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
487 .ops = &clk_rcg2_ops,
488 },
489 };
490
491 static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = {
492 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
493 { }
494 };
495
496 static struct clk_rcg2 gcc_lpass_sway_clk_src = {
497 .cmd_rcgr = 0x27004,
498 .mnd_width = 0,
499 .hid_width = 5,
500 .parent_map = gcc_parent_map_1,
501 .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
502 .clkr.hw.init = &(const struct clk_init_data) {
503 .name = "gcc_lpass_sway_clk_src",
504 .parent_data = gcc_parent_data_1,
505 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
506 .ops = &clk_rcg2_ops,
507 },
508 };
509
510 static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = {
511 F(24000000, P_XO, 1, 0, 0),
512 { }
513 };
514
515 static struct clk_rcg2 gcc_nss_ts_clk_src = {
516 .cmd_rcgr = 0x17088,
517 .mnd_width = 0,
518 .hid_width = 5,
519 .parent_map = gcc_parent_map_xo,
520 .freq_tbl = ftbl_gcc_nss_ts_clk_src,
521 .clkr.hw.init = &(const struct clk_init_data) {
522 .name = "gcc_nss_ts_clk_src",
523 .parent_data = &gcc_parent_data_xo,
524 .num_parents = 1,
525 .ops = &clk_rcg2_ops,
526 },
527 };
528
529 static const struct freq_tbl ftbl_gcc_pcie3x1_0_axi_clk_src[] = {
530 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
531 { }
532 };
533
534 static struct clk_rcg2 gcc_pcie3x1_0_axi_clk_src = {
535 .cmd_rcgr = 0x29018,
536 .mnd_width = 0,
537 .hid_width = 5,
538 .parent_map = gcc_parent_map_2,
539 .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
540 .clkr.hw.init = &(const struct clk_init_data) {
541 .name = "gcc_pcie3x1_0_axi_clk_src",
542 .parent_data = gcc_parent_data_2,
543 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
544 .ops = &clk_rcg2_ops,
545 },
546 };
547
548 static struct clk_rcg2 gcc_pcie3x1_0_rchg_clk_src = {
549 .cmd_rcgr = 0x2907c,
550 .hid_width = 5,
551 .parent_map = gcc_parent_map_0,
552 .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
553 .clkr.hw.init = &(const struct clk_init_data) {
554 .name = "gcc_pcie3x1_0_rchg_clk_src",
555 .parent_data = gcc_parent_data_0,
556 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
557 .ops = &clk_rcg2_ops,
558 },
559 };
560
561 static struct clk_branch gcc_pcie3x1_0_rchg_clk = {
562 .halt_reg = 0x2907c,
563 .clkr = {
564 .enable_reg = 0x2907c,
565 .enable_mask = BIT(1),
566 .hw.init = &(struct clk_init_data) {
567 .name = "gcc_pcie3x1_0_rchg_clk",
568 .parent_hws = (const struct clk_hw *[]) {
569 &gcc_pcie3x1_0_rchg_clk_src.clkr.hw },
570 .num_parents = 1,
571 .flags = CLK_SET_RATE_PARENT,
572 .ops = &clk_branch2_ops,
573 },
574 },
575 };
576
577 static struct clk_rcg2 gcc_pcie3x1_1_axi_clk_src = {
578 .cmd_rcgr = 0x2a004,
579 .mnd_width = 0,
580 .hid_width = 5,
581 .parent_map = gcc_parent_map_2,
582 .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
583 .clkr.hw.init = &(const struct clk_init_data) {
584 .name = "gcc_pcie3x1_1_axi_clk_src",
585 .parent_data = gcc_parent_data_2,
586 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
587 .ops = &clk_rcg2_ops,
588 },
589 };
590
591 static struct clk_rcg2 gcc_pcie3x1_1_rchg_clk_src = {
592 .cmd_rcgr = 0x2a078,
593 .hid_width = 5,
594 .parent_map = gcc_parent_map_0,
595 .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
596 .clkr.hw.init = &(const struct clk_init_data) {
597 .name = "gcc_pcie3x1_1_rchg_clk_src",
598 .parent_data = gcc_parent_data_0,
599 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
600 .ops = &clk_rcg2_ops,
601 },
602 };
603
604 static struct clk_branch gcc_pcie3x1_1_rchg_clk = {
605 .halt_reg = 0x2a078,
606 .clkr = {
607 .enable_reg = 0x2a078,
608 .enable_mask = BIT(1),
609 .hw.init = &(struct clk_init_data) {
610 .name = "gcc_pcie3x1_1_rchg_clk",
611 .parent_hws = (const struct clk_hw *[]) {
612 &gcc_pcie3x1_1_rchg_clk_src.clkr.hw },
613 .num_parents = 1,
614 .flags = CLK_SET_RATE_PARENT,
615 .ops = &clk_branch2_ops,
616 },
617 },
618 };
619
620 static const struct freq_tbl ftbl_gcc_pcie3x2_axi_m_clk_src[] = {
621 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
622 { }
623 };
624
625 static struct clk_rcg2 gcc_pcie3x2_axi_m_clk_src = {
626 .cmd_rcgr = 0x28018,
627 .mnd_width = 0,
628 .hid_width = 5,
629 .parent_map = gcc_parent_map_2,
630 .freq_tbl = ftbl_gcc_pcie3x2_axi_m_clk_src,
631 .clkr.hw.init = &(const struct clk_init_data) {
632 .name = "gcc_pcie3x2_axi_m_clk_src",
633 .parent_data = gcc_parent_data_2,
634 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
635 .ops = &clk_rcg2_ops,
636 },
637 };
638
639 static struct clk_rcg2 gcc_pcie3x2_axi_s_clk_src = {
640 .cmd_rcgr = 0x28084,
641 .mnd_width = 0,
642 .hid_width = 5,
643 .parent_map = gcc_parent_map_2,
644 .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
645 .clkr.hw.init = &(const struct clk_init_data) {
646 .name = "gcc_pcie3x2_axi_s_clk_src",
647 .parent_data = gcc_parent_data_2,
648 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
649 .ops = &clk_rcg2_ops,
650 },
651 };
652
653 static struct clk_rcg2 gcc_pcie3x2_rchg_clk_src = {
654 .cmd_rcgr = 0x28078,
655 .mnd_width = 0,
656 .hid_width = 5,
657 .parent_map = gcc_parent_map_0,
658 .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
659 .clkr.hw.init = &(const struct clk_init_data) {
660 .name = "gcc_pcie3x2_rchg_clk_src",
661 .parent_data = gcc_parent_data_0,
662 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
663 .ops = &clk_rcg2_ops,
664 },
665 };
666
667 static struct clk_branch gcc_pcie3x2_rchg_clk = {
668 .halt_reg = 0x28078,
669 .clkr = {
670 .enable_reg = 0x28078,
671 .enable_mask = BIT(1),
672 .hw.init = &(struct clk_init_data) {
673 .name = "gcc_pcie3x2_rchg_clk",
674 .parent_hws = (const struct clk_hw *[]) {
675 &gcc_pcie3x2_rchg_clk_src.clkr.hw },
676 .num_parents = 1,
677 .flags = CLK_SET_RATE_PARENT,
678 .ops = &clk_branch2_ops,
679 },
680 },
681 };
682
683 static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
684 F(2000000, P_XO, 12, 0, 0),
685 { }
686 };
687
688 static struct clk_rcg2 gcc_pcie_aux_clk_src = {
689 .cmd_rcgr = 0x28004,
690 .mnd_width = 16,
691 .hid_width = 5,
692 .parent_map = gcc_parent_map_5,
693 .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
694 .clkr.hw.init = &(const struct clk_init_data) {
695 .name = "gcc_pcie_aux_clk_src",
696 .parent_data = gcc_parent_data_5,
697 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
698 .ops = &clk_rcg2_ops,
699 },
700 };
701
702 static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = {
703 .reg = 0x28064,
704 .clkr = {
705 .hw.init = &(struct clk_init_data) {
706 .name = "gcc_pcie3x2_pipe_clk_src",
707 .parent_data = &(const struct clk_parent_data) {
708 .index = DT_PCIE_2LANE_PHY_PIPE_CLK,
709 },
710 .num_parents = 1,
711 .ops = &clk_regmap_phy_mux_ops,
712 },
713 },
714 };
715
716 static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
717 .reg = 0x29064,
718 .clkr = {
719 .hw.init = &(struct clk_init_data) {
720 .name = "gcc_pcie3x1_0_pipe_clk_src",
721 .parent_data = &(const struct clk_parent_data) {
722 .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
723 },
724 .num_parents = 1,
725 .ops = &clk_regmap_phy_mux_ops,
726 },
727 },
728 };
729
730 static struct clk_regmap_phy_mux gcc_pcie3x1_1_pipe_clk_src = {
731 .reg = 0x2a064,
732 .clkr = {
733 .hw.init = &(struct clk_init_data) {
734 .name = "gcc_pcie3x1_1_pipe_clk_src",
735 .parent_data = &(const struct clk_parent_data) {
736 .index = DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
737 },
738 .num_parents = 1,
739 .ops = &clk_regmap_phy_mux_ops,
740 },
741 },
742 };
743
744 static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = {
745 F(24000000, P_XO, 1, 0, 0),
746 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
747 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
748 { }
749 };
750
751 static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = {
752 .cmd_rcgr = 0x31004,
753 .mnd_width = 0,
754 .hid_width = 5,
755 .parent_map = gcc_parent_map_0,
756 .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src,
757 .clkr.hw.init = &(const struct clk_init_data) {
758 .name = "gcc_pcnoc_bfdcd_clk_src",
759 .parent_data = gcc_parent_data_0,
760 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
761 .ops = &clk_rcg2_ops,
762 },
763 };
764
765 static struct clk_rcg2 gcc_q6_axim_clk_src = {
766 .cmd_rcgr = 0x25004,
767 .mnd_width = 0,
768 .hid_width = 5,
769 .parent_map = gcc_parent_map_6,
770 .freq_tbl = ftbl_gcc_apss_axi_clk_src,
771 .clkr.hw.init = &(const struct clk_init_data) {
772 .name = "gcc_q6_axim_clk_src",
773 .parent_data = gcc_parent_data_6,
774 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
775 .ops = &clk_rcg2_ops,
776 },
777 };
778
779 static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = {
780 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
781 { }
782 };
783
784 static struct clk_rcg2 gcc_qdss_at_clk_src = {
785 .cmd_rcgr = 0x2d004,
786 .mnd_width = 0,
787 .hid_width = 5,
788 .parent_map = gcc_parent_map_4,
789 .freq_tbl = ftbl_gcc_qdss_at_clk_src,
790 .clkr.hw.init = &(const struct clk_init_data) {
791 .name = "gcc_qdss_at_clk_src",
792 .parent_data = gcc_parent_data_4,
793 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
794 .ops = &clk_rcg2_ops,
795 },
796 };
797
798 static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = {
799 F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
800 { }
801 };
802
803 static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
804 .cmd_rcgr = 0x2d01c,
805 .mnd_width = 0,
806 .hid_width = 5,
807 .parent_map = gcc_parent_map_4,
808 .freq_tbl = ftbl_gcc_qdss_tsctr_clk_src,
809 .clkr.hw.init = &(const struct clk_init_data) {
810 .name = "gcc_qdss_tsctr_clk_src",
811 .parent_data = gcc_parent_data_4,
812 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
813 .ops = &clk_rcg2_ops,
814 },
815 };
816
817 static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
818 .mult = 1,
819 .div = 2,
820 .hw.init = &(struct clk_init_data) {
821 .name = "gcc_qdss_tsctr_div2_clk_src",
822 .parent_hws = (const struct clk_hw *[]) {
823 &gcc_qdss_tsctr_clk_src.clkr.hw },
824 .num_parents = 1,
825 .flags = CLK_SET_RATE_PARENT,
826 .ops = &clk_fixed_factor_ops,
827 },
828 };
829
830 static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {
831 .mult = 1,
832 .div = 3,
833 .hw.init = &(struct clk_init_data) {
834 .name = "gcc_qdss_tsctr_div3_clk_src",
835 .parent_hws = (const struct clk_hw *[]) {
836 &gcc_qdss_tsctr_clk_src.clkr.hw },
837 .num_parents = 1,
838 .ops = &clk_fixed_factor_ops,
839 },
840 };
841
842 static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {
843 .mult = 1,
844 .div = 4,
845 .hw.init = &(struct clk_init_data) {
846 .name = "gcc_qdss_tsctr_div4_clk_src",
847 .parent_hws = (const struct clk_hw *[]) {
848 &gcc_qdss_tsctr_clk_src.clkr.hw },
849 .num_parents = 1,
850 .ops = &clk_fixed_factor_ops,
851 },
852 };
853
854 static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {
855 .mult = 1,
856 .div = 8,
857 .hw.init = &(struct clk_init_data) {
858 .name = "gcc_qdss_tsctr_div8_clk_src",
859 .parent_hws = (const struct clk_hw *[]) {
860 &gcc_qdss_tsctr_clk_src.clkr.hw },
861 .num_parents = 1,
862 .ops = &clk_fixed_factor_ops,
863 },
864 };
865
866 static struct clk_fixed_factor gcc_qdss_tsctr_div16_clk_src = {
867 .mult = 1,
868 .div = 16,
869 .hw.init = &(struct clk_init_data) {
870 .name = "gcc_qdss_tsctr_div16_clk_src",
871 .parent_hws = (const struct clk_hw *[]) {
872 &gcc_qdss_tsctr_clk_src.clkr.hw },
873 .num_parents = 1,
874 .ops = &clk_fixed_factor_ops,
875 },
876 };
877
878 static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = {
879 F(24000000, P_XO, 1, 0, 0),
880 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
881 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
882 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
883 { }
884 };
885
886 static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
887 .cmd_rcgr = 0x32004,
888 .mnd_width = 0,
889 .hid_width = 5,
890 .parent_map = gcc_parent_map_7,
891 .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
892 .clkr.hw.init = &(const struct clk_init_data) {
893 .name = "gcc_qpic_io_macro_clk_src",
894 .parent_data = gcc_parent_data_7,
895 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
896 .ops = &clk_rcg2_ops,
897 },
898 };
899
900 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
901 F(143713, P_XO, 1, 1, 167),
902 F(400000, P_XO, 1, 1, 60),
903 F(24000000, P_XO, 1, 0, 0),
904 F(48000000, P_GPLL2_OUT_MAIN, 12, 1, 2),
905 F(96000000, P_GPLL2_OUT_MAIN, 12, 0, 0),
906 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
907 F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
908 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
909 { }
910 };
911
912 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
913 .cmd_rcgr = 0x33004,
914 .mnd_width = 8,
915 .hid_width = 5,
916 .parent_map = gcc_parent_map_8,
917 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
918 .clkr.hw.init = &(const struct clk_init_data) {
919 .name = "gcc_sdcc1_apps_clk_src",
920 .parent_data = gcc_parent_data_8,
921 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
922 .ops = &clk_rcg2_floor_ops,
923 },
924 };
925
926 static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = {
927 F(32000, P_SLEEP_CLK, 1, 0, 0),
928 { }
929 };
930
931 static struct clk_rcg2 gcc_sleep_clk_src = {
932 .cmd_rcgr = 0x3400c,
933 .mnd_width = 0,
934 .hid_width = 5,
935 .parent_map = gcc_parent_map_9,
936 .freq_tbl = ftbl_gcc_sleep_clk_src,
937 .clkr.hw.init = &(const struct clk_init_data) {
938 .name = "gcc_sleep_clk_src",
939 .parent_data = gcc_parent_data_9,
940 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
941 .ops = &clk_rcg2_ops,
942 },
943 };
944
945 static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = {
946 F(24000000, P_XO, 1, 0, 0),
947 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
948 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
949 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
950 { }
951 };
952
953 static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
954 .cmd_rcgr = 0x2e004,
955 .mnd_width = 0,
956 .hid_width = 5,
957 .parent_map = gcc_parent_map_10,
958 .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
959 .clkr.hw.init = &(const struct clk_init_data) {
960 .name = "gcc_system_noc_bfdcd_clk_src",
961 .parent_data = gcc_parent_data_10,
962 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
963 .ops = &clk_rcg2_ops,
964 },
965 };
966
967 static struct clk_fixed_factor gcc_system_noc_bfdcd_div2_clk_src = {
968 .mult = 1,
969 .div = 2,
970 .hw.init = &(struct clk_init_data) {
971 .name = "gcc_system_noc_bfdcd_div2_clk_src",
972 .parent_hws = (const struct clk_hw *[]) {
973 &gcc_system_noc_bfdcd_clk_src.clkr.hw },
974 .num_parents = 1,
975 .ops = &clk_fixed_factor_ops,
976 .flags = CLK_SET_RATE_PARENT,
977 },
978 };
979
980 static struct clk_rcg2 gcc_uniphy_sys_clk_src = {
981 .cmd_rcgr = 0x16004,
982 .mnd_width = 0,
983 .hid_width = 5,
984 .parent_map = gcc_parent_map_xo,
985 .freq_tbl = ftbl_gcc_nss_ts_clk_src,
986 .clkr.hw.init = &(const struct clk_init_data) {
987 .name = "gcc_uniphy_sys_clk_src",
988 .parent_data = &gcc_parent_data_xo,
989 .num_parents = 1,
990 .ops = &clk_rcg2_ops,
991 },
992 };
993
994 static struct clk_rcg2 gcc_usb0_aux_clk_src = {
995 .cmd_rcgr = 0x2c018,
996 .mnd_width = 16,
997 .hid_width = 5,
998 .parent_map = gcc_parent_map_11,
999 .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
1000 .clkr.hw.init = &(const struct clk_init_data) {
1001 .name = "gcc_usb0_aux_clk_src",
1002 .parent_data = gcc_parent_data_11,
1003 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
1004 .ops = &clk_rcg2_ops,
1005 },
1006 };
1007
1008 static const struct freq_tbl ftbl_gcc_usb0_lfps_clk_src[] = {
1009 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1010 { }
1011 };
1012
1013 static struct clk_rcg2 gcc_usb0_lfps_clk_src = {
1014 .cmd_rcgr = 0x2c07c,
1015 .mnd_width = 8,
1016 .hid_width = 5,
1017 .parent_map = gcc_parent_map_1,
1018 .freq_tbl = ftbl_gcc_usb0_lfps_clk_src,
1019 .clkr.hw.init = &(const struct clk_init_data) {
1020 .name = "gcc_usb0_lfps_clk_src",
1021 .parent_data = gcc_parent_data_1,
1022 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1023 .ops = &clk_rcg2_ops,
1024 },
1025 };
1026
1027 static struct clk_rcg2 gcc_usb0_master_clk_src = {
1028 .cmd_rcgr = 0x2c004,
1029 .mnd_width = 8,
1030 .hid_width = 5,
1031 .parent_map = gcc_parent_map_0,
1032 .freq_tbl = ftbl_gcc_gp1_clk_src,
1033 .clkr.hw.init = &(const struct clk_init_data) {
1034 .name = "gcc_usb0_master_clk_src",
1035 .parent_data = gcc_parent_data_0,
1036 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1037 .ops = &clk_rcg2_ops,
1038 },
1039 };
1040
1041 static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {
1042 F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),
1043 { }
1044 };
1045
1046 static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
1047 .cmd_rcgr = 0x2c02c,
1048 .mnd_width = 8,
1049 .hid_width = 5,
1050 .parent_map = gcc_parent_map_12,
1051 .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
1052 .clkr.hw.init = &(const struct clk_init_data) {
1053 .name = "gcc_usb0_mock_utmi_clk_src",
1054 .parent_data = gcc_parent_data_12,
1055 .num_parents = ARRAY_SIZE(gcc_parent_data_12),
1056 .ops = &clk_rcg2_ops,
1057 },
1058 };
1059
1060 static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
1061 .reg = 0x2c074,
1062 .clkr = {
1063 .hw.init = &(struct clk_init_data) {
1064 .name = "gcc_usb0_pipe_clk_src",
1065 .parent_data = &(const struct clk_parent_data) {
1066 .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
1067 },
1068 .num_parents = 1,
1069 .ops = &clk_regmap_phy_mux_ops,
1070 },
1071 },
1072 };
1073
1074 static struct clk_rcg2 gcc_wcss_ahb_clk_src = {
1075 .cmd_rcgr = 0x25030,
1076 .mnd_width = 0,
1077 .hid_width = 5,
1078 .parent_map = gcc_parent_map_1,
1079 .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
1080 .clkr.hw.init = &(const struct clk_init_data) {
1081 .name = "gcc_wcss_ahb_clk_src",
1082 .parent_data = gcc_parent_data_1,
1083 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1084 .ops = &clk_rcg2_ops,
1085 },
1086 };
1087
1088 static struct clk_rcg2 gcc_xo_clk_src = {
1089 .cmd_rcgr = 0x34004,
1090 .mnd_width = 0,
1091 .hid_width = 5,
1092 .parent_map = gcc_parent_map_xo,
1093 .freq_tbl = ftbl_gcc_nss_ts_clk_src,
1094 .clkr.hw.init = &(const struct clk_init_data) {
1095 .name = "gcc_xo_clk_src",
1096 .parent_data = &gcc_parent_data_xo,
1097 .num_parents = 1,
1098 .ops = &clk_rcg2_ops,
1099 },
1100 };
1101
1102 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1103 .mult = 1,
1104 .div = 4,
1105 .hw.init = &(struct clk_init_data) {
1106 .name = "gcc_xo_div4_clk_src",
1107 .parent_hws = (const struct clk_hw *[]) {
1108 &gcc_xo_clk_src.clkr.hw },
1109 .num_parents = 1,
1110 .ops = &clk_fixed_factor_ops,
1111 .flags = CLK_SET_RATE_PARENT,
1112 },
1113 };
1114
1115 static struct clk_regmap_div gcc_qdss_dap_div_clk_src = {
1116 .reg = 0x2d028,
1117 .shift = 0,
1118 .width = 4,
1119 .clkr.hw.init = &(const struct clk_init_data) {
1120 .name = "gcc_qdss_dap_div_clk_src",
1121 .parent_hws = (const struct clk_hw*[]) {
1122 &gcc_qdss_tsctr_clk_src.clkr.hw,
1123 },
1124 .num_parents = 1,
1125 .ops = &clk_regmap_div_ro_ops,
1126 },
1127 };
1128
1129 static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = {
1130 .reg = 0x2c040,
1131 .shift = 0,
1132 .width = 2,
1133 .clkr.hw.init = &(const struct clk_init_data) {
1134 .name = "gcc_usb0_mock_utmi_div_clk_src",
1135 .parent_hws = (const struct clk_hw*[]) {
1136 &gcc_usb0_mock_utmi_clk_src.clkr.hw,
1137 },
1138 .num_parents = 1,
1139 .flags = CLK_SET_RATE_PARENT,
1140 .ops = &clk_regmap_div_ro_ops,
1141 },
1142 };
1143
1144 static struct clk_branch gcc_adss_pwm_clk = {
1145 .halt_reg = 0x1c00c,
1146 .halt_check = BRANCH_HALT,
1147 .clkr = {
1148 .enable_reg = 0x1c00c,
1149 .enable_mask = BIT(0),
1150 .hw.init = &(const struct clk_init_data) {
1151 .name = "gcc_adss_pwm_clk",
1152 .parent_hws = (const struct clk_hw*[]) {
1153 &gcc_adss_pwm_clk_src.clkr.hw,
1154 },
1155 .num_parents = 1,
1156 .flags = CLK_SET_RATE_PARENT,
1157 .ops = &clk_branch2_ops,
1158 },
1159 },
1160 };
1161
1162 static struct clk_branch gcc_ahb_clk = {
1163 .halt_reg = 0x34024,
1164 .halt_check = BRANCH_HALT_VOTED,
1165 .clkr = {
1166 .enable_reg = 0x34024,
1167 .enable_mask = BIT(0),
1168 .hw.init = &(const struct clk_init_data) {
1169 .name = "gcc_ahb_clk",
1170 .parent_hws = (const struct clk_hw*[]) {
1171 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1172 },
1173 .num_parents = 1,
1174 .flags = CLK_SET_RATE_PARENT,
1175 .ops = &clk_branch2_ops,
1176 },
1177 },
1178 };
1179
1180 static struct clk_branch gcc_blsp1_ahb_clk = {
1181 .halt_reg = 0x1008,
1182 .halt_check = BRANCH_HALT_VOTED,
1183 .clkr = {
1184 .enable_reg = 0xb004,
1185 .enable_mask = BIT(4),
1186 .hw.init = &(const struct clk_init_data) {
1187 .name = "gcc_blsp1_ahb_clk",
1188 .parent_hws = (const struct clk_hw*[]) {
1189 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1190 },
1191 .num_parents = 1,
1192 .flags = CLK_SET_RATE_PARENT,
1193 .ops = &clk_branch2_ops,
1194 },
1195 },
1196 };
1197
1198 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1199 .halt_reg = 0x2024,
1200 .halt_check = BRANCH_HALT,
1201 .clkr = {
1202 .enable_reg = 0x2024,
1203 .enable_mask = BIT(0),
1204 .hw.init = &(const struct clk_init_data) {
1205 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1206 .parent_hws = (const struct clk_hw*[]) {
1207 &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
1208 },
1209 .num_parents = 1,
1210 .flags = CLK_SET_RATE_PARENT,
1211 .ops = &clk_branch2_ops,
1212 },
1213 },
1214 };
1215
1216 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1217 .halt_reg = 0x2020,
1218 .halt_check = BRANCH_HALT,
1219 .clkr = {
1220 .enable_reg = 0x2020,
1221 .enable_mask = BIT(0),
1222 .hw.init = &(const struct clk_init_data) {
1223 .name = "gcc_blsp1_qup1_spi_apps_clk",
1224 .parent_hws = (const struct clk_hw*[]) {
1225 &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
1226 },
1227 .num_parents = 1,
1228 .flags = CLK_SET_RATE_PARENT,
1229 .ops = &clk_branch2_ops,
1230 },
1231 },
1232 };
1233
1234 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1235 .halt_reg = 0x3024,
1236 .halt_check = BRANCH_HALT,
1237 .clkr = {
1238 .enable_reg = 0x3024,
1239 .enable_mask = BIT(0),
1240 .hw.init = &(const struct clk_init_data) {
1241 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1242 .parent_hws = (const struct clk_hw*[]) {
1243 &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
1244 },
1245 .num_parents = 1,
1246 .flags = CLK_SET_RATE_PARENT,
1247 .ops = &clk_branch2_ops,
1248 },
1249 },
1250 };
1251
1252 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1253 .halt_reg = 0x3020,
1254 .halt_check = BRANCH_HALT,
1255 .clkr = {
1256 .enable_reg = 0x3020,
1257 .enable_mask = BIT(0),
1258 .hw.init = &(const struct clk_init_data) {
1259 .name = "gcc_blsp1_qup2_spi_apps_clk",
1260 .parent_hws = (const struct clk_hw*[]) {
1261 &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
1262 },
1263 .num_parents = 1,
1264 .flags = CLK_SET_RATE_PARENT,
1265 .ops = &clk_branch2_ops,
1266 },
1267 },
1268 };
1269
1270 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1271 .halt_reg = 0x4024,
1272 .halt_check = BRANCH_HALT,
1273 .clkr = {
1274 .enable_reg = 0x4024,
1275 .enable_mask = BIT(0),
1276 .hw.init = &(const struct clk_init_data) {
1277 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1278 .parent_hws = (const struct clk_hw*[]) {
1279 &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
1280 },
1281 .num_parents = 1,
1282 .flags = CLK_SET_RATE_PARENT,
1283 .ops = &clk_branch2_ops,
1284 },
1285 },
1286 };
1287
1288 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1289 .halt_reg = 0x4020,
1290 .halt_check = BRANCH_HALT,
1291 .clkr = {
1292 .enable_reg = 0x4020,
1293 .enable_mask = BIT(0),
1294 .hw.init = &(const struct clk_init_data) {
1295 .name = "gcc_blsp1_qup3_spi_apps_clk",
1296 .parent_hws = (const struct clk_hw*[]) {
1297 &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
1298 },
1299 .num_parents = 1,
1300 .flags = CLK_SET_RATE_PARENT,
1301 .ops = &clk_branch2_ops,
1302 },
1303 },
1304 };
1305
1306 static struct clk_branch gcc_blsp1_sleep_clk = {
1307 .halt_reg = 0x1010,
1308 .halt_check = BRANCH_HALT_VOTED,
1309 .clkr = {
1310 .enable_reg = 0xb004,
1311 .enable_mask = BIT(5),
1312 .hw.init = &(const struct clk_init_data) {
1313 .name = "gcc_blsp1_sleep_clk",
1314 .parent_hws = (const struct clk_hw*[]) {
1315 &gcc_sleep_clk_src.clkr.hw,
1316 },
1317 .num_parents = 1,
1318 .flags = CLK_SET_RATE_PARENT,
1319 .ops = &clk_branch2_ops,
1320 },
1321 },
1322 };
1323
1324 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1325 .halt_reg = 0x2040,
1326 .halt_check = BRANCH_HALT,
1327 .clkr = {
1328 .enable_reg = 0x2040,
1329 .enable_mask = BIT(0),
1330 .hw.init = &(const struct clk_init_data) {
1331 .name = "gcc_blsp1_uart1_apps_clk",
1332 .parent_hws = (const struct clk_hw*[]) {
1333 &gcc_blsp1_uart1_apps_clk_src.clkr.hw,
1334 },
1335 .num_parents = 1,
1336 .flags = CLK_SET_RATE_PARENT,
1337 .ops = &clk_branch2_ops,
1338 },
1339 },
1340 };
1341
1342 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1343 .halt_reg = 0x3040,
1344 .halt_check = BRANCH_HALT,
1345 .clkr = {
1346 .enable_reg = 0x3040,
1347 .enable_mask = BIT(0),
1348 .hw.init = &(const struct clk_init_data) {
1349 .name = "gcc_blsp1_uart2_apps_clk",
1350 .parent_hws = (const struct clk_hw*[]) {
1351 &gcc_blsp1_uart2_apps_clk_src.clkr.hw,
1352 },
1353 .num_parents = 1,
1354 .flags = CLK_SET_RATE_PARENT,
1355 .ops = &clk_branch2_ops,
1356 },
1357 },
1358 };
1359
1360 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1361 .halt_reg = 0x4054,
1362 .halt_check = BRANCH_HALT,
1363 .clkr = {
1364 .enable_reg = 0x4054,
1365 .enable_mask = BIT(0),
1366 .hw.init = &(const struct clk_init_data) {
1367 .name = "gcc_blsp1_uart3_apps_clk",
1368 .parent_hws = (const struct clk_hw*[]) {
1369 &gcc_blsp1_uart3_apps_clk_src.clkr.hw,
1370 },
1371 .num_parents = 1,
1372 .flags = CLK_SET_RATE_PARENT,
1373 .ops = &clk_branch2_ops,
1374 },
1375 },
1376 };
1377
1378 static struct clk_branch gcc_ce_ahb_clk = {
1379 .halt_reg = 0x25074,
1380 .halt_check = BRANCH_HALT,
1381 .clkr = {
1382 .enable_reg = 0x25074,
1383 .enable_mask = BIT(0),
1384 .hw.init = &(const struct clk_init_data) {
1385 .name = "gcc_ce_ahb_clk",
1386 .parent_hws = (const struct clk_hw*[]) {
1387 &gcc_system_noc_bfdcd_div2_clk_src.hw,
1388 },
1389 .num_parents = 1,
1390 .flags = CLK_SET_RATE_PARENT,
1391 .ops = &clk_branch2_ops,
1392 },
1393 },
1394 };
1395
1396 static struct clk_branch gcc_ce_axi_clk = {
1397 .halt_reg = 0x25068,
1398 .halt_check = BRANCH_HALT,
1399 .clkr = {
1400 .enable_reg = 0x25068,
1401 .enable_mask = BIT(0),
1402 .hw.init = &(const struct clk_init_data) {
1403 .name = "gcc_ce_axi_clk",
1404 .parent_hws = (const struct clk_hw*[]) {
1405 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
1406 },
1407 .num_parents = 1,
1408 .flags = CLK_SET_RATE_PARENT,
1409 .ops = &clk_branch2_ops,
1410 },
1411 },
1412 };
1413
1414 static struct clk_branch gcc_ce_pcnoc_ahb_clk = {
1415 .halt_reg = 0x25070,
1416 .halt_check = BRANCH_HALT,
1417 .clkr = {
1418 .enable_reg = 0x25070,
1419 .enable_mask = BIT(0),
1420 .hw.init = &(const struct clk_init_data) {
1421 .name = "gcc_ce_pcnoc_ahb_clk",
1422 .parent_hws = (const struct clk_hw*[]) {
1423 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1424 },
1425 .num_parents = 1,
1426 .flags = CLK_SET_RATE_PARENT,
1427 .ops = &clk_branch2_ops,
1428 },
1429 },
1430 };
1431
1432 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
1433 .halt_reg = 0x3a004,
1434 .halt_check = BRANCH_HALT,
1435 .clkr = {
1436 .enable_reg = 0x3a004,
1437 .enable_mask = BIT(0),
1438 .hw.init = &(const struct clk_init_data) {
1439 .name = "gcc_cmn_12gpll_ahb_clk",
1440 .parent_hws = (const struct clk_hw*[]) {
1441 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1442 },
1443 .num_parents = 1,
1444 .flags = CLK_SET_RATE_PARENT,
1445 .ops = &clk_branch2_ops,
1446 },
1447 },
1448 };
1449
1450 static struct clk_branch gcc_cmn_12gpll_apu_clk = {
1451 .halt_reg = 0x3a00c,
1452 .halt_check = BRANCH_HALT,
1453 .clkr = {
1454 .enable_reg = 0x3a00c,
1455 .enable_mask = BIT(0),
1456 .hw.init = &(const struct clk_init_data) {
1457 .name = "gcc_cmn_12gpll_apu_clk",
1458 .parent_hws = (const struct clk_hw*[]) {
1459 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1460 },
1461 .num_parents = 1,
1462 .flags = CLK_SET_RATE_PARENT,
1463 .ops = &clk_branch2_ops,
1464 },
1465 },
1466 };
1467
1468 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
1469 .halt_reg = 0x3a008,
1470 .halt_check = BRANCH_HALT,
1471 .clkr = {
1472 .enable_reg = 0x3a008,
1473 .enable_mask = BIT(0),
1474 .hw.init = &(const struct clk_init_data) {
1475 .name = "gcc_cmn_12gpll_sys_clk",
1476 .parent_hws = (const struct clk_hw*[]) {
1477 &gcc_uniphy_sys_clk_src.clkr.hw,
1478 },
1479 .num_parents = 1,
1480 .flags = CLK_SET_RATE_PARENT,
1481 .ops = &clk_branch2_ops,
1482 },
1483 },
1484 };
1485
1486 static struct clk_branch gcc_gp1_clk = {
1487 .halt_reg = 0x8018,
1488 .halt_check = BRANCH_HALT,
1489 .clkr = {
1490 .enable_reg = 0x8018,
1491 .enable_mask = BIT(0),
1492 .hw.init = &(const struct clk_init_data) {
1493 .name = "gcc_gp1_clk",
1494 .parent_hws = (const struct clk_hw*[]) {
1495 &gcc_gp1_clk_src.clkr.hw,
1496 },
1497 .num_parents = 1,
1498 .flags = CLK_SET_RATE_PARENT,
1499 .ops = &clk_branch2_ops,
1500 },
1501 },
1502 };
1503
1504 static struct clk_branch gcc_gp2_clk = {
1505 .halt_reg = 0x9018,
1506 .halt_check = BRANCH_HALT,
1507 .clkr = {
1508 .enable_reg = 0x9018,
1509 .enable_mask = BIT(0),
1510 .hw.init = &(const struct clk_init_data) {
1511 .name = "gcc_gp2_clk",
1512 .parent_hws = (const struct clk_hw*[]) {
1513 &gcc_gp2_clk_src.clkr.hw,
1514 },
1515 .num_parents = 1,
1516 .flags = CLK_SET_RATE_PARENT,
1517 .ops = &clk_branch2_ops,
1518 },
1519 },
1520 };
1521
1522 static struct clk_branch gcc_lpass_core_axim_clk = {
1523 .halt_reg = 0x27018,
1524 .halt_check = BRANCH_HALT_VOTED,
1525 .clkr = {
1526 .enable_reg = 0x27018,
1527 .enable_mask = BIT(0),
1528 .hw.init = &(const struct clk_init_data) {
1529 .name = "gcc_lpass_core_axim_clk",
1530 .parent_hws = (const struct clk_hw*[]) {
1531 &gcc_lpass_sway_clk_src.clkr.hw,
1532 },
1533 .num_parents = 1,
1534 .flags = CLK_SET_RATE_PARENT,
1535 .ops = &clk_branch2_ops,
1536 },
1537 },
1538 };
1539
1540 static struct clk_branch gcc_lpass_sway_clk = {
1541 .halt_reg = 0x27014,
1542 .halt_check = BRANCH_HALT,
1543 .clkr = {
1544 .enable_reg = 0x27014,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(const struct clk_init_data) {
1547 .name = "gcc_lpass_sway_clk",
1548 .parent_hws = (const struct clk_hw*[]) {
1549 &gcc_lpass_sway_clk_src.clkr.hw,
1550 },
1551 .num_parents = 1,
1552 .flags = CLK_SET_RATE_PARENT,
1553 .ops = &clk_branch2_ops,
1554 },
1555 },
1556 };
1557
1558 static struct clk_branch gcc_mdio_ahb_clk = {
1559 .halt_reg = 0x12004,
1560 .halt_check = BRANCH_HALT,
1561 .clkr = {
1562 .enable_reg = 0x12004,
1563 .enable_mask = BIT(0),
1564 .hw.init = &(const struct clk_init_data) {
1565 .name = "gcc_mdio_ahb_clk",
1566 .parent_hws = (const struct clk_hw*[]) {
1567 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1568 },
1569 .num_parents = 1,
1570 .flags = CLK_SET_RATE_PARENT,
1571 .ops = &clk_branch2_ops,
1572 },
1573 },
1574 };
1575
1576 static struct clk_branch gcc_mdio_slave_ahb_clk = {
1577 .halt_reg = 0x1200c,
1578 .halt_check = BRANCH_HALT,
1579 .clkr = {
1580 .enable_reg = 0x1200c,
1581 .enable_mask = BIT(0),
1582 .hw.init = &(const struct clk_init_data) {
1583 .name = "gcc_mdio_slave_ahb_clk",
1584 .parent_hws = (const struct clk_hw*[]) {
1585 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1586 },
1587 .num_parents = 1,
1588 .flags = CLK_SET_RATE_PARENT,
1589 .ops = &clk_branch2_ops,
1590 },
1591 },
1592 };
1593
1594 static struct clk_branch gcc_nss_ts_clk = {
1595 .halt_reg = 0x17018,
1596 .halt_check = BRANCH_HALT_VOTED,
1597 .clkr = {
1598 .enable_reg = 0x17018,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(const struct clk_init_data) {
1601 .name = "gcc_nss_ts_clk",
1602 .parent_hws = (const struct clk_hw*[]) {
1603 &gcc_nss_ts_clk_src.clkr.hw,
1604 },
1605 .num_parents = 1,
1606 .flags = CLK_SET_RATE_PARENT,
1607 .ops = &clk_branch2_ops,
1608 },
1609 },
1610 };
1611
1612 static struct clk_branch gcc_nsscc_clk = {
1613 .halt_reg = 0x17034,
1614 .halt_check = BRANCH_HALT,
1615 .clkr = {
1616 .enable_reg = 0x17034,
1617 .enable_mask = BIT(0),
1618 .hw.init = &(const struct clk_init_data) {
1619 .name = "gcc_nsscc_clk",
1620 .parent_hws = (const struct clk_hw*[]) {
1621 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1622 },
1623 .num_parents = 1,
1624 .flags = CLK_SET_RATE_PARENT,
1625 .ops = &clk_branch2_ops,
1626 },
1627 },
1628 };
1629
1630 static struct clk_branch gcc_nsscfg_clk = {
1631 .halt_reg = 0x1702c,
1632 .halt_check = BRANCH_HALT,
1633 .clkr = {
1634 .enable_reg = 0x1702c,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(const struct clk_init_data) {
1637 .name = "gcc_nsscfg_clk",
1638 .parent_hws = (const struct clk_hw*[]) {
1639 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1640 },
1641 .num_parents = 1,
1642 .flags = CLK_SET_RATE_PARENT,
1643 .ops = &clk_branch2_ops,
1644 },
1645 },
1646 };
1647
1648 static struct clk_branch gcc_nssnoc_atb_clk = {
1649 .halt_reg = 0x17014,
1650 .halt_check = BRANCH_HALT,
1651 .clkr = {
1652 .enable_reg = 0x17014,
1653 .enable_mask = BIT(0),
1654 .hw.init = &(const struct clk_init_data) {
1655 .name = "gcc_nssnoc_atb_clk",
1656 .parent_hws = (const struct clk_hw*[]) {
1657 &gcc_qdss_at_clk_src.clkr.hw,
1658 },
1659 .num_parents = 1,
1660 .flags = CLK_SET_RATE_PARENT,
1661 .ops = &clk_branch2_ops,
1662 },
1663 },
1664 };
1665
1666 static struct clk_branch gcc_nssnoc_nsscc_clk = {
1667 .halt_reg = 0x17030,
1668 .halt_check = BRANCH_HALT,
1669 .clkr = {
1670 .enable_reg = 0x17030,
1671 .enable_mask = BIT(0),
1672 .hw.init = &(const struct clk_init_data) {
1673 .name = "gcc_nssnoc_nsscc_clk",
1674 .parent_hws = (const struct clk_hw*[]) {
1675 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1676 },
1677 .num_parents = 1,
1678 .flags = CLK_SET_RATE_PARENT,
1679 .ops = &clk_branch2_ops,
1680 },
1681 },
1682 };
1683
1684 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
1685 .halt_reg = 0x1701c,
1686 .halt_check = BRANCH_HALT,
1687 .clkr = {
1688 .enable_reg = 0x1701c,
1689 .enable_mask = BIT(0),
1690 .hw.init = &(const struct clk_init_data) {
1691 .name = "gcc_nssnoc_qosgen_ref_clk",
1692 .parent_hws = (const struct clk_hw*[]) {
1693 &gcc_xo_div4_clk_src.hw,
1694 },
1695 .num_parents = 1,
1696 .flags = CLK_SET_RATE_PARENT,
1697 .ops = &clk_branch2_ops,
1698 },
1699 },
1700 };
1701
1702 static struct clk_branch gcc_nssnoc_snoc_1_clk = {
1703 .halt_reg = 0x1707c,
1704 .halt_check = BRANCH_HALT,
1705 .clkr = {
1706 .enable_reg = 0x1707c,
1707 .enable_mask = BIT(0),
1708 .hw.init = &(const struct clk_init_data) {
1709 .name = "gcc_nssnoc_snoc_1_clk",
1710 .parent_hws = (const struct clk_hw*[]) {
1711 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
1712 },
1713 .num_parents = 1,
1714 .flags = CLK_SET_RATE_PARENT,
1715 .ops = &clk_branch2_ops,
1716 },
1717 },
1718 };
1719
1720 static struct clk_branch gcc_nssnoc_snoc_clk = {
1721 .halt_reg = 0x17028,
1722 .halt_check = BRANCH_HALT,
1723 .clkr = {
1724 .enable_reg = 0x17028,
1725 .enable_mask = BIT(0),
1726 .hw.init = &(const struct clk_init_data) {
1727 .name = "gcc_nssnoc_snoc_clk",
1728 .parent_hws = (const struct clk_hw*[]) {
1729 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
1730 },
1731 .num_parents = 1,
1732 .flags = CLK_SET_RATE_PARENT,
1733 .ops = &clk_branch2_ops,
1734 },
1735 },
1736 };
1737
1738 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
1739 .halt_reg = 0x17020,
1740 .halt_check = BRANCH_HALT,
1741 .clkr = {
1742 .enable_reg = 0x17020,
1743 .enable_mask = BIT(0),
1744 .hw.init = &(const struct clk_init_data) {
1745 .name = "gcc_nssnoc_timeout_ref_clk",
1746 .parent_hws = (const struct clk_hw*[]) {
1747 &gcc_xo_div4_clk_src.hw,
1748 },
1749 .num_parents = 1,
1750 .flags = CLK_SET_RATE_PARENT,
1751 .ops = &clk_branch2_ops,
1752 },
1753 },
1754 };
1755
1756 static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
1757 .halt_reg = 0x17074,
1758 .halt_check = BRANCH_HALT,
1759 .clkr = {
1760 .enable_reg = 0x17074,
1761 .enable_mask = BIT(0),
1762 .hw.init = &(const struct clk_init_data) {
1763 .name = "gcc_nssnoc_xo_dcd_clk",
1764 .parent_hws = (const struct clk_hw*[]) {
1765 &gcc_xo_clk_src.clkr.hw,
1766 },
1767 .num_parents = 1,
1768 .flags = CLK_SET_RATE_PARENT,
1769 .ops = &clk_branch2_ops,
1770 },
1771 },
1772 };
1773
1774 static struct clk_branch gcc_pcie3x1_0_ahb_clk = {
1775 .halt_reg = 0x29030,
1776 .halt_check = BRANCH_HALT,
1777 .clkr = {
1778 .enable_reg = 0x29030,
1779 .enable_mask = BIT(0),
1780 .hw.init = &(const struct clk_init_data) {
1781 .name = "gcc_pcie3x1_0_ahb_clk",
1782 .parent_hws = (const struct clk_hw*[]) {
1783 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1784 },
1785 .num_parents = 1,
1786 .flags = CLK_SET_RATE_PARENT,
1787 .ops = &clk_branch2_ops,
1788 },
1789 },
1790 };
1791
1792 static struct clk_branch gcc_pcie3x1_0_aux_clk = {
1793 .halt_reg = 0x29070,
1794 .halt_check = BRANCH_HALT,
1795 .clkr = {
1796 .enable_reg = 0x29070,
1797 .enable_mask = BIT(0),
1798 .hw.init = &(const struct clk_init_data) {
1799 .name = "gcc_pcie3x1_0_aux_clk",
1800 .parent_hws = (const struct clk_hw*[]) {
1801 &gcc_pcie_aux_clk_src.clkr.hw,
1802 },
1803 .num_parents = 1,
1804 .flags = CLK_SET_RATE_PARENT,
1805 .ops = &clk_branch2_ops,
1806 },
1807 },
1808 };
1809
1810 static struct clk_branch gcc_pcie3x1_0_axi_m_clk = {
1811 .halt_reg = 0x29038,
1812 .halt_check = BRANCH_HALT,
1813 .clkr = {
1814 .enable_reg = 0x29038,
1815 .enable_mask = BIT(0),
1816 .hw.init = &(const struct clk_init_data) {
1817 .name = "gcc_pcie3x1_0_axi_m_clk",
1818 .parent_hws = (const struct clk_hw*[]) {
1819 &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
1820 },
1821 .num_parents = 1,
1822 .flags = CLK_SET_RATE_PARENT,
1823 .ops = &clk_branch2_ops,
1824 },
1825 },
1826 };
1827
1828 static struct clk_branch gcc_pcie3x1_0_axi_s_bridge_clk = {
1829 .halt_reg = 0x29048,
1830 .halt_check = BRANCH_HALT,
1831 .clkr = {
1832 .enable_reg = 0x29048,
1833 .enable_mask = BIT(0),
1834 .hw.init = &(const struct clk_init_data) {
1835 .name = "gcc_pcie3x1_0_axi_s_bridge_clk",
1836 .parent_hws = (const struct clk_hw*[]) {
1837 &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
1838 },
1839 .num_parents = 1,
1840 .flags = CLK_SET_RATE_PARENT,
1841 .ops = &clk_branch2_ops,
1842 },
1843 },
1844 };
1845
1846 static struct clk_branch gcc_pcie3x1_0_axi_s_clk = {
1847 .halt_reg = 0x29040,
1848 .halt_check = BRANCH_HALT,
1849 .clkr = {
1850 .enable_reg = 0x29040,
1851 .enable_mask = BIT(0),
1852 .hw.init = &(const struct clk_init_data) {
1853 .name = "gcc_pcie3x1_0_axi_s_clk",
1854 .parent_hws = (const struct clk_hw*[]) {
1855 &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
1856 },
1857 .num_parents = 1,
1858 .flags = CLK_SET_RATE_PARENT,
1859 .ops = &clk_branch2_ops,
1860 },
1861 },
1862 };
1863
1864 static struct clk_branch gcc_pcie3x1_0_pipe_clk = {
1865 .halt_reg = 0x29068,
1866 .halt_check = BRANCH_HALT_DELAY,
1867 .clkr = {
1868 .enable_reg = 0x29068,
1869 .enable_mask = BIT(0),
1870 .hw.init = &(const struct clk_init_data) {
1871 .name = "gcc_pcie3x1_0_pipe_clk",
1872 .parent_hws = (const struct clk_hw*[]) {
1873 &gcc_pcie3x1_0_pipe_clk_src.clkr.hw,
1874 },
1875 .num_parents = 1,
1876 .flags = CLK_SET_RATE_PARENT,
1877 .ops = &clk_branch2_ops,
1878 },
1879 },
1880 };
1881
1882 static struct clk_branch gcc_pcie3x1_1_ahb_clk = {
1883 .halt_reg = 0x2a00c,
1884 .halt_check = BRANCH_HALT,
1885 .clkr = {
1886 .enable_reg = 0x2a00c,
1887 .enable_mask = BIT(0),
1888 .hw.init = &(const struct clk_init_data) {
1889 .name = "gcc_pcie3x1_1_ahb_clk",
1890 .parent_hws = (const struct clk_hw*[]) {
1891 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1892 },
1893 .num_parents = 1,
1894 .flags = CLK_SET_RATE_PARENT,
1895 .ops = &clk_branch2_ops,
1896 },
1897 },
1898 };
1899
1900 static struct clk_branch gcc_pcie3x1_1_aux_clk = {
1901 .halt_reg = 0x2a070,
1902 .halt_check = BRANCH_HALT,
1903 .clkr = {
1904 .enable_reg = 0x2a070,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(const struct clk_init_data) {
1907 .name = "gcc_pcie3x1_1_aux_clk",
1908 .parent_hws = (const struct clk_hw*[]) {
1909 &gcc_pcie_aux_clk_src.clkr.hw,
1910 },
1911 .num_parents = 1,
1912 .flags = CLK_SET_RATE_PARENT,
1913 .ops = &clk_branch2_ops,
1914 },
1915 },
1916 };
1917
1918 static struct clk_branch gcc_pcie3x1_1_axi_m_clk = {
1919 .halt_reg = 0x2a014,
1920 .halt_check = BRANCH_HALT,
1921 .clkr = {
1922 .enable_reg = 0x2a014,
1923 .enable_mask = BIT(0),
1924 .hw.init = &(const struct clk_init_data) {
1925 .name = "gcc_pcie3x1_1_axi_m_clk",
1926 .parent_hws = (const struct clk_hw*[]) {
1927 &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
1928 },
1929 .num_parents = 1,
1930 .flags = CLK_SET_RATE_PARENT,
1931 .ops = &clk_branch2_ops,
1932 },
1933 },
1934 };
1935
1936 static struct clk_branch gcc_pcie3x1_1_axi_s_bridge_clk = {
1937 .halt_reg = 0x2a024,
1938 .halt_check = BRANCH_HALT,
1939 .clkr = {
1940 .enable_reg = 0x2a024,
1941 .enable_mask = BIT(0),
1942 .hw.init = &(const struct clk_init_data) {
1943 .name = "gcc_pcie3x1_1_axi_s_bridge_clk",
1944 .parent_hws = (const struct clk_hw*[]) {
1945 &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
1946 },
1947 .num_parents = 1,
1948 .flags = CLK_SET_RATE_PARENT,
1949 .ops = &clk_branch2_ops,
1950 },
1951 },
1952 };
1953
1954 static struct clk_branch gcc_pcie3x1_1_axi_s_clk = {
1955 .halt_reg = 0x2a01c,
1956 .halt_check = BRANCH_HALT,
1957 .clkr = {
1958 .enable_reg = 0x2a01c,
1959 .enable_mask = BIT(0),
1960 .hw.init = &(const struct clk_init_data) {
1961 .name = "gcc_pcie3x1_1_axi_s_clk",
1962 .parent_hws = (const struct clk_hw*[]) {
1963 &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
1964 },
1965 .num_parents = 1,
1966 .flags = CLK_SET_RATE_PARENT,
1967 .ops = &clk_branch2_ops,
1968 },
1969 },
1970 };
1971
1972 static struct clk_branch gcc_pcie3x1_1_pipe_clk = {
1973 .halt_reg = 0x2a068,
1974 .halt_check = BRANCH_HALT_DELAY,
1975 .clkr = {
1976 .enable_reg = 0x2a068,
1977 .enable_mask = BIT(0),
1978 .hw.init = &(const struct clk_init_data) {
1979 .name = "gcc_pcie3x1_1_pipe_clk",
1980 .parent_hws = (const struct clk_hw*[]) {
1981 &gcc_pcie3x1_1_pipe_clk_src.clkr.hw,
1982 },
1983 .num_parents = 1,
1984 .flags = CLK_SET_RATE_PARENT,
1985 .ops = &clk_branch2_ops,
1986 },
1987 },
1988 };
1989
1990 static struct clk_branch gcc_pcie3x1_phy_ahb_clk = {
1991 .halt_reg = 0x29078,
1992 .halt_check = BRANCH_HALT,
1993 .clkr = {
1994 .enable_reg = 0x29078,
1995 .enable_mask = BIT(0),
1996 .hw.init = &(const struct clk_init_data) {
1997 .name = "gcc_pcie3x1_phy_ahb_clk",
1998 .parent_hws = (const struct clk_hw*[]) {
1999 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2000 },
2001 .num_parents = 1,
2002 .flags = CLK_SET_RATE_PARENT,
2003 .ops = &clk_branch2_ops,
2004 },
2005 },
2006 };
2007
2008 static struct clk_branch gcc_pcie3x2_ahb_clk = {
2009 .halt_reg = 0x28030,
2010 .halt_check = BRANCH_HALT,
2011 .clkr = {
2012 .enable_reg = 0x28030,
2013 .enable_mask = BIT(0),
2014 .hw.init = &(const struct clk_init_data) {
2015 .name = "gcc_pcie3x2_ahb_clk",
2016 .parent_hws = (const struct clk_hw*[]) {
2017 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2018 },
2019 .num_parents = 1,
2020 .flags = CLK_SET_RATE_PARENT,
2021 .ops = &clk_branch2_ops,
2022 },
2023 },
2024 };
2025
2026 static struct clk_branch gcc_pcie3x2_aux_clk = {
2027 .halt_reg = 0x28070,
2028 .halt_check = BRANCH_HALT,
2029 .clkr = {
2030 .enable_reg = 0x28070,
2031 .enable_mask = BIT(0),
2032 .hw.init = &(const struct clk_init_data) {
2033 .name = "gcc_pcie3x2_aux_clk",
2034 .parent_hws = (const struct clk_hw*[]) {
2035 &gcc_pcie_aux_clk_src.clkr.hw,
2036 },
2037 .num_parents = 1,
2038 .flags = CLK_SET_RATE_PARENT,
2039 .ops = &clk_branch2_ops,
2040 },
2041 },
2042 };
2043
2044 static struct clk_branch gcc_pcie3x2_axi_m_clk = {
2045 .halt_reg = 0x28038,
2046 .halt_check = BRANCH_HALT,
2047 .clkr = {
2048 .enable_reg = 0x28038,
2049 .enable_mask = BIT(0),
2050 .hw.init = &(const struct clk_init_data) {
2051 .name = "gcc_pcie3x2_axi_m_clk",
2052 .parent_hws = (const struct clk_hw*[]) {
2053 &gcc_pcie3x2_axi_m_clk_src.clkr.hw,
2054 },
2055 .num_parents = 1,
2056 .flags = CLK_SET_RATE_PARENT,
2057 .ops = &clk_branch2_ops,
2058 },
2059 },
2060 };
2061
2062 static struct clk_branch gcc_pcie3x2_axi_s_bridge_clk = {
2063 .halt_reg = 0x28048,
2064 .halt_check = BRANCH_HALT,
2065 .clkr = {
2066 .enable_reg = 0x28048,
2067 .enable_mask = BIT(0),
2068 .hw.init = &(const struct clk_init_data) {
2069 .name = "gcc_pcie3x2_axi_s_bridge_clk",
2070 .parent_hws = (const struct clk_hw*[]) {
2071 &gcc_pcie3x2_axi_s_clk_src.clkr.hw,
2072 },
2073 .num_parents = 1,
2074 .flags = CLK_SET_RATE_PARENT,
2075 .ops = &clk_branch2_ops,
2076 },
2077 },
2078 };
2079
2080 static struct clk_branch gcc_pcie3x2_axi_s_clk = {
2081 .halt_reg = 0x28040,
2082 .halt_check = BRANCH_HALT,
2083 .clkr = {
2084 .enable_reg = 0x28040,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(const struct clk_init_data) {
2087 .name = "gcc_pcie3x2_axi_s_clk",
2088 .parent_hws = (const struct clk_hw*[]) {
2089 &gcc_pcie3x2_axi_s_clk_src.clkr.hw,
2090 },
2091 .num_parents = 1,
2092 .flags = CLK_SET_RATE_PARENT,
2093 .ops = &clk_branch2_ops,
2094 },
2095 },
2096 };
2097
2098 static struct clk_branch gcc_pcie3x2_phy_ahb_clk = {
2099 .halt_reg = 0x28080,
2100 .halt_check = BRANCH_HALT,
2101 .clkr = {
2102 .enable_reg = 0x28080,
2103 .enable_mask = BIT(0),
2104 .hw.init = &(const struct clk_init_data) {
2105 .name = "gcc_pcie3x2_phy_ahb_clk",
2106 .parent_hws = (const struct clk_hw*[]) {
2107 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2108 },
2109 .num_parents = 1,
2110 .flags = CLK_SET_RATE_PARENT,
2111 .ops = &clk_branch2_ops,
2112 },
2113 },
2114 };
2115
2116 static struct clk_branch gcc_pcie3x2_pipe_clk = {
2117 .halt_reg = 0x28068,
2118 .halt_check = BRANCH_HALT_DELAY,
2119 .clkr = {
2120 .enable_reg = 0x28068,
2121 .enable_mask = BIT(0),
2122 .hw.init = &(const struct clk_init_data) {
2123 .name = "gcc_pcie3x2_pipe_clk",
2124 .parent_hws = (const struct clk_hw*[]) {
2125 &gcc_pcie3x2_pipe_clk_src.clkr.hw,
2126 },
2127 .num_parents = 1,
2128 .flags = CLK_SET_RATE_PARENT,
2129 .ops = &clk_branch2_ops,
2130 },
2131 },
2132 };
2133
2134 static struct clk_branch gcc_pcnoc_at_clk = {
2135 .halt_reg = 0x31024,
2136 .halt_check = BRANCH_HALT_VOTED,
2137 .clkr = {
2138 .enable_reg = 0x31024,
2139 .enable_mask = BIT(0),
2140 .hw.init = &(const struct clk_init_data) {
2141 .name = "gcc_pcnoc_at_clk",
2142 .parent_hws = (const struct clk_hw*[]) {
2143 &gcc_qdss_at_clk_src.clkr.hw,
2144 },
2145 .num_parents = 1,
2146 .flags = CLK_SET_RATE_PARENT,
2147 .ops = &clk_branch2_ops,
2148 },
2149 },
2150 };
2151
2152 static struct clk_branch gcc_pcnoc_lpass_clk = {
2153 .halt_reg = 0x31020,
2154 .halt_check = BRANCH_HALT,
2155 .clkr = {
2156 .enable_reg = 0x31020,
2157 .enable_mask = BIT(0),
2158 .hw.init = &(const struct clk_init_data) {
2159 .name = "gcc_pcnoc_lpass_clk",
2160 .parent_hws = (const struct clk_hw*[]) {
2161 &gcc_lpass_sway_clk_src.clkr.hw,
2162 },
2163 .num_parents = 1,
2164 .flags = CLK_SET_RATE_PARENT,
2165 .ops = &clk_branch2_ops,
2166 },
2167 },
2168 };
2169
2170 static struct clk_branch gcc_prng_ahb_clk = {
2171 .halt_reg = 0x13024,
2172 .halt_check = BRANCH_HALT_VOTED,
2173 .clkr = {
2174 .enable_reg = 0xb004,
2175 .enable_mask = BIT(10),
2176 .hw.init = &(const struct clk_init_data) {
2177 .name = "gcc_prng_ahb_clk",
2178 .parent_hws = (const struct clk_hw*[]) {
2179 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2180 },
2181 .num_parents = 1,
2182 .flags = CLK_SET_RATE_PARENT,
2183 .ops = &clk_branch2_ops,
2184 },
2185 },
2186 };
2187
2188 static struct clk_branch gcc_qdss_at_clk = {
2189 .halt_reg = 0x2d038,
2190 .halt_check = BRANCH_HALT_VOTED,
2191 .clkr = {
2192 .enable_reg = 0x2d038,
2193 .enable_mask = BIT(0),
2194 .hw.init = &(const struct clk_init_data) {
2195 .name = "gcc_qdss_at_clk",
2196 .parent_hws = (const struct clk_hw*[]) {
2197 &gcc_qdss_at_clk_src.clkr.hw,
2198 },
2199 .num_parents = 1,
2200 .flags = CLK_SET_RATE_PARENT,
2201 .ops = &clk_branch2_ops,
2202 },
2203 },
2204 };
2205
2206 static struct clk_branch gcc_qdss_cfg_ahb_clk = {
2207 .halt_reg = 0x2d06c,
2208 .halt_check = BRANCH_HALT_VOTED,
2209 .clkr = {
2210 .enable_reg = 0x2d06c,
2211 .enable_mask = BIT(0),
2212 .hw.init = &(const struct clk_init_data) {
2213 .name = "gcc_qdss_cfg_ahb_clk",
2214 .parent_hws = (const struct clk_hw*[]) {
2215 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2216 },
2217 .num_parents = 1,
2218 .flags = CLK_SET_RATE_PARENT,
2219 .ops = &clk_branch2_ops,
2220 },
2221 },
2222 };
2223
2224 static struct clk_branch gcc_qdss_dap_ahb_clk = {
2225 .halt_reg = 0x2d068,
2226 .halt_check = BRANCH_HALT_VOTED,
2227 .clkr = {
2228 .enable_reg = 0x2d068,
2229 .enable_mask = BIT(0),
2230 .hw.init = &(const struct clk_init_data) {
2231 .name = "gcc_qdss_dap_ahb_clk",
2232 .parent_hws = (const struct clk_hw*[]) {
2233 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2234 },
2235 .num_parents = 1,
2236 .flags = CLK_SET_RATE_PARENT,
2237 .ops = &clk_branch2_ops,
2238 },
2239 },
2240 };
2241
2242 static struct clk_branch gcc_qdss_dap_clk = {
2243 .halt_reg = 0x2d05c,
2244 .halt_check = BRANCH_HALT_VOTED,
2245 .clkr = {
2246 .enable_reg = 0xb004,
2247 .enable_mask = BIT(2),
2248 .hw.init = &(const struct clk_init_data) {
2249 .name = "gcc_qdss_dap_clk",
2250 .parent_hws = (const struct clk_hw*[]) {
2251 &gcc_qdss_dap_div_clk_src.clkr.hw,
2252 },
2253 .num_parents = 1,
2254 .flags = CLK_SET_RATE_PARENT,
2255 .ops = &clk_branch2_ops,
2256 },
2257 },
2258 };
2259
2260 static struct clk_branch gcc_qdss_etr_usb_clk = {
2261 .halt_reg = 0x2d064,
2262 .halt_check = BRANCH_HALT_VOTED,
2263 .clkr = {
2264 .enable_reg = 0x2d064,
2265 .enable_mask = BIT(0),
2266 .hw.init = &(const struct clk_init_data) {
2267 .name = "gcc_qdss_etr_usb_clk",
2268 .parent_hws = (const struct clk_hw*[]) {
2269 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
2270 },
2271 .num_parents = 1,
2272 .flags = CLK_SET_RATE_PARENT,
2273 .ops = &clk_branch2_ops,
2274 },
2275 },
2276 };
2277
2278 static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
2279 .mult = 1,
2280 .div = 6,
2281 .hw.init = &(struct clk_init_data) {
2282 .name = "gcc_eud_at_div_clk_src",
2283 .parent_hws = (const struct clk_hw *[]) {
2284 &gcc_qdss_at_clk_src.clkr.hw },
2285 .num_parents = 1,
2286 .flags = CLK_SET_RATE_PARENT,
2287 .ops = &clk_fixed_factor_ops,
2288 },
2289 };
2290
2291 static struct clk_branch gcc_qdss_eud_at_clk = {
2292 .halt_reg = 0x2d070,
2293 .halt_check = BRANCH_HALT_VOTED,
2294 .clkr = {
2295 .enable_reg = 0x2d070,
2296 .enable_mask = BIT(0),
2297 .hw.init = &(const struct clk_init_data) {
2298 .name = "gcc_qdss_eud_at_clk",
2299 .parent_hws = (const struct clk_hw*[]) {
2300 &gcc_eud_at_div_clk_src.hw,
2301 },
2302 .num_parents = 1,
2303 .flags = CLK_SET_RATE_PARENT,
2304 .ops = &clk_branch2_ops,
2305 },
2306 },
2307 };
2308
2309 static struct clk_branch gcc_qpic_ahb_clk = {
2310 .halt_reg = 0x32010,
2311 .halt_check = BRANCH_HALT,
2312 .clkr = {
2313 .enable_reg = 0x32010,
2314 .enable_mask = BIT(0),
2315 .hw.init = &(const struct clk_init_data) {
2316 .name = "gcc_qpic_ahb_clk",
2317 .parent_hws = (const struct clk_hw*[]) {
2318 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2319 },
2320 .num_parents = 1,
2321 .flags = CLK_SET_RATE_PARENT,
2322 .ops = &clk_branch2_ops,
2323 },
2324 },
2325 };
2326
2327 static struct clk_branch gcc_qpic_clk = {
2328 .halt_reg = 0x32014,
2329 .halt_check = BRANCH_HALT,
2330 .clkr = {
2331 .enable_reg = 0x32014,
2332 .enable_mask = BIT(0),
2333 .hw.init = &(const struct clk_init_data) {
2334 .name = "gcc_qpic_clk",
2335 .parent_hws = (const struct clk_hw*[]) {
2336 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2337 },
2338 .num_parents = 1,
2339 .flags = CLK_SET_RATE_PARENT,
2340 .ops = &clk_branch2_ops,
2341 },
2342 },
2343 };
2344
2345 static struct clk_branch gcc_qpic_io_macro_clk = {
2346 .halt_reg = 0x3200c,
2347 .halt_check = BRANCH_HALT,
2348 .clkr = {
2349 .enable_reg = 0x3200c,
2350 .enable_mask = BIT(0),
2351 .hw.init = &(const struct clk_init_data) {
2352 .name = "gcc_qpic_io_macro_clk",
2353 .parent_hws = (const struct clk_hw*[]) {
2354 &gcc_qpic_io_macro_clk_src.clkr.hw,
2355 },
2356 .num_parents = 1,
2357 .flags = CLK_SET_RATE_PARENT,
2358 .ops = &clk_branch2_ops,
2359 },
2360 },
2361 };
2362
2363 static struct clk_branch gcc_qpic_sleep_clk = {
2364 .halt_reg = 0x3201c,
2365 .halt_check = BRANCH_HALT,
2366 .clkr = {
2367 .enable_reg = 0x3201c,
2368 .enable_mask = BIT(0),
2369 .hw.init = &(const struct clk_init_data) {
2370 .name = "gcc_qpic_sleep_clk",
2371 .parent_hws = (const struct clk_hw*[]) {
2372 &gcc_sleep_clk_src.clkr.hw,
2373 },
2374 .num_parents = 1,
2375 .flags = CLK_SET_RATE_PARENT,
2376 .ops = &clk_branch2_ops,
2377 },
2378 },
2379 };
2380
2381 static struct clk_branch gcc_sdcc1_ahb_clk = {
2382 .halt_reg = 0x33034,
2383 .halt_check = BRANCH_HALT,
2384 .clkr = {
2385 .enable_reg = 0x33034,
2386 .enable_mask = BIT(0),
2387 .hw.init = &(const struct clk_init_data) {
2388 .name = "gcc_sdcc1_ahb_clk",
2389 .parent_hws = (const struct clk_hw*[]) {
2390 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2391 },
2392 .num_parents = 1,
2393 .flags = CLK_SET_RATE_PARENT,
2394 .ops = &clk_branch2_ops,
2395 },
2396 },
2397 };
2398
2399 static struct clk_branch gcc_sdcc1_apps_clk = {
2400 .halt_reg = 0x3302c,
2401 .halt_check = BRANCH_HALT,
2402 .clkr = {
2403 .enable_reg = 0x3302c,
2404 .enable_mask = BIT(0),
2405 .hw.init = &(const struct clk_init_data) {
2406 .name = "gcc_sdcc1_apps_clk",
2407 .parent_hws = (const struct clk_hw*[]) {
2408 &gcc_sdcc1_apps_clk_src.clkr.hw,
2409 },
2410 .num_parents = 1,
2411 .flags = CLK_SET_RATE_PARENT,
2412 .ops = &clk_branch2_ops,
2413 },
2414 },
2415 };
2416
2417 static struct clk_branch gcc_snoc_lpass_cfg_clk = {
2418 .halt_reg = 0x2e028,
2419 .halt_check = BRANCH_HALT,
2420 .clkr = {
2421 .enable_reg = 0x2e028,
2422 .enable_mask = BIT(0),
2423 .hw.init = &(const struct clk_init_data) {
2424 .name = "gcc_snoc_lpass_cfg_clk",
2425 .parent_hws = (const struct clk_hw*[]) {
2426 &gcc_lpass_sway_clk_src.clkr.hw,
2427 },
2428 .num_parents = 1,
2429 .flags = CLK_SET_RATE_PARENT,
2430 .ops = &clk_branch2_ops,
2431 },
2432 },
2433 };
2434
2435 static struct clk_branch gcc_snoc_nssnoc_1_clk = {
2436 .halt_reg = 0x17090,
2437 .halt_check = BRANCH_HALT,
2438 .clkr = {
2439 .enable_reg = 0x17090,
2440 .enable_mask = BIT(0),
2441 .hw.init = &(const struct clk_init_data) {
2442 .name = "gcc_snoc_nssnoc_1_clk",
2443 .parent_hws = (const struct clk_hw*[]) {
2444 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
2445 },
2446 .num_parents = 1,
2447 .flags = CLK_SET_RATE_PARENT,
2448 .ops = &clk_branch2_ops,
2449 },
2450 },
2451 };
2452
2453 static struct clk_branch gcc_snoc_nssnoc_clk = {
2454 .halt_reg = 0x17084,
2455 .halt_check = BRANCH_HALT,
2456 .clkr = {
2457 .enable_reg = 0x17084,
2458 .enable_mask = BIT(0),
2459 .hw.init = &(const struct clk_init_data) {
2460 .name = "gcc_snoc_nssnoc_clk",
2461 .parent_hws = (const struct clk_hw*[]) {
2462 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
2463 },
2464 .num_parents = 1,
2465 .flags = CLK_SET_RATE_PARENT,
2466 .ops = &clk_branch2_ops,
2467 },
2468 },
2469 };
2470
2471 static struct clk_branch gcc_snoc_pcie3_1lane_1_m_clk = {
2472 .halt_reg = 0x2e050,
2473 .halt_check = BRANCH_HALT,
2474 .clkr = {
2475 .enable_reg = 0x2e050,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(const struct clk_init_data) {
2478 .name = "gcc_snoc_pcie3_1lane_1_m_clk",
2479 .parent_hws = (const struct clk_hw*[]) {
2480 &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
2481 },
2482 .num_parents = 1,
2483 .flags = CLK_SET_RATE_PARENT,
2484 .ops = &clk_branch2_ops,
2485 },
2486 },
2487 };
2488
2489 static struct clk_branch gcc_snoc_pcie3_1lane_1_s_clk = {
2490 .halt_reg = 0x2e0ac,
2491 .halt_check = BRANCH_HALT,
2492 .clkr = {
2493 .enable_reg = 0x2e0ac,
2494 .enable_mask = BIT(0),
2495 .hw.init = &(const struct clk_init_data) {
2496 .name = "gcc_snoc_pcie3_1lane_1_s_clk",
2497 .parent_hws = (const struct clk_hw*[]) {
2498 &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
2499 },
2500 .num_parents = 1,
2501 .flags = CLK_SET_RATE_PARENT,
2502 .ops = &clk_branch2_ops,
2503 },
2504 },
2505 };
2506
2507 static struct clk_branch gcc_snoc_pcie3_1lane_m_clk = {
2508 .halt_reg = 0x2e080,
2509 .halt_check = BRANCH_HALT,
2510 .clkr = {
2511 .enable_reg = 0x2e080,
2512 .enable_mask = BIT(0),
2513 .hw.init = &(const struct clk_init_data) {
2514 .name = "gcc_snoc_pcie3_1lane_m_clk",
2515 .parent_hws = (const struct clk_hw*[]) {
2516 &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
2517 },
2518 .num_parents = 1,
2519 .flags = CLK_SET_RATE_PARENT,
2520 .ops = &clk_branch2_ops,
2521 },
2522 },
2523 };
2524
2525 static struct clk_branch gcc_snoc_pcie3_1lane_s_clk = {
2526 .halt_reg = 0x2e04c,
2527 .halt_check = BRANCH_HALT,
2528 .clkr = {
2529 .enable_reg = 0x2e04c,
2530 .enable_mask = BIT(0),
2531 .hw.init = &(const struct clk_init_data) {
2532 .name = "gcc_snoc_pcie3_1lane_s_clk",
2533 .parent_hws = (const struct clk_hw*[]) {
2534 &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
2535 },
2536 .num_parents = 1,
2537 .flags = CLK_SET_RATE_PARENT,
2538 .ops = &clk_branch2_ops,
2539 },
2540 },
2541 };
2542
2543 static struct clk_branch gcc_snoc_pcie3_2lane_m_clk = {
2544 .halt_reg = 0x2e07c,
2545 .halt_check = BRANCH_HALT,
2546 .clkr = {
2547 .enable_reg = 0x2e07c,
2548 .enable_mask = BIT(0),
2549 .hw.init = &(const struct clk_init_data) {
2550 .name = "gcc_snoc_pcie3_2lane_m_clk",
2551 .parent_hws = (const struct clk_hw*[]) {
2552 &gcc_pcie3x2_axi_m_clk_src.clkr.hw,
2553 },
2554 .num_parents = 1,
2555 .flags = CLK_SET_RATE_PARENT,
2556 .ops = &clk_branch2_ops,
2557 },
2558 },
2559 };
2560
2561 static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
2562 .halt_reg = 0x2e048,
2563 .halt_check = BRANCH_HALT,
2564 .clkr = {
2565 .enable_reg = 0x2e048,
2566 .enable_mask = BIT(0),
2567 .hw.init = &(const struct clk_init_data) {
2568 .name = "gcc_snoc_pcie3_2lane_s_clk",
2569 .parent_hws = (const struct clk_hw*[]) {
2570 &gcc_pcie3x2_axi_s_clk_src.clkr.hw,
2571 },
2572 .num_parents = 1,
2573 .flags = CLK_SET_RATE_PARENT,
2574 .ops = &clk_branch2_ops,
2575 },
2576 },
2577 };
2578
2579 static struct clk_branch gcc_snoc_usb_clk = {
2580 .halt_reg = 0x2e058,
2581 .halt_check = BRANCH_HALT_VOTED,
2582 .clkr = {
2583 .enable_reg = 0x2e058,
2584 .enable_mask = BIT(0),
2585 .hw.init = &(const struct clk_init_data) {
2586 .name = "gcc_snoc_usb_clk",
2587 .parent_hws = (const struct clk_hw*[]) {
2588 &gcc_usb0_master_clk_src.clkr.hw,
2589 },
2590 .num_parents = 1,
2591 .flags = CLK_SET_RATE_PARENT,
2592 .ops = &clk_branch2_ops,
2593 },
2594 },
2595 };
2596
2597 static struct clk_branch gcc_sys_noc_at_clk = {
2598 .halt_reg = 0x2e038,
2599 .halt_check = BRANCH_HALT_VOTED,
2600 .clkr = {
2601 .enable_reg = 0x2e038,
2602 .enable_mask = BIT(0),
2603 .hw.init = &(const struct clk_init_data) {
2604 .name = "gcc_sys_noc_at_clk",
2605 .parent_hws = (const struct clk_hw*[]) {
2606 &gcc_qdss_at_clk_src.clkr.hw,
2607 },
2608 .num_parents = 1,
2609 .flags = CLK_SET_RATE_PARENT,
2610 .ops = &clk_branch2_ops,
2611 },
2612 },
2613 };
2614
2615 static struct clk_branch gcc_uniphy0_ahb_clk = {
2616 .halt_reg = 0x16010,
2617 .halt_check = BRANCH_HALT,
2618 .clkr = {
2619 .enable_reg = 0x16010,
2620 .enable_mask = BIT(0),
2621 .hw.init = &(const struct clk_init_data) {
2622 .name = "gcc_uniphy0_ahb_clk",
2623 .parent_hws = (const struct clk_hw*[]) {
2624 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2625 },
2626 .num_parents = 1,
2627 .flags = CLK_SET_RATE_PARENT,
2628 .ops = &clk_branch2_ops,
2629 },
2630 },
2631 };
2632
2633 static struct clk_branch gcc_uniphy0_sys_clk = {
2634 .halt_reg = 0x1600c,
2635 .halt_check = BRANCH_HALT,
2636 .clkr = {
2637 .enable_reg = 0x1600c,
2638 .enable_mask = BIT(0),
2639 .hw.init = &(const struct clk_init_data) {
2640 .name = "gcc_uniphy0_sys_clk",
2641 .parent_hws = (const struct clk_hw*[]) {
2642 &gcc_uniphy_sys_clk_src.clkr.hw,
2643 },
2644 .num_parents = 1,
2645 .flags = CLK_SET_RATE_PARENT,
2646 .ops = &clk_branch2_ops,
2647 },
2648 },
2649 };
2650
2651 static struct clk_branch gcc_uniphy1_ahb_clk = {
2652 .halt_reg = 0x1601c,
2653 .halt_check = BRANCH_HALT,
2654 .clkr = {
2655 .enable_reg = 0x1601c,
2656 .enable_mask = BIT(0),
2657 .hw.init = &(const struct clk_init_data) {
2658 .name = "gcc_uniphy1_ahb_clk",
2659 .parent_hws = (const struct clk_hw*[]) {
2660 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2661 },
2662 .num_parents = 1,
2663 .flags = CLK_SET_RATE_PARENT,
2664 .ops = &clk_branch2_ops,
2665 },
2666 },
2667 };
2668
2669 static struct clk_branch gcc_uniphy1_sys_clk = {
2670 .halt_reg = 0x16018,
2671 .halt_check = BRANCH_HALT,
2672 .clkr = {
2673 .enable_reg = 0x16018,
2674 .enable_mask = BIT(0),
2675 .hw.init = &(const struct clk_init_data) {
2676 .name = "gcc_uniphy1_sys_clk",
2677 .parent_hws = (const struct clk_hw*[]) {
2678 &gcc_uniphy_sys_clk_src.clkr.hw,
2679 },
2680 .num_parents = 1,
2681 .flags = CLK_SET_RATE_PARENT,
2682 .ops = &clk_branch2_ops,
2683 },
2684 },
2685 };
2686
2687 static struct clk_branch gcc_usb0_aux_clk = {
2688 .halt_reg = 0x2c050,
2689 .halt_check = BRANCH_HALT_VOTED,
2690 .clkr = {
2691 .enable_reg = 0x2c050,
2692 .enable_mask = BIT(0),
2693 .hw.init = &(const struct clk_init_data) {
2694 .name = "gcc_usb0_aux_clk",
2695 .parent_hws = (const struct clk_hw*[]) {
2696 &gcc_usb0_aux_clk_src.clkr.hw,
2697 },
2698 .num_parents = 1,
2699 .flags = CLK_SET_RATE_PARENT,
2700 .ops = &clk_branch2_ops,
2701 },
2702 },
2703 };
2704
2705 static struct clk_branch gcc_usb0_eud_at_clk = {
2706 .halt_reg = 0x30004,
2707 .halt_check = BRANCH_HALT_VOTED,
2708 .clkr = {
2709 .enable_reg = 0x30004,
2710 .enable_mask = BIT(0),
2711 .hw.init = &(const struct clk_init_data) {
2712 .name = "gcc_usb0_eud_at_clk",
2713 .parent_hws = (const struct clk_hw*[]) {
2714 &gcc_eud_at_div_clk_src.hw,
2715 },
2716 .num_parents = 1,
2717 .flags = CLK_SET_RATE_PARENT,
2718 .ops = &clk_branch2_ops,
2719 },
2720 },
2721 };
2722
2723 static struct clk_branch gcc_usb0_lfps_clk = {
2724 .halt_reg = 0x2c090,
2725 .halt_check = BRANCH_HALT_VOTED,
2726 .clkr = {
2727 .enable_reg = 0x2c090,
2728 .enable_mask = BIT(0),
2729 .hw.init = &(const struct clk_init_data) {
2730 .name = "gcc_usb0_lfps_clk",
2731 .parent_hws = (const struct clk_hw*[]) {
2732 &gcc_usb0_lfps_clk_src.clkr.hw,
2733 },
2734 .num_parents = 1,
2735 .flags = CLK_SET_RATE_PARENT,
2736 .ops = &clk_branch2_ops,
2737 },
2738 },
2739 };
2740
2741 static struct clk_branch gcc_usb0_master_clk = {
2742 .halt_reg = 0x2c048,
2743 .halt_check = BRANCH_HALT_VOTED,
2744 .clkr = {
2745 .enable_reg = 0x2c048,
2746 .enable_mask = BIT(0),
2747 .hw.init = &(const struct clk_init_data) {
2748 .name = "gcc_usb0_master_clk",
2749 .parent_hws = (const struct clk_hw*[]) {
2750 &gcc_usb0_master_clk_src.clkr.hw,
2751 },
2752 .num_parents = 1,
2753 .flags = CLK_SET_RATE_PARENT,
2754 .ops = &clk_branch2_ops,
2755 },
2756 },
2757 };
2758
2759 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2760 .halt_reg = 0x2c054,
2761 .clkr = {
2762 .enable_reg = 0x2c054,
2763 .enable_mask = BIT(0),
2764 .hw.init = &(const struct clk_init_data) {
2765 .name = "gcc_usb0_mock_utmi_clk",
2766 .parent_hws = (const struct clk_hw*[]) {
2767 &gcc_usb0_mock_utmi_div_clk_src.clkr.hw,
2768 },
2769 .num_parents = 1,
2770 .flags = CLK_SET_RATE_PARENT,
2771 .ops = &clk_branch2_ops,
2772 },
2773 },
2774 };
2775
2776 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2777 .halt_reg = 0x2c05c,
2778 .halt_check = BRANCH_HALT_VOTED,
2779 .clkr = {
2780 .enable_reg = 0x2c05c,
2781 .enable_mask = BIT(0),
2782 .hw.init = &(const struct clk_init_data) {
2783 .name = "gcc_usb0_phy_cfg_ahb_clk",
2784 .parent_hws = (const struct clk_hw*[]) {
2785 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2786 },
2787 .num_parents = 1,
2788 .flags = CLK_SET_RATE_PARENT,
2789 .ops = &clk_branch2_ops,
2790 },
2791 },
2792 };
2793
2794 static struct clk_branch gcc_usb0_pipe_clk = {
2795 .halt_reg = 0x2c078,
2796 .halt_check = BRANCH_HALT_DELAY,
2797 .clkr = {
2798 .enable_reg = 0x2c078,
2799 .enable_mask = BIT(0),
2800 .hw.init = &(const struct clk_init_data) {
2801 .name = "gcc_usb0_pipe_clk",
2802 .parent_hws = (const struct clk_hw*[]) {
2803 &gcc_usb0_pipe_clk_src.clkr.hw,
2804 },
2805 .num_parents = 1,
2806 .flags = CLK_SET_RATE_PARENT,
2807 .ops = &clk_branch2_ops,
2808 },
2809 },
2810 };
2811
2812 static struct clk_branch gcc_usb0_sleep_clk = {
2813 .halt_reg = 0x2c058,
2814 .halt_check = BRANCH_HALT_VOTED,
2815 .clkr = {
2816 .enable_reg = 0x2c058,
2817 .enable_mask = BIT(0),
2818 .hw.init = &(const struct clk_init_data) {
2819 .name = "gcc_usb0_sleep_clk",
2820 .parent_hws = (const struct clk_hw*[]) {
2821 &gcc_sleep_clk_src.clkr.hw,
2822 },
2823 .num_parents = 1,
2824 .flags = CLK_SET_RATE_PARENT,
2825 .ops = &clk_branch2_ops,
2826 },
2827 },
2828 };
2829
2830 static struct clk_branch gcc_xo_clk = {
2831 .halt_reg = 0x34018,
2832 .halt_check = BRANCH_HALT,
2833 .clkr = {
2834 .enable_reg = 0x34018,
2835 .enable_mask = BIT(0),
2836 .hw.init = &(const struct clk_init_data) {
2837 .name = "gcc_xo_clk",
2838 .parent_hws = (const struct clk_hw*[]) {
2839 &gcc_xo_clk_src.clkr.hw,
2840 },
2841 .num_parents = 1,
2842 .flags = CLK_SET_RATE_PARENT,
2843 .ops = &clk_branch2_ops,
2844 },
2845 },
2846 };
2847
2848 static struct clk_branch gcc_xo_div4_clk = {
2849 .halt_reg = 0x3401c,
2850 .halt_check = BRANCH_HALT,
2851 .clkr = {
2852 .enable_reg = 0x3401c,
2853 .enable_mask = BIT(0),
2854 .hw.init = &(const struct clk_init_data) {
2855 .name = "gcc_xo_div4_clk",
2856 .parent_hws = (const struct clk_hw*[]) {
2857 &gcc_xo_div4_clk_src.hw,
2858 },
2859 .num_parents = 1,
2860 .flags = CLK_SET_RATE_PARENT,
2861 .ops = &clk_branch2_ops,
2862 },
2863 },
2864 };
2865
2866 static struct clk_branch gcc_im_sleep_clk = {
2867 .halt_reg = 0x34020,
2868 .halt_check = BRANCH_HALT,
2869 .clkr = {
2870 .enable_reg = 0x34020,
2871 .enable_mask = BIT(0),
2872 .hw.init = &(const struct clk_init_data) {
2873 .name = "gcc_im_sleep_clk",
2874 .parent_hws = (const struct clk_hw*[]) {
2875 &gcc_sleep_clk_src.clkr.hw,
2876 },
2877 .num_parents = 1,
2878 .flags = CLK_SET_RATE_PARENT,
2879 .ops = &clk_branch2_ops,
2880 },
2881 },
2882 };
2883
2884 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
2885 .halt_reg = 0x17080,
2886 .halt_check = BRANCH_HALT,
2887 .clkr = {
2888 .enable_reg = 0x17080,
2889 .enable_mask = BIT(0),
2890 .hw.init = &(const struct clk_init_data) {
2891 .name = "gcc_nssnoc_pcnoc_1_clk",
2892 .parent_hws = (const struct clk_hw*[]) {
2893 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2894 },
2895 .num_parents = 1,
2896 .flags = CLK_SET_RATE_PARENT,
2897 .ops = &clk_branch2_ops,
2898 },
2899 },
2900 };
2901
2902 static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
2903 .reg = 0x2e010,
2904 .shift = 0,
2905 .width = 2,
2906 .clkr.hw.init = &(const struct clk_init_data) {
2907 .name = "gcc_snoc_qosgen_extref_div_clk_src",
2908 .parent_hws = (const struct clk_hw*[]) {
2909 &gcc_xo_clk_src.clkr.hw,
2910 },
2911 .num_parents = 1,
2912 .flags = CLK_SET_RATE_PARENT,
2913 .ops = &clk_regmap_div_ro_ops,
2914 },
2915 };
2916
2917 static struct clk_regmap *gcc_ipq5332_clocks[] = {
2918 [GPLL0_MAIN] = &gpll0_main.clkr,
2919 [GPLL0] = &gpll0.clkr,
2920 [GPLL2_MAIN] = &gpll2_main.clkr,
2921 [GPLL2] = &gpll2.clkr,
2922 [GPLL4_MAIN] = &gpll4_main.clkr,
2923 [GPLL4] = &gpll4.clkr,
2924 [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
2925 [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
2926 [GCC_AHB_CLK] = &gcc_ahb_clk.clkr,
2927 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2928 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2929 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2930 [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup1_spi_apps_clk_src.clkr,
2931 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2932 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2933 [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup2_spi_apps_clk_src.clkr,
2934 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2935 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2936 [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup3_spi_apps_clk_src.clkr,
2937 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
2938 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2939 [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
2940 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2941 [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
2942 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2943 [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
2944 [GCC_CE_AHB_CLK] = &gcc_ce_ahb_clk.clkr,
2945 [GCC_CE_AXI_CLK] = &gcc_ce_axi_clk.clkr,
2946 [GCC_CE_PCNOC_AHB_CLK] = &gcc_ce_pcnoc_ahb_clk.clkr,
2947 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
2948 [GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
2949 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
2950 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2951 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2952 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2953 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2954 [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
2955 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
2956 [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
2957 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
2958 [GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr,
2959 [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
2960 [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
2961 [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
2962 [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
2963 [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
2964 [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
2965 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
2966 [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
2967 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
2968 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
2969 [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
2970 [GCC_PCIE3X1_0_AHB_CLK] = &gcc_pcie3x1_0_ahb_clk.clkr,
2971 [GCC_PCIE3X1_0_AUX_CLK] = &gcc_pcie3x1_0_aux_clk.clkr,
2972 [GCC_PCIE3X1_0_AXI_CLK_SRC] = &gcc_pcie3x1_0_axi_clk_src.clkr,
2973 [GCC_PCIE3X1_0_AXI_M_CLK] = &gcc_pcie3x1_0_axi_m_clk.clkr,
2974 [GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_0_axi_s_bridge_clk.clkr,
2975 [GCC_PCIE3X1_0_AXI_S_CLK] = &gcc_pcie3x1_0_axi_s_clk.clkr,
2976 [GCC_PCIE3X1_0_PIPE_CLK] = &gcc_pcie3x1_0_pipe_clk.clkr,
2977 [GCC_PCIE3X1_0_RCHG_CLK] = &gcc_pcie3x1_0_rchg_clk.clkr,
2978 [GCC_PCIE3X1_0_RCHG_CLK_SRC] = &gcc_pcie3x1_0_rchg_clk_src.clkr,
2979 [GCC_PCIE3X1_1_AHB_CLK] = &gcc_pcie3x1_1_ahb_clk.clkr,
2980 [GCC_PCIE3X1_1_AUX_CLK] = &gcc_pcie3x1_1_aux_clk.clkr,
2981 [GCC_PCIE3X1_1_AXI_CLK_SRC] = &gcc_pcie3x1_1_axi_clk_src.clkr,
2982 [GCC_PCIE3X1_1_AXI_M_CLK] = &gcc_pcie3x1_1_axi_m_clk.clkr,
2983 [GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_1_axi_s_bridge_clk.clkr,
2984 [GCC_PCIE3X1_1_AXI_S_CLK] = &gcc_pcie3x1_1_axi_s_clk.clkr,
2985 [GCC_PCIE3X1_1_PIPE_CLK] = &gcc_pcie3x1_1_pipe_clk.clkr,
2986 [GCC_PCIE3X1_1_RCHG_CLK] = &gcc_pcie3x1_1_rchg_clk.clkr,
2987 [GCC_PCIE3X1_1_RCHG_CLK_SRC] = &gcc_pcie3x1_1_rchg_clk_src.clkr,
2988 [GCC_PCIE3X1_PHY_AHB_CLK] = &gcc_pcie3x1_phy_ahb_clk.clkr,
2989 [GCC_PCIE3X2_AHB_CLK] = &gcc_pcie3x2_ahb_clk.clkr,
2990 [GCC_PCIE3X2_AUX_CLK] = &gcc_pcie3x2_aux_clk.clkr,
2991 [GCC_PCIE3X2_AXI_M_CLK] = &gcc_pcie3x2_axi_m_clk.clkr,
2992 [GCC_PCIE3X2_AXI_M_CLK_SRC] = &gcc_pcie3x2_axi_m_clk_src.clkr,
2993 [GCC_PCIE3X2_AXI_S_BRIDGE_CLK] = &gcc_pcie3x2_axi_s_bridge_clk.clkr,
2994 [GCC_PCIE3X2_AXI_S_CLK] = &gcc_pcie3x2_axi_s_clk.clkr,
2995 [GCC_PCIE3X2_AXI_S_CLK_SRC] = &gcc_pcie3x2_axi_s_clk_src.clkr,
2996 [GCC_PCIE3X2_PHY_AHB_CLK] = &gcc_pcie3x2_phy_ahb_clk.clkr,
2997 [GCC_PCIE3X2_PIPE_CLK] = &gcc_pcie3x2_pipe_clk.clkr,
2998 [GCC_PCIE3X2_RCHG_CLK] = &gcc_pcie3x2_rchg_clk.clkr,
2999 [GCC_PCIE3X2_RCHG_CLK_SRC] = &gcc_pcie3x2_rchg_clk_src.clkr,
3000 [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
3001 [GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
3002 [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr,
3003 [GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
3004 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3005 [GCC_Q6_AXIM_CLK_SRC] = &gcc_q6_axim_clk_src.clkr,
3006 [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
3007 [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr,
3008 [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
3009 [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
3010 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3011 [GCC_QDSS_DAP_DIV_CLK_SRC] = &gcc_qdss_dap_div_clk_src.clkr,
3012 [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
3013 [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
3014 [GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr,
3015 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
3016 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
3017 [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
3018 [GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr,
3019 [GCC_QPIC_SLEEP_CLK] = &gcc_qpic_sleep_clk.clkr,
3020 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3021 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3022 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3023 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3024 [GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
3025 [GCC_SNOC_NSSNOC_1_CLK] = &gcc_snoc_nssnoc_1_clk.clkr,
3026 [GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
3027 [GCC_SNOC_PCIE3_1LANE_1_M_CLK] = &gcc_snoc_pcie3_1lane_1_m_clk.clkr,
3028 [GCC_SNOC_PCIE3_1LANE_1_S_CLK] = &gcc_snoc_pcie3_1lane_1_s_clk.clkr,
3029 [GCC_SNOC_PCIE3_1LANE_M_CLK] = &gcc_snoc_pcie3_1lane_m_clk.clkr,
3030 [GCC_SNOC_PCIE3_1LANE_S_CLK] = &gcc_snoc_pcie3_1lane_s_clk.clkr,
3031 [GCC_SNOC_PCIE3_2LANE_M_CLK] = &gcc_snoc_pcie3_2lane_m_clk.clkr,
3032 [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
3033 [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
3034 [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
3035 [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr,
3036 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
3037 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
3038 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
3039 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
3040 [GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr,
3041 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
3042 [GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr,
3043 [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
3044 [GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
3045 [GCC_USB0_LFPS_CLK_SRC] = &gcc_usb0_lfps_clk_src.clkr,
3046 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
3047 [GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr,
3048 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
3049 [GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr,
3050 [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr,
3051 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
3052 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
3053 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
3054 [GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr,
3055 [GCC_XO_CLK] = &gcc_xo_clk.clkr,
3056 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
3057 [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
3058 [GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr,
3059 [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
3060 [GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr,
3061 [GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr,
3062 [GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,
3063 [GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,
3064 [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,
3065 };
3066
3067 static const struct qcom_reset_map gcc_ipq5332_resets[] = {
3068 [GCC_ADSS_BCR] = { 0x1c000 },
3069 [GCC_ADSS_PWM_CLK_ARES] = { 0x1c00c, 2 },
3070 [GCC_AHB_CLK_ARES] = { 0x34024, 2 },
3071 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 },
3072 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] = { 0x3800c, 2 },
3073 [GCC_APSS_AHB_CLK_ARES] = { 0x24018, 2 },
3074 [GCC_APSS_AXI_CLK_ARES] = { 0x2401c, 2 },
3075 [GCC_BLSP1_AHB_CLK_ARES] = { 0x1008, 2 },
3076 [GCC_BLSP1_BCR] = { 0x1000 },
3077 [GCC_BLSP1_QUP1_BCR] = { 0x2000 },
3078 [GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES] = { 0x2024, 2 },
3079 [GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES] = { 0x2020, 2 },
3080 [GCC_BLSP1_QUP2_BCR] = { 0x3000 },
3081 [GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES] = { 0x3024, 2 },
3082 [GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES] = { 0x3020, 2 },
3083 [GCC_BLSP1_QUP3_BCR] = { 0x4000 },
3084 [GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES] = { 0x4024, 2 },
3085 [GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES] = { 0x4020, 2 },
3086 [GCC_BLSP1_SLEEP_CLK_ARES] = { 0x1010, 2 },
3087 [GCC_BLSP1_UART1_APPS_CLK_ARES] = { 0x2040, 2 },
3088 [GCC_BLSP1_UART1_BCR] = { 0x2028 },
3089 [GCC_BLSP1_UART2_APPS_CLK_ARES] = { 0x3040, 2 },
3090 [GCC_BLSP1_UART2_BCR] = { 0x3028 },
3091 [GCC_BLSP1_UART3_APPS_CLK_ARES] = { 0x4054, 2 },
3092 [GCC_BLSP1_UART3_BCR] = { 0x4028 },
3093 [GCC_CE_BCR] = { 0x18008 },
3094 [GCC_CMN_BLK_BCR] = { 0x3a000 },
3095 [GCC_CMN_LDO0_BCR] = { 0x1d000 },
3096 [GCC_CMN_LDO1_BCR] = { 0x1d008 },
3097 [GCC_DCC_BCR] = { 0x35000 },
3098 [GCC_GP1_CLK_ARES] = { 0x8018, 2 },
3099 [GCC_GP2_CLK_ARES] = { 0x9018, 2 },
3100 [GCC_LPASS_BCR] = { 0x27000 },
3101 [GCC_LPASS_CORE_AXIM_CLK_ARES] = { 0x27018, 2 },
3102 [GCC_LPASS_SWAY_CLK_ARES] = { 0x27014, 2 },
3103 [GCC_MDIOM_BCR] = { 0x12000 },
3104 [GCC_MDIOS_BCR] = { 0x12008 },
3105 [GCC_NSS_BCR] = { 0x17000 },
3106 [GCC_NSS_TS_CLK_ARES] = { 0x17018, 2 },
3107 [GCC_NSSCC_CLK_ARES] = { 0x17034, 2 },
3108 [GCC_NSSCFG_CLK_ARES] = { 0x1702c, 2 },
3109 [GCC_NSSNOC_ATB_CLK_ARES] = { 0x17014, 2 },
3110 [GCC_NSSNOC_NSSCC_CLK_ARES] = { 0x17030, 2 },
3111 [GCC_NSSNOC_QOSGEN_REF_CLK_ARES] = { 0x1701c, 2 },
3112 [GCC_NSSNOC_SNOC_1_CLK_ARES] = { 0x1707c, 2 },
3113 [GCC_NSSNOC_SNOC_CLK_ARES] = { 0x17028, 2 },
3114 [GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] = { 0x17020, 2 },
3115 [GCC_NSSNOC_XO_DCD_CLK_ARES] = { 0x17074, 2 },
3116 [GCC_PCIE3X1_0_AHB_CLK_ARES] = { 0x29030, 2 },
3117 [GCC_PCIE3X1_0_AUX_CLK_ARES] = { 0x29070, 2 },
3118 [GCC_PCIE3X1_0_AXI_M_CLK_ARES] = { 0x29038, 2 },
3119 [GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES] = { 0x29048, 2 },
3120 [GCC_PCIE3X1_0_AXI_S_CLK_ARES] = { 0x29040, 2 },
3121 [GCC_PCIE3X1_0_BCR] = { 0x29000 },
3122 [GCC_PCIE3X1_0_LINK_DOWN_BCR] = { 0x29054 },
3123 [GCC_PCIE3X1_0_PHY_BCR] = { 0x29060 },
3124 [GCC_PCIE3X1_0_PHY_PHY_BCR] = { 0x2905c },
3125 [GCC_PCIE3X1_1_AHB_CLK_ARES] = { 0x2a00c, 2 },
3126 [GCC_PCIE3X1_1_AUX_CLK_ARES] = { 0x2a070, 2 },
3127 [GCC_PCIE3X1_1_AXI_M_CLK_ARES] = { 0x2a014, 2 },
3128 [GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES] = { 0x2a024, 2 },
3129 [GCC_PCIE3X1_1_AXI_S_CLK_ARES] = { 0x2a01c, 2 },
3130 [GCC_PCIE3X1_1_BCR] = { 0x2a000 },
3131 [GCC_PCIE3X1_1_LINK_DOWN_BCR] = { 0x2a028 },
3132 [GCC_PCIE3X1_1_PHY_BCR] = { 0x2a030 },
3133 [GCC_PCIE3X1_1_PHY_PHY_BCR] = { 0x2a02c },
3134 [GCC_PCIE3X1_PHY_AHB_CLK_ARES] = { 0x29078, 2 },
3135 [GCC_PCIE3X2_AHB_CLK_ARES] = { 0x28030, 2 },
3136 [GCC_PCIE3X2_AUX_CLK_ARES] = { 0x28070, 2 },
3137 [GCC_PCIE3X2_AXI_M_CLK_ARES] = { 0x28038, 2 },
3138 [GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES] = { 0x28048, 2 },
3139 [GCC_PCIE3X2_AXI_S_CLK_ARES] = { 0x28040, 2 },
3140 [GCC_PCIE3X2_BCR] = { 0x28000 },
3141 [GCC_PCIE3X2_LINK_DOWN_BCR] = { 0x28054 },
3142 [GCC_PCIE3X2_PHY_AHB_CLK_ARES] = { 0x28080, 2 },
3143 [GCC_PCIE3X2_PHY_BCR] = { 0x28060 },
3144 [GCC_PCIE3X2PHY_PHY_BCR] = { 0x2805c },
3145 [GCC_PCNOC_BCR] = { 0x31000 },
3146 [GCC_PCNOC_LPASS_CLK_ARES] = { 0x31020, 2 },
3147 [GCC_PRNG_AHB_CLK_ARES] = { 0x13024, 2 },
3148 [GCC_PRNG_BCR] = { 0x13020 },
3149 [GCC_Q6_AHB_CLK_ARES] = { 0x25014, 2 },
3150 [GCC_Q6_AHB_S_CLK_ARES] = { 0x25018, 2 },
3151 [GCC_Q6_AXIM_CLK_ARES] = { 0x2500c, 2 },
3152 [GCC_Q6_AXIS_CLK_ARES] = { 0x25010, 2 },
3153 [GCC_Q6_TSCTR_1TO2_CLK_ARES] = { 0x25020, 2 },
3154 [GCC_Q6SS_ATBM_CLK_ARES] = { 0x2501c, 2 },
3155 [GCC_Q6SS_PCLKDBG_CLK_ARES] = { 0x25024, 2 },
3156 [GCC_Q6SS_TRIG_CLK_ARES] = { 0x250a0, 2 },
3157 [GCC_QDSS_APB2JTAG_CLK_ARES] = { 0x2d060, 2 },
3158 [GCC_QDSS_AT_CLK_ARES] = { 0x2d038, 2 },
3159 [GCC_QDSS_BCR] = { 0x2d000 },
3160 [GCC_QDSS_CFG_AHB_CLK_ARES] = { 0x2d06c, 2 },
3161 [GCC_QDSS_DAP_AHB_CLK_ARES] = { 0x2d068, 2 },
3162 [GCC_QDSS_DAP_CLK_ARES] = { 0x2d05c, 2 },
3163 [GCC_QDSS_ETR_USB_CLK_ARES] = { 0x2d064, 2 },
3164 [GCC_QDSS_EUD_AT_CLK_ARES] = { 0x2d070, 2 },
3165 [GCC_QDSS_STM_CLK_ARES] = { 0x2d040, 2 },
3166 [GCC_QDSS_TRACECLKIN_CLK_ARES] = { 0x2d044, 2 },
3167 [GCC_QDSS_TS_CLK_ARES] = { 0x2d078, 2 },
3168 [GCC_QDSS_TSCTR_DIV16_CLK_ARES] = { 0x2d058, 2 },
3169 [GCC_QDSS_TSCTR_DIV2_CLK_ARES] = { 0x2d048, 2 },
3170 [GCC_QDSS_TSCTR_DIV3_CLK_ARES] = { 0x2d04c, 2 },
3171 [GCC_QDSS_TSCTR_DIV4_CLK_ARES] = { 0x2d050, 2 },
3172 [GCC_QDSS_TSCTR_DIV8_CLK_ARES] = { 0x2d054, 2 },
3173 [GCC_QPIC_AHB_CLK_ARES] = { 0x32010, 2 },
3174 [GCC_QPIC_CLK_ARES] = { 0x32014, 2 },
3175 [GCC_QPIC_BCR] = { 0x32000 },
3176 [GCC_QPIC_IO_MACRO_CLK_ARES] = { 0x3200c, 2 },
3177 [GCC_QPIC_SLEEP_CLK_ARES] = { 0x3201c, 2 },
3178 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },
3179 [GCC_SDCC1_AHB_CLK_ARES] = { 0x33034, 2 },
3180 [GCC_SDCC1_APPS_CLK_ARES] = { 0x3302c, 2 },
3181 [GCC_SDCC_BCR] = { 0x33000 },
3182 [GCC_SNOC_BCR] = { 0x2e000 },
3183 [GCC_SNOC_LPASS_CFG_CLK_ARES] = { 0x2e028, 2 },
3184 [GCC_SNOC_NSSNOC_1_CLK_ARES] = { 0x17090, 2 },
3185 [GCC_SNOC_NSSNOC_CLK_ARES] = { 0x17084, 2 },
3186 [GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES] = { 0x2e034, 2 },
3187 [GCC_SYS_NOC_WCSS_AHB_CLK_ARES] = { 0x2e030, 2 },
3188 [GCC_UNIPHY0_AHB_CLK_ARES] = { 0x16010, 2 },
3189 [GCC_UNIPHY0_BCR] = { 0x16000 },
3190 [GCC_UNIPHY0_SYS_CLK_ARES] = { 0x1600c, 2 },
3191 [GCC_UNIPHY1_AHB_CLK_ARES] = { 0x1601c, 2 },
3192 [GCC_UNIPHY1_BCR] = { 0x16014 },
3193 [GCC_UNIPHY1_SYS_CLK_ARES] = { 0x16018, 2 },
3194 [GCC_USB0_AUX_CLK_ARES] = { 0x2c050, 2 },
3195 [GCC_USB0_EUD_AT_CLK_ARES] = { 0x30004, 2 },
3196 [GCC_USB0_LFPS_CLK_ARES] = { 0x2c090, 2 },
3197 [GCC_USB0_MASTER_CLK_ARES] = { 0x2c048, 2 },
3198 [GCC_USB0_MOCK_UTMI_CLK_ARES] = { 0x2c054, 2 },
3199 [GCC_USB0_PHY_BCR] = { 0x2c06c },
3200 [GCC_USB0_PHY_CFG_AHB_CLK_ARES] = { 0x2c05c, 2 },
3201 [GCC_USB0_SLEEP_CLK_ARES] = { 0x2c058, 2 },
3202 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 },
3203 [GCC_USB_BCR] = { 0x2c000 },
3204 [GCC_WCSS_AXIM_CLK_ARES] = { 0x2505c, 2 },
3205 [GCC_WCSS_AXIS_CLK_ARES] = { 0x25060, 2 },
3206 [GCC_WCSS_BCR] = { 0x18004 },
3207 [GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES] = { 0x25048, 2 },
3208 [GCC_WCSS_DBG_IFC_APB_CLK_ARES] = { 0x25038, 2 },
3209 [GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES] = { 0x2504c, 2 },
3210 [GCC_WCSS_DBG_IFC_ATB_CLK_ARES] = { 0x2503c, 2 },
3211 [GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES] = { 0x25050, 2 },
3212 [GCC_WCSS_DBG_IFC_NTS_CLK_ARES] = { 0x25040, 2 },
3213 [GCC_WCSS_ECAHB_CLK_ARES] = { 0x25058, 2 },
3214 [GCC_WCSS_MST_ASYNC_BDG_CLK_ARES] = { 0x2e0b0, 2 },
3215 [GCC_WCSS_Q6_BCR] = { 0x18000 },
3216 [GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES] = { 0x2e0b4, 2 },
3217 [GCC_XO_CLK_ARES] = { 0x34018, 2 },
3218 [GCC_XO_DIV4_CLK_ARES] = { 0x3401c, 2 },
3219 [GCC_Q6SS_DBG_ARES] = { 0x25094 },
3220 [GCC_WCSS_DBG_BDG_ARES] = { 0x25098, 0 },
3221 [GCC_WCSS_DBG_ARES] = { 0x25098, 1 },
3222 [GCC_WCSS_AXI_S_ARES] = { 0x25098, 2 },
3223 [GCC_WCSS_AXI_M_ARES] = { 0x25098, 3 },
3224 [GCC_WCSSAON_ARES] = { 0x2509C },
3225 [GCC_PCIE3X2_PIPE_ARES] = { 0x28058, 0 },
3226 [GCC_PCIE3X2_CORE_STICKY_ARES] = { 0x28058, 1 },
3227 [GCC_PCIE3X2_AXI_S_STICKY_ARES] = { 0x28058, 2 },
3228 [GCC_PCIE3X2_AXI_M_STICKY_ARES] = { 0x28058, 3 },
3229 [GCC_PCIE3X1_0_PIPE_ARES] = { 0x29058, 0 },
3230 [GCC_PCIE3X1_0_CORE_STICKY_ARES] = { 0x29058, 1 },
3231 [GCC_PCIE3X1_0_AXI_S_STICKY_ARES] = { 0x29058, 2 },
3232 [GCC_PCIE3X1_0_AXI_M_STICKY_ARES] = { 0x29058, 3 },
3233 [GCC_PCIE3X1_1_PIPE_ARES] = { 0x2a058, 0 },
3234 [GCC_PCIE3X1_1_CORE_STICKY_ARES] = { 0x2a058, 1 },
3235 [GCC_PCIE3X1_1_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
3236 [GCC_PCIE3X1_1_AXI_M_STICKY_ARES] = { 0x2a058, 3 },
3237 [GCC_IM_SLEEP_CLK_ARES] = { 0x34020, 2 },
3238 [GCC_NSSNOC_PCNOC_1_CLK_ARES] = { 0x17080, 2 },
3239 [GCC_UNIPHY0_XPCS_ARES] = { 0x16050 },
3240 [GCC_UNIPHY1_XPCS_ARES] = { 0x16060 },
3241 };
3242
3243 #define IPQ_APPS_ID 5332 /* some unique value */
3244
3245 static const struct qcom_icc_hws_data icc_ipq5332_hws[] = {
3246 { MASTER_SNOC_PCIE3_1_M, SLAVE_SNOC_PCIE3_1_M, GCC_SNOC_PCIE3_1LANE_M_CLK },
3247 { MASTER_ANOC_PCIE3_1_S, SLAVE_ANOC_PCIE3_1_S, GCC_SNOC_PCIE3_1LANE_S_CLK },
3248 { MASTER_SNOC_PCIE3_2_M, SLAVE_SNOC_PCIE3_2_M, GCC_SNOC_PCIE3_2LANE_M_CLK },
3249 { MASTER_ANOC_PCIE3_2_S, SLAVE_ANOC_PCIE3_2_S, GCC_SNOC_PCIE3_2LANE_S_CLK },
3250 { MASTER_SNOC_USB, SLAVE_SNOC_USB, GCC_SNOC_USB_CLK },
3251 { MASTER_NSSNOC_NSSCC, SLAVE_NSSNOC_NSSCC, GCC_NSSNOC_NSSCC_CLK },
3252 { MASTER_NSSNOC_SNOC_0, SLAVE_NSSNOC_SNOC_0, GCC_NSSNOC_SNOC_CLK },
3253 { MASTER_NSSNOC_SNOC_1, SLAVE_NSSNOC_SNOC_1, GCC_NSSNOC_SNOC_1_CLK },
3254 { MASTER_NSSNOC_ATB, SLAVE_NSSNOC_ATB, GCC_NSSNOC_ATB_CLK },
3255 { MASTER_NSSNOC_PCNOC_1, SLAVE_NSSNOC_PCNOC_1, GCC_NSSNOC_PCNOC_1_CLK },
3256 { MASTER_NSSNOC_QOSGEN_REF, SLAVE_NSSNOC_QOSGEN_REF, GCC_NSSNOC_QOSGEN_REF_CLK },
3257 { MASTER_NSSNOC_TIMEOUT_REF, SLAVE_NSSNOC_TIMEOUT_REF, GCC_NSSNOC_TIMEOUT_REF_CLK },
3258 { MASTER_NSSNOC_XO_DCD, SLAVE_NSSNOC_XO_DCD, GCC_NSSNOC_XO_DCD_CLK },
3259 };
3260
3261 static const struct regmap_config gcc_ipq5332_regmap_config = {
3262 .reg_bits = 32,
3263 .reg_stride = 4,
3264 .val_bits = 32,
3265 .max_register = 0x3f024,
3266 .fast_io = true,
3267 };
3268
3269 static struct clk_hw *gcc_ipq5332_hws[] = {
3270 &gpll0_div2.hw,
3271 &gcc_xo_div4_clk_src.hw,
3272 &gcc_system_noc_bfdcd_div2_clk_src.hw,
3273 &gcc_qdss_tsctr_div2_clk_src.hw,
3274 &gcc_qdss_tsctr_div3_clk_src.hw,
3275 &gcc_qdss_tsctr_div4_clk_src.hw,
3276 &gcc_qdss_tsctr_div8_clk_src.hw,
3277 &gcc_qdss_tsctr_div16_clk_src.hw,
3278 &gcc_eud_at_div_clk_src.hw,
3279 };
3280
3281 static const struct qcom_cc_desc gcc_ipq5332_desc = {
3282 .config = &gcc_ipq5332_regmap_config,
3283 .clks = gcc_ipq5332_clocks,
3284 .num_clks = ARRAY_SIZE(gcc_ipq5332_clocks),
3285 .resets = gcc_ipq5332_resets,
3286 .num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
3287 .clk_hws = gcc_ipq5332_hws,
3288 .num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
3289 .icc_hws = icc_ipq5332_hws,
3290 .num_icc_hws = ARRAY_SIZE(icc_ipq5332_hws),
3291 .icc_first_node_id = IPQ_APPS_ID,
3292 };
3293
gcc_ipq5332_probe(struct platform_device * pdev)3294 static int gcc_ipq5332_probe(struct platform_device *pdev)
3295 {
3296 return qcom_cc_probe(pdev, &gcc_ipq5332_desc);
3297 }
3298
3299 static const struct of_device_id gcc_ipq5332_match_table[] = {
3300 { .compatible = "qcom,ipq5332-gcc" },
3301 { }
3302 };
3303 MODULE_DEVICE_TABLE(of, gcc_ipq5332_match_table);
3304
3305 static struct platform_driver gcc_ipq5332_driver = {
3306 .probe = gcc_ipq5332_probe,
3307 .driver = {
3308 .name = "gcc-ipq5332",
3309 .of_match_table = gcc_ipq5332_match_table,
3310 .sync_state = icc_sync_state,
3311 },
3312 };
3313
gcc_ipq5332_init(void)3314 static int __init gcc_ipq5332_init(void)
3315 {
3316 return platform_driver_register(&gcc_ipq5332_driver);
3317 }
3318 core_initcall(gcc_ipq5332_init);
3319
gcc_ipq5332_exit(void)3320 static void __exit gcc_ipq5332_exit(void)
3321 {
3322 platform_driver_unregister(&gcc_ipq5332_driver);
3323 }
3324 module_exit(gcc_ipq5332_exit);
3325
3326 MODULE_DESCRIPTION("QTI GCC IPQ5332 Driver");
3327 MODULE_LICENSE("GPL");
3328