1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for GalaxyCore gc08a3 image sensor 4 * 5 * Copyright 2024 MediaTek 6 * 7 * Zhi Mao <zhi.mao@mediatek.com> 8 */ 9 #include <linux/array_size.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/container_of.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/math64.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/property.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/types.h> 22 #include <linux/units.h> 23 24 #include <media/v4l2-cci.h> 25 #include <media/v4l2-ctrls.h> 26 #include <media/v4l2-fwnode.h> 27 #include <media/v4l2-subdev.h> 28 29 #define GC08A3_REG_TEST_PATTERN_EN CCI_REG8(0x008c) 30 #define GC08A3_REG_TEST_PATTERN_IDX CCI_REG8(0x008d) 31 #define GC08A3_TEST_PATTERN_EN 0x01 32 33 #define GC08A3_STREAMING_REG CCI_REG8(0x0100) 34 35 #define GC08A3_FLIP_REG CCI_REG8(0x0101) 36 #define GC08A3_FLIP_H_MASK BIT(0) 37 #define GC08A3_FLIP_V_MASK BIT(1) 38 39 #define GC08A3_EXP_REG CCI_REG16(0x0202) 40 #define GC08A3_EXP_MARGIN 16 41 #define GC08A3_EXP_MIN 4 42 #define GC08A3_EXP_STEP 1 43 44 #define GC08A3_AGAIN_REG CCI_REG16(0x0204) 45 #define GC08A3_AGAIN_MIN 1024 46 #define GC08A3_AGAIN_MAX (1024 * 16) 47 #define GC08A3_AGAIN_STEP 1 48 49 #define GC08A3_FRAME_LENGTH_REG CCI_REG16(0x0340) 50 #define GC08A3_VTS_MAX 0xfff0 51 52 #define GC08A3_REG_CHIP_ID CCI_REG16(0x03f0) 53 #define GC08A3_CHIP_ID 0x08a3 54 55 #define GC08A3_NATIVE_WIDTH 3264 56 #define GC08A3_NATIVE_HEIGHT 2448 57 58 #define GC08A3_DEFAULT_CLK_FREQ (24 * HZ_PER_MHZ) 59 #define GC08A3_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10 60 #define GC08A3_DATA_LANES 4 61 62 #define GC08A3_RGB_DEPTH 10 63 64 #define GC08A3_SLEEP_US (2 * USEC_PER_MSEC) 65 66 static const char *const gc08a3_test_pattern_menu[] = { 67 "No Pattern", "Solid Black", "Colour Bar", "Solid White", 68 "Solid Red", "Solid Green", "Solid Blue", "Solid Yellow", 69 }; 70 71 static const s64 gc08a3_link_freq_menu_items[] = { 72 (336 * HZ_PER_MHZ), 73 (207 * HZ_PER_MHZ), 74 }; 75 76 static const char *const gc08a3_supply_name[] = { 77 "avdd", 78 "dvdd", 79 "dovdd", 80 }; 81 82 struct gc08a3 { 83 struct device *dev; 84 struct v4l2_subdev sd; 85 struct media_pad pad; 86 87 struct clk *xclk; 88 struct regulator_bulk_data supplies[ARRAY_SIZE(gc08a3_supply_name)]; 89 struct gpio_desc *reset_gpio; 90 91 struct v4l2_ctrl_handler ctrls; 92 struct v4l2_ctrl *pixel_rate; 93 struct v4l2_ctrl *link_freq; 94 struct v4l2_ctrl *exposure; 95 struct v4l2_ctrl *vblank; 96 struct v4l2_ctrl *hblank; 97 struct v4l2_ctrl *hflip; 98 struct v4l2_ctrl *vflip; 99 100 struct regmap *regmap; 101 unsigned long link_freq_bitmap; 102 const struct gc08a3_mode *cur_mode; 103 }; 104 105 struct gc08a3_reg_list { 106 u32 num_of_regs; 107 const struct cci_reg_sequence *regs; 108 }; 109 110 static const struct cci_reg_sequence mode_3264x2448[] = { 111 /* system */ 112 { CCI_REG8(0x0336), 0x70 }, 113 { CCI_REG8(0x0383), 0xbb }, 114 { CCI_REG8(0x0344), 0x00 }, 115 { CCI_REG8(0x0345), 0x06 }, 116 { CCI_REG8(0x0346), 0x00 }, 117 { CCI_REG8(0x0347), 0x04 }, 118 { CCI_REG8(0x0348), 0x0c }, 119 { CCI_REG8(0x0349), 0xd0 }, 120 { CCI_REG8(0x034a), 0x09 }, 121 { CCI_REG8(0x034b), 0x9c }, 122 { CCI_REG8(0x0202), 0x09 }, 123 { CCI_REG8(0x0203), 0x04 }, 124 { CCI_REG8(0x0340), 0x09 }, 125 { CCI_REG8(0x0341), 0xf4 }, 126 { CCI_REG8(0x0342), 0x07 }, 127 { CCI_REG8(0x0343), 0x1c }, 128 129 { CCI_REG8(0x0226), 0x00 }, 130 { CCI_REG8(0x0227), 0x28 }, 131 { CCI_REG8(0x0e38), 0x49 }, 132 { CCI_REG8(0x0210), 0x13 }, 133 { CCI_REG8(0x0218), 0x00 }, 134 { CCI_REG8(0x0241), 0x88 }, 135 { CCI_REG8(0x0392), 0x60 }, 136 137 /* ISP */ 138 { CCI_REG8(0x00a2), 0x00 }, 139 { CCI_REG8(0x00a3), 0x00 }, 140 { CCI_REG8(0x00ab), 0x00 }, 141 { CCI_REG8(0x00ac), 0x00 }, 142 143 /* GAIN */ 144 { CCI_REG8(0x0204), 0x04 }, 145 { CCI_REG8(0x0205), 0x00 }, 146 { CCI_REG8(0x0050), 0x5c }, 147 { CCI_REG8(0x0051), 0x44 }, 148 149 /* out window */ 150 { CCI_REG8(0x009a), 0x66 }, 151 { CCI_REG8(0x0351), 0x00 }, 152 { CCI_REG8(0x0352), 0x06 }, 153 { CCI_REG8(0x0353), 0x00 }, 154 { CCI_REG8(0x0354), 0x08 }, 155 { CCI_REG8(0x034c), 0x0c }, 156 { CCI_REG8(0x034d), 0xc0 }, 157 { CCI_REG8(0x034e), 0x09 }, 158 { CCI_REG8(0x034f), 0x90 }, 159 160 /* MIPI */ 161 { CCI_REG8(0x0114), 0x03 }, 162 { CCI_REG8(0x0180), 0x65 }, 163 { CCI_REG8(0x0181), 0xf0 }, 164 { CCI_REG8(0x0185), 0x01 }, 165 { CCI_REG8(0x0115), 0x30 }, 166 { CCI_REG8(0x011b), 0x12 }, 167 { CCI_REG8(0x011c), 0x12 }, 168 { CCI_REG8(0x0121), 0x06 }, 169 { CCI_REG8(0x0122), 0x06 }, 170 { CCI_REG8(0x0123), 0x15 }, 171 { CCI_REG8(0x0124), 0x01 }, 172 { CCI_REG8(0x0125), 0x0b }, 173 { CCI_REG8(0x0126), 0x08 }, 174 { CCI_REG8(0x0129), 0x06 }, 175 { CCI_REG8(0x012a), 0x08 }, 176 { CCI_REG8(0x012b), 0x08 }, 177 178 { CCI_REG8(0x0a73), 0x60 }, 179 { CCI_REG8(0x0a70), 0x11 }, 180 { CCI_REG8(0x0313), 0x80 }, 181 { CCI_REG8(0x0aff), 0x00 }, 182 { CCI_REG8(0x0a70), 0x00 }, 183 { CCI_REG8(0x00a4), 0x80 }, 184 { CCI_REG8(0x0316), 0x01 }, 185 { CCI_REG8(0x0a67), 0x00 }, 186 { CCI_REG8(0x0084), 0x10 }, 187 { CCI_REG8(0x0102), 0x09 }, 188 }; 189 190 static const struct cci_reg_sequence mode_1920x1080[] = { 191 /* system */ 192 { CCI_REG8(0x0336), 0x45 }, 193 { CCI_REG8(0x0383), 0x8b }, 194 { CCI_REG8(0x0344), 0x02 }, 195 { CCI_REG8(0x0345), 0xa6 }, 196 { CCI_REG8(0x0346), 0x02 }, 197 { CCI_REG8(0x0347), 0xb0 }, 198 { CCI_REG8(0x0348), 0x07 }, 199 { CCI_REG8(0x0349), 0x90 }, 200 { CCI_REG8(0x034a), 0x04 }, 201 { CCI_REG8(0x034b), 0x44 }, 202 { CCI_REG8(0x0202), 0x03 }, 203 { CCI_REG8(0x0203), 0x00 }, 204 { CCI_REG8(0x0340), 0x04 }, 205 { CCI_REG8(0x0341), 0xfc }, 206 { CCI_REG8(0x0342), 0x07 }, 207 { CCI_REG8(0x0343), 0x1c }, 208 { CCI_REG8(0x0226), 0x00 }, 209 { CCI_REG8(0x0227), 0x88 }, 210 { CCI_REG8(0x0e38), 0x49 }, 211 { CCI_REG8(0x0210), 0x13 }, 212 { CCI_REG8(0x0218), 0x00 }, 213 { CCI_REG8(0x0241), 0x88 }, 214 { CCI_REG8(0x0392), 0x60 }, 215 216 /* ISP */ 217 { CCI_REG8(0x00a2), 0xac }, 218 { CCI_REG8(0x00a3), 0x02 }, 219 { CCI_REG8(0x00ab), 0xa0 }, 220 { CCI_REG8(0x00ac), 0x02 }, 221 222 /* GAIN */ 223 { CCI_REG8(0x0204), 0x04 }, 224 { CCI_REG8(0x0205), 0x00 }, 225 { CCI_REG8(0x0050), 0x38 }, 226 { CCI_REG8(0x0051), 0x20 }, 227 228 /* out window */ 229 { CCI_REG8(0x009a), 0x66 }, 230 { CCI_REG8(0x0351), 0x00 }, 231 { CCI_REG8(0x0352), 0x06 }, 232 { CCI_REG8(0x0353), 0x00 }, 233 { CCI_REG8(0x0354), 0x08 }, 234 { CCI_REG8(0x034c), 0x07 }, 235 { CCI_REG8(0x034d), 0x80 }, 236 { CCI_REG8(0x034e), 0x04 }, 237 { CCI_REG8(0x034f), 0x38 }, 238 239 /* MIPI */ 240 { CCI_REG8(0x0114), 0x03 }, 241 { CCI_REG8(0x0180), 0x65 }, 242 { CCI_REG8(0x0181), 0xf0 }, 243 { CCI_REG8(0x0185), 0x01 }, 244 { CCI_REG8(0x0115), 0x30 }, 245 { CCI_REG8(0x011b), 0x12 }, 246 { CCI_REG8(0x011c), 0x12 }, 247 { CCI_REG8(0x0121), 0x02 }, 248 { CCI_REG8(0x0122), 0x03 }, 249 { CCI_REG8(0x0123), 0x0c }, 250 { CCI_REG8(0x0124), 0x00 }, 251 { CCI_REG8(0x0125), 0x09 }, 252 { CCI_REG8(0x0126), 0x06 }, 253 { CCI_REG8(0x0129), 0x04 }, 254 { CCI_REG8(0x012a), 0x03 }, 255 { CCI_REG8(0x012b), 0x06 }, 256 257 { CCI_REG8(0x0a73), 0x60 }, 258 { CCI_REG8(0x0a70), 0x11 }, 259 { CCI_REG8(0x0313), 0x80 }, 260 { CCI_REG8(0x0aff), 0x00 }, 261 { CCI_REG8(0x0a70), 0x00 }, 262 { CCI_REG8(0x00a4), 0x80 }, 263 { CCI_REG8(0x0316), 0x01 }, 264 { CCI_REG8(0x0a67), 0x00 }, 265 { CCI_REG8(0x0084), 0x10 }, 266 { CCI_REG8(0x0102), 0x09 }, 267 }; 268 269 static const struct cci_reg_sequence mode_table_common[] = { 270 { GC08A3_STREAMING_REG, 0x00 }, 271 /* system */ 272 { CCI_REG8(0x031c), 0x60 }, 273 { CCI_REG8(0x0337), 0x04 }, 274 { CCI_REG8(0x0335), 0x51 }, 275 { CCI_REG8(0x0336), 0x70 }, 276 { CCI_REG8(0x0383), 0xbb }, 277 { CCI_REG8(0x031a), 0x00 }, 278 { CCI_REG8(0x0321), 0x10 }, 279 { CCI_REG8(0x0327), 0x03 }, 280 { CCI_REG8(0x0325), 0x40 }, 281 { CCI_REG8(0x0326), 0x23 }, 282 { CCI_REG8(0x0314), 0x11 }, 283 { CCI_REG8(0x0315), 0xd6 }, 284 { CCI_REG8(0x0316), 0x01 }, 285 { CCI_REG8(0x0334), 0x40 }, 286 { CCI_REG8(0x0324), 0x42 }, 287 { CCI_REG8(0x031c), 0x00 }, 288 { CCI_REG8(0x031c), 0x9f }, 289 { CCI_REG8(0x039a), 0x13 }, 290 { CCI_REG8(0x0084), 0x30 }, 291 { CCI_REG8(0x02b3), 0x08 }, 292 { CCI_REG8(0x0057), 0x0c }, 293 { CCI_REG8(0x05c3), 0x50 }, 294 { CCI_REG8(0x0311), 0x90 }, 295 { CCI_REG8(0x05a0), 0x02 }, 296 { CCI_REG8(0x0074), 0x0a }, 297 { CCI_REG8(0x0059), 0x11 }, 298 { CCI_REG8(0x0070), 0x05 }, 299 { CCI_REG8(0x0101), 0x00 }, 300 301 /* analog */ 302 { CCI_REG8(0x0344), 0x00 }, 303 { CCI_REG8(0x0345), 0x06 }, 304 { CCI_REG8(0x0346), 0x00 }, 305 { CCI_REG8(0x0347), 0x04 }, 306 { CCI_REG8(0x0348), 0x0c }, 307 { CCI_REG8(0x0349), 0xd0 }, 308 { CCI_REG8(0x034a), 0x09 }, 309 { CCI_REG8(0x034b), 0x9c }, 310 { CCI_REG8(0x0202), 0x09 }, 311 { CCI_REG8(0x0203), 0x04 }, 312 313 { CCI_REG8(0x0219), 0x05 }, 314 { CCI_REG8(0x0226), 0x00 }, 315 { CCI_REG8(0x0227), 0x28 }, 316 { CCI_REG8(0x0e0a), 0x00 }, 317 { CCI_REG8(0x0e0b), 0x00 }, 318 { CCI_REG8(0x0e24), 0x04 }, 319 { CCI_REG8(0x0e25), 0x04 }, 320 { CCI_REG8(0x0e26), 0x00 }, 321 { CCI_REG8(0x0e27), 0x10 }, 322 { CCI_REG8(0x0e01), 0x74 }, 323 { CCI_REG8(0x0e03), 0x47 }, 324 { CCI_REG8(0x0e04), 0x33 }, 325 { CCI_REG8(0x0e05), 0x44 }, 326 { CCI_REG8(0x0e06), 0x44 }, 327 { CCI_REG8(0x0e0c), 0x1e }, 328 { CCI_REG8(0x0e17), 0x3a }, 329 { CCI_REG8(0x0e18), 0x3c }, 330 { CCI_REG8(0x0e19), 0x40 }, 331 { CCI_REG8(0x0e1a), 0x42 }, 332 { CCI_REG8(0x0e28), 0x21 }, 333 { CCI_REG8(0x0e2b), 0x68 }, 334 { CCI_REG8(0x0e2c), 0x0d }, 335 { CCI_REG8(0x0e2d), 0x08 }, 336 { CCI_REG8(0x0e34), 0xf4 }, 337 { CCI_REG8(0x0e35), 0x44 }, 338 { CCI_REG8(0x0e36), 0x07 }, 339 { CCI_REG8(0x0e38), 0x49 }, 340 { CCI_REG8(0x0210), 0x13 }, 341 { CCI_REG8(0x0218), 0x00 }, 342 { CCI_REG8(0x0241), 0x88 }, 343 { CCI_REG8(0x0e32), 0x00 }, 344 { CCI_REG8(0x0e33), 0x18 }, 345 { CCI_REG8(0x0e42), 0x03 }, 346 { CCI_REG8(0x0e43), 0x80 }, 347 { CCI_REG8(0x0e44), 0x04 }, 348 { CCI_REG8(0x0e45), 0x00 }, 349 { CCI_REG8(0x0e4f), 0x04 }, 350 { CCI_REG8(0x057a), 0x20 }, 351 { CCI_REG8(0x0381), 0x7c }, 352 { CCI_REG8(0x0382), 0x9b }, 353 { CCI_REG8(0x0384), 0xfb }, 354 { CCI_REG8(0x0389), 0x38 }, 355 { CCI_REG8(0x038a), 0x03 }, 356 { CCI_REG8(0x0390), 0x6a }, 357 { CCI_REG8(0x0391), 0x0b }, 358 { CCI_REG8(0x0392), 0x60 }, 359 { CCI_REG8(0x0393), 0xc1 }, 360 { CCI_REG8(0x0396), 0xff }, 361 { CCI_REG8(0x0398), 0x62 }, 362 363 /* cisctl reset */ 364 { CCI_REG8(0x031c), 0x80 }, 365 { CCI_REG8(0x03fe), 0x10 }, 366 { CCI_REG8(0x03fe), 0x00 }, 367 { CCI_REG8(0x031c), 0x9f }, 368 { CCI_REG8(0x03fe), 0x00 }, 369 { CCI_REG8(0x03fe), 0x00 }, 370 { CCI_REG8(0x03fe), 0x00 }, 371 { CCI_REG8(0x03fe), 0x00 }, 372 { CCI_REG8(0x031c), 0x80 }, 373 { CCI_REG8(0x03fe), 0x10 }, 374 { CCI_REG8(0x03fe), 0x00 }, 375 { CCI_REG8(0x031c), 0x9f }, 376 { CCI_REG8(0x0360), 0x01 }, 377 { CCI_REG8(0x0360), 0x00 }, 378 { CCI_REG8(0x0316), 0x09 }, 379 { CCI_REG8(0x0a67), 0x80 }, 380 { CCI_REG8(0x0313), 0x00 }, 381 { CCI_REG8(0x0a53), 0x0e }, 382 { CCI_REG8(0x0a65), 0x17 }, 383 { CCI_REG8(0x0a68), 0xa1 }, 384 { CCI_REG8(0x0a58), 0x00 }, 385 { CCI_REG8(0x0ace), 0x0c }, 386 { CCI_REG8(0x00a4), 0x00 }, 387 { CCI_REG8(0x00a5), 0x01 }, 388 { CCI_REG8(0x00a7), 0x09 }, 389 { CCI_REG8(0x00a8), 0x9c }, 390 { CCI_REG8(0x00a9), 0x0c }, 391 { CCI_REG8(0x00aa), 0xd0 }, 392 { CCI_REG8(0x0a8a), 0x00 }, 393 { CCI_REG8(0x0a8b), 0xe0 }, 394 { CCI_REG8(0x0a8c), 0x13 }, 395 { CCI_REG8(0x0a8d), 0xe8 }, 396 { CCI_REG8(0x0a90), 0x0a }, 397 { CCI_REG8(0x0a91), 0x10 }, 398 { CCI_REG8(0x0a92), 0xf8 }, 399 { CCI_REG8(0x0a71), 0xf2 }, 400 { CCI_REG8(0x0a72), 0x12 }, 401 { CCI_REG8(0x0a73), 0x64 }, 402 { CCI_REG8(0x0a75), 0x41 }, 403 { CCI_REG8(0x0a70), 0x07 }, 404 { CCI_REG8(0x0313), 0x80 }, 405 406 /* ISP */ 407 { CCI_REG8(0x00a0), 0x01 }, 408 { CCI_REG8(0x0080), 0xd2 }, 409 { CCI_REG8(0x0081), 0x3f }, 410 { CCI_REG8(0x0087), 0x51 }, 411 { CCI_REG8(0x0089), 0x03 }, 412 { CCI_REG8(0x009b), 0x40 }, 413 { CCI_REG8(0x05a0), 0x82 }, 414 { CCI_REG8(0x05ac), 0x00 }, 415 { CCI_REG8(0x05ad), 0x01 }, 416 { CCI_REG8(0x05ae), 0x00 }, 417 { CCI_REG8(0x0800), 0x0a }, 418 { CCI_REG8(0x0801), 0x14 }, 419 { CCI_REG8(0x0802), 0x28 }, 420 { CCI_REG8(0x0803), 0x34 }, 421 { CCI_REG8(0x0804), 0x0e }, 422 { CCI_REG8(0x0805), 0x33 }, 423 { CCI_REG8(0x0806), 0x03 }, 424 { CCI_REG8(0x0807), 0x8a }, 425 { CCI_REG8(0x0808), 0x50 }, 426 { CCI_REG8(0x0809), 0x00 }, 427 { CCI_REG8(0x080a), 0x34 }, 428 { CCI_REG8(0x080b), 0x03 }, 429 { CCI_REG8(0x080c), 0x26 }, 430 { CCI_REG8(0x080d), 0x03 }, 431 { CCI_REG8(0x080e), 0x18 }, 432 { CCI_REG8(0x080f), 0x03 }, 433 { CCI_REG8(0x0810), 0x10 }, 434 { CCI_REG8(0x0811), 0x03 }, 435 { CCI_REG8(0x0812), 0x00 }, 436 { CCI_REG8(0x0813), 0x00 }, 437 { CCI_REG8(0x0814), 0x01 }, 438 { CCI_REG8(0x0815), 0x00 }, 439 { CCI_REG8(0x0816), 0x01 }, 440 { CCI_REG8(0x0817), 0x00 }, 441 { CCI_REG8(0x0818), 0x00 }, 442 { CCI_REG8(0x0819), 0x0a }, 443 { CCI_REG8(0x081a), 0x01 }, 444 { CCI_REG8(0x081b), 0x6c }, 445 { CCI_REG8(0x081c), 0x00 }, 446 { CCI_REG8(0x081d), 0x0b }, 447 { CCI_REG8(0x081e), 0x02 }, 448 { CCI_REG8(0x081f), 0x00 }, 449 { CCI_REG8(0x0820), 0x00 }, 450 { CCI_REG8(0x0821), 0x0c }, 451 { CCI_REG8(0x0822), 0x02 }, 452 { CCI_REG8(0x0823), 0xd9 }, 453 { CCI_REG8(0x0824), 0x00 }, 454 { CCI_REG8(0x0825), 0x0d }, 455 { CCI_REG8(0x0826), 0x03 }, 456 { CCI_REG8(0x0827), 0xf0 }, 457 { CCI_REG8(0x0828), 0x00 }, 458 { CCI_REG8(0x0829), 0x0e }, 459 { CCI_REG8(0x082a), 0x05 }, 460 { CCI_REG8(0x082b), 0x94 }, 461 { CCI_REG8(0x082c), 0x09 }, 462 { CCI_REG8(0x082d), 0x6e }, 463 { CCI_REG8(0x082e), 0x07 }, 464 { CCI_REG8(0x082f), 0xe6 }, 465 { CCI_REG8(0x0830), 0x10 }, 466 { CCI_REG8(0x0831), 0x0e }, 467 { CCI_REG8(0x0832), 0x0b }, 468 { CCI_REG8(0x0833), 0x2c }, 469 { CCI_REG8(0x0834), 0x14 }, 470 { CCI_REG8(0x0835), 0xae }, 471 { CCI_REG8(0x0836), 0x0f }, 472 { CCI_REG8(0x0837), 0xc4 }, 473 { CCI_REG8(0x0838), 0x18 }, 474 { CCI_REG8(0x0839), 0x0e }, 475 { CCI_REG8(0x05ac), 0x01 }, 476 { CCI_REG8(0x059a), 0x00 }, 477 { CCI_REG8(0x059b), 0x00 }, 478 { CCI_REG8(0x059c), 0x01 }, 479 { CCI_REG8(0x0598), 0x00 }, 480 { CCI_REG8(0x0597), 0x14 }, 481 { CCI_REG8(0x05ab), 0x09 }, 482 { CCI_REG8(0x05a4), 0x02 }, 483 { CCI_REG8(0x05a3), 0x05 }, 484 { CCI_REG8(0x05a0), 0xc2 }, 485 { CCI_REG8(0x0207), 0xc4 }, 486 487 /* GAIN */ 488 { CCI_REG8(0x0208), 0x01 }, 489 { CCI_REG8(0x0209), 0x72 }, 490 { CCI_REG8(0x0204), 0x04 }, 491 { CCI_REG8(0x0205), 0x00 }, 492 493 { CCI_REG8(0x0040), 0x22 }, 494 { CCI_REG8(0x0041), 0x20 }, 495 { CCI_REG8(0x0043), 0x10 }, 496 { CCI_REG8(0x0044), 0x00 }, 497 { CCI_REG8(0x0046), 0x08 }, 498 { CCI_REG8(0x0047), 0xf0 }, 499 { CCI_REG8(0x0048), 0x0f }, 500 { CCI_REG8(0x004b), 0x0f }, 501 { CCI_REG8(0x004c), 0x00 }, 502 { CCI_REG8(0x0050), 0x5c }, 503 { CCI_REG8(0x0051), 0x44 }, 504 { CCI_REG8(0x005b), 0x03 }, 505 { CCI_REG8(0x00c0), 0x00 }, 506 { CCI_REG8(0x00c1), 0x80 }, 507 { CCI_REG8(0x00c2), 0x31 }, 508 { CCI_REG8(0x00c3), 0x00 }, 509 { CCI_REG8(0x0460), 0x04 }, 510 { CCI_REG8(0x0462), 0x08 }, 511 { CCI_REG8(0x0464), 0x0e }, 512 { CCI_REG8(0x0466), 0x0a }, 513 { CCI_REG8(0x0468), 0x12 }, 514 { CCI_REG8(0x046a), 0x12 }, 515 { CCI_REG8(0x046c), 0x10 }, 516 { CCI_REG8(0x046e), 0x0c }, 517 { CCI_REG8(0x0461), 0x03 }, 518 { CCI_REG8(0x0463), 0x03 }, 519 { CCI_REG8(0x0465), 0x03 }, 520 { CCI_REG8(0x0467), 0x03 }, 521 { CCI_REG8(0x0469), 0x04 }, 522 { CCI_REG8(0x046b), 0x04 }, 523 { CCI_REG8(0x046d), 0x04 }, 524 { CCI_REG8(0x046f), 0x04 }, 525 { CCI_REG8(0x0470), 0x04 }, 526 { CCI_REG8(0x0472), 0x10 }, 527 { CCI_REG8(0x0474), 0x26 }, 528 { CCI_REG8(0x0476), 0x38 }, 529 { CCI_REG8(0x0478), 0x20 }, 530 { CCI_REG8(0x047a), 0x30 }, 531 { CCI_REG8(0x047c), 0x38 }, 532 { CCI_REG8(0x047e), 0x60 }, 533 { CCI_REG8(0x0471), 0x05 }, 534 { CCI_REG8(0x0473), 0x05 }, 535 { CCI_REG8(0x0475), 0x05 }, 536 { CCI_REG8(0x0477), 0x05 }, 537 { CCI_REG8(0x0479), 0x04 }, 538 { CCI_REG8(0x047b), 0x04 }, 539 { CCI_REG8(0x047d), 0x04 }, 540 { CCI_REG8(0x047f), 0x04 }, 541 }; 542 543 struct gc08a3_mode { 544 u32 width; 545 u32 height; 546 const struct gc08a3_reg_list reg_list; 547 548 u32 hts; /* Horizontal timining size */ 549 u32 vts_def; /* Default vertical timining size */ 550 u32 vts_min; /* Min vertical timining size */ 551 }; 552 553 /* Declare modes in order, from biggest to smallest height. */ 554 static const struct gc08a3_mode gc08a3_modes[] = { 555 { 556 /* 3264*2448@30fps */ 557 .width = GC08A3_NATIVE_WIDTH, 558 .height = GC08A3_NATIVE_HEIGHT, 559 .reg_list = { 560 .num_of_regs = ARRAY_SIZE(mode_3264x2448), 561 .regs = mode_3264x2448, 562 }, 563 .hts = 3640, 564 .vts_def = 2548, 565 .vts_min = 2548, 566 }, 567 { 568 /* 1920*1080@60fps */ 569 .width = 1920, 570 .height = 1080, 571 .reg_list = { 572 .num_of_regs = ARRAY_SIZE(mode_1920x1080), 573 .regs = mode_1920x1080, 574 }, 575 .hts = 3640, 576 .vts_def = 1276, 577 .vts_min = 1276, 578 }, 579 }; 580 581 static inline struct gc08a3 *to_gc08a3(struct v4l2_subdev *sd) 582 { 583 return container_of(sd, struct gc08a3, sd); 584 } 585 586 static int gc08a3_power_on(struct device *dev) 587 { 588 struct v4l2_subdev *sd = dev_get_drvdata(dev); 589 struct gc08a3 *gc08a3 = to_gc08a3(sd); 590 int ret; 591 592 ret = regulator_bulk_enable(ARRAY_SIZE(gc08a3_supply_name), 593 gc08a3->supplies); 594 if (ret < 0) { 595 dev_err(gc08a3->dev, "failed to enable regulators: %d\n", ret); 596 return ret; 597 } 598 599 ret = clk_prepare_enable(gc08a3->xclk); 600 if (ret < 0) { 601 regulator_bulk_disable(ARRAY_SIZE(gc08a3_supply_name), 602 gc08a3->supplies); 603 dev_err(gc08a3->dev, "clk prepare enable failed\n"); 604 return ret; 605 } 606 607 fsleep(GC08A3_SLEEP_US); 608 609 gpiod_set_value_cansleep(gc08a3->reset_gpio, 0); 610 fsleep(GC08A3_SLEEP_US); 611 612 return 0; 613 } 614 615 static int gc08a3_power_off(struct device *dev) 616 { 617 struct v4l2_subdev *sd = dev_get_drvdata(dev); 618 struct gc08a3 *gc08a3 = to_gc08a3(sd); 619 620 clk_disable_unprepare(gc08a3->xclk); 621 gpiod_set_value_cansleep(gc08a3->reset_gpio, 1); 622 regulator_bulk_disable(ARRAY_SIZE(gc08a3_supply_name), 623 gc08a3->supplies); 624 625 return 0; 626 } 627 628 static int gc08a3_enum_mbus_code(struct v4l2_subdev *sd, 629 struct v4l2_subdev_state *sd_state, 630 struct v4l2_subdev_mbus_code_enum *code) 631 { 632 if (code->index > 0) 633 return -EINVAL; 634 635 code->code = GC08A3_MBUS_CODE; 636 637 return 0; 638 } 639 640 static int gc08a3_enum_frame_size(struct v4l2_subdev *subdev, 641 struct v4l2_subdev_state *sd_state, 642 struct v4l2_subdev_frame_size_enum *fse) 643 { 644 if (fse->code != GC08A3_MBUS_CODE) 645 return -EINVAL; 646 647 if (fse->index >= ARRAY_SIZE(gc08a3_modes)) 648 return -EINVAL; 649 650 fse->min_width = gc08a3_modes[fse->index].width; 651 fse->max_width = gc08a3_modes[fse->index].width; 652 fse->min_height = gc08a3_modes[fse->index].height; 653 fse->max_height = gc08a3_modes[fse->index].height; 654 655 return 0; 656 } 657 658 static int gc08a3_update_cur_mode_controls(struct gc08a3 *gc08a3, 659 const struct gc08a3_mode *mode) 660 { 661 s64 exposure_max, h_blank; 662 int ret; 663 664 ret = __v4l2_ctrl_modify_range(gc08a3->vblank, 665 mode->vts_min - mode->height, 666 GC08A3_VTS_MAX - mode->height, 1, 667 mode->vts_def - mode->height); 668 if (ret) { 669 dev_err(gc08a3->dev, "VB ctrl range update failed\n"); 670 return ret; 671 } 672 673 h_blank = mode->hts - mode->width; 674 ret = __v4l2_ctrl_modify_range(gc08a3->hblank, h_blank, h_blank, 1, 675 h_blank); 676 if (ret) { 677 dev_err(gc08a3->dev, "HB ctrl range update failed\n"); 678 return ret; 679 } 680 681 exposure_max = mode->vts_def - GC08A3_EXP_MARGIN; 682 ret = __v4l2_ctrl_modify_range(gc08a3->exposure, GC08A3_EXP_MIN, 683 exposure_max, GC08A3_EXP_STEP, 684 exposure_max); 685 if (ret) { 686 dev_err(gc08a3->dev, "exposure ctrl range update failed\n"); 687 return ret; 688 } 689 690 return 0; 691 } 692 693 static void gc08a3_update_pad_format(struct gc08a3 *gc08a3, 694 const struct gc08a3_mode *mode, 695 struct v4l2_mbus_framefmt *fmt) 696 { 697 fmt->width = mode->width; 698 fmt->height = mode->height; 699 fmt->code = GC08A3_MBUS_CODE; 700 fmt->field = V4L2_FIELD_NONE; 701 fmt->colorspace = V4L2_COLORSPACE_RAW; 702 fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace); 703 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 704 fmt->xfer_func = V4L2_XFER_FUNC_NONE; 705 } 706 707 static int gc08a3_set_format(struct v4l2_subdev *sd, 708 const struct v4l2_subdev_client_info *ci, 709 struct v4l2_subdev_state *state, 710 struct v4l2_subdev_format *fmt) 711 { 712 struct gc08a3 *gc08a3 = to_gc08a3(sd); 713 struct v4l2_mbus_framefmt *mbus_fmt; 714 struct v4l2_rect *crop; 715 const struct gc08a3_mode *mode; 716 717 mode = v4l2_find_nearest_size(gc08a3_modes, ARRAY_SIZE(gc08a3_modes), 718 width, height, fmt->format.width, 719 fmt->format.height); 720 721 /* update crop info to subdev state */ 722 crop = v4l2_subdev_state_get_crop(state, 0); 723 crop->width = mode->width; 724 crop->height = mode->height; 725 726 /* update fmt info to subdev state */ 727 gc08a3_update_pad_format(gc08a3, mode, &fmt->format); 728 mbus_fmt = v4l2_subdev_state_get_format(state, 0); 729 *mbus_fmt = fmt->format; 730 731 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 732 return 0; 733 734 gc08a3->cur_mode = mode; 735 gc08a3_update_cur_mode_controls(gc08a3, mode); 736 737 return 0; 738 } 739 740 static int gc08a3_get_selection(struct v4l2_subdev *sd, 741 const struct v4l2_subdev_client_info *ci, 742 struct v4l2_subdev_state *state, 743 struct v4l2_subdev_selection *sel) 744 { 745 switch (sel->target) { 746 case V4L2_SEL_TGT_CROP_DEFAULT: 747 case V4L2_SEL_TGT_CROP: 748 sel->r = *v4l2_subdev_state_get_crop(state, 0); 749 break; 750 case V4L2_SEL_TGT_CROP_BOUNDS: 751 sel->r.top = 0; 752 sel->r.left = 0; 753 sel->r.width = GC08A3_NATIVE_WIDTH; 754 sel->r.height = GC08A3_NATIVE_HEIGHT; 755 break; 756 default: 757 return -EINVAL; 758 } 759 760 return 0; 761 } 762 763 static int gc08a3_init_state(struct v4l2_subdev *sd, 764 struct v4l2_subdev_state *state) 765 { 766 struct v4l2_subdev_format fmt = { 767 .which = V4L2_SUBDEV_FORMAT_TRY, 768 .pad = 0, 769 .format = { 770 .code = GC08A3_MBUS_CODE, 771 .width = gc08a3_modes[0].width, 772 .height = gc08a3_modes[0].height, 773 }, 774 }; 775 776 gc08a3_set_format(sd, NULL, state, &fmt); 777 778 return 0; 779 } 780 781 static int gc08a3_set_ctrl_hflip(struct gc08a3 *gc08a3, u32 ctrl_val) 782 { 783 int ret; 784 u64 val; 785 786 ret = cci_read(gc08a3->regmap, GC08A3_FLIP_REG, &val, NULL); 787 if (ret) { 788 dev_err(gc08a3->dev, "read hflip register failed: %d\n", ret); 789 return ret; 790 } 791 792 return cci_update_bits(gc08a3->regmap, GC08A3_FLIP_REG, 793 GC08A3_FLIP_H_MASK, 794 ctrl_val ? GC08A3_FLIP_H_MASK : 0, NULL); 795 } 796 797 static int gc08a3_set_ctrl_vflip(struct gc08a3 *gc08a3, u32 ctrl_val) 798 { 799 int ret; 800 u64 val; 801 802 ret = cci_read(gc08a3->regmap, GC08A3_FLIP_REG, &val, NULL); 803 if (ret) { 804 dev_err(gc08a3->dev, "read vflip register failed: %d\n", ret); 805 return ret; 806 } 807 808 return cci_update_bits(gc08a3->regmap, GC08A3_FLIP_REG, 809 GC08A3_FLIP_V_MASK, 810 ctrl_val ? GC08A3_FLIP_V_MASK : 0, NULL); 811 } 812 813 static int gc08a3_test_pattern(struct gc08a3 *gc08a3, u32 pattern_menu) 814 { 815 u32 pattern; 816 int ret; 817 818 if (pattern_menu) { 819 switch (pattern_menu) { 820 case 1: 821 pattern = 0x00; 822 break; 823 case 2: 824 pattern = 0x10; 825 break; 826 case 3: 827 case 4: 828 case 5: 829 case 6: 830 case 7: 831 pattern = pattern_menu + 1; 832 break; 833 default: 834 pattern = 0x00; 835 break; 836 } 837 838 ret = cci_write(gc08a3->regmap, GC08A3_REG_TEST_PATTERN_IDX, 839 pattern, NULL); 840 if (ret) 841 return ret; 842 843 return cci_write(gc08a3->regmap, GC08A3_REG_TEST_PATTERN_EN, 844 GC08A3_TEST_PATTERN_EN, NULL); 845 } else { 846 return cci_write(gc08a3->regmap, GC08A3_REG_TEST_PATTERN_EN, 847 0x00, NULL); 848 } 849 } 850 851 static int gc08a3_set_ctrl(struct v4l2_ctrl *ctrl) 852 { 853 struct gc08a3 *gc08a3 = 854 container_of(ctrl->handler, struct gc08a3, ctrls); 855 int ret = 0; 856 s64 exposure_max; 857 struct v4l2_subdev_state *state; 858 const struct v4l2_mbus_framefmt *format; 859 860 state = v4l2_subdev_get_locked_active_state(&gc08a3->sd); 861 format = v4l2_subdev_state_get_format(state, 0); 862 863 if (ctrl->id == V4L2_CID_VBLANK) { 864 /* Update max exposure while meeting expected vblanking */ 865 exposure_max = format->height + ctrl->val - GC08A3_EXP_MARGIN; 866 __v4l2_ctrl_modify_range(gc08a3->exposure, 867 gc08a3->exposure->minimum, 868 exposure_max, gc08a3->exposure->step, 869 exposure_max); 870 } 871 872 /* 873 * Applying V4L2 control value only happens 874 * when power is on for streaming. 875 */ 876 if (!pm_runtime_get_if_active(gc08a3->dev)) 877 return 0; 878 879 switch (ctrl->id) { 880 case V4L2_CID_EXPOSURE: 881 ret = cci_write(gc08a3->regmap, GC08A3_EXP_REG, 882 ctrl->val, NULL); 883 break; 884 885 case V4L2_CID_ANALOGUE_GAIN: 886 ret = cci_write(gc08a3->regmap, GC08A3_AGAIN_REG, 887 ctrl->val, NULL); 888 break; 889 890 case V4L2_CID_VBLANK: 891 ret = cci_write(gc08a3->regmap, GC08A3_FRAME_LENGTH_REG, 892 gc08a3->cur_mode->height + ctrl->val, NULL); 893 break; 894 895 case V4L2_CID_HFLIP: 896 ret = gc08a3_set_ctrl_hflip(gc08a3, ctrl->val); 897 break; 898 899 case V4L2_CID_VFLIP: 900 ret = gc08a3_set_ctrl_vflip(gc08a3, ctrl->val); 901 break; 902 903 case V4L2_CID_TEST_PATTERN: 904 ret = gc08a3_test_pattern(gc08a3, ctrl->val); 905 break; 906 907 default: 908 break; 909 } 910 911 pm_runtime_put(gc08a3->dev); 912 913 return ret; 914 } 915 916 static const struct v4l2_ctrl_ops gc08a3_ctrl_ops = { 917 .s_ctrl = gc08a3_set_ctrl, 918 }; 919 920 static int gc08a3_start_streaming(struct gc08a3 *gc08a3) 921 { 922 const struct gc08a3_mode *mode; 923 const struct gc08a3_reg_list *reg_list; 924 int ret; 925 926 ret = pm_runtime_resume_and_get(gc08a3->dev); 927 if (ret < 0) 928 return ret; 929 930 ret = cci_multi_reg_write(gc08a3->regmap, 931 mode_table_common, 932 ARRAY_SIZE(mode_table_common), NULL); 933 if (ret) 934 goto err_rpm_put; 935 936 mode = gc08a3->cur_mode; 937 reg_list = &mode->reg_list; 938 ret = cci_multi_reg_write(gc08a3->regmap, 939 reg_list->regs, reg_list->num_of_regs, NULL); 940 if (ret < 0) 941 goto err_rpm_put; 942 943 ret = __v4l2_ctrl_handler_setup(&gc08a3->ctrls); 944 if (ret < 0) { 945 dev_err(gc08a3->dev, "could not sync v4l2 controls\n"); 946 goto err_rpm_put; 947 } 948 949 ret = cci_write(gc08a3->regmap, GC08A3_STREAMING_REG, 1, NULL); 950 if (ret < 0) { 951 dev_err(gc08a3->dev, "write STREAMING_REG failed: %d\n", ret); 952 goto err_rpm_put; 953 } 954 955 return 0; 956 957 err_rpm_put: 958 pm_runtime_put(gc08a3->dev); 959 return ret; 960 } 961 962 static int gc08a3_stop_streaming(struct gc08a3 *gc08a3) 963 { 964 int ret; 965 966 ret = cci_write(gc08a3->regmap, GC08A3_STREAMING_REG, 0, NULL); 967 if (ret < 0) 968 dev_err(gc08a3->dev, "could not sent stop streaming %d\n", ret); 969 970 pm_runtime_put(gc08a3->dev); 971 return ret; 972 } 973 974 static int gc08a3_s_stream(struct v4l2_subdev *subdev, int enable) 975 { 976 struct gc08a3 *gc08a3 = to_gc08a3(subdev); 977 struct v4l2_subdev_state *state; 978 int ret; 979 980 state = v4l2_subdev_lock_and_get_active_state(subdev); 981 982 if (enable) 983 ret = gc08a3_start_streaming(gc08a3); 984 else 985 ret = gc08a3_stop_streaming(gc08a3); 986 987 v4l2_subdev_unlock_state(state); 988 989 return ret; 990 } 991 992 static const struct v4l2_subdev_video_ops gc08a3_video_ops = { 993 .s_stream = gc08a3_s_stream, 994 }; 995 996 static const struct v4l2_subdev_pad_ops gc08a3_subdev_pad_ops = { 997 .enum_mbus_code = gc08a3_enum_mbus_code, 998 .enum_frame_size = gc08a3_enum_frame_size, 999 .get_fmt = v4l2_subdev_get_fmt, 1000 .set_fmt = gc08a3_set_format, 1001 .get_selection = gc08a3_get_selection, 1002 }; 1003 1004 static const struct v4l2_subdev_ops gc08a3_subdev_ops = { 1005 .video = &gc08a3_video_ops, 1006 .pad = &gc08a3_subdev_pad_ops, 1007 }; 1008 1009 static const struct v4l2_subdev_internal_ops gc08a3_internal_ops = { 1010 .init_state = gc08a3_init_state, 1011 }; 1012 1013 static int gc08a3_get_regulators(struct device *dev, struct gc08a3 *gc08a3) 1014 { 1015 unsigned int i; 1016 1017 for (i = 0; i < ARRAY_SIZE(gc08a3_supply_name); i++) 1018 gc08a3->supplies[i].supply = gc08a3_supply_name[i]; 1019 1020 return devm_regulator_bulk_get(dev, ARRAY_SIZE(gc08a3_supply_name), 1021 gc08a3->supplies); 1022 } 1023 1024 static int gc08a3_parse_fwnode(struct gc08a3 *gc08a3) 1025 { 1026 struct fwnode_handle *endpoint; 1027 struct v4l2_fwnode_endpoint bus_cfg = { 1028 .bus_type = V4L2_MBUS_CSI2_DPHY, 1029 }; 1030 int ret; 1031 struct device *dev = gc08a3->dev; 1032 1033 endpoint = 1034 fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 1035 FWNODE_GRAPH_ENDPOINT_NEXT); 1036 if (!endpoint) { 1037 dev_err(dev, "endpoint node not found\n"); 1038 return -EINVAL; 1039 } 1040 1041 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg); 1042 if (ret) { 1043 dev_err(dev, "parsing endpoint node failed\n"); 1044 goto done; 1045 } 1046 1047 ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies, 1048 bus_cfg.nr_of_link_frequencies, 1049 gc08a3_link_freq_menu_items, 1050 ARRAY_SIZE(gc08a3_link_freq_menu_items), 1051 &gc08a3->link_freq_bitmap); 1052 if (ret) 1053 goto done; 1054 1055 done: 1056 v4l2_fwnode_endpoint_free(&bus_cfg); 1057 fwnode_handle_put(endpoint); 1058 return ret; 1059 } 1060 1061 static u64 gc08a3_to_pixel_rate(u32 f_index) 1062 { 1063 u64 pixel_rate = 1064 gc08a3_link_freq_menu_items[f_index] * 2 * GC08A3_DATA_LANES; 1065 1066 return div_u64(pixel_rate, GC08A3_RGB_DEPTH); 1067 } 1068 1069 static int gc08a3_init_controls(struct gc08a3 *gc08a3) 1070 { 1071 struct i2c_client *client = v4l2_get_subdevdata(&gc08a3->sd); 1072 const struct gc08a3_mode *mode = &gc08a3_modes[0]; 1073 const struct v4l2_ctrl_ops *ops = &gc08a3_ctrl_ops; 1074 struct v4l2_fwnode_device_properties props; 1075 struct v4l2_ctrl_handler *ctrl_hdlr; 1076 s64 exposure_max, h_blank; 1077 int ret; 1078 1079 ctrl_hdlr = &gc08a3->ctrls; 1080 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 9); 1081 if (ret) 1082 return ret; 1083 1084 gc08a3->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &gc08a3_ctrl_ops, 1085 V4L2_CID_HFLIP, 0, 1, 1, 0); 1086 gc08a3->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &gc08a3_ctrl_ops, 1087 V4L2_CID_VFLIP, 0, 1, 1, 0); 1088 v4l2_ctrl_cluster(2, &gc08a3->hflip); 1089 1090 gc08a3->link_freq = 1091 v4l2_ctrl_new_int_menu(ctrl_hdlr, 1092 &gc08a3_ctrl_ops, 1093 V4L2_CID_LINK_FREQ, 1094 ARRAY_SIZE(gc08a3_link_freq_menu_items) - 1, 1095 0, 1096 gc08a3_link_freq_menu_items); 1097 if (gc08a3->link_freq) 1098 gc08a3->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1099 1100 gc08a3->pixel_rate = 1101 v4l2_ctrl_new_std(ctrl_hdlr, 1102 &gc08a3_ctrl_ops, 1103 V4L2_CID_PIXEL_RATE, 0, 1104 gc08a3_to_pixel_rate(0), 1105 1, 1106 gc08a3_to_pixel_rate(0)); 1107 1108 gc08a3->vblank = 1109 v4l2_ctrl_new_std(ctrl_hdlr, 1110 &gc08a3_ctrl_ops, V4L2_CID_VBLANK, 1111 mode->vts_min - mode->height, 1112 GC08A3_VTS_MAX - mode->height, 1, 1113 mode->vts_def - mode->height); 1114 1115 h_blank = mode->hts - mode->width; 1116 gc08a3->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &gc08a3_ctrl_ops, 1117 V4L2_CID_HBLANK, h_blank, h_blank, 1, 1118 h_blank); 1119 if (gc08a3->hblank) 1120 gc08a3->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1121 1122 v4l2_ctrl_new_std(ctrl_hdlr, &gc08a3_ctrl_ops, 1123 V4L2_CID_ANALOGUE_GAIN, GC08A3_AGAIN_MIN, 1124 GC08A3_AGAIN_MAX, GC08A3_AGAIN_STEP, 1125 GC08A3_AGAIN_MIN); 1126 1127 exposure_max = mode->vts_def - GC08A3_EXP_MARGIN; 1128 gc08a3->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &gc08a3_ctrl_ops, 1129 V4L2_CID_EXPOSURE, GC08A3_EXP_MIN, 1130 exposure_max, GC08A3_EXP_STEP, 1131 exposure_max); 1132 1133 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &gc08a3_ctrl_ops, 1134 V4L2_CID_TEST_PATTERN, 1135 ARRAY_SIZE(gc08a3_test_pattern_menu) - 1, 1136 0, 0, gc08a3_test_pattern_menu); 1137 1138 /* register properties to fwnode (e.g. rotation, orientation) */ 1139 ret = v4l2_fwnode_device_parse(&client->dev, &props); 1140 if (ret) 1141 goto error_ctrls; 1142 1143 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, ops, &props); 1144 if (ret) 1145 goto error_ctrls; 1146 1147 if (ctrl_hdlr->error) { 1148 ret = ctrl_hdlr->error; 1149 goto error_ctrls; 1150 } 1151 1152 gc08a3->sd.ctrl_handler = ctrl_hdlr; 1153 1154 return 0; 1155 1156 error_ctrls: 1157 v4l2_ctrl_handler_free(ctrl_hdlr); 1158 1159 return ret; 1160 } 1161 1162 static int gc08a3_identify_module(struct gc08a3 *gc08a3) 1163 { 1164 u64 val; 1165 int ret; 1166 1167 ret = cci_read(gc08a3->regmap, GC08A3_REG_CHIP_ID, &val, NULL); 1168 if (ret) { 1169 dev_err(gc08a3->dev, "failed to read chip id"); 1170 return ret; 1171 } 1172 1173 if (val != GC08A3_CHIP_ID) { 1174 dev_err(gc08a3->dev, "chip id mismatch: 0x%x!=0x%llx", 1175 GC08A3_CHIP_ID, val); 1176 return -ENXIO; 1177 } 1178 1179 return 0; 1180 } 1181 1182 static int gc08a3_probe(struct i2c_client *client) 1183 { 1184 struct device *dev = &client->dev; 1185 struct gc08a3 *gc08a3; 1186 int ret; 1187 1188 gc08a3 = devm_kzalloc(dev, sizeof(*gc08a3), GFP_KERNEL); 1189 if (!gc08a3) 1190 return -ENOMEM; 1191 1192 gc08a3->dev = dev; 1193 1194 ret = gc08a3_parse_fwnode(gc08a3); 1195 if (ret) 1196 return ret; 1197 1198 gc08a3->regmap = devm_cci_regmap_init_i2c(client, 16); 1199 if (IS_ERR(gc08a3->regmap)) 1200 return dev_err_probe(dev, PTR_ERR(gc08a3->regmap), 1201 "failed to init CCI\n"); 1202 1203 gc08a3->xclk = devm_v4l2_sensor_clk_get_legacy(dev, NULL, true, 1204 GC08A3_DEFAULT_CLK_FREQ); 1205 if (IS_ERR(gc08a3->xclk)) 1206 return dev_err_probe(dev, PTR_ERR(gc08a3->xclk), 1207 "failed to get xclk\n"); 1208 1209 ret = gc08a3_get_regulators(dev, gc08a3); 1210 if (ret < 0) 1211 return dev_err_probe(dev, ret, 1212 "failed to get regulators\n"); 1213 1214 gc08a3->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 1215 if (IS_ERR(gc08a3->reset_gpio)) 1216 return dev_err_probe(dev, PTR_ERR(gc08a3->reset_gpio), 1217 "failed to get gpio\n"); 1218 1219 v4l2_i2c_subdev_init(&gc08a3->sd, client, &gc08a3_subdev_ops); 1220 gc08a3->sd.internal_ops = &gc08a3_internal_ops; 1221 gc08a3->cur_mode = &gc08a3_modes[0]; 1222 1223 ret = gc08a3_power_on(gc08a3->dev); 1224 if (ret) 1225 return dev_err_probe(dev, ret, 1226 "failed to sensor power on\n"); 1227 1228 ret = gc08a3_identify_module(gc08a3); 1229 if (ret) { 1230 dev_err(&client->dev, "failed to find sensor: %d\n", ret); 1231 goto err_power_off; 1232 } 1233 1234 ret = gc08a3_init_controls(gc08a3); 1235 if (ret) { 1236 dev_err(&client->dev, "failed to init controls: %d", ret); 1237 goto err_power_off; 1238 } 1239 1240 gc08a3->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1241 gc08a3->pad.flags = MEDIA_PAD_FL_SOURCE; 1242 gc08a3->sd.dev = &client->dev; 1243 gc08a3->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1244 1245 ret = media_entity_pads_init(&gc08a3->sd.entity, 1, &gc08a3->pad); 1246 if (ret < 0) { 1247 dev_err(dev, "could not register media entity\n"); 1248 goto err_v4l2_ctrl_handler_free; 1249 } 1250 1251 gc08a3->sd.state_lock = gc08a3->ctrls.lock; 1252 ret = v4l2_subdev_init_finalize(&gc08a3->sd); 1253 if (ret < 0) { 1254 dev_err(dev, "v4l2 subdev init error: %d\n", ret); 1255 goto err_media_entity_cleanup; 1256 } 1257 1258 pm_runtime_set_active(gc08a3->dev); 1259 pm_runtime_enable(gc08a3->dev); 1260 pm_runtime_set_autosuspend_delay(gc08a3->dev, 1000); 1261 pm_runtime_use_autosuspend(gc08a3->dev); 1262 pm_runtime_idle(gc08a3->dev); 1263 1264 ret = v4l2_async_register_subdev_sensor(&gc08a3->sd); 1265 if (ret < 0) { 1266 dev_err(dev, "could not register v4l2 device\n"); 1267 goto err_rpm; 1268 } 1269 1270 return 0; 1271 1272 err_rpm: 1273 pm_runtime_disable(gc08a3->dev); 1274 v4l2_subdev_cleanup(&gc08a3->sd); 1275 1276 err_media_entity_cleanup: 1277 media_entity_cleanup(&gc08a3->sd.entity); 1278 1279 err_v4l2_ctrl_handler_free: 1280 v4l2_ctrl_handler_free(gc08a3->sd.ctrl_handler); 1281 1282 err_power_off: 1283 gc08a3_power_off(gc08a3->dev); 1284 1285 return ret; 1286 } 1287 1288 static void gc08a3_remove(struct i2c_client *client) 1289 { 1290 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1291 struct gc08a3 *gc08a3 = to_gc08a3(sd); 1292 1293 v4l2_async_unregister_subdev(&gc08a3->sd); 1294 v4l2_subdev_cleanup(sd); 1295 media_entity_cleanup(&gc08a3->sd.entity); 1296 v4l2_ctrl_handler_free(&gc08a3->ctrls); 1297 1298 pm_runtime_disable(&client->dev); 1299 if (!pm_runtime_status_suspended(&client->dev)) 1300 gc08a3_power_off(gc08a3->dev); 1301 pm_runtime_set_suspended(&client->dev); 1302 } 1303 1304 static const struct of_device_id gc08a3_of_match[] = { 1305 { .compatible = "galaxycore,gc08a3" }, 1306 {} 1307 }; 1308 MODULE_DEVICE_TABLE(of, gc08a3_of_match); 1309 1310 static DEFINE_RUNTIME_DEV_PM_OPS(gc08a3_pm_ops, 1311 gc08a3_power_off, 1312 gc08a3_power_on, 1313 NULL); 1314 1315 static struct i2c_driver gc08a3_i2c_driver = { 1316 .driver = { 1317 .of_match_table = gc08a3_of_match, 1318 .pm = pm_ptr(&gc08a3_pm_ops), 1319 .name = "gc08a3", 1320 }, 1321 .probe = gc08a3_probe, 1322 .remove = gc08a3_remove, 1323 }; 1324 module_i2c_driver(gc08a3_i2c_driver); 1325 1326 MODULE_DESCRIPTION("GalaxyCore gc08a3 Camera driver"); 1327 MODULE_AUTHOR("Zhi Mao <zhi.mao@mediatek.com>"); 1328 MODULE_LICENSE("GPL"); 1329