xref: /linux/drivers/net/wireless/realtek/rtw89/ser.c (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #include <linux/devcoredump.h>
6 
7 #include "cam.h"
8 #include "chan.h"
9 #include "debug.h"
10 #include "fw.h"
11 #include "mac.h"
12 #include "ps.h"
13 #include "reg.h"
14 #include "ser.h"
15 #include "util.h"
16 
17 #define SER_RECFG_TIMEOUT 1000
18 
19 enum ser_evt {
20 	SER_EV_NONE,
21 	SER_EV_STATE_IN,
22 	SER_EV_STATE_OUT,
23 	SER_EV_L1_RESET_PREPARE, /* pre-M0 */
24 	SER_EV_L1_RESET, /* M1 */
25 	SER_EV_DO_RECOVERY, /* M3 */
26 	SER_EV_MAC_RESET_DONE, /* M5 */
27 	SER_EV_L2_RESET,
28 	SER_EV_L2_RECFG_DONE,
29 	SER_EV_L2_RECFG_TIMEOUT,
30 	SER_EV_M1_TIMEOUT,
31 	SER_EV_M3_TIMEOUT,
32 	SER_EV_FW_M5_TIMEOUT,
33 	SER_EV_L0_RESET,
34 	SER_EV_MAXX
35 };
36 
37 enum ser_state {
38 	SER_IDLE_ST,
39 	SER_L1_RESET_PRE_ST,
40 	SER_RESET_TRX_ST,
41 	SER_DO_HCI_ST,
42 	SER_L2_RESET_ST,
43 	SER_ST_MAX_ST
44 };
45 
46 struct ser_msg {
47 	struct list_head list;
48 	u8 event;
49 };
50 
51 struct state_ent {
52 	u8 state;
53 	char *name;
54 	void (*st_func)(struct rtw89_ser *ser, u8 event);
55 };
56 
57 struct event_ent {
58 	u8 event;
59 	char *name;
60 };
61 
ser_ev_name(struct rtw89_ser * ser,u8 event)62 static char *ser_ev_name(struct rtw89_ser *ser, u8 event)
63 {
64 	if (event < SER_EV_MAXX)
65 		return ser->ev_tbl[event].name;
66 
67 	return "err_ev_name";
68 }
69 
ser_st_name(struct rtw89_ser * ser)70 static char *ser_st_name(struct rtw89_ser *ser)
71 {
72 	if (ser->state < SER_ST_MAX_ST)
73 		return ser->st_tbl[ser->state].name;
74 
75 	return "err_st_name";
76 }
77 
78 #define RTW89_DEF_SER_CD_TYPE(_name, _type, _size) \
79 struct ser_cd_ ## _name { \
80 	u32 type; \
81 	u32 type_size; \
82 	u64 padding; \
83 	u8 data[_size]; \
84 } __packed; \
85 static void ser_cd_ ## _name ## _init(struct ser_cd_ ## _name *p) \
86 { \
87 	p->type = _type; \
88 	p->type_size = sizeof(p->data); \
89 	p->padding = 0x0123456789abcdef; \
90 }
91 
92 enum rtw89_ser_cd_type {
93 	RTW89_SER_CD_FW_RSVD_PLE	= 0,
94 	RTW89_SER_CD_FW_BACKTRACE	= 1,
95 };
96 
97 RTW89_DEF_SER_CD_TYPE(fw_rsvd_ple,
98 		      RTW89_SER_CD_FW_RSVD_PLE,
99 		      RTW89_FW_RSVD_PLE_SIZE);
100 
101 RTW89_DEF_SER_CD_TYPE(fw_backtrace,
102 		      RTW89_SER_CD_FW_BACKTRACE,
103 		      RTW89_FW_BACKTRACE_MAX_SIZE);
104 
105 struct rtw89_ser_cd_buffer {
106 	struct ser_cd_fw_rsvd_ple fwple;
107 	struct ser_cd_fw_backtrace fwbt;
108 } __packed;
109 
rtw89_ser_cd_prep(struct rtw89_dev * rtwdev)110 static struct rtw89_ser_cd_buffer *rtw89_ser_cd_prep(struct rtw89_dev *rtwdev)
111 {
112 	struct rtw89_ser_cd_buffer *buf;
113 
114 	buf = vzalloc(sizeof(*buf));
115 	if (!buf)
116 		return NULL;
117 
118 	ser_cd_fw_rsvd_ple_init(&buf->fwple);
119 	ser_cd_fw_backtrace_init(&buf->fwbt);
120 
121 	return buf;
122 }
123 
rtw89_ser_cd_send(struct rtw89_dev * rtwdev,struct rtw89_ser_cd_buffer * buf)124 static void rtw89_ser_cd_send(struct rtw89_dev *rtwdev,
125 			      struct rtw89_ser_cd_buffer *buf)
126 {
127 	rtw89_debug(rtwdev, RTW89_DBG_SER, "SER sends core dump\n");
128 
129 	/* After calling dev_coredump, buf's lifetime is supposed to be
130 	 * handled by the device coredump framework. Note that a new dump
131 	 * will be discarded if a previous one hasn't been released by
132 	 * framework yet.
133 	 */
134 	dev_coredumpv(rtwdev->dev, buf, sizeof(*buf), GFP_KERNEL);
135 }
136 
rtw89_ser_cd_free(struct rtw89_dev * rtwdev,struct rtw89_ser_cd_buffer * buf,bool free_self)137 static void rtw89_ser_cd_free(struct rtw89_dev *rtwdev,
138 			      struct rtw89_ser_cd_buffer *buf, bool free_self)
139 {
140 	if (!free_self)
141 		return;
142 
143 	rtw89_debug(rtwdev, RTW89_DBG_SER, "SER frees core dump by self\n");
144 
145 	/* When some problems happen during filling data of core dump,
146 	 * we won't send it to device coredump framework. Instead, we
147 	 * free buf by ourselves.
148 	 */
149 	vfree(buf);
150 }
151 
ser_state_run(struct rtw89_ser * ser,u8 evt)152 static void ser_state_run(struct rtw89_ser *ser, u8 evt)
153 {
154 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
155 
156 	rtw89_debug(rtwdev, RTW89_DBG_SER, "ser: %s receive %s\n",
157 		    ser_st_name(ser), ser_ev_name(ser, evt));
158 
159 	mutex_lock(&rtwdev->mutex);
160 	rtw89_leave_lps(rtwdev);
161 	mutex_unlock(&rtwdev->mutex);
162 
163 	ser->st_tbl[ser->state].st_func(ser, evt);
164 }
165 
ser_state_goto(struct rtw89_ser * ser,u8 new_state)166 static void ser_state_goto(struct rtw89_ser *ser, u8 new_state)
167 {
168 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
169 
170 	if (ser->state == new_state || new_state >= SER_ST_MAX_ST)
171 		return;
172 	ser_state_run(ser, SER_EV_STATE_OUT);
173 
174 	rtw89_debug(rtwdev, RTW89_DBG_SER, "ser: %s goto -> %s\n",
175 		    ser_st_name(ser), ser->st_tbl[new_state].name);
176 
177 	ser->state = new_state;
178 	ser_state_run(ser, SER_EV_STATE_IN);
179 }
180 
__rtw89_ser_dequeue_msg(struct rtw89_ser * ser)181 static struct ser_msg *__rtw89_ser_dequeue_msg(struct rtw89_ser *ser)
182 {
183 	struct ser_msg *msg;
184 
185 	spin_lock_irq(&ser->msg_q_lock);
186 	msg = list_first_entry_or_null(&ser->msg_q, struct ser_msg, list);
187 	if (msg)
188 		list_del(&msg->list);
189 	spin_unlock_irq(&ser->msg_q_lock);
190 
191 	return msg;
192 }
193 
rtw89_ser_hdl_work(struct work_struct * work)194 static void rtw89_ser_hdl_work(struct work_struct *work)
195 {
196 	struct ser_msg *msg;
197 	struct rtw89_ser *ser = container_of(work, struct rtw89_ser,
198 					     ser_hdl_work);
199 
200 	while ((msg = __rtw89_ser_dequeue_msg(ser))) {
201 		ser_state_run(ser, msg->event);
202 		kfree(msg);
203 	}
204 }
205 
ser_send_msg(struct rtw89_ser * ser,u8 event)206 static int ser_send_msg(struct rtw89_ser *ser, u8 event)
207 {
208 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
209 	struct ser_msg *msg = NULL;
210 
211 	if (test_bit(RTW89_SER_DRV_STOP_RUN, ser->flags))
212 		return -EIO;
213 
214 	msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
215 	if (!msg)
216 		return -ENOMEM;
217 
218 	msg->event = event;
219 
220 	spin_lock_irq(&ser->msg_q_lock);
221 	list_add(&msg->list, &ser->msg_q);
222 	spin_unlock_irq(&ser->msg_q_lock);
223 
224 	ieee80211_queue_work(rtwdev->hw, &ser->ser_hdl_work);
225 	return 0;
226 }
227 
rtw89_ser_alarm_work(struct work_struct * work)228 static void rtw89_ser_alarm_work(struct work_struct *work)
229 {
230 	struct rtw89_ser *ser = container_of(work, struct rtw89_ser,
231 					     ser_alarm_work.work);
232 
233 	ser_send_msg(ser, ser->alarm_event);
234 	ser->alarm_event = SER_EV_NONE;
235 }
236 
ser_set_alarm(struct rtw89_ser * ser,u32 ms,u8 event)237 static void ser_set_alarm(struct rtw89_ser *ser, u32 ms, u8 event)
238 {
239 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
240 
241 	if (test_bit(RTW89_SER_DRV_STOP_RUN, ser->flags))
242 		return;
243 
244 	ser->alarm_event = event;
245 	ieee80211_queue_delayed_work(rtwdev->hw, &ser->ser_alarm_work,
246 				     msecs_to_jiffies(ms));
247 }
248 
ser_del_alarm(struct rtw89_ser * ser)249 static void ser_del_alarm(struct rtw89_ser *ser)
250 {
251 	cancel_delayed_work(&ser->ser_alarm_work);
252 	ser->alarm_event = SER_EV_NONE;
253 }
254 
255 /* driver function */
drv_stop_tx(struct rtw89_ser * ser)256 static void drv_stop_tx(struct rtw89_ser *ser)
257 {
258 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
259 
260 	ieee80211_stop_queues(rtwdev->hw);
261 	set_bit(RTW89_SER_DRV_STOP_TX, ser->flags);
262 }
263 
drv_stop_rx(struct rtw89_ser * ser)264 static void drv_stop_rx(struct rtw89_ser *ser)
265 {
266 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
267 
268 	clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
269 	set_bit(RTW89_SER_DRV_STOP_RX, ser->flags);
270 }
271 
drv_trx_reset(struct rtw89_ser * ser)272 static void drv_trx_reset(struct rtw89_ser *ser)
273 {
274 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
275 
276 	rtw89_hci_reset(rtwdev);
277 }
278 
drv_resume_tx(struct rtw89_ser * ser)279 static void drv_resume_tx(struct rtw89_ser *ser)
280 {
281 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
282 
283 	if (!test_bit(RTW89_SER_DRV_STOP_TX, ser->flags))
284 		return;
285 
286 	ieee80211_wake_queues(rtwdev->hw);
287 	clear_bit(RTW89_SER_DRV_STOP_TX, ser->flags);
288 }
289 
drv_resume_rx(struct rtw89_ser * ser)290 static void drv_resume_rx(struct rtw89_ser *ser)
291 {
292 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
293 
294 	if (!test_bit(RTW89_SER_DRV_STOP_RX, ser->flags))
295 		return;
296 
297 	set_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
298 	clear_bit(RTW89_SER_DRV_STOP_RX, ser->flags);
299 }
300 
ser_reset_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)301 static void ser_reset_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
302 {
303 	rtw89_core_release_bit_map(rtwdev->hw_port, rtwvif->port);
304 	rtwvif->net_type = RTW89_NET_TYPE_NO_LINK;
305 	rtwvif->trigger = false;
306 	rtwvif->tdls_peer = 0;
307 }
308 
ser_sta_deinit_cam_iter(void * data,struct ieee80211_sta * sta)309 static void ser_sta_deinit_cam_iter(void *data, struct ieee80211_sta *sta)
310 {
311 	struct rtw89_vif *target_rtwvif = (struct rtw89_vif *)data;
312 	struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
313 	struct rtw89_vif *rtwvif = rtwsta->rtwvif;
314 	struct rtw89_dev *rtwdev = rtwvif->rtwdev;
315 
316 	if (rtwvif != target_rtwvif)
317 		return;
318 
319 	if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
320 		rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam);
321 	if (sta->tdls)
322 		rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam);
323 
324 	INIT_LIST_HEAD(&rtwsta->ba_cam_list);
325 }
326 
ser_deinit_cam(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)327 static void ser_deinit_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
328 {
329 	ieee80211_iterate_stations_atomic(rtwdev->hw,
330 					  ser_sta_deinit_cam_iter,
331 					  rtwvif);
332 
333 	rtw89_cam_deinit(rtwdev, rtwvif);
334 
335 	bitmap_zero(rtwdev->cam_info.ba_cam_map, RTW89_MAX_BA_CAM_NUM);
336 }
337 
ser_reset_mac_binding(struct rtw89_dev * rtwdev)338 static void ser_reset_mac_binding(struct rtw89_dev *rtwdev)
339 {
340 	struct rtw89_vif *rtwvif;
341 
342 	rtw89_cam_reset_keys(rtwdev);
343 	rtw89_for_each_rtwvif(rtwdev, rtwvif)
344 		ser_deinit_cam(rtwdev, rtwvif);
345 
346 	rtw89_core_release_all_bits_map(rtwdev->mac_id_map, RTW89_MAX_MAC_ID_NUM);
347 	rtw89_for_each_rtwvif(rtwdev, rtwvif)
348 		ser_reset_vif(rtwdev, rtwvif);
349 
350 	rtwdev->total_sta_assoc = 0;
351 }
352 
353 /* hal function */
hal_enable_dma(struct rtw89_ser * ser)354 static int hal_enable_dma(struct rtw89_ser *ser)
355 {
356 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
357 	int ret;
358 
359 	if (!test_bit(RTW89_SER_HAL_STOP_DMA, ser->flags))
360 		return 0;
361 
362 	if (!rtwdev->hci.ops->mac_lv1_rcvy)
363 		return -EIO;
364 
365 	ret = rtwdev->hci.ops->mac_lv1_rcvy(rtwdev, RTW89_LV1_RCVY_STEP_2);
366 	if (!ret)
367 		clear_bit(RTW89_SER_HAL_STOP_DMA, ser->flags);
368 	else
369 		rtw89_debug(rtwdev, RTW89_DBG_SER,
370 			    "lv1 rcvy fail to start dma: %d\n", ret);
371 
372 	return ret;
373 }
374 
hal_stop_dma(struct rtw89_ser * ser)375 static int hal_stop_dma(struct rtw89_ser *ser)
376 {
377 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
378 	int ret;
379 
380 	if (!rtwdev->hci.ops->mac_lv1_rcvy)
381 		return -EIO;
382 
383 	ret = rtwdev->hci.ops->mac_lv1_rcvy(rtwdev, RTW89_LV1_RCVY_STEP_1);
384 	if (!ret)
385 		set_bit(RTW89_SER_HAL_STOP_DMA, ser->flags);
386 	else
387 		rtw89_debug(rtwdev, RTW89_DBG_SER,
388 			    "lv1 rcvy fail to stop dma: %d\n", ret);
389 
390 	return ret;
391 }
392 
hal_send_post_m0_event(struct rtw89_ser * ser)393 static void hal_send_post_m0_event(struct rtw89_ser *ser)
394 {
395 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
396 
397 	rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_START_DMAC);
398 }
399 
hal_send_m2_event(struct rtw89_ser * ser)400 static void hal_send_m2_event(struct rtw89_ser *ser)
401 {
402 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
403 
404 	rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_DISABLE_EN);
405 }
406 
hal_send_m4_event(struct rtw89_ser * ser)407 static void hal_send_m4_event(struct rtw89_ser *ser)
408 {
409 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
410 
411 	rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RCVY_EN);
412 }
413 
414 /* state handler */
ser_idle_st_hdl(struct rtw89_ser * ser,u8 evt)415 static void ser_idle_st_hdl(struct rtw89_ser *ser, u8 evt)
416 {
417 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
418 
419 	switch (evt) {
420 	case SER_EV_STATE_IN:
421 		rtw89_hci_recovery_complete(rtwdev);
422 		clear_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags);
423 		clear_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags);
424 		break;
425 	case SER_EV_L1_RESET_PREPARE:
426 		ser_state_goto(ser, SER_L1_RESET_PRE_ST);
427 		break;
428 	case SER_EV_L1_RESET:
429 		ser_state_goto(ser, SER_RESET_TRX_ST);
430 		break;
431 	case SER_EV_L2_RESET:
432 		ser_state_goto(ser, SER_L2_RESET_ST);
433 		break;
434 	case SER_EV_STATE_OUT:
435 		set_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags);
436 		rtw89_hci_recovery_start(rtwdev);
437 		break;
438 	default:
439 		break;
440 	}
441 }
442 
ser_l1_reset_pre_st_hdl(struct rtw89_ser * ser,u8 evt)443 static void ser_l1_reset_pre_st_hdl(struct rtw89_ser *ser, u8 evt)
444 {
445 	switch (evt) {
446 	case SER_EV_STATE_IN:
447 		ser->prehandle_l1 = true;
448 		hal_send_post_m0_event(ser);
449 		ser_set_alarm(ser, 1000, SER_EV_M1_TIMEOUT);
450 		break;
451 	case SER_EV_L1_RESET:
452 		ser_state_goto(ser, SER_RESET_TRX_ST);
453 		break;
454 	case SER_EV_M1_TIMEOUT:
455 		ser_state_goto(ser, SER_L2_RESET_ST);
456 		break;
457 	case SER_EV_STATE_OUT:
458 		ser_del_alarm(ser);
459 		break;
460 	default:
461 		break;
462 	}
463 }
464 
ser_reset_trx_st_hdl(struct rtw89_ser * ser,u8 evt)465 static void ser_reset_trx_st_hdl(struct rtw89_ser *ser, u8 evt)
466 {
467 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
468 
469 	switch (evt) {
470 	case SER_EV_STATE_IN:
471 		cancel_delayed_work_sync(&rtwdev->track_work);
472 		drv_stop_tx(ser);
473 
474 		if (hal_stop_dma(ser)) {
475 			ser_state_goto(ser, SER_L2_RESET_ST);
476 			break;
477 		}
478 
479 		drv_stop_rx(ser);
480 		drv_trx_reset(ser);
481 
482 		/* wait m3 */
483 		hal_send_m2_event(ser);
484 
485 		/* set alarm to prevent FW response timeout */
486 		ser_set_alarm(ser, 1000, SER_EV_M3_TIMEOUT);
487 		break;
488 
489 	case SER_EV_DO_RECOVERY:
490 		ser_state_goto(ser, SER_DO_HCI_ST);
491 		break;
492 
493 	case SER_EV_M3_TIMEOUT:
494 		ser_state_goto(ser, SER_L2_RESET_ST);
495 		break;
496 
497 	case SER_EV_STATE_OUT:
498 		ser_del_alarm(ser);
499 		hal_enable_dma(ser);
500 		drv_resume_rx(ser);
501 		drv_resume_tx(ser);
502 		ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
503 					     RTW89_TRACK_WORK_PERIOD);
504 		break;
505 
506 	default:
507 		break;
508 	}
509 }
510 
ser_do_hci_st_hdl(struct rtw89_ser * ser,u8 evt)511 static void ser_do_hci_st_hdl(struct rtw89_ser *ser, u8 evt)
512 {
513 	switch (evt) {
514 	case SER_EV_STATE_IN:
515 		/* wait m5 */
516 		hal_send_m4_event(ser);
517 
518 		/* prevent FW response timeout */
519 		ser_set_alarm(ser, 1000, SER_EV_FW_M5_TIMEOUT);
520 		break;
521 
522 	case SER_EV_FW_M5_TIMEOUT:
523 		ser_state_goto(ser, SER_L2_RESET_ST);
524 		break;
525 
526 	case SER_EV_MAC_RESET_DONE:
527 		ser_state_goto(ser, SER_IDLE_ST);
528 		break;
529 
530 	case SER_EV_STATE_OUT:
531 		ser_del_alarm(ser);
532 		break;
533 
534 	default:
535 		break;
536 	}
537 }
538 
ser_mac_mem_dump(struct rtw89_dev * rtwdev,u8 * buf,u8 sel,u32 start_addr,u32 len)539 static void ser_mac_mem_dump(struct rtw89_dev *rtwdev, u8 *buf,
540 			     u8 sel, u32 start_addr, u32 len)
541 {
542 	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
543 	u32 filter_model_addr = mac->filter_model_addr;
544 	u32 indir_access_addr = mac->indir_access_addr;
545 	u32 *ptr = (u32 *)buf;
546 	u32 base_addr, start_page, residue;
547 	u32 cnt = 0;
548 	u32 i;
549 
550 	start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE;
551 	residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE;
552 	base_addr = mac->mem_base_addrs[sel];
553 	base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE;
554 
555 	while (cnt < len) {
556 		rtw89_write32(rtwdev, filter_model_addr, base_addr);
557 
558 		for (i = indir_access_addr + residue;
559 		     i < indir_access_addr + MAC_MEM_DUMP_PAGE_SIZE;
560 		     i += 4, ptr++) {
561 			*ptr = rtw89_read32(rtwdev, i);
562 			cnt += 4;
563 			if (cnt >= len)
564 				break;
565 		}
566 
567 		residue = 0;
568 		base_addr += MAC_MEM_DUMP_PAGE_SIZE;
569 	}
570 }
571 
rtw89_ser_fw_rsvd_ple_dump(struct rtw89_dev * rtwdev,u8 * buf)572 static void rtw89_ser_fw_rsvd_ple_dump(struct rtw89_dev *rtwdev, u8 *buf)
573 {
574 	u32 start_addr = rtwdev->chip->rsvd_ple_ofst;
575 
576 	rtw89_debug(rtwdev, RTW89_DBG_SER,
577 		    "dump mem for fw rsvd payload engine (start addr: 0x%x)\n",
578 		    start_addr);
579 	ser_mac_mem_dump(rtwdev, buf, RTW89_MAC_MEM_SHARED_BUF, start_addr,
580 			 RTW89_FW_RSVD_PLE_SIZE);
581 }
582 
583 struct __fw_backtrace_entry {
584 	u32 wcpu_addr;
585 	u32 size;
586 	u32 key;
587 } __packed;
588 
589 struct __fw_backtrace_info {
590 	u32 ra;
591 	u32 sp;
592 } __packed;
593 
594 static_assert(RTW89_FW_BACKTRACE_INFO_SIZE ==
595 	      sizeof(struct __fw_backtrace_info));
596 
convert_addr_from_wcpu(u32 wcpu_addr)597 static u32 convert_addr_from_wcpu(u32 wcpu_addr)
598 {
599 	if (wcpu_addr < 0x30000000)
600 		return wcpu_addr;
601 
602 	return wcpu_addr & GENMASK(28, 0);
603 }
604 
rtw89_ser_fw_backtrace_dump(struct rtw89_dev * rtwdev,u8 * buf,const struct __fw_backtrace_entry * ent)605 static int rtw89_ser_fw_backtrace_dump(struct rtw89_dev *rtwdev, u8 *buf,
606 				       const struct __fw_backtrace_entry *ent)
607 {
608 	struct __fw_backtrace_info *ptr = (struct __fw_backtrace_info *)buf;
609 	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
610 	u32 filter_model_addr = mac->filter_model_addr;
611 	u32 indir_access_addr = mac->indir_access_addr;
612 	u32 fwbt_addr = convert_addr_from_wcpu(ent->wcpu_addr);
613 	u32 fwbt_size = ent->size;
614 	u32 fwbt_key = ent->key;
615 	u32 i;
616 
617 	if (fwbt_addr == 0) {
618 		rtw89_warn(rtwdev, "FW backtrace invalid address: 0x%x\n",
619 			   fwbt_addr);
620 		return -EINVAL;
621 	}
622 
623 	if (fwbt_key != RTW89_FW_BACKTRACE_KEY) {
624 		rtw89_warn(rtwdev, "FW backtrace invalid key: 0x%x\n",
625 			   fwbt_key);
626 		return -EINVAL;
627 	}
628 
629 	if (fwbt_size == 0 || !RTW89_VALID_FW_BACKTRACE_SIZE(fwbt_size) ||
630 	    fwbt_size > RTW89_FW_BACKTRACE_MAX_SIZE) {
631 		rtw89_warn(rtwdev, "FW backtrace invalid size: 0x%x\n",
632 			   fwbt_size);
633 		return -EINVAL;
634 	}
635 
636 	rtw89_debug(rtwdev, RTW89_DBG_SER, "dump fw backtrace start\n");
637 	rtw89_write32(rtwdev, filter_model_addr, fwbt_addr);
638 
639 	for (i = indir_access_addr;
640 	     i < indir_access_addr + fwbt_size;
641 	     i += RTW89_FW_BACKTRACE_INFO_SIZE, ptr++) {
642 		*ptr = (struct __fw_backtrace_info){
643 			.ra = rtw89_read32(rtwdev, i),
644 			.sp = rtw89_read32(rtwdev, i + 4),
645 		};
646 		rtw89_debug(rtwdev, RTW89_DBG_SER,
647 			    "next sp: 0x%x, next ra: 0x%x\n",
648 			    ptr->sp, ptr->ra);
649 	}
650 
651 	rtw89_debug(rtwdev, RTW89_DBG_SER, "dump fw backtrace end\n");
652 	return 0;
653 }
654 
ser_l2_reset_st_pre_hdl(struct rtw89_ser * ser)655 static void ser_l2_reset_st_pre_hdl(struct rtw89_ser *ser)
656 {
657 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
658 	struct rtw89_ser_cd_buffer *buf;
659 	struct __fw_backtrace_entry fwbt_ent;
660 	int ret = 0;
661 
662 	buf = rtw89_ser_cd_prep(rtwdev);
663 	if (!buf) {
664 		ret = -ENOMEM;
665 		goto bottom;
666 	}
667 
668 	rtw89_ser_fw_rsvd_ple_dump(rtwdev, buf->fwple.data);
669 
670 	fwbt_ent = *(struct __fw_backtrace_entry *)buf->fwple.data;
671 	ret = rtw89_ser_fw_backtrace_dump(rtwdev, buf->fwbt.data, &fwbt_ent);
672 	if (ret)
673 		goto bottom;
674 
675 	rtw89_ser_cd_send(rtwdev, buf);
676 
677 bottom:
678 	rtw89_ser_cd_free(rtwdev, buf, !!ret);
679 
680 	ser_reset_mac_binding(rtwdev);
681 	rtw89_core_stop(rtwdev);
682 	rtw89_entity_init(rtwdev);
683 	rtw89_fw_release_general_pkt_list(rtwdev, false);
684 	INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
685 }
686 
ser_l2_reset_st_hdl(struct rtw89_ser * ser,u8 evt)687 static void ser_l2_reset_st_hdl(struct rtw89_ser *ser, u8 evt)
688 {
689 	struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
690 
691 	switch (evt) {
692 	case SER_EV_STATE_IN:
693 		mutex_lock(&rtwdev->mutex);
694 		ser_l2_reset_st_pre_hdl(ser);
695 		mutex_unlock(&rtwdev->mutex);
696 
697 		ieee80211_restart_hw(rtwdev->hw);
698 		ser_set_alarm(ser, SER_RECFG_TIMEOUT, SER_EV_L2_RECFG_TIMEOUT);
699 		break;
700 
701 	case SER_EV_L2_RECFG_TIMEOUT:
702 		rtw89_info(rtwdev, "Err: ser L2 re-config timeout\n");
703 		fallthrough;
704 	case SER_EV_L2_RECFG_DONE:
705 		ser_state_goto(ser, SER_IDLE_ST);
706 		break;
707 
708 	case SER_EV_STATE_OUT:
709 		ser_del_alarm(ser);
710 		break;
711 
712 	default:
713 		break;
714 	}
715 }
716 
717 static const struct event_ent ser_ev_tbl[] = {
718 	{SER_EV_NONE, "SER_EV_NONE"},
719 	{SER_EV_STATE_IN, "SER_EV_STATE_IN"},
720 	{SER_EV_STATE_OUT, "SER_EV_STATE_OUT"},
721 	{SER_EV_L1_RESET_PREPARE, "SER_EV_L1_RESET_PREPARE pre-m0"},
722 	{SER_EV_L1_RESET, "SER_EV_L1_RESET m1"},
723 	{SER_EV_DO_RECOVERY, "SER_EV_DO_RECOVERY m3"},
724 	{SER_EV_MAC_RESET_DONE, "SER_EV_MAC_RESET_DONE m5"},
725 	{SER_EV_L2_RESET, "SER_EV_L2_RESET"},
726 	{SER_EV_L2_RECFG_DONE, "SER_EV_L2_RECFG_DONE"},
727 	{SER_EV_L2_RECFG_TIMEOUT, "SER_EV_L2_RECFG_TIMEOUT"},
728 	{SER_EV_M1_TIMEOUT, "SER_EV_M1_TIMEOUT"},
729 	{SER_EV_M3_TIMEOUT, "SER_EV_M3_TIMEOUT"},
730 	{SER_EV_FW_M5_TIMEOUT, "SER_EV_FW_M5_TIMEOUT"},
731 	{SER_EV_L0_RESET, "SER_EV_L0_RESET"},
732 	{SER_EV_MAXX, "SER_EV_MAX"}
733 };
734 
735 static const struct state_ent ser_st_tbl[] = {
736 	{SER_IDLE_ST, "SER_IDLE_ST", ser_idle_st_hdl},
737 	{SER_L1_RESET_PRE_ST, "SER_L1_RESET_PRE_ST", ser_l1_reset_pre_st_hdl},
738 	{SER_RESET_TRX_ST, "SER_RESET_TRX_ST", ser_reset_trx_st_hdl},
739 	{SER_DO_HCI_ST, "SER_DO_HCI_ST", ser_do_hci_st_hdl},
740 	{SER_L2_RESET_ST, "SER_L2_RESET_ST", ser_l2_reset_st_hdl}
741 };
742 
rtw89_ser_init(struct rtw89_dev * rtwdev)743 int rtw89_ser_init(struct rtw89_dev *rtwdev)
744 {
745 	struct rtw89_ser *ser = &rtwdev->ser;
746 
747 	memset(ser, 0, sizeof(*ser));
748 	INIT_LIST_HEAD(&ser->msg_q);
749 	ser->state = SER_IDLE_ST;
750 	ser->st_tbl = ser_st_tbl;
751 	ser->ev_tbl = ser_ev_tbl;
752 
753 	bitmap_zero(ser->flags, RTW89_NUM_OF_SER_FLAGS);
754 	spin_lock_init(&ser->msg_q_lock);
755 	INIT_WORK(&ser->ser_hdl_work, rtw89_ser_hdl_work);
756 	INIT_DELAYED_WORK(&ser->ser_alarm_work, rtw89_ser_alarm_work);
757 	return 0;
758 }
759 
rtw89_ser_deinit(struct rtw89_dev * rtwdev)760 int rtw89_ser_deinit(struct rtw89_dev *rtwdev)
761 {
762 	struct rtw89_ser *ser = (struct rtw89_ser *)&rtwdev->ser;
763 
764 	set_bit(RTW89_SER_DRV_STOP_RUN, ser->flags);
765 	cancel_delayed_work_sync(&ser->ser_alarm_work);
766 	cancel_work_sync(&ser->ser_hdl_work);
767 	clear_bit(RTW89_SER_DRV_STOP_RUN, ser->flags);
768 	return 0;
769 }
770 
rtw89_ser_recfg_done(struct rtw89_dev * rtwdev)771 void rtw89_ser_recfg_done(struct rtw89_dev *rtwdev)
772 {
773 	ser_send_msg(&rtwdev->ser, SER_EV_L2_RECFG_DONE);
774 }
775 
rtw89_ser_notify(struct rtw89_dev * rtwdev,u32 err)776 int rtw89_ser_notify(struct rtw89_dev *rtwdev, u32 err)
777 {
778 	u8 event = SER_EV_NONE;
779 
780 	rtw89_info(rtwdev, "SER catches error: 0x%x\n", err);
781 
782 	switch (err) {
783 	case MAC_AX_ERR_L1_PREERR_DMAC: /* pre-M0 */
784 		event = SER_EV_L1_RESET_PREPARE;
785 		break;
786 	case MAC_AX_ERR_L1_ERR_DMAC:
787 	case MAC_AX_ERR_L0_PROMOTE_TO_L1:
788 		event = SER_EV_L1_RESET; /* M1 */
789 		break;
790 	case MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE:
791 		event = SER_EV_DO_RECOVERY; /* M3 */
792 		break;
793 	case MAC_AX_ERR_L1_RESET_RECOVERY_DONE:
794 		event = SER_EV_MAC_RESET_DONE; /* M5 */
795 		break;
796 	case MAC_AX_ERR_L0_ERR_CMAC0:
797 	case MAC_AX_ERR_L0_ERR_CMAC1:
798 	case MAC_AX_ERR_L0_RESET_DONE:
799 		event = SER_EV_L0_RESET;
800 		break;
801 	default:
802 		if (err == MAC_AX_ERR_L1_PROMOTE_TO_L2 ||
803 		    (err >= MAC_AX_ERR_L2_ERR_AH_DMA &&
804 		     err <= MAC_AX_GET_ERR_MAX))
805 			event = SER_EV_L2_RESET;
806 		break;
807 	}
808 
809 	if (event == SER_EV_NONE) {
810 		rtw89_warn(rtwdev, "SER cannot recognize error: 0x%x\n", err);
811 		return -EINVAL;
812 	}
813 
814 	ser_send_msg(&rtwdev->ser, event);
815 	return 0;
816 }
817 EXPORT_SYMBOL(rtw89_ser_notify);
818