1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver
4 //
5 // Copyright(c) 2024 Realtek Semiconductor Corp.
6 //
7 //
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/regmap.h>
14 #include <linux/dmi.h>
15 #include <linux/firmware.h>
16 #include <sound/core.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc-dapm.h>
20 #include <sound/initval.h>
21 #include <sound/tlv.h>
22 #include <sound/sdw.h>
23 #include "rt1320-sdw.h"
24 #include "rt-sdw-common.h"
25
26 /*
27 * The 'blind writes' is an SDCA term to deal with platform-specific initialization.
28 * It might include vendor-specific or SDCA control registers.
29 */
30 static const struct reg_sequence rt1320_blind_write[] = {
31 { 0xc003, 0xe0 },
32 { 0xc01b, 0xfc },
33 { 0xc5c3, 0xf2 },
34 { 0xc5c2, 0x00 },
35 { 0xc5c6, 0x10 },
36 { 0xc5c4, 0x12 },
37 { 0xc5c8, 0x03 },
38 { 0xc5d8, 0x0a },
39 { 0xc5f7, 0x22 },
40 { 0xc5f6, 0x22 },
41 { 0xc5d0, 0x0f },
42 { 0xc5d1, 0x89 },
43 { 0xc057, 0x51 },
44 { 0xc054, 0x35 },
45 { 0xc053, 0x55 },
46 { 0xc052, 0x55 },
47 { 0xc051, 0x13 },
48 { 0xc050, 0x15 },
49 { 0xc060, 0x77 },
50 { 0xc061, 0x55 },
51 { 0xc063, 0x55 },
52 { 0xc065, 0xa5 },
53 { 0xc06b, 0x0a },
54 { 0xca05, 0xd6 },
55 { 0xca25, 0xd6 },
56 { 0xcd00, 0x05 },
57 { 0xc604, 0x40 },
58 { 0xc609, 0x40 },
59 { 0xc046, 0xff },
60 { 0xc045, 0xff },
61 { 0xc044, 0xff },
62 { 0xc043, 0xff },
63 { 0xc042, 0xff },
64 { 0xc041, 0xff },
65 { 0xc040, 0xff },
66 { 0xcc10, 0x01 },
67 { 0xc700, 0xf0 },
68 { 0xc701, 0x13 },
69 { 0xc901, 0x04 },
70 { 0xc900, 0x73 },
71 { 0xde03, 0x05 },
72 { 0xdd0b, 0x0d },
73 { 0xdd0a, 0xff },
74 { 0xdd09, 0x0d },
75 { 0xdd08, 0xff },
76 { 0xc570, 0x08 },
77 { 0xe803, 0xbe },
78 { 0xc003, 0xc0 },
79 { 0xc081, 0xfe },
80 { 0xce31, 0x0d },
81 { 0xce30, 0xae },
82 { 0xce37, 0x0b },
83 { 0xce36, 0xd2 },
84 { 0xce39, 0x04 },
85 { 0xce38, 0x80 },
86 { 0xce3f, 0x00 },
87 { 0xce3e, 0x00 },
88 { 0xd470, 0x8b },
89 { 0xd471, 0x18 },
90 { 0xc019, 0x10 },
91 { 0xd487, 0x3f },
92 { 0xd486, 0xc3 },
93 { 0x3fc2bfc7, 0x00 },
94 { 0x3fc2bfc6, 0x00 },
95 { 0x3fc2bfc5, 0x00 },
96 { 0x3fc2bfc4, 0x01 },
97 { 0x0000d486, 0x43 },
98 { 0x1000db00, 0x02 },
99 { 0x1000db01, 0x00 },
100 { 0x1000db02, 0x11 },
101 { 0x1000db03, 0x00 },
102 { 0x1000db04, 0x00 },
103 { 0x1000db05, 0x82 },
104 { 0x1000db06, 0x04 },
105 { 0x1000db07, 0xf1 },
106 { 0x1000db08, 0x00 },
107 { 0x1000db09, 0x00 },
108 { 0x1000db0a, 0x40 },
109 { 0x0000d540, 0x01 },
110 { 0xd172, 0x2a },
111 { 0xc5d6, 0x01 },
112 { 0xd478, 0xff },
113 };
114
115 static const struct reg_sequence rt1320_vc_blind_write[] = {
116 { 0xc003, 0xe0 },
117 { 0xe80a, 0x01 },
118 { 0xc5c3, 0xf2 },
119 { 0xc5c8, 0x03 },
120 { 0xc057, 0x51 },
121 { 0xc054, 0x35 },
122 { 0xca05, 0xd6 },
123 { 0xca07, 0x07 },
124 { 0xca25, 0xd6 },
125 { 0xca27, 0x07 },
126 { 0xc604, 0x40 },
127 { 0xc609, 0x40 },
128 { 0xc046, 0xff },
129 { 0xc045, 0xff },
130 { 0xc044, 0xff },
131 { 0xc043, 0xff },
132 { 0xc042, 0xff },
133 { 0xc041, 0x7f },
134 { 0xc040, 0xff },
135 { 0xcc10, 0x01 },
136 { 0xc700, 0xf0 },
137 { 0xc701, 0x13 },
138 { 0xc901, 0x04 },
139 { 0xc900, 0x73 },
140 { 0xde03, 0x05 },
141 { 0xdd0b, 0x0d },
142 { 0xdd0a, 0xff },
143 { 0xdd09, 0x0d },
144 { 0xdd08, 0xff },
145 { 0xc570, 0x08 },
146 { 0xc086, 0x02 },
147 { 0xc085, 0x7f },
148 { 0xc084, 0x00 },
149 { 0xc081, 0xfe },
150 { 0xf084, 0x0f },
151 { 0xf083, 0xff },
152 { 0xf082, 0xff },
153 { 0xf081, 0xff },
154 { 0xf080, 0xff },
155 { 0xe801, 0x01 },
156 { 0xe802, 0xf8 },
157 { 0xe803, 0xbe },
158 { 0xc003, 0xc0 },
159 { 0xd470, 0xec },
160 { 0xd471, 0x3a },
161 { 0xd474, 0x11 },
162 { 0xd475, 0x32 },
163 { 0xd478, 0xff },
164 { 0xd479, 0x20 },
165 { 0xd47a, 0x10 },
166 { 0xd47c, 0xff },
167 { 0xc019, 0x10 },
168 { 0xd487, 0x0b },
169 { 0xd487, 0x3b },
170 { 0xd486, 0xc3 },
171 { 0xc598, 0x04 },
172 { 0xdb03, 0xf0 },
173 { 0xdb09, 0x00 },
174 { 0xdb08, 0x7a },
175 { 0xdb19, 0x02 },
176 { 0xdb07, 0x5a },
177 { 0xdb05, 0x45 },
178 { 0xd500, 0x00 },
179 { 0xd500, 0x17 },
180 { 0xd600, 0x01 },
181 { 0xd601, 0x02 },
182 { 0xd602, 0x03 },
183 { 0xd603, 0x04 },
184 { 0xd64c, 0x03 },
185 { 0xd64d, 0x03 },
186 { 0xd64e, 0x03 },
187 { 0xd64f, 0x03 },
188 { 0xd650, 0x03 },
189 { 0xd651, 0x03 },
190 { 0xd652, 0x03 },
191 { 0xd610, 0x01 },
192 { 0xd608, 0x03 },
193 { 0xd609, 0x00 },
194 { 0x3fc2bf83, 0x00 },
195 { 0x3fc2bf82, 0x00 },
196 { 0x3fc2bf81, 0x00 },
197 { 0x3fc2bf80, 0x00 },
198 { 0x3fc2bfc7, 0x00 },
199 { 0x3fc2bfc6, 0x00 },
200 { 0x3fc2bfc5, 0x00 },
201 { 0x3fc2bfc4, 0x00 },
202 { 0x3fc2bfc3, 0x00 },
203 { 0x3fc2bfc2, 0x00 },
204 { 0x3fc2bfc1, 0x00 },
205 { 0x3fc2bfc0, 0x07 },
206 { 0x1000cc46, 0x00 },
207 { 0x0000d486, 0x43 },
208 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 },
209 { 0x1000db00, 0x07 },
210 { 0x1000db01, 0x00 },
211 { 0x1000db02, 0x11 },
212 { 0x1000db03, 0x00 },
213 { 0x1000db04, 0x00 },
214 { 0x1000db05, 0x82 },
215 { 0x1000db06, 0x04 },
216 { 0x1000db07, 0xf1 },
217 { 0x1000db08, 0x00 },
218 { 0x1000db09, 0x00 },
219 { 0x1000db0a, 0x40 },
220 { 0x1000db0b, 0x02 },
221 { 0x1000db0c, 0xf2 },
222 { 0x1000db0d, 0x00 },
223 { 0x1000db0e, 0x00 },
224 { 0x1000db0f, 0xe0 },
225 { 0x1000db10, 0x00 },
226 { 0x1000db11, 0x10 },
227 { 0x1000db12, 0x00 },
228 { 0x1000db13, 0x00 },
229 { 0x1000db14, 0x45 },
230 { 0x1000db15, 0x0d },
231 { 0x1000db16, 0x01 },
232 { 0x1000db17, 0x00 },
233 { 0x1000db18, 0x00 },
234 { 0x1000db19, 0xbf },
235 { 0x1000db1a, 0x13 },
236 { 0x1000db1b, 0x09 },
237 { 0x1000db1c, 0x00 },
238 { 0x1000db1d, 0x00 },
239 { 0x1000db1e, 0x00 },
240 { 0x1000db1f, 0x12 },
241 { 0x1000db20, 0x09 },
242 { 0x1000db21, 0x00 },
243 { 0x1000db22, 0x00 },
244 { 0x1000db23, 0x00 },
245 { 0x0000d540, 0x21 },
246 { 0xc01b, 0xfc },
247 { 0xc5d1, 0x89 },
248 { 0xc5d8, 0x0a },
249 { 0xc5f7, 0x22 },
250 { 0xc5f6, 0x22 },
251 { 0xc065, 0xa5 },
252 { 0xc06b, 0x0a },
253 { 0xd172, 0x2a },
254 { 0xc5d6, 0x01 },
255 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
256 };
257
258 static const struct reg_sequence rt1321_blind_write[] = {
259 { 0x0000c003, 0xf0 },
260 { 0x0000c01b, 0xfc },
261 { 0x0000c5c3, 0xf2 },
262 { 0x0000c5c2, 0x00 },
263 { 0x0000c5c1, 0x10 },
264 { 0x0000c5c0, 0x04 },
265 { 0x0000c5c7, 0x03 },
266 { 0x0000c5c6, 0x10 },
267 { 0x0000c526, 0x47 },
268 { 0x0000c5c4, 0x12 },
269 { 0x0000c5c5, 0x60 },
270 { 0x0000c520, 0x10 },
271 { 0x0000c521, 0x32 },
272 { 0x0000c5c7, 0x00 },
273 { 0x0000c5c8, 0x03 },
274 { 0x0000c5d3, 0x08 },
275 { 0x0000c5d2, 0x0a },
276 { 0x0000c5d1, 0x49 },
277 { 0x0000c5d0, 0x0f },
278 { 0x0000c580, 0x10 },
279 { 0x0000c581, 0x32 },
280 { 0x0000c582, 0x01 },
281 { 0x0000cb00, 0x03 },
282 { 0x0000cb02, 0x52 },
283 { 0x0000cb04, 0x80 },
284 { 0x0000cb0b, 0x01 },
285 { 0x0000c682, 0x60 },
286 { 0x0000c019, 0x10 },
287 { 0x0000c5f0, 0x01 },
288 { 0x0000c5f7, 0x22 },
289 { 0x0000c5f6, 0x22 },
290 { 0x0000c057, 0x51 },
291 { 0x0000c054, 0x55 },
292 { 0x0000c053, 0x55 },
293 { 0x0000c052, 0x55 },
294 { 0x0000c051, 0x01 },
295 { 0x0000c050, 0x15 },
296 { 0x0000c060, 0x99 },
297 { 0x0000c030, 0x55 },
298 { 0x0000c061, 0x55 },
299 { 0x0000c063, 0x55 },
300 { 0x0000c065, 0xa5 },
301 { 0x0000c06b, 0x0a },
302 { 0x0000ca05, 0xd6 },
303 { 0x0000ca07, 0x07 },
304 { 0x0000ca25, 0xd6 },
305 { 0x0000ca27, 0x07 },
306 { 0x0000cd00, 0x05 },
307 { 0x0000c604, 0x40 },
308 { 0x0000c609, 0x40 },
309 { 0x0000c046, 0xf7 },
310 { 0x0000c045, 0xff },
311 { 0x0000c044, 0xff },
312 { 0x0000c043, 0xff },
313 { 0x0000c042, 0xff },
314 { 0x0000c041, 0xff },
315 { 0x0000c040, 0xff },
316 { 0x0000c049, 0xff },
317 { 0x0000c028, 0x3f },
318 { 0x0000c020, 0x3f },
319 { 0x0000c032, 0x13 },
320 { 0x0000c033, 0x01 },
321 { 0x0000cc10, 0x01 },
322 { 0x0000dc20, 0x03 },
323 { 0x0000de03, 0x05 },
324 { 0x0000dc00, 0x00 },
325 { 0x0000c700, 0xf0 },
326 { 0x0000c701, 0x13 },
327 { 0x0000c900, 0xc3 },
328 { 0x0000c570, 0x08 },
329 { 0x0000c086, 0x02 },
330 { 0x0000c085, 0x7f },
331 { 0x0000c084, 0x00 },
332 { 0x0000c081, 0xff },
333 { 0x0000f084, 0x0f },
334 { 0x0000f083, 0xff },
335 { 0x0000f082, 0xff },
336 { 0x0000f081, 0xff },
337 { 0x0000f080, 0xff },
338 { 0x20003003, 0x3f },
339 { 0x20005818, 0x81 },
340 { 0x20009018, 0x81 },
341 { 0x2000301c, 0x81 },
342 { 0x0000c003, 0xc0 },
343 { 0x0000c047, 0x80 },
344 { 0x0000d541, 0x80 },
345 { 0x0000d487, 0x0b },
346 { 0x0000d487, 0x3b },
347 { 0x0000d486, 0xc3 },
348 { 0x0000d470, 0x89 },
349 { 0x0000d471, 0x3a },
350 { 0x0000d472, 0x1d },
351 { 0x0000d478, 0xff },
352 { 0x0000d479, 0x20 },
353 { 0x0000d47a, 0x10 },
354 { 0x0000d73c, 0xb7 },
355 { 0x0000d73d, 0xd7 },
356 { 0x0000d73e, 0x00 },
357 { 0x0000d73f, 0x10 },
358 { 0x1000cd56, 0x00 },
359 { 0x3fc2dfc3, 0x00 },
360 { 0x3fc2dfc2, 0x00 },
361 { 0x3fc2dfc1, 0x00 },
362 { 0x3fc2dfc0, 0x07 },
363 { 0x3fc2dfc7, 0x00 },
364 { 0x3fc2dfc6, 0x00 },
365 { 0x3fc2dfc5, 0x00 },
366 { 0x3fc2dfc4, 0x01 },
367 { 0x3fc2df83, 0x00 },
368 { 0x3fc2df82, 0x00 },
369 { 0x3fc2df81, 0x00 },
370 { 0x3fc2df80, 0x00 },
371 { 0x0000d541, 0x40 },
372 { 0x0000d486, 0x43 },
373 { 0x1000db00, 0x03 },
374 { 0x1000db01, 0x00 },
375 { 0x1000db02, 0x10 },
376 { 0x1000db03, 0x00 },
377 { 0x1000db04, 0x00 },
378 { 0x1000db05, 0x45 },
379 { 0x1000db06, 0x12 },
380 { 0x1000db07, 0x09 },
381 { 0x1000db08, 0x00 },
382 { 0x1000db09, 0x00 },
383 { 0x1000db0a, 0x00 },
384 { 0x1000db0b, 0x13 },
385 { 0x1000db0c, 0x09 },
386 { 0x1000db0d, 0x00 },
387 { 0x1000db0e, 0x00 },
388 { 0x1000db0f, 0x00 },
389 { 0x0000d540, 0x21 },
390 { 0x41000189, 0x00 },
391 { 0x4100018a, 0x00 },
392 { 0x41001988, 0x00 },
393 { 0x41081400, 0x09 },
394 { 0x40801508, 0x03 },
395 { 0x40801588, 0x03 },
396 { 0x40801809, 0x00 },
397 { 0x4080180a, 0x00 },
398 { 0x4080180b, 0x00 },
399 { 0x4080180c, 0x00 },
400 { 0x40801b09, 0x00 },
401 { 0x40801b0a, 0x00 },
402 { 0x40801b0b, 0x00 },
403 { 0x40801b0c, 0x00 },
404 { 0x0000d714, 0x17 },
405 { 0x20009012, 0x00 },
406 { 0x0000dd0b, 0x0d },
407 { 0x0000dd0a, 0xff },
408 { 0x0000dd09, 0x0d },
409 { 0x0000dd08, 0xff },
410 { 0x0000d172, 0x2a },
411 { 0x41001988, 0x03 },
412 };
413
414 static const struct reg_default rt1320_reg_defaults[] = {
415 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
416 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
417 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
418 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
419 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
420 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
421 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b },
422 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 },
423 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
424 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
425 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
426 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
427 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 },
428 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
429 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 },
430 };
431
432 static const struct reg_default rt1320_mbq_defaults[] = {
433 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
434 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
435 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
436 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
437 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
438 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
439 };
440
rt1320_readable_register(struct device * dev,unsigned int reg)441 static bool rt1320_readable_register(struct device *dev, unsigned int reg)
442 {
443 switch (reg) {
444 case 0xc000 ... 0xc086:
445 case 0xc400 ... 0xc409:
446 case 0xc480 ... 0xc48f:
447 case 0xc4c0 ... 0xc4c4:
448 case 0xc4e0 ... 0xc4e7:
449 case 0xc500:
450 case 0xc560 ... 0xc56b:
451 case 0xc570:
452 case 0xc580 ... 0xc59a:
453 case 0xc5b0 ... 0xc60f:
454 case 0xc640 ... 0xc64f:
455 case 0xc670:
456 case 0xc680 ... 0xc683:
457 case 0xc700 ... 0xc76f:
458 case 0xc800 ... 0xc801:
459 case 0xc820:
460 case 0xc900 ... 0xc901:
461 case 0xc920 ... 0xc921:
462 case 0xca00 ... 0xca07:
463 case 0xca20 ... 0xca27:
464 case 0xca40 ... 0xca4b:
465 case 0xca60 ... 0xca68:
466 case 0xca80 ... 0xca88:
467 case 0xcb00 ... 0xcb0c:
468 case 0xcc00 ... 0xcc12:
469 case 0xcc80 ... 0xcc81:
470 case 0xcd00:
471 case 0xcd80 ... 0xcd82:
472 case 0xce00 ... 0xce4d:
473 case 0xcf00 ... 0xcf25:
474 case 0xd000 ... 0xd0ff:
475 case 0xd100 ... 0xd1ff:
476 case 0xd200 ... 0xd2ff:
477 case 0xd300 ... 0xd3ff:
478 case 0xd400 ... 0xd403:
479 case 0xd410 ... 0xd417:
480 case 0xd470 ... 0xd497:
481 case 0xd4dc ... 0xd50f:
482 case 0xd520 ... 0xd543:
483 case 0xd560 ... 0xd5ef:
484 case 0xd600 ... 0xd663:
485 case 0xda00 ... 0xda6e:
486 case 0xda80 ... 0xda9e:
487 case 0xdb00 ... 0xdb7f:
488 case 0xdc00:
489 case 0xdc20 ... 0xdc21:
490 case 0xdd00 ... 0xdd17:
491 case 0xde00 ... 0xde09:
492 case 0xdf00 ... 0xdf1b:
493 case 0xe000 ... 0xe847:
494 case 0xf01e:
495 case 0xf717 ... 0xf719:
496 case 0xf720 ... 0xf723:
497 case 0x1000cd91 ... 0x1000cd96:
498 case RT1321_PATCH_MAIN_VER ... RT1321_PATCH_BETA_VER:
499 case 0x1000f008:
500 case 0x1000f021:
501 case 0x2000300f:
502 case 0x2000301c:
503 case 0x2000900f:
504 case 0x20009018:
505 case 0x3fc000c0 ... 0x3fc2dfc8:
506 case 0x3fe00000 ... 0x3fe36fff:
507 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */
508 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
509 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01):
510 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02):
511 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01):
512 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02):
513 /* 0x40880900/0x40880980 */
514 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
515 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
516 /* 0x40881500 */
517 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
518 /* 0x41000189/0x4100018a */
519 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01):
520 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02):
521 /* 0x41001388 */
522 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
523 /* 0x41001988 */
524 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
525 /* 0x41080000 */
526 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
527 /* 0x41080200 */
528 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0):
529 /* 0x41080900 */
530 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
531 /* 0x41080980 */
532 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
533 /* 0x41081080 */
534 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
535 /* 0x41081480/0x41081488 */
536 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
537 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
538 /* 0x41081980 */
539 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
540 return true;
541 default:
542 return false;
543 }
544 }
545
rt1320_volatile_register(struct device * dev,unsigned int reg)546 static bool rt1320_volatile_register(struct device *dev, unsigned int reg)
547 {
548 switch (reg) {
549 case 0xc000:
550 case 0xc003:
551 case 0xc081:
552 case 0xc402 ... 0xc406:
553 case 0xc48c ... 0xc48f:
554 case 0xc560:
555 case 0xc5b5 ... 0xc5b7:
556 case 0xc5c3:
557 case 0xc5c8:
558 case 0xc5fc ... 0xc5ff:
559 case 0xc680 ... 0xc683:
560 case 0xc820:
561 case 0xc900:
562 case 0xc920:
563 case 0xca42:
564 case 0xca62:
565 case 0xca82:
566 case 0xcd00:
567 case 0xce03:
568 case 0xce10:
569 case 0xce14 ... 0xce17:
570 case 0xce44 ... 0xce49:
571 case 0xce4c ... 0xce4d:
572 case 0xcf0c:
573 case 0xcf10 ... 0xcf25:
574 case 0xd486 ... 0xd487:
575 case 0xd4e5 ... 0xd4e6:
576 case 0xd4e8 ... 0xd4ff:
577 case 0xd530:
578 case 0xd540 ... 0xd541:
579 case 0xd543:
580 case 0xdb58 ... 0xdb5f:
581 case 0xdb60 ... 0xdb63:
582 case 0xdb68 ... 0xdb69:
583 case 0xdb6d:
584 case 0xdb70 ... 0xdb71:
585 case 0xdb76:
586 case 0xdb7a:
587 case 0xdb7c ... 0xdb7f:
588 case 0xdd0c ... 0xdd13:
589 case 0xde02:
590 case 0xdf14 ... 0xdf1b:
591 case 0xe80b:
592 case 0xe83c ... 0xe847:
593 case 0xf01e:
594 case 0xf717 ... 0xf719:
595 case 0xf720 ... 0xf723:
596 case 0x10000000 ... 0x10008fff:
597 case 0x1000c000 ... 0x1000dfff:
598 case 0x1000f008:
599 case 0x1000f021:
600 case 0x2000300f:
601 case 0x2000301c:
602 case 0x2000900f:
603 case 0x20009018:
604 case 0x3fc2ab80 ... 0x3fc2ac4c:
605 case 0x3fc2b780:
606 case 0x3fc2bf80 ... 0x3fc2bf83:
607 case 0x3fc2bfc0 ... 0x3fc2bfc8:
608 case 0x3fc2d300 ... 0x3fc2d354:
609 case 0x3fc2dfc0 ... 0x3fc2dfc8:
610 case 0x3fe2e000 ... 0x3fe2e003:
611 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
612 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
613 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
614 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
615 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
616 return true;
617 default:
618 return false;
619 }
620 }
621
rt1320_mbq_readable_register(struct device * dev,unsigned int reg)622 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg)
623 {
624 switch (reg) {
625 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
626 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
627 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
628 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
629 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
630 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
631 return true;
632 default:
633 return false;
634 }
635 }
636
637 static const struct regmap_config rt1320_sdw_regmap = {
638 .reg_bits = 32,
639 .val_bits = 8,
640 .readable_reg = rt1320_readable_register,
641 .volatile_reg = rt1320_volatile_register,
642 .max_register = 0x41081980,
643 .reg_defaults = rt1320_reg_defaults,
644 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults),
645 .cache_type = REGCACHE_MAPLE,
646 .use_single_read = true,
647 .use_single_write = true,
648 };
649
650 static const struct regmap_config rt1320_mbq_regmap = {
651 .name = "sdw-mbq",
652 .reg_bits = 32,
653 .val_bits = 16,
654 .readable_reg = rt1320_mbq_readable_register,
655 .max_register = 0x41000192,
656 .reg_defaults = rt1320_mbq_defaults,
657 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults),
658 .cache_type = REGCACHE_MAPLE,
659 .use_single_read = true,
660 .use_single_write = true,
661 };
662
rt1320_read_prop(struct sdw_slave * slave)663 static int rt1320_read_prop(struct sdw_slave *slave)
664 {
665 struct sdw_slave_prop *prop = &slave->prop;
666 int nval;
667 int i, j;
668 u32 bit;
669 unsigned long addr;
670 struct sdw_dpn_prop *dpn;
671
672 /*
673 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping
674 */
675 sdw_slave_read_prop(slave);
676
677 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
678 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
679
680 prop->paging_support = true;
681 prop->lane_control_support = true;
682
683 /* first we need to allocate memory for set bits in port lists */
684 prop->source_ports = BIT(4) | BIT(8) | BIT(10);
685 prop->sink_ports = BIT(1);
686
687 nval = hweight32(prop->source_ports);
688 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
689 sizeof(*prop->src_dpn_prop), GFP_KERNEL);
690 if (!prop->src_dpn_prop)
691 return -ENOMEM;
692
693 i = 0;
694 dpn = prop->src_dpn_prop;
695 addr = prop->source_ports;
696 for_each_set_bit(bit, &addr, 32) {
697 dpn[i].num = bit;
698 dpn[i].type = SDW_DPN_FULL;
699 dpn[i].simple_ch_prep_sm = true;
700 dpn[i].ch_prep_timeout = 10;
701 i++;
702 }
703
704 /* do this again for sink now */
705 nval = hweight32(prop->sink_ports);
706 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
707 sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
708 if (!prop->sink_dpn_prop)
709 return -ENOMEM;
710
711 j = 0;
712 dpn = prop->sink_dpn_prop;
713 addr = prop->sink_ports;
714 for_each_set_bit(bit, &addr, 32) {
715 dpn[j].num = bit;
716 dpn[j].type = SDW_DPN_FULL;
717 dpn[j].simple_ch_prep_sm = true;
718 dpn[j].ch_prep_timeout = 10;
719 j++;
720 }
721
722 prop->dp0_prop = devm_kzalloc(&slave->dev, sizeof(*prop->dp0_prop), GFP_KERNEL);
723 if (!prop->dp0_prop)
724 return -ENOMEM;
725
726 prop->dp0_prop->simple_ch_prep_sm = true;
727 prop->dp0_prop->ch_prep_timeout = 10;
728
729 /* set the timeout values */
730 prop->clk_stop_timeout = 64;
731
732 /* BIOS may set wake_capable. Make sure it is 0 as wake events are disabled. */
733 prop->wake_capable = 0;
734
735 return 0;
736 }
737
rt1320_pde_transition_delay(struct rt1320_sdw_priv * rt1320,unsigned char func,unsigned char entity,unsigned char ps)738 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func,
739 unsigned char entity, unsigned char ps)
740 {
741 unsigned int delay = 2000, val;
742
743 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev);
744
745 /* waiting for Actual PDE becomes to PS0/PS3 */
746 while (delay) {
747 regmap_read(rt1320->regmap,
748 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val);
749 if (val == ps)
750 break;
751
752 usleep_range(1000, 1500);
753 delay--;
754 }
755 if (!delay) {
756 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0");
757 return -ETIMEDOUT;
758 }
759
760 return 0;
761 }
762
rt1320_data_rw(struct rt1320_sdw_priv * rt1320,unsigned int start,unsigned char * data,unsigned int size,enum rt1320_rw_type rw)763 static void rt1320_data_rw(struct rt1320_sdw_priv *rt1320, unsigned int start,
764 unsigned char *data, unsigned int size, enum rt1320_rw_type rw)
765 {
766 struct device *dev = &rt1320->sdw_slave->dev;
767 unsigned int tmp;
768 int ret = -1;
769 int i, j;
770
771 pm_runtime_set_autosuspend_delay(dev, 20000);
772 pm_runtime_mark_last_busy(dev);
773
774 switch (rw) {
775 case RT1320_BRA_WRITE:
776 case RT1320_BRA_READ:
777 ret = sdw_bpt_send_sync(rt1320->sdw_slave->bus, rt1320->sdw_slave, &rt1320->bra_msg);
778 if (ret < 0)
779 dev_err(dev, "%s: Failed to send BRA message: %d\n", __func__, ret);
780 fallthrough;
781 case RT1320_PARAM_WRITE:
782 case RT1320_PARAM_READ:
783 if (ret < 0) {
784 /* if BRA fails, we try to access by the control word */
785 if (rw == RT1320_BRA_WRITE || rw == RT1320_BRA_READ) {
786 for (i = 0; i < rt1320->bra_msg.sections; i++) {
787 pm_runtime_mark_last_busy(dev);
788 for (j = 0; j < rt1320->bra_msg.sec[i].len; j++) {
789 if (rw == RT1320_BRA_WRITE) {
790 regmap_write(rt1320->regmap,
791 rt1320->bra_msg.sec[i].addr + j, rt1320->bra_msg.sec[i].buf[j]);
792 } else {
793 regmap_read(rt1320->regmap, rt1320->bra_msg.sec[i].addr + j, &tmp);
794 rt1320->bra_msg.sec[i].buf[j] = tmp;
795 }
796 }
797 }
798 } else {
799 for (i = 0; i < size; i++) {
800 if (rw == RT1320_PARAM_WRITE)
801 regmap_write(rt1320->regmap, start + i, data[i]);
802 else {
803 regmap_read(rt1320->regmap, start + i, &tmp);
804 data[i] = tmp;
805 }
806 }
807 }
808 }
809 break;
810 }
811
812 pm_runtime_set_autosuspend_delay(dev, 3000);
813 pm_runtime_mark_last_busy(dev);
814 }
815
rt1320_rsgain_to_rsratio(struct rt1320_sdw_priv * rt1320,unsigned int rsgain)816 static unsigned long long rt1320_rsgain_to_rsratio(struct rt1320_sdw_priv *rt1320, unsigned int rsgain)
817 {
818 unsigned long long base = 1000000000U;
819 unsigned long long step = 1960784U;
820 unsigned long long tmp, result;
821
822 if (rsgain == 0 || rsgain == 0x1ff)
823 result = 1000000000;
824 else if (rsgain & 0x100) {
825 tmp = 0xff - (rsgain & 0xff);
826 tmp = tmp * step;
827 result = base + tmp;
828 } else {
829 tmp = (rsgain & 0xff);
830 tmp = tmp * step;
831 result = base - tmp;
832 }
833
834 return result;
835 }
836
rt1320_pr_read(struct rt1320_sdw_priv * rt1320,unsigned int reg,unsigned int * val)837 static void rt1320_pr_read(struct rt1320_sdw_priv *rt1320, unsigned int reg, unsigned int *val)
838 {
839 unsigned int byte3, byte2, byte1, byte0;
840
841 regmap_write(rt1320->regmap, 0xc483, 0x80);
842 regmap_write(rt1320->regmap, 0xc482, 0x40);
843 regmap_write(rt1320->regmap, 0xc481, 0x0c);
844 regmap_write(rt1320->regmap, 0xc480, 0x10);
845
846 regmap_write(rt1320->regmap, 0xc487, ((reg & 0xff000000) >> 24));
847 regmap_write(rt1320->regmap, 0xc486, ((reg & 0x00ff0000) >> 16));
848 regmap_write(rt1320->regmap, 0xc485, ((reg & 0x0000ff00) >> 8));
849 regmap_write(rt1320->regmap, 0xc484, (reg & 0x000000ff));
850
851 regmap_write(rt1320->regmap, 0xc482, 0xc0);
852
853 regmap_read(rt1320->regmap, 0xc48f, &byte3);
854 regmap_read(rt1320->regmap, 0xc48e, &byte2);
855 regmap_read(rt1320->regmap, 0xc48d, &byte1);
856 regmap_read(rt1320->regmap, 0xc48c, &byte0);
857
858 *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
859 }
860
rt1320_check_fw_ready(struct rt1320_sdw_priv * rt1320)861 static int rt1320_check_fw_ready(struct rt1320_sdw_priv *rt1320)
862 {
863 struct device *dev = &rt1320->sdw_slave->dev;
864 unsigned int tmp, retry = 0;
865 unsigned int cmd_addr;
866
867 switch (rt1320->dev_id) {
868 case RT1320_DEV_ID:
869 cmd_addr = RT1320_CMD_ID;
870 break;
871 case RT1321_DEV_ID:
872 cmd_addr = RT1321_CMD_ID;
873 break;
874 default:
875 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
876 return -EINVAL;
877 }
878
879 pm_runtime_mark_last_busy(dev);
880 /* check the value of cmd_addr becomes to zero */
881 while (retry < 500) {
882 regmap_read(rt1320->regmap, cmd_addr, &tmp);
883 if (tmp == 0)
884 break;
885 usleep_range(1000, 1100);
886 retry++;
887 }
888 if (retry == 500) {
889 dev_warn(dev, "%s FW is NOT ready!", __func__);
890 return -ETIMEDOUT;
891 }
892
893 return 0;
894 }
895
rt1320_check_power_state_ready(struct rt1320_sdw_priv * rt1320,enum rt1320_power_state ps)896 static int rt1320_check_power_state_ready(struct rt1320_sdw_priv *rt1320, enum rt1320_power_state ps)
897 {
898 struct device *dev = &rt1320->sdw_slave->dev;
899 unsigned int retry = 0, tmp;
900
901 pm_runtime_mark_last_busy(dev);
902 while (retry < 200) {
903 regmap_read(rt1320->regmap, RT1320_POWER_STATE, &tmp);
904 dev_dbg(dev, "%s, RT1320_POWER_STATE=0x%x\n", __func__, tmp);
905 if (tmp >= ps)
906 break;
907 usleep_range(1000, 1500);
908 retry++;
909 }
910 if (retry == 200) {
911 dev_warn(dev, "%s FW Power State is NOT ready!", __func__);
912 return -ETIMEDOUT;
913 }
914
915 return 0;
916 }
917
rt1320_process_fw_param(struct rt1320_sdw_priv * rt1320,unsigned char * buf,unsigned int buf_size)918 static int rt1320_process_fw_param(struct rt1320_sdw_priv *rt1320, unsigned char *buf, unsigned int buf_size)
919 {
920 struct device *dev = &rt1320->sdw_slave->dev;
921 struct rt1320_paramcmd *paramhr = (struct rt1320_paramcmd *)buf;
922 unsigned char moudleid = paramhr->moudleid;
923 unsigned char cmdtype = paramhr->commandtype;
924 unsigned int fw_param_addr;
925 unsigned int start_addr;
926 int ret = 0;
927
928 switch (rt1320->dev_id) {
929 case RT1320_DEV_ID:
930 fw_param_addr = RT1320_FW_PARAM_ADDR;
931 start_addr = RT1320_CMD_PARAM_ADDR;
932 break;
933 case RT1321_DEV_ID:
934 fw_param_addr = RT1321_FW_PARAM_ADDR;
935 start_addr = RT1321_CMD_PARAM_ADDR;
936 break;
937 default:
938 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
939 return -EINVAL;
940 }
941
942 ret = rt1320_check_fw_ready(rt1320);
943 if (ret < 0)
944 goto _timeout_;
945
946 /* don't set offset 0x0/0x1, it will be set later*/
947 paramhr->moudleid = 0;
948 paramhr->commandtype = 0;
949 rt1320_data_rw(rt1320, fw_param_addr, buf, buf_size, RT1320_PARAM_WRITE);
950
951 dev_dbg(dev, "%s, moudleid=%d, cmdtype=%d, paramid=%d, paramlength=%d\n", __func__,
952 moudleid, cmdtype, paramhr->paramid, paramhr->paramlength);
953
954 if (cmdtype == RT1320_SET_PARAM) {
955 regmap_write(rt1320->regmap, fw_param_addr, moudleid);
956 regmap_write(rt1320->regmap, fw_param_addr + 1, 0x01);
957 }
958 if (cmdtype == RT1320_GET_PARAM) {
959 regmap_write(rt1320->regmap, fw_param_addr, moudleid);
960 regmap_write(rt1320->regmap, fw_param_addr + 1, 0x02);
961 ret = rt1320_check_fw_ready(rt1320);
962 if (ret < 0)
963 goto _timeout_;
964
965 rt1320_data_rw(rt1320, start_addr, buf + 0x10, paramhr->commandlength, RT1320_PARAM_READ);
966 }
967 return 0;
968
969 _timeout_:
970 dev_err(&rt1320->sdw_slave->dev, "%s: FW is NOT ready for SET/GET_PARAM\n", __func__);
971 return ret;
972 }
973
rt1320_fw_param_protocol(struct rt1320_sdw_priv * rt1320,enum rt1320_fw_cmdid cmdid,unsigned int paramid,void * parambuf,unsigned int paramsize)974 static int rt1320_fw_param_protocol(struct rt1320_sdw_priv *rt1320, enum rt1320_fw_cmdid cmdid,
975 unsigned int paramid, void *parambuf, unsigned int paramsize)
976 {
977 struct device *dev = &rt1320->sdw_slave->dev;
978 unsigned char *tempbuf = NULL;
979 struct rt1320_paramcmd paramhr;
980 int ret = 0;
981
982 tempbuf = kzalloc(sizeof(paramhr) + paramsize, GFP_KERNEL);
983 if (!tempbuf)
984 return -ENOMEM;
985
986 paramhr.moudleid = 1;
987 paramhr.commandtype = cmdid;
988 /* 8 is "sizeof(paramid) + sizeof(paramlength)" */
989 paramhr.commandlength = 8 + paramsize;
990 paramhr.paramid = paramid;
991 paramhr.paramlength = paramsize;
992
993 memcpy(tempbuf, ¶mhr, sizeof(paramhr));
994 if (cmdid == RT1320_SET_PARAM)
995 memcpy(tempbuf + sizeof(paramhr), parambuf, paramsize);
996
997 ret = rt1320_process_fw_param(rt1320, tempbuf, sizeof(paramhr) + paramsize);
998 if (ret < 0) {
999 dev_err(dev, "%s: process_fw_param failed\n", __func__);
1000 goto _finish_;
1001 }
1002
1003 if (cmdid == RT1320_GET_PARAM)
1004 memcpy(parambuf, tempbuf + sizeof(paramhr), paramsize);
1005
1006 _finish_:
1007 kfree(tempbuf);
1008 return ret;
1009 }
1010
rt1320_set_advancemode(struct rt1320_sdw_priv * rt1320)1011 static void rt1320_set_advancemode(struct rt1320_sdw_priv *rt1320)
1012 {
1013 struct device *dev = &rt1320->sdw_slave->dev;
1014 struct rt1320_datafixpoint r0_data[2];
1015 unsigned short l_advancegain, r_advancegain;
1016 int ret;
1017
1018 /* Get advance gain/r0 */
1019 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint));
1020 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint));
1021 l_advancegain = r0_data[0].advancegain;
1022 r_advancegain = r0_data[1].advancegain;
1023 dev_dbg(dev, "%s, LR advanceGain=0x%x 0x%x\n", __func__, l_advancegain, r_advancegain);
1024
1025 /* set R0 and enable protection by SetParameter id 6, 7 */
1026 r0_data[0].silencedetect = 0;
1027 r0_data[0].r0 = rt1320->r0_l_reg;
1028 r0_data[1].silencedetect = 0;
1029 r0_data[1].r0 = rt1320->r0_r_reg;
1030 dev_dbg(dev, "%s, write LR r0=%d, %d\n", __func__, r0_data[0].r0, r0_data[1].r0);
1031
1032 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint));
1033 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint));
1034 ret = rt1320_check_fw_ready(rt1320);
1035 if (ret < 0)
1036 dev_err(dev, "%s: Failed to set FW param 6,7!\n", __func__);
1037
1038 if (l_advancegain != 0 && r_advancegain != 0) {
1039 regmap_write(rt1320->regmap, 0xdd0b, (l_advancegain & 0xff00) >> 8);
1040 regmap_write(rt1320->regmap, 0xdd0a, (l_advancegain & 0xff));
1041 regmap_write(rt1320->regmap, 0xdd09, (r_advancegain & 0xff00) >> 8);
1042 regmap_write(rt1320->regmap, 0xdd08, (r_advancegain & 0xff));
1043 dev_dbg(dev, "%s, set Advance mode gain\n", __func__);
1044 }
1045 }
1046
rt1320_invrs_load(struct rt1320_sdw_priv * rt1320)1047 static int rt1320_invrs_load(struct rt1320_sdw_priv *rt1320)
1048 {
1049 struct device *dev = &rt1320->sdw_slave->dev;
1050 unsigned long long l_rsratio, r_rsratio;
1051 unsigned int pr_1058, pr_1059, pr_105a;
1052 unsigned long long l_invrs, r_invrs;
1053 unsigned long long factor = (1 << 28);
1054 unsigned int l_rsgain, r_rsgain;
1055 struct rt1320_datafixpoint r0_data[2];
1056 int ret;
1057
1058 /* read L/Rch Rs Gain - it uses for compensating the R0 value */
1059 rt1320_pr_read(rt1320, 0x1058, &pr_1058);
1060 rt1320_pr_read(rt1320, 0x1059, &pr_1059);
1061 rt1320_pr_read(rt1320, 0x105a, &pr_105a);
1062 l_rsgain = ((pr_1059 & 0x7f) << 2) | ((pr_105a & 0xc0) >> 6);
1063 r_rsgain = ((pr_1058 & 0xff) << 1) | ((pr_1059 & 0x80) >> 7);
1064 dev_dbg(dev, "%s, LR rsgain=0x%x, 0x%x\n", __func__, l_rsgain, r_rsgain);
1065
1066 l_rsratio = rt1320_rsgain_to_rsratio(rt1320, l_rsgain);
1067 r_rsratio = rt1320_rsgain_to_rsratio(rt1320, r_rsgain);
1068 dev_dbg(dev, "%s, LR rsratio=%lld, %lld\n", __func__, l_rsratio, r_rsratio);
1069
1070 l_invrs = div_u64(l_rsratio * factor, 1000000000U);
1071 r_invrs = div_u64(r_rsratio * factor, 1000000000U);
1072
1073 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint));
1074 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint));
1075
1076 r0_data[0].invrs = l_invrs;
1077 r0_data[1].invrs = r_invrs;
1078 dev_dbg(dev, "%s, write DSP LR invrs=0x%x, 0x%x\n", __func__, r0_data[0].invrs, r0_data[1].invrs);
1079
1080 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint));
1081 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint));
1082 ret = rt1320_check_fw_ready(rt1320);
1083 if (ret < 0)
1084 dev_err(dev, "%s: Failed to set FW param 6,7!\n", __func__);
1085
1086 return ret;
1087 }
1088
rt1320_calc_r0(struct rt1320_sdw_priv * rt1320)1089 static void rt1320_calc_r0(struct rt1320_sdw_priv *rt1320)
1090 {
1091 struct device *dev = &rt1320->sdw_slave->dev;
1092 unsigned long long l_calir0, r_calir0, l_calir0_lo, r_calir0_lo;
1093
1094 l_calir0 = rt1320->r0_l_reg >> 27;
1095 r_calir0 = rt1320->r0_r_reg >> 27;
1096 l_calir0_lo = ((rt1320->r0_l_reg & ((1ull << 27) - 1)) * 1000) >> 27;
1097 r_calir0_lo = ((rt1320->r0_r_reg & ((1ull << 27) - 1)) * 1000) >> 27;
1098
1099 dev_dbg(dev, "%s, l_calir0=%lld.%03lld ohm, r_calir0=%lld.%03lld ohm\n", __func__,
1100 l_calir0, l_calir0_lo, r_calir0, r_calir0_lo);
1101 }
1102
rt1320_calibrate(struct rt1320_sdw_priv * rt1320)1103 static void rt1320_calibrate(struct rt1320_sdw_priv *rt1320)
1104 {
1105 struct device *dev = &rt1320->sdw_slave->dev;
1106 struct rt1320_datafixpoint audfixpoint[2];
1107 unsigned int reg_c5fb, reg_c570, reg_cd00;
1108 unsigned int vol_reg[4], fw_ready;
1109 unsigned long long l_meanr0, r_meanr0;
1110 unsigned int fw_status_addr;
1111 int l_re[5], r_re[5];
1112 int ret, tmp;
1113 unsigned long long factor = (1 << 27);
1114 unsigned short l_advancegain, r_advancegain;
1115 unsigned int delay_s = 7; /* delay seconds for the calibration */
1116
1117 if (!rt1320->component)
1118 return;
1119
1120 switch (rt1320->dev_id) {
1121 case RT1320_DEV_ID:
1122 fw_status_addr = RT1320_DSPFW_STATUS_ADDR;
1123 break;
1124 case RT1321_DEV_ID:
1125 fw_status_addr = RT1321_DSPFW_STATUS_ADDR;
1126 break;
1127 default:
1128 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1129 return;
1130 }
1131
1132 /* set volume 0dB */
1133 regmap_read(rt1320->regmap, 0xdd0b, &vol_reg[3]);
1134 regmap_read(rt1320->regmap, 0xdd0a, &vol_reg[2]);
1135 regmap_read(rt1320->regmap, 0xdd09, &vol_reg[1]);
1136 regmap_read(rt1320->regmap, 0xdd08, &vol_reg[0]);
1137 regmap_write(rt1320->regmap, 0xdd0b, 0x0f);
1138 regmap_write(rt1320->regmap, 0xdd0a, 0xff);
1139 regmap_write(rt1320->regmap, 0xdd09, 0x0f);
1140 regmap_write(rt1320->regmap, 0xdd08, 0xff);
1141
1142 regmap_read(rt1320->regmap, 0xc5fb, ®_c5fb);
1143 regmap_read(rt1320->regmap, 0xc570, ®_c570);
1144 regmap_read(rt1320->regmap, 0xcd00, ®_cd00);
1145
1146 regmap_write(rt1320->regmap,
1147 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
1148 ret = rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
1149 if (ret < 0) {
1150 dev_dbg(dev, "%s, PDE=PS0 is NOT ready\n", __func__);
1151 goto _finish_;
1152 }
1153
1154 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready);
1155 fw_ready &= 0x1;
1156 if (!fw_ready) {
1157 dev_dbg(dev, "%s, DSP FW is NOT ready. Please load DSP FW first\n", __func__);
1158 goto _finish_;
1159 }
1160
1161 ret = rt1320_check_power_state_ready(rt1320, RT1320_NORMAL_STATE);
1162 if (ret < 0) {
1163 dev_dbg(dev, "%s, DSP FW PS is NOT ready\n", __func__);
1164 goto _finish_;
1165 }
1166
1167 if (rt1320->dev_id == RT1320_DEV_ID)
1168 regmap_write(rt1320->regmap, 0xc5fb, 0x00);
1169 regmap_write(rt1320->regmap, 0xc570, 0x0b);
1170 regmap_write(rt1320->regmap, 0xcd00, 0xc5);
1171
1172 /* disable silence detection */
1173 regmap_update_bits(rt1320->regmap, 0xc044, 0xe0, 0x00);
1174 dev_dbg(dev, "%s, disable silence detection\n", __func__);
1175
1176 ret = rt1320_check_power_state_ready(rt1320, RT1320_K_R0_STATE);
1177 if (ret < 0) {
1178 dev_dbg(dev, "%s, check class D status before k r0\n", __func__);
1179 goto _finish_;
1180 }
1181
1182 for (tmp = 0; tmp < delay_s; tmp++) {
1183 msleep(1000);
1184 pm_runtime_mark_last_busy(dev);
1185
1186 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 11, &l_re[0], sizeof(l_re));
1187 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 12, &r_re[0], sizeof(r_re));
1188
1189 dev_dbg(dev, "%s, LR re=0x%x, 0x%x\n", __func__, l_re[4], r_re[4]);
1190 dev_dbg(dev, "%s, waiting for calibration R0...%d seconds\n", __func__, tmp + 1);
1191 }
1192
1193 /* Get Calibration data */
1194 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 11, &l_re[0], sizeof(l_re));
1195 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 12, &r_re[0], sizeof(r_re));
1196 dev_dbg(dev, "%s, LR re=0x%x, 0x%x\n", __func__, l_re[4], r_re[4]);
1197
1198 /* Get advance gain/mean r0 */
1199 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &audfixpoint[0], sizeof(struct rt1320_datafixpoint));
1200 l_meanr0 = audfixpoint[0].meanr0;
1201 l_advancegain = audfixpoint[0].advancegain;
1202 l_meanr0 = ((l_meanr0 * 1000U) / factor);
1203 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &audfixpoint[1], sizeof(struct rt1320_datafixpoint));
1204 r_meanr0 = audfixpoint[1].meanr0;
1205 r_advancegain = audfixpoint[1].advancegain;
1206 r_meanr0 = ((r_meanr0 * 1000U) / factor);
1207 dev_dbg(dev, "%s, LR meanr0=%lld, %lld\n", __func__, l_meanr0, r_meanr0);
1208 dev_dbg(dev, "%s, LR advanceGain=0x%x, 0x%x\n", __func__, l_advancegain, r_advancegain);
1209 dev_dbg(dev, "%s, LR invrs=0x%x, 0x%x\n", __func__, audfixpoint[0].invrs, audfixpoint[1].invrs);
1210
1211 /* enable silence detection */
1212 regmap_update_bits(rt1320->regmap, 0xc044, 0xe0, 0xe0);
1213 dev_dbg(dev, "%s, enable silence detection\n", __func__);
1214
1215 regmap_write(rt1320->regmap, 0xc5fb, reg_c5fb);
1216 regmap_write(rt1320->regmap, 0xc570, reg_c570);
1217 regmap_write(rt1320->regmap, 0xcd00, reg_cd00);
1218
1219 rt1320->r0_l_reg = l_re[4];
1220 rt1320->r0_r_reg = r_re[4];
1221 rt1320->cali_done = true;
1222 rt1320_calc_r0(rt1320);
1223
1224 _finish_:
1225 regmap_write(rt1320->regmap,
1226 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
1227 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
1228
1229 /* advance gain will be set when R0 load, not here */
1230 regmap_write(rt1320->regmap, 0xdd0b, vol_reg[3]);
1231 regmap_write(rt1320->regmap, 0xdd0a, vol_reg[2]);
1232 regmap_write(rt1320->regmap, 0xdd09, vol_reg[1]);
1233 regmap_write(rt1320->regmap, 0xdd08, vol_reg[0]);
1234 }
1235
rt1320_r0_cali_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1236 static int rt1320_r0_cali_get(struct snd_kcontrol *kcontrol,
1237 struct snd_ctl_elem_value *ucontrol)
1238 {
1239 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1240 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1241
1242 ucontrol->value.integer.value[0] = rt1320->cali_done;
1243 return 0;
1244 }
1245
rt1320_r0_cali_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1246 static int rt1320_r0_cali_put(struct snd_kcontrol *kcontrol,
1247 struct snd_ctl_elem_value *ucontrol)
1248 {
1249 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1250 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1251 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component);
1252 int ret;
1253
1254 if (!rt1320->hw_init)
1255 return 0;
1256
1257 ret = pm_runtime_resume(component->dev);
1258 if (ret < 0 && ret != -EACCES)
1259 return ret;
1260
1261 rt1320->cali_done = false;
1262 snd_soc_dapm_mutex_lock(dapm);
1263 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF &&
1264 ucontrol->value.integer.value[0]) {
1265 rt1320_calibrate(rt1320);
1266 }
1267 snd_soc_dapm_mutex_unlock(dapm);
1268
1269 return 0;
1270 }
1271
1272 /*
1273 * The 'patch code' is written to the patch code area.
1274 * The patch code area is used for SDCA register expansion flexibility.
1275 */
rt1320_load_mcu_patch(struct rt1320_sdw_priv * rt1320)1276 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320)
1277 {
1278 struct sdw_slave *slave = rt1320->sdw_slave;
1279 const struct firmware *patch;
1280 const char *filename;
1281 unsigned int addr, val, min_addr, max_addr;
1282 const unsigned char *ptr;
1283 int ret, i;
1284
1285 switch (rt1320->dev_id) {
1286 case RT1320_DEV_ID:
1287 if (rt1320->version_id <= RT1320_VB)
1288 filename = RT1320_VAB_MCU_PATCH;
1289 else
1290 filename = RT1320_VC_MCU_PATCH;
1291 min_addr = 0x10007000;
1292 max_addr = 0x10007fff;
1293 break;
1294 case RT1321_DEV_ID:
1295 filename = RT1321_VA_MCU_PATCH;
1296 min_addr = 0x10008000;
1297 max_addr = 0x10008fff;
1298 break;
1299 default:
1300 dev_err(&slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1301 return;
1302 }
1303
1304 /* load the patch code here */
1305 ret = request_firmware(&patch, filename, &slave->dev);
1306 if (ret) {
1307 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename);
1308 regmap_write(rt1320->regmap, 0xc598, 0x00);
1309 regmap_write(rt1320->regmap, min_addr, 0x67);
1310 regmap_write(rt1320->regmap, min_addr + 0x1, 0x80);
1311 regmap_write(rt1320->regmap, min_addr + 0x2, 0x00);
1312 regmap_write(rt1320->regmap, min_addr + 0x3, 0x00);
1313 if (rt1320->dev_id == RT1321_DEV_ID) {
1314 regmap_write(rt1320->regmap, 0xd73c, 0x67);
1315 regmap_write(rt1320->regmap, 0xd73d, 0x80);
1316 regmap_write(rt1320->regmap, 0xd73e, 0x00);
1317 regmap_write(rt1320->regmap, 0xd73f, 0x00);
1318 }
1319 } else {
1320 ptr = (const unsigned char *)patch->data;
1321 if ((patch->size % 8) == 0) {
1322 for (i = 0; i < patch->size; i += 8) {
1323 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 |
1324 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24;
1325 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 |
1326 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24;
1327
1328 if (addr > max_addr || addr < min_addr) {
1329 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr);
1330 goto _exit_;
1331 }
1332 if (val > 0xff) {
1333 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val);
1334 goto _exit_;
1335 }
1336 regmap_write(rt1320->regmap, addr, val);
1337 }
1338 }
1339 _exit_:
1340 release_firmware(patch);
1341 }
1342 }
1343
rt1320_vab_preset(struct rt1320_sdw_priv * rt1320)1344 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320)
1345 {
1346 unsigned int i, reg, val, delay;
1347
1348 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) {
1349 reg = rt1320_blind_write[i].reg;
1350 val = rt1320_blind_write[i].def;
1351 delay = rt1320_blind_write[i].delay_us;
1352
1353 if (reg == 0x3fc2bfc7)
1354 rt1320_load_mcu_patch(rt1320);
1355
1356 regmap_write(rt1320->regmap, reg, val);
1357 if (delay)
1358 usleep_range(delay, delay + 1000);
1359 }
1360 }
1361
rt1320_t0_load(struct rt1320_sdw_priv * rt1320,unsigned int l_t0,unsigned int r_t0)1362 static void rt1320_t0_load(struct rt1320_sdw_priv *rt1320, unsigned int l_t0, unsigned int r_t0)
1363 {
1364 struct device *dev = &rt1320->sdw_slave->dev;
1365 unsigned int factor = (1 << 22), fw_ready;
1366 int l_t0_data[38], r_t0_data[38];
1367 unsigned int fw_status_addr;
1368
1369 switch (rt1320->dev_id) {
1370 case RT1320_DEV_ID:
1371 fw_status_addr = RT1320_DSPFW_STATUS_ADDR;
1372 break;
1373 case RT1321_DEV_ID:
1374 fw_status_addr = RT1321_DSPFW_STATUS_ADDR;
1375 break;
1376 default:
1377 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1378 return;
1379 }
1380
1381 regmap_write(rt1320->regmap,
1382 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1383 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
1384 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
1385
1386 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready);
1387 fw_ready &= 0x1;
1388 if (!fw_ready) {
1389 dev_warn(dev, "%s, DSP FW is NOT ready\n", __func__);
1390 goto _exit_;
1391 }
1392
1393 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data));
1394 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data));
1395
1396 l_t0_data[37] = l_t0 * factor;
1397 r_t0_data[37] = r_t0 * factor;
1398
1399 dev_dbg(dev, "%s, write LR t0=0x%x, 0x%x\n", __func__, l_t0_data[37], r_t0_data[37]);
1400
1401 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data));
1402 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data));
1403 if (rt1320_check_fw_ready(rt1320) < 0)
1404 dev_err(dev, "%s: Failed to set FW param 3,4!\n", __func__);
1405
1406 rt1320->temp_l_calib = l_t0;
1407 rt1320->temp_r_calib = r_t0;
1408
1409 memset(&l_t0_data[0], 0x00, sizeof(l_t0_data));
1410 memset(&r_t0_data[0], 0x00, sizeof(r_t0_data));
1411 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data));
1412 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data));
1413 dev_dbg(dev, "%s, read after writing LR t0=0x%x, 0x%x\n", __func__, l_t0_data[37], r_t0_data[37]);
1414
1415 _exit_:
1416 regmap_write(rt1320->regmap,
1417 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1418 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
1419 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
1420 }
1421
rt1320_rae_load(struct rt1320_sdw_priv * rt1320)1422 static int rt1320_rae_load(struct rt1320_sdw_priv *rt1320)
1423 {
1424 struct device *dev = &rt1320->sdw_slave->dev;
1425 static const char func_tag[] = "FUNC";
1426 static const char xu_tag[] = "XU";
1427 const struct firmware *rae_fw = NULL;
1428 unsigned int fw_offset;
1429 unsigned char *fw_data;
1430 unsigned char *param_data;
1431 unsigned int addr, size;
1432 unsigned int func, value;
1433 const char *dmi_vendor, *dmi_product, *dmi_sku;
1434 int len_vendor, len_product, len_sku;
1435 char rae_filename[512];
1436 char tag[5];
1437 int ret = 0;
1438 int retry = 200;
1439
1440 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1441 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME);
1442 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU);
1443
1444 if (dmi_vendor && dmi_product && dmi_sku) {
1445 len_vendor = strchrnul(dmi_vendor, ' ') - dmi_vendor;
1446 len_product = strchrnul(dmi_product, ' ') - dmi_product;
1447 len_sku = strchrnul(dmi_sku, ' ') - dmi_sku;
1448
1449 snprintf(rae_filename, sizeof(rae_filename),
1450 "realtek/rt1320/rt1320_RAE_%.*s_%.*s_%.*s.dat",
1451 len_vendor, dmi_vendor, len_product, dmi_product, len_sku, dmi_sku);
1452 dev_dbg(dev, "%s: try to load RAE file %s\n", __func__, rae_filename);
1453 } else {
1454 dev_warn(dev, "%s: Can't find proper RAE file name\n", __func__);
1455 return -EINVAL;
1456 }
1457
1458 regmap_write(rt1320->regmap,
1459 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1460 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
1461 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
1462
1463 request_firmware(&rae_fw, rae_filename, dev);
1464 if (rae_fw) {
1465
1466 /* RAE CRC clear */
1467 regmap_write(rt1320->regmap, 0xe80b, 0x0f);
1468
1469 /* RAE stop & CRC disable */
1470 regmap_update_bits(rt1320->regmap, 0xe803, 0xbc, 0x00);
1471
1472 while (--retry) {
1473 regmap_read(rt1320->regmap, 0xe83f, &value);
1474 if (value & 0x40)
1475 break;
1476 usleep_range(1000, 1100);
1477 }
1478 if (!retry && !(value & 0x40)) {
1479 dev_err(dev, "%s: RAE is not ready to load\n", __func__);
1480 return -ETIMEDOUT;
1481 }
1482
1483 dev_dbg(dev, "%s, rae_fw size=0x%zx\n", __func__, rae_fw->size);
1484 regcache_cache_bypass(rt1320->regmap, true);
1485 for (fw_offset = 0; fw_offset < rae_fw->size;) {
1486
1487 dev_dbg(dev, "%s, fw_offset=0x%x\n", __func__, fw_offset);
1488
1489 fw_data = (unsigned char *)&rae_fw->data[fw_offset];
1490
1491 memcpy(tag, fw_data, 4);
1492 tag[4] = '\0';
1493 dev_dbg(dev, "%s, tag=%s\n", __func__, tag);
1494 if (strcmp(tag, xu_tag) == 0) {
1495 dev_dbg(dev, "%s: This is a XU tag", __func__);
1496 memcpy(&addr, (fw_data + 4), 4);
1497 memcpy(&size, (fw_data + 8), 4);
1498 param_data = (unsigned char *)(fw_data + 12);
1499
1500 dev_dbg(dev, "%s: addr=0x%x, size=0x%x\n", __func__, addr, size);
1501
1502 /*
1503 * UI register ranges from 0x1000d000 to 0x1000d7ff
1504 * UI registers should be accessed by tuning tool.
1505 * So, there registers should be cached.
1506 */
1507 if (addr <= 0x1000d7ff && addr >= 0x1000d000)
1508 regcache_cache_bypass(rt1320->regmap, false);
1509
1510 rt1320_data_rw(rt1320, addr, param_data, size, RT1320_PARAM_WRITE);
1511
1512 regcache_cache_bypass(rt1320->regmap, true);
1513
1514 fw_offset += (size + 12);
1515 } else if (strcmp(tag, func_tag) == 0) {
1516 dev_err(dev, "%s: This is a FUNC tag", __func__);
1517
1518 memcpy(&func, (fw_data + 4), 4);
1519 memcpy(&value, (fw_data + 8), 4);
1520
1521 dev_dbg(dev, "%s: func=0x%x, value=0x%x\n", __func__, func, value);
1522 if (func == 1) //DelayMs
1523 msleep(value);
1524
1525 fw_offset += 12;
1526 } else {
1527 dev_err(dev, "%s: This is NOT a XU file (wrong tag)", __func__);
1528 break;
1529 }
1530 }
1531
1532 regcache_cache_bypass(rt1320->regmap, false);
1533 release_firmware(rae_fw);
1534
1535 } else {
1536 dev_err(dev, "%s: Failed to load %s firmware\n", __func__, rae_filename);
1537 ret = -EINVAL;
1538 goto _exit_;
1539 }
1540
1541 /* RAE CRC enable */
1542 regmap_update_bits(rt1320->regmap, 0xe803, 0x0c, 0x0c);
1543
1544 /* RAE update */
1545 regmap_update_bits(rt1320->regmap, 0xe80b, 0x80, 0x00);
1546 regmap_update_bits(rt1320->regmap, 0xe80b, 0x80, 0x80);
1547
1548 /* RAE run */
1549 regmap_update_bits(rt1320->regmap, 0xe803, 0x80, 0x80);
1550
1551 regmap_read(rt1320->regmap, 0xe80b, &value);
1552 dev_dbg(dev, "%s: CAE run => 0xe80b reg = 0x%x\n", __func__, value);
1553
1554 rt1320->rae_update_done = true;
1555
1556 _exit_:
1557 regmap_write(rt1320->regmap,
1558 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1559 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
1560 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
1561
1562 return ret;
1563 }
1564
rt1320_dspfw_load_code(struct rt1320_sdw_priv * rt1320)1565 static void rt1320_dspfw_load_code(struct rt1320_sdw_priv *rt1320)
1566 {
1567 struct rt1320_imageinfo {
1568 unsigned int addr;
1569 unsigned int size;
1570 };
1571
1572 struct rt1320_dspfwheader {
1573 unsigned int sync;
1574 short num;
1575 short crc;
1576 };
1577
1578 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component);
1579 struct device *dev = &rt1320->sdw_slave->dev;
1580 unsigned int val, i, fw_offset, fw_ready;
1581 unsigned int fw_status_addr;
1582 struct rt1320_dspfwheader *fwheader;
1583 struct rt1320_imageinfo *ptr_img;
1584 struct sdw_bpt_section sec[10];
1585 const struct firmware *fw = NULL;
1586 unsigned char *fw_data;
1587 bool dev_fw_match = false;
1588 static const char hdr_sig[] = "AFX";
1589 unsigned int hdr_size = 0;
1590 const char *dmi_vendor, *dmi_product, *dmi_sku;
1591 int len_vendor, len_product, len_sku;
1592 char filename[512];
1593
1594 switch (rt1320->dev_id) {
1595 case RT1320_DEV_ID:
1596 fw_status_addr = RT1320_DSPFW_STATUS_ADDR;
1597 break;
1598 case RT1321_DEV_ID:
1599 fw_status_addr = RT1321_DSPFW_STATUS_ADDR;
1600 break;
1601 default:
1602 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1603 return;
1604 }
1605
1606 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1607 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME);
1608 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU);
1609
1610 if (dmi_vendor && dmi_product && dmi_sku) {
1611 len_vendor = strchrnul(dmi_vendor, ' ') - dmi_vendor;
1612 len_product = strchrnul(dmi_product, ' ') - dmi_product;
1613 len_sku = strchrnul(dmi_sku, ' ') - dmi_sku;
1614
1615 snprintf(filename, sizeof(filename),
1616 "realtek/rt1320/rt1320_%.*s_%.*s_%.*s.dat",
1617 len_vendor, dmi_vendor, len_product, dmi_product, len_sku, dmi_sku);
1618
1619 dev_dbg(dev, "%s: try to load FW file %s\n", __func__, filename);
1620 } else if (rt1320->dspfw_name) {
1621 snprintf(filename, sizeof(filename), "rt1320_%s.dat",
1622 rt1320->dspfw_name);
1623 dev_dbg(dev, "%s: try to load FW file %s\n", __func__, filename);
1624 } else {
1625 dev_warn(dev, "%s: Can't find proper FW file name\n", __func__);
1626 return;
1627 }
1628
1629 snd_soc_dapm_mutex_lock(dapm);
1630 regmap_write(rt1320->regmap,
1631 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1632 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
1633 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
1634
1635 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready);
1636 fw_ready &= 0x1;
1637 if (fw_ready) {
1638 dev_dbg(dev, "%s, DSP FW was already\n", __func__);
1639 rt1320->fw_load_done = true;
1640 goto _exit_;
1641 }
1642
1643 /* change to IRAM */
1644 regmap_update_bits(rt1320->regmap, 0xf01e, 0x80, 0x00);
1645
1646 request_firmware(&fw, filename, dev);
1647 if (fw) {
1648 fwheader = (struct rt1320_dspfwheader *)fw->data;
1649 dev_dbg(dev, "%s, fw sync = 0x%x, num=%d, crc=0x%x\n", __func__,
1650 fwheader->sync, fwheader->num, fwheader->crc);
1651
1652 if (fwheader->sync != 0x0a1c5679) {
1653 dev_err(dev, "%s: FW sync error\n", __func__);
1654 release_firmware(fw);
1655 goto _exit_;
1656 }
1657
1658 fw_offset = sizeof(struct rt1320_dspfwheader) + (sizeof(struct rt1320_imageinfo) * fwheader->num);
1659 dev_dbg(dev, "%s, fw_offset = 0x%x\n", __func__, fw_offset);
1660
1661 regcache_cache_bypass(rt1320->regmap, true);
1662
1663 for (i = 0; i < fwheader->num; i++) {
1664 ptr_img = (struct rt1320_imageinfo *)&fw->data[sizeof(struct rt1320_dspfwheader) + (sizeof(struct rt1320_imageinfo) * i)];
1665
1666 dev_dbg(dev, "%s, fw_offset=0x%x, load fw addr=0x%x, size=%d\n", __func__,
1667 fw_offset, ptr_img->addr, ptr_img->size);
1668
1669 fw_data = (unsigned char *)&fw->data[fw_offset];
1670
1671 /* The binary file has a header of 64 bytes */
1672 if (memcmp(fw_data, hdr_sig, sizeof(hdr_sig)) == 0)
1673 hdr_size = 64;
1674 else
1675 hdr_size = 0;
1676
1677 sec[i].addr = ptr_img->addr;
1678 sec[i].len = ptr_img->size - hdr_size;
1679 sec[i].buf = fw_data + hdr_size;
1680
1681 dev_dbg(dev, "%s, hdr_size=%d, sec[%d].buf[0]=0x%x\n",
1682 __func__, hdr_size, i, sec[i].buf[0]);
1683
1684 switch (rt1320->dev_id) {
1685 case RT1320_DEV_ID:
1686 if (ptr_img->addr == 0x3fc29d80)
1687 if (fw_data[9] == '0')
1688 dev_fw_match = true;
1689 break;
1690 case RT1321_DEV_ID:
1691 if (ptr_img->addr == 0x3fc00000)
1692 if (fw_data[9] == '1')
1693 dev_fw_match = true;
1694 break;
1695 default:
1696 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1697 goto _exit_;
1698 }
1699
1700 fw_offset += ptr_img->size;
1701 }
1702
1703 if (dev_fw_match) {
1704 dev_dbg(dev, "%s, starting BRA downloading FW..\n", __func__);
1705 rt1320->bra_msg.dev_num = rt1320->sdw_slave->dev_num;
1706 rt1320->bra_msg.flags = SDW_MSG_FLAG_WRITE;
1707 rt1320->bra_msg.sections = fwheader->num;
1708 rt1320->bra_msg.sec = &sec[0];
1709 rt1320_data_rw(rt1320, 0, NULL, 0, RT1320_BRA_WRITE);
1710 dev_dbg(dev, "%s, BRA downloading FW done..\n", __func__);
1711 }
1712
1713 regcache_cache_bypass(rt1320->regmap, false);
1714 release_firmware(fw);
1715
1716 if (!dev_fw_match) {
1717 dev_err(dev, "%s: FW file doesn't match to device\n", __func__);
1718 goto _exit_;
1719 }
1720 } else {
1721 dev_err(dev, "%s: Failed to load %s firmware\n", __func__, filename);
1722 goto _exit_;
1723 }
1724
1725 /* run RAM code */
1726 regmap_read(rt1320->regmap, 0x3fc2bfc0, &val);
1727 val |= 0x8;
1728 regmap_write(rt1320->regmap, 0x3fc2bfc0, val);
1729
1730 /* clear frame counter */
1731 switch (rt1320->dev_id) {
1732 case RT1320_DEV_ID:
1733 regmap_write(rt1320->regmap, 0x3fc2bfcb, 0x00);
1734 regmap_write(rt1320->regmap, 0x3fc2bfca, 0x00);
1735 regmap_write(rt1320->regmap, 0x3fc2bfc9, 0x00);
1736 regmap_write(rt1320->regmap, 0x3fc2bfc8, 0x00);
1737 break;
1738 case RT1321_DEV_ID:
1739 regmap_write(rt1320->regmap, 0x3fc2dfcb, 0x00);
1740 regmap_write(rt1320->regmap, 0x3fc2dfca, 0x00);
1741 regmap_write(rt1320->regmap, 0x3fc2dfc9, 0x00);
1742 regmap_write(rt1320->regmap, 0x3fc2dfc8, 0x00);
1743 break;
1744 }
1745
1746 /* enable DSP FW */
1747 regmap_write(rt1320->regmap, 0xc081, 0xfc);
1748 regmap_update_bits(rt1320->regmap, 0xf01e, 0x1, 0x0);
1749
1750 /* RsRatio should restore into DSP FW when FW was ready */
1751 rt1320_invrs_load(rt1320);
1752
1753 /* DSP clock switches to PLL */
1754 regmap_write(rt1320->regmap, 0xc081, 0xfc);
1755 /* pass DSP settings */
1756 regmap_write(rt1320->regmap, 0xc5c3, 0xf3);
1757 regmap_write(rt1320->regmap, 0xc5c8, 0x05);
1758
1759 rt1320->fw_load_done = true;
1760
1761 pm_runtime_set_autosuspend_delay(dev, 3000);
1762 pm_runtime_mark_last_busy(dev);
1763
1764 _exit_:
1765 regmap_write(rt1320->regmap,
1766 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1767 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
1768 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
1769
1770 snd_soc_dapm_mutex_unlock(dapm);
1771 }
1772
rt1320_load_dspfw_work(struct work_struct * work)1773 static void rt1320_load_dspfw_work(struct work_struct *work)
1774 {
1775 struct rt1320_sdw_priv *rt1320 =
1776 container_of(work, struct rt1320_sdw_priv, load_dspfw_work);
1777 int ret;
1778
1779 ret = pm_runtime_resume(rt1320->component->dev);
1780 if (ret < 0 && ret != -EACCES)
1781 return;
1782
1783 dev_dbg(&rt1320->sdw_slave->dev, "%s, Starting to reload DSP FW", __func__);
1784 rt1320_dspfw_load_code(rt1320);
1785 }
1786
rt1320_vc_preset(struct rt1320_sdw_priv * rt1320)1787 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320)
1788 {
1789 struct sdw_slave *slave = rt1320->sdw_slave;
1790 unsigned int i, reg, val, delay, retry, tmp;
1791
1792 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) {
1793 reg = rt1320_vc_blind_write[i].reg;
1794 val = rt1320_vc_blind_write[i].def;
1795 delay = rt1320_vc_blind_write[i].delay_us;
1796
1797 if (reg == 0x3fc2bf83)
1798 rt1320_load_mcu_patch(rt1320);
1799
1800 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) &&
1801 (val == 0x00)) {
1802 retry = 200;
1803 while (retry) {
1804 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp);
1805 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp);
1806 if (tmp == 0x1f)
1807 break;
1808 usleep_range(1000, 1500);
1809 retry--;
1810 }
1811 if (!retry)
1812 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__);
1813 }
1814 regmap_write(rt1320->regmap, reg, val);
1815 if (delay)
1816 usleep_range(delay, delay + 1000);
1817
1818 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0))
1819 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val);
1820 }
1821 }
1822
rt1321_preset(struct rt1320_sdw_priv * rt1320)1823 static void rt1321_preset(struct rt1320_sdw_priv *rt1320)
1824 {
1825 unsigned int i, reg, val, delay;
1826
1827 for (i = 0; i < ARRAY_SIZE(rt1321_blind_write); i++) {
1828 reg = rt1321_blind_write[i].reg;
1829 val = rt1321_blind_write[i].def;
1830 delay = rt1321_blind_write[i].delay_us;
1831
1832 if (reg == 0x3fc2dfc3)
1833 rt1320_load_mcu_patch(rt1320);
1834
1835 regmap_write(rt1320->regmap, reg, val);
1836
1837 if (delay)
1838 usleep_range(delay, delay + 1000);
1839
1840 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0))
1841 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val);
1842 }
1843 }
1844
rt1320_io_init(struct device * dev,struct sdw_slave * slave)1845 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave)
1846 {
1847 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
1848 unsigned int amp_func_status, val, tmp;
1849
1850 if (rt1320->hw_init)
1851 return 0;
1852
1853 regcache_cache_only(rt1320->regmap, false);
1854 regcache_cache_only(rt1320->mbq_regmap, false);
1855 if (rt1320->first_hw_init) {
1856 regcache_cache_bypass(rt1320->regmap, true);
1857 regcache_cache_bypass(rt1320->mbq_regmap, true);
1858 } else {
1859 /*
1860 * PM runtime status is marked as 'active' only when a Slave reports as Attached
1861 */
1862 /* update count of parent 'active' children */
1863 pm_runtime_set_active(&slave->dev);
1864 }
1865
1866 pm_runtime_get_noresume(&slave->dev);
1867
1868 if (rt1320->version_id < 0) {
1869 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val);
1870 rt1320->version_id = val;
1871 regmap_read(rt1320->regmap, RT1320_DEV_ID_0, &val);
1872 regmap_read(rt1320->regmap, RT1320_DEV_ID_1, &tmp);
1873 rt1320->dev_id = (val << 8) | tmp;
1874 }
1875
1876 regmap_read(rt1320->regmap,
1877 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status);
1878 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status);
1879
1880 /* initialization write */
1881 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) {
1882 switch (rt1320->dev_id) {
1883 case RT1320_DEV_ID:
1884 if (rt1320->version_id < RT1320_VC)
1885 rt1320_vab_preset(rt1320);
1886 else
1887 rt1320_vc_preset(rt1320);
1888 break;
1889 case RT1321_DEV_ID:
1890 rt1321_preset(rt1320);
1891 break;
1892 default:
1893 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1894 }
1895
1896 regmap_write(rt1320->regmap,
1897 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0),
1898 FUNCTION_NEEDS_INITIALIZATION);
1899
1900 /* reload DSP FW */
1901 if (rt1320->fw_load_done)
1902 schedule_work(&rt1320->load_dspfw_work);
1903 }
1904 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA && rt1320->dev_id == RT1320_DEV_ID) {
1905 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1906 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0);
1907 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val);
1908 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp);
1909 val = (tmp << 8) | val;
1910 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp);
1911 val = (tmp << 16) | val;
1912 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp);
1913 val = (tmp << 24) | val;
1914 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val);
1915 /*
1916 * We call the version b which has the new DSP ROM code against version a.
1917 * Therefore, we read the DSP address to check the ID.
1918 */
1919 if (val == RT1320_VER_B_ID)
1920 rt1320->version_id = RT1320_VB;
1921 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1922 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3);
1923 }
1924 dev_dbg(dev, "%s version_id=%d, dev_id=0x%x\n", __func__, rt1320->version_id, rt1320->dev_id);
1925
1926 if (rt1320->first_hw_init) {
1927 regcache_cache_bypass(rt1320->regmap, false);
1928 regcache_cache_bypass(rt1320->mbq_regmap, false);
1929 regcache_mark_dirty(rt1320->regmap);
1930 regcache_mark_dirty(rt1320->mbq_regmap);
1931 }
1932
1933 /* Mark Slave initialization complete */
1934 rt1320->first_hw_init = true;
1935 rt1320->hw_init = true;
1936
1937 pm_runtime_put_autosuspend(&slave->dev);
1938
1939 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
1940 return 0;
1941 }
1942
rt1320_update_status(struct sdw_slave * slave,enum sdw_slave_status status)1943 static int rt1320_update_status(struct sdw_slave *slave,
1944 enum sdw_slave_status status)
1945 {
1946 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev);
1947
1948 if (status == SDW_SLAVE_UNATTACHED)
1949 rt1320->hw_init = false;
1950
1951 /*
1952 * Perform initialization only if slave status is present and
1953 * hw_init flag is false
1954 */
1955 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED)
1956 return 0;
1957
1958 /* perform I/O transfers required for Slave initialization */
1959 return rt1320_io_init(&slave->dev, slave);
1960 }
1961
rt1320_pde11_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1962 static int rt1320_pde11_event(struct snd_soc_dapm_widget *w,
1963 struct snd_kcontrol *kcontrol, int event)
1964 {
1965 struct snd_soc_component *component =
1966 snd_soc_dapm_to_component(w->dapm);
1967 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1968 unsigned char ps0 = 0x0, ps3 = 0x3;
1969
1970 switch (event) {
1971 case SND_SOC_DAPM_POST_PMU:
1972 regmap_write(rt1320->regmap,
1973 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11,
1974 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
1975 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0);
1976 break;
1977 case SND_SOC_DAPM_PRE_PMD:
1978 regmap_write(rt1320->regmap,
1979 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11,
1980 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
1981 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3);
1982 break;
1983 default:
1984 break;
1985 }
1986
1987 return 0;
1988 }
1989
rt1320_pde23_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1990 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w,
1991 struct snd_kcontrol *kcontrol, int event)
1992 {
1993 struct snd_soc_component *component =
1994 snd_soc_dapm_to_component(w->dapm);
1995 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1996 unsigned char ps0 = 0x0, ps3 = 0x3;
1997
1998 switch (event) {
1999 case SND_SOC_DAPM_POST_PMU:
2000 regmap_write(rt1320->regmap,
2001 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
2002 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
2003 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0);
2004 break;
2005 case SND_SOC_DAPM_PRE_PMD:
2006 regmap_write(rt1320->regmap,
2007 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
2008 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
2009 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3);
2010 break;
2011 default:
2012 break;
2013 }
2014
2015 return 0;
2016 }
2017
rt1320_set_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2018 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol,
2019 struct snd_ctl_elem_value *ucontrol)
2020 {
2021 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2022 struct soc_mixer_control *mc =
2023 (struct soc_mixer_control *)kcontrol->private_value;
2024 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2025 unsigned int gain_l_val, gain_r_val;
2026 unsigned int lvalue, rvalue;
2027 const unsigned int interval_offset = 0xc0;
2028 unsigned int changed = 0, reg_base;
2029 struct rt_sdca_dmic_kctrl_priv *p;
2030 unsigned int regvalue[4], gain_val[4], i;
2031 int err;
2032
2033 if (strstr(ucontrol->id.name, "FU Capture Volume"))
2034 goto _dmic_vol_;
2035
2036 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue);
2037 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue);
2038
2039 /* L Channel */
2040 gain_l_val = ucontrol->value.integer.value[0];
2041 if (gain_l_val > mc->max)
2042 gain_l_val = mc->max;
2043 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset);
2044 gain_l_val &= 0xffff;
2045
2046 /* R Channel */
2047 gain_r_val = ucontrol->value.integer.value[1];
2048 if (gain_r_val > mc->max)
2049 gain_r_val = mc->max;
2050 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset);
2051 gain_r_val &= 0xffff;
2052
2053 if (lvalue == gain_l_val && rvalue == gain_r_val)
2054 return 0;
2055
2056 /* Lch*/
2057 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val);
2058 /* Rch */
2059 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val);
2060 goto _done_;
2061
2062 _dmic_vol_:
2063 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2064
2065 /* check all channels */
2066 for (i = 0; i < p->count; i++) {
2067 switch (rt1320->dev_id) {
2068 case RT1320_DEV_ID:
2069 if (i < 2) {
2070 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2071 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]);
2072 } else {
2073 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2074 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]);
2075 }
2076 break;
2077 case RT1321_DEV_ID:
2078 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2079 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]);
2080 break;
2081 }
2082
2083 gain_val[i] = ucontrol->value.integer.value[i];
2084 if (gain_val[i] > p->max)
2085 gain_val[i] = p->max;
2086
2087 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset);
2088 gain_val[i] &= 0xffff;
2089 if (regvalue[i] != gain_val[i])
2090 changed = 1;
2091 }
2092
2093 if (!changed)
2094 return 0;
2095
2096 for (i = 0; i < p->count; i++) {
2097 switch (rt1320->dev_id) {
2098 case RT1320_DEV_ID:
2099 if (i < 2) {
2100 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2101 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]);
2102 } else {
2103 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2104 err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]);
2105 }
2106 break;
2107 case RT1321_DEV_ID:
2108 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2109 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]);
2110 break;
2111 }
2112
2113 if (err < 0)
2114 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i);
2115 }
2116
2117 _done_:
2118 return 1;
2119 }
2120
rt1320_set_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2121 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol,
2122 struct snd_ctl_elem_value *ucontrol)
2123 {
2124 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2125 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2126 struct soc_mixer_control *mc =
2127 (struct soc_mixer_control *)kcontrol->private_value;
2128 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
2129 const unsigned int interval_offset = 0xc0;
2130 unsigned int reg_base, regvalue, ctl, i;
2131 struct rt_sdca_dmic_kctrl_priv *p;
2132
2133 if (strstr(ucontrol->id.name, "FU Capture Volume"))
2134 goto _dmic_vol_;
2135
2136 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l);
2137 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r);
2138
2139 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset);
2140
2141 if (read_l != read_r)
2142 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset);
2143 else
2144 ctl_r = ctl_l;
2145
2146 ucontrol->value.integer.value[0] = ctl_l;
2147 ucontrol->value.integer.value[1] = ctl_r;
2148 goto _done_;
2149
2150 _dmic_vol_:
2151 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2152
2153 /* check all channels */
2154 for (i = 0; i < p->count; i++) {
2155 switch (rt1320->dev_id) {
2156 case RT1320_DEV_ID:
2157 if (i < 2) {
2158 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2159 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value);
2160 } else {
2161 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2162 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value);
2163 }
2164 break;
2165 case RT1321_DEV_ID:
2166 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2167 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value);
2168 break;
2169 }
2170
2171 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset);
2172 ucontrol->value.integer.value[i] = ctl;
2173 }
2174 _done_:
2175 return 0;
2176 }
2177
rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv * rt1320)2178 static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320)
2179 {
2180 int err, i;
2181 unsigned int ch_mute;
2182
2183 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) {
2184 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00;
2185
2186 switch (rt1320->dev_id) {
2187 case RT1320_DEV_ID:
2188 if (i < 2)
2189 err = regmap_write(rt1320->regmap,
2190 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113,
2191 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
2192 else
2193 err = regmap_write(rt1320->regmap,
2194 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14,
2195 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute);
2196 break;
2197 case RT1321_DEV_ID:
2198 err = regmap_write(rt1320->regmap,
2199 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113,
2200 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
2201 break;
2202 default:
2203 dev_err(&rt1320->sdw_slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
2204 return -EINVAL;
2205 }
2206 if (err < 0)
2207 return err;
2208 }
2209
2210 return 0;
2211 }
2212
rt1320_dmic_fu_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2213 static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol,
2214 struct snd_ctl_elem_value *ucontrol)
2215 {
2216 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2217 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2218 struct rt_sdca_dmic_kctrl_priv *p =
2219 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2220 unsigned int i;
2221
2222 for (i = 0; i < p->count; i++)
2223 ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i];
2224
2225 return 0;
2226 }
2227
rt1320_dmic_fu_capture_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2228 static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol,
2229 struct snd_ctl_elem_value *ucontrol)
2230 {
2231 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2232 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2233 struct rt_sdca_dmic_kctrl_priv *p =
2234 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2235 int err, changed = 0, i;
2236
2237 for (i = 0; i < p->count; i++) {
2238 if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i])
2239 changed = 1;
2240 rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i];
2241 }
2242
2243 err = rt1320_set_fu_capture_ctl(rt1320);
2244 if (err < 0)
2245 return err;
2246
2247 return changed;
2248 }
2249
rt1320_dmic_fu_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2250 static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol,
2251 struct snd_ctl_elem_info *uinfo)
2252 {
2253 struct rt_sdca_dmic_kctrl_priv *p =
2254 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2255
2256 if (p->max == 1)
2257 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2258 else
2259 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2260 uinfo->count = p->count;
2261 uinfo->value.integer.min = 0;
2262 uinfo->value.integer.max = p->max;
2263 return 0;
2264 }
2265
rt1320_dmic_fu_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2266 static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w,
2267 struct snd_kcontrol *kcontrol, int event)
2268 {
2269 struct snd_soc_component *component =
2270 snd_soc_dapm_to_component(w->dapm);
2271 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2272
2273 switch (event) {
2274 case SND_SOC_DAPM_POST_PMU:
2275 rt1320->fu_dapm_mute = false;
2276 rt1320_set_fu_capture_ctl(rt1320);
2277 break;
2278 case SND_SOC_DAPM_PRE_PMD:
2279 rt1320->fu_dapm_mute = true;
2280 rt1320_set_fu_capture_ctl(rt1320);
2281 break;
2282 }
2283 return 0;
2284 }
2285
2286 static const char * const rt1320_rx_data_ch_select[] = {
2287 "L,R",
2288 "R,L",
2289 "L,L",
2290 "R,R",
2291 "L,L+R",
2292 "R,L+R",
2293 "L+R,L",
2294 "L+R,R",
2295 "L+R,L+R",
2296 };
2297
2298 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum,
2299 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0,
2300 rt1320_rx_data_ch_select);
2301
2302 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
2303 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
2304
rt1320_r0_load(struct rt1320_sdw_priv * rt1320)2305 static int rt1320_r0_load(struct rt1320_sdw_priv *rt1320)
2306 {
2307 struct device *dev = regmap_get_device(rt1320->regmap);
2308 unsigned int fw_status_addr;
2309 unsigned int fw_ready;
2310 int ret = 0;
2311
2312 if (!rt1320->r0_l_reg || !rt1320->r0_r_reg)
2313 return -EINVAL;
2314
2315 switch (rt1320->dev_id) {
2316 case RT1320_DEV_ID:
2317 fw_status_addr = RT1320_DSPFW_STATUS_ADDR;
2318 break;
2319 case RT1321_DEV_ID:
2320 fw_status_addr = RT1321_DSPFW_STATUS_ADDR;
2321 break;
2322 default:
2323 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
2324 return -EINVAL;
2325 }
2326
2327 regmap_write(rt1320->regmap,
2328 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
2329 ret = rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
2330 if (ret < 0) {
2331 dev_dbg(dev, "%s, PDE=PS0 is NOT ready\n", __func__);
2332 goto _timeout_;
2333 }
2334
2335 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready);
2336 fw_ready &= 0x1;
2337 if (!fw_ready) {
2338 dev_dbg(dev, "%s, DSP FW is NOT ready\n", __func__);
2339 goto _timeout_;
2340 }
2341
2342 ret = rt1320_check_power_state_ready(rt1320, RT1320_NORMAL_STATE);
2343 if (ret < 0) {
2344 dev_dbg(dev, "%s, DSP FW PS is NOT ready\n", __func__);
2345 goto _timeout_;
2346 }
2347
2348 rt1320_set_advancemode(rt1320);
2349
2350 _timeout_:
2351 regmap_write(rt1320->regmap,
2352 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
2353 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
2354
2355 return ret;
2356 }
2357
rt1320_r0_load_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2358 static int rt1320_r0_load_mode_get(struct snd_kcontrol *kcontrol,
2359 struct snd_ctl_elem_value *ucontrol)
2360 {
2361 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2362 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2363
2364 ucontrol->value.integer.value[0] = rt1320->r0_l_reg;
2365 ucontrol->value.integer.value[1] = rt1320->r0_r_reg;
2366
2367 return 0;
2368 }
2369
rt1320_r0_load_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2370 static int rt1320_r0_load_mode_put(struct snd_kcontrol *kcontrol,
2371 struct snd_ctl_elem_value *ucontrol)
2372 {
2373 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2374 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2375 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component);
2376 int ret;
2377
2378 if (!rt1320->hw_init)
2379 return 0;
2380
2381 if (ucontrol->value.integer.value[0] == 0 ||
2382 ucontrol->value.integer.value[1] == 0)
2383 return -EINVAL;
2384
2385 ret = pm_runtime_resume(component->dev);
2386 if (ret < 0 && ret != -EACCES)
2387 return ret;
2388
2389 snd_soc_dapm_mutex_lock(dapm);
2390 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) {
2391 rt1320->r0_l_reg = ucontrol->value.integer.value[0];
2392 rt1320->r0_r_reg = ucontrol->value.integer.value[1];
2393 rt1320_calc_r0(rt1320);
2394 rt1320_r0_load(rt1320);
2395 }
2396 snd_soc_dapm_mutex_unlock(dapm);
2397
2398 return 0;
2399 }
2400
rt1320_t0_r0_load_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2401 static int rt1320_t0_r0_load_info(struct snd_kcontrol *kcontrol,
2402 struct snd_ctl_elem_info *uinfo)
2403 {
2404 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2405 uinfo->count = 2;
2406 uinfo->value.integer.max = kcontrol->private_value;
2407
2408 return 0;
2409 }
2410
2411 #define RT1320_T0_R0_LOAD(xname, xmax, xhandler_get, xhandler_put) \
2412 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2413 .info = rt1320_t0_r0_load_info, \
2414 .get = xhandler_get, \
2415 .put = xhandler_put, \
2416 .private_value = xmax, \
2417 }
2418
rt1320_dspfw_load_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2419 static int rt1320_dspfw_load_get(struct snd_kcontrol *kcontrol,
2420 struct snd_ctl_elem_value *ucontrol)
2421 {
2422 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2423 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2424
2425 ucontrol->value.integer.value[0] = rt1320->fw_load_done;
2426 return 0;
2427 }
2428
rt1320_dspfw_load_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2429 static int rt1320_dspfw_load_put(struct snd_kcontrol *kcontrol,
2430 struct snd_ctl_elem_value *ucontrol)
2431 {
2432 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2433 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2434 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
2435 int ret;
2436
2437 if (!rt1320->hw_init)
2438 return 0;
2439
2440 ret = pm_runtime_resume(component->dev);
2441 if (ret < 0 && ret != -EACCES)
2442 return ret;
2443
2444 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF &&
2445 ucontrol->value.integer.value[0])
2446 rt1320_dspfw_load_code(rt1320);
2447
2448 if (!ucontrol->value.integer.value[0])
2449 rt1320->fw_load_done = false;
2450
2451 return 0;
2452 }
2453
rt1320_rae_update_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2454 static int rt1320_rae_update_get(struct snd_kcontrol *kcontrol,
2455 struct snd_ctl_elem_value *ucontrol)
2456 {
2457 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2458 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2459
2460 ucontrol->value.integer.value[0] = rt1320->rae_update_done;
2461 return 0;
2462 }
2463
rt1320_rae_update_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2464 static int rt1320_rae_update_put(struct snd_kcontrol *kcontrol,
2465 struct snd_ctl_elem_value *ucontrol)
2466 {
2467 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2468 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2469 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
2470 int ret;
2471
2472 if (!rt1320->hw_init)
2473 return 0;
2474
2475 ret = pm_runtime_resume(component->dev);
2476 if (ret < 0 && ret != -EACCES)
2477 return ret;
2478
2479 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF &&
2480 ucontrol->value.integer.value[0] && rt1320->fw_load_done)
2481 rt1320_rae_load(rt1320);
2482
2483 if (!ucontrol->value.integer.value[0])
2484 rt1320->rae_update_done = false;
2485
2486 return 0;
2487 }
2488
rt1320_r0_temperature_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2489 static int rt1320_r0_temperature_get(struct snd_kcontrol *kcontrol,
2490 struct snd_ctl_elem_value *ucontrol)
2491 {
2492 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2493 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2494
2495 ucontrol->value.integer.value[0] = rt1320->temp_l_calib;
2496 ucontrol->value.integer.value[1] = rt1320->temp_r_calib;
2497 return 0;
2498 }
2499
rt1320_r0_temperature_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2500 static int rt1320_r0_temperature_put(struct snd_kcontrol *kcontrol,
2501 struct snd_ctl_elem_value *ucontrol)
2502 {
2503 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2504 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2505 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component);
2506 int ret;
2507
2508 if (!rt1320->hw_init)
2509 return 0;
2510
2511 ret = pm_runtime_resume(component->dev);
2512 if (ret < 0 && ret != -EACCES)
2513 return ret;
2514
2515 snd_soc_dapm_mutex_lock(dapm);
2516 if ((snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) &&
2517 ucontrol->value.integer.value[0] && ucontrol->value.integer.value[1])
2518 rt1320_t0_load(rt1320, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1]);
2519 snd_soc_dapm_mutex_unlock(dapm);
2520
2521 return 0;
2522 }
2523
2524 static const struct snd_kcontrol_new rt1320_snd_controls[] = {
2525 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume",
2526 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01),
2527 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02),
2528 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv),
2529 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum),
2530
2531 RT_SDCA_FU_CTRL("FU Capture Switch",
2532 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01),
2533 1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put),
2534 RT_SDCA_EXT_TLV("FU Capture Volume",
2535 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01),
2536 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info),
2537
2538 SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0,
2539 rt1320_r0_cali_get, rt1320_r0_cali_put),
2540 SOC_SINGLE_EXT("DSP FW Update", SND_SOC_NOPM, 0, 1, 0,
2541 rt1320_dspfw_load_get, rt1320_dspfw_load_put),
2542 RT1320_T0_R0_LOAD("R0 Load Mode", 0xffffffff,
2543 rt1320_r0_load_mode_get, rt1320_r0_load_mode_put),
2544 RT1320_T0_R0_LOAD("R0 Temperature", 0xff,
2545 rt1320_r0_temperature_get, rt1320_r0_temperature_put),
2546 SOC_SINGLE_EXT("RAE Update", SND_SOC_NOPM, 0, 1, 0,
2547 rt1320_rae_update_get, rt1320_rae_update_put),
2548 };
2549
2550 static const struct snd_kcontrol_new rt1320_spk_l_dac =
2551 SOC_DAPM_SINGLE_AUTODISABLE("Switch",
2552 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01),
2553 0, 1, 1);
2554 static const struct snd_kcontrol_new rt1320_spk_r_dac =
2555 SOC_DAPM_SINGLE_AUTODISABLE("Switch",
2556 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02),
2557 0, 1, 1);
2558
2559 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = {
2560 /* Audio Interface */
2561 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
2562 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
2563 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0),
2564
2565 /* Digital Interface */
2566 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0),
2567 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0,
2568 rt1320_pde23_event,
2569 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2570 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0,
2571 rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2572 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0),
2573 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0),
2574 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0,
2575 rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2576
2577 /* Output */
2578 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac),
2579 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac),
2580 SND_SOC_DAPM_OUTPUT("SPOL"),
2581 SND_SOC_DAPM_OUTPUT("SPOR"),
2582
2583 /* Input */
2584 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0),
2585 SND_SOC_DAPM_SIGGEN("AEC Gen"),
2586 SND_SOC_DAPM_INPUT("DMIC1"),
2587 SND_SOC_DAPM_INPUT("DMIC2"),
2588 };
2589
2590 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = {
2591 { "FU21", NULL, "DP1RX" },
2592 { "FU21", NULL, "PDE 23" },
2593 { "OT23 L", "Switch", "FU21" },
2594 { "OT23 R", "Switch", "FU21" },
2595 { "SPOL", NULL, "OT23 L" },
2596 { "SPOR", NULL, "OT23 R" },
2597
2598 { "AEC Data", NULL, "AEC Gen" },
2599 { "DP4TX", NULL, "AEC Data" },
2600
2601 {"DP8-10TX", NULL, "FU"},
2602 {"FU", NULL, "PDE 11"},
2603 {"FU", NULL, "FU 113"},
2604 {"FU", NULL, "FU 14"},
2605 {"FU 113", NULL, "DMIC1"},
2606 {"FU 14", NULL, "DMIC2"},
2607 };
2608
rt1320_set_sdw_stream(struct snd_soc_dai * dai,void * sdw_stream,int direction)2609 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
2610 int direction)
2611 {
2612 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
2613 return 0;
2614 }
2615
rt1320_sdw_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2616 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream,
2617 struct snd_soc_dai *dai)
2618 {
2619 snd_soc_dai_set_dma_data(dai, substream, NULL);
2620 }
2621
rt1320_sdw_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2622 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream,
2623 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2624 {
2625 struct snd_soc_component *component = dai->component;
2626 struct rt1320_sdw_priv *rt1320 =
2627 snd_soc_component_get_drvdata(component);
2628 struct sdw_stream_config stream_config;
2629 struct sdw_port_config port_config;
2630 struct sdw_port_config dmic_port_config[2];
2631 struct sdw_stream_runtime *sdw_stream;
2632 int retval;
2633 unsigned int sampling_rate;
2634
2635 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
2636 sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
2637
2638 if (!sdw_stream)
2639 return -EINVAL;
2640
2641 if (!rt1320->sdw_slave)
2642 return -EINVAL;
2643
2644 /* SoundWire specific configuration */
2645 snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
2646
2647 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2648 if (dai->id == RT1320_AIF1)
2649 port_config.num = 1;
2650 else
2651 return -EINVAL;
2652 } else {
2653 if (dai->id == RT1320_AIF1)
2654 port_config.num = 4;
2655 else if (dai->id == RT1320_AIF2) {
2656 switch (rt1320->dev_id) {
2657 case RT1320_DEV_ID:
2658 dmic_port_config[0].ch_mask = BIT(0) | BIT(1);
2659 dmic_port_config[0].num = 8;
2660 dmic_port_config[1].ch_mask = BIT(0) | BIT(1);
2661 dmic_port_config[1].num = 10;
2662 break;
2663 case RT1321_DEV_ID:
2664 dmic_port_config[0].ch_mask = BIT(0) | BIT(1);
2665 dmic_port_config[0].num = 8;
2666 break;
2667 default:
2668 return -EINVAL;
2669 }
2670 } else
2671 return -EINVAL;
2672 }
2673
2674 if (dai->id == RT1320_AIF1)
2675 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
2676 &port_config, 1, sdw_stream);
2677 else if (dai->id == RT1320_AIF2) {
2678 switch (rt1320->dev_id) {
2679 case RT1320_DEV_ID:
2680 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
2681 dmic_port_config, 2, sdw_stream);
2682 break;
2683 case RT1321_DEV_ID:
2684 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
2685 dmic_port_config, 1, sdw_stream);
2686 break;
2687 default:
2688 dev_err(dai->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
2689 return -EINVAL;
2690 }
2691 } else
2692 return -EINVAL;
2693 if (retval) {
2694 dev_err(dai->dev, "%s: Unable to configure port\n", __func__);
2695 return retval;
2696 }
2697
2698 /* sampling rate configuration */
2699 switch (params_rate(params)) {
2700 case 16000:
2701 sampling_rate = RT1320_SDCA_RATE_16000HZ;
2702 break;
2703 case 32000:
2704 sampling_rate = RT1320_SDCA_RATE_32000HZ;
2705 break;
2706 case 44100:
2707 sampling_rate = RT1320_SDCA_RATE_44100HZ;
2708 break;
2709 case 48000:
2710 sampling_rate = RT1320_SDCA_RATE_48000HZ;
2711 break;
2712 case 96000:
2713 sampling_rate = RT1320_SDCA_RATE_96000HZ;
2714 break;
2715 case 192000:
2716 sampling_rate = RT1320_SDCA_RATE_192000HZ;
2717 break;
2718 default:
2719 dev_err(component->dev, "%s: Rate %d is not supported\n",
2720 __func__, params_rate(params));
2721 return -EINVAL;
2722 }
2723
2724 /* set sampling frequency */
2725 if (dai->id == RT1320_AIF1)
2726 regmap_write(rt1320->regmap,
2727 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
2728 sampling_rate);
2729 else {
2730 regmap_write(rt1320->regmap,
2731 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
2732 sampling_rate);
2733
2734 if (rt1320->dev_id == RT1320_DEV_ID)
2735 regmap_write(rt1320->regmap,
2736 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
2737 sampling_rate);
2738 }
2739
2740 return 0;
2741 }
2742
rt1320_sdw_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2743 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
2744 struct snd_soc_dai *dai)
2745 {
2746 struct snd_soc_component *component = dai->component;
2747 struct rt1320_sdw_priv *rt1320 =
2748 snd_soc_component_get_drvdata(component);
2749 struct sdw_stream_runtime *sdw_stream =
2750 snd_soc_dai_get_dma_data(dai, substream);
2751
2752 if (!rt1320->sdw_slave)
2753 return -EINVAL;
2754
2755 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream);
2756 return 0;
2757 }
2758
2759 /*
2760 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
2761 * port_prep are not defined for now
2762 */
2763 static const struct sdw_slave_ops rt1320_slave_ops = {
2764 .read_prop = rt1320_read_prop,
2765 .update_status = rt1320_update_status,
2766 };
2767
rt1320_sdw_component_probe(struct snd_soc_component * component)2768 static int rt1320_sdw_component_probe(struct snd_soc_component *component)
2769 {
2770 int ret;
2771 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2772
2773 rt1320->component = component;
2774
2775 if (!rt1320->first_hw_init)
2776 return 0;
2777
2778 ret = pm_runtime_resume(component->dev);
2779 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret);
2780 if (ret < 0 && ret != -EACCES)
2781 return ret;
2782
2783 /* Apply temperature and calibration data from device property */
2784 if ((rt1320->temp_l_calib <= 0xff) && (rt1320->temp_l_calib > 0) &&
2785 (rt1320->temp_r_calib <= 0xff) && (rt1320->temp_r_calib > 0))
2786 rt1320_t0_load(rt1320, rt1320->temp_l_calib, rt1320->temp_r_calib);
2787
2788 if (rt1320->r0_l_calib && rt1320->r0_r_calib) {
2789 rt1320->r0_l_reg = rt1320->r0_l_calib;
2790 rt1320->r0_r_reg = rt1320->r0_r_calib;
2791 rt1320_calc_r0(rt1320);
2792 rt1320_r0_load(rt1320);
2793 }
2794
2795 return 0;
2796 }
2797
2798 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = {
2799 .probe = rt1320_sdw_component_probe,
2800 .controls = rt1320_snd_controls,
2801 .num_controls = ARRAY_SIZE(rt1320_snd_controls),
2802 .dapm_widgets = rt1320_dapm_widgets,
2803 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets),
2804 .dapm_routes = rt1320_dapm_routes,
2805 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes),
2806 .endianness = 1,
2807 };
2808
2809 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = {
2810 .hw_params = rt1320_sdw_hw_params,
2811 .hw_free = rt1320_sdw_pcm_hw_free,
2812 .set_stream = rt1320_set_sdw_stream,
2813 .shutdown = rt1320_sdw_shutdown,
2814 };
2815
2816 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
2817 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
2818 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
2819 SNDRV_PCM_FMTBIT_S32_LE)
2820
2821 static struct snd_soc_dai_driver rt1320_sdw_dai[] = {
2822 {
2823 .name = "rt1320-aif1",
2824 .id = RT1320_AIF1,
2825 .playback = {
2826 .stream_name = "DP1 Playback",
2827 .channels_min = 1,
2828 .channels_max = 2,
2829 .rates = RT1320_STEREO_RATES,
2830 .formats = RT1320_FORMATS,
2831 },
2832 .capture = {
2833 .stream_name = "DP4 Capture",
2834 .channels_min = 1,
2835 .channels_max = 2,
2836 .rates = RT1320_STEREO_RATES,
2837 .formats = RT1320_FORMATS,
2838 },
2839 .ops = &rt1320_aif_dai_ops,
2840 },
2841 /* DMIC: DP8 2ch + DP10 2ch */
2842 {
2843 .name = "rt1320-aif2",
2844 .id = RT1320_AIF2,
2845 .capture = {
2846 .stream_name = "DP8-10 Capture",
2847 .channels_min = 1,
2848 .channels_max = 4,
2849 .rates = RT1320_STEREO_RATES,
2850 .formats = RT1320_FORMATS,
2851 },
2852 .ops = &rt1320_aif_dai_ops,
2853 },
2854 };
2855
rt1320_parse_dp(struct rt1320_sdw_priv * rt1320,struct device * dev)2856 static int rt1320_parse_dp(struct rt1320_sdw_priv *rt1320, struct device *dev)
2857 {
2858 device_property_read_u32(dev, "realtek,temperature_l_calib",
2859 &rt1320->temp_l_calib);
2860 device_property_read_u32(dev, "realtek,temperature_r_calib",
2861 &rt1320->temp_r_calib);
2862 device_property_read_u32(dev, "realtek,r0_l_calib",
2863 &rt1320->r0_l_calib);
2864 device_property_read_u32(dev, "realtek,r0_r_calib",
2865 &rt1320->r0_r_calib);
2866 device_property_read_string(dev, "realtek,dspfw-name",
2867 &rt1320->dspfw_name);
2868
2869 dev_dbg(dev, "%s: temp_l_calib: %d temp_r_calib: %d r0_l_calib: %d, r0_r_calib: %d",
2870 __func__, rt1320->temp_l_calib, rt1320->temp_r_calib, rt1320->r0_l_calib, rt1320->r0_r_calib);
2871 dev_dbg(dev, "%s: dspfw_name: %s", __func__, rt1320->dspfw_name);
2872
2873 return 0;
2874 }
2875
rt1320_sdw_init(struct device * dev,struct regmap * regmap,struct regmap * mbq_regmap,struct sdw_slave * slave)2876 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap,
2877 struct regmap *mbq_regmap, struct sdw_slave *slave)
2878 {
2879 struct rt1320_sdw_priv *rt1320;
2880 int ret;
2881
2882 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL);
2883 if (!rt1320)
2884 return -ENOMEM;
2885
2886 dev_set_drvdata(dev, rt1320);
2887 rt1320->sdw_slave = slave;
2888 rt1320->mbq_regmap = mbq_regmap;
2889 rt1320->regmap = regmap;
2890
2891 regcache_cache_only(rt1320->regmap, true);
2892 regcache_cache_only(rt1320->mbq_regmap, true);
2893
2894 rt1320_parse_dp(rt1320, dev);
2895
2896 /*
2897 * Mark hw_init to false
2898 * HW init will be performed when device reports present
2899 */
2900 rt1320->hw_init = false;
2901 rt1320->first_hw_init = false;
2902 rt1320->version_id = -1;
2903 rt1320->fu_dapm_mute = true;
2904 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] =
2905 rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true;
2906
2907 INIT_WORK(&rt1320->load_dspfw_work, rt1320_load_dspfw_work);
2908
2909 ret = devm_snd_soc_register_component(dev,
2910 &soc_component_sdw_rt1320,
2911 rt1320_sdw_dai,
2912 ARRAY_SIZE(rt1320_sdw_dai));
2913 if (ret < 0)
2914 return ret;
2915
2916 /* set autosuspend parameters */
2917 pm_runtime_set_autosuspend_delay(dev, 3000);
2918 pm_runtime_use_autosuspend(dev);
2919
2920 /* make sure the device does not suspend immediately */
2921 pm_runtime_mark_last_busy(dev);
2922
2923 pm_runtime_enable(dev);
2924
2925 /* important note: the device is NOT tagged as 'active' and will remain
2926 * 'suspended' until the hardware is enumerated/initialized. This is required
2927 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
2928 * fail with -EACCESS because of race conditions between card creation and enumeration
2929 */
2930
2931 dev_dbg(dev, "%s\n", __func__);
2932
2933 return ret;
2934 }
2935
rt1320_sdw_probe(struct sdw_slave * slave,const struct sdw_device_id * id)2936 static int rt1320_sdw_probe(struct sdw_slave *slave,
2937 const struct sdw_device_id *id)
2938 {
2939 struct regmap *regmap, *mbq_regmap;
2940
2941 /* Regmap Initialization */
2942 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap);
2943 if (IS_ERR(mbq_regmap))
2944 return PTR_ERR(mbq_regmap);
2945
2946 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap);
2947 if (IS_ERR(regmap))
2948 return PTR_ERR(regmap);
2949
2950 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave);
2951 }
2952
rt1320_sdw_remove(struct sdw_slave * slave)2953 static void rt1320_sdw_remove(struct sdw_slave *slave)
2954 {
2955 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev);
2956
2957 cancel_work_sync(&rt1320->load_dspfw_work);
2958 pm_runtime_disable(&slave->dev);
2959 }
2960
2961 /*
2962 * Version A/B will use the class id 0
2963 * The newer version than A/B will use the class id 1, so add it in advance
2964 */
2965 static const struct sdw_device_id rt1320_id[] = {
2966 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0),
2967 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0),
2968 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1321, 0x3, 0x1, 0),
2969 {},
2970 };
2971 MODULE_DEVICE_TABLE(sdw, rt1320_id);
2972
rt1320_dev_suspend(struct device * dev)2973 static int rt1320_dev_suspend(struct device *dev)
2974 {
2975 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
2976
2977 if (!rt1320->hw_init)
2978 return 0;
2979
2980 regcache_cache_only(rt1320->regmap, true);
2981 regcache_cache_only(rt1320->mbq_regmap, true);
2982 return 0;
2983 }
2984
2985 #define RT1320_PROBE_TIMEOUT 5000
2986
rt1320_dev_resume(struct device * dev)2987 static int rt1320_dev_resume(struct device *dev)
2988 {
2989 struct sdw_slave *slave = dev_to_sdw_dev(dev);
2990 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
2991 unsigned long time;
2992
2993 if (!rt1320->first_hw_init)
2994 return 0;
2995
2996 if (!slave->unattach_request)
2997 goto regmap_sync;
2998
2999 time = wait_for_completion_timeout(&slave->initialization_complete,
3000 msecs_to_jiffies(RT1320_PROBE_TIMEOUT));
3001 if (!time) {
3002 dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__);
3003 return -ETIMEDOUT;
3004 }
3005
3006 regmap_sync:
3007 slave->unattach_request = 0;
3008 regcache_cache_only(rt1320->regmap, false);
3009 regcache_sync(rt1320->regmap);
3010 regcache_cache_only(rt1320->mbq_regmap, false);
3011 regcache_sync(rt1320->mbq_regmap);
3012 return 0;
3013 }
3014
3015 static const struct dev_pm_ops rt1320_pm = {
3016 SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume)
3017 RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL)
3018 };
3019
3020 static struct sdw_driver rt1320_sdw_driver = {
3021 .driver = {
3022 .name = "rt1320-sdca",
3023 .pm = pm_ptr(&rt1320_pm),
3024 },
3025 .probe = rt1320_sdw_probe,
3026 .remove = rt1320_sdw_remove,
3027 .ops = &rt1320_slave_ops,
3028 .id_table = rt1320_id,
3029 };
3030 module_sdw_driver(rt1320_sdw_driver);
3031
3032 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW");
3033 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
3034 MODULE_LICENSE("GPL");
3035