1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_H__ 28 #define __AMDGPU_DM_H__ 29 30 #include <drm/display/drm_dp_mst_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_connector.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_plane.h> 35 #include "link_service_types.h" 36 #include <drm/drm_writeback.h> 37 38 /* 39 * This file contains the definition for amdgpu_display_manager 40 * and its API for amdgpu driver's use. 41 * This component provides all the display related functionality 42 * and this is the only component that calls DAL API. 43 * The API contained here intended for amdgpu driver use. 44 * The API that is called directly from KMS framework is located 45 * in amdgpu_dm_kms.h file 46 */ 47 48 #define AMDGPU_DM_MAX_CRTC 6 49 50 #define AMDGPU_DM_MAX_NUM_EDP 2 51 52 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 53 54 enum amd_vsdb_panel_type { 55 AMD_VSDB_PANEL_TYPE_DEFAULT = 0, 56 AMD_VSDB_PANEL_TYPE_MINILED, 57 AMD_VSDB_PANEL_TYPE_OLED, 58 AMD_VSDB_PANEL_TYPE_RESERVED, 59 }; 60 61 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 62 63 /* 64 * Maximum HDMI HPD debounce delay in milliseconds 65 */ 66 #define AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 5000 67 /* 68 #include "include/amdgpu_dal_power_if.h" 69 #include "amdgpu_dm_irq.h" 70 */ 71 72 #include "irq_types.h" 73 #include "signal_types.h" 74 #include "amdgpu_dm_crc.h" 75 #include "mod_info_packet.h" 76 struct aux_payload; 77 struct set_config_cmd_payload; 78 enum aux_return_code_type; 79 enum set_config_status; 80 81 /* Forward declarations */ 82 struct amdgpu_device; 83 struct amdgpu_crtc; 84 struct drm_device; 85 struct dc; 86 struct amdgpu_bo; 87 struct dmub_srv; 88 struct dc_plane_state; 89 struct dmub_notification; 90 struct dmub_cmd_fused_request; 91 92 struct common_irq_params { 93 struct amdgpu_device *adev; 94 enum dc_irq_source irq_src; 95 atomic64_t previous_timestamp; 96 }; 97 98 /** 99 * struct dm_compressor_info - Buffer info used by frame buffer compression 100 * @cpu_addr: MMIO cpu addr 101 * @bo_ptr: Pointer to the buffer object 102 * @gpu_addr: MMIO gpu addr 103 */ 104 struct dm_compressor_info { 105 void *cpu_addr; 106 struct amdgpu_bo *bo_ptr; 107 uint64_t gpu_addr; 108 }; 109 110 /** 111 * struct dm_boot_time_crc_info - Buffer info used by boot time CRC 112 * @cpu_addr: MMIO cpu addr 113 * @bo_ptr: Pointer to the buffer object 114 * @gpu_addr: MMIO gpu addr 115 * @size: Size of the buffer 116 */ 117 struct dm_boot_time_crc_info { 118 void *cpu_addr; 119 struct amdgpu_bo *bo_ptr; 120 uint64_t gpu_addr; 121 uint32_t size; 122 }; 123 124 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 125 126 /** 127 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 128 * 129 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 130 * @dmub_notify: notification for callback function 131 * @adev: amdgpu_device pointer 132 */ 133 struct dmub_hpd_work { 134 struct work_struct handle_hpd_work; 135 struct dmub_notification *dmub_notify; 136 struct amdgpu_device *adev; 137 }; 138 139 /** 140 * struct vblank_control_work - Work data for vblank control 141 * @work: Kernel work data for the work event 142 * @dm: amdgpu display manager device 143 * @acrtc: amdgpu CRTC instance for which the event has occurred 144 * @stream: DC stream for which the event has occurred 145 * @enable: true if enabling vblank 146 */ 147 struct vblank_control_work { 148 struct work_struct work; 149 struct amdgpu_display_manager *dm; 150 struct amdgpu_crtc *acrtc; 151 struct dc_stream_state *stream; 152 bool enable; 153 }; 154 155 /** 156 * struct idle_workqueue - Work data for periodic action in idle 157 * @work: Kernel work data for the work event 158 * @dm: amdgpu display manager device 159 * @enable: true if idle worker is enabled 160 * @running: true if idle worker is running 161 */ 162 struct idle_workqueue { 163 struct work_struct work; 164 struct amdgpu_display_manager *dm; 165 bool enable; 166 bool running; 167 }; 168 169 /** 170 * struct vupdate_offload_work - Work data for offloading task from vupdate handler 171 * @work: Kernel work data for the work event 172 * @adev: amdgpu_device back pointer 173 * @stream: DC stream associated with the crtc 174 * @adjust: DC CRTC timing adjust to be applied to the crtc 175 */ 176 struct vupdate_offload_work { 177 struct work_struct work; 178 struct amdgpu_device *adev; 179 struct dc_stream_state *stream; 180 struct dc_crtc_timing_adjust *adjust; 181 }; 182 183 #define MAX_LUMINANCE_DATA_POINTS 99 184 185 /** 186 * struct amdgpu_dm_luminance_data - Custom luminance data 187 * @luminance: Luminance in percent 188 * @input_signal: Input signal in range 0-255 189 */ 190 struct amdgpu_dm_luminance_data { 191 u8 luminance; 192 u8 input_signal; 193 } __packed; 194 195 /** 196 * struct amdgpu_dm_backlight_caps - Information about backlight 197 * 198 * Describe the backlight support for ACPI or eDP AUX. 199 */ 200 struct amdgpu_dm_backlight_caps { 201 /** 202 * @ext_caps: Keep the data struct with all the information about the 203 * display support for HDR. 204 */ 205 union dpcd_sink_ext_caps *ext_caps; 206 /** 207 * @aux_min_input_signal: Min brightness value supported by the display 208 */ 209 u32 aux_min_input_signal; 210 /** 211 * @aux_max_input_signal: Max brightness value supported by the display 212 * in nits. 213 */ 214 u32 aux_max_input_signal; 215 /** 216 * @min_input_signal: minimum possible input in range 0-255. 217 */ 218 int min_input_signal; 219 /** 220 * @max_input_signal: maximum possible input in range 0-255. 221 */ 222 int max_input_signal; 223 /** 224 * @caps_valid: true if these values are from the ACPI interface. 225 */ 226 bool caps_valid; 227 /** 228 * @aux_support: Describes if the display supports AUX backlight. 229 */ 230 bool aux_support; 231 /** 232 * @brightness_mask: After deriving brightness, OR it with this mask. 233 * Workaround for panels with issues with certain brightness values. 234 */ 235 u32 brightness_mask; 236 /** 237 * @ac_level: the default brightness if booted on AC 238 */ 239 u8 ac_level; 240 /** 241 * @dc_level: the default brightness if booted on DC 242 */ 243 u8 dc_level; 244 /** 245 * @data_points: the number of custom luminance data points 246 */ 247 u8 data_points; 248 /** 249 * @luminance_data: custom luminance data 250 */ 251 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 252 }; 253 254 /** 255 * struct dal_allocation - Tracks mapped FB memory for SMU communication 256 * @list: list of dal allocations 257 * @bo: GPU buffer object 258 * @cpu_ptr: CPU virtual address of the GPU buffer object 259 * @gpu_addr: GPU virtual address of the GPU buffer object 260 */ 261 struct dal_allocation { 262 struct list_head list; 263 struct amdgpu_bo *bo; 264 void *cpu_ptr; 265 u64 gpu_addr; 266 }; 267 268 /** 269 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 270 * offload work 271 */ 272 struct hpd_rx_irq_offload_work_queue { 273 /** 274 * @wq: workqueue structure to queue offload work. 275 */ 276 struct workqueue_struct *wq; 277 /** 278 * @offload_lock: To protect fields of offload work queue. 279 */ 280 spinlock_t offload_lock; 281 /** 282 * @is_handling_link_loss: Used to prevent inserting link loss event when 283 * we're handling link loss 284 */ 285 bool is_handling_link_loss; 286 /** 287 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 288 * ready event when we're already handling mst message ready event 289 */ 290 bool is_handling_mst_msg_rdy_event; 291 /** 292 * @aconnector: The aconnector that this work queue is attached to 293 */ 294 struct amdgpu_dm_connector *aconnector; 295 }; 296 297 /** 298 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 299 */ 300 struct hpd_rx_irq_offload_work { 301 /** 302 * @work: offload work 303 */ 304 struct work_struct work; 305 /** 306 * @data: reference irq data which is used while handling offload work 307 */ 308 union hpd_irq_data data; 309 /** 310 * @offload_wq: offload work queue that this work is queued to 311 */ 312 struct hpd_rx_irq_offload_work_queue *offload_wq; 313 /** 314 * @adev: amdgpu_device pointer 315 */ 316 struct amdgpu_device *adev; 317 }; 318 319 /** 320 * struct amdgpu_display_manager - Central amdgpu display manager device 321 * 322 * @dc: Display Core control structure 323 * @adev: AMDGPU base driver structure 324 * @ddev: DRM base driver structure 325 * @display_indexes_num: Max number of display streams supported 326 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 327 * @backlight_dev: Backlight control device 328 * @backlight_link: Link on which to control backlight 329 * @backlight_caps: Capabilities of the backlight device 330 * @freesync_module: Module handling freesync calculations 331 * @hdcp_workqueue: AMDGPU content protection queue 332 * @fw_dmcu: Reference to DMCU firmware 333 * @dmcu_fw_version: Version of the DMCU firmware 334 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 335 * @cached_state: Caches device atomic state for suspend/resume 336 * @cached_dc_state: Cached state of content streams 337 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 338 * @force_timing_sync: set via debugfs. When set, indicates that all connected 339 * displays will be forced to synchronize. 340 * @dmcub_trace_event_en: enable dmcub trace events 341 * @dmub_outbox_params: DMUB Outbox parameters 342 * @num_of_edps: number of backlight eDPs 343 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 344 * driver when true 345 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 346 * transfers are done 347 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 348 */ 349 struct amdgpu_display_manager { 350 351 struct dc *dc; 352 353 /** 354 * @dmub_srv: 355 * 356 * DMUB service, used for controlling the DMUB on hardware 357 * that supports it. The pointer to the dmub_srv will be 358 * NULL on hardware that does not support it. 359 */ 360 struct dmub_srv *dmub_srv; 361 362 /** 363 * @dmub_notify: 364 * 365 * Notification from DMUB. 366 */ 367 368 struct dmub_notification *dmub_notify; 369 370 /** 371 * @dmub_callback: 372 * 373 * Callback functions to handle notification from DMUB. 374 */ 375 376 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 377 378 /** 379 * @dmub_thread_offload: 380 * 381 * Flag to indicate if callback is offload. 382 */ 383 384 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 385 386 /** 387 * @dmub_fb_info: 388 * 389 * Framebuffer regions for the DMUB. 390 */ 391 struct dmub_srv_fb_info *dmub_fb_info; 392 393 /** 394 * @dmub_fw: 395 * 396 * DMUB firmware, required on hardware that has DMUB support. 397 */ 398 const struct firmware *dmub_fw; 399 400 /** 401 * @dmub_bo: 402 * 403 * Buffer object for the DMUB. 404 */ 405 struct amdgpu_bo *dmub_bo; 406 407 /** 408 * @dmub_bo_gpu_addr: 409 * 410 * GPU virtual address for the DMUB buffer object. 411 */ 412 u64 dmub_bo_gpu_addr; 413 414 /** 415 * @dmub_bo_cpu_addr: 416 * 417 * CPU address for the DMUB buffer object. 418 */ 419 void *dmub_bo_cpu_addr; 420 421 /** 422 * @dmcub_fw_version: 423 * 424 * DMCUB firmware version. 425 */ 426 uint32_t dmcub_fw_version; 427 428 /** 429 * @fw_inst_size: 430 * 431 * Size of the firmware instruction buffer. 432 */ 433 uint32_t fw_inst_size; 434 435 /** 436 * @cgs_device: 437 * 438 * The Common Graphics Services device. It provides an interface for 439 * accessing registers. 440 */ 441 struct cgs_device *cgs_device; 442 443 struct amdgpu_device *adev; 444 struct drm_device *ddev; 445 u16 display_indexes_num; 446 447 /** 448 * @atomic_obj: 449 * 450 * In combination with &dm_atomic_state it helps manage 451 * global atomic state that doesn't map cleanly into existing 452 * drm resources, like &dc_context. 453 */ 454 struct drm_private_obj atomic_obj; 455 456 /** 457 * @dc_lock: 458 * 459 * Guards access to DC functions that can issue register write 460 * sequences. 461 */ 462 struct mutex dc_lock; 463 464 /** 465 * @dmub_lock: 466 * 467 * Guards access to DMUB command submission. 468 */ 469 spinlock_t dmub_lock; 470 471 /** 472 * @audio_lock: 473 * 474 * Guards access to audio instance changes. 475 */ 476 struct mutex audio_lock; 477 478 /** 479 * @audio_component: 480 * 481 * Used to notify ELD changes to sound driver. 482 */ 483 struct drm_audio_component *audio_component; 484 485 /** 486 * @audio_registered: 487 * 488 * True if the audio component has been registered 489 * successfully, false otherwise. 490 */ 491 bool audio_registered; 492 493 /** 494 * @irq_handler_list_low_tab: 495 * 496 * Low priority IRQ handler table. 497 * 498 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 499 * source. Low priority IRQ handlers are deferred to a workqueue to be 500 * processed. Hence, they can sleep. 501 * 502 * Note that handlers are called in the same order as they were 503 * registered (FIFO). 504 */ 505 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 506 507 /** 508 * @irq_handler_list_high_tab: 509 * 510 * High priority IRQ handler table. 511 * 512 * It is a n*m table, same as &irq_handler_list_low_tab. However, 513 * handlers in this table are not deferred and are called immediately. 514 */ 515 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 516 517 /** 518 * @pflip_params: 519 * 520 * Page flip IRQ parameters, passed to registered handlers when 521 * triggered. 522 */ 523 struct common_irq_params 524 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 525 526 /** 527 * @vblank_params: 528 * 529 * Vertical blanking IRQ parameters, passed to registered handlers when 530 * triggered. 531 */ 532 struct common_irq_params 533 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 534 535 /** 536 * @vline0_params: 537 * 538 * OTG vertical interrupt0 IRQ parameters, passed to registered 539 * handlers when triggered. 540 */ 541 struct common_irq_params 542 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 543 544 /** 545 * @vupdate_params: 546 * 547 * Vertical update IRQ parameters, passed to registered handlers when 548 * triggered. 549 */ 550 struct common_irq_params 551 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 552 553 /** 554 * @dmub_trace_params: 555 * 556 * DMUB trace event IRQ parameters, passed to registered handlers when 557 * triggered. 558 */ 559 struct common_irq_params 560 dmub_trace_params[1]; 561 562 struct common_irq_params 563 dmub_outbox_params[1]; 564 565 spinlock_t irq_handler_list_table_lock; 566 567 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 568 569 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 570 571 uint8_t num_of_edps; 572 573 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 574 575 struct mod_freesync *freesync_module; 576 struct mod_power *power_module; 577 struct hdcp_workqueue *hdcp_workqueue; 578 579 /** 580 * @vblank_control_workqueue: 581 * 582 * Deferred work for vblank control events. 583 */ 584 struct workqueue_struct *vblank_control_workqueue; 585 586 /** 587 * @idle_workqueue: 588 * 589 * Periodic work for idle events. 590 */ 591 struct idle_workqueue *idle_workqueue; 592 593 struct drm_atomic_commit *cached_state; 594 struct dc_state *cached_dc_state; 595 596 struct dm_compressor_info compressor; 597 598 const struct firmware *fw_dmcu; 599 uint32_t dmcu_fw_version; 600 /** 601 * @soc_bounding_box: 602 * 603 * gpu_info FW provided soc bounding box struct or 0 if not 604 * available in FW 605 */ 606 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 607 608 /** 609 * @active_vblank_irq_count: 610 * 611 * number of currently active vblank irqs 612 */ 613 uint32_t active_vblank_irq_count; 614 615 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 616 /** 617 * @secure_display_ctx: 618 * 619 * Store secure display relevant info. e.g. the ROI information 620 * , the work_struct to command dmub, etc. 621 */ 622 struct secure_display_context secure_display_ctx; 623 #endif 624 /** 625 * @hpd_rx_offload_wq: 626 * 627 * Work queue to offload works of hpd_rx_irq 628 */ 629 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 630 /** 631 * @mst_encoders: 632 * 633 * fake encoders used for DP MST. 634 */ 635 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 636 bool force_timing_sync; 637 bool disable_hpd_irq; 638 bool dmcub_trace_event_en; 639 /** 640 * @da_list: 641 * 642 * DAL fb memory allocation list, for communication with SMU. 643 */ 644 struct list_head da_list; 645 struct completion dmub_aux_transfer_done; 646 struct workqueue_struct *delayed_hpd_wq; 647 648 /** 649 * @brightness: 650 * 651 * cached backlight values. 652 */ 653 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 654 /** 655 * @actual_brightness: 656 * 657 * last successfully applied backlight values. 658 */ 659 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 660 661 /** 662 * @aux_hpd_discon_quirk: 663 * 664 * quirk for hpd discon while aux is on-going. 665 * occurred on certain intel platform 666 */ 667 bool aux_hpd_discon_quirk; 668 669 /** 670 * @edp0_on_dp1_quirk: 671 * 672 * quirk for platforms that put edp0 on DP1. 673 */ 674 bool edp0_on_dp1_quirk; 675 676 /** 677 * @dpia_aux_lock: 678 * 679 * Guards access to DPIA AUX 680 */ 681 struct mutex dpia_aux_lock; 682 683 /** 684 * @bb_from_dmub: 685 * 686 * Bounding box data read from dmub during early initialization for DCN4+ 687 * Data is stored as a byte array that should be casted to the appropriate bb struct 688 */ 689 void *bb_from_dmub; 690 691 /** 692 * @oem_i2c: 693 * 694 * OEM i2c bus 695 */ 696 struct amdgpu_i2c_adapter *oem_i2c; 697 698 /** 699 * @fused_io: 700 * 701 * dmub fused io interface 702 */ 703 struct fused_io_sync { 704 struct completion replied; 705 char reply_data[0x40]; // Cannot include dmub_cmd here 706 } fused_io[8]; 707 /** 708 * @hdmi_frl_status_polling_work: 709 * 710 * workqueue for 200ms frl status polling 711 */ 712 struct workqueue_struct *hdmi_frl_status_polling_wq; 713 struct delayed_work hdmi_frl_status_polling_work; 714 unsigned int hdmi_frl_status_polling_delay_ms; 715 716 /** 717 * @dm_boot_time_crc_info: 718 * 719 * Buffer info for the boot time crc. 720 */ 721 struct dm_boot_time_crc_info boot_time_crc_info; 722 }; 723 724 enum dsc_clock_force_state { 725 DSC_CLK_FORCE_DEFAULT = 0, 726 DSC_CLK_FORCE_ENABLE, 727 DSC_CLK_FORCE_DISABLE, 728 }; 729 730 struct dsc_preferred_settings { 731 enum dsc_clock_force_state dsc_force_enable; 732 uint32_t dsc_num_slices_v; 733 uint32_t dsc_num_slices_h; 734 uint32_t dsc_bits_per_pixel; 735 bool dsc_force_disable_passthrough; 736 }; 737 738 enum mst_progress_status { 739 MST_STATUS_DEFAULT = 0, 740 MST_PROBE = BIT(0), 741 MST_REMOTE_EDID = BIT(1), 742 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 743 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 744 }; 745 746 /** 747 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 748 * 749 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 750 * struct is useful to keep track of the display-specific information about 751 * FreeSync. 752 */ 753 struct amdgpu_hdmi_vsdb_info { 754 /** 755 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 756 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 757 */ 758 unsigned int amd_vsdb_version; 759 760 /** 761 * @freesync_supported: FreeSync Supported. 762 */ 763 bool freesync_supported; 764 765 /** 766 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 767 */ 768 unsigned int min_refresh_rate_hz; 769 770 /** 771 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 772 */ 773 unsigned int max_refresh_rate_hz; 774 775 /** 776 * @freesync_mccs_vcp_code: MCCS VCP code for freesync state 777 */ 778 unsigned int freesync_mccs_vcp_code; 779 780 /** 781 * @replay_mode: Replay supported 782 */ 783 bool replay_mode; 784 }; 785 786 struct amdgpu_dm_connector { 787 788 struct drm_connector base; 789 uint32_t connector_id; 790 int bl_idx; 791 792 struct cec_notifier *notifier; 793 794 /* we need to mind the EDID between detect 795 and get modes due to analog/digital/tvencoder */ 796 const struct drm_edid *drm_edid; 797 798 /* shared with amdgpu */ 799 struct amdgpu_hpd hpd; 800 801 /* number of modes generated from EDID at 'dc_sink' */ 802 int num_modes; 803 804 /* The 'old' sink - before an HPD. 805 * The 'current' sink is in dc_link->sink. */ 806 struct dc_sink *dc_sink; 807 struct dc_link *dc_link; 808 809 /** 810 * @dc_em_sink: Reference to the emulated (virtual) sink. 811 */ 812 struct dc_sink *dc_em_sink; 813 814 /* DM only */ 815 struct drm_dp_mst_topology_mgr mst_mgr; 816 struct amdgpu_dm_dp_aux dm_dp_aux; 817 struct drm_dp_mst_port *mst_output_port; 818 struct amdgpu_dm_connector *mst_root; 819 struct drm_dp_aux *dsc_aux; 820 uint32_t mst_local_bw; 821 uint16_t vc_full_pbn; 822 struct mutex handle_mst_msg_ready; 823 824 /* branch device specific data */ 825 uint32_t branch_ieee_oui; 826 827 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 828 struct amdgpu_i2c_adapter *i2c; 829 830 /* Monitor range limits */ 831 /** 832 * @min_vfreq: Minimal frequency supported by the display in Hz. This 833 * value is set to zero when there is no FreeSync support. 834 */ 835 int min_vfreq; 836 837 /** 838 * @max_vfreq: Maximum frequency supported by the display in Hz. This 839 * value is set to zero when there is no FreeSync support. 840 */ 841 int max_vfreq ; 842 843 /* Audio instance - protected by audio_lock. */ 844 int audio_inst; 845 846 struct mutex hpd_lock; 847 848 bool fake_enable; 849 bool force_yuv420_output; 850 bool force_yuv422_output; 851 uint8_t force_yuv_pixel_format; 852 struct dsc_preferred_settings dsc_settings; 853 struct psr_caps psr_caps; 854 union dp_downstream_port_present mst_downstream_port_present; 855 /* Cached display modes */ 856 struct drm_display_mode freesync_vid_base; 857 858 int sr_skip_count; 859 bool disallow_edp_enter_psr; 860 bool disallow_edp_enter_replay; 861 862 union dwnstream_portxcaps mst_downstream_port_caps; 863 864 /* Record progress status of mst*/ 865 uint8_t mst_status; 866 867 /* Automated testing */ 868 bool timing_changed; 869 struct dc_crtc_timing *timing_requested; 870 871 /* Adaptive Sync */ 872 bool pack_sdp_v1_3; 873 enum adaptive_sync_type as_type; 874 struct amdgpu_hdmi_vsdb_info vsdb_info; 875 876 /* HDMI HPD debounce support */ 877 unsigned int hdmi_hpd_debounce_delay_ms; 878 struct delayed_work hdmi_hpd_debounce_work; 879 struct dc_sink *hdmi_prev_sink; 880 }; 881 882 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 883 uint8_t flags, bool set) 884 { 885 if (set) 886 *status |= flags; 887 else 888 *status &= ~flags; 889 } 890 891 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 892 893 struct amdgpu_dm_wb_connector { 894 struct drm_writeback_connector base; 895 struct dc_link *link; 896 }; 897 898 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 899 900 extern const struct amdgpu_ip_block_version dm_ip_block; 901 902 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 903 * 904 * It includes standardized transfer functions and pure power functions. The 905 * transfer function coefficients are available at modules/color/color_gamma.c 906 */ 907 enum amdgpu_transfer_function { 908 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 909 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 910 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 911 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 912 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 913 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 914 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 915 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 916 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 917 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 918 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 919 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 920 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 921 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 922 AMDGPU_TRANSFER_FUNCTION_COUNT 923 }; 924 925 struct dm_plane_state { 926 struct drm_plane_state base; 927 struct dc_plane_state *dc_state; 928 929 /* Plane color mgmt */ 930 /** 931 * @degamma_lut: 932 * 933 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 934 * blending operations. It's usually applied to linearize input space. 935 * The blob (if not NULL) is an array of &struct drm_color_lut. 936 */ 937 struct drm_property_blob *degamma_lut; 938 /** 939 * @degamma_tf: 940 * 941 * Predefined transfer function to tell DC driver the input space to 942 * linearize. 943 */ 944 enum amdgpu_transfer_function degamma_tf; 945 /** 946 * @hdr_mult: 947 * 948 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 949 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 950 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 951 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 952 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 953 * S31.32 sign-magnitude. 954 * 955 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 956 * TF is needed for any subsequent linear-to-non-linear transforms. 957 */ 958 __u64 hdr_mult; 959 /** 960 * @ctm: 961 * 962 * Color transformation matrix. The blob (if not NULL) is a &struct 963 * drm_color_ctm_3x4. 964 */ 965 struct drm_property_blob *ctm; 966 /** 967 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 968 * array of &struct drm_color_lut. 969 */ 970 struct drm_property_blob *shaper_lut; 971 /** 972 * @shaper_tf: 973 * 974 * Predefined transfer function to delinearize color space. 975 */ 976 enum amdgpu_transfer_function shaper_tf; 977 /** 978 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 979 * &struct drm_color_lut. 980 */ 981 struct drm_property_blob *lut3d; 982 /** 983 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 984 * array of &struct drm_color_lut. 985 */ 986 struct drm_property_blob *blend_lut; 987 /** 988 * @blend_tf: 989 * 990 * Pre-defined transfer function for converting plane pixel data before 991 * applying blend LUT. 992 */ 993 enum amdgpu_transfer_function blend_tf; 994 }; 995 996 enum amdgpu_dm_cursor_mode { 997 DM_CURSOR_NATIVE_MODE = 0, 998 DM_CURSOR_OVERLAY_MODE, 999 }; 1000 1001 struct dm_crtc_state { 1002 struct drm_crtc_state base; 1003 struct dc_stream_state *stream; 1004 1005 bool cm_has_degamma; 1006 bool cm_is_degamma_srgb; 1007 1008 bool mpo_requested; 1009 1010 int update_type; 1011 int active_planes; 1012 1013 int crc_skip_count; 1014 1015 bool freesync_vrr_info_changed; 1016 1017 bool mode_changed_independent_from_dsc; 1018 bool dsc_force_changed; 1019 bool vrr_supported; 1020 struct mod_freesync_config freesync_config; 1021 struct dc_info_packet vrr_infopacket; 1022 1023 int abm_level; 1024 1025 /** 1026 * @regamma_tf: 1027 * 1028 * Pre-defined transfer function for converting internal FB -> wire 1029 * encoding. 1030 */ 1031 enum amdgpu_transfer_function regamma_tf; 1032 1033 enum amdgpu_dm_cursor_mode cursor_mode; 1034 }; 1035 1036 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 1037 1038 struct dm_atomic_state { 1039 struct drm_private_state base; 1040 1041 struct dc_state *context; 1042 }; 1043 1044 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 1045 1046 struct dm_connector_state { 1047 struct drm_connector_state base; 1048 1049 enum amdgpu_rmx_type scaling; 1050 uint8_t underscan_vborder; 1051 uint8_t underscan_hborder; 1052 bool underscan_enable; 1053 bool freesync_capable; 1054 bool update_hdcp; 1055 bool abm_sysfs_forbidden; 1056 uint8_t abm_level; 1057 int vcpi_slots; 1058 uint64_t pbn; 1059 }; 1060 1061 #define to_dm_connector_state(x)\ 1062 container_of((x), struct dm_connector_state, base) 1063 1064 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 1065 struct drm_connector_state * 1066 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 1067 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 1068 struct drm_connector_state *state, 1069 struct drm_property *property, 1070 uint64_t val); 1071 1072 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 1073 const struct drm_connector_state *state, 1074 struct drm_property *property, 1075 uint64_t *val); 1076 1077 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 1078 1079 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 1080 struct amdgpu_dm_connector *aconnector, 1081 int connector_type, 1082 struct dc_link *link, 1083 int link_index); 1084 1085 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 1086 const struct drm_display_mode *mode); 1087 1088 void dm_restore_drm_connector_state(struct drm_device *dev, 1089 struct drm_connector *connector); 1090 1091 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 1092 const struct drm_edid *drm_edid, bool do_mccs); 1093 1094 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 1095 1096 /* 3D LUT max size is 17x17x17 (4913 entries) */ 1097 #define MAX_COLOR_3DLUT_SIZE 17 1098 #define MAX_COLOR_3DLUT_BITDEPTH 12 1099 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 1100 struct drm_plane_state *plane_state); 1101 /* 1D LUT size */ 1102 #define MAX_COLOR_LUT_ENTRIES 4096 1103 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1104 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1105 1106 void amdgpu_dm_init_color_mod(void); 1107 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1108 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1109 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1110 int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, 1111 bool check_only); 1112 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1113 struct drm_plane_state *plane_state, 1114 struct dc_plane_state *dc_plane_state); 1115 1116 void amdgpu_dm_update_connector_after_detect( 1117 struct amdgpu_dm_connector *aconnector); 1118 1119 void populate_hdmi_info_from_connector(bool enable_frl, struct drm_hdmi_info *info, 1120 struct dc_edid_caps *edid_caps); 1121 1122 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 1123 1124 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1125 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1126 1127 bool amdgpu_dm_execute_fused_io( 1128 struct amdgpu_device *dev, 1129 struct dc_link *link, 1130 union dmub_rb_cmd *commands, 1131 uint8_t count, 1132 uint32_t timeout_us 1133 ); 1134 1135 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1136 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1137 1138 struct dc_stream_state * 1139 create_validate_stream_for_sink(struct drm_connector *connector, 1140 const struct drm_display_mode *drm_mode, 1141 const struct dm_connector_state *dm_state, 1142 const struct dc_stream_state *old_stream); 1143 1144 int dm_atomic_get_state(struct drm_atomic_commit *state, 1145 struct dm_atomic_state **dm_state); 1146 1147 struct drm_connector * 1148 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_commit *state, 1149 struct drm_crtc *crtc); 1150 1151 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 1152 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1153 1154 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1155 enum dc_gpu_mem_alloc_type type, 1156 size_t size, 1157 long long *addr); 1158 void dm_free_gpu_mem(struct amdgpu_device *adev, 1159 enum dc_gpu_mem_alloc_type type, 1160 void *addr); 1161 1162 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1163 1164 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector); 1165 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector); 1166 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); 1167 1168 void retrieve_dmi_info(struct amdgpu_display_manager *dm); 1169 1170 void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, int bl_idx); 1171 #endif /* __AMDGPU_DM_H__ */ 1172