1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // ALSA SoC Texas Instruments TAC5XX2 Audio Smart Amplifier 4 // 5 // Copyright (C) 2025 Texas Instruments Incorporated 6 // https://www.ti.com 7 // 8 // Author: Niranjan H Y <niranjan.hy@ti.com> 9 10 #include <linux/err.h> 11 #include <linux/firmware.h> 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/pm.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/soundwire/sdw.h> 19 #include <linux/soundwire/sdw_registers.h> 20 #include <linux/soundwire/sdw_type.h> 21 #include <linux/time.h> 22 #include <linux/unaligned.h> 23 #include <sound/pcm_params.h> 24 #include <sound/sdw.h> 25 #include <sound/soc.h> 26 #include <sound/tlv.h> 27 #include <sound/sdca_asoc.h> 28 #include <sound/sdca_function.h> 29 #include <sound/sdca_regmap.h> 30 #include <sound/jack.h> 31 32 #include "tac5xx2.h" 33 34 #define TAC5XX2_PROBE_TIMEOUT_MS 3000 35 #define TAC5XX2_FW_CACHE_TIMEOUT_MS 300 36 37 #define TAC5XX2_DEVICE_RATES (SNDRV_PCM_RATE_44100 | \ 38 SNDRV_PCM_RATE_48000 | \ 39 SNDRV_PCM_RATE_96000 | \ 40 SNDRV_PCM_RATE_88200) 41 #define TAC5XX2_DEVICE_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 42 SNDRV_PCM_FMTBIT_S24_LE | \ 43 SNDRV_PCM_FMTBIT_S32_LE) 44 /* Define channel constants */ 45 #define TAC_CHANNEL_LEFT 1 46 #define TAC_CHANNEL_RIGHT 2 47 #define TAC_JACK_MONO_CS 2 48 49 #define TAC_MUTE_REG(func, fu, ch) \ 50 SDW_SDCA_CTL(TAC_FUNCTION_ID_##func, TAC_SDCA_ENT_##fu, \ 51 TAC_SDCA_CHANNEL_MUTE, TAC_CHANNEL_##ch) 52 #define TAC_USAGE_REG(func, ent) \ 53 SDW_SDCA_CTL(TAC_FUNCTION_ID_##func, TAC_SDCA_ENT_##ent, \ 54 TAC_SDCA_CTL_USAGE, 0) 55 #define TAC_XU_BYPASS_REG(func, xu) \ 56 SDW_SDCA_CTL(TAC_FUNCTION_ID_##func, TAC_SDCA_ENT_##xu, \ 57 TAC_SDCA_CTL_XU_BYPASS, 0) 58 #define TAC_VOLUME_REG(func, fu, ch) \ 59 SDW_SDCA_CTL(TAC_FUNCTION_ID_##func, TAC_SDCA_ENT_##fu, \ 60 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_##ch) 61 #define TAC_GAIN_REG(func, fu, ch) \ 62 SDW_SDCA_CTL(TAC_FUNCTION_ID_##func, TAC_SDCA_ENT_##fu, \ 63 TAC_SDCA_CHANNEL_GAIN, TAC_CHANNEL_##ch) 64 65 /* mute registers */ 66 #define FU21_L_MUTE_REG TAC_MUTE_REG(SA, FU21, LEFT) 67 #define FU21_R_MUTE_REG TAC_MUTE_REG(SA, FU21, RIGHT) 68 #define FU23_L_MUTE_REG TAC_MUTE_REG(SA, FU23, LEFT) 69 #define FU23_R_MUTE_REG TAC_MUTE_REG(SA, FU23, RIGHT) 70 #define FU26_MUTE_REG TAC_MUTE_REG(SA, FU26, LEFT) 71 #define FU11_L_MUTE_REG TAC_MUTE_REG(SM, FU11, LEFT) 72 #define FU11_R_MUTE_REG TAC_MUTE_REG(SM, FU11, RIGHT) 73 #define FU113_L_MUTE_REG TAC_MUTE_REG(SM, FU113, LEFT) 74 #define FU113_R_MUTE_REG TAC_MUTE_REG(SM, FU113, RIGHT) 75 #define FU41_L_MUTE_REG TAC_MUTE_REG(UAJ, FU41, LEFT) 76 #define FU41_R_MUTE_REG TAC_MUTE_REG(UAJ, FU41, RIGHT) 77 #define FU36_MUTE_REG TAC_MUTE_REG(UAJ, FU36, RIGHT) 78 79 /* it/ot usage */ 80 #define IT11_USAGE_REG TAC_USAGE_REG(SM, IT11) 81 #define IT41_USAGE_REG TAC_USAGE_REG(UAJ, IT41) 82 #define IT33_USAGE_REG TAC_USAGE_REG(UAJ, IT33) 83 #define OT113_USAGE_REG TAC_USAGE_REG(SM, OT113) 84 #define OT45_USAGE_REG TAC_USAGE_REG(UAJ, OT45) 85 #define OT36_USAGE_REG TAC_USAGE_REG(UAJ, OT36) 86 87 /* xu bypass */ 88 #define XU12_BYPASS_REG TAC_XU_BYPASS_REG(SM, XU12) 89 #define XU42_BYPASS_REG TAC_XU_BYPASS_REG(UAJ, XU42) 90 91 #define TAC_DSP_ALGO_STATUS TAC_REG_SDW(0, 3, 12) 92 #define TAC_DSP_ALGO_STATUS_RUNNING 0x20 93 #define TAC_FW_HDR_SIZE 88 94 #define TAC_FW_FILE_HDR 20 95 #define TAC_MAX_FW_CHUNKS 512 96 97 #define TAC_UAJ_PREP_CONNECTED 0xff 98 #define TAC_UAJ_PREP_DISCONNECTED 0xdf 99 100 struct tac_fw_hdr { 101 u32 size; 102 u32 version_offset; 103 u32 plt_id; 104 u32 ppc3_ver; 105 u64 timestamp; 106 u8 ddc_name[64]; 107 }; 108 109 /* Firmware file/chunk structure */ 110 struct tac_fw_file { 111 u32 vendor_id; 112 u32 file_id; 113 u32 version; 114 u32 length; 115 u32 dest_addr; 116 u8 *fw_data; 117 }; 118 119 /* TLV for volume control */ 120 static const DECLARE_TLV_DB_SCALE(tac5xx2_amp_tlv, 0, 50, 0); 121 static const DECLARE_TLV_DB_SCALE(tac5xx2_dvc_tlv, -7200, 50, 0); 122 123 /* Q7.8 volume control parameters: range -72dB to +6dB, step 0.5dB */ 124 #define TAC_DVC_STEP 128 /* 0.5 dB in Q7.8 format */ 125 #define TAC_DVC_MIN (-144) /* -72 dB / 0.5 dB step */ 126 #define TAC_DVC_MAX 12 /* +6 dB / 0.5 dB step */ 127 128 /* TAC-specific stereo volume control macro using SDW_SDCA_CTL (single control for L/R) */ 129 #define TAC_DOUBLE_Q78_TLV(name, func_id, ent_id) \ 130 SDCA_DOUBLE_Q78_TLV(name, \ 131 SDW_SDCA_CTL(TAC_FUNCTION_ID_##func_id, TAC_SDCA_ENT_##ent_id, \ 132 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_LEFT), \ 133 SDW_SDCA_CTL(TAC_FUNCTION_ID_##func_id, TAC_SDCA_ENT_##ent_id, \ 134 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_RIGHT), \ 135 TAC_DVC_MIN, TAC_DVC_MAX, TAC_DVC_STEP, tac5xx2_dvc_tlv) 136 137 struct tac5xx2_prv { 138 struct snd_soc_component *component; 139 struct sdw_slave *sdw_peripheral; 140 struct sdca_function_data *sa_func_data; 141 struct sdca_function_data *sm_func_data; 142 struct sdca_function_data *uaj_func_data; 143 struct sdca_function_data *hid_func_data; 144 enum sdw_slave_status status; 145 struct regmap *regmap; 146 struct device *dev; 147 bool hw_init; 148 bool first_hw_init_done; 149 u32 part_id; 150 u32 rev_id; 151 struct snd_soc_jack *hs_jack; 152 int jack_type; 153 /* Custom fw binary. UMP File Download is not used. */ 154 unsigned int fw_file_cnt; 155 struct tac_fw_file *fw_files; 156 struct completion fw_caching_complete; 157 bool fw_dl_success; 158 u8 fw_binaryname[64]; 159 }; 160 161 static const struct reg_default tac_reg_default[] = { 162 {TAC_SW_RESET, 0x0}, 163 {TAC_SLEEP_MODEZ, 0x0}, 164 {TAC_FEATURE_PDZ, 0x0}, 165 {TAC_TX_CH_EN, 0xf0}, 166 {TAC_REG_SDW(0, 0, 0x5), 0xcf}, 167 {TAC_REG_SDW(0, 0, 0x6), 0xa}, 168 {TAC_REG_SDW(0, 0, 0x7), 0x0}, 169 {TAC_REG_SDW(0, 0, 0x8), 0xfe}, 170 {TAC_REG_SDW(0, 0, 0x9), 0x9}, 171 {TAC_REG_SDW(0, 0, 0xa), 0x28}, 172 {TAC_REG_SDW(0, 0, 0xb), 0x1}, 173 {TAC_REG_SDW(0, 0, 0xc), 0x11}, 174 {TAC_REG_SDW(0, 0, 0xd), 0x11}, 175 {TAC_REG_SDW(0, 0, 0xe), 0x61}, 176 {TAC_REG_SDW(0, 0, 0xf), 0x0}, 177 {TAC_REG_SDW(0, 0, 0x10), 0x50}, 178 {TAC_REG_SDW(0, 0, 0x11), 0x70}, 179 {TAC_REG_SDW(0, 0, 0x12), 0x60}, 180 {TAC_REG_SDW(0, 0, 0x13), 0x28}, 181 {TAC_REG_SDW(0, 0, 0x14), 0x0}, 182 {TAC_REG_SDW(0, 0, 0x15), 0x18}, 183 {TAC_REG_SDW(0, 0, 0x16), 0x20}, 184 {TAC_REG_SDW(0, 0, 0x17), 0x0}, 185 {TAC_REG_SDW(0, 0, 0x18), 0x18}, 186 {TAC_REG_SDW(0, 0, 0x19), 0x54}, 187 {TAC_REG_SDW(0, 0, 0x1a), 0x8}, 188 {TAC_REG_SDW(0, 0, 0x1b), 0x0}, 189 {TAC_REG_SDW(0, 0, 0x1c), 0x30}, 190 {TAC_REG_SDW(0, 0, 0x1d), 0x0}, 191 {TAC_REG_SDW(0, 0, 0x1e), 0x0}, 192 {TAC_REG_SDW(0, 0, 0x1f), 0x0}, 193 {TAC_REG_SDW(0, 0, 0x20), 0x0}, 194 {TAC_REG_SDW(0, 0, 0x21), 0x20}, 195 {TAC_REG_SDW(0, 0, 0x22), 0x21}, 196 {TAC_REG_SDW(0, 0, 0x23), 0x22}, 197 {TAC_REG_SDW(0, 0, 0x24), 0x23}, 198 {TAC_REG_SDW(0, 0, 0x25), 0x4}, 199 {TAC_REG_SDW(0, 0, 0x26), 0x5}, 200 {TAC_REG_SDW(0, 0, 0x27), 0x6}, 201 {TAC_REG_SDW(0, 0, 0x28), 0x7}, 202 {TAC_REG_SDW(0, 0, 0x29), 0x0}, 203 {TAC_REG_SDW(0, 0, 0x2a), 0x0}, 204 {TAC_REG_SDW(0, 0, 0x2b), 0x0}, 205 {TAC_REG_SDW(0, 0, 0x2c), 0x20}, 206 {TAC_REG_SDW(0, 0, 0x2d), 0x21}, 207 {TAC_REG_SDW(0, 0, 0x2e), 0x2}, 208 {TAC_REG_SDW(0, 0, 0x2f), 0x3}, 209 {TAC_REG_SDW(0, 0, 0x30), 0x4}, 210 {TAC_REG_SDW(0, 0, 0x31), 0x5}, 211 {TAC_REG_SDW(0, 0, 0x32), 0x6}, 212 {TAC_REG_SDW(0, 0, 0x33), 0x7}, 213 {TAC_REG_SDW(0, 0, 0x34), 0x0}, 214 {TAC_REG_SDW(0, 0, 0x35), 0x90}, 215 {TAC_REG_SDW(0, 0, 0x36), 0x80}, 216 {TAC_REG_SDW(0, 0, 0x37), 0x0}, 217 {TAC_REG_SDW(0, 0, 0x39), 0x0}, 218 {TAC_REG_SDW(0, 0, 0x3a), 0x90}, 219 {TAC_REG_SDW(0, 0, 0x3b), 0x80}, 220 {TAC_REG_SDW(0, 0, 0x3c), 0x0}, 221 {TAC_REG_SDW(0, 0, 0x3e), 0x0}, 222 {TAC_REG_SDW(0, 0, 0x3f), 0x90}, 223 {TAC_REG_SDW(0, 0, 0x40), 0x80}, 224 {TAC_REG_SDW(0, 0, 0x41), 0x0}, 225 {TAC_REG_SDW(0, 0, 0x43), 0x90}, 226 {TAC_REG_SDW(0, 0, 0x44), 0x80}, 227 {TAC_REG_SDW(0, 0, 0x45), 0x0}, 228 {TAC_REG_SDW(0, 0, 0x47), 0x90}, 229 {TAC_REG_SDW(0, 0, 0x48), 0x80}, 230 {TAC_REG_SDW(0, 0, 0x49), 0x0}, 231 {TAC_REG_SDW(0, 0, 0x4b), 0x90}, 232 {TAC_REG_SDW(0, 0, 0x4c), 0x80}, 233 {TAC_REG_SDW(0, 0, 0x4d), 0x0}, 234 {TAC_REG_SDW(0, 0, 0x4f), 0x31}, 235 {TAC_REG_SDW(0, 0, 0x50), 0x0}, 236 {TAC_REG_SDW(0, 0, 0x51), 0x0}, 237 {TAC_REG_SDW(0, 0, 0x52), 0x90}, 238 {TAC_REG_SDW(0, 0, 0x53), 0x80}, 239 {TAC_REG_SDW(0, 0, 0x55), 0x90}, 240 {TAC_REG_SDW(0, 0, 0x56), 0x80}, 241 {TAC_REG_SDW(0, 0, 0x58), 0x90}, 242 {TAC_REG_SDW(0, 0, 0x59), 0x80}, 243 {TAC_REG_SDW(0, 0, 0x5b), 0x90}, 244 {TAC_REG_SDW(0, 0, 0x5c), 0x80}, 245 {TAC_REG_SDW(0, 0, 0x5e), 0x8}, 246 {TAC_REG_SDW(0, 0, 0x5f), 0x8}, 247 {TAC_REG_SDW(0, 0, 0x60), 0x0}, 248 {TAC_REG_SDW(0, 0, 0x61), 0x0}, 249 {TAC_REG_SDW(0, 0, 0x62), 0xff}, 250 {TAC_REG_SDW(0, 0, 0x63), 0xc0}, 251 {TAC_REG_SDW(0, 0, 0x64), 0x5}, 252 {TAC_REG_SDW(0, 0, 0x65), 0x3}, 253 {TAC_REG_SDW(0, 0, 0x66), 0x0}, 254 {TAC_REG_SDW(0, 0, 0x67), 0x0}, 255 {TAC_REG_SDW(0, 0, 0x68), 0x0}, 256 {TAC_REG_SDW(0, 0, 0x69), 0x8}, 257 {TAC_REG_SDW(0, 0, 0x6a), 0x0}, 258 {TAC_REG_SDW(0, 0, 0x6b), 0xa0}, 259 {TAC_REG_SDW(0, 0, 0x6c), 0x18}, 260 {TAC_REG_SDW(0, 0, 0x6d), 0x18}, 261 {TAC_REG_SDW(0, 0, 0x6e), 0x18}, 262 {TAC_REG_SDW(0, 0, 0x6f), 0x18}, 263 {TAC_REG_SDW(0, 0, 0x70), 0x88}, 264 {TAC_REG_SDW(0, 0, 0x71), 0xff}, 265 {TAC_REG_SDW(0, 0, 0x72), 0x0}, 266 {TAC_REG_SDW(0, 0, 0x73), 0x31}, 267 {TAC_REG_SDW(0, 0, 0x74), 0xc0}, 268 {TAC_REG_SDW(0, 0, 0x75), 0x0}, 269 {TAC_REG_SDW(0, 0, 0x76), 0x0}, 270 {TAC_REG_SDW(0, 0, 0x77), 0x0}, 271 {TAC_REG_SDW(0, 0, 0x78), 0x0}, 272 {TAC_REG_SDW(0, 0, 0x7b), 0x0}, 273 {TAC_REG_SDW(0, 0, 0x7c), 0xd0}, 274 {TAC_REG_SDW(0, 0, 0x7e), 0x0}, 275 {TAC_REG_SDW(0, 1, 0x1), 0x0}, 276 {TAC_REG_SDW(0, 1, 0x2), 0x0}, 277 {TAC_REG_SDW(0, 1, 0x3), 0x0}, 278 {TAC_REG_SDW(0, 1, 0x4), 0x4}, 279 {TAC_REG_SDW(0, 1, 0x5), 0x0}, 280 {TAC_REG_SDW(0, 1, 0x6), 0x0}, 281 {TAC_REG_SDW(0, 1, 0x7), 0x0}, 282 {TAC_REG_SDW(0, 1, 0x8), 0x0}, 283 {TAC_REG_SDW(0, 1, 0x9), 0x0}, 284 {TAC_REG_SDW(0, 1, 0xa), 0x0}, 285 {TAC_REG_SDW(0, 1, 0xb), 0x1}, 286 {TAC_REG_SDW(0, 1, 0xc), 0x0}, 287 {TAC_REG_SDW(0, 1, 0xd), 0x0}, 288 {TAC_REG_SDW(0, 1, 0xe), 0x0}, 289 {TAC_REG_SDW(0, 1, 0xf), 0x8}, 290 {TAC_REG_SDW(0, 1, 0x10), 0x0}, 291 {TAC_REG_SDW(0, 1, 0x11), 0x0}, 292 {TAC_REG_SDW(0, 1, 0x12), 0x1}, 293 {TAC_REG_SDW(0, 1, 0x13), 0x0}, 294 {TAC_REG_SDW(0, 1, 0x14), 0x0}, 295 {TAC_REG_SDW(0, 1, 0x15), 0x0}, 296 {TAC_REG_SDW(0, 1, 0x16), 0x0}, 297 {TAC_REG_SDW(0, 1, 0x17), 0x0}, 298 {TAC_REG_SDW(0, 1, 0x18), 0x0}, 299 {TAC_REG_SDW(0, 1, 0x19), 0x0}, 300 {TAC_REG_SDW(0, 1, 0x1a), 0x0}, 301 {TAC_REG_SDW(0, 1, 0x1b), 0x0}, 302 {TAC_REG_SDW(0, 1, 0x1c), 0x0}, 303 {TAC_REG_SDW(0, 1, 0x1d), 0x0}, 304 {TAC_REG_SDW(0, 1, 0x1e), 0x2}, 305 {TAC_REG_SDW(0, 1, 0x1f), 0x8}, 306 {TAC_REG_SDW(0, 1, 0x20), 0x9}, 307 {TAC_REG_SDW(0, 1, 0x21), 0xa}, 308 {TAC_REG_SDW(0, 1, 0x22), 0xb}, 309 {TAC_REG_SDW(0, 1, 0x23), 0xc}, 310 {TAC_REG_SDW(0, 1, 0x24), 0xd}, 311 {TAC_REG_SDW(0, 1, 0x25), 0xe}, 312 {TAC_REG_SDW(0, 1, 0x26), 0xf}, 313 {TAC_REG_SDW(0, 1, 0x27), 0x8}, 314 {TAC_REG_SDW(0, 1, 0x28), 0x9}, 315 {TAC_REG_SDW(0, 1, 0x29), 0xa}, 316 {TAC_REG_SDW(0, 1, 0x2a), 0xb}, 317 {TAC_REG_SDW(0, 1, 0x2b), 0xc}, 318 {TAC_REG_SDW(0, 1, 0x2c), 0xd}, 319 {TAC_REG_SDW(0, 1, 0x2d), 0xe}, 320 {TAC_REG_SDW(0, 1, 0x2e), 0xf}, 321 {TAC_REG_SDW(0, 1, 0x2f), 0x0}, 322 {TAC_REG_SDW(0, 1, 0x30), 0x0}, 323 {TAC_REG_SDW(0, 1, 0x31), 0x0}, 324 {TAC_REG_SDW(0, 1, 0x32), 0x0}, 325 {TAC_REG_SDW(0, 1, 0x33), 0x0}, 326 {TAC_REG_SDW(0, 1, 0x34), 0x0}, 327 {TAC_REG_SDW(0, 1, 0x35), 0x0}, 328 {TAC_REG_SDW(0, 1, 0x36), 0x0}, 329 {TAC_REG_SDW(0, 1, 0x37), 0x0}, 330 {TAC_REG_SDW(0, 1, 0x38), 0x98}, 331 {TAC_REG_SDW(0, 1, 0x39), 0x0}, 332 {TAC_REG_SDW(0, 1, 0x3a), 0x0}, 333 {TAC_REG_SDW(0, 1, 0x3b), 0x0}, 334 {TAC_REG_SDW(0, 1, 0x3c), 0x1}, 335 {TAC_REG_SDW(0, 1, 0x3d), 0x2}, 336 {TAC_REG_SDW(0, 1, 0x3e), 0x3}, 337 {TAC_REG_SDW(0, 1, 0x3f), 0x4}, 338 {TAC_REG_SDW(0, 1, 0x40), 0x5}, 339 {TAC_REG_SDW(0, 1, 0x41), 0x6}, 340 {TAC_REG_SDW(0, 1, 0x42), 0x7}, 341 {TAC_REG_SDW(0, 1, 0x43), 0x0}, 342 {TAC_REG_SDW(0, 1, 0x44), 0x0}, 343 {TAC_REG_SDW(0, 1, 0x45), 0x1}, 344 {TAC_REG_SDW(0, 1, 0x46), 0x2}, 345 {TAC_REG_SDW(0, 1, 0x47), 0x3}, 346 {TAC_REG_SDW(0, 1, 0x48), 0x4}, 347 {TAC_REG_SDW(0, 1, 0x49), 0x5}, 348 {TAC_REG_SDW(0, 1, 0x4a), 0x6}, 349 {TAC_REG_SDW(0, 1, 0x4b), 0x7}, 350 {TAC_REG_SDW(0, 1, 0x4c), 0x98}, 351 {TAC_REG_SDW(0, 1, 0x4d), 0x0}, 352 {TAC_REG_SDW(0, 1, 0x4e), 0x0}, 353 {TAC_REG_SDW(0, 1, 0x4f), 0x0}, 354 {TAC_REG_SDW(0, 1, 0x50), 0x1}, 355 {TAC_REG_SDW(0, 1, 0x51), 0x2}, 356 {TAC_REG_SDW(0, 1, 0x52), 0x3}, 357 {TAC_REG_SDW(0, 1, 0x53), 0x4}, 358 {TAC_REG_SDW(0, 1, 0x54), 0x5}, 359 {TAC_REG_SDW(0, 1, 0x55), 0x6}, 360 {TAC_REG_SDW(0, 1, 0x56), 0x7}, 361 {TAC_REG_SDW(0, 1, 0x57), 0x0}, 362 {TAC_REG_SDW(0, 1, 0x58), 0x0}, 363 {TAC_REG_SDW(0, 1, 0x59), 0x1}, 364 {TAC_REG_SDW(0, 1, 0x5a), 0x2}, 365 {TAC_REG_SDW(0, 1, 0x5b), 0x3}, 366 {TAC_REG_SDW(0, 1, 0x5c), 0x4}, 367 {TAC_REG_SDW(0, 1, 0x5d), 0x5}, 368 {TAC_REG_SDW(0, 1, 0x5e), 0x6}, 369 {TAC_REG_SDW(0, 1, 0x5f), 0x7}, 370 {TAC_REG_SDW(0, 1, 0x60), 0x98}, 371 {TAC_REG_SDW(0, 1, 0x61), 0x0}, 372 {TAC_REG_SDW(0, 1, 0x62), 0x0}, 373 {TAC_REG_SDW(0, 1, 0x63), 0x0}, 374 {TAC_REG_SDW(0, 1, 0x64), 0x1}, 375 {TAC_REG_SDW(0, 1, 0x65), 0x2}, 376 {TAC_REG_SDW(0, 1, 0x66), 0x3}, 377 {TAC_REG_SDW(0, 1, 0x67), 0x4}, 378 {TAC_REG_SDW(0, 1, 0x68), 0x5}, 379 {TAC_REG_SDW(0, 1, 0x69), 0x6}, 380 {TAC_REG_SDW(0, 1, 0x6a), 0x7}, 381 {TAC_REG_SDW(0, 1, 0x6b), 0x0}, 382 {TAC_REG_SDW(0, 1, 0x6c), 0x0}, 383 {TAC_REG_SDW(0, 1, 0x6d), 0x1}, 384 {TAC_REG_SDW(0, 1, 0x6e), 0x2}, 385 {TAC_REG_SDW(0, 1, 0x6f), 0x3}, 386 {TAC_REG_SDW(0, 1, 0x70), 0x4}, 387 {TAC_REG_SDW(0, 1, 0x71), 0x5}, 388 {TAC_REG_SDW(0, 1, 0x72), 0x6}, 389 {TAC_REG_SDW(0, 1, 0x73), 0x7}, 390 /* SA */ 391 {TAC_MUTE_REG(SA, FU21, LEFT), 0x1}, 392 {TAC_MUTE_REG(SA, FU21, RIGHT), 0x1}, 393 {TAC_VOLUME_REG(SA, FU21, LEFT), 0x9c00}, 394 {TAC_VOLUME_REG(SA, FU21, RIGHT), 0x9c00}, 395 {TAC_MUTE_REG(SA, FU23, LEFT), 0x1}, 396 {TAC_MUTE_REG(SA, FU23, RIGHT), 0x1}, 397 {TAC_GAIN_REG(SA, FU23, LEFT), 0x0}, 398 {TAC_GAIN_REG(SA, FU23, RIGHT), 0x0}, 399 /* SM */ 400 {TAC_USAGE_REG(SM, IT11), 0x0}, 401 {TAC_USAGE_REG(SM, OT113), 0x0}, 402 {TAC_MUTE_REG(SM, FU113, LEFT), 0x1}, 403 {TAC_MUTE_REG(SM, FU113, RIGHT), 0x1}, 404 {TAC_GAIN_REG(SM, FU113, LEFT), 0x0}, 405 {TAC_GAIN_REG(SM, FU113, RIGHT), 0x0}, 406 {TAC_MUTE_REG(SM, FU11, LEFT), 0x1}, 407 {TAC_MUTE_REG(SM, FU11, RIGHT), 0x1}, 408 {TAC_GAIN_REG(SM, FU11, LEFT), 0x0}, 409 {TAC_GAIN_REG(SM, FU11, RIGHT), 0x0}, 410 {TAC_XU_BYPASS_REG(SM, XU12), 0x1}, 411 {SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_CS113, 412 TAC_SDCA_CTL_CS_SAMP_RATE_IDX, 0), 0x0}, 413 /* UAJ */ 414 {TAC_USAGE_REG(UAJ, IT33), 0x0}, 415 {TAC_USAGE_REG(UAJ, IT41), 0x0}, 416 {TAC_USAGE_REG(UAJ, OT36), 0x0}, 417 {TAC_USAGE_REG(UAJ, OT45), 0x0}, 418 {TAC_MUTE_REG(UAJ, FU41, LEFT), 0x1}, 419 {TAC_MUTE_REG(UAJ, FU41, RIGHT), 0x1}, 420 {TAC_VOLUME_REG(UAJ, FU41, LEFT), 0x0}, 421 {TAC_VOLUME_REG(UAJ, FU41, RIGHT), 0x0}, 422 {TAC_MUTE_REG(UAJ, FU36, RIGHT), 0x1}, 423 {SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_FU36, 424 TAC_SDCA_CHANNEL_VOLUME, TAC_JACK_MONO_CS), 0x0}, 425 {TAC_XU_BYPASS_REG(UAJ, XU42), 0x0}, 426 {SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_CS36, 427 TAC_SDCA_CTL_CS_SAMP_RATE_IDX, 0), 0x0}, 428 {SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_CS41, 429 TAC_SDCA_CTL_CS_SAMP_RATE_IDX, 0), 0x0}, 430 }; 431 432 static const struct reg_sequence tac_spk_seq[] = { 433 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU21, 434 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_LEFT), 0), 435 REG_SEQ0(SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU21, 436 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_RIGHT), 0), 437 }; 438 439 static bool tac_volatile_reg(struct device *dev, unsigned int reg) 440 { 441 switch (reg) { 442 case TAC_REG_SDW(0, 0, 1) ... TAC_REG_SDW(0, 0, 5): 443 case TAC_REG_SDW(0, 2, 1) ... TAC_REG_SDW(0, 2, 6): 444 case TAC_REG_SDW(0, 2, 24) ... TAC_REG_SDW(0, 2, 55): 445 case SDW_SDCA_CTL(TAC_FUNCTION_ID_HID, TAC_SDCA_ENT_HID1, 446 TAC_SDCA_CTL_HIDTX_CURRENT_OWNER, 0): 447 case SDW_SDCA_CTL(TAC_FUNCTION_ID_HID, TAC_SDCA_ENT_HID1, 448 TAC_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0): 449 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_GE35, 450 TAC_SDCA_CTL_DET_MODE, 0): 451 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_PDE23, 452 TAC_SDCA_REQUESTED_PS, 0): 453 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_PDE11, 454 TAC_SDCA_REQUESTED_PS, 0): 455 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_PDE47, 456 TAC_SDCA_REQUESTED_PS, 0): 457 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_PDE34, 458 TAC_SDCA_REQUESTED_PS, 0): 459 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_PDE23, 460 TAC_SDCA_ACTUAL_PS, 0): 461 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_PDE11, 462 TAC_SDCA_ACTUAL_PS, 0): 463 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_PDE47, 464 TAC_SDCA_ACTUAL_PS, 0): 465 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_PDE34, 466 TAC_SDCA_ACTUAL_PS, 0): 467 case SDW_SCP_SDCA_INT1: 468 case SDW_SCP_SDCA_INT2: 469 case SDW_SCP_SDCA_INT3: 470 case SDW_SCP_SDCA_INT4: 471 case SDW_SDCA_CTL(1, 0, 0x10, 0): 472 case SDW_SDCA_CTL(2, 0, 0x10, 0): 473 case SDW_SDCA_CTL(3, 0, 0x10, 0): 474 case SDW_SDCA_CTL(4, 0, 0x1, 0): 475 case 0x44007F80 ... 0x44007F87: 476 case TAC_DSP_ALGO_STATUS: /* DSP algo status - always read from HW */ 477 return true; 478 default: 479 break; 480 } 481 482 return false; 483 } 484 485 static int tac_sdca_mbq_size(struct device *dev, unsigned int reg) 486 { 487 switch (reg) { 488 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU21, 489 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_LEFT): 490 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU21, 491 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_RIGHT): 492 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU23, 493 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_LEFT): 494 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU23, 495 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_RIGHT): 496 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SA, TAC_SDCA_ENT_FU23, 497 TAC_SDCA_CHANNEL_GAIN, 0): 498 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_FU113, 499 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_LEFT): 500 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_FU113, 501 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_RIGHT): 502 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_FU11, 503 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_LEFT): 504 case SDW_SDCA_CTL(TAC_FUNCTION_ID_SM, TAC_SDCA_ENT_FU11, 505 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_RIGHT): 506 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_FU41, 507 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_LEFT): 508 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_FU41, 509 TAC_SDCA_CHANNEL_VOLUME, TAC_CHANNEL_RIGHT): 510 case SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_FU36, 511 TAC_SDCA_CHANNEL_VOLUME, TAC_JACK_MONO_CS): 512 return 2; 513 514 default: 515 return 1; 516 } 517 } 518 519 static const struct regmap_sdw_mbq_cfg tac_mbq_cfg = { 520 .mbq_size = tac_sdca_mbq_size, 521 }; 522 523 static const struct regmap_config tac_regmap = { 524 .reg_bits = 32, 525 .val_bits = 16, /* mbq support */ 526 .reg_defaults = tac_reg_default, 527 .num_reg_defaults = ARRAY_SIZE(tac_reg_default), 528 .max_register = 0x47FFFFFF, 529 .cache_type = REGCACHE_MAPLE, 530 .volatile_reg = tac_volatile_reg, 531 .use_single_read = true, 532 .use_single_write = true, 533 }; 534 535 /* Check if device has UAJ (Universal Audio Jack) support */ 536 static bool tac_has_uaj_support(struct tac5xx2_prv *tac_dev) 537 { 538 return tac_dev->uaj_func_data; 539 } 540 541 /* Forward declaration for headset detection */ 542 static int tac5xx2_sdca_headset_detect(struct tac5xx2_prv *tac_dev); 543 544 /* Volume controls for mic, hp and mic cap */ 545 static const struct snd_kcontrol_new tac5xx2_snd_controls[] = { 546 SOC_DOUBLE_R_RANGE_TLV("Amp Volume", TAC_AMP_LVL_CFG0, TAC_AMP_LVL_CFG1, 547 2, 0, 44, 1, tac5xx2_amp_tlv), 548 TAC_DOUBLE_Q78_TLV("DMIC Capture Volume", SM, FU113), 549 TAC_DOUBLE_Q78_TLV("Speaker Volume", SA, FU21), 550 }; 551 552 static const struct snd_kcontrol_new tac_uaj_controls[] = { 553 TAC_DOUBLE_Q78_TLV("UAJ Playback Volume", UAJ, FU41), 554 SDCA_SINGLE_Q78_TLV("UAJ Capture Volume", 555 SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_FU36, 556 TAC_SDCA_CHANNEL_VOLUME, TAC_JACK_MONO_CS), 557 TAC_DVC_MIN, TAC_DVC_MAX, TAC_DVC_STEP, tac5xx2_dvc_tlv), 558 }; 559 560 static const struct snd_soc_dapm_widget tac5xx2_common_widgets[] = { 561 /* Port 1: Speaker Playback Path */ 562 SND_SOC_DAPM_AIF_IN("AIF1 Playback", "DP1 Speaker Playback", 0, 563 SND_SOC_NOPM, 0, 0), 564 SND_SOC_DAPM_PGA("FU21_L", FU21_L_MUTE_REG, 0, 1, NULL, 0), 565 SND_SOC_DAPM_PGA("FU21_R", FU21_R_MUTE_REG, 0, 1, NULL, 0), 566 SND_SOC_DAPM_PGA("FU23_L", FU23_L_MUTE_REG, 0, 1, NULL, 0), 567 SND_SOC_DAPM_PGA("FU23_R", FU23_R_MUTE_REG, 0, 1, NULL, 0), 568 SND_SOC_DAPM_OUTPUT("SPK_L"), 569 SND_SOC_DAPM_OUTPUT("SPK_R"), 570 571 /* Port 3: Smart Mic (DMIC) Capture Path */ 572 SND_SOC_DAPM_AIF_OUT("AIF3 Capture", "DP3 Mic Capture", 0, SND_SOC_NOPM, 0, 0), 573 SND_SOC_DAPM_INPUT("DMIC_L"), 574 SND_SOC_DAPM_INPUT("DMIC_R"), 575 SND_SOC_DAPM_PGA("IT11", IT11_USAGE_REG, 0, 0, NULL, 0), 576 SND_SOC_DAPM_SUPPLY("CS113", SND_SOC_NOPM, 0, 0, NULL, 0), 577 SND_SOC_DAPM_PGA("FU11_L", FU11_L_MUTE_REG, 0, 1, NULL, 0), 578 SND_SOC_DAPM_PGA("FU11_R", FU11_R_MUTE_REG, 0, 1, NULL, 0), 579 SND_SOC_DAPM_PGA("PPU11", SND_SOC_NOPM, 0, 0, NULL, 0), 580 SND_SOC_DAPM_PGA("XU12", XU12_BYPASS_REG, 0, 0, NULL, 0), 581 SND_SOC_DAPM_PGA("FU113_L", FU113_L_MUTE_REG, 0, 1, NULL, 0), 582 SND_SOC_DAPM_PGA("FU113_R", FU113_R_MUTE_REG, 0, 1, NULL, 0), 583 SND_SOC_DAPM_PGA("OT113", OT113_USAGE_REG, 0, 0, NULL, 0), 584 }; 585 586 static const struct snd_soc_dapm_widget tac_uaj_widgets[] = { 587 /* Port 4: UAJ (Headphone) Playback Path */ 588 SND_SOC_DAPM_AIF_IN("AIF4 Playback", "DP4 UAJ Speaker Playback", 0, 589 SND_SOC_NOPM, 0, 0), 590 SND_SOC_DAPM_PGA("IT41", IT41_USAGE_REG, 0, 0, NULL, 0), 591 SND_SOC_DAPM_PGA("FU41_L", FU41_L_MUTE_REG, 0, 1, NULL, 0), 592 SND_SOC_DAPM_PGA("FU41_R", FU41_R_MUTE_REG, 0, 1, NULL, 0), 593 SND_SOC_DAPM_PGA("XU42", XU42_BYPASS_REG, 0, 0, NULL, 0), 594 SND_SOC_DAPM_SUPPLY("CS41", SND_SOC_NOPM, 0, 0, NULL, 0), 595 SND_SOC_DAPM_DAC("OT45", "DP4 UAJ Speaker Playback", OT45_USAGE_REG, 0, 0), 596 SND_SOC_DAPM_OUTPUT("HP_L"), 597 SND_SOC_DAPM_OUTPUT("HP_R"), 598 599 /* Port 7: UAJ (Headset Mic) Capture Path */ 600 SND_SOC_DAPM_AIF_OUT("AIF7 Capture", "DP7 UAJ Mic Capture", 0, 601 SND_SOC_NOPM, 0, 0), 602 SND_SOC_DAPM_INPUT("UAJ_MIC"), 603 SND_SOC_DAPM_ADC("IT33", "DP7 UAJ Mic Capture", IT33_USAGE_REG, 0, 0), 604 SND_SOC_DAPM_PGA("FU36", FU36_MUTE_REG, 0, 1, NULL, 0), 605 SND_SOC_DAPM_SUPPLY("CS36", SND_SOC_NOPM, 0, 0, NULL, 0), 606 SND_SOC_DAPM_PGA("OT36", OT36_USAGE_REG, 0, 0, NULL, 0), 607 }; 608 609 static const struct snd_soc_dapm_route tac5xx2_common_routes[] = { 610 /* Speaker Playback Path */ 611 {"FU21_L", NULL, "AIF1 Playback"}, 612 {"FU21_R", NULL, "AIF1 Playback"}, 613 614 {"FU23_L", NULL, "FU21_L"}, 615 {"FU23_R", NULL, "FU21_R"}, 616 617 {"SPK_L", NULL, "FU23_L"}, 618 {"SPK_R", NULL, "FU23_R"}, 619 620 /* Smart Mic DAPM Routes */ 621 {"IT11", NULL, "DMIC_L"}, 622 {"IT11", NULL, "DMIC_R"}, 623 {"FU11_L", NULL, "IT11"}, 624 {"FU11_R", NULL, "IT11"}, 625 {"PPU11", NULL, "FU11_L"}, 626 {"PPU11", NULL, "FU11_R"}, 627 {"XU12", NULL, "PPU11"}, 628 {"FU113_L", NULL, "XU12"}, 629 {"FU113_R", NULL, "XU12"}, 630 {"FU113_L", NULL, "CS113"}, 631 {"FU113_R", NULL, "CS113"}, 632 {"OT113", NULL, "FU113_L"}, 633 {"OT113", NULL, "FU113_R"}, 634 {"OT113", NULL, "CS113"}, 635 {"AIF3 Capture", NULL, "OT113"}, 636 }; 637 638 static const struct snd_soc_dapm_route tac_uaj_routes[] = { 639 /* UAJ Playback routes */ 640 {"IT41", NULL, "AIF4 Playback"}, 641 {"IT41", NULL, "CS41"}, 642 {"FU41_L", NULL, "IT41"}, 643 {"FU41_R", NULL, "IT41"}, 644 {"XU42", NULL, "FU41_L"}, 645 {"XU42", NULL, "FU41_R"}, 646 {"OT45", NULL, "XU42"}, 647 {"OT45", NULL, "CS41"}, 648 {"HP_L", NULL, "OT45"}, 649 {"HP_R", NULL, "OT45"}, 650 651 /* UAJ Capture routes */ 652 {"IT33", NULL, "UAJ_MIC"}, 653 {"IT33", NULL, "CS36"}, 654 {"FU36", NULL, "IT33"}, 655 {"OT36", NULL, "FU36"}, 656 {"OT36", NULL, "CS36"}, 657 {"AIF7 Capture", NULL, "OT36"}, 658 }; 659 660 static s32 tac_set_sdw_stream(struct snd_soc_dai *dai, 661 void *sdw_stream, s32 direction) 662 { 663 if (sdw_stream) 664 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 665 666 return 0; 667 } 668 669 static void tac_sdw_shutdown(struct snd_pcm_substream *substream, 670 struct snd_soc_dai *dai) 671 { 672 snd_soc_dai_set_dma_data(dai, substream, NULL); 673 } 674 675 static int tac_clear_latch(struct tac5xx2_prv *priv) 676 { 677 /* CLR_REG is a self-clearing bit */ 678 return regmap_update_bits(priv->regmap, TAC_INT_CFG, 679 TAC_INT_CFG_CLR_REG, TAC_INT_CFG_CLR_REG); 680 } 681 682 static int tac_sdw_hw_params(struct snd_pcm_substream *substream, 683 struct snd_pcm_hw_params *params, 684 struct snd_soc_dai *dai) 685 { 686 struct snd_soc_component *component = dai->component; 687 struct tac5xx2_prv *tac_dev = snd_soc_component_get_drvdata(component); 688 struct sdw_slave *sdw_peripheral = tac_dev->sdw_peripheral; 689 struct sdw_stream_runtime *sdw_stream; 690 struct sdw_stream_config stream_config = {0}; 691 struct sdw_port_config port_config = {0}; 692 u8 sample_rate_idx = 0; 693 int function_id; 694 int pde_entity; 695 int port_num; 696 int ret; 697 698 if (!tac_dev->hw_init) { 699 dev_err(tac_dev->dev, 700 "error: operation without hw initialization"); 701 return -EINVAL; 702 } 703 704 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 705 if (!sdw_stream) { 706 dev_err(tac_dev->dev, "failed to get dma data"); 707 return -EINVAL; 708 } 709 710 ret = tac_clear_latch(tac_dev); 711 if (ret) 712 dev_warn(tac_dev->dev, "clear latch failed, err=%d", ret); 713 714 switch (dai->id) { 715 case TAC5XX2_DMIC: 716 function_id = TAC_FUNCTION_ID_SM; 717 pde_entity = TAC_SDCA_ENT_PDE11; 718 port_num = TAC_SDW_PORT_NUM_DMIC; 719 break; 720 case TAC5XX2_UAJ: 721 function_id = TAC_FUNCTION_ID_UAJ; 722 pde_entity = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 723 TAC_SDCA_ENT_PDE47 : TAC_SDCA_ENT_PDE34; 724 port_num = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 725 TAC_SDW_PORT_NUM_UAJ_PLAYBACK : 726 TAC_SDW_PORT_NUM_UAJ_CAPTURE; 727 break; 728 case TAC5XX2_SPK: 729 function_id = TAC_FUNCTION_ID_SA; 730 pde_entity = TAC_SDCA_ENT_PDE23; 731 port_num = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 732 TAC_SDW_PORT_NUM_SPK_PLAYBACK : 733 TAC_SDW_PORT_NUM_SPK_CAPTURE; 734 break; 735 default: 736 dev_err(tac_dev->dev, "Invalid dai id: %d for power up\n", dai->id); 737 return -EINVAL; 738 } 739 740 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 741 port_config.num = port_num; 742 ret = sdw_stream_add_slave(sdw_peripheral, &stream_config, 743 &port_config, 1, sdw_stream); 744 if (ret) { 745 dev_err(dai->dev, 746 "Unable to configure port %d: %d\n", port_num, ret); 747 return ret; 748 } 749 750 switch (params_rate(params)) { 751 case 48000: 752 sample_rate_idx = 0x01; 753 break; 754 case 44100: 755 sample_rate_idx = 0x02; 756 break; 757 case 96000: 758 sample_rate_idx = 0x03; 759 break; 760 case 88200: 761 sample_rate_idx = 0x04; 762 break; 763 default: 764 dev_dbg(tac_dev->dev, "Unsupported sample rate: %d Hz", 765 params_rate(params)); 766 return -EINVAL; 767 } 768 769 switch (function_id) { 770 case TAC_FUNCTION_ID_SM: 771 ret = regmap_write(tac_dev->regmap, 772 SDW_SDCA_CTL(function_id, TAC_SDCA_ENT_CS113, 773 TAC_SDCA_CTL_CS_SAMP_RATE_IDX, 0), 774 sample_rate_idx); 775 if (ret) { 776 dev_err(tac_dev->dev, "Failed to set CS113 sample rate: %d", ret); 777 return ret; 778 } 779 780 break; 781 case TAC_FUNCTION_ID_UAJ: 782 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 783 ret = regmap_write(tac_dev->regmap, 784 SDW_SDCA_CTL(function_id, TAC_SDCA_ENT_CS41, 785 TAC_SDCA_CTL_CS_SAMP_RATE_IDX, 0), 786 sample_rate_idx); 787 if (ret) { 788 dev_err(tac_dev->dev, "Failed to set CS41 sample rate: %d", ret); 789 return ret; 790 } 791 } else { 792 ret = regmap_write(tac_dev->regmap, 793 SDW_SDCA_CTL(function_id, TAC_SDCA_ENT_CS36, 794 TAC_SDCA_CTL_CS_SAMP_RATE_IDX, 0), 795 sample_rate_idx); 796 if (ret) { 797 dev_err(tac_dev->dev, "Failed to set CS36 sample rate: %d", ret); 798 return ret; 799 } 800 } 801 break; 802 case TAC_FUNCTION_ID_SA: 803 /* SmartAmp: no additional sample rate configuration needed */ 804 break; 805 } 806 807 ret = regmap_write(tac_dev->regmap, SDW_SDCA_CTL(function_id, pde_entity, 808 TAC_SDCA_REQUESTED_PS, 0), 0); 809 if (ret) { 810 dev_err(tac_dev->dev, 811 "failed to set func %d, entity %d's requested PS to 0: %d\n", 812 function_id, pde_entity, ret); 813 return ret; 814 } 815 816 ret = sdca_asoc_pde_poll_actual_ps(tac_dev->regmap, function_id, pde_entity, 817 SDCA_PDE_PS3, SDCA_PDE_PS0, NULL, 0); 818 if (ret) 819 dev_err(tac_dev->dev, "failed to transition func %d, pde %d from PS3 -> PS0, err=%d\n", 820 function_id, pde_entity, ret); 821 return ret; 822 } 823 824 static int tac_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 825 struct snd_soc_dai *dai) 826 { 827 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 828 struct tac5xx2_prv *tac_dev = snd_soc_component_get_drvdata(dai->component); 829 int pde_entity, function_id; 830 int ret; 831 832 sdw_stream_remove_slave(tac_dev->sdw_peripheral, sdw_stream); 833 834 switch (dai->id) { 835 case TAC5XX2_DMIC: 836 pde_entity = TAC_SDCA_ENT_PDE11; 837 function_id = TAC_FUNCTION_ID_SM; 838 break; 839 case TAC5XX2_UAJ: 840 function_id = TAC_FUNCTION_ID_UAJ; 841 pde_entity = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 842 TAC_SDCA_ENT_PDE47 : TAC_SDCA_ENT_PDE34; 843 break; 844 case TAC5XX2_SPK: 845 function_id = TAC_FUNCTION_ID_SA; 846 pde_entity = TAC_SDCA_ENT_PDE23; 847 break; 848 default: 849 dev_err(tac_dev->dev, "unhandled dai %d for power down\n", dai->id); 850 return -EINVAL; 851 } 852 853 ret = regmap_write(tac_dev->regmap, SDW_SDCA_CTL(function_id, pde_entity, 854 TAC_SDCA_REQUESTED_PS, 0), 855 SDCA_PDE_PS3); 856 if (ret) { 857 dev_err(tac_dev->dev, 858 "failed to set func %d, entity %d's requested PS to 3: %d\n", 859 function_id, pde_entity, ret); 860 return ret; 861 } 862 863 ret = sdca_asoc_pde_poll_actual_ps(tac_dev->regmap, function_id, 864 pde_entity, SDCA_PDE_PS0, SDCA_PDE_PS3, 865 NULL, 0); 866 if (ret) 867 dev_err(tac_dev->dev, 868 "failed to transition func %d, pde %d from PS0 -> PS3, err=%d\n", 869 function_id, pde_entity, ret); 870 871 return ret; 872 } 873 874 static const struct snd_soc_dai_ops tac_dai_ops = { 875 .hw_params = tac_sdw_hw_params, 876 .hw_free = tac_sdw_pcm_hw_free, 877 .set_stream = tac_set_sdw_stream, 878 .shutdown = tac_sdw_shutdown, 879 }; 880 881 static int tac5xx2_sdca_btn_type(unsigned char *buffer, struct tac5xx2_prv *tac_dev) 882 { 883 switch (*buffer) { 884 case 1: /* play pause */ 885 return SND_JACK_BTN_0; 886 case 10: /* vol down */ 887 return SND_JACK_BTN_3; 888 case 8: /* vol up */ 889 return SND_JACK_BTN_2; 890 case 4: /* long press */ 891 return SND_JACK_BTN_1; 892 case 2: /* next song */ 893 case 32: /* next song */ 894 return SND_JACK_BTN_4; 895 default: 896 return 0; 897 } 898 } 899 900 static int tac5xx2_sdca_button_detect(struct tac5xx2_prv *tac_dev) 901 { 902 unsigned int btn_type, offset, idx; 903 int ret, value, owner; 904 u8 buf[2]; 905 906 ret = regmap_read(tac_dev->regmap, 907 SDW_SDCA_CTL(TAC_FUNCTION_ID_HID, TAC_SDCA_ENT_HID1, 908 TAC_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), &owner); 909 if (ret) { 910 dev_err(tac_dev->dev, 911 "Failed to read current UMP message owner 0x%x", ret); 912 return ret; 913 } 914 915 if (owner == SDCA_UMP_OWNER_DEVICE) { 916 dev_dbg(tac_dev->dev, "skip button detect as current owner is not host\n"); 917 return 0; 918 } 919 920 ret = regmap_read(tac_dev->regmap, 921 SDW_SDCA_CTL(TAC_FUNCTION_ID_HID, TAC_SDCA_ENT_HID1, 922 TAC_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset); 923 if (ret) { 924 dev_err(tac_dev->dev, 925 "Failed to read current UMP message offset: %d", ret); 926 goto end_btn_det; 927 } 928 929 dev_dbg(tac_dev->dev, "button detect: message offset = %x", offset); 930 931 for (idx = 0; idx < sizeof(buf); idx++) { 932 ret = regmap_read(tac_dev->regmap, 933 TAC_BUF_ADDR_HID1 + offset + idx, &value); 934 if (ret) { 935 dev_err(tac_dev->dev, 936 "Failed to read HID buffer: %d", ret); 937 goto end_btn_det; 938 } 939 buf[idx] = value & 0xff; 940 } 941 942 if (buf[0] == 0x1) { 943 btn_type = tac5xx2_sdca_btn_type(&buf[1], tac_dev); 944 ret = btn_type; 945 } 946 947 end_btn_det: 948 regmap_write(tac_dev->regmap, 949 SDW_SDCA_CTL(TAC_FUNCTION_ID_HID, TAC_SDCA_ENT_HID1, 950 TAC_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), 0x01); 951 952 return ret; 953 } 954 955 static int tac5xx2_sdca_headset_detect(struct tac5xx2_prv *tac_dev) 956 { 957 int val, ret; 958 u8 jack_prep; 959 960 ret = regmap_read(tac_dev->regmap, 961 SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_GE35, 962 TAC_SDCA_CTL_DET_MODE, 0), &val); 963 if (ret) { 964 dev_err(tac_dev->dev, "Failed to read the detect mode"); 965 return ret; 966 } 967 968 jack_prep = TAC_UAJ_PREP_CONNECTED; 969 970 switch (val) { 971 case 4: 972 tac_dev->jack_type = SND_JACK_MICROPHONE; 973 break; 974 case 5: 975 tac_dev->jack_type = SND_JACK_HEADPHONE; 976 break; 977 case 6: 978 tac_dev->jack_type = SND_JACK_HEADSET; 979 break; 980 case 0: 981 default: 982 tac_dev->jack_type = 0; 983 jack_prep = TAC_UAJ_PREP_DISCONNECTED; 984 break; 985 } 986 987 ret = regmap_write(tac_dev->regmap, 988 SDW_SDCA_CTL(TAC_FUNCTION_ID_UAJ, TAC_SDCA_ENT_GE35, 989 TAC_SDCA_CTL_SEL_MODE, 0), val); 990 if (ret) 991 dev_err(tac_dev->dev, "Failed to update the jack type to device"); 992 993 /* 994 * When uaj is uplugged and booted, we end up with the channel prepare 995 * timeout error for the uaj ports. This writes allows the channel prepare 996 * to succeed when the uaj is not plugged in. 997 */ 998 if (tac_dev->rev_id >= 0x30) { 999 ret = regmap_write(tac_dev->regmap, TAC_REG_SDW(0, 3, 127), jack_prep); 1000 if (ret) 1001 dev_warn(tac_dev->dev, "Failed to write jack_prep register: %d\n", ret); 1002 } 1003 1004 return 0; 1005 } 1006 1007 static int tac5xx2_jack_init(struct tac5xx2_prv *tac_dev) 1008 { 1009 u32 jd_int_mask, hid_int_mask; 1010 int ret = 0; 1011 1012 if (tac_dev->rev_id >= 0x30) { 1013 jd_int_mask = SDW_SCP_SDCA_INTMASK_SDCA_12; 1014 hid_int_mask = SDW_SCP_SDCA_INTMASK_SDCA_17; 1015 } else { 1016 jd_int_mask = SDW_SCP_SDCA_INTMASK_SDCA_11; 1017 hid_int_mask = SDW_SCP_SDCA_INTMASK_SDCA_16; 1018 } 1019 1020 if (!tac_dev->hs_jack) 1021 goto disable_interrupts; 1022 1023 ret = regmap_write(tac_dev->regmap, SDW_SCP_SDCA_INTMASK2, jd_int_mask); 1024 if (ret) { 1025 dev_err(tac_dev->dev, 1026 "Failed to register jack detection interrupt: %d\n", ret); 1027 goto disable_interrupts; 1028 } 1029 1030 ret = regmap_write(tac_dev->regmap, SDW_SCP_SDCA_INTMASK3, hid_int_mask); 1031 if (ret) { 1032 dev_err(tac_dev->dev, 1033 "Failed to register for button detect interrupt: %d\n", ret); 1034 goto disable_interrupts; 1035 } 1036 1037 return 0; 1038 1039 disable_interrupts: 1040 /* ignore errors while disabling interrupts */ 1041 regmap_write(tac_dev->regmap, SDW_SCP_SDCA_INTMASK2, 0); 1042 regmap_write(tac_dev->regmap, SDW_SCP_SDCA_INTMASK3, 0); 1043 1044 return ret; 1045 } 1046 1047 static int tac5xx2_set_jack(struct snd_soc_component *component, 1048 struct snd_soc_jack *hs_jack, void *data) 1049 { 1050 struct tac5xx2_prv *tac_dev = snd_soc_component_get_drvdata(component); 1051 int ret; 1052 1053 tac_dev->hs_jack = hs_jack; 1054 1055 /* resume can happen only after first hw_init */ 1056 if (!tac_dev->first_hw_init_done) 1057 return 0; 1058 1059 ret = pm_runtime_resume_and_get(component->dev); 1060 if (ret < 0) { 1061 if (ret != -EACCES) { 1062 dev_err(component->dev, 1063 "%s: failed to resume %d\n", __func__, ret); 1064 return ret; 1065 } 1066 1067 /* pm_runtime not enabled yet */ 1068 dev_dbg(component->dev, 1069 "%s: skipping jack init for now\n", __func__); 1070 return 0; 1071 } 1072 1073 ret = tac5xx2_jack_init(tac_dev); 1074 if (ret) 1075 dev_err(tac_dev->dev, "jack init failed, err=%d\n", ret); 1076 1077 pm_runtime_mark_last_busy(component->dev); 1078 pm_runtime_put_autosuspend(component->dev); 1079 1080 return ret; 1081 } 1082 1083 static int tac_interrupt_callback(struct sdw_slave *slave, 1084 struct sdw_slave_intr_status *status) 1085 { 1086 unsigned int sdca_int2, sdca_int3, jack_report_mask = 0; 1087 struct tac5xx2_prv *tac_dev = dev_get_drvdata(&slave->dev); 1088 struct device *dev = &slave->dev; 1089 u32 headset_detect_chk, hid_detect_chk; 1090 int btn_type = 0; 1091 int ret = 0; 1092 1093 if (status->control_port) { 1094 if (status->control_port & SDW_SCP_INT1_PARITY) 1095 dev_warn(dev, "SCP: Parity error interrupt"); 1096 if (status->control_port & SDW_SCP_INT1_BUS_CLASH) 1097 dev_warn(dev, "SCP: Bus clash interrupt"); 1098 } 1099 1100 if (!tac_has_uaj_support(tac_dev)) 1101 return 0; 1102 1103 ret = regmap_read(tac_dev->regmap, SDW_SCP_SDCA_INT2, &sdca_int2); 1104 if (ret) { 1105 dev_err(dev, "Failed to read UAJ Interrupt, reg:%#x err=%d\n", 1106 SDW_SCP_SDCA_INT2, ret); 1107 return ret; 1108 } 1109 1110 ret = regmap_read(tac_dev->regmap, SDW_SCP_SDCA_INT3, &sdca_int3); 1111 if (ret) { 1112 dev_err(dev, "Failed to read HID interrupt reg=%#x: err=%d", 1113 SDW_SCP_SDCA_INT3, ret); 1114 return ret; 1115 } 1116 1117 dev_dbg(dev, "SDCA_INT2: 0x%02x, SDCA_INT3: 0x%02x\n", 1118 sdca_int2, sdca_int3); 1119 1120 if (tac_dev->rev_id >= 0x30) { 1121 headset_detect_chk = SDW_SCP_SDCA_INT_SDCA_12; 1122 hid_detect_chk = SDW_SCP_SDCA_INT_SDCA_17; 1123 } else { 1124 headset_detect_chk = SDW_SCP_SDCA_INT_SDCA_11; 1125 hid_detect_chk = SDW_SCP_SDCA_INT_SDCA_16; 1126 } 1127 1128 if (sdca_int2 & headset_detect_chk) { 1129 ret = tac5xx2_sdca_headset_detect(tac_dev); 1130 if (ret < 0) 1131 goto clear; 1132 jack_report_mask |= SND_JACK_HEADSET; 1133 } 1134 1135 if (sdca_int3 & hid_detect_chk) { 1136 btn_type = tac5xx2_sdca_button_detect(tac_dev); 1137 if (btn_type < 0) 1138 btn_type = 0; 1139 jack_report_mask |= SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1140 SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4; 1141 } 1142 1143 if (tac_dev->jack_type == 0) 1144 btn_type = 0; 1145 1146 dev_dbg(tac_dev->dev, "in %s, jack_type=%d\n", __func__, tac_dev->jack_type); 1147 dev_dbg(tac_dev->dev, "in %s, btn_type=0x%x\n", __func__, btn_type); 1148 1149 if (!tac_dev->hs_jack) 1150 goto clear; 1151 1152 snd_soc_jack_report(tac_dev->hs_jack, tac_dev->jack_type | btn_type, 1153 jack_report_mask); 1154 1155 clear: 1156 if (sdca_int2) { 1157 ret = regmap_write(tac_dev->regmap, SDW_SCP_SDCA_INT2, sdca_int2); 1158 if (ret) 1159 dev_dbg(tac_dev->dev, "Failed to clear jack interrupt\n"); 1160 } 1161 1162 if (sdca_int3) { 1163 ret = regmap_write(tac_dev->regmap, SDW_SCP_SDCA_INT3, sdca_int3); 1164 if (ret) 1165 dev_dbg(tac_dev->dev, "failed to clear hid interrupt\n"); 1166 } 1167 1168 return 0; 1169 } 1170 1171 static struct snd_soc_dai_driver tac5572_dai_driver[] = { 1172 { 1173 .name = "tac5xx2-aif1", 1174 .id = TAC5XX2_SPK, 1175 .playback = { 1176 .stream_name = "DP1 Speaker Playback", 1177 .channels_min = 1, 1178 .channels_max = 2, 1179 .rates = TAC5XX2_DEVICE_RATES, 1180 .formats = TAC5XX2_DEVICE_FORMATS, 1181 }, 1182 .ops = &tac_dai_ops, 1183 }, 1184 { 1185 .name = "tac5xx2-aif2", 1186 .id = TAC5XX2_DMIC, 1187 .capture = { 1188 .stream_name = "DP3 Mic Capture", 1189 .channels_min = 1, 1190 .channels_max = 4, 1191 .rates = TAC5XX2_DEVICE_RATES, 1192 .formats = TAC5XX2_DEVICE_FORMATS, 1193 }, 1194 .ops = &tac_dai_ops, 1195 }, 1196 { 1197 .name = "tac5xx2-aif3", 1198 .id = TAC5XX2_UAJ, 1199 .playback = { 1200 .stream_name = "DP4 UAJ Speaker Playback", 1201 .channels_min = 1, 1202 .channels_max = 2, 1203 .rates = TAC5XX2_DEVICE_RATES, 1204 .formats = TAC5XX2_DEVICE_FORMATS, 1205 }, 1206 .capture = { 1207 .stream_name = "DP7 UAJ Mic Capture", 1208 .channels_min = 1, 1209 .channels_max = 2, 1210 .rates = TAC5XX2_DEVICE_RATES, 1211 .formats = TAC5XX2_DEVICE_FORMATS, 1212 }, 1213 .ops = &tac_dai_ops, 1214 }, 1215 }; 1216 1217 static struct snd_soc_dai_driver tac5672_dai_driver[] = { 1218 { 1219 .name = "tac5xx2-aif1", 1220 .id = TAC5XX2_SPK, 1221 .playback = { 1222 .stream_name = "DP1 Speaker Playback", 1223 .channels_min = 1, 1224 .channels_max = 2, 1225 .rates = TAC5XX2_DEVICE_RATES, 1226 .formats = TAC5XX2_DEVICE_FORMATS, 1227 }, 1228 .capture = { 1229 .stream_name = "DP8 IV Sense Capture", 1230 .channels_min = 1, 1231 .channels_max = 4, 1232 .rates = TAC5XX2_DEVICE_RATES, 1233 .formats = TAC5XX2_DEVICE_FORMATS, 1234 }, 1235 .ops = &tac_dai_ops, 1236 .symmetric_rate = 1, 1237 }, 1238 { 1239 .name = "tac5xx2-aif2", 1240 .id = TAC5XX2_DMIC, 1241 .capture = { 1242 .stream_name = "DP3 Mic Capture", 1243 .channels_min = 1, 1244 .channels_max = 4, 1245 .rates = TAC5XX2_DEVICE_RATES, 1246 .formats = TAC5XX2_DEVICE_FORMATS, 1247 }, 1248 .ops = &tac_dai_ops, 1249 }, 1250 { 1251 .name = "tac5xx2-aif3", 1252 .id = TAC5XX2_UAJ, 1253 .playback = { 1254 .stream_name = "DP4 UAJ Speaker Playback", 1255 .channels_min = 1, 1256 .channels_max = 2, 1257 .rates = TAC5XX2_DEVICE_RATES, 1258 .formats = TAC5XX2_DEVICE_FORMATS, 1259 }, 1260 .capture = { 1261 .stream_name = "DP7 UAJ Mic Capture", 1262 .channels_min = 1, 1263 .channels_max = 2, 1264 .rates = TAC5XX2_DEVICE_RATES, 1265 .formats = TAC5XX2_DEVICE_FORMATS, 1266 }, 1267 .ops = &tac_dai_ops, 1268 }, 1269 }; 1270 1271 static struct snd_soc_dai_driver tac5682_dai_driver[] = { 1272 { 1273 .name = "tac5xx2-aif1", 1274 .id = TAC5XX2_SPK, 1275 .playback = { 1276 .stream_name = "DP1 Speaker Playback", 1277 .channels_min = 1, 1278 .channels_max = 2, 1279 .rates = TAC5XX2_DEVICE_RATES, 1280 .formats = TAC5XX2_DEVICE_FORMATS, 1281 }, 1282 .capture = { 1283 .stream_name = "DP2 Echo Reference Capture", 1284 .channels_min = 1, 1285 .channels_max = 4, 1286 .rates = TAC5XX2_DEVICE_RATES, 1287 .formats = TAC5XX2_DEVICE_FORMATS, 1288 }, 1289 .ops = &tac_dai_ops, 1290 .symmetric_rate = 1, 1291 }, 1292 { 1293 .name = "tac5xx2-aif2", 1294 .id = TAC5XX2_DMIC, 1295 .capture = { 1296 .stream_name = "DP3 Mic Capture", 1297 .channels_min = 1, 1298 .channels_max = 4, 1299 .rates = TAC5XX2_DEVICE_RATES, 1300 .formats = TAC5XX2_DEVICE_FORMATS, 1301 }, 1302 .ops = &tac_dai_ops, 1303 }, 1304 { 1305 .name = "tac5xx2-aif3", 1306 .id = TAC5XX2_UAJ, 1307 .playback = { 1308 .stream_name = "DP4 UAJ Speaker Playback", 1309 .channels_min = 1, 1310 .channels_max = 2, 1311 .rates = TAC5XX2_DEVICE_RATES, 1312 .formats = TAC5XX2_DEVICE_FORMATS, 1313 }, 1314 .capture = { 1315 .stream_name = "DP7 UAJ Mic Capture", 1316 .channels_min = 1, 1317 .channels_max = 2, 1318 .rates = TAC5XX2_DEVICE_RATES, 1319 .formats = TAC5XX2_DEVICE_FORMATS, 1320 }, 1321 .ops = &tac_dai_ops, 1322 }, 1323 }; 1324 1325 static struct snd_soc_dai_driver tas2883_dai_driver[] = { 1326 { 1327 .name = "tac5xx2-aif1", 1328 .id = TAC5XX2_SPK, 1329 .playback = { 1330 .stream_name = "DP1 Speaker Playback", 1331 .channels_min = 1, 1332 .channels_max = 2, 1333 .rates = TAC5XX2_DEVICE_RATES, 1334 .formats = TAC5XX2_DEVICE_FORMATS, 1335 }, 1336 .ops = &tac_dai_ops, 1337 .symmetric_rate = 1, 1338 }, 1339 { 1340 .name = "tac5xx2-aif2", 1341 .id = TAC5XX2_DMIC, 1342 .capture = { 1343 .stream_name = "DP3 Mic Capture", 1344 .channels_min = 1, 1345 .channels_max = 4, 1346 .rates = TAC5XX2_DEVICE_RATES, 1347 .formats = TAC5XX2_DEVICE_FORMATS, 1348 }, 1349 .ops = &tac_dai_ops, 1350 }, 1351 }; 1352 1353 static s32 tac_component_probe(struct snd_soc_component *component) 1354 { 1355 struct tac5xx2_prv *tac_dev = snd_soc_component_get_drvdata(component); 1356 int ret; 1357 1358 ret = pm_runtime_resume(component->dev); 1359 if (ret < 0 && ret != -EACCES) 1360 return ret; 1361 1362 if (!tac_has_uaj_support(tac_dev)) 1363 goto done_comp_probe; 1364 1365 ret = snd_soc_dapm_new_controls(snd_soc_component_to_dapm(component), 1366 tac_uaj_widgets, 1367 ARRAY_SIZE(tac_uaj_widgets)); 1368 if (ret) { 1369 dev_err(component->dev, "Failed to add UAJ widgets: %d\n", ret); 1370 return ret; 1371 } 1372 1373 ret = snd_soc_dapm_add_routes(snd_soc_component_to_dapm(component), 1374 tac_uaj_routes, ARRAY_SIZE(tac_uaj_routes)); 1375 if (ret) { 1376 dev_err(component->dev, "Failed to add UAJ routes: %d\n", ret); 1377 return ret; 1378 } 1379 1380 ret = snd_soc_add_component_controls(component, tac_uaj_controls, 1381 ARRAY_SIZE(tac_uaj_controls)); 1382 if (ret) { 1383 dev_err(component->dev, "Failed to add UAJ controls: %d\n", ret); 1384 return ret; 1385 } 1386 1387 done_comp_probe: 1388 tac_dev->component = component; 1389 return 0; 1390 } 1391 1392 static void tac_component_remove(struct snd_soc_component *codec) 1393 { 1394 struct tac5xx2_prv *tac_dev = snd_soc_component_get_drvdata(codec); 1395 1396 tac_dev->component = NULL; 1397 } 1398 1399 static const struct snd_soc_component_driver soc_codec_driver_tacdevice = { 1400 .probe = tac_component_probe, 1401 .remove = tac_component_remove, 1402 .controls = tac5xx2_snd_controls, 1403 .num_controls = ARRAY_SIZE(tac5xx2_snd_controls), 1404 .dapm_widgets = tac5xx2_common_widgets, 1405 .num_dapm_widgets = ARRAY_SIZE(tac5xx2_common_widgets), 1406 .dapm_routes = tac5xx2_common_routes, 1407 .num_dapm_routes = ARRAY_SIZE(tac5xx2_common_routes), 1408 .idle_bias_on = 0, 1409 .endianness = 1, 1410 }; 1411 1412 static s32 tac_init(struct tac5xx2_prv *tac_dev) 1413 { 1414 struct snd_soc_component_driver *component_driver; 1415 struct snd_soc_dai_driver *dai_drv; 1416 int num_dais; 1417 s32 ret; 1418 1419 dev_set_drvdata(tac_dev->dev, tac_dev); 1420 1421 switch (tac_dev->part_id) { 1422 case 0x5572: 1423 dai_drv = tac5572_dai_driver; 1424 num_dais = ARRAY_SIZE(tac5572_dai_driver); 1425 break; 1426 case 0x5672: 1427 dai_drv = tac5672_dai_driver; 1428 num_dais = ARRAY_SIZE(tac5672_dai_driver); 1429 break; 1430 case 0x5682: 1431 dai_drv = tac5682_dai_driver; 1432 num_dais = ARRAY_SIZE(tac5682_dai_driver); 1433 break; 1434 case 0x2883: 1435 dai_drv = tas2883_dai_driver; 1436 num_dais = ARRAY_SIZE(tas2883_dai_driver); 1437 break; 1438 default: 1439 dev_err(tac_dev->dev, "Unsupported device: 0x%x\n", 1440 tac_dev->part_id); 1441 return -EINVAL; 1442 } 1443 1444 component_driver = devm_kzalloc(tac_dev->dev, sizeof(*component_driver), 1445 GFP_KERNEL); 1446 if (!component_driver) 1447 return -ENOMEM; 1448 1449 memcpy(component_driver, &soc_codec_driver_tacdevice, sizeof(*component_driver)); 1450 if (tac_has_uaj_support(tac_dev)) 1451 component_driver->set_jack = tac5xx2_set_jack; 1452 1453 ret = devm_snd_soc_register_component(tac_dev->dev, component_driver, 1454 dai_drv, num_dais); 1455 if (ret) { 1456 dev_err(tac_dev->dev, "%s: codec register error:%d.\n", 1457 __func__, ret); 1458 return ret; 1459 } 1460 1461 return 0; 1462 } 1463 1464 static s32 tac5xx2_sdca_dev_suspend(struct device *dev) 1465 { 1466 struct tac5xx2_prv *tac_dev = dev_get_drvdata(dev); 1467 1468 if (!tac_dev->hw_init) 1469 return 0; 1470 1471 regcache_cache_only(tac_dev->regmap, true); 1472 return 0; 1473 } 1474 1475 static s32 tac5xx2_sdca_dev_system_suspend(struct device *dev) 1476 { 1477 return tac5xx2_sdca_dev_suspend(dev); 1478 } 1479 1480 static s32 tac5xx2_sdca_dev_resume(struct device *dev) 1481 { 1482 struct tac5xx2_prv *tac_dev = dev_get_drvdata(dev); 1483 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1484 int ret; 1485 1486 if (!tac_dev->first_hw_init_done) { 1487 dev_dbg(dev, "Device not initialized yet, skipping resume sync\n"); 1488 return 0; 1489 } 1490 1491 ret = sdw_slave_wait_for_init(slave, TAC5XX2_PROBE_TIMEOUT_MS); 1492 if (ret) { 1493 sdw_show_ping_status(slave->bus, true); 1494 return ret; 1495 } 1496 1497 regcache_cache_only(tac_dev->regmap, false); 1498 regcache_mark_dirty(tac_dev->regmap); 1499 ret = regcache_sync(tac_dev->regmap); 1500 if (ret < 0) 1501 dev_warn(dev, "Failed to sync regcache: %d\n", ret); 1502 1503 /* Detect and set jack type for UAJ path before playback. 1504 * This is required as jack detection does not trigger interrupt 1505 * when device is in runtime_pm suspend with bus in clock stop mode. 1506 */ 1507 if (tac_has_uaj_support(tac_dev)) 1508 tac5xx2_sdca_headset_detect(tac_dev); 1509 1510 return 0; 1511 } 1512 1513 static const struct dev_pm_ops tac5xx2_sdca_pm = { 1514 SYSTEM_SLEEP_PM_OPS(tac5xx2_sdca_dev_system_suspend, tac5xx2_sdca_dev_resume) 1515 RUNTIME_PM_OPS(tac5xx2_sdca_dev_suspend, tac5xx2_sdca_dev_resume, NULL) 1516 }; 1517 1518 static s32 tac_fw_read_hdr(const u8 *data, struct tac_fw_hdr *hdr) 1519 { 1520 hdr->size = get_unaligned_le32(data); 1521 hdr->version_offset = get_unaligned_le32(data + 4); 1522 hdr->plt_id = get_unaligned_le32(data + 8); 1523 hdr->ppc3_ver = get_unaligned_le32(data + 12); 1524 memcpy(hdr->ddc_name, data + 16, 64); 1525 hdr->ddc_name[63] = 0; 1526 hdr->timestamp = get_unaligned_le64(data + 80); 1527 1528 return TAC_FW_HDR_SIZE; 1529 } 1530 1531 static s32 tac_fw_get_next_file(const u8 *data, size_t data_size, struct tac_fw_file *file) 1532 { 1533 u32 file_length; 1534 1535 /* Validate file header size */ 1536 if (data_size < TAC_FW_FILE_HDR) 1537 return -EINVAL; 1538 1539 file->vendor_id = get_unaligned_le32(&data[0]); 1540 file->file_id = get_unaligned_le32(&data[4]); 1541 file->version = get_unaligned_le32(&data[8]); 1542 file->length = get_unaligned_le32(&data[12]); 1543 file->dest_addr = get_unaligned_le32(&data[16]); 1544 file_length = file->length; 1545 1546 /* Validate file payload exists */ 1547 if (data_size < TAC_FW_FILE_HDR + file_length) 1548 return -EINVAL; 1549 1550 file->fw_data = (u8 *)&data[20]; 1551 1552 return file_length + sizeof(u32) * 5; 1553 } 1554 1555 static void tac5xx2_fw_ready(const struct firmware *fmw, void *context) 1556 { 1557 struct tac5xx2_prv *tac_dev = context; 1558 struct tac_fw_file *files; 1559 u32 fw_hdr_size; 1560 u32 num_files = 0; 1561 struct tac_fw_hdr hdr; 1562 struct tm tm_time; 1563 size_t img_sz; 1564 u32 offset; 1565 s32 ret = 0; 1566 u8 *buf; 1567 1568 if (!fmw || !fmw->data || fmw->size == 0 || fmw->size < TAC_FW_HDR_SIZE + TAC_FW_FILE_HDR) { 1569 dev_err(tac_dev->dev, "fw file: %s is empty or invalid\n", 1570 tac_dev->fw_binaryname); 1571 goto out; 1572 } 1573 1574 /* Verify firmware size from header */ 1575 fw_hdr_size = get_unaligned_le32(fmw->data); 1576 if (fw_hdr_size != fmw->size) { 1577 dev_err(tac_dev->dev, "firmware size mismatch: hdr=%u, actual=%zu\n", 1578 fw_hdr_size, fmw->size); 1579 goto out; 1580 } 1581 1582 files = devm_kzalloc(tac_dev->dev, sizeof(*files) * TAC_MAX_FW_CHUNKS, GFP_KERNEL); 1583 buf = devm_kmemdup(tac_dev->dev, fmw->data, fmw->size, GFP_KERNEL); 1584 if (!files || !buf) 1585 goto out; 1586 1587 /* validate the cache the firmware */ 1588 img_sz = fmw->size; 1589 offset = tac_fw_read_hdr(buf, &hdr); 1590 while (offset < img_sz && num_files < TAC_MAX_FW_CHUNKS) { 1591 u32 file_length; 1592 1593 if (offset + TAC_FW_FILE_HDR > img_sz) { 1594 dev_warn(tac_dev->dev, "Incomplete block header at offset %d\n", 1595 offset); 1596 goto out; 1597 } 1598 /* Validate that the file payload doesn't exceed buffer */ 1599 file_length = get_unaligned_le32(&buf[offset + 12]); 1600 /* Check for integer overflow and buffer bounds */ 1601 if (file_length > img_sz || offset > img_sz - TAC_FW_FILE_HDR || 1602 file_length > img_sz - offset - TAC_FW_FILE_HDR) { 1603 dev_warn(tac_dev->dev, "File at offset %d exceeds buffer: length=%u, available=%zu\n", 1604 offset, file_length, img_sz - offset - TAC_FW_FILE_HDR); 1605 goto out; 1606 } 1607 ret = tac_fw_get_next_file(&buf[offset], img_sz - offset, &files[num_files]); 1608 if (ret < 0) { 1609 dev_err(tac_dev->dev, "Failed to parse file at offset %d\n", offset); 1610 goto out; 1611 } 1612 offset += ret; 1613 num_files++; 1614 } 1615 1616 if (num_files == 0) { 1617 dev_err(tac_dev->dev, "firmware with no files\n"); 1618 goto out; 1619 } 1620 1621 /* cache ready to use validated firmware */ 1622 tac_dev->fw_file_cnt = num_files; 1623 tac_dev->fw_files = files; 1624 1625 time64_to_tm(hdr.timestamp, 0, &tm_time); 1626 dev_dbg(tac_dev->dev, "fw file: %s, num_files=%u, ts:%04ld-%02d-%02d %02d:%02d\n", 1627 tac_dev->fw_binaryname, tac_dev->fw_file_cnt, 1628 tm_time.tm_year + 1900, tm_time.tm_mon + 1, tm_time.tm_mday, 1629 tm_time.tm_hour, tm_time.tm_min); 1630 dev_dbg(tac_dev->dev, "fw file: DDC Name: %s\n", hdr.ddc_name); 1631 dev_dbg(tac_dev->dev, "fw file: PPC3 Version: 3.%ld.%ld.%ld\n", 1632 FIELD_GET(GENMASK(31, 24), hdr.ppc3_ver), 1633 FIELD_GET(GENMASK(23, 16), hdr.ppc3_ver), 1634 FIELD_GET(GENMASK(15, 8), hdr.ppc3_ver) & 0x3f); 1635 1636 out: 1637 complete_all(&tac_dev->fw_caching_complete); 1638 if (fmw) 1639 release_firmware(fmw); 1640 } 1641 1642 static int tac_load_and_cache_firmware_async(struct tac5xx2_prv *tac_dev) 1643 { 1644 tac_dev->fw_file_cnt = 0; 1645 tac_dev->fw_files = NULL; /* ready to download files */ 1646 1647 return request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT, 1648 tac_dev->fw_binaryname, tac_dev->dev, 1649 GFP_KERNEL, tac_dev, tac5xx2_fw_ready); 1650 } 1651 1652 static int tac_download(struct tac5xx2_prv *tac_dev) 1653 { 1654 struct tac_fw_file *files = tac_dev->fw_files; 1655 u32 num_files = tac_dev->fw_file_cnt; 1656 u32 i; 1657 int ret = 0; 1658 1659 for (i = 0; i < num_files; i++) { 1660 ret = sdw_nwrite_no_pm(tac_dev->sdw_peripheral, files[i].dest_addr, 1661 files[i].length, files[i].fw_data); 1662 if (ret < 0) { 1663 dev_dbg(tac_dev->dev, 1664 "FW write failed at addr 0x%x: %d\n", 1665 files[i].dest_addr, ret); 1666 return ret; 1667 } 1668 } 1669 1670 return 0; 1671 } 1672 1673 /* 1674 * tac5xx2 uses custom firmware binary fw. 1675 * This is not using UMP File Download. 1676 */ 1677 static s32 tac_download_fw_to_hw(struct tac5xx2_prv *tac_dev) 1678 { 1679 int ret; 1680 1681 ret = tac_download(tac_dev); 1682 if (ret < 0) { 1683 dev_err(tac_dev->dev, "Firmware download failed: %d\n", ret); 1684 return ret; 1685 } 1686 1687 dev_dbg(tac_dev->dev, "Firmware download complete: %d chunks\n", 1688 tac_dev->fw_file_cnt); 1689 tac_dev->fw_dl_success = true; 1690 1691 return 0; 1692 } 1693 1694 static struct pci_dev *tac_get_pci_dev(struct sdw_slave *peripheral) 1695 { 1696 struct device *dev = &peripheral->dev; 1697 1698 for (; dev; dev = dev->parent) { 1699 if (dev_is_pci(dev)) 1700 return to_pci_dev(dev); 1701 } 1702 1703 return NULL; 1704 } 1705 1706 static void tac_generate_fw_name(struct sdw_slave *slave, char *name, size_t size) 1707 { 1708 struct sdw_bus *bus = slave->bus; 1709 u16 part_id = slave->id.part_id; 1710 u8 unique_id = slave->id.unique_id; 1711 struct pci_dev *pci = tac_get_pci_dev(slave); 1712 1713 if (pci) 1714 scnprintf(name, size, "%04X-%04X-%1X-%1X.bin", part_id, 1715 pci->subsystem_device, bus->link_id, unique_id); 1716 else 1717 /* Default firmware name based on part ID */ 1718 scnprintf(name, size, "%s%04x-%1X-%1X.bin", 1719 part_id == 0x2883 ? "tas" : "tac", 1720 part_id, bus->link_id, unique_id); 1721 } 1722 1723 static int tac_io_init(struct device *dev, struct sdw_slave *slave, bool first) 1724 { 1725 struct tac5xx2_prv *tac_dev = dev_get_drvdata(dev); 1726 u64 time; 1727 int ret; 1728 1729 if (tac_dev->hw_init) { 1730 dev_dbg(dev, "early return hw_init already done.."); 1731 return 0; 1732 } 1733 1734 time = wait_for_completion_timeout(&tac_dev->fw_caching_complete, 1735 msecs_to_jiffies(TAC5XX2_FW_CACHE_TIMEOUT_MS)); 1736 if (!time) { 1737 ret = -ETIMEDOUT; 1738 dev_warn(tac_dev->dev, "%s: fw caching timeout\n", __func__); 1739 goto io_init_err; 1740 } 1741 1742 if (!tac_dev->rev_id) { 1743 ret = regmap_read(tac_dev->regmap, TAC_REV_ID, &tac_dev->rev_id); 1744 if (ret) { 1745 dev_err(tac_dev->dev, "failed to rev id, err=%d\n", ret); 1746 goto io_init_err; 1747 } 1748 dev_dbg(tac_dev->dev, "detected rev_id 0x%x", tac_dev->rev_id); 1749 } 1750 1751 if (tac_dev->fw_files && tac_dev->fw_file_cnt > 0) { 1752 ret = tac_download_fw_to_hw(tac_dev); 1753 if (ret) { 1754 dev_err(tac_dev->dev, "FW download failed, fw: %d\n", ret); 1755 goto io_init_err; 1756 } 1757 } 1758 1759 if (tac_dev->sa_func_data) { 1760 ret = sdca_regmap_write_init(dev, tac_dev->regmap, 1761 tac_dev->sa_func_data); 1762 if (ret) { 1763 dev_err(dev, "smartamp init table update failed\n"); 1764 goto io_init_err; 1765 } 1766 dev_dbg(dev, "smartamp init done\n"); 1767 1768 if (first) { 1769 ret = regmap_multi_reg_write(tac_dev->regmap, tac_spk_seq, 1770 ARRAY_SIZE(tac_spk_seq)); 1771 if (ret) { 1772 dev_err(dev, "init writes failed, err=%d", ret); 1773 goto io_init_err; 1774 } 1775 } 1776 } 1777 1778 if (tac_dev->sm_func_data) { 1779 ret = sdca_regmap_write_init(dev, tac_dev->regmap, 1780 tac_dev->sm_func_data); 1781 if (ret) { 1782 dev_err(dev, "smartmic init table update failed\n"); 1783 goto io_init_err; 1784 } 1785 dev_dbg(dev, "smartmic init done\n"); 1786 } 1787 1788 if (tac_dev->uaj_func_data) { 1789 ret = sdca_regmap_write_init(dev, tac_dev->regmap, 1790 tac_dev->uaj_func_data); 1791 if (ret) { 1792 dev_err(dev, "uaj init table update failed\n"); 1793 goto io_init_err; 1794 } 1795 dev_dbg(dev, "uaj init done\n"); 1796 1797 if (first) { 1798 if (tac_dev->hs_jack) { 1799 ret = tac5xx2_jack_init(tac_dev); 1800 if (ret) { 1801 dev_err(tac_dev->dev, "jack init failed"); 1802 goto io_init_err; 1803 } 1804 } 1805 } 1806 } 1807 1808 if (tac_dev->hid_func_data) { 1809 ret = sdca_regmap_write_init(dev, tac_dev->regmap, 1810 tac_dev->hid_func_data); 1811 if (ret) { 1812 dev_err(dev, "hid init table update failed\n"); 1813 goto io_init_err; 1814 } 1815 dev_dbg(dev, "hid init done\n"); 1816 } 1817 1818 tac_dev->hw_init = true; 1819 1820 return 0; 1821 1822 io_init_err: 1823 dev_err(dev, "init writes failed, err=%d", ret); 1824 return ret; 1825 } 1826 1827 static int tac_update_status(struct sdw_slave *slave, 1828 enum sdw_slave_status status) 1829 { 1830 struct tac5xx2_prv *tac_dev = dev_get_drvdata(&slave->dev); 1831 struct device *dev = &slave->dev; 1832 bool first = false; 1833 int ret; 1834 1835 tac_dev->status = status; 1836 if (status == SDW_SLAVE_UNATTACHED) { 1837 tac_dev->hw_init = false; 1838 tac_dev->fw_dl_success = false; 1839 } 1840 1841 if (tac_dev->hw_init || tac_dev->status != SDW_SLAVE_ATTACHED) { 1842 dev_dbg(dev, "%s: early return, hw_init=%d, status=%d", 1843 __func__, tac_dev->hw_init, tac_dev->status); 1844 return 0; 1845 } 1846 1847 if (!tac_dev->first_hw_init_done) { 1848 pm_runtime_set_active(tac_dev->dev); 1849 tac_dev->first_hw_init_done = true; 1850 first = true; 1851 } 1852 1853 pm_runtime_get_noresume(tac_dev->dev); 1854 1855 regcache_mark_dirty(tac_dev->regmap); 1856 regcache_cache_only(tac_dev->regmap, false); 1857 ret = tac_io_init(&slave->dev, slave, first); 1858 if (ret) { 1859 dev_err(dev, "Device initialization failed: %d\n", ret); 1860 goto err_out; 1861 } 1862 1863 ret = regcache_sync(tac_dev->regmap); 1864 if (ret) 1865 dev_warn(dev, "Failed to sync regcache after init: %d\n", ret); 1866 1867 err_out: 1868 pm_runtime_mark_last_busy(tac_dev->dev); 1869 pm_runtime_put_autosuspend(tac_dev->dev); 1870 1871 return ret; 1872 } 1873 1874 static int tac5xx2_sdw_read_prop(struct sdw_slave *peripheral) 1875 { 1876 struct device *dev = &peripheral->dev; 1877 int ret; 1878 1879 ret = sdw_slave_read_prop(peripheral); 1880 if (ret) { 1881 dev_err(dev, "sdw_slave_read_prop failed: %d", ret); 1882 return ret; 1883 } 1884 1885 return 0; 1886 } 1887 1888 static int tac_port_prep(struct sdw_slave *slave, struct sdw_prepare_ch *prep_ch, 1889 enum sdw_port_prep_ops pre_ops) 1890 { 1891 struct device *dev = &slave->dev; 1892 struct tac5xx2_prv *tac_dev = dev_get_drvdata(dev); 1893 unsigned int val; 1894 int ret; 1895 1896 if (pre_ops != SDW_OPS_PORT_POST_PREP) 1897 return 0; 1898 1899 if (!tac_dev->fw_dl_success) 1900 return 0; 1901 1902 ret = regmap_read(tac_dev->regmap, TAC_DSP_ALGO_STATUS, &val); 1903 if (ret) { 1904 dev_err(dev, "Failed to read algo status: %d\n", ret); 1905 return ret; 1906 } 1907 1908 if (val != TAC_DSP_ALGO_STATUS_RUNNING) { 1909 dev_dbg(dev, "Algo not running (0x%02x), re-enabling\n", val); 1910 ret = regmap_write(tac_dev->regmap, TAC_DSP_ALGO_STATUS, 1911 TAC_DSP_ALGO_STATUS_RUNNING); 1912 if (ret) { 1913 dev_err(dev, "Failed to re-enable algo: %d\n", ret); 1914 return ret; 1915 } 1916 } 1917 1918 return 0; 1919 } 1920 1921 static const struct sdw_slave_ops tac_sdw_ops = { 1922 .read_prop = tac5xx2_sdw_read_prop, 1923 .update_status = tac_update_status, 1924 .interrupt_callback = tac_interrupt_callback, 1925 .port_prep = tac_port_prep, 1926 }; 1927 1928 static s32 tac_sdw_probe(struct sdw_slave *peripheral, 1929 const struct sdw_device_id *id) 1930 { 1931 struct sdca_function_data *function_data = NULL; 1932 struct device *dev = &peripheral->dev; 1933 struct tac5xx2_prv *tac_dev; 1934 struct regmap *regmap; 1935 int ret, i; 1936 1937 tac_dev = devm_kzalloc(dev, sizeof(*tac_dev), GFP_KERNEL); 1938 if (!tac_dev) 1939 return dev_err_probe(dev, -ENOMEM, 1940 "Failed devm_kzalloc"); 1941 1942 if (peripheral->sdca_data.num_functions > 0) { 1943 dev_dbg(dev, "SDCA functions found: %d", 1944 peripheral->sdca_data.num_functions); 1945 1946 for (i = 0; i < peripheral->sdca_data.num_functions; i++) { 1947 struct sdca_function_data **func_ptr; 1948 const char *func_name; 1949 1950 switch (peripheral->sdca_data.function[i].type) { 1951 case SDCA_FUNCTION_TYPE_SMART_AMP: 1952 func_ptr = &tac_dev->sa_func_data; 1953 func_name = "smartamp"; 1954 break; 1955 case SDCA_FUNCTION_TYPE_SMART_MIC: 1956 func_ptr = &tac_dev->sm_func_data; 1957 func_name = "smartmic"; 1958 break; 1959 case SDCA_FUNCTION_TYPE_UAJ: 1960 func_ptr = &tac_dev->uaj_func_data; 1961 func_name = "uaj"; 1962 break; 1963 case SDCA_FUNCTION_TYPE_HID: 1964 func_ptr = &tac_dev->hid_func_data; 1965 func_name = "hid"; 1966 break; 1967 default: 1968 continue; 1969 } 1970 1971 function_data = devm_kzalloc(dev, sizeof(*function_data), 1972 GFP_KERNEL); 1973 if (!function_data) 1974 return dev_err_probe(dev, -ENOMEM, 1975 "failed to allocate %s function data", 1976 func_name); 1977 function_data->desc = &peripheral->sdca_data.function[i]; 1978 ret = sdca_parse_function(dev, function_data); 1979 if (!ret) 1980 *func_ptr = function_data; 1981 else 1982 devm_kfree(dev, function_data); 1983 } 1984 } 1985 1986 dev_dbg(dev, "SDCA functions enabled: SA=%s SM=%s UAJ=%s HID=%s", 1987 tac_dev->sa_func_data ? "yes" : "no", 1988 tac_dev->sm_func_data ? "yes" : "no", 1989 tac_dev->uaj_func_data ? "yes" : "no", 1990 tac_dev->hid_func_data ? "yes" : "no"); 1991 1992 tac_dev->dev = dev; 1993 tac_dev->sdw_peripheral = peripheral; 1994 tac_dev->hw_init = false; 1995 tac_dev->first_hw_init_done = false; 1996 tac_dev->part_id = id->part_id; 1997 tac_dev->rev_id = 0x0; 1998 dev_set_drvdata(dev, tac_dev); 1999 2000 regmap = devm_regmap_init_sdw_mbq_cfg(&peripheral->dev, peripheral, 2001 &tac_regmap, &tac_mbq_cfg); 2002 if (IS_ERR(regmap)) 2003 return dev_err_probe(dev, PTR_ERR(regmap), 2004 "Failed devm_regmap_init_sdw\n"); 2005 2006 regcache_cache_only(regmap, true); 2007 tac_dev->regmap = regmap; 2008 tac_dev->jack_type = 0; 2009 init_completion(&tac_dev->fw_caching_complete); 2010 2011 tac_generate_fw_name(peripheral, tac_dev->fw_binaryname, 2012 sizeof(tac_dev->fw_binaryname)); 2013 2014 ret = tac_load_and_cache_firmware_async(tac_dev); 2015 if (ret) { 2016 complete_all(&tac_dev->fw_caching_complete); 2017 dev_dbg(dev, "failed to load fw: %d, use rom mode\n", ret); 2018 } 2019 2020 ret = tac_init(tac_dev); 2021 if (ret) 2022 return dev_err_probe(dev, ret, 2023 "failed to initialize tac device\n"); 2024 2025 /* set autosuspend parameters */ 2026 pm_runtime_set_autosuspend_delay(dev, 3000); 2027 pm_runtime_use_autosuspend(dev); 2028 2029 /* make sure the device does not suspend immediately */ 2030 pm_runtime_mark_last_busy(dev); 2031 2032 pm_runtime_enable(dev); 2033 /* the device is still not in active */ 2034 2035 return 0; 2036 } 2037 2038 static void tac_sdw_remove(struct sdw_slave *peripheral) 2039 { 2040 struct tac5xx2_prv *tac_dev = dev_get_drvdata(&peripheral->dev); 2041 2042 pm_runtime_disable(tac_dev->dev); 2043 2044 dev_set_drvdata(&peripheral->dev, NULL); 2045 } 2046 2047 static const struct sdw_device_id tac_sdw_id[] = { 2048 SDW_SLAVE_ENTRY(0x0102, 0x5572, 0), 2049 SDW_SLAVE_ENTRY(0x0102, 0x5672, 0), 2050 SDW_SLAVE_ENTRY(0x0102, 0x5682, 0), 2051 SDW_SLAVE_ENTRY(0x0102, 0x2883, 0), 2052 {}, 2053 }; 2054 MODULE_DEVICE_TABLE(sdw, tac_sdw_id); 2055 2056 static struct sdw_driver tac_sdw_driver = { 2057 .driver = { 2058 .name = "slave-tac5xx2", 2059 .pm = pm_ptr(&tac5xx2_sdca_pm), 2060 }, 2061 .probe = tac_sdw_probe, 2062 .remove = tac_sdw_remove, 2063 .ops = &tac_sdw_ops, 2064 .id_table = tac_sdw_id, 2065 }; 2066 module_sdw_driver(tac_sdw_driver); 2067 2068 MODULE_IMPORT_NS("SND_SOC_SDCA"); 2069 MODULE_AUTHOR("Texas Instruments Inc."); 2070 MODULE_DESCRIPTION("ASoC TAC5XX2 SoundWire Driver"); 2071 MODULE_LICENSE("GPL"); 2072