1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 /* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */
3
4 #include <linux/bitfield.h>
5 #include <linux/bitops.h>
6 #include <linux/err.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/types.h>
11
12 #include <linux/pinctrl/pinctrl.h>
13 #include <linux/pinctrl/pinmux.h>
14
15 #define MLXBF3_NGPIOS_GPIO0 32
16 #define MLXBF3_MAX_GPIO_PINS 56
17
18 enum {
19 MLXBF3_GPIO_HW_MODE,
20 MLXBF3_GPIO_SW_MODE,
21 };
22
23 struct mlxbf3_pinctrl {
24 void __iomem *fw_ctrl_set0;
25 void __iomem *fw_ctrl_clr0;
26 void __iomem *fw_ctrl_set1;
27 void __iomem *fw_ctrl_clr1;
28 struct device *dev;
29 struct pinctrl_dev *pctl;
30 struct pinctrl_gpio_range gpio_range;
31 };
32
33 #define MLXBF3_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \
34 { \
35 .name = "mlxbf3_gpio_range", \
36 .id = _id, \
37 .base = _gpiobase, \
38 .pin_base = _pinbase, \
39 .npins = _npins, \
40 }
41
42 static struct pinctrl_gpio_range mlxbf3_pinctrl_gpio_ranges[] = {
43 MLXBF3_GPIO_RANGE(0, 0, 480, 32),
44 MLXBF3_GPIO_RANGE(1, 32, 456, 24),
45 };
46
47 static const struct pinctrl_pin_desc mlxbf3_pins[] = {
48 PINCTRL_PIN(0, "gpio0"),
49 PINCTRL_PIN(1, "gpio1"),
50 PINCTRL_PIN(2, "gpio2"),
51 PINCTRL_PIN(3, "gpio3"),
52 PINCTRL_PIN(4, "gpio4"),
53 PINCTRL_PIN(5, "gpio5"),
54 PINCTRL_PIN(6, "gpio6"),
55 PINCTRL_PIN(7, "gpio7"),
56 PINCTRL_PIN(8, "gpio8"),
57 PINCTRL_PIN(9, "gpio9"),
58 PINCTRL_PIN(10, "gpio10"),
59 PINCTRL_PIN(11, "gpio11"),
60 PINCTRL_PIN(12, "gpio12"),
61 PINCTRL_PIN(13, "gpio13"),
62 PINCTRL_PIN(14, "gpio14"),
63 PINCTRL_PIN(15, "gpio15"),
64 PINCTRL_PIN(16, "gpio16"),
65 PINCTRL_PIN(17, "gpio17"),
66 PINCTRL_PIN(18, "gpio18"),
67 PINCTRL_PIN(19, "gpio19"),
68 PINCTRL_PIN(20, "gpio20"),
69 PINCTRL_PIN(21, "gpio21"),
70 PINCTRL_PIN(22, "gpio22"),
71 PINCTRL_PIN(23, "gpio23"),
72 PINCTRL_PIN(24, "gpio24"),
73 PINCTRL_PIN(25, "gpio25"),
74 PINCTRL_PIN(26, "gpio26"),
75 PINCTRL_PIN(27, "gpio27"),
76 PINCTRL_PIN(28, "gpio28"),
77 PINCTRL_PIN(29, "gpio29"),
78 PINCTRL_PIN(30, "gpio30"),
79 PINCTRL_PIN(31, "gpio31"),
80 PINCTRL_PIN(32, "gpio32"),
81 PINCTRL_PIN(33, "gpio33"),
82 PINCTRL_PIN(34, "gpio34"),
83 PINCTRL_PIN(35, "gpio35"),
84 PINCTRL_PIN(36, "gpio36"),
85 PINCTRL_PIN(37, "gpio37"),
86 PINCTRL_PIN(38, "gpio38"),
87 PINCTRL_PIN(39, "gpio39"),
88 PINCTRL_PIN(40, "gpio40"),
89 PINCTRL_PIN(41, "gpio41"),
90 PINCTRL_PIN(42, "gpio42"),
91 PINCTRL_PIN(43, "gpio43"),
92 PINCTRL_PIN(44, "gpio44"),
93 PINCTRL_PIN(45, "gpio45"),
94 PINCTRL_PIN(46, "gpio46"),
95 PINCTRL_PIN(47, "gpio47"),
96 PINCTRL_PIN(48, "gpio48"),
97 PINCTRL_PIN(49, "gpio49"),
98 PINCTRL_PIN(50, "gpio50"),
99 PINCTRL_PIN(51, "gpio51"),
100 PINCTRL_PIN(52, "gpio52"),
101 PINCTRL_PIN(53, "gpio53"),
102 PINCTRL_PIN(54, "gpio54"),
103 PINCTRL_PIN(55, "gpio55"),
104 };
105
106 /*
107 * All single-pin functions can be mapped to any GPIO, however pinmux applies
108 * functions to pin groups and only those groups declared as supporting that
109 * function. To make this work we must put each pin in its own dummy group so
110 * that the functions can be described as applying to all pins.
111 * We use the same name as in the datasheet.
112 */
113 static const char * const mlxbf3_pinctrl_single_group_names[] = {
114 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
115 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
116 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
117 "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
118 "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
119 "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
120 "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55",
121 };
122
mlxbf3_get_groups_count(struct pinctrl_dev * pctldev)123 static int mlxbf3_get_groups_count(struct pinctrl_dev *pctldev)
124 {
125 /* Number single-pin groups */
126 return MLXBF3_MAX_GPIO_PINS;
127 }
128
mlxbf3_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)129 static const char *mlxbf3_get_group_name(struct pinctrl_dev *pctldev,
130 unsigned int selector)
131 {
132 return mlxbf3_pinctrl_single_group_names[selector];
133 }
134
mlxbf3_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)135 static int mlxbf3_get_group_pins(struct pinctrl_dev *pctldev,
136 unsigned int selector,
137 const unsigned int **pins,
138 unsigned int *num_pins)
139 {
140 /* return the dummy group for a single pin */
141 *pins = &selector;
142 *num_pins = 1;
143
144 return 0;
145 }
146
147 static const struct pinctrl_ops mlxbf3_pinctrl_group_ops = {
148 .get_groups_count = mlxbf3_get_groups_count,
149 .get_group_name = mlxbf3_get_group_name,
150 .get_group_pins = mlxbf3_get_group_pins,
151 };
152
153 /*
154 * Only 2 functions are supported and they apply to all pins:
155 * 1) Default hardware functionality
156 * 2) Software controlled GPIO
157 */
158 static const char * const mlxbf3_gpiofunc_group_names[] = { "swctrl" };
159 static const char * const mlxbf3_hwfunc_group_names[] = { "hwctrl" };
160
161 static struct pinfunction mlxbf3_pmx_funcs[] = {
162 PINCTRL_PINFUNCTION("hwfunc", mlxbf3_hwfunc_group_names, 1),
163 PINCTRL_PINFUNCTION("gpiofunc", mlxbf3_gpiofunc_group_names, 1),
164 };
165
mlxbf3_pmx_get_funcs_count(struct pinctrl_dev * pctldev)166 static int mlxbf3_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
167 {
168 return ARRAY_SIZE(mlxbf3_pmx_funcs);
169 }
170
mlxbf3_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned int selector)171 static const char *mlxbf3_pmx_get_func_name(struct pinctrl_dev *pctldev,
172 unsigned int selector)
173 {
174 return mlxbf3_pmx_funcs[selector].name;
175 }
176
mlxbf3_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)177 static int mlxbf3_pmx_get_groups(struct pinctrl_dev *pctldev,
178 unsigned int selector,
179 const char * const **groups,
180 unsigned int * const num_groups)
181 {
182 *groups = mlxbf3_pmx_funcs[selector].groups;
183 *num_groups = MLXBF3_MAX_GPIO_PINS;
184
185 return 0;
186 }
187
mlxbf3_pmx_set(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)188 static int mlxbf3_pmx_set(struct pinctrl_dev *pctldev,
189 unsigned int selector,
190 unsigned int group)
191 {
192 struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
193
194 if (selector == MLXBF3_GPIO_HW_MODE) {
195 if (group < MLXBF3_NGPIOS_GPIO0)
196 writel(BIT(group), priv->fw_ctrl_clr0);
197 else
198 writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1);
199 }
200
201 if (selector == MLXBF3_GPIO_SW_MODE) {
202 if (group < MLXBF3_NGPIOS_GPIO0)
203 writel(BIT(group), priv->fw_ctrl_set0);
204 else
205 writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1);
206 }
207
208 return 0;
209 }
210
mlxbf3_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)211 static int mlxbf3_gpio_request_enable(struct pinctrl_dev *pctldev,
212 struct pinctrl_gpio_range *range,
213 unsigned int offset)
214 {
215 struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
216
217 if (offset < MLXBF3_NGPIOS_GPIO0)
218 writel(BIT(offset), priv->fw_ctrl_set0);
219 else
220 writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1);
221
222 return 0;
223 }
224
225 static const struct pinmux_ops mlxbf3_pmx_ops = {
226 .get_functions_count = mlxbf3_pmx_get_funcs_count,
227 .get_function_name = mlxbf3_pmx_get_func_name,
228 .get_function_groups = mlxbf3_pmx_get_groups,
229 .set_mux = mlxbf3_pmx_set,
230 .gpio_request_enable = mlxbf3_gpio_request_enable,
231 };
232
233 static const struct pinctrl_desc mlxbf3_pin_desc = {
234 .name = "pinctrl-mlxbf3",
235 .pins = mlxbf3_pins,
236 .npins = ARRAY_SIZE(mlxbf3_pins),
237 .pctlops = &mlxbf3_pinctrl_group_ops,
238 .pmxops = &mlxbf3_pmx_ops,
239 .owner = THIS_MODULE,
240 };
241
242 static_assert(ARRAY_SIZE(mlxbf3_pinctrl_single_group_names) == MLXBF3_MAX_GPIO_PINS);
243
mlxbf3_pinctrl_probe(struct platform_device * pdev)244 static int mlxbf3_pinctrl_probe(struct platform_device *pdev)
245 {
246 struct device *dev = &pdev->dev;
247 struct mlxbf3_pinctrl *priv;
248 int ret;
249
250 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
251 if (!priv)
252 return -ENOMEM;
253
254 priv->dev = &pdev->dev;
255
256 priv->fw_ctrl_set0 = devm_platform_ioremap_resource(pdev, 0);
257 if (IS_ERR(priv->fw_ctrl_set0))
258 return PTR_ERR(priv->fw_ctrl_set0);
259
260 priv->fw_ctrl_clr0 = devm_platform_ioremap_resource(pdev, 1);
261 if (IS_ERR(priv->fw_ctrl_clr0))
262 return PTR_ERR(priv->fw_ctrl_clr0);
263
264 priv->fw_ctrl_set1 = devm_platform_ioremap_resource(pdev, 2);
265 if (IS_ERR(priv->fw_ctrl_set1))
266 return PTR_ERR(priv->fw_ctrl_set1);
267
268 priv->fw_ctrl_clr1 = devm_platform_ioremap_resource(pdev, 3);
269 if (IS_ERR(priv->fw_ctrl_clr1))
270 return PTR_ERR(priv->fw_ctrl_clr1);
271
272 ret = devm_pinctrl_register_and_init(dev,
273 &mlxbf3_pin_desc,
274 priv,
275 &priv->pctl);
276 if (ret)
277 return dev_err_probe(dev, ret, "Failed to register pinctrl\n");
278
279 ret = pinctrl_enable(priv->pctl);
280 if (ret)
281 return dev_err_probe(dev, ret, "Failed to enable pinctrl\n");
282
283 pinctrl_add_gpio_ranges(priv->pctl, mlxbf3_pinctrl_gpio_ranges, 2);
284
285 return 0;
286 }
287
288 static const struct acpi_device_id mlxbf3_pinctrl_acpi_ids[] = {
289 { "MLNXBF34", 0 },
290 {}
291 };
292 MODULE_DEVICE_TABLE(acpi, mlxbf3_pinctrl_acpi_ids);
293
294 static struct platform_driver mlxbf3_pinctrl_driver = {
295 .driver = {
296 .name = "pinctrl-mlxbf3",
297 .acpi_match_table = mlxbf3_pinctrl_acpi_ids,
298 },
299 .probe = mlxbf3_pinctrl_probe,
300 };
301 module_platform_driver(mlxbf3_pinctrl_driver);
302
303 MODULE_DESCRIPTION("NVIDIA pinctrl driver");
304 MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
305 MODULE_LICENSE("Dual BSD/GPL");
306