1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for the TI TPS23881 PoE PSE Controller driver (I2C bus)
4 *
5 * Copyright (c) 2023 Bootlin, Kory Maincent <kory.maincent@bootlin.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/delay.h>
10 #include <linux/firmware.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pse-pd/pse.h>
17
18 #define TPS23881_MAX_CHANS 8
19
20 #define TPS23881_REG_PW_STATUS 0x10
21 #define TPS23881_REG_OP_MODE 0x12
22 #define TPS23881_OP_MODE_SEMIAUTO 0xaaaa
23 #define TPS23881_REG_DIS_EN 0x13
24 #define TPS23881_REG_DET_CLA_EN 0x14
25 #define TPS23881_REG_GEN_MASK 0x17
26 #define TPS23881_REG_NBITACC BIT(5)
27 #define TPS23881_REG_PW_EN 0x19
28 #define TPS23881_REG_PORT_MAP 0x26
29 #define TPS23881_REG_PORT_POWER 0x29
30 #define TPS23881_REG_POEPLUS 0x40
31 #define TPS23881_REG_TPON BIT(0)
32 #define TPS23881_REG_FWREV 0x41
33 #define TPS23881_REG_DEVID 0x43
34 #define TPS23881_REG_DEVID_MASK 0xF0
35 #define TPS23881_DEVICE_ID 0x02
36 #define TPS23881_REG_SRAM_CTRL 0x60
37 #define TPS23881_REG_SRAM_DATA 0x61
38
39 struct tps23881_port_desc {
40 u8 chan[2];
41 bool is_4p;
42 };
43
44 struct tps23881_priv {
45 struct i2c_client *client;
46 struct pse_controller_dev pcdev;
47 struct device_node *np;
48 struct tps23881_port_desc port[TPS23881_MAX_CHANS];
49 };
50
to_tps23881_priv(struct pse_controller_dev * pcdev)51 static struct tps23881_priv *to_tps23881_priv(struct pse_controller_dev *pcdev)
52 {
53 return container_of(pcdev, struct tps23881_priv, pcdev);
54 }
55
tps23881_pi_enable(struct pse_controller_dev * pcdev,int id)56 static int tps23881_pi_enable(struct pse_controller_dev *pcdev, int id)
57 {
58 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
59 struct i2c_client *client = priv->client;
60 u8 chan;
61 u16 val;
62 int ret;
63
64 if (id >= TPS23881_MAX_CHANS)
65 return -ERANGE;
66
67 chan = priv->port[id].chan[0];
68 if (chan < 4)
69 val = BIT(chan);
70 else
71 val = BIT(chan + 4);
72
73 if (priv->port[id].is_4p) {
74 chan = priv->port[id].chan[1];
75 if (chan < 4)
76 val |= BIT(chan);
77 else
78 val |= BIT(chan + 4);
79 }
80
81 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PW_EN, val);
82 if (ret)
83 return ret;
84
85 return 0;
86 }
87
tps23881_pi_disable(struct pse_controller_dev * pcdev,int id)88 static int tps23881_pi_disable(struct pse_controller_dev *pcdev, int id)
89 {
90 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
91 struct i2c_client *client = priv->client;
92 u8 chan;
93 u16 val;
94 int ret;
95
96 if (id >= TPS23881_MAX_CHANS)
97 return -ERANGE;
98
99 chan = priv->port[id].chan[0];
100 if (chan < 4)
101 val = BIT(chan + 4);
102 else
103 val = BIT(chan + 8);
104
105 if (priv->port[id].is_4p) {
106 chan = priv->port[id].chan[1];
107 if (chan < 4)
108 val |= BIT(chan + 4);
109 else
110 val |= BIT(chan + 8);
111 }
112
113 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PW_EN, val);
114 if (ret)
115 return ret;
116
117 return 0;
118 }
119
tps23881_pi_is_enabled(struct pse_controller_dev * pcdev,int id)120 static int tps23881_pi_is_enabled(struct pse_controller_dev *pcdev, int id)
121 {
122 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
123 struct i2c_client *client = priv->client;
124 bool enabled;
125 u8 chan;
126 int ret;
127
128 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS);
129 if (ret < 0)
130 return ret;
131
132 chan = priv->port[id].chan[0];
133 if (chan < 4)
134 enabled = ret & BIT(chan);
135 else
136 enabled = ret & BIT(chan + 4);
137
138 if (priv->port[id].is_4p) {
139 chan = priv->port[id].chan[1];
140 if (chan < 4)
141 enabled &= !!(ret & BIT(chan));
142 else
143 enabled &= !!(ret & BIT(chan + 4));
144 }
145
146 /* Return enabled status only if both channel are on this state */
147 return enabled;
148 }
149
tps23881_ethtool_get_status(struct pse_controller_dev * pcdev,unsigned long id,struct netlink_ext_ack * extack,struct pse_control_status * status)150 static int tps23881_ethtool_get_status(struct pse_controller_dev *pcdev,
151 unsigned long id,
152 struct netlink_ext_ack *extack,
153 struct pse_control_status *status)
154 {
155 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
156 struct i2c_client *client = priv->client;
157 bool enabled, delivering;
158 u8 chan;
159 int ret;
160
161 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS);
162 if (ret < 0)
163 return ret;
164
165 chan = priv->port[id].chan[0];
166 if (chan < 4) {
167 enabled = ret & BIT(chan);
168 delivering = ret & BIT(chan + 4);
169 } else {
170 enabled = ret & BIT(chan + 4);
171 delivering = ret & BIT(chan + 8);
172 }
173
174 if (priv->port[id].is_4p) {
175 chan = priv->port[id].chan[1];
176 if (chan < 4) {
177 enabled &= !!(ret & BIT(chan));
178 delivering &= !!(ret & BIT(chan + 4));
179 } else {
180 enabled &= !!(ret & BIT(chan + 4));
181 delivering &= !!(ret & BIT(chan + 8));
182 }
183 }
184
185 /* Return delivering status only if both channel are on this state */
186 if (delivering)
187 status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING;
188 else
189 status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED;
190
191 /* Return enabled status only if both channel are on this state */
192 if (enabled)
193 status->c33_admin_state = ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED;
194 else
195 status->c33_admin_state = ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED;
196
197 return 0;
198 }
199
200 /* Parse managers subnode into a array of device node */
201 static int
tps23881_get_of_channels(struct tps23881_priv * priv,struct device_node * chan_node[TPS23881_MAX_CHANS])202 tps23881_get_of_channels(struct tps23881_priv *priv,
203 struct device_node *chan_node[TPS23881_MAX_CHANS])
204 {
205 struct device_node *channels_node, *node;
206 int i, ret;
207
208 if (!priv->np)
209 return -EINVAL;
210
211 channels_node = of_find_node_by_name(priv->np, "channels");
212 if (!channels_node)
213 return -EINVAL;
214
215 for_each_child_of_node(channels_node, node) {
216 u32 chan_id;
217
218 if (!of_node_name_eq(node, "channel"))
219 continue;
220
221 ret = of_property_read_u32(node, "reg", &chan_id);
222 if (ret) {
223 ret = -EINVAL;
224 goto out;
225 }
226
227 if (chan_id >= TPS23881_MAX_CHANS || chan_node[chan_id]) {
228 dev_err(&priv->client->dev,
229 "wrong number of port (%d)\n", chan_id);
230 ret = -EINVAL;
231 goto out;
232 }
233
234 of_node_get(node);
235 chan_node[chan_id] = node;
236 }
237
238 of_node_put(channels_node);
239 return 0;
240
241 out:
242 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
243 of_node_put(chan_node[i]);
244 chan_node[i] = NULL;
245 }
246
247 of_node_put(node);
248 of_node_put(channels_node);
249 return ret;
250 }
251
252 struct tps23881_port_matrix {
253 u8 pi_id;
254 u8 lgcl_chan[2];
255 u8 hw_chan[2];
256 bool is_4p;
257 bool exist;
258 };
259
260 static int
tps23881_match_channel(const struct pse_pi_pairset * pairset,struct device_node * chan_node[TPS23881_MAX_CHANS])261 tps23881_match_channel(const struct pse_pi_pairset *pairset,
262 struct device_node *chan_node[TPS23881_MAX_CHANS])
263 {
264 int i;
265
266 /* Look on every channels */
267 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
268 if (pairset->np == chan_node[i])
269 return i;
270 }
271
272 return -ENODEV;
273 }
274
275 static bool
tps23881_is_chan_free(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],int chan)276 tps23881_is_chan_free(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],
277 int chan)
278 {
279 int i;
280
281 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
282 if (port_matrix[i].exist &&
283 (port_matrix[i].hw_chan[0] == chan ||
284 port_matrix[i].hw_chan[1] == chan))
285 return false;
286 }
287
288 return true;
289 }
290
291 /* Fill port matrix with the matching channels */
292 static int
tps23881_match_port_matrix(struct pse_pi * pi,int pi_id,struct device_node * chan_node[TPS23881_MAX_CHANS],struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])293 tps23881_match_port_matrix(struct pse_pi *pi, int pi_id,
294 struct device_node *chan_node[TPS23881_MAX_CHANS],
295 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])
296 {
297 int ret;
298
299 if (!pi->pairset[0].np)
300 return 0;
301
302 ret = tps23881_match_channel(&pi->pairset[0], chan_node);
303 if (ret < 0)
304 return ret;
305
306 if (!tps23881_is_chan_free(port_matrix, ret)) {
307 pr_err("tps23881: channel %d already used\n", ret);
308 return -ENODEV;
309 }
310
311 port_matrix[pi_id].hw_chan[0] = ret;
312 port_matrix[pi_id].exist = true;
313
314 if (!pi->pairset[1].np)
315 return 0;
316
317 ret = tps23881_match_channel(&pi->pairset[1], chan_node);
318 if (ret < 0)
319 return ret;
320
321 if (!tps23881_is_chan_free(port_matrix, ret)) {
322 pr_err("tps23881: channel %d already used\n", ret);
323 return -ENODEV;
324 }
325
326 if (port_matrix[pi_id].hw_chan[0] / 4 != ret / 4) {
327 pr_err("tps23881: 4-pair PSE can only be set within the same 4 ports group");
328 return -ENODEV;
329 }
330
331 port_matrix[pi_id].hw_chan[1] = ret;
332 port_matrix[pi_id].is_4p = true;
333
334 return 0;
335 }
336
337 static int
tps23881_get_unused_chan(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],int port_cnt)338 tps23881_get_unused_chan(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],
339 int port_cnt)
340 {
341 bool used;
342 int i, j;
343
344 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
345 used = false;
346
347 for (j = 0; j < port_cnt; j++) {
348 if (port_matrix[j].hw_chan[0] == i) {
349 used = true;
350 break;
351 }
352
353 if (port_matrix[j].is_4p &&
354 port_matrix[j].hw_chan[1] == i) {
355 used = true;
356 break;
357 }
358 }
359
360 if (!used)
361 return i;
362 }
363
364 return -ENODEV;
365 }
366
367 /* Sort the port matrix to following particular hardware ports matrix
368 * specification of the tps23881. The device has two 4-ports groups and
369 * each 4-pair powered device has to be configured to use two consecutive
370 * logical channel in each 4 ports group (1 and 2 or 3 and 4). Also the
371 * hardware matrix has to be fully configured even with unused chan to be
372 * valid.
373 */
374 static int
tps23881_sort_port_matrix(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])375 tps23881_sort_port_matrix(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])
376 {
377 struct tps23881_port_matrix tmp_port_matrix[TPS23881_MAX_CHANS] = {0};
378 int i, ret, port_cnt = 0, cnt_4ch_grp1 = 0, cnt_4ch_grp2 = 4;
379
380 /* Configure 4p port matrix */
381 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
382 int *cnt;
383
384 if (!port_matrix[i].exist || !port_matrix[i].is_4p)
385 continue;
386
387 if (port_matrix[i].hw_chan[0] < 4)
388 cnt = &cnt_4ch_grp1;
389 else
390 cnt = &cnt_4ch_grp2;
391
392 tmp_port_matrix[port_cnt].exist = true;
393 tmp_port_matrix[port_cnt].is_4p = true;
394 tmp_port_matrix[port_cnt].pi_id = i;
395 tmp_port_matrix[port_cnt].hw_chan[0] = port_matrix[i].hw_chan[0];
396 tmp_port_matrix[port_cnt].hw_chan[1] = port_matrix[i].hw_chan[1];
397
398 /* 4-pair ports have to be configured with consecutive
399 * logical channels 0 and 1, 2 and 3.
400 */
401 tmp_port_matrix[port_cnt].lgcl_chan[0] = (*cnt)++;
402 tmp_port_matrix[port_cnt].lgcl_chan[1] = (*cnt)++;
403
404 port_cnt++;
405 }
406
407 /* Configure 2p port matrix */
408 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
409 int *cnt;
410
411 if (!port_matrix[i].exist || port_matrix[i].is_4p)
412 continue;
413
414 if (port_matrix[i].hw_chan[0] < 4)
415 cnt = &cnt_4ch_grp1;
416 else
417 cnt = &cnt_4ch_grp2;
418
419 tmp_port_matrix[port_cnt].exist = true;
420 tmp_port_matrix[port_cnt].pi_id = i;
421 tmp_port_matrix[port_cnt].lgcl_chan[0] = (*cnt)++;
422 tmp_port_matrix[port_cnt].hw_chan[0] = port_matrix[i].hw_chan[0];
423
424 port_cnt++;
425 }
426
427 /* Complete the rest of the first 4 port group matrix even if
428 * channels are unused
429 */
430 while (cnt_4ch_grp1 < 4) {
431 ret = tps23881_get_unused_chan(tmp_port_matrix, port_cnt);
432 if (ret < 0) {
433 pr_err("tps23881: port matrix issue, no chan available\n");
434 return ret;
435 }
436
437 if (port_cnt >= TPS23881_MAX_CHANS) {
438 pr_err("tps23881: wrong number of channels\n");
439 return -ENODEV;
440 }
441 tmp_port_matrix[port_cnt].lgcl_chan[0] = cnt_4ch_grp1;
442 tmp_port_matrix[port_cnt].hw_chan[0] = ret;
443 cnt_4ch_grp1++;
444 port_cnt++;
445 }
446
447 /* Complete the rest of the second 4 port group matrix even if
448 * channels are unused
449 */
450 while (cnt_4ch_grp2 < 8) {
451 ret = tps23881_get_unused_chan(tmp_port_matrix, port_cnt);
452 if (ret < 0) {
453 pr_err("tps23881: port matrix issue, no chan available\n");
454 return -ENODEV;
455 }
456
457 if (port_cnt >= TPS23881_MAX_CHANS) {
458 pr_err("tps23881: wrong number of channels\n");
459 return -ENODEV;
460 }
461 tmp_port_matrix[port_cnt].lgcl_chan[0] = cnt_4ch_grp2;
462 tmp_port_matrix[port_cnt].hw_chan[0] = ret;
463 cnt_4ch_grp2++;
464 port_cnt++;
465 }
466
467 memcpy(port_matrix, tmp_port_matrix, sizeof(tmp_port_matrix));
468
469 return port_cnt;
470 }
471
472 /* Write port matrix to the hardware port matrix and the software port
473 * matrix.
474 */
475 static int
tps23881_write_port_matrix(struct tps23881_priv * priv,struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],int port_cnt)476 tps23881_write_port_matrix(struct tps23881_priv *priv,
477 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],
478 int port_cnt)
479 {
480 struct i2c_client *client = priv->client;
481 u8 pi_id, lgcl_chan, hw_chan;
482 u16 val = 0;
483 int i, ret;
484
485 for (i = 0; i < port_cnt; i++) {
486 pi_id = port_matrix[i].pi_id;
487 lgcl_chan = port_matrix[i].lgcl_chan[0];
488 hw_chan = port_matrix[i].hw_chan[0] % 4;
489
490 /* Set software port matrix for existing ports */
491 if (port_matrix[i].exist)
492 priv->port[pi_id].chan[0] = lgcl_chan;
493
494 /* Set hardware port matrix for all ports */
495 val |= hw_chan << (lgcl_chan * 2);
496
497 if (!port_matrix[i].is_4p)
498 continue;
499
500 lgcl_chan = port_matrix[i].lgcl_chan[1];
501 hw_chan = port_matrix[i].hw_chan[1] % 4;
502
503 /* Set software port matrix for existing ports */
504 if (port_matrix[i].exist) {
505 priv->port[pi_id].is_4p = true;
506 priv->port[pi_id].chan[1] = lgcl_chan;
507 }
508
509 /* Set hardware port matrix for all ports */
510 val |= hw_chan << (lgcl_chan * 2);
511 }
512
513 /* Write hardware ports matrix */
514 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PORT_MAP, val);
515 if (ret)
516 return ret;
517
518 return 0;
519 }
520
521 static int
tps23881_set_ports_conf(struct tps23881_priv * priv,struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])522 tps23881_set_ports_conf(struct tps23881_priv *priv,
523 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])
524 {
525 struct i2c_client *client = priv->client;
526 int i, ret;
527 u16 val;
528
529 /* Set operating mode */
530 ret = i2c_smbus_write_word_data(client, TPS23881_REG_OP_MODE,
531 TPS23881_OP_MODE_SEMIAUTO);
532 if (ret)
533 return ret;
534
535 /* Disable DC disconnect */
536 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DIS_EN, 0x0);
537 if (ret)
538 return ret;
539
540 /* Set port power allocation */
541 val = 0;
542 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
543 if (!port_matrix[i].exist)
544 continue;
545
546 if (port_matrix[i].is_4p)
547 val |= 0xf << ((port_matrix[i].lgcl_chan[0] / 2) * 4);
548 else
549 val |= 0x3 << ((port_matrix[i].lgcl_chan[0] / 2) * 4);
550 }
551 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PORT_POWER, val);
552 if (ret)
553 return ret;
554
555 /* Enable detection and classification */
556 val = 0;
557 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
558 if (!port_matrix[i].exist)
559 continue;
560
561 val |= BIT(port_matrix[i].lgcl_chan[0]) |
562 BIT(port_matrix[i].lgcl_chan[0] + 4);
563 if (port_matrix[i].is_4p)
564 val |= BIT(port_matrix[i].lgcl_chan[1]) |
565 BIT(port_matrix[i].lgcl_chan[1] + 4);
566 }
567 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DET_CLA_EN, val);
568 if (ret)
569 return ret;
570
571 return 0;
572 }
573
574 static int
tps23881_set_ports_matrix(struct tps23881_priv * priv,struct device_node * chan_node[TPS23881_MAX_CHANS])575 tps23881_set_ports_matrix(struct tps23881_priv *priv,
576 struct device_node *chan_node[TPS23881_MAX_CHANS])
577 {
578 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS] = {0};
579 int i, ret;
580
581 /* Update with values for every PSE PIs */
582 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
583 ret = tps23881_match_port_matrix(&priv->pcdev.pi[i], i,
584 chan_node, port_matrix);
585 if (ret)
586 return ret;
587 }
588
589 ret = tps23881_sort_port_matrix(port_matrix);
590 if (ret < 0)
591 return ret;
592
593 ret = tps23881_write_port_matrix(priv, port_matrix, ret);
594 if (ret)
595 return ret;
596
597 ret = tps23881_set_ports_conf(priv, port_matrix);
598 if (ret)
599 return ret;
600
601 return 0;
602 }
603
tps23881_setup_pi_matrix(struct pse_controller_dev * pcdev)604 static int tps23881_setup_pi_matrix(struct pse_controller_dev *pcdev)
605 {
606 struct device_node *chan_node[TPS23881_MAX_CHANS] = {NULL};
607 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
608 int ret, i;
609
610 ret = tps23881_get_of_channels(priv, chan_node);
611 if (ret < 0) {
612 dev_warn(&priv->client->dev,
613 "Unable to parse port-matrix, default matrix will be used\n");
614 return 0;
615 }
616
617 ret = tps23881_set_ports_matrix(priv, chan_node);
618
619 for (i = 0; i < TPS23881_MAX_CHANS; i++)
620 of_node_put(chan_node[i]);
621
622 return ret;
623 }
624
625 static const struct pse_controller_ops tps23881_ops = {
626 .setup_pi_matrix = tps23881_setup_pi_matrix,
627 .pi_enable = tps23881_pi_enable,
628 .pi_disable = tps23881_pi_disable,
629 .pi_is_enabled = tps23881_pi_is_enabled,
630 .ethtool_get_status = tps23881_ethtool_get_status,
631 };
632
633 static const char fw_parity_name[] = "ti/tps23881/tps23881-parity-14.bin";
634 static const char fw_sram_name[] = "ti/tps23881/tps23881-sram-14.bin";
635
636 struct tps23881_fw_conf {
637 u8 reg;
638 u8 val;
639 };
640
641 static const struct tps23881_fw_conf tps23881_fw_parity_conf[] = {
642 {.reg = 0x60, .val = 0x01},
643 {.reg = 0x62, .val = 0x00},
644 {.reg = 0x63, .val = 0x80},
645 {.reg = 0x60, .val = 0xC4},
646 {.reg = 0x1D, .val = 0xBC},
647 {.reg = 0xD7, .val = 0x02},
648 {.reg = 0x91, .val = 0x00},
649 {.reg = 0x90, .val = 0x00},
650 {.reg = 0xD7, .val = 0x00},
651 {.reg = 0x1D, .val = 0x00},
652 { /* sentinel */ }
653 };
654
655 static const struct tps23881_fw_conf tps23881_fw_sram_conf[] = {
656 {.reg = 0x60, .val = 0xC5},
657 {.reg = 0x62, .val = 0x00},
658 {.reg = 0x63, .val = 0x80},
659 {.reg = 0x60, .val = 0xC0},
660 {.reg = 0x1D, .val = 0xBC},
661 {.reg = 0xD7, .val = 0x02},
662 {.reg = 0x91, .val = 0x00},
663 {.reg = 0x90, .val = 0x00},
664 {.reg = 0xD7, .val = 0x00},
665 {.reg = 0x1D, .val = 0x00},
666 { /* sentinel */ }
667 };
668
tps23881_flash_sram_fw_part(struct i2c_client * client,const char * fw_name,const struct tps23881_fw_conf * fw_conf)669 static int tps23881_flash_sram_fw_part(struct i2c_client *client,
670 const char *fw_name,
671 const struct tps23881_fw_conf *fw_conf)
672 {
673 const struct firmware *fw = NULL;
674 int i, ret;
675
676 ret = request_firmware(&fw, fw_name, &client->dev);
677 if (ret)
678 return ret;
679
680 dev_dbg(&client->dev, "Flashing %s\n", fw_name);
681
682 /* Prepare device for RAM download */
683 while (fw_conf->reg) {
684 ret = i2c_smbus_write_byte_data(client, fw_conf->reg,
685 fw_conf->val);
686 if (ret)
687 goto out;
688
689 fw_conf++;
690 }
691
692 /* Flash the firmware file */
693 for (i = 0; i < fw->size; i++) {
694 ret = i2c_smbus_write_byte_data(client,
695 TPS23881_REG_SRAM_DATA,
696 fw->data[i]);
697 if (ret)
698 goto out;
699 }
700
701 out:
702 release_firmware(fw);
703 return ret;
704 }
705
tps23881_flash_sram_fw(struct i2c_client * client)706 static int tps23881_flash_sram_fw(struct i2c_client *client)
707 {
708 int ret;
709
710 ret = tps23881_flash_sram_fw_part(client, fw_parity_name,
711 tps23881_fw_parity_conf);
712 if (ret)
713 return ret;
714
715 ret = tps23881_flash_sram_fw_part(client, fw_sram_name,
716 tps23881_fw_sram_conf);
717 if (ret)
718 return ret;
719
720 ret = i2c_smbus_write_byte_data(client, TPS23881_REG_SRAM_CTRL, 0x18);
721 if (ret)
722 return ret;
723
724 mdelay(12);
725
726 return 0;
727 }
728
tps23881_i2c_probe(struct i2c_client * client)729 static int tps23881_i2c_probe(struct i2c_client *client)
730 {
731 struct device *dev = &client->dev;
732 struct tps23881_priv *priv;
733 struct gpio_desc *reset;
734 int ret;
735 u8 val;
736
737 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
738 dev_err(dev, "i2c check functionality failed\n");
739 return -ENXIO;
740 }
741
742 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
743 if (!priv)
744 return -ENOMEM;
745
746 reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
747 if (IS_ERR(reset))
748 return dev_err_probe(&client->dev, PTR_ERR(reset), "Failed to get reset GPIO\n");
749
750 if (reset) {
751 /* TPS23880 datasheet (Rev G) indicates minimum reset pulse is 5us */
752 usleep_range(5, 10);
753 gpiod_set_value_cansleep(reset, 0); /* De-assert reset */
754
755 /* TPS23880 datasheet indicates the minimum time after power on reset
756 * should be 20ms, but the document describing how to load SRAM ("How
757 * to Load TPS2388x SRAM and Parity Code over I2C" (Rev E))
758 * indicates we should delay that programming by at least 50ms. So
759 * we'll wait the entire 50ms here to ensure we're safe to go to the
760 * SRAM loading proceedure.
761 */
762 msleep(50);
763 }
764
765 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_DEVID);
766 if (ret < 0)
767 return ret;
768
769 if (FIELD_GET(TPS23881_REG_DEVID_MASK, ret) != TPS23881_DEVICE_ID) {
770 dev_err(dev, "Wrong device ID\n");
771 return -ENXIO;
772 }
773
774 ret = tps23881_flash_sram_fw(client);
775 if (ret < 0)
776 return ret;
777
778 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_FWREV);
779 if (ret < 0)
780 return ret;
781
782 dev_info(&client->dev, "Firmware revision 0x%x\n", ret);
783
784 /* Set configuration B, 16 bit access on a single device address */
785 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_GEN_MASK);
786 if (ret < 0)
787 return ret;
788
789 val = ret | TPS23881_REG_NBITACC;
790 ret = i2c_smbus_write_byte_data(client, TPS23881_REG_GEN_MASK, val);
791 if (ret)
792 return ret;
793
794 priv->client = client;
795 i2c_set_clientdata(client, priv);
796 priv->np = dev->of_node;
797
798 priv->pcdev.owner = THIS_MODULE;
799 priv->pcdev.ops = &tps23881_ops;
800 priv->pcdev.dev = dev;
801 priv->pcdev.types = ETHTOOL_PSE_C33;
802 priv->pcdev.nr_lines = TPS23881_MAX_CHANS;
803 ret = devm_pse_controller_register(dev, &priv->pcdev);
804 if (ret) {
805 return dev_err_probe(dev, ret,
806 "failed to register PSE controller\n");
807 }
808
809 return ret;
810 }
811
812 static const struct i2c_device_id tps23881_id[] = {
813 { "tps23881" },
814 { }
815 };
816 MODULE_DEVICE_TABLE(i2c, tps23881_id);
817
818 static const struct of_device_id tps23881_of_match[] = {
819 { .compatible = "ti,tps23881", },
820 { },
821 };
822 MODULE_DEVICE_TABLE(of, tps23881_of_match);
823
824 static struct i2c_driver tps23881_driver = {
825 .probe = tps23881_i2c_probe,
826 .id_table = tps23881_id,
827 .driver = {
828 .name = "tps23881",
829 .of_match_table = tps23881_of_match,
830 },
831 };
832 module_i2c_driver(tps23881_driver);
833
834 MODULE_AUTHOR("Kory Maincent <kory.maincent@bootlin.com>");
835 MODULE_DESCRIPTION("TI TPS23881 PoE PSE Controller driver");
836 MODULE_LICENSE("GPL");
837