1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * PCI Endpoint *Controller* (EPC) header file
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9 #ifndef __LINUX_PCI_EPC_H
10 #define __LINUX_PCI_EPC_H
11
12 #include <linux/pci-epf.h>
13
14 struct pci_epc;
15
16 enum pci_epc_interface_type {
17 UNKNOWN_INTERFACE = -1,
18 PRIMARY_INTERFACE,
19 SECONDARY_INTERFACE,
20 };
21
22 static inline const char *
pci_epc_interface_string(enum pci_epc_interface_type type)23 pci_epc_interface_string(enum pci_epc_interface_type type)
24 {
25 switch (type) {
26 case PRIMARY_INTERFACE:
27 return "primary";
28 case SECONDARY_INTERFACE:
29 return "secondary";
30 default:
31 return "UNKNOWN interface";
32 }
33 }
34
35 /**
36 * struct pci_epc_map - information about EPC memory for mapping a RC PCI
37 * address range
38 * @pci_addr: start address of the RC PCI address range to map
39 * @pci_size: size of the RC PCI address range mapped from @pci_addr
40 * @map_pci_addr: RC PCI address used as the first address mapped (may be lower
41 * than @pci_addr)
42 * @map_size: size of the controller memory needed for mapping the RC PCI address
43 * range @map_pci_addr..@pci_addr+@pci_size
44 * @phys_base: base physical address of the allocated EPC memory for mapping the
45 * RC PCI address range
46 * @phys_addr: physical address at which @pci_addr is mapped
47 * @virt_base: base virtual address of the allocated EPC memory for mapping the
48 * RC PCI address range
49 * @virt_addr: virtual address at which @pci_addr is mapped
50 */
51 struct pci_epc_map {
52 u64 pci_addr;
53 size_t pci_size;
54
55 u64 map_pci_addr;
56 size_t map_size;
57
58 phys_addr_t phys_base;
59 phys_addr_t phys_addr;
60 void __iomem *virt_base;
61 void __iomem *virt_addr;
62 };
63
64 /**
65 * enum pci_epc_aux_resource_type - auxiliary resource type identifiers
66 * @PCI_EPC_AUX_DOORBELL_MMIO: Doorbell MMIO, that might be outside the DMA
67 * controller register window
68 *
69 * EPC backends may expose auxiliary blocks (e.g. DMA engines) by mapping their
70 * register windows and descriptor memories into BAR space. This enum
71 * identifies the type of each exposable resource.
72 */
73 enum pci_epc_aux_resource_type {
74 PCI_EPC_AUX_DOORBELL_MMIO,
75 };
76
77 /**
78 * struct pci_epc_aux_resource - a physical auxiliary resource that may be
79 * exposed for peer use
80 * @type: resource type, see enum pci_epc_aux_resource_type
81 * @phys_addr: physical base address of the resource
82 * @size: size of the resource in bytes
83 * @bar: BAR number where this resource is already exposed to the RC
84 * (NO_BAR if not)
85 * @bar_offset: offset within @bar where the resource starts (valid iff
86 * @bar != NO_BAR)
87 * @u: type-specific metadata
88 */
89 struct pci_epc_aux_resource {
90 enum pci_epc_aux_resource_type type;
91 phys_addr_t phys_addr;
92 resource_size_t size;
93 enum pci_barno bar;
94 resource_size_t bar_offset;
95
96 union {
97 /* PCI_EPC_AUX_DOORBELL_MMIO */
98 struct {
99 int irq; /* IRQ number for the doorbell handler */
100 u32 data; /* write value to ring the doorbell */
101 } db_mmio;
102 } u;
103 };
104
105 /**
106 * struct pci_epc_ops - set of function pointers for performing EPC operations
107 * @write_header: ops to populate configuration space header
108 * @set_bar: ops to configure the BAR
109 * @clear_bar: ops to reset the BAR
110 * @align_addr: operation to get the mapping address, mapping size and offset
111 * into a controller memory window needed to map an RC PCI address
112 * region
113 * @map_addr: ops to map CPU address to PCI address
114 * @unmap_addr: ops to unmap CPU address and PCI address
115 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
116 * capability register
117 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
118 * the MSI capability register
119 * @set_msix: ops to set the requested number of MSI-X interrupts in the
120 * MSI-X capability register
121 * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
122 * from the MSI-X capability register
123 * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
124 * @map_msi_irq: ops to map physical address to MSI address and return MSI data
125 * @start: ops to start the PCI link
126 * @stop: ops to stop the PCI link
127 * @get_features: ops to get the features supported by the EPC
128 * @get_aux_resources_count: ops to get the number of controller-owned
129 * auxiliary resources
130 * @get_aux_resources: ops to retrieve controller-owned auxiliary resources
131 * @owner: the module owner containing the ops
132 */
133 struct pci_epc_ops {
134 int (*write_header)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
135 struct pci_epf_header *hdr);
136 int (*set_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
137 struct pci_epf_bar *epf_bar);
138 void (*clear_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
139 struct pci_epf_bar *epf_bar);
140 u64 (*align_addr)(struct pci_epc *epc, u64 pci_addr, size_t *size,
141 size_t *offset);
142 int (*map_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
143 phys_addr_t addr, u64 pci_addr, size_t size);
144 void (*unmap_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
145 phys_addr_t addr);
146 int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
147 u8 nr_irqs);
148 int (*get_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
149 int (*set_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
150 u16 nr_irqs, enum pci_barno, u32 offset);
151 int (*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
152 int (*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
153 unsigned int type, u16 interrupt_num);
154 int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
155 phys_addr_t phys_addr, u8 interrupt_num,
156 u32 entry_size, u32 *msi_data,
157 u32 *msi_addr_offset);
158 int (*start)(struct pci_epc *epc);
159 void (*stop)(struct pci_epc *epc);
160 const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
161 u8 func_no, u8 vfunc_no);
162 int (*get_aux_resources_count)(struct pci_epc *epc, u8 func_no,
163 u8 vfunc_no);
164 int (*get_aux_resources)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
165 struct pci_epc_aux_resource *resources,
166 int num_resources);
167 struct module *owner;
168 };
169
170 /**
171 * struct pci_epc_mem_window - address window of the endpoint controller
172 * @phys_base: physical base address of the PCI address window
173 * @size: the size of the PCI address window
174 * @page_size: size of each page
175 */
176 struct pci_epc_mem_window {
177 phys_addr_t phys_base;
178 size_t size;
179 size_t page_size;
180 };
181
182 /**
183 * struct pci_epc_mem - address space of the endpoint controller
184 * @window: address window of the endpoint controller
185 * @bitmap: bitmap to manage the PCI address space
186 * @pages: number of bits representing the address region
187 * @lock: mutex to protect bitmap
188 */
189 struct pci_epc_mem {
190 struct pci_epc_mem_window window;
191 unsigned long *bitmap;
192 int pages;
193 /* mutex to protect against concurrent access for memory allocation*/
194 struct mutex lock;
195 };
196
197 /**
198 * struct pci_epc - represents the PCI EPC device
199 * @dev: PCI EPC device
200 * @pci_epf: list of endpoint functions present in this EPC device
201 * @list_lock: Mutex for protecting pci_epf list
202 * @ops: function pointers for performing endpoint operations
203 * @windows: array of address space of the endpoint controller
204 * @mem: first window of the endpoint controller, which corresponds to
205 * default address space of the endpoint controller supporting
206 * single window.
207 * @num_windows: number of windows supported by device
208 * @max_functions: max number of functions that can be configured in this EPC
209 * @max_vfs: Array indicating the maximum number of virtual functions that can
210 * be associated with each physical function
211 * @group: configfs group representing the PCI EPC device
212 * @lock: mutex to protect pci_epc ops
213 * @function_num_map: bitmap to manage physical function number
214 * @domain_nr: PCI domain number of the endpoint controller
215 * @init_complete: flag to indicate whether the EPC initialization is complete
216 * or not
217 */
218 struct pci_epc {
219 struct device dev;
220 struct list_head pci_epf;
221 struct mutex list_lock;
222 const struct pci_epc_ops *ops;
223 struct pci_epc_mem **windows;
224 struct pci_epc_mem *mem;
225 unsigned int num_windows;
226 u8 max_functions;
227 u8 *max_vfs;
228 struct config_group *group;
229 /* mutex to protect against concurrent access of EP controller */
230 struct mutex lock;
231 unsigned long function_num_map;
232 int domain_nr;
233 bool init_complete;
234 };
235
236 /**
237 * enum pci_epc_bar_type - configurability of endpoint BAR
238 * @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC.
239 * @BAR_FIXED: The BAR mask is fixed by the hardware.
240 * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability.
241 * NOTE: An EPC driver can currently only set a single supported
242 * size.
243 * @BAR_RESERVED: Used for HW-backed BARs (e.g. MSI-X table, DMA regs). The BAR
244 * should not be disabled by an EPC driver. The BAR should not be
245 * reprogrammed by an EPF driver. An EPF driver is allowed to
246 * disable the BAR if absolutely necessary. (However, right now
247 * there is no EPC operation to disable a BAR that has not been
248 * programmed using pci_epc_set_bar().)
249 * @BAR_DISABLED: The BAR should be disabled by an EPC driver. The BAR will be
250 * unavailable to an EPF driver.
251 */
252 enum pci_epc_bar_type {
253 BAR_PROGRAMMABLE = 0,
254 BAR_FIXED,
255 BAR_RESIZABLE,
256 BAR_RESERVED,
257 BAR_DISABLED,
258 };
259
260 /**
261 * enum pci_epc_bar_rsvd_region_type - type of a fixed subregion behind a BAR
262 * @PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO: Integrated DMA controller MMIO window
263 * @PCI_EPC_BAR_RSVD_MSIX_TBL_RAM: MSI-X table structure
264 * @PCI_EPC_BAR_RSVD_MSIX_PBA_RAM: MSI-X PBA structure
265 *
266 * BARs marked BAR_RESERVED are owned by the SoC/EPC hardware and must not be
267 * reprogrammed by EPF drivers. Some of them still expose fixed subregions that
268 * EPFs may want to reference (e.g. embedded doorbell fallback).
269 */
270 enum pci_epc_bar_rsvd_region_type {
271 PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO = 0,
272 PCI_EPC_BAR_RSVD_MSIX_TBL_RAM,
273 PCI_EPC_BAR_RSVD_MSIX_PBA_RAM,
274 };
275
276 /**
277 * struct pci_epc_bar_rsvd_region - fixed subregion behind a BAR
278 * @type: reserved region type
279 * @offset: offset within the BAR aperture
280 * @size: size of the reserved region
281 */
282 struct pci_epc_bar_rsvd_region {
283 enum pci_epc_bar_rsvd_region_type type;
284 resource_size_t offset;
285 resource_size_t size;
286 };
287
288 /**
289 * struct pci_epc_bar_desc - hardware description for a BAR
290 * @type: the type of the BAR
291 * @fixed_size: the fixed size, only applicable if type is BAR_FIXED_MASK.
292 * @only_64bit: if true, an EPF driver is not allowed to choose if this BAR
293 * should be configured as 32-bit or 64-bit, the EPF driver must
294 * configure this BAR as 64-bit.
295 * @nr_rsvd_regions: number of fixed subregions described for BAR_RESERVED
296 * @rsvd_regions: fixed subregions behind BAR_RESERVED
297 */
298 struct pci_epc_bar_desc {
299 enum pci_epc_bar_type type;
300 u64 fixed_size;
301 bool only_64bit;
302 u8 nr_rsvd_regions;
303 const struct pci_epc_bar_rsvd_region *rsvd_regions;
304 };
305
306 /**
307 * struct pci_epc_features - features supported by a EPC device per function
308 * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
309 * @dynamic_inbound_mapping: indicate if the EPC device supports updating
310 * inbound mappings for an already configured BAR
311 * (i.e. allow calling pci_epc_set_bar() again
312 * without first calling pci_epc_clear_bar())
313 * @subrange_mapping: indicate if the EPC device can map inbound subranges for a
314 * BAR. This feature depends on @dynamic_inbound_mapping
315 * feature.
316 * @msi_capable: indicate if the endpoint function has MSI capability
317 * @msix_capable: indicate if the endpoint function has MSI-X capability
318 * @intx_capable: indicate if the endpoint can raise INTx interrupts
319 * @bar: array specifying the hardware description for each BAR
320 * @align: alignment size required for BAR buffer allocation
321 */
322 struct pci_epc_features {
323 unsigned int linkup_notifier : 1;
324 unsigned int dynamic_inbound_mapping : 1;
325 unsigned int subrange_mapping : 1;
326 unsigned int msi_capable : 1;
327 unsigned int msix_capable : 1;
328 unsigned int intx_capable : 1;
329 struct pci_epc_bar_desc bar[PCI_STD_NUM_BARS];
330 size_t align;
331 };
332
333 #define to_pci_epc(device) container_of((device), struct pci_epc, dev)
334
335 #ifdef CONFIG_PCI_ENDPOINT
336
337 #define pci_epc_create(dev, ops) \
338 __pci_epc_create((dev), (ops), THIS_MODULE)
339 #define devm_pci_epc_create(dev, ops) \
340 __devm_pci_epc_create((dev), (ops), THIS_MODULE)
341
epc_set_drvdata(struct pci_epc * epc,void * data)342 static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
343 {
344 dev_set_drvdata(&epc->dev, data);
345 }
346
epc_get_drvdata(struct pci_epc * epc)347 static inline void *epc_get_drvdata(struct pci_epc *epc)
348 {
349 return dev_get_drvdata(&epc->dev);
350 }
351
352 struct pci_epc *
353 __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
354 struct module *owner);
355 struct pci_epc *
356 __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
357 struct module *owner);
358 void pci_epc_destroy(struct pci_epc *epc);
359 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf,
360 enum pci_epc_interface_type type);
361 void pci_epc_linkup(struct pci_epc *epc);
362 void pci_epc_linkdown(struct pci_epc *epc);
363 void pci_epc_init_notify(struct pci_epc *epc);
364 void pci_epc_notify_pending_init(struct pci_epc *epc, struct pci_epf *epf);
365 void pci_epc_deinit_notify(struct pci_epc *epc);
366 void pci_epc_bus_master_enable_notify(struct pci_epc *epc);
367 void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf,
368 enum pci_epc_interface_type type);
369 int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
370 struct pci_epf_header *hdr);
371 int pci_epc_bar_size_to_rebar_cap(size_t size, u32 *cap);
372 int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
373 struct pci_epf_bar *epf_bar);
374 void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
375 struct pci_epf_bar *epf_bar);
376 int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
377 phys_addr_t phys_addr,
378 u64 pci_addr, size_t size);
379 void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
380 phys_addr_t phys_addr);
381 int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 nr_irqs);
382 int pci_epc_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
383 int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u16 nr_irqs,
384 enum pci_barno, u32 offset);
385 int pci_epc_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
386 int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
387 phys_addr_t phys_addr, u8 interrupt_num,
388 u32 entry_size, u32 *msi_data, u32 *msi_addr_offset);
389 int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
390 unsigned int type, u16 interrupt_num);
391 int pci_epc_start(struct pci_epc *epc);
392 void pci_epc_stop(struct pci_epc *epc);
393 const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
394 u8 func_no, u8 vfunc_no);
395 int pci_epc_get_aux_resources_count(struct pci_epc *epc, u8 func_no,
396 u8 vfunc_no);
397 int pci_epc_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
398 struct pci_epc_aux_resource *resources,
399 int num_resources);
400 enum pci_barno
401 pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features);
402 enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
403 *epc_features, enum pci_barno bar);
404 struct pci_epc *pci_epc_get(const char *epc_name);
405 void pci_epc_put(struct pci_epc *epc);
406
407 int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
408 size_t size, size_t page_size);
409 int pci_epc_multi_mem_init(struct pci_epc *epc,
410 struct pci_epc_mem_window *window,
411 unsigned int num_windows);
412 void pci_epc_mem_exit(struct pci_epc *epc);
413 void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
414 phys_addr_t *phys_addr, size_t size);
415 void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
416 void __iomem *virt_addr, size_t size);
417 int pci_epc_mem_map(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
418 u64 pci_addr, size_t pci_size, struct pci_epc_map *map);
419 void pci_epc_mem_unmap(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
420 struct pci_epc_map *map);
421
422 #else
pci_epc_init_notify(struct pci_epc * epc)423 static inline void pci_epc_init_notify(struct pci_epc *epc)
424 {
425 }
426
pci_epc_deinit_notify(struct pci_epc * epc)427 static inline void pci_epc_deinit_notify(struct pci_epc *epc)
428 {
429 }
430 #endif /* CONFIG_PCI_ENDPOINT */
431 #endif /* __LINUX_PCI_EPC_H */
432