1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces 4 * 5 * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>, 6 * Pilo Chambert <pilo.c@wanadoo.fr> 7 * 8 * Thanks to : Anders Torger <torger@ludd.luth.se>, 9 * Henk Hesselink <henk@anda.nl> 10 * for writing the digi96-driver 11 * and RME for all informations. 12 * 13 * **************************************************************************** 14 * 15 * Note #1 "Sek'd models" ................................... martin 2002-12-07 16 * 17 * Identical soundcards by Sek'd were labeled: 18 * RME Digi 32 = Sek'd Prodif 32 19 * RME Digi 32 Pro = Sek'd Prodif 96 20 * RME Digi 32/8 = Sek'd Prodif Gold 21 * 22 * **************************************************************************** 23 * 24 * Note #2 "full duplex mode" ............................... martin 2002-12-07 25 * 26 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical 27 * in this mode. Rec data and play data are using the same buffer therefore. At 28 * first you have got the playing bits in the buffer and then (after playing 29 * them) they were overwitten by the captured sound of the CS8412/14. Both 30 * modes (play/record) are running harmonically hand in hand in the same buffer 31 * and you have only one start bit plus one interrupt bit to control this 32 * paired action. 33 * This is opposite to the latter rme96 where playing and capturing is totally 34 * separated and so their full duplex mode is supported by alsa (using two 35 * start bits and two interrupts for two different buffers). 36 * But due to the wrong sequence of playing and capturing ALSA shows no solved 37 * full duplex support for the rme32 at the moment. That's bad, but I'm not 38 * able to solve it. Are you motivated enough to solve this problem now? Your 39 * patch would be welcome! 40 * 41 * **************************************************************************** 42 * 43 * "The story after the long seeking" -- tiwai 44 * 45 * Ok, the situation regarding the full duplex is now improved a bit. 46 * In the fullduplex mode (given by the module parameter), the hardware buffer 47 * is split to halves for read and write directions at the DMA pointer. 48 * That is, the half above the current DMA pointer is used for write, and 49 * the half below is used for read. To mangle this strange behavior, an 50 * software intermediate buffer is introduced. This is, of course, not good 51 * from the viewpoint of the data transfer efficiency. However, this allows 52 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size. 53 * 54 * **************************************************************************** 55 */ 56 57 58 #include <linux/delay.h> 59 #include <linux/gfp.h> 60 #include <linux/init.h> 61 #include <linux/interrupt.h> 62 #include <linux/pci.h> 63 #include <linux/module.h> 64 #include <linux/io.h> 65 66 #include <sound/core.h> 67 #include <sound/info.h> 68 #include <sound/control.h> 69 #include <sound/pcm.h> 70 #include <sound/pcm_params.h> 71 #include <sound/pcm-indirect.h> 72 #include <sound/asoundef.h> 73 #include <sound/initval.h> 74 75 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 76 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 77 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 78 static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1}; 79 80 module_param_array(index, int, NULL, 0444); 81 MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard."); 82 module_param_array(id, charp, NULL, 0444); 83 MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard."); 84 module_param_array(enable, bool, NULL, 0444); 85 MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard."); 86 module_param_array(fullduplex, bool, NULL, 0444); 87 MODULE_PARM_DESC(fullduplex, "Support full-duplex mode."); 88 MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>"); 89 MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO"); 90 MODULE_LICENSE("GPL"); 91 92 /* Defines for RME Digi32 series */ 93 #define RME32_SPDIF_NCHANNELS 2 94 95 /* Playback and capture buffer size */ 96 #define RME32_BUFFER_SIZE 0x20000 97 98 /* IO area size */ 99 #define RME32_IO_SIZE 0x30000 100 101 /* IO area offsets */ 102 #define RME32_IO_DATA_BUFFER 0x0 103 #define RME32_IO_CONTROL_REGISTER 0x20000 104 #define RME32_IO_GET_POS 0x20000 105 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004 106 #define RME32_IO_RESET_POS 0x20100 107 108 /* Write control register bits */ 109 #define RME32_WCR_START (1 << 0) /* startbit */ 110 #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono 111 Setting the whole card to mono 112 doesn't seem to be very useful. 113 A software-solution can handle 114 full-duplex with one direction in 115 stereo and the other way in mono. 116 So, the hardware should work all 117 the time in stereo! */ 118 #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */ 119 #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */ 120 #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */ 121 #define RME32_WCR_FREQ_1 (1 << 5) 122 #define RME32_WCR_INP_0 (1 << 6) /* input switch */ 123 #define RME32_WCR_INP_1 (1 << 7) 124 #define RME32_WCR_RESET (1 << 8) /* Reset address */ 125 #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */ 126 #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */ 127 #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */ 128 #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */ 129 #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */ 130 #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */ 131 #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */ 132 133 #define RME32_WCR_BITPOS_FREQ_0 4 134 #define RME32_WCR_BITPOS_FREQ_1 5 135 #define RME32_WCR_BITPOS_INP_0 6 136 #define RME32_WCR_BITPOS_INP_1 7 137 138 /* Read control register bits */ 139 #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff 140 #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */ 141 #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */ 142 #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */ 143 #define RME32_RCR_FREQ_1 (1 << 28) 144 #define RME32_RCR_FREQ_2 (1 << 29) 145 #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */ 146 #define RME32_RCR_IRQ (1 << 31) /* interrupt */ 147 148 #define RME32_RCR_BITPOS_F0 27 149 #define RME32_RCR_BITPOS_F1 28 150 #define RME32_RCR_BITPOS_F2 29 151 152 /* Input types */ 153 #define RME32_INPUT_OPTICAL 0 154 #define RME32_INPUT_COAXIAL 1 155 #define RME32_INPUT_INTERNAL 2 156 #define RME32_INPUT_XLR 3 157 158 /* Clock modes */ 159 #define RME32_CLOCKMODE_SLAVE 0 160 #define RME32_CLOCKMODE_MASTER_32 1 161 #define RME32_CLOCKMODE_MASTER_44 2 162 #define RME32_CLOCKMODE_MASTER_48 3 163 164 /* Block sizes in bytes */ 165 #define RME32_BLOCK_SIZE 8192 166 167 /* Software intermediate buffer (max) size */ 168 #define RME32_MID_BUFFER_SIZE (1024*1024) 169 170 /* Hardware revisions */ 171 #define RME32_32_REVISION 192 172 #define RME32_328_REVISION_OLD 100 173 #define RME32_328_REVISION_NEW 101 174 #define RME32_PRO_REVISION_WITH_8412 192 175 #define RME32_PRO_REVISION_WITH_8414 150 176 177 178 struct rme32 { 179 spinlock_t lock; 180 int irq; 181 unsigned long port; 182 void __iomem *iobase; 183 184 u32 wcreg; /* cached write control register value */ 185 u32 wcreg_spdif; /* S/PDIF setup */ 186 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ 187 u32 rcreg; /* cached read control register value */ 188 189 u8 rev; /* card revision number */ 190 191 struct snd_pcm_substream *playback_substream; 192 struct snd_pcm_substream *capture_substream; 193 194 int playback_frlog; /* log2 of framesize */ 195 int capture_frlog; 196 197 size_t playback_periodsize; /* in bytes, zero if not used */ 198 size_t capture_periodsize; /* in bytes, zero if not used */ 199 200 unsigned int fullduplex_mode; 201 int running; 202 203 struct snd_pcm_indirect playback_pcm; 204 struct snd_pcm_indirect capture_pcm; 205 206 struct snd_card *card; 207 struct snd_pcm *spdif_pcm; 208 struct snd_pcm *adat_pcm; 209 struct pci_dev *pci; 210 struct snd_kcontrol *spdif_ctl; 211 }; 212 213 static const struct pci_device_id snd_rme32_ids[] = { 214 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,}, 215 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,}, 216 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,}, 217 {0,} 218 }; 219 220 MODULE_DEVICE_TABLE(pci, snd_rme32_ids); 221 222 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START) 223 #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414) 224 225 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream); 226 227 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream); 228 229 static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd); 230 231 static void snd_rme32_proc_init(struct rme32 * rme32); 232 233 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32); 234 235 static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32) 236 { 237 return (readl(rme32->iobase + RME32_IO_GET_POS) 238 & RME32_RCR_AUDIO_ADDR_MASK); 239 } 240 241 /* silence callback for halfduplex mode */ 242 static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, 243 int channel, unsigned long pos, 244 unsigned long count) 245 { 246 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 247 248 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count); 249 return 0; 250 } 251 252 /* copy callback for halfduplex mode */ 253 static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, 254 int channel, unsigned long pos, 255 struct iov_iter *src, unsigned long count) 256 { 257 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 258 259 if (copy_from_iter_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 260 count, src) != count) 261 return -EFAULT; 262 return 0; 263 } 264 265 /* copy callback for halfduplex mode */ 266 static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, 267 int channel, unsigned long pos, 268 struct iov_iter *dst, unsigned long count) 269 { 270 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 271 272 if (copy_to_iter_fromio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 273 count, dst) != count) 274 return -EFAULT; 275 return 0; 276 } 277 278 /* 279 * SPDIF I/O capabilities (half-duplex mode) 280 */ 281 static const struct snd_pcm_hardware snd_rme32_spdif_info = { 282 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 283 SNDRV_PCM_INFO_MMAP_VALID | 284 SNDRV_PCM_INFO_INTERLEAVED | 285 SNDRV_PCM_INFO_PAUSE | 286 SNDRV_PCM_INFO_SYNC_START | 287 SNDRV_PCM_INFO_SYNC_APPLPTR), 288 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 289 SNDRV_PCM_FMTBIT_S32_LE), 290 .rates = (SNDRV_PCM_RATE_32000 | 291 SNDRV_PCM_RATE_44100 | 292 SNDRV_PCM_RATE_48000), 293 .rate_min = 32000, 294 .rate_max = 48000, 295 .channels_min = 2, 296 .channels_max = 2, 297 .buffer_bytes_max = RME32_BUFFER_SIZE, 298 .period_bytes_min = RME32_BLOCK_SIZE, 299 .period_bytes_max = RME32_BLOCK_SIZE, 300 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 301 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 302 .fifo_size = 0, 303 }; 304 305 /* 306 * ADAT I/O capabilities (half-duplex mode) 307 */ 308 static const struct snd_pcm_hardware snd_rme32_adat_info = 309 { 310 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 311 SNDRV_PCM_INFO_MMAP_VALID | 312 SNDRV_PCM_INFO_INTERLEAVED | 313 SNDRV_PCM_INFO_PAUSE | 314 SNDRV_PCM_INFO_SYNC_START | 315 SNDRV_PCM_INFO_SYNC_APPLPTR), 316 .formats= SNDRV_PCM_FMTBIT_S16_LE, 317 .rates = (SNDRV_PCM_RATE_44100 | 318 SNDRV_PCM_RATE_48000), 319 .rate_min = 44100, 320 .rate_max = 48000, 321 .channels_min = 8, 322 .channels_max = 8, 323 .buffer_bytes_max = RME32_BUFFER_SIZE, 324 .period_bytes_min = RME32_BLOCK_SIZE, 325 .period_bytes_max = RME32_BLOCK_SIZE, 326 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 327 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 328 .fifo_size = 0, 329 }; 330 331 /* 332 * SPDIF I/O capabilities (full-duplex mode) 333 */ 334 static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = { 335 .info = (SNDRV_PCM_INFO_MMAP | 336 SNDRV_PCM_INFO_MMAP_VALID | 337 SNDRV_PCM_INFO_INTERLEAVED | 338 SNDRV_PCM_INFO_PAUSE | 339 SNDRV_PCM_INFO_SYNC_START | 340 SNDRV_PCM_INFO_SYNC_APPLPTR), 341 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 342 SNDRV_PCM_FMTBIT_S32_LE), 343 .rates = (SNDRV_PCM_RATE_32000 | 344 SNDRV_PCM_RATE_44100 | 345 SNDRV_PCM_RATE_48000), 346 .rate_min = 32000, 347 .rate_max = 48000, 348 .channels_min = 2, 349 .channels_max = 2, 350 .buffer_bytes_max = RME32_MID_BUFFER_SIZE, 351 .period_bytes_min = RME32_BLOCK_SIZE, 352 .period_bytes_max = RME32_BLOCK_SIZE, 353 .periods_min = 2, 354 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, 355 .fifo_size = 0, 356 }; 357 358 /* 359 * ADAT I/O capabilities (full-duplex mode) 360 */ 361 static const struct snd_pcm_hardware snd_rme32_adat_fd_info = 362 { 363 .info = (SNDRV_PCM_INFO_MMAP | 364 SNDRV_PCM_INFO_MMAP_VALID | 365 SNDRV_PCM_INFO_INTERLEAVED | 366 SNDRV_PCM_INFO_PAUSE | 367 SNDRV_PCM_INFO_SYNC_START | 368 SNDRV_PCM_INFO_SYNC_APPLPTR), 369 .formats= SNDRV_PCM_FMTBIT_S16_LE, 370 .rates = (SNDRV_PCM_RATE_44100 | 371 SNDRV_PCM_RATE_48000), 372 .rate_min = 44100, 373 .rate_max = 48000, 374 .channels_min = 8, 375 .channels_max = 8, 376 .buffer_bytes_max = RME32_MID_BUFFER_SIZE, 377 .period_bytes_min = RME32_BLOCK_SIZE, 378 .period_bytes_max = RME32_BLOCK_SIZE, 379 .periods_min = 2, 380 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, 381 .fifo_size = 0, 382 }; 383 384 static void snd_rme32_reset_dac(struct rme32 *rme32) 385 { 386 writel(rme32->wcreg | RME32_WCR_PD, 387 rme32->iobase + RME32_IO_CONTROL_REGISTER); 388 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 389 } 390 391 static int snd_rme32_playback_getrate(struct rme32 * rme32) 392 { 393 int rate; 394 395 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + 396 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); 397 switch (rate) { 398 case 1: 399 rate = 32000; 400 break; 401 case 2: 402 rate = 44100; 403 break; 404 case 3: 405 rate = 48000; 406 break; 407 default: 408 return -1; 409 } 410 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate; 411 } 412 413 static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat) 414 { 415 int n; 416 417 *is_adat = 0; 418 if (rme32->rcreg & RME32_RCR_LOCK) { 419 /* ADAT rate */ 420 *is_adat = 1; 421 } 422 if (rme32->rcreg & RME32_RCR_ERF) { 423 return -1; 424 } 425 426 /* S/PDIF rate */ 427 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) + 428 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) + 429 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2); 430 431 if (RME32_PRO_WITH_8414(rme32)) 432 switch (n) { /* supporting the CS8414 */ 433 case 0: 434 case 1: 435 case 2: 436 return -1; 437 case 3: 438 return 96000; 439 case 4: 440 return 88200; 441 case 5: 442 return 48000; 443 case 6: 444 return 44100; 445 case 7: 446 return 32000; 447 default: 448 return -1; 449 } 450 else 451 switch (n) { /* supporting the CS8412 */ 452 case 0: 453 return -1; 454 case 1: 455 return 48000; 456 case 2: 457 return 44100; 458 case 3: 459 return 32000; 460 case 4: 461 return 48000; 462 case 5: 463 return 44100; 464 case 6: 465 return 44056; 466 case 7: 467 return 32000; 468 default: 469 break; 470 } 471 return -1; 472 } 473 474 static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate) 475 { 476 int ds; 477 478 ds = rme32->wcreg & RME32_WCR_DS_BM; 479 switch (rate) { 480 case 32000: 481 rme32->wcreg &= ~RME32_WCR_DS_BM; 482 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 483 ~RME32_WCR_FREQ_1; 484 break; 485 case 44100: 486 rme32->wcreg &= ~RME32_WCR_DS_BM; 487 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 488 ~RME32_WCR_FREQ_0; 489 break; 490 case 48000: 491 rme32->wcreg &= ~RME32_WCR_DS_BM; 492 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 493 RME32_WCR_FREQ_1; 494 break; 495 case 64000: 496 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) 497 return -EINVAL; 498 rme32->wcreg |= RME32_WCR_DS_BM; 499 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 500 ~RME32_WCR_FREQ_1; 501 break; 502 case 88200: 503 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) 504 return -EINVAL; 505 rme32->wcreg |= RME32_WCR_DS_BM; 506 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 507 ~RME32_WCR_FREQ_0; 508 break; 509 case 96000: 510 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) 511 return -EINVAL; 512 rme32->wcreg |= RME32_WCR_DS_BM; 513 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 514 RME32_WCR_FREQ_1; 515 break; 516 default: 517 return -EINVAL; 518 } 519 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) || 520 (ds && !(rme32->wcreg & RME32_WCR_DS_BM))) 521 { 522 /* change to/from double-speed: reset the DAC (if available) */ 523 snd_rme32_reset_dac(rme32); 524 } else { 525 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 526 } 527 return 0; 528 } 529 530 static int snd_rme32_setclockmode(struct rme32 * rme32, int mode) 531 { 532 switch (mode) { 533 case RME32_CLOCKMODE_SLAVE: 534 /* AutoSync */ 535 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) & 536 ~RME32_WCR_FREQ_1; 537 break; 538 case RME32_CLOCKMODE_MASTER_32: 539 /* Internal 32.0kHz */ 540 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 541 ~RME32_WCR_FREQ_1; 542 break; 543 case RME32_CLOCKMODE_MASTER_44: 544 /* Internal 44.1kHz */ 545 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) | 546 RME32_WCR_FREQ_1; 547 break; 548 case RME32_CLOCKMODE_MASTER_48: 549 /* Internal 48.0kHz */ 550 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 551 RME32_WCR_FREQ_1; 552 break; 553 default: 554 return -EINVAL; 555 } 556 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 557 return 0; 558 } 559 560 static int snd_rme32_getclockmode(struct rme32 * rme32) 561 { 562 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + 563 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); 564 } 565 566 static int snd_rme32_setinputtype(struct rme32 * rme32, int type) 567 { 568 switch (type) { 569 case RME32_INPUT_OPTICAL: 570 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) & 571 ~RME32_WCR_INP_1; 572 break; 573 case RME32_INPUT_COAXIAL: 574 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) & 575 ~RME32_WCR_INP_1; 576 break; 577 case RME32_INPUT_INTERNAL: 578 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) | 579 RME32_WCR_INP_1; 580 break; 581 case RME32_INPUT_XLR: 582 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) | 583 RME32_WCR_INP_1; 584 break; 585 default: 586 return -EINVAL; 587 } 588 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 589 return 0; 590 } 591 592 static int snd_rme32_getinputtype(struct rme32 * rme32) 593 { 594 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) + 595 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1); 596 } 597 598 static void 599 snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback) 600 { 601 int frlog; 602 603 if (n_channels == 2) { 604 frlog = 1; 605 } else { 606 /* assume 8 channels */ 607 frlog = 3; 608 } 609 if (is_playback) { 610 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; 611 rme32->playback_frlog = frlog; 612 } else { 613 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; 614 rme32->capture_frlog = frlog; 615 } 616 } 617 618 static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format) 619 { 620 switch (format) { 621 case SNDRV_PCM_FORMAT_S16_LE: 622 rme32->wcreg &= ~RME32_WCR_MODE24; 623 break; 624 case SNDRV_PCM_FORMAT_S32_LE: 625 rme32->wcreg |= RME32_WCR_MODE24; 626 break; 627 default: 628 return -EINVAL; 629 } 630 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 631 return 0; 632 } 633 634 static int 635 snd_rme32_playback_hw_params(struct snd_pcm_substream *substream, 636 struct snd_pcm_hw_params *params) 637 { 638 int err, rate, dummy; 639 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 640 struct snd_pcm_runtime *runtime = substream->runtime; 641 642 if (!rme32->fullduplex_mode) { 643 runtime->dma_area = (void __force *)(rme32->iobase + 644 RME32_IO_DATA_BUFFER); 645 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; 646 runtime->dma_bytes = RME32_BUFFER_SIZE; 647 } 648 649 spin_lock_irq(&rme32->lock); 650 rate = 0; 651 if (rme32->rcreg & RME32_RCR_KMODE) 652 rate = snd_rme32_capture_getrate(rme32, &dummy); 653 if (rate > 0) { 654 /* AutoSync */ 655 if ((int)params_rate(params) != rate) { 656 spin_unlock_irq(&rme32->lock); 657 return -EIO; 658 } 659 } else { 660 err = snd_rme32_playback_setrate(rme32, params_rate(params)); 661 if (err < 0) { 662 spin_unlock_irq(&rme32->lock); 663 return err; 664 } 665 } 666 err = snd_rme32_setformat(rme32, params_format(params)); 667 if (err < 0) { 668 spin_unlock_irq(&rme32->lock); 669 return err; 670 } 671 672 snd_rme32_setframelog(rme32, params_channels(params), 1); 673 if (rme32->capture_periodsize != 0) { 674 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) { 675 spin_unlock_irq(&rme32->lock); 676 return -EBUSY; 677 } 678 } 679 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog; 680 /* S/PDIF setup */ 681 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) { 682 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); 683 rme32->wcreg |= rme32->wcreg_spdif_stream; 684 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 685 } 686 spin_unlock_irq(&rme32->lock); 687 688 return 0; 689 } 690 691 static int 692 snd_rme32_capture_hw_params(struct snd_pcm_substream *substream, 693 struct snd_pcm_hw_params *params) 694 { 695 int err, isadat, rate; 696 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 697 struct snd_pcm_runtime *runtime = substream->runtime; 698 699 if (!rme32->fullduplex_mode) { 700 runtime->dma_area = (void __force *)rme32->iobase + 701 RME32_IO_DATA_BUFFER; 702 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; 703 runtime->dma_bytes = RME32_BUFFER_SIZE; 704 } 705 706 spin_lock_irq(&rme32->lock); 707 /* enable AutoSync for record-preparing */ 708 rme32->wcreg |= RME32_WCR_AUTOSYNC; 709 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 710 711 err = snd_rme32_setformat(rme32, params_format(params)); 712 if (err < 0) { 713 spin_unlock_irq(&rme32->lock); 714 return err; 715 } 716 err = snd_rme32_playback_setrate(rme32, params_rate(params)); 717 if (err < 0) { 718 spin_unlock_irq(&rme32->lock); 719 return err; 720 } 721 rate = snd_rme32_capture_getrate(rme32, &isadat); 722 if (rate > 0) { 723 if ((int)params_rate(params) != rate) { 724 spin_unlock_irq(&rme32->lock); 725 return -EIO; 726 } 727 if ((isadat && runtime->hw.channels_min == 2) || 728 (!isadat && runtime->hw.channels_min == 8)) { 729 spin_unlock_irq(&rme32->lock); 730 return -EIO; 731 } 732 } 733 /* AutoSync off for recording */ 734 rme32->wcreg &= ~RME32_WCR_AUTOSYNC; 735 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 736 737 snd_rme32_setframelog(rme32, params_channels(params), 0); 738 if (rme32->playback_periodsize != 0) { 739 if (params_period_size(params) << rme32->capture_frlog != 740 rme32->playback_periodsize) { 741 spin_unlock_irq(&rme32->lock); 742 return -EBUSY; 743 } 744 } 745 rme32->capture_periodsize = 746 params_period_size(params) << rme32->capture_frlog; 747 spin_unlock_irq(&rme32->lock); 748 749 return 0; 750 } 751 752 static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause) 753 { 754 if (!from_pause) { 755 writel(0, rme32->iobase + RME32_IO_RESET_POS); 756 } 757 758 rme32->wcreg |= RME32_WCR_START; 759 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 760 } 761 762 static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause) 763 { 764 /* 765 * Check if there is an unconfirmed IRQ, if so confirm it, or else 766 * the hardware will not stop generating interrupts 767 */ 768 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); 769 if (rme32->rcreg & RME32_RCR_IRQ) { 770 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); 771 } 772 rme32->wcreg &= ~RME32_WCR_START; 773 if (rme32->wcreg & RME32_WCR_SEL) 774 rme32->wcreg |= RME32_WCR_MUTE; 775 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 776 if (! to_pause) 777 writel(0, rme32->iobase + RME32_IO_RESET_POS); 778 } 779 780 static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id) 781 { 782 struct rme32 *rme32 = (struct rme32 *) dev_id; 783 784 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); 785 if (!(rme32->rcreg & RME32_RCR_IRQ)) { 786 return IRQ_NONE; 787 } else { 788 if (rme32->capture_substream) { 789 snd_pcm_period_elapsed(rme32->capture_substream); 790 } 791 if (rme32->playback_substream) { 792 snd_pcm_period_elapsed(rme32->playback_substream); 793 } 794 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); 795 } 796 return IRQ_HANDLED; 797 } 798 799 static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE }; 800 801 static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { 802 .count = ARRAY_SIZE(period_bytes), 803 .list = period_bytes, 804 .mask = 0 805 }; 806 807 static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime) 808 { 809 if (! rme32->fullduplex_mode) { 810 snd_pcm_hw_constraint_single(runtime, 811 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 812 RME32_BUFFER_SIZE); 813 snd_pcm_hw_constraint_list(runtime, 0, 814 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 815 &hw_constraints_period_bytes); 816 } 817 } 818 819 static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream) 820 { 821 int rate, dummy; 822 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 823 struct snd_pcm_runtime *runtime = substream->runtime; 824 825 snd_pcm_set_sync(substream); 826 827 spin_lock_irq(&rme32->lock); 828 if (rme32->playback_substream != NULL) { 829 spin_unlock_irq(&rme32->lock); 830 return -EBUSY; 831 } 832 rme32->wcreg &= ~RME32_WCR_ADAT; 833 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 834 rme32->playback_substream = substream; 835 spin_unlock_irq(&rme32->lock); 836 837 if (rme32->fullduplex_mode) 838 runtime->hw = snd_rme32_spdif_fd_info; 839 else 840 runtime->hw = snd_rme32_spdif_info; 841 if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) { 842 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; 843 runtime->hw.rate_max = 96000; 844 } 845 rate = 0; 846 if (rme32->rcreg & RME32_RCR_KMODE) 847 rate = snd_rme32_capture_getrate(rme32, &dummy); 848 if (rate > 0) { 849 /* AutoSync */ 850 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 851 runtime->hw.rate_min = rate; 852 runtime->hw.rate_max = rate; 853 } 854 855 snd_rme32_set_buffer_constraint(rme32, runtime); 856 857 rme32->wcreg_spdif_stream = rme32->wcreg_spdif; 858 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 859 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | 860 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id); 861 return 0; 862 } 863 864 static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream) 865 { 866 int isadat, rate; 867 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 868 struct snd_pcm_runtime *runtime = substream->runtime; 869 870 snd_pcm_set_sync(substream); 871 872 spin_lock_irq(&rme32->lock); 873 if (rme32->capture_substream != NULL) { 874 spin_unlock_irq(&rme32->lock); 875 return -EBUSY; 876 } 877 rme32->capture_substream = substream; 878 spin_unlock_irq(&rme32->lock); 879 880 if (rme32->fullduplex_mode) 881 runtime->hw = snd_rme32_spdif_fd_info; 882 else 883 runtime->hw = snd_rme32_spdif_info; 884 if (RME32_PRO_WITH_8414(rme32)) { 885 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; 886 runtime->hw.rate_max = 96000; 887 } 888 rate = snd_rme32_capture_getrate(rme32, &isadat); 889 if (rate > 0) { 890 if (isadat) { 891 return -EIO; 892 } 893 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 894 runtime->hw.rate_min = rate; 895 runtime->hw.rate_max = rate; 896 } 897 898 snd_rme32_set_buffer_constraint(rme32, runtime); 899 900 return 0; 901 } 902 903 static int 904 snd_rme32_playback_adat_open(struct snd_pcm_substream *substream) 905 { 906 int rate, dummy; 907 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 908 struct snd_pcm_runtime *runtime = substream->runtime; 909 910 snd_pcm_set_sync(substream); 911 912 spin_lock_irq(&rme32->lock); 913 if (rme32->playback_substream != NULL) { 914 spin_unlock_irq(&rme32->lock); 915 return -EBUSY; 916 } 917 rme32->wcreg |= RME32_WCR_ADAT; 918 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 919 rme32->playback_substream = substream; 920 spin_unlock_irq(&rme32->lock); 921 922 if (rme32->fullduplex_mode) 923 runtime->hw = snd_rme32_adat_fd_info; 924 else 925 runtime->hw = snd_rme32_adat_info; 926 rate = 0; 927 if (rme32->rcreg & RME32_RCR_KMODE) 928 rate = snd_rme32_capture_getrate(rme32, &dummy); 929 if (rate > 0) { 930 /* AutoSync */ 931 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 932 runtime->hw.rate_min = rate; 933 runtime->hw.rate_max = rate; 934 } 935 936 snd_rme32_set_buffer_constraint(rme32, runtime); 937 return 0; 938 } 939 940 static int 941 snd_rme32_capture_adat_open(struct snd_pcm_substream *substream) 942 { 943 int isadat, rate; 944 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 945 struct snd_pcm_runtime *runtime = substream->runtime; 946 947 if (rme32->fullduplex_mode) 948 runtime->hw = snd_rme32_adat_fd_info; 949 else 950 runtime->hw = snd_rme32_adat_info; 951 rate = snd_rme32_capture_getrate(rme32, &isadat); 952 if (rate > 0) { 953 if (!isadat) { 954 return -EIO; 955 } 956 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 957 runtime->hw.rate_min = rate; 958 runtime->hw.rate_max = rate; 959 } 960 961 snd_pcm_set_sync(substream); 962 963 spin_lock_irq(&rme32->lock); 964 if (rme32->capture_substream != NULL) { 965 spin_unlock_irq(&rme32->lock); 966 return -EBUSY; 967 } 968 rme32->capture_substream = substream; 969 spin_unlock_irq(&rme32->lock); 970 971 snd_rme32_set_buffer_constraint(rme32, runtime); 972 return 0; 973 } 974 975 static int snd_rme32_playback_close(struct snd_pcm_substream *substream) 976 { 977 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 978 int spdif = 0; 979 980 spin_lock_irq(&rme32->lock); 981 rme32->playback_substream = NULL; 982 rme32->playback_periodsize = 0; 983 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0; 984 spin_unlock_irq(&rme32->lock); 985 if (spdif) { 986 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 987 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | 988 SNDRV_CTL_EVENT_MASK_INFO, 989 &rme32->spdif_ctl->id); 990 } 991 return 0; 992 } 993 994 static int snd_rme32_capture_close(struct snd_pcm_substream *substream) 995 { 996 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 997 998 spin_lock_irq(&rme32->lock); 999 rme32->capture_substream = NULL; 1000 rme32->capture_periodsize = 0; 1001 spin_unlock_irq(&rme32->lock); 1002 return 0; 1003 } 1004 1005 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream) 1006 { 1007 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1008 1009 spin_lock_irq(&rme32->lock); 1010 if (rme32->fullduplex_mode) { 1011 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm)); 1012 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE; 1013 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1014 } else { 1015 writel(0, rme32->iobase + RME32_IO_RESET_POS); 1016 } 1017 if (rme32->wcreg & RME32_WCR_SEL) 1018 rme32->wcreg &= ~RME32_WCR_MUTE; 1019 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1020 spin_unlock_irq(&rme32->lock); 1021 return 0; 1022 } 1023 1024 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream) 1025 { 1026 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1027 1028 spin_lock_irq(&rme32->lock); 1029 if (rme32->fullduplex_mode) { 1030 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm)); 1031 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE; 1032 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2; 1033 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1034 } else { 1035 writel(0, rme32->iobase + RME32_IO_RESET_POS); 1036 } 1037 spin_unlock_irq(&rme32->lock); 1038 return 0; 1039 } 1040 1041 static int 1042 snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1043 { 1044 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1045 struct snd_pcm_substream *s; 1046 1047 spin_lock(&rme32->lock); 1048 snd_pcm_group_for_each_entry(s, substream) { 1049 if (s != rme32->playback_substream && 1050 s != rme32->capture_substream) 1051 continue; 1052 switch (cmd) { 1053 case SNDRV_PCM_TRIGGER_START: 1054 rme32->running |= (1 << s->stream); 1055 if (rme32->fullduplex_mode) { 1056 /* remember the current DMA position */ 1057 if (s == rme32->playback_substream) { 1058 rme32->playback_pcm.hw_io = 1059 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); 1060 } else { 1061 rme32->capture_pcm.hw_io = 1062 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); 1063 } 1064 } 1065 break; 1066 case SNDRV_PCM_TRIGGER_STOP: 1067 rme32->running &= ~(1 << s->stream); 1068 break; 1069 } 1070 snd_pcm_trigger_done(s, substream); 1071 } 1072 1073 switch (cmd) { 1074 case SNDRV_PCM_TRIGGER_START: 1075 if (rme32->running && ! RME32_ISWORKING(rme32)) 1076 snd_rme32_pcm_start(rme32, 0); 1077 break; 1078 case SNDRV_PCM_TRIGGER_STOP: 1079 if (! rme32->running && RME32_ISWORKING(rme32)) 1080 snd_rme32_pcm_stop(rme32, 0); 1081 break; 1082 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1083 if (rme32->running && RME32_ISWORKING(rme32)) 1084 snd_rme32_pcm_stop(rme32, 1); 1085 break; 1086 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1087 if (rme32->running && ! RME32_ISWORKING(rme32)) 1088 snd_rme32_pcm_start(rme32, 1); 1089 break; 1090 } 1091 spin_unlock(&rme32->lock); 1092 return 0; 1093 } 1094 1095 /* pointer callback for halfduplex mode */ 1096 static snd_pcm_uframes_t 1097 snd_rme32_playback_pointer(struct snd_pcm_substream *substream) 1098 { 1099 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1100 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog; 1101 } 1102 1103 static snd_pcm_uframes_t 1104 snd_rme32_capture_pointer(struct snd_pcm_substream *substream) 1105 { 1106 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1107 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog; 1108 } 1109 1110 1111 /* ack and pointer callbacks for fullduplex mode */ 1112 static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream, 1113 struct snd_pcm_indirect *rec, size_t bytes) 1114 { 1115 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1116 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, 1117 substream->runtime->dma_area + rec->sw_data, bytes); 1118 } 1119 1120 static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream) 1121 { 1122 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1123 struct snd_pcm_indirect *rec, *cprec; 1124 1125 rec = &rme32->playback_pcm; 1126 cprec = &rme32->capture_pcm; 1127 spin_lock(&rme32->lock); 1128 rec->hw_queue_size = RME32_BUFFER_SIZE; 1129 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE)) 1130 rec->hw_queue_size -= cprec->hw_ready; 1131 spin_unlock(&rme32->lock); 1132 return snd_pcm_indirect_playback_transfer(substream, rec, 1133 snd_rme32_pb_trans_copy); 1134 } 1135 1136 static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream, 1137 struct snd_pcm_indirect *rec, size_t bytes) 1138 { 1139 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1140 memcpy_fromio(substream->runtime->dma_area + rec->sw_data, 1141 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, 1142 bytes); 1143 } 1144 1145 static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream) 1146 { 1147 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1148 return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm, 1149 snd_rme32_cp_trans_copy); 1150 } 1151 1152 static snd_pcm_uframes_t 1153 snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream) 1154 { 1155 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1156 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm, 1157 snd_rme32_pcm_byteptr(rme32)); 1158 } 1159 1160 static snd_pcm_uframes_t 1161 snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream) 1162 { 1163 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1164 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm, 1165 snd_rme32_pcm_byteptr(rme32)); 1166 } 1167 1168 /* for halfduplex mode */ 1169 static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = { 1170 .open = snd_rme32_playback_spdif_open, 1171 .close = snd_rme32_playback_close, 1172 .hw_params = snd_rme32_playback_hw_params, 1173 .prepare = snd_rme32_playback_prepare, 1174 .trigger = snd_rme32_pcm_trigger, 1175 .pointer = snd_rme32_playback_pointer, 1176 .copy = snd_rme32_playback_copy, 1177 .fill_silence = snd_rme32_playback_silence, 1178 .mmap = snd_pcm_lib_mmap_iomem, 1179 }; 1180 1181 static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = { 1182 .open = snd_rme32_capture_spdif_open, 1183 .close = snd_rme32_capture_close, 1184 .hw_params = snd_rme32_capture_hw_params, 1185 .prepare = snd_rme32_capture_prepare, 1186 .trigger = snd_rme32_pcm_trigger, 1187 .pointer = snd_rme32_capture_pointer, 1188 .copy = snd_rme32_capture_copy, 1189 .mmap = snd_pcm_lib_mmap_iomem, 1190 }; 1191 1192 static const struct snd_pcm_ops snd_rme32_playback_adat_ops = { 1193 .open = snd_rme32_playback_adat_open, 1194 .close = snd_rme32_playback_close, 1195 .hw_params = snd_rme32_playback_hw_params, 1196 .prepare = snd_rme32_playback_prepare, 1197 .trigger = snd_rme32_pcm_trigger, 1198 .pointer = snd_rme32_playback_pointer, 1199 .copy = snd_rme32_playback_copy, 1200 .fill_silence = snd_rme32_playback_silence, 1201 .mmap = snd_pcm_lib_mmap_iomem, 1202 }; 1203 1204 static const struct snd_pcm_ops snd_rme32_capture_adat_ops = { 1205 .open = snd_rme32_capture_adat_open, 1206 .close = snd_rme32_capture_close, 1207 .hw_params = snd_rme32_capture_hw_params, 1208 .prepare = snd_rme32_capture_prepare, 1209 .trigger = snd_rme32_pcm_trigger, 1210 .pointer = snd_rme32_capture_pointer, 1211 .copy = snd_rme32_capture_copy, 1212 .mmap = snd_pcm_lib_mmap_iomem, 1213 }; 1214 1215 /* for fullduplex mode */ 1216 static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = { 1217 .open = snd_rme32_playback_spdif_open, 1218 .close = snd_rme32_playback_close, 1219 .hw_params = snd_rme32_playback_hw_params, 1220 .prepare = snd_rme32_playback_prepare, 1221 .trigger = snd_rme32_pcm_trigger, 1222 .pointer = snd_rme32_playback_fd_pointer, 1223 .ack = snd_rme32_playback_fd_ack, 1224 }; 1225 1226 static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = { 1227 .open = snd_rme32_capture_spdif_open, 1228 .close = snd_rme32_capture_close, 1229 .hw_params = snd_rme32_capture_hw_params, 1230 .prepare = snd_rme32_capture_prepare, 1231 .trigger = snd_rme32_pcm_trigger, 1232 .pointer = snd_rme32_capture_fd_pointer, 1233 .ack = snd_rme32_capture_fd_ack, 1234 }; 1235 1236 static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = { 1237 .open = snd_rme32_playback_adat_open, 1238 .close = snd_rme32_playback_close, 1239 .hw_params = snd_rme32_playback_hw_params, 1240 .prepare = snd_rme32_playback_prepare, 1241 .trigger = snd_rme32_pcm_trigger, 1242 .pointer = snd_rme32_playback_fd_pointer, 1243 .ack = snd_rme32_playback_fd_ack, 1244 }; 1245 1246 static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = { 1247 .open = snd_rme32_capture_adat_open, 1248 .close = snd_rme32_capture_close, 1249 .hw_params = snd_rme32_capture_hw_params, 1250 .prepare = snd_rme32_capture_prepare, 1251 .trigger = snd_rme32_pcm_trigger, 1252 .pointer = snd_rme32_capture_fd_pointer, 1253 .ack = snd_rme32_capture_fd_ack, 1254 }; 1255 1256 static void snd_rme32_free(struct rme32 *rme32) 1257 { 1258 if (rme32->irq >= 0) 1259 snd_rme32_pcm_stop(rme32, 0); 1260 } 1261 1262 static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm) 1263 { 1264 struct rme32 *rme32 = (struct rme32 *) pcm->private_data; 1265 rme32->spdif_pcm = NULL; 1266 } 1267 1268 static void 1269 snd_rme32_free_adat_pcm(struct snd_pcm *pcm) 1270 { 1271 struct rme32 *rme32 = (struct rme32 *) pcm->private_data; 1272 rme32->adat_pcm = NULL; 1273 } 1274 1275 static int snd_rme32_create(struct rme32 *rme32) 1276 { 1277 struct pci_dev *pci = rme32->pci; 1278 int err; 1279 1280 rme32->irq = -1; 1281 spin_lock_init(&rme32->lock); 1282 1283 err = pcim_enable_device(pci); 1284 if (err < 0) 1285 return err; 1286 1287 err = pci_request_regions(pci, "RME32"); 1288 if (err < 0) 1289 return err; 1290 rme32->port = pci_resource_start(rme32->pci, 0); 1291 1292 rme32->iobase = devm_ioremap(&pci->dev, rme32->port, RME32_IO_SIZE); 1293 if (!rme32->iobase) { 1294 dev_err(rme32->card->dev, 1295 "unable to remap memory region 0x%lx-0x%lx\n", 1296 rme32->port, rme32->port + RME32_IO_SIZE - 1); 1297 return -ENOMEM; 1298 } 1299 1300 if (devm_request_irq(&pci->dev, pci->irq, snd_rme32_interrupt, 1301 IRQF_SHARED, KBUILD_MODNAME, rme32)) { 1302 dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq); 1303 return -EBUSY; 1304 } 1305 rme32->irq = pci->irq; 1306 rme32->card->sync_irq = rme32->irq; 1307 1308 /* read the card's revision number */ 1309 pci_read_config_byte(pci, 8, &rme32->rev); 1310 1311 /* set up ALSA pcm device for S/PDIF */ 1312 err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm); 1313 if (err < 0) 1314 return err; 1315 rme32->spdif_pcm->private_data = rme32; 1316 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm; 1317 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958"); 1318 if (rme32->fullduplex_mode) { 1319 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1320 &snd_rme32_playback_spdif_fd_ops); 1321 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, 1322 &snd_rme32_capture_spdif_fd_ops); 1323 snd_pcm_set_managed_buffer_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS, 1324 NULL, 0, RME32_MID_BUFFER_SIZE); 1325 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 1326 } else { 1327 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1328 &snd_rme32_playback_spdif_ops); 1329 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, 1330 &snd_rme32_capture_spdif_ops); 1331 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; 1332 } 1333 1334 /* set up ALSA pcm device for ADAT */ 1335 if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) || 1336 (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) { 1337 /* ADAT is not available on DIGI32 and DIGI32 Pro */ 1338 rme32->adat_pcm = NULL; 1339 } 1340 else { 1341 err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1, 1342 1, 1, &rme32->adat_pcm); 1343 if (err < 0) 1344 return err; 1345 rme32->adat_pcm->private_data = rme32; 1346 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm; 1347 strcpy(rme32->adat_pcm->name, "Digi32 ADAT"); 1348 if (rme32->fullduplex_mode) { 1349 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1350 &snd_rme32_playback_adat_fd_ops); 1351 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 1352 &snd_rme32_capture_adat_fd_ops); 1353 snd_pcm_set_managed_buffer_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS, 1354 NULL, 1355 0, RME32_MID_BUFFER_SIZE); 1356 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 1357 } else { 1358 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1359 &snd_rme32_playback_adat_ops); 1360 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 1361 &snd_rme32_capture_adat_ops); 1362 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; 1363 } 1364 } 1365 1366 1367 rme32->playback_periodsize = 0; 1368 rme32->capture_periodsize = 0; 1369 1370 /* make sure playback/capture is stopped, if by some reason active */ 1371 snd_rme32_pcm_stop(rme32, 0); 1372 1373 /* reset DAC */ 1374 snd_rme32_reset_dac(rme32); 1375 1376 /* reset buffer pointer */ 1377 writel(0, rme32->iobase + RME32_IO_RESET_POS); 1378 1379 /* set default values in registers */ 1380 rme32->wcreg = RME32_WCR_SEL | /* normal playback */ 1381 RME32_WCR_INP_0 | /* input select */ 1382 RME32_WCR_MUTE; /* muting on */ 1383 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1384 1385 1386 /* init switch interface */ 1387 err = snd_rme32_create_switches(rme32->card, rme32); 1388 if (err < 0) 1389 return err; 1390 1391 /* init proc interface */ 1392 snd_rme32_proc_init(rme32); 1393 1394 rme32->capture_substream = NULL; 1395 rme32->playback_substream = NULL; 1396 1397 return 0; 1398 } 1399 1400 /* 1401 * proc interface 1402 */ 1403 1404 static void 1405 snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer) 1406 { 1407 int n; 1408 struct rme32 *rme32 = (struct rme32 *) entry->private_data; 1409 1410 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); 1411 1412 snd_iprintf(buffer, rme32->card->longname); 1413 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1); 1414 1415 snd_iprintf(buffer, "\nGeneral settings\n"); 1416 if (rme32->fullduplex_mode) 1417 snd_iprintf(buffer, " Full-duplex mode\n"); 1418 else 1419 snd_iprintf(buffer, " Half-duplex mode\n"); 1420 if (RME32_PRO_WITH_8414(rme32)) { 1421 snd_iprintf(buffer, " receiver: CS8414\n"); 1422 } else { 1423 snd_iprintf(buffer, " receiver: CS8412\n"); 1424 } 1425 if (rme32->wcreg & RME32_WCR_MODE24) { 1426 snd_iprintf(buffer, " format: 24 bit"); 1427 } else { 1428 snd_iprintf(buffer, " format: 16 bit"); 1429 } 1430 if (rme32->wcreg & RME32_WCR_MONO) { 1431 snd_iprintf(buffer, ", Mono\n"); 1432 } else { 1433 snd_iprintf(buffer, ", Stereo\n"); 1434 } 1435 1436 snd_iprintf(buffer, "\nInput settings\n"); 1437 switch (snd_rme32_getinputtype(rme32)) { 1438 case RME32_INPUT_OPTICAL: 1439 snd_iprintf(buffer, " input: optical"); 1440 break; 1441 case RME32_INPUT_COAXIAL: 1442 snd_iprintf(buffer, " input: coaxial"); 1443 break; 1444 case RME32_INPUT_INTERNAL: 1445 snd_iprintf(buffer, " input: internal"); 1446 break; 1447 case RME32_INPUT_XLR: 1448 snd_iprintf(buffer, " input: XLR"); 1449 break; 1450 } 1451 if (snd_rme32_capture_getrate(rme32, &n) < 0) { 1452 snd_iprintf(buffer, "\n sample rate: no valid signal\n"); 1453 } else { 1454 if (n) { 1455 snd_iprintf(buffer, " (8 channels)\n"); 1456 } else { 1457 snd_iprintf(buffer, " (2 channels)\n"); 1458 } 1459 snd_iprintf(buffer, " sample rate: %d Hz\n", 1460 snd_rme32_capture_getrate(rme32, &n)); 1461 } 1462 1463 snd_iprintf(buffer, "\nOutput settings\n"); 1464 if (rme32->wcreg & RME32_WCR_SEL) { 1465 snd_iprintf(buffer, " output signal: normal playback"); 1466 } else { 1467 snd_iprintf(buffer, " output signal: same as input"); 1468 } 1469 if (rme32->wcreg & RME32_WCR_MUTE) { 1470 snd_iprintf(buffer, " (muted)\n"); 1471 } else { 1472 snd_iprintf(buffer, "\n"); 1473 } 1474 1475 /* master output frequency */ 1476 if (! 1477 ((!(rme32->wcreg & RME32_WCR_FREQ_0)) 1478 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) { 1479 snd_iprintf(buffer, " sample rate: %d Hz\n", 1480 snd_rme32_playback_getrate(rme32)); 1481 } 1482 if (rme32->rcreg & RME32_RCR_KMODE) { 1483 snd_iprintf(buffer, " sample clock source: AutoSync\n"); 1484 } else { 1485 snd_iprintf(buffer, " sample clock source: Internal\n"); 1486 } 1487 if (rme32->wcreg & RME32_WCR_PRO) { 1488 snd_iprintf(buffer, " format: AES/EBU (professional)\n"); 1489 } else { 1490 snd_iprintf(buffer, " format: IEC958 (consumer)\n"); 1491 } 1492 if (rme32->wcreg & RME32_WCR_EMP) { 1493 snd_iprintf(buffer, " emphasis: on\n"); 1494 } else { 1495 snd_iprintf(buffer, " emphasis: off\n"); 1496 } 1497 } 1498 1499 static void snd_rme32_proc_init(struct rme32 *rme32) 1500 { 1501 snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read); 1502 } 1503 1504 /* 1505 * control interface 1506 */ 1507 1508 #define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info 1509 1510 static int 1511 snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol, 1512 struct snd_ctl_elem_value *ucontrol) 1513 { 1514 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1515 1516 spin_lock_irq(&rme32->lock); 1517 ucontrol->value.integer.value[0] = 1518 rme32->wcreg & RME32_WCR_SEL ? 0 : 1; 1519 spin_unlock_irq(&rme32->lock); 1520 return 0; 1521 } 1522 static int 1523 snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol, 1524 struct snd_ctl_elem_value *ucontrol) 1525 { 1526 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1527 unsigned int val; 1528 int change; 1529 1530 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL; 1531 spin_lock_irq(&rme32->lock); 1532 val = (rme32->wcreg & ~RME32_WCR_SEL) | val; 1533 change = val != rme32->wcreg; 1534 if (ucontrol->value.integer.value[0]) 1535 val &= ~RME32_WCR_MUTE; 1536 else 1537 val |= RME32_WCR_MUTE; 1538 rme32->wcreg = val; 1539 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1540 spin_unlock_irq(&rme32->lock); 1541 return change; 1542 } 1543 1544 static int 1545 snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol, 1546 struct snd_ctl_elem_info *uinfo) 1547 { 1548 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1549 static const char * const texts[4] = { 1550 "Optical", "Coaxial", "Internal", "XLR" 1551 }; 1552 int num_items; 1553 1554 switch (rme32->pci->device) { 1555 case PCI_DEVICE_ID_RME_DIGI32: 1556 case PCI_DEVICE_ID_RME_DIGI32_8: 1557 num_items = 3; 1558 break; 1559 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1560 num_items = 4; 1561 break; 1562 default: 1563 snd_BUG(); 1564 return -EINVAL; 1565 } 1566 return snd_ctl_enum_info(uinfo, 1, num_items, texts); 1567 } 1568 static int 1569 snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol, 1570 struct snd_ctl_elem_value *ucontrol) 1571 { 1572 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1573 unsigned int items = 3; 1574 1575 spin_lock_irq(&rme32->lock); 1576 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32); 1577 1578 switch (rme32->pci->device) { 1579 case PCI_DEVICE_ID_RME_DIGI32: 1580 case PCI_DEVICE_ID_RME_DIGI32_8: 1581 items = 3; 1582 break; 1583 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1584 items = 4; 1585 break; 1586 default: 1587 snd_BUG(); 1588 break; 1589 } 1590 if (ucontrol->value.enumerated.item[0] >= items) { 1591 ucontrol->value.enumerated.item[0] = items - 1; 1592 } 1593 1594 spin_unlock_irq(&rme32->lock); 1595 return 0; 1596 } 1597 static int 1598 snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol, 1599 struct snd_ctl_elem_value *ucontrol) 1600 { 1601 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1602 unsigned int val; 1603 int change, items = 3; 1604 1605 switch (rme32->pci->device) { 1606 case PCI_DEVICE_ID_RME_DIGI32: 1607 case PCI_DEVICE_ID_RME_DIGI32_8: 1608 items = 3; 1609 break; 1610 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1611 items = 4; 1612 break; 1613 default: 1614 snd_BUG(); 1615 break; 1616 } 1617 val = ucontrol->value.enumerated.item[0] % items; 1618 1619 spin_lock_irq(&rme32->lock); 1620 change = val != (unsigned int)snd_rme32_getinputtype(rme32); 1621 snd_rme32_setinputtype(rme32, val); 1622 spin_unlock_irq(&rme32->lock); 1623 return change; 1624 } 1625 1626 static int 1627 snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol, 1628 struct snd_ctl_elem_info *uinfo) 1629 { 1630 static const char * const texts[4] = { "AutoSync", 1631 "Internal 32.0kHz", 1632 "Internal 44.1kHz", 1633 "Internal 48.0kHz" }; 1634 1635 return snd_ctl_enum_info(uinfo, 1, 4, texts); 1636 } 1637 static int 1638 snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol, 1639 struct snd_ctl_elem_value *ucontrol) 1640 { 1641 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1642 1643 spin_lock_irq(&rme32->lock); 1644 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32); 1645 spin_unlock_irq(&rme32->lock); 1646 return 0; 1647 } 1648 static int 1649 snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol, 1650 struct snd_ctl_elem_value *ucontrol) 1651 { 1652 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1653 unsigned int val; 1654 int change; 1655 1656 val = ucontrol->value.enumerated.item[0] % 3; 1657 spin_lock_irq(&rme32->lock); 1658 change = val != (unsigned int)snd_rme32_getclockmode(rme32); 1659 snd_rme32_setclockmode(rme32, val); 1660 spin_unlock_irq(&rme32->lock); 1661 return change; 1662 } 1663 1664 static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes) 1665 { 1666 u32 val = 0; 1667 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0; 1668 if (val & RME32_WCR_PRO) 1669 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0; 1670 else 1671 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0; 1672 return val; 1673 } 1674 1675 static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val) 1676 { 1677 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0); 1678 if (val & RME32_WCR_PRO) 1679 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 1680 else 1681 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 1682 } 1683 1684 static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol, 1685 struct snd_ctl_elem_info *uinfo) 1686 { 1687 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1688 uinfo->count = 1; 1689 return 0; 1690 } 1691 1692 static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol, 1693 struct snd_ctl_elem_value *ucontrol) 1694 { 1695 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1696 1697 snd_rme32_convert_to_aes(&ucontrol->value.iec958, 1698 rme32->wcreg_spdif); 1699 return 0; 1700 } 1701 1702 static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol, 1703 struct snd_ctl_elem_value *ucontrol) 1704 { 1705 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1706 int change; 1707 u32 val; 1708 1709 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); 1710 spin_lock_irq(&rme32->lock); 1711 change = val != rme32->wcreg_spdif; 1712 rme32->wcreg_spdif = val; 1713 spin_unlock_irq(&rme32->lock); 1714 return change; 1715 } 1716 1717 static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol, 1718 struct snd_ctl_elem_info *uinfo) 1719 { 1720 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1721 uinfo->count = 1; 1722 return 0; 1723 } 1724 1725 static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol, 1726 struct snd_ctl_elem_value * 1727 ucontrol) 1728 { 1729 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1730 1731 snd_rme32_convert_to_aes(&ucontrol->value.iec958, 1732 rme32->wcreg_spdif_stream); 1733 return 0; 1734 } 1735 1736 static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol, 1737 struct snd_ctl_elem_value * 1738 ucontrol) 1739 { 1740 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1741 int change; 1742 u32 val; 1743 1744 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); 1745 spin_lock_irq(&rme32->lock); 1746 change = val != rme32->wcreg_spdif_stream; 1747 rme32->wcreg_spdif_stream = val; 1748 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); 1749 rme32->wcreg |= val; 1750 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1751 spin_unlock_irq(&rme32->lock); 1752 return change; 1753 } 1754 1755 static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol, 1756 struct snd_ctl_elem_info *uinfo) 1757 { 1758 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1759 uinfo->count = 1; 1760 return 0; 1761 } 1762 1763 static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol, 1764 struct snd_ctl_elem_value * 1765 ucontrol) 1766 { 1767 ucontrol->value.iec958.status[0] = kcontrol->private_value; 1768 return 0; 1769 } 1770 1771 static const struct snd_kcontrol_new snd_rme32_controls[] = { 1772 { 1773 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1774 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1775 .info = snd_rme32_control_spdif_info, 1776 .get = snd_rme32_control_spdif_get, 1777 .put = snd_rme32_control_spdif_put 1778 }, 1779 { 1780 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 1781 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1782 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), 1783 .info = snd_rme32_control_spdif_stream_info, 1784 .get = snd_rme32_control_spdif_stream_get, 1785 .put = snd_rme32_control_spdif_stream_put 1786 }, 1787 { 1788 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1789 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1790 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), 1791 .info = snd_rme32_control_spdif_mask_info, 1792 .get = snd_rme32_control_spdif_mask_get, 1793 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS 1794 }, 1795 { 1796 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1797 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1798 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK), 1799 .info = snd_rme32_control_spdif_mask_info, 1800 .get = snd_rme32_control_spdif_mask_get, 1801 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS 1802 }, 1803 { 1804 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1805 .name = "Input Connector", 1806 .info = snd_rme32_info_inputtype_control, 1807 .get = snd_rme32_get_inputtype_control, 1808 .put = snd_rme32_put_inputtype_control 1809 }, 1810 { 1811 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1812 .name = "Loopback Input", 1813 .info = snd_rme32_info_loopback_control, 1814 .get = snd_rme32_get_loopback_control, 1815 .put = snd_rme32_put_loopback_control 1816 }, 1817 { 1818 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1819 .name = "Sample Clock Source", 1820 .info = snd_rme32_info_clockmode_control, 1821 .get = snd_rme32_get_clockmode_control, 1822 .put = snd_rme32_put_clockmode_control 1823 } 1824 }; 1825 1826 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32) 1827 { 1828 int idx, err; 1829 struct snd_kcontrol *kctl; 1830 1831 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) { 1832 kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32); 1833 err = snd_ctl_add(card, kctl); 1834 if (err < 0) 1835 return err; 1836 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 1837 rme32->spdif_ctl = kctl; 1838 } 1839 1840 return 0; 1841 } 1842 1843 /* 1844 * Card initialisation 1845 */ 1846 1847 static void snd_rme32_card_free(struct snd_card *card) 1848 { 1849 snd_rme32_free(card->private_data); 1850 } 1851 1852 static int 1853 __snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1854 { 1855 static int dev; 1856 struct rme32 *rme32; 1857 struct snd_card *card; 1858 int err; 1859 1860 if (dev >= SNDRV_CARDS) { 1861 return -ENODEV; 1862 } 1863 if (!enable[dev]) { 1864 dev++; 1865 return -ENOENT; 1866 } 1867 1868 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1869 sizeof(*rme32), &card); 1870 if (err < 0) 1871 return err; 1872 card->private_free = snd_rme32_card_free; 1873 rme32 = (struct rme32 *) card->private_data; 1874 rme32->card = card; 1875 rme32->pci = pci; 1876 if (fullduplex[dev]) 1877 rme32->fullduplex_mode = 1; 1878 err = snd_rme32_create(rme32); 1879 if (err < 0) 1880 return err; 1881 1882 strcpy(card->driver, "Digi32"); 1883 switch (rme32->pci->device) { 1884 case PCI_DEVICE_ID_RME_DIGI32: 1885 strcpy(card->shortname, "RME Digi32"); 1886 break; 1887 case PCI_DEVICE_ID_RME_DIGI32_8: 1888 strcpy(card->shortname, "RME Digi32/8"); 1889 break; 1890 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1891 strcpy(card->shortname, "RME Digi32 PRO"); 1892 break; 1893 } 1894 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d", 1895 card->shortname, rme32->rev, rme32->port, rme32->irq); 1896 1897 err = snd_card_register(card); 1898 if (err < 0) 1899 return err; 1900 pci_set_drvdata(pci, card); 1901 dev++; 1902 return 0; 1903 } 1904 1905 static int 1906 snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1907 { 1908 return snd_card_free_on_error(&pci->dev, __snd_rme32_probe(pci, pci_id)); 1909 } 1910 1911 static struct pci_driver rme32_driver = { 1912 .name = KBUILD_MODNAME, 1913 .id_table = snd_rme32_ids, 1914 .probe = snd_rme32_probe, 1915 }; 1916 1917 module_pci_driver(rme32_driver); 1918