1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/clk-provider.h>
13 #include <linux/regmap.h>
14
15 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
16
17 #include "common.h"
18 #include "clk-regmap.h"
19 #include "clk-regmap-divider.h"
20 #include "clk-alpha-pll.h"
21 #include "clk-rcg.h"
22 #include "clk-branch.h"
23 #include "reset.h"
24 #include "gdsc.h"
25
26
27 enum {
28 P_XO,
29 P_GPLL0,
30 P_MMPLL0,
31 P_MMPLL1,
32 P_MMPLL3,
33 P_MMPLL4,
34 P_MMPLL5, /* Is this one even used by anything? Downstream doesn't tell. */
35 P_DSI0PLL,
36 P_DSI1PLL,
37 P_DSI0PLL_BYTE,
38 P_DSI1PLL_BYTE,
39 P_HDMIPLL,
40 };
41 static const struct parent_map mmcc_xo_gpll0_map[] = {
42 { P_XO, 0 },
43 { P_GPLL0, 5 }
44 };
45
46 static const struct clk_parent_data mmcc_xo_gpll0[] = {
47 { .fw_name = "xo" },
48 { .fw_name = "gpll0" },
49 };
50
51 static const struct parent_map mmss_xo_hdmi_map[] = {
52 { P_XO, 0 },
53 { P_HDMIPLL, 3 }
54 };
55
56 static const struct clk_parent_data mmss_xo_hdmi[] = {
57 { .fw_name = "xo" },
58 { .fw_name = "hdmipll" },
59 };
60
61 static const struct parent_map mmcc_xo_dsi0pll_dsi1pll_map[] = {
62 { P_XO, 0 },
63 { P_DSI0PLL, 1 },
64 { P_DSI1PLL, 2 }
65 };
66
67 static const struct clk_parent_data mmcc_xo_dsi0pll_dsi1pll[] = {
68 { .fw_name = "xo" },
69 { .fw_name = "dsi0pll" },
70 { .fw_name = "dsi1pll" },
71 };
72
73 static const struct parent_map mmcc_xo_dsibyte_map[] = {
74 { P_XO, 0 },
75 { P_DSI0PLL_BYTE, 1 },
76 { P_DSI1PLL_BYTE, 2 }
77 };
78
79 static const struct clk_parent_data mmcc_xo_dsibyte[] = {
80 { .fw_name = "xo" },
81 { .fw_name = "dsi0pllbyte" },
82 { .fw_name = "dsi1pllbyte" },
83 };
84
85 static const struct pll_vco mmpll_p_vco[] = {
86 { 250000000, 500000000, 3 },
87 { 500000000, 1000000000, 2 },
88 { 1000000000, 1500000000, 1 },
89 { 1500000000, 2000000000, 0 },
90 };
91
92 static const struct pll_vco mmpll_t_vco[] = {
93 { 500000000, 1500000000, 0 },
94 };
95
96 static const struct alpha_pll_config mmpll_p_config = {
97 .post_div_mask = 0xf00,
98 };
99
100 static struct clk_alpha_pll mmpll0_early = {
101 .offset = 0x0,
102 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
103 .vco_table = mmpll_p_vco,
104 .num_vco = ARRAY_SIZE(mmpll_p_vco),
105 .clkr = {
106 .enable_reg = 0x100,
107 .enable_mask = BIT(0),
108 .hw.init = &(struct clk_init_data){
109 .name = "mmpll0_early",
110 .parent_data = &(const struct clk_parent_data){
111 .fw_name = "xo",
112 },
113 .num_parents = 1,
114 .ops = &clk_alpha_pll_ops,
115 },
116 },
117 };
118
119 static struct clk_alpha_pll_postdiv mmpll0 = {
120 .offset = 0x0,
121 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
122 .width = 4,
123 .clkr.hw.init = &(struct clk_init_data){
124 .name = "mmpll0",
125 .parent_hws = (const struct clk_hw *[]){ &mmpll0_early.clkr.hw },
126 .num_parents = 1,
127 .ops = &clk_alpha_pll_postdiv_ops,
128 .flags = CLK_SET_RATE_PARENT,
129 },
130 };
131
132 static struct clk_alpha_pll mmpll1_early = {
133 .offset = 0x30,
134 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
135 .vco_table = mmpll_p_vco,
136 .num_vco = ARRAY_SIZE(mmpll_p_vco),
137 .clkr = {
138 .enable_reg = 0x100,
139 .enable_mask = BIT(1),
140 .hw.init = &(struct clk_init_data){
141 .name = "mmpll1_early",
142 .parent_data = &(const struct clk_parent_data){
143 .fw_name = "xo",
144 },
145 .num_parents = 1,
146 .ops = &clk_alpha_pll_ops,
147 }
148 },
149 };
150
151 static struct clk_alpha_pll_postdiv mmpll1 = {
152 .offset = 0x30,
153 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
154 .width = 4,
155 .clkr.hw.init = &(struct clk_init_data){
156 .name = "mmpll1",
157 .parent_hws = (const struct clk_hw *[]){ &mmpll1_early.clkr.hw },
158 .num_parents = 1,
159 .ops = &clk_alpha_pll_postdiv_ops,
160 .flags = CLK_SET_RATE_PARENT,
161 },
162 };
163
164 static struct clk_alpha_pll mmpll3_early = {
165 .offset = 0x60,
166 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
167 .vco_table = mmpll_p_vco,
168 .num_vco = ARRAY_SIZE(mmpll_p_vco),
169 .clkr.hw.init = &(struct clk_init_data){
170 .name = "mmpll3_early",
171 .parent_data = &(const struct clk_parent_data){
172 .fw_name = "xo",
173 },
174 .num_parents = 1,
175 .ops = &clk_alpha_pll_ops,
176 },
177 };
178
179 static struct clk_alpha_pll_postdiv mmpll3 = {
180 .offset = 0x60,
181 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
182 .width = 4,
183 .clkr.hw.init = &(struct clk_init_data){
184 .name = "mmpll3",
185 .parent_hws = (const struct clk_hw *[]){ &mmpll3_early.clkr.hw },
186 .num_parents = 1,
187 .ops = &clk_alpha_pll_postdiv_ops,
188 .flags = CLK_SET_RATE_PARENT,
189 },
190 };
191
192 static struct clk_alpha_pll mmpll4_early = {
193 .offset = 0x90,
194 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
195 .vco_table = mmpll_t_vco,
196 .num_vco = ARRAY_SIZE(mmpll_t_vco),
197 .clkr.hw.init = &(struct clk_init_data){
198 .name = "mmpll4_early",
199 .parent_data = &(const struct clk_parent_data){
200 .fw_name = "xo",
201 },
202 .num_parents = 1,
203 .ops = &clk_alpha_pll_ops,
204 },
205 };
206
207 static struct clk_alpha_pll_postdiv mmpll4 = {
208 .offset = 0x90,
209 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
210 .width = 2,
211 .clkr.hw.init = &(struct clk_init_data){
212 .name = "mmpll4",
213 .parent_hws = (const struct clk_hw *[]){ &mmpll4_early.clkr.hw },
214 .num_parents = 1,
215 .ops = &clk_alpha_pll_postdiv_ops,
216 .flags = CLK_SET_RATE_PARENT,
217 },
218 };
219
220 static const struct parent_map mmcc_xo_gpll0_mmpll1_map[] = {
221 { P_XO, 0 },
222 { P_GPLL0, 5 },
223 { P_MMPLL1, 2 }
224 };
225
226 static const struct clk_parent_data mmcc_xo_gpll0_mmpll1[] = {
227 { .fw_name = "xo" },
228 { .fw_name = "gpll0" },
229 { .hw = &mmpll1.clkr.hw },
230 };
231
232 static const struct parent_map mmcc_xo_gpll0_mmpll0_map[] = {
233 { P_XO, 0 },
234 { P_GPLL0, 5 },
235 { P_MMPLL0, 1 }
236 };
237
238 static const struct clk_parent_data mmcc_xo_gpll0_mmpll0[] = {
239 { .fw_name = "xo" },
240 { .fw_name = "gpll0" },
241 { .hw = &mmpll0.clkr.hw },
242 };
243
244 static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll3_map[] = {
245 { P_XO, 0 },
246 { P_GPLL0, 5 },
247 { P_MMPLL0, 1 },
248 { P_MMPLL3, 3 }
249 };
250
251 static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll3[] = {
252 { .fw_name = "xo" },
253 { .fw_name = "gpll0" },
254 { .hw = &mmpll0.clkr.hw },
255 { .hw = &mmpll3.clkr.hw },
256 };
257
258 static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll4_map[] = {
259 { P_XO, 0 },
260 { P_GPLL0, 5 },
261 { P_MMPLL0, 1 },
262 { P_MMPLL4, 3 }
263 };
264
265 static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll4[] = {
266 { .fw_name = "xo" },
267 { .fw_name = "gpll0" },
268 { .hw = &mmpll0.clkr.hw },
269 { .hw = &mmpll4.clkr.hw },
270 };
271
272 static struct clk_alpha_pll mmpll5_early = {
273 .offset = 0xc0,
274 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
275 .vco_table = mmpll_p_vco,
276 .num_vco = ARRAY_SIZE(mmpll_p_vco),
277 .clkr.hw.init = &(struct clk_init_data){
278 .name = "mmpll5_early",
279 .parent_data = &(const struct clk_parent_data){
280 .fw_name = "xo",
281 },
282 .num_parents = 1,
283 .ops = &clk_alpha_pll_ops,
284 },
285 };
286
287 static struct clk_alpha_pll_postdiv mmpll5 = {
288 .offset = 0xc0,
289 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
290 .width = 4,
291 .clkr.hw.init = &(struct clk_init_data){
292 .name = "mmpll5",
293 .parent_hws = (const struct clk_hw *[]){ &mmpll5_early.clkr.hw },
294 .num_parents = 1,
295 .ops = &clk_alpha_pll_postdiv_ops,
296 .flags = CLK_SET_RATE_PARENT,
297 },
298 };
299
300 static const struct freq_tbl ftbl_ahb_clk_src[] = {
301 /* Note: There might be more frequencies desired here. */
302 F(19200000, P_XO, 1, 0, 0),
303 F(40000000, P_GPLL0, 15, 0, 0),
304 F(80000000, P_MMPLL0, 10, 0, 0),
305 { }
306 };
307
308 static struct clk_rcg2 ahb_clk_src = {
309 .cmd_rcgr = 0x5000,
310 .hid_width = 5,
311 .parent_map = mmcc_xo_gpll0_mmpll0_map,
312 .freq_tbl = ftbl_ahb_clk_src,
313 .clkr.hw.init = &(struct clk_init_data){
314 .name = "ahb_clk_src",
315 .parent_data = mmcc_xo_gpll0_mmpll0,
316 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
317 .ops = &clk_rcg2_ops,
318 },
319 };
320
321 static const struct freq_tbl ftbl_axi_clk_src[] = {
322 F(75000000, P_GPLL0, 8, 0, 0),
323 F(150000000, P_GPLL0, 4, 0, 0),
324 F(333430000, P_MMPLL1, 3.5, 0, 0),
325 F(466800000, P_MMPLL1, 2.5, 0, 0),
326 { }
327 };
328
329 static const struct freq_tbl ftbl_axi_clk_src_8992[] = {
330 F(75000000, P_GPLL0, 8, 0, 0),
331 F(150000000, P_GPLL0, 4, 0, 0),
332 F(300000000, P_GPLL0, 2, 0, 0),
333 F(404000000, P_MMPLL1, 2, 0, 0),
334 { }
335 };
336
337 static struct clk_rcg2 axi_clk_src = {
338 .cmd_rcgr = 0x5040,
339 .hid_width = 5,
340 .parent_map = mmcc_xo_gpll0_mmpll1_map,
341 .freq_tbl = ftbl_axi_clk_src,
342 .clkr.hw.init = &(struct clk_init_data){
343 .name = "axi_clk_src",
344 .parent_data = mmcc_xo_gpll0_mmpll1,
345 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll1),
346 .ops = &clk_rcg2_ops,
347 },
348 };
349
350 static const struct freq_tbl ftbl_csi0_1_2_3_clk_src[] = {
351 F(100000000, P_GPLL0, 6, 0, 0),
352 F(240000000, P_GPLL0, 2.5, 0, 0),
353 F(266670000, P_MMPLL0, 3, 0, 0),
354 { }
355 };
356
357 static const struct freq_tbl ftbl_csi0_1_2_3_clk_src_8992[] = {
358 F(100000000, P_GPLL0, 6, 0, 0),
359 F(266670000, P_MMPLL0, 3, 0, 0),
360 { }
361 };
362
363 static struct clk_rcg2 csi0_clk_src = {
364 .cmd_rcgr = 0x3090,
365 .hid_width = 5,
366 .parent_map = mmcc_xo_gpll0_mmpll0_map,
367 .freq_tbl = ftbl_csi0_1_2_3_clk_src,
368 .clkr.hw.init = &(struct clk_init_data){
369 .name = "csi0_clk_src",
370 .parent_data = mmcc_xo_gpll0_mmpll0,
371 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
372 .ops = &clk_rcg2_ops,
373 },
374 };
375
376 static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
377 F(66670000, P_GPLL0, 9, 0, 0),
378 F(100000000, P_GPLL0, 6, 0, 0),
379 F(133330000, P_GPLL0, 4.5, 0, 0),
380 F(150000000, P_GPLL0, 4, 0, 0),
381 F(200000000, P_MMPLL0, 4, 0, 0),
382 F(240000000, P_GPLL0, 2.5, 0, 0),
383 F(266670000, P_MMPLL0, 3, 0, 0),
384 F(320000000, P_MMPLL0, 2.5, 0, 0),
385 F(510000000, P_MMPLL3, 2, 0, 0),
386 { }
387 };
388
389 static const struct freq_tbl ftbl_vcodec0_clk_src_8992[] = {
390 F(66670000, P_GPLL0, 9, 0, 0),
391 F(100000000, P_GPLL0, 6, 0, 0),
392 F(133330000, P_GPLL0, 4.5, 0, 0),
393 F(200000000, P_MMPLL0, 4, 0, 0),
394 F(320000000, P_MMPLL0, 2.5, 0, 0),
395 F(510000000, P_MMPLL3, 2, 0, 0),
396 { }
397 };
398
399 static struct clk_rcg2 vcodec0_clk_src = {
400 .cmd_rcgr = 0x1000,
401 .mnd_width = 8,
402 .hid_width = 5,
403 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll3_map,
404 .freq_tbl = ftbl_vcodec0_clk_src,
405 .clkr.hw.init = &(struct clk_init_data){
406 .name = "vcodec0_clk_src",
407 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll3,
408 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll3),
409 .ops = &clk_rcg2_ops,
410 },
411 };
412
413 static struct clk_rcg2 csi1_clk_src = {
414 .cmd_rcgr = 0x3100,
415 .hid_width = 5,
416 .parent_map = mmcc_xo_gpll0_mmpll0_map,
417 .freq_tbl = ftbl_csi0_1_2_3_clk_src,
418 .clkr.hw.init = &(struct clk_init_data){
419 .name = "csi1_clk_src",
420 .parent_data = mmcc_xo_gpll0_mmpll0,
421 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
422 .ops = &clk_rcg2_ops,
423 },
424 };
425
426 static struct clk_rcg2 csi2_clk_src = {
427 .cmd_rcgr = 0x3160,
428 .hid_width = 5,
429 .parent_map = mmcc_xo_gpll0_mmpll0_map,
430 .freq_tbl = ftbl_csi0_1_2_3_clk_src,
431 .clkr.hw.init = &(struct clk_init_data){
432 .name = "csi2_clk_src",
433 .parent_data = mmcc_xo_gpll0_mmpll0,
434 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
435 .ops = &clk_rcg2_ops,
436 },
437 };
438
439 static struct clk_rcg2 csi3_clk_src = {
440 .cmd_rcgr = 0x31c0,
441 .hid_width = 5,
442 .parent_map = mmcc_xo_gpll0_mmpll0_map,
443 .freq_tbl = ftbl_csi0_1_2_3_clk_src,
444 .clkr.hw.init = &(struct clk_init_data){
445 .name = "csi3_clk_src",
446 .parent_data = mmcc_xo_gpll0_mmpll0,
447 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
448 .ops = &clk_rcg2_ops,
449 },
450 };
451
452 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
453 F(80000000, P_GPLL0, 7.5, 0, 0),
454 F(100000000, P_GPLL0, 6, 0, 0),
455 F(200000000, P_GPLL0, 3, 0, 0),
456 F(320000000, P_MMPLL0, 2.5, 0, 0),
457 F(400000000, P_MMPLL0, 2, 0, 0),
458 F(480000000, P_MMPLL4, 2, 0, 0),
459 F(533330000, P_MMPLL0, 1.5, 0, 0),
460 F(600000000, P_GPLL0, 1, 0, 0),
461 { }
462 };
463
464 static const struct freq_tbl ftbl_vfe0_1_clk_src_8992[] = {
465 F(80000000, P_GPLL0, 7.5, 0, 0),
466 F(100000000, P_GPLL0, 6, 0, 0),
467 F(200000000, P_GPLL0, 3, 0, 0),
468 F(320000000, P_MMPLL0, 2.5, 0, 0),
469 F(480000000, P_MMPLL4, 2, 0, 0),
470 F(600000000, P_GPLL0, 1, 0, 0),
471 { }
472 };
473
474 static struct clk_rcg2 vfe0_clk_src = {
475 .cmd_rcgr = 0x3600,
476 .hid_width = 5,
477 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
478 .freq_tbl = ftbl_vfe0_clk_src,
479 .clkr.hw.init = &(struct clk_init_data){
480 .name = "vfe0_clk_src",
481 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
482 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
483 .ops = &clk_rcg2_ops,
484 },
485 };
486
487 static const struct freq_tbl ftbl_vfe1_clk_src[] = {
488 F(80000000, P_GPLL0, 7.5, 0, 0),
489 F(100000000, P_GPLL0, 6, 0, 0),
490 F(200000000, P_GPLL0, 3, 0, 0),
491 F(320000000, P_MMPLL0, 2.5, 0, 0),
492 F(400000000, P_MMPLL0, 2, 0, 0),
493 F(533330000, P_MMPLL0, 1.5, 0, 0),
494 { }
495 };
496
497 static struct clk_rcg2 vfe1_clk_src = {
498 .cmd_rcgr = 0x3620,
499 .hid_width = 5,
500 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
501 .freq_tbl = ftbl_vfe1_clk_src,
502 .clkr.hw.init = &(struct clk_init_data){
503 .name = "vfe1_clk_src",
504 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
505 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
506 .ops = &clk_rcg2_ops,
507 },
508 };
509
510 static const struct freq_tbl ftbl_cpp_clk_src[] = {
511 F(100000000, P_GPLL0, 6, 0, 0),
512 F(200000000, P_GPLL0, 3, 0, 0),
513 F(320000000, P_MMPLL0, 2.5, 0, 0),
514 F(480000000, P_MMPLL4, 2, 0, 0),
515 F(600000000, P_GPLL0, 1, 0, 0),
516 F(640000000, P_MMPLL4, 1.5, 0, 0),
517 { }
518 };
519
520 static const struct freq_tbl ftbl_cpp_clk_src_8992[] = {
521 F(100000000, P_GPLL0, 6, 0, 0),
522 F(200000000, P_GPLL0, 3, 0, 0),
523 F(320000000, P_MMPLL0, 2.5, 0, 0),
524 F(480000000, P_MMPLL4, 2, 0, 0),
525 F(640000000, P_MMPLL4, 1.5, 0, 0),
526 { }
527 };
528
529 static struct clk_rcg2 cpp_clk_src = {
530 .cmd_rcgr = 0x3640,
531 .hid_width = 5,
532 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
533 .freq_tbl = ftbl_cpp_clk_src,
534 .clkr.hw.init = &(struct clk_init_data){
535 .name = "cpp_clk_src",
536 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
537 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
538 .ops = &clk_rcg2_ops,
539 },
540 };
541
542 static const struct freq_tbl ftbl_jpeg0_1_clk_src[] = {
543 F(75000000, P_GPLL0, 8, 0, 0),
544 F(150000000, P_GPLL0, 4, 0, 0),
545 F(228570000, P_MMPLL0, 3.5, 0, 0),
546 F(266670000, P_MMPLL0, 3, 0, 0),
547 F(320000000, P_MMPLL0, 2.5, 0, 0),
548 F(480000000, P_MMPLL4, 2, 0, 0),
549 { }
550 };
551
552 static struct clk_rcg2 jpeg1_clk_src = {
553 .cmd_rcgr = 0x3520,
554 .hid_width = 5,
555 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
556 .freq_tbl = ftbl_jpeg0_1_clk_src,
557 .clkr.hw.init = &(struct clk_init_data){
558 .name = "jpeg1_clk_src",
559 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
560 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
561 .ops = &clk_rcg2_ops,
562 },
563 };
564
565 static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
566 F(75000000, P_GPLL0, 8, 0, 0),
567 F(133330000, P_GPLL0, 4.5, 0, 0),
568 F(150000000, P_GPLL0, 4, 0, 0),
569 F(228570000, P_MMPLL0, 3.5, 0, 0),
570 F(266670000, P_MMPLL0, 3, 0, 0),
571 F(320000000, P_MMPLL0, 2.5, 0, 0),
572 { }
573 };
574
575 static struct clk_rcg2 jpeg2_clk_src = {
576 .cmd_rcgr = 0x3540,
577 .hid_width = 5,
578 .parent_map = mmcc_xo_gpll0_mmpll0_map,
579 .freq_tbl = ftbl_jpeg2_clk_src,
580 .clkr.hw.init = &(struct clk_init_data){
581 .name = "jpeg2_clk_src",
582 .parent_data = mmcc_xo_gpll0_mmpll0,
583 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
584 .ops = &clk_rcg2_ops,
585 },
586 };
587
588 static const struct freq_tbl ftbl_csi2phytimer_clk_src[] = {
589 F(50000000, P_GPLL0, 12, 0, 0),
590 F(100000000, P_GPLL0, 6, 0, 0),
591 F(200000000, P_MMPLL0, 4, 0, 0),
592 { }
593 };
594
595 static struct clk_rcg2 csi2phytimer_clk_src = {
596 .cmd_rcgr = 0x3060,
597 .hid_width = 5,
598 .parent_map = mmcc_xo_gpll0_mmpll0_map,
599 .freq_tbl = ftbl_csi2phytimer_clk_src,
600 .clkr.hw.init = &(struct clk_init_data){
601 .name = "csi2phytimer_clk_src",
602 .parent_data = mmcc_xo_gpll0_mmpll0,
603 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
604 .ops = &clk_rcg2_ops,
605 },
606 };
607
608 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
609 F(60000000, P_GPLL0, 10, 0, 0),
610 F(200000000, P_GPLL0, 3, 0, 0),
611 F(320000000, P_MMPLL0, 2.5, 0, 0),
612 F(400000000, P_MMPLL0, 2, 0, 0),
613 { }
614 };
615
616 static struct clk_rcg2 fd_core_clk_src = {
617 .cmd_rcgr = 0x3b00,
618 .hid_width = 5,
619 .parent_map = mmcc_xo_gpll0_mmpll0_map,
620 .freq_tbl = ftbl_fd_core_clk_src,
621 .clkr.hw.init = &(struct clk_init_data){
622 .name = "fd_core_clk_src",
623 .parent_data = mmcc_xo_gpll0_mmpll0,
624 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
625 .ops = &clk_rcg2_ops,
626 },
627 };
628
629 static const struct freq_tbl ftbl_mdp_clk_src[] = {
630 F(85710000, P_GPLL0, 7, 0, 0),
631 F(100000000, P_GPLL0, 6, 0, 0),
632 F(120000000, P_GPLL0, 5, 0, 0),
633 F(150000000, P_GPLL0, 4, 0, 0),
634 F(171430000, P_GPLL0, 3.5, 0, 0),
635 F(200000000, P_GPLL0, 3, 0, 0),
636 F(240000000, P_GPLL0, 2.5, 0, 0),
637 F(266670000, P_MMPLL0, 3, 0, 0),
638 F(300000000, P_GPLL0, 2, 0, 0),
639 F(320000000, P_MMPLL0, 2.5, 0, 0),
640 F(400000000, P_MMPLL0, 2, 0, 0),
641 { }
642 };
643
644 static const struct freq_tbl ftbl_mdp_clk_src_8992[] = {
645 F(85710000, P_GPLL0, 7, 0, 0),
646 F(171430000, P_GPLL0, 3.5, 0, 0),
647 F(200000000, P_GPLL0, 3, 0, 0),
648 F(240000000, P_GPLL0, 2.5, 0, 0),
649 F(266670000, P_MMPLL0, 3, 0, 0),
650 F(320000000, P_MMPLL0, 2.5, 0, 0),
651 F(400000000, P_MMPLL0, 2, 0, 0),
652 { }
653 };
654
655 static struct clk_rcg2 mdp_clk_src = {
656 .cmd_rcgr = 0x2040,
657 .hid_width = 5,
658 .parent_map = mmcc_xo_gpll0_mmpll0_map,
659 .freq_tbl = ftbl_mdp_clk_src,
660 .clkr.hw.init = &(struct clk_init_data){
661 .name = "mdp_clk_src",
662 .parent_data = mmcc_xo_gpll0_mmpll0,
663 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
664 .ops = &clk_rcg2_ops,
665 },
666 };
667
668 static struct clk_rcg2 pclk0_clk_src = {
669 .cmd_rcgr = 0x2000,
670 .mnd_width = 8,
671 .hid_width = 5,
672 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
673 .clkr.hw.init = &(struct clk_init_data){
674 .name = "pclk0_clk_src",
675 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
676 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
677 .ops = &clk_pixel_ops,
678 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
679 },
680 };
681
682 static struct clk_rcg2 pclk1_clk_src = {
683 .cmd_rcgr = 0x2020,
684 .mnd_width = 8,
685 .hid_width = 5,
686 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
687 .clkr.hw.init = &(struct clk_init_data){
688 .name = "pclk1_clk_src",
689 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
690 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
691 .ops = &clk_pixel_ops,
692 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
693 },
694 };
695
696 static const struct freq_tbl ftbl_ocmemnoc_clk_src[] = {
697 F(19200000, P_XO, 1, 0, 0),
698 F(75000000, P_GPLL0, 8, 0, 0),
699 F(100000000, P_GPLL0, 6, 0, 0),
700 F(150000000, P_GPLL0, 4, 0, 0),
701 F(228570000, P_MMPLL0, 3.5, 0, 0),
702 F(266670000, P_MMPLL0, 3, 0, 0),
703 F(320000000, P_MMPLL0, 2.5, 0, 0),
704 F(400000000, P_MMPLL0, 2, 0, 0),
705 { }
706 };
707
708 static const struct freq_tbl ftbl_ocmemnoc_clk_src_8992[] = {
709 F(19200000, P_XO, 1, 0, 0),
710 F(75000000, P_GPLL0, 8, 0, 0),
711 F(100000000, P_GPLL0, 6, 0, 0),
712 F(150000000, P_GPLL0, 4, 0, 0),
713 F(320000000, P_MMPLL0, 2.5, 0, 0),
714 F(400000000, P_MMPLL0, 2, 0, 0),
715 { }
716 };
717
718 static struct clk_rcg2 ocmemnoc_clk_src = {
719 .cmd_rcgr = 0x5090,
720 .hid_width = 5,
721 .parent_map = mmcc_xo_gpll0_mmpll0_map,
722 .freq_tbl = ftbl_ocmemnoc_clk_src,
723 .clkr.hw.init = &(struct clk_init_data){
724 .name = "ocmemnoc_clk_src",
725 .parent_data = mmcc_xo_gpll0_mmpll0,
726 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
727 .ops = &clk_rcg2_ops,
728 },
729 };
730
731 static const struct freq_tbl ftbl_cci_clk_src[] = {
732 F(19200000, P_XO, 1, 0, 0),
733 F(37500000, P_GPLL0, 16, 0, 0),
734 F(50000000, P_GPLL0, 12, 0, 0),
735 F(100000000, P_GPLL0, 6, 0, 0),
736 { }
737 };
738
739 static struct clk_rcg2 cci_clk_src = {
740 .cmd_rcgr = 0x3300,
741 .mnd_width = 8,
742 .hid_width = 5,
743 .parent_map = mmcc_xo_gpll0_map,
744 .freq_tbl = ftbl_cci_clk_src,
745 .clkr.hw.init = &(struct clk_init_data){
746 .name = "cci_clk_src",
747 .parent_data = mmcc_xo_gpll0,
748 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
749 .ops = &clk_rcg2_ops,
750 },
751 };
752
753 static const struct freq_tbl ftbl_mmss_gp0_1_clk_src[] = {
754 F(10000, P_XO, 16, 10, 120),
755 F(24000, P_GPLL0, 16, 1, 50),
756 F(6000000, P_GPLL0, 10, 1, 10),
757 F(12000000, P_GPLL0, 10, 1, 5),
758 F(13000000, P_GPLL0, 4, 13, 150),
759 F(24000000, P_GPLL0, 5, 1, 5),
760 { }
761 };
762
763 static struct clk_rcg2 mmss_gp0_clk_src = {
764 .cmd_rcgr = 0x3420,
765 .mnd_width = 8,
766 .hid_width = 5,
767 .parent_map = mmcc_xo_gpll0_map,
768 .freq_tbl = ftbl_mmss_gp0_1_clk_src,
769 .clkr.hw.init = &(struct clk_init_data){
770 .name = "mmss_gp0_clk_src",
771 .parent_data = mmcc_xo_gpll0,
772 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
773 .ops = &clk_rcg2_ops,
774 },
775 };
776
777 static struct clk_rcg2 mmss_gp1_clk_src = {
778 .cmd_rcgr = 0x3450,
779 .mnd_width = 8,
780 .hid_width = 5,
781 .parent_map = mmcc_xo_gpll0_map,
782 .freq_tbl = ftbl_mmss_gp0_1_clk_src,
783 .clkr.hw.init = &(struct clk_init_data){
784 .name = "mmss_gp1_clk_src",
785 .parent_data = mmcc_xo_gpll0,
786 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
787 .ops = &clk_rcg2_ops,
788 },
789 };
790
791 static struct clk_rcg2 jpeg0_clk_src = {
792 .cmd_rcgr = 0x3500,
793 .hid_width = 5,
794 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
795 .freq_tbl = ftbl_jpeg0_1_clk_src,
796 .clkr.hw.init = &(struct clk_init_data){
797 .name = "jpeg0_clk_src",
798 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
799 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
800 .ops = &clk_rcg2_ops,
801 },
802 };
803
804 static struct clk_rcg2 jpeg_dma_clk_src = {
805 .cmd_rcgr = 0x3560,
806 .hid_width = 5,
807 .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
808 .freq_tbl = ftbl_jpeg0_1_clk_src,
809 .clkr.hw.init = &(struct clk_init_data){
810 .name = "jpeg_dma_clk_src",
811 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
812 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
813 .ops = &clk_rcg2_ops,
814 },
815 };
816
817 static const struct freq_tbl ftbl_mclk0_1_2_3_clk_src[] = {
818 F(4800000, P_XO, 4, 0, 0),
819 F(6000000, P_GPLL0, 10, 1, 10),
820 F(8000000, P_GPLL0, 15, 1, 5),
821 F(9600000, P_XO, 2, 0, 0),
822 F(16000000, P_MMPLL0, 10, 1, 5),
823 F(19200000, P_XO, 1, 0, 0),
824 F(24000000, P_GPLL0, 5, 1, 5),
825 F(32000000, P_MMPLL0, 5, 1, 5),
826 F(48000000, P_GPLL0, 12.5, 0, 0),
827 F(64000000, P_MMPLL0, 12.5, 0, 0),
828 { }
829 };
830
831 static const struct freq_tbl ftbl_mclk0_clk_src_8992[] = {
832 F(4800000, P_XO, 4, 0, 0),
833 F(6000000, P_MMPLL4, 10, 1, 16),
834 F(8000000, P_MMPLL4, 10, 1, 12),
835 F(9600000, P_XO, 2, 0, 0),
836 F(12000000, P_MMPLL4, 10, 1, 8),
837 F(16000000, P_MMPLL4, 10, 1, 6),
838 F(19200000, P_XO, 1, 0, 0),
839 F(24000000, P_MMPLL4, 10, 1, 4),
840 F(32000000, P_MMPLL4, 10, 1, 3),
841 F(48000000, P_MMPLL4, 10, 1, 2),
842 F(64000000, P_MMPLL4, 15, 0, 0),
843 { }
844 };
845
846 static const struct freq_tbl ftbl_mclk1_2_3_clk_src_8992[] = {
847 F(4800000, P_XO, 4, 0, 0),
848 F(6000000, P_MMPLL4, 10, 1, 16),
849 F(8000000, P_MMPLL4, 10, 1, 12),
850 F(9600000, P_XO, 2, 0, 0),
851 F(16000000, P_MMPLL4, 10, 1, 6),
852 F(19200000, P_XO, 1, 0, 0),
853 F(24000000, P_MMPLL4, 10, 1, 4),
854 F(32000000, P_MMPLL4, 10, 1, 3),
855 F(48000000, P_MMPLL4, 10, 1, 2),
856 F(64000000, P_MMPLL4, 15, 0, 0),
857 { }
858 };
859
860 static struct clk_rcg2 mclk0_clk_src = {
861 .cmd_rcgr = 0x3360,
862 .mnd_width = 8,
863 .hid_width = 5,
864 .parent_map = mmcc_xo_gpll0_mmpll0_map,
865 .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
866 .clkr.hw.init = &(struct clk_init_data){
867 .name = "mclk0_clk_src",
868 .parent_data = mmcc_xo_gpll0_mmpll0,
869 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
870 .ops = &clk_rcg2_ops,
871 },
872 };
873
874 static struct clk_rcg2 mclk1_clk_src = {
875 .cmd_rcgr = 0x3390,
876 .mnd_width = 8,
877 .hid_width = 5,
878 .parent_map = mmcc_xo_gpll0_mmpll0_map,
879 .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
880 .clkr.hw.init = &(struct clk_init_data){
881 .name = "mclk1_clk_src",
882 .parent_data = mmcc_xo_gpll0_mmpll0,
883 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
884 .ops = &clk_rcg2_ops,
885 },
886 };
887
888 static struct clk_rcg2 mclk2_clk_src = {
889 .cmd_rcgr = 0x33c0,
890 .mnd_width = 8,
891 .hid_width = 5,
892 .parent_map = mmcc_xo_gpll0_mmpll0_map,
893 .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
894 .clkr.hw.init = &(struct clk_init_data){
895 .name = "mclk2_clk_src",
896 .parent_data = mmcc_xo_gpll0_mmpll0,
897 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
898 .ops = &clk_rcg2_ops,
899 },
900 };
901
902 static struct clk_rcg2 mclk3_clk_src = {
903 .cmd_rcgr = 0x33f0,
904 .mnd_width = 8,
905 .hid_width = 5,
906 .parent_map = mmcc_xo_gpll0_mmpll0_map,
907 .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
908 .clkr.hw.init = &(struct clk_init_data){
909 .name = "mclk3_clk_src",
910 .parent_data = mmcc_xo_gpll0_mmpll0,
911 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
912 .ops = &clk_rcg2_ops,
913 },
914 };
915
916 static const struct freq_tbl ftbl_csi0_1phytimer_clk_src[] = {
917 F(50000000, P_GPLL0, 12, 0, 0),
918 F(100000000, P_GPLL0, 6, 0, 0),
919 F(200000000, P_MMPLL0, 4, 0, 0),
920 { }
921 };
922
923 static struct clk_rcg2 csi0phytimer_clk_src = {
924 .cmd_rcgr = 0x3000,
925 .hid_width = 5,
926 .parent_map = mmcc_xo_gpll0_mmpll0_map,
927 .freq_tbl = ftbl_csi0_1phytimer_clk_src,
928 .clkr.hw.init = &(struct clk_init_data){
929 .name = "csi0phytimer_clk_src",
930 .parent_data = mmcc_xo_gpll0_mmpll0,
931 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
932 .ops = &clk_rcg2_ops,
933 },
934 };
935
936 static struct clk_rcg2 csi1phytimer_clk_src = {
937 .cmd_rcgr = 0x3030,
938 .hid_width = 5,
939 .parent_map = mmcc_xo_gpll0_mmpll0_map,
940 .freq_tbl = ftbl_csi0_1phytimer_clk_src,
941 .clkr.hw.init = &(struct clk_init_data){
942 .name = "csi1phytimer_clk_src",
943 .parent_data = mmcc_xo_gpll0_mmpll0,
944 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
945 .ops = &clk_rcg2_ops,
946 },
947 };
948
949 static struct clk_rcg2 byte0_clk_src = {
950 .cmd_rcgr = 0x2120,
951 .hid_width = 5,
952 .parent_map = mmcc_xo_dsibyte_map,
953 .clkr.hw.init = &(struct clk_init_data){
954 .name = "byte0_clk_src",
955 .parent_data = mmcc_xo_dsibyte,
956 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
957 .ops = &clk_byte2_ops,
958 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
959 },
960 };
961
962 static struct clk_rcg2 byte1_clk_src = {
963 .cmd_rcgr = 0x2140,
964 .hid_width = 5,
965 .parent_map = mmcc_xo_dsibyte_map,
966 .clkr.hw.init = &(struct clk_init_data){
967 .name = "byte1_clk_src",
968 .parent_data = mmcc_xo_dsibyte,
969 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
970 .ops = &clk_byte2_ops,
971 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
972 },
973 };
974
975 static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
976 F(19200000, P_XO, 1, 0, 0),
977 { }
978 };
979
980 static struct clk_rcg2 esc0_clk_src = {
981 .cmd_rcgr = 0x2160,
982 .hid_width = 5,
983 .parent_map = mmcc_xo_dsibyte_map,
984 .freq_tbl = ftbl_mdss_esc0_1_clk,
985 .clkr.hw.init = &(struct clk_init_data){
986 .name = "esc0_clk_src",
987 .parent_data = mmcc_xo_dsibyte,
988 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
989 .ops = &clk_rcg2_ops,
990 },
991 };
992
993 static struct clk_rcg2 esc1_clk_src = {
994 .cmd_rcgr = 0x2180,
995 .hid_width = 5,
996 .parent_map = mmcc_xo_dsibyte_map,
997 .freq_tbl = ftbl_mdss_esc0_1_clk,
998 .clkr.hw.init = &(struct clk_init_data){
999 .name = "esc1_clk_src",
1000 .parent_data = mmcc_xo_dsibyte,
1001 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
1002 .ops = &clk_rcg2_ops,
1003 },
1004 };
1005
1006 static const struct freq_tbl extpclk_freq_tbl[] = {
1007 { .src = P_HDMIPLL },
1008 { }
1009 };
1010
1011 static struct clk_rcg2 extpclk_clk_src = {
1012 .cmd_rcgr = 0x2060,
1013 .hid_width = 5,
1014 .parent_map = mmss_xo_hdmi_map,
1015 .freq_tbl = extpclk_freq_tbl,
1016 .clkr.hw.init = &(struct clk_init_data){
1017 .name = "extpclk_clk_src",
1018 .parent_data = mmss_xo_hdmi,
1019 .num_parents = ARRAY_SIZE(mmss_xo_hdmi),
1020 .ops = &clk_rcg2_ops,
1021 .flags = CLK_SET_RATE_PARENT,
1022 },
1023 };
1024
1025 static const struct freq_tbl ftbl_hdmi_clk_src[] = {
1026 F(19200000, P_XO, 1, 0, 0),
1027 { }
1028 };
1029
1030 static struct clk_rcg2 hdmi_clk_src = {
1031 .cmd_rcgr = 0x2100,
1032 .hid_width = 5,
1033 .parent_map = mmcc_xo_gpll0_map,
1034 .freq_tbl = ftbl_hdmi_clk_src,
1035 .clkr.hw.init = &(struct clk_init_data){
1036 .name = "hdmi_clk_src",
1037 .parent_data = mmcc_xo_gpll0,
1038 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1039 .ops = &clk_rcg2_ops,
1040 },
1041 };
1042
1043 static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
1044 F(19200000, P_XO, 1, 0, 0),
1045 { }
1046 };
1047
1048 static struct clk_rcg2 vsync_clk_src = {
1049 .cmd_rcgr = 0x2080,
1050 .hid_width = 5,
1051 .parent_map = mmcc_xo_gpll0_map,
1052 .freq_tbl = ftbl_mdss_vsync_clk,
1053 .clkr.hw.init = &(struct clk_init_data){
1054 .name = "vsync_clk_src",
1055 .parent_data = mmcc_xo_gpll0,
1056 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1057 .ops = &clk_rcg2_ops,
1058 },
1059 };
1060
1061 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
1062 F(19200000, P_XO, 1, 0, 0),
1063 { }
1064 };
1065
1066 static struct clk_rcg2 rbbmtimer_clk_src = {
1067 .cmd_rcgr = 0x4090,
1068 .hid_width = 5,
1069 .parent_map = mmcc_xo_gpll0_map,
1070 .freq_tbl = ftbl_rbbmtimer_clk_src,
1071 .clkr.hw.init = &(struct clk_init_data){
1072 .name = "rbbmtimer_clk_src",
1073 .parent_data = mmcc_xo_gpll0,
1074 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1075 .ops = &clk_rcg2_ops,
1076 },
1077 };
1078
1079 static struct clk_branch camss_ahb_clk = {
1080 .halt_reg = 0x348c,
1081 .clkr = {
1082 .enable_reg = 0x348c,
1083 .enable_mask = BIT(0),
1084 .hw.init = &(struct clk_init_data){
1085 .name = "camss_ahb_clk",
1086 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1087 .num_parents = 1,
1088 .flags = CLK_SET_RATE_PARENT,
1089 .ops = &clk_branch2_ops,
1090 },
1091 },
1092 };
1093
1094 static struct clk_branch camss_cci_cci_ahb_clk = {
1095 .halt_reg = 0x3348,
1096 .clkr = {
1097 .enable_reg = 0x3348,
1098 .enable_mask = BIT(0),
1099 .hw.init = &(struct clk_init_data){
1100 .name = "camss_cci_cci_ahb_clk",
1101 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1102 .num_parents = 1,
1103 .flags = CLK_SET_RATE_PARENT,
1104 .ops = &clk_branch2_ops,
1105 },
1106 },
1107 };
1108
1109 static struct clk_branch camss_cci_cci_clk = {
1110 .halt_reg = 0x3344,
1111 .clkr = {
1112 .enable_reg = 0x3344,
1113 .enable_mask = BIT(0),
1114 .hw.init = &(struct clk_init_data){
1115 .name = "camss_cci_cci_clk",
1116 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1117 .num_parents = 1,
1118 .ops = &clk_branch2_ops,
1119 },
1120 },
1121 };
1122
1123 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1124 .halt_reg = 0x36b4,
1125 .clkr = {
1126 .enable_reg = 0x36b4,
1127 .enable_mask = BIT(0),
1128 .hw.init = &(struct clk_init_data){
1129 .name = "camss_vfe_cpp_ahb_clk",
1130 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1131 .num_parents = 1,
1132 .flags = CLK_SET_RATE_PARENT,
1133 .ops = &clk_branch2_ops,
1134 },
1135 },
1136 };
1137
1138 static struct clk_branch camss_vfe_cpp_axi_clk = {
1139 .halt_reg = 0x36c4,
1140 .clkr = {
1141 .enable_reg = 0x36c4,
1142 .enable_mask = BIT(0),
1143 .hw.init = &(struct clk_init_data){
1144 .name = "camss_vfe_cpp_axi_clk",
1145 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1146 .num_parents = 1,
1147 .ops = &clk_branch2_ops,
1148 },
1149 },
1150 };
1151
1152 static struct clk_branch camss_vfe_cpp_clk = {
1153 .halt_reg = 0x36b0,
1154 .clkr = {
1155 .enable_reg = 0x36b0,
1156 .enable_mask = BIT(0),
1157 .hw.init = &(struct clk_init_data){
1158 .name = "camss_vfe_cpp_clk",
1159 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
1160 .num_parents = 1,
1161 .ops = &clk_branch2_ops,
1162 },
1163 },
1164 };
1165
1166 static struct clk_branch camss_csi0_ahb_clk = {
1167 .halt_reg = 0x30bc,
1168 .clkr = {
1169 .enable_reg = 0x30bc,
1170 .enable_mask = BIT(0),
1171 .hw.init = &(struct clk_init_data){
1172 .name = "camss_csi0_ahb_clk",
1173 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1174 .num_parents = 1,
1175 .flags = CLK_SET_RATE_PARENT,
1176 .ops = &clk_branch2_ops,
1177 },
1178 },
1179 };
1180
1181 static struct clk_branch camss_csi0_clk = {
1182 .halt_reg = 0x30b4,
1183 .clkr = {
1184 .enable_reg = 0x30b4,
1185 .enable_mask = BIT(0),
1186 .hw.init = &(struct clk_init_data){
1187 .name = "camss_csi0_clk",
1188 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1189 .num_parents = 1,
1190 .ops = &clk_branch2_ops,
1191 },
1192 },
1193 };
1194
1195 static struct clk_branch camss_csi0phy_clk = {
1196 .halt_reg = 0x30c4,
1197 .clkr = {
1198 .enable_reg = 0x30c4,
1199 .enable_mask = BIT(0),
1200 .hw.init = &(struct clk_init_data){
1201 .name = "camss_csi0phy_clk",
1202 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1203 .num_parents = 1,
1204 .ops = &clk_branch2_ops,
1205 },
1206 },
1207 };
1208
1209 static struct clk_branch camss_csi0pix_clk = {
1210 .halt_reg = 0x30e4,
1211 .clkr = {
1212 .enable_reg = 0x30e4,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data){
1215 .name = "camss_csi0pix_clk",
1216 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1217 .num_parents = 1,
1218 .ops = &clk_branch2_ops,
1219 },
1220 },
1221 };
1222
1223 static struct clk_branch camss_csi0rdi_clk = {
1224 .halt_reg = 0x30d4,
1225 .clkr = {
1226 .enable_reg = 0x30d4,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "camss_csi0rdi_clk",
1230 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1231 .num_parents = 1,
1232 .ops = &clk_branch2_ops,
1233 },
1234 },
1235 };
1236
1237 static struct clk_branch camss_csi1_ahb_clk = {
1238 .halt_reg = 0x3128,
1239 .clkr = {
1240 .enable_reg = 0x3128,
1241 .enable_mask = BIT(0),
1242 .hw.init = &(struct clk_init_data){
1243 .name = "camss_csi1_ahb_clk",
1244 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1245 .num_parents = 1,
1246 .flags = CLK_SET_RATE_PARENT,
1247 .ops = &clk_branch2_ops,
1248 },
1249 },
1250 };
1251
1252 static struct clk_branch camss_csi1_clk = {
1253 .halt_reg = 0x3124,
1254 .clkr = {
1255 .enable_reg = 0x3124,
1256 .enable_mask = BIT(0),
1257 .hw.init = &(struct clk_init_data){
1258 .name = "camss_csi1_clk",
1259 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1260 .num_parents = 1,
1261 .ops = &clk_branch2_ops,
1262 },
1263 },
1264 };
1265
1266 static struct clk_branch camss_csi1phy_clk = {
1267 .halt_reg = 0x3134,
1268 .clkr = {
1269 .enable_reg = 0x3134,
1270 .enable_mask = BIT(0),
1271 .hw.init = &(struct clk_init_data){
1272 .name = "camss_csi1phy_clk",
1273 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1274 .num_parents = 1,
1275 .ops = &clk_branch2_ops,
1276 },
1277 },
1278 };
1279
1280 static struct clk_branch camss_csi1pix_clk = {
1281 .halt_reg = 0x3154,
1282 .clkr = {
1283 .enable_reg = 0x3154,
1284 .enable_mask = BIT(0),
1285 .hw.init = &(struct clk_init_data){
1286 .name = "camss_csi1pix_clk",
1287 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1288 .num_parents = 1,
1289 .ops = &clk_branch2_ops,
1290 },
1291 },
1292 };
1293
1294 static struct clk_branch camss_csi1rdi_clk = {
1295 .halt_reg = 0x3144,
1296 .clkr = {
1297 .enable_reg = 0x3144,
1298 .enable_mask = BIT(0),
1299 .hw.init = &(struct clk_init_data){
1300 .name = "camss_csi1rdi_clk",
1301 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1302 .num_parents = 1,
1303 .ops = &clk_branch2_ops,
1304 },
1305 },
1306 };
1307
1308 static struct clk_branch camss_csi2_ahb_clk = {
1309 .halt_reg = 0x3188,
1310 .clkr = {
1311 .enable_reg = 0x3188,
1312 .enable_mask = BIT(0),
1313 .hw.init = &(struct clk_init_data){
1314 .name = "camss_csi2_ahb_clk",
1315 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1316 .num_parents = 1,
1317 .flags = CLK_SET_RATE_PARENT,
1318 .ops = &clk_branch2_ops,
1319 },
1320 },
1321 };
1322
1323 static struct clk_branch camss_csi2_clk = {
1324 .halt_reg = 0x3184,
1325 .clkr = {
1326 .enable_reg = 0x3184,
1327 .enable_mask = BIT(0),
1328 .hw.init = &(struct clk_init_data){
1329 .name = "camss_csi2_clk",
1330 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1331 .num_parents = 1,
1332 .ops = &clk_branch2_ops,
1333 },
1334 },
1335 };
1336
1337 static struct clk_branch camss_csi2phy_clk = {
1338 .halt_reg = 0x3194,
1339 .clkr = {
1340 .enable_reg = 0x3194,
1341 .enable_mask = BIT(0),
1342 .hw.init = &(struct clk_init_data){
1343 .name = "camss_csi2phy_clk",
1344 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1345 .num_parents = 1,
1346 .ops = &clk_branch2_ops,
1347 },
1348 },
1349 };
1350
1351 static struct clk_branch camss_csi2pix_clk = {
1352 .halt_reg = 0x31b4,
1353 .clkr = {
1354 .enable_reg = 0x31b4,
1355 .enable_mask = BIT(0),
1356 .hw.init = &(struct clk_init_data){
1357 .name = "camss_csi2pix_clk",
1358 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1359 .num_parents = 1,
1360 .ops = &clk_branch2_ops,
1361 },
1362 },
1363 };
1364
1365 static struct clk_branch camss_csi2rdi_clk = {
1366 .halt_reg = 0x31a4,
1367 .clkr = {
1368 .enable_reg = 0x31a4,
1369 .enable_mask = BIT(0),
1370 .hw.init = &(struct clk_init_data){
1371 .name = "camss_csi2rdi_clk",
1372 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1373 .num_parents = 1,
1374 .ops = &clk_branch2_ops,
1375 },
1376 },
1377 };
1378
1379 static struct clk_branch camss_csi3_ahb_clk = {
1380 .halt_reg = 0x31e8,
1381 .clkr = {
1382 .enable_reg = 0x31e8,
1383 .enable_mask = BIT(0),
1384 .hw.init = &(struct clk_init_data){
1385 .name = "camss_csi3_ahb_clk",
1386 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1387 .num_parents = 1,
1388 .flags = CLK_SET_RATE_PARENT,
1389 .ops = &clk_branch2_ops,
1390 },
1391 },
1392 };
1393
1394 static struct clk_branch camss_csi3_clk = {
1395 .halt_reg = 0x31e4,
1396 .clkr = {
1397 .enable_reg = 0x31e4,
1398 .enable_mask = BIT(0),
1399 .hw.init = &(struct clk_init_data){
1400 .name = "camss_csi3_clk",
1401 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1402 .num_parents = 1,
1403 .ops = &clk_branch2_ops,
1404 },
1405 },
1406 };
1407
1408 static struct clk_branch camss_csi3phy_clk = {
1409 .halt_reg = 0x31f4,
1410 .clkr = {
1411 .enable_reg = 0x31f4,
1412 .enable_mask = BIT(0),
1413 .hw.init = &(struct clk_init_data){
1414 .name = "camss_csi3phy_clk",
1415 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1416 .num_parents = 1,
1417 .ops = &clk_branch2_ops,
1418 },
1419 },
1420 };
1421
1422 static struct clk_branch camss_csi3pix_clk = {
1423 .halt_reg = 0x3214,
1424 .clkr = {
1425 .enable_reg = 0x3214,
1426 .enable_mask = BIT(0),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "camss_csi3pix_clk",
1429 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1430 .num_parents = 1,
1431 .ops = &clk_branch2_ops,
1432 },
1433 },
1434 };
1435
1436 static struct clk_branch camss_csi3rdi_clk = {
1437 .halt_reg = 0x3204,
1438 .clkr = {
1439 .enable_reg = 0x3204,
1440 .enable_mask = BIT(0),
1441 .hw.init = &(struct clk_init_data){
1442 .name = "camss_csi3rdi_clk",
1443 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1444 .num_parents = 1,
1445 .ops = &clk_branch2_ops,
1446 },
1447 },
1448 };
1449
1450 static struct clk_branch camss_csi_vfe0_clk = {
1451 .halt_reg = 0x3704,
1452 .clkr = {
1453 .enable_reg = 0x3704,
1454 .enable_mask = BIT(0),
1455 .hw.init = &(struct clk_init_data){
1456 .name = "camss_csi_vfe0_clk",
1457 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1458 .num_parents = 1,
1459 .ops = &clk_branch2_ops,
1460 },
1461 },
1462 };
1463
1464 static struct clk_branch camss_csi_vfe1_clk = {
1465 .halt_reg = 0x3714,
1466 .clkr = {
1467 .enable_reg = 0x3714,
1468 .enable_mask = BIT(0),
1469 .hw.init = &(struct clk_init_data){
1470 .name = "camss_csi_vfe1_clk",
1471 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1472 .num_parents = 1,
1473 .ops = &clk_branch2_ops,
1474 },
1475 },
1476 };
1477
1478 static struct clk_branch camss_gp0_clk = {
1479 .halt_reg = 0x3444,
1480 .clkr = {
1481 .enable_reg = 0x3444,
1482 .enable_mask = BIT(0),
1483 .hw.init = &(struct clk_init_data){
1484 .name = "camss_gp0_clk",
1485 .parent_hws = (const struct clk_hw *[]){ &mmss_gp0_clk_src.clkr.hw },
1486 .num_parents = 1,
1487 .ops = &clk_branch2_ops,
1488 },
1489 },
1490 };
1491
1492 static struct clk_branch camss_gp1_clk = {
1493 .halt_reg = 0x3474,
1494 .clkr = {
1495 .enable_reg = 0x3474,
1496 .enable_mask = BIT(0),
1497 .hw.init = &(struct clk_init_data){
1498 .name = "camss_gp1_clk",
1499 .parent_hws = (const struct clk_hw *[]){ &mmss_gp1_clk_src.clkr.hw },
1500 .num_parents = 1,
1501 .ops = &clk_branch2_ops,
1502 },
1503 },
1504 };
1505
1506 static struct clk_branch camss_ispif_ahb_clk = {
1507 .halt_reg = 0x3224,
1508 .clkr = {
1509 .enable_reg = 0x3224,
1510 .enable_mask = BIT(0),
1511 .hw.init = &(struct clk_init_data){
1512 .name = "camss_ispif_ahb_clk",
1513 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1514 .num_parents = 1,
1515 .flags = CLK_SET_RATE_PARENT,
1516 .ops = &clk_branch2_ops,
1517 },
1518 },
1519 };
1520
1521 static struct clk_branch camss_jpeg_dma_clk = {
1522 .halt_reg = 0x35c0,
1523 .clkr = {
1524 .enable_reg = 0x35c0,
1525 .enable_mask = BIT(0),
1526 .hw.init = &(struct clk_init_data){
1527 .name = "camss_jpeg_dma_clk",
1528 .parent_hws = (const struct clk_hw *[]){ &jpeg_dma_clk_src.clkr.hw },
1529 .num_parents = 1,
1530 .ops = &clk_branch2_ops,
1531 },
1532 },
1533 };
1534
1535 static struct clk_branch camss_jpeg_jpeg0_clk = {
1536 .halt_reg = 0x35a8,
1537 .clkr = {
1538 .enable_reg = 0x35a8,
1539 .enable_mask = BIT(0),
1540 .hw.init = &(struct clk_init_data){
1541 .name = "camss_jpeg_jpeg0_clk",
1542 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
1543 .num_parents = 1,
1544 .ops = &clk_branch2_ops,
1545 },
1546 },
1547 };
1548
1549 static struct clk_branch camss_jpeg_jpeg1_clk = {
1550 .halt_reg = 0x35ac,
1551 .clkr = {
1552 .enable_reg = 0x35ac,
1553 .enable_mask = BIT(0),
1554 .hw.init = &(struct clk_init_data){
1555 .name = "camss_jpeg_jpeg1_clk",
1556 .parent_hws = (const struct clk_hw *[]){ &jpeg1_clk_src.clkr.hw },
1557 .num_parents = 1,
1558 .ops = &clk_branch2_ops,
1559 },
1560 },
1561 };
1562
1563 static struct clk_branch camss_jpeg_jpeg2_clk = {
1564 .halt_reg = 0x35b0,
1565 .clkr = {
1566 .enable_reg = 0x35b0,
1567 .enable_mask = BIT(0),
1568 .hw.init = &(struct clk_init_data){
1569 .name = "camss_jpeg_jpeg2_clk",
1570 .parent_hws = (const struct clk_hw *[]){ &jpeg2_clk_src.clkr.hw },
1571 .num_parents = 1,
1572 .ops = &clk_branch2_ops,
1573 },
1574 },
1575 };
1576
1577 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1578 .halt_reg = 0x35b4,
1579 .clkr = {
1580 .enable_reg = 0x35b4,
1581 .enable_mask = BIT(0),
1582 .hw.init = &(struct clk_init_data){
1583 .name = "camss_jpeg_jpeg_ahb_clk",
1584 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1585 .num_parents = 1,
1586 .flags = CLK_SET_RATE_PARENT,
1587 .ops = &clk_branch2_ops,
1588 },
1589 },
1590 };
1591
1592 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1593 .halt_reg = 0x35b8,
1594 .clkr = {
1595 .enable_reg = 0x35b8,
1596 .enable_mask = BIT(0),
1597 .hw.init = &(struct clk_init_data){
1598 .name = "camss_jpeg_jpeg_axi_clk",
1599 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1600 .num_parents = 1,
1601 .ops = &clk_branch2_ops,
1602 },
1603 },
1604 };
1605
1606 static struct clk_branch camss_mclk0_clk = {
1607 .halt_reg = 0x3384,
1608 .clkr = {
1609 .enable_reg = 0x3384,
1610 .enable_mask = BIT(0),
1611 .hw.init = &(struct clk_init_data){
1612 .name = "camss_mclk0_clk",
1613 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1614 .num_parents = 1,
1615 .ops = &clk_branch2_ops,
1616 },
1617 },
1618 };
1619
1620 static struct clk_branch camss_mclk1_clk = {
1621 .halt_reg = 0x33b4,
1622 .clkr = {
1623 .enable_reg = 0x33b4,
1624 .enable_mask = BIT(0),
1625 .hw.init = &(struct clk_init_data){
1626 .name = "camss_mclk1_clk",
1627 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1628 .num_parents = 1,
1629 .ops = &clk_branch2_ops,
1630 },
1631 },
1632 };
1633
1634 static struct clk_branch camss_mclk2_clk = {
1635 .halt_reg = 0x33e4,
1636 .clkr = {
1637 .enable_reg = 0x33e4,
1638 .enable_mask = BIT(0),
1639 .hw.init = &(struct clk_init_data){
1640 .name = "camss_mclk2_clk",
1641 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1642 .num_parents = 1,
1643 .ops = &clk_branch2_ops,
1644 },
1645 },
1646 };
1647
1648 static struct clk_branch camss_mclk3_clk = {
1649 .halt_reg = 0x3414,
1650 .clkr = {
1651 .enable_reg = 0x3414,
1652 .enable_mask = BIT(0),
1653 .hw.init = &(struct clk_init_data){
1654 .name = "camss_mclk3_clk",
1655 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
1656 .num_parents = 1,
1657 .ops = &clk_branch2_ops,
1658 },
1659 },
1660 };
1661
1662 static struct clk_branch camss_micro_ahb_clk = {
1663 .halt_reg = 0x3494,
1664 .clkr = {
1665 .enable_reg = 0x3494,
1666 .enable_mask = BIT(0),
1667 .hw.init = &(struct clk_init_data){
1668 .name = "camss_micro_ahb_clk",
1669 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1670 .num_parents = 1,
1671 .flags = CLK_SET_RATE_PARENT,
1672 .ops = &clk_branch2_ops,
1673 },
1674 },
1675 };
1676
1677 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1678 .halt_reg = 0x3024,
1679 .clkr = {
1680 .enable_reg = 0x3024,
1681 .enable_mask = BIT(0),
1682 .hw.init = &(struct clk_init_data){
1683 .name = "camss_phy0_csi0phytimer_clk",
1684 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1685 .num_parents = 1,
1686 .ops = &clk_branch2_ops,
1687 },
1688 },
1689 };
1690
1691 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1692 .halt_reg = 0x3054,
1693 .clkr = {
1694 .enable_reg = 0x3054,
1695 .enable_mask = BIT(0),
1696 .hw.init = &(struct clk_init_data){
1697 .name = "camss_phy1_csi1phytimer_clk",
1698 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1699 .num_parents = 1,
1700 .ops = &clk_branch2_ops,
1701 },
1702 },
1703 };
1704
1705 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1706 .halt_reg = 0x3084,
1707 .clkr = {
1708 .enable_reg = 0x3084,
1709 .enable_mask = BIT(0),
1710 .hw.init = &(struct clk_init_data){
1711 .name = "camss_phy2_csi2phytimer_clk",
1712 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1713 .num_parents = 1,
1714 .ops = &clk_branch2_ops,
1715 },
1716 },
1717 };
1718
1719 static struct clk_branch camss_top_ahb_clk = {
1720 .halt_reg = 0x3484,
1721 .clkr = {
1722 .enable_reg = 0x3484,
1723 .enable_mask = BIT(0),
1724 .hw.init = &(struct clk_init_data){
1725 .name = "camss_top_ahb_clk",
1726 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1727 .num_parents = 1,
1728 .flags = CLK_SET_RATE_PARENT,
1729 .ops = &clk_branch2_ops,
1730 },
1731 },
1732 };
1733
1734 static struct clk_branch camss_vfe_vfe0_clk = {
1735 .halt_reg = 0x36a8,
1736 .clkr = {
1737 .enable_reg = 0x36a8,
1738 .enable_mask = BIT(0),
1739 .hw.init = &(struct clk_init_data){
1740 .name = "camss_vfe_vfe0_clk",
1741 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1742 .num_parents = 1,
1743 .ops = &clk_branch2_ops,
1744 },
1745 },
1746 };
1747
1748 static struct clk_branch camss_vfe_vfe1_clk = {
1749 .halt_reg = 0x36ac,
1750 .clkr = {
1751 .enable_reg = 0x36ac,
1752 .enable_mask = BIT(0),
1753 .hw.init = &(struct clk_init_data){
1754 .name = "camss_vfe_vfe1_clk",
1755 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1756 .num_parents = 1,
1757 .ops = &clk_branch2_ops,
1758 },
1759 },
1760 };
1761
1762 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1763 .halt_reg = 0x36b8,
1764 .clkr = {
1765 .enable_reg = 0x36b8,
1766 .enable_mask = BIT(0),
1767 .hw.init = &(struct clk_init_data){
1768 .name = "camss_vfe_vfe_ahb_clk",
1769 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1770 .num_parents = 1,
1771 .flags = CLK_SET_RATE_PARENT,
1772 .ops = &clk_branch2_ops,
1773 },
1774 },
1775 };
1776
1777 static struct clk_branch camss_vfe_vfe_axi_clk = {
1778 .halt_reg = 0x36bc,
1779 .clkr = {
1780 .enable_reg = 0x36bc,
1781 .enable_mask = BIT(0),
1782 .hw.init = &(struct clk_init_data){
1783 .name = "camss_vfe_vfe_axi_clk",
1784 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1785 .num_parents = 1,
1786 .ops = &clk_branch2_ops,
1787 },
1788 },
1789 };
1790
1791 static struct clk_branch fd_ahb_clk = {
1792 .halt_reg = 0x3b74,
1793 .clkr = {
1794 .enable_reg = 0x3b74,
1795 .enable_mask = BIT(0),
1796 .hw.init = &(struct clk_init_data){
1797 .name = "fd_ahb_clk",
1798 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1799 .num_parents = 1,
1800 .ops = &clk_branch2_ops,
1801 },
1802 },
1803 };
1804
1805 static struct clk_branch fd_axi_clk = {
1806 .halt_reg = 0x3b70,
1807 .clkr = {
1808 .enable_reg = 0x3b70,
1809 .enable_mask = BIT(0),
1810 .hw.init = &(struct clk_init_data){
1811 .name = "fd_axi_clk",
1812 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1813 .num_parents = 1,
1814 .ops = &clk_branch2_ops,
1815 },
1816 },
1817 };
1818
1819 static struct clk_branch fd_core_clk = {
1820 .halt_reg = 0x3b68,
1821 .clkr = {
1822 .enable_reg = 0x3b68,
1823 .enable_mask = BIT(0),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "fd_core_clk",
1826 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
1827 .num_parents = 1,
1828 .ops = &clk_branch2_ops,
1829 },
1830 },
1831 };
1832
1833 static struct clk_branch fd_core_uar_clk = {
1834 .halt_reg = 0x3b6c,
1835 .clkr = {
1836 .enable_reg = 0x3b6c,
1837 .enable_mask = BIT(0),
1838 .hw.init = &(struct clk_init_data){
1839 .name = "fd_core_uar_clk",
1840 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
1841 .num_parents = 1,
1842 .ops = &clk_branch2_ops,
1843 },
1844 },
1845 };
1846
1847 static struct clk_branch mdss_ahb_clk = {
1848 .halt_reg = 0x2308,
1849 .halt_check = BRANCH_HALT,
1850 .clkr = {
1851 .enable_reg = 0x2308,
1852 .enable_mask = BIT(0),
1853 .hw.init = &(struct clk_init_data){
1854 .name = "mdss_ahb_clk",
1855 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1856 .num_parents = 1,
1857 .flags = CLK_SET_RATE_PARENT,
1858 .ops = &clk_branch2_ops,
1859 },
1860 },
1861 };
1862
1863 static struct clk_branch mdss_axi_clk = {
1864 .halt_reg = 0x2310,
1865 .clkr = {
1866 .enable_reg = 0x2310,
1867 .enable_mask = BIT(0),
1868 .hw.init = &(struct clk_init_data){
1869 .name = "mdss_axi_clk",
1870 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1871 .num_parents = 1,
1872 .flags = CLK_SET_RATE_PARENT,
1873 .ops = &clk_branch2_ops,
1874 },
1875 },
1876 };
1877
1878 static struct clk_branch mdss_byte0_clk = {
1879 .halt_reg = 0x233c,
1880 .clkr = {
1881 .enable_reg = 0x233c,
1882 .enable_mask = BIT(0),
1883 .hw.init = &(struct clk_init_data){
1884 .name = "mdss_byte0_clk",
1885 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1886 .num_parents = 1,
1887 .flags = CLK_SET_RATE_PARENT,
1888 .ops = &clk_branch2_ops,
1889 },
1890 },
1891 };
1892
1893 static struct clk_branch mdss_byte1_clk = {
1894 .halt_reg = 0x2340,
1895 .clkr = {
1896 .enable_reg = 0x2340,
1897 .enable_mask = BIT(0),
1898 .hw.init = &(struct clk_init_data){
1899 .name = "mdss_byte1_clk",
1900 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1901 .num_parents = 1,
1902 .flags = CLK_SET_RATE_PARENT,
1903 .ops = &clk_branch2_ops,
1904 },
1905 },
1906 };
1907
1908 static struct clk_branch mdss_esc0_clk = {
1909 .halt_reg = 0x2344,
1910 .clkr = {
1911 .enable_reg = 0x2344,
1912 .enable_mask = BIT(0),
1913 .hw.init = &(struct clk_init_data){
1914 .name = "mdss_esc0_clk",
1915 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1916 .num_parents = 1,
1917 .flags = CLK_SET_RATE_PARENT,
1918 .ops = &clk_branch2_ops,
1919 },
1920 },
1921 };
1922
1923 static struct clk_branch mdss_esc1_clk = {
1924 .halt_reg = 0x2348,
1925 .clkr = {
1926 .enable_reg = 0x2348,
1927 .enable_mask = BIT(0),
1928 .hw.init = &(struct clk_init_data){
1929 .name = "mdss_esc1_clk",
1930 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1931 .num_parents = 1,
1932 .flags = CLK_SET_RATE_PARENT,
1933 .ops = &clk_branch2_ops,
1934 },
1935 },
1936 };
1937
1938 static struct clk_branch mdss_extpclk_clk = {
1939 .halt_reg = 0x2324,
1940 .clkr = {
1941 .enable_reg = 0x2324,
1942 .enable_mask = BIT(0),
1943 .hw.init = &(struct clk_init_data){
1944 .name = "mdss_extpclk_clk",
1945 .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1946 .num_parents = 1,
1947 .flags = CLK_SET_RATE_PARENT,
1948 .ops = &clk_branch2_ops,
1949 },
1950 },
1951 };
1952
1953 static struct clk_branch mdss_hdmi_ahb_clk = {
1954 .halt_reg = 0x230c,
1955 .clkr = {
1956 .enable_reg = 0x230c,
1957 .enable_mask = BIT(0),
1958 .hw.init = &(struct clk_init_data){
1959 .name = "mdss_hdmi_ahb_clk",
1960 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1961 .num_parents = 1,
1962 .flags = CLK_SET_RATE_PARENT,
1963 .ops = &clk_branch2_ops,
1964 },
1965 },
1966 };
1967
1968 static struct clk_branch mdss_hdmi_clk = {
1969 .halt_reg = 0x2338,
1970 .clkr = {
1971 .enable_reg = 0x2338,
1972 .enable_mask = BIT(0),
1973 .hw.init = &(struct clk_init_data){
1974 .name = "mdss_hdmi_clk",
1975 .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1976 .num_parents = 1,
1977 .flags = CLK_SET_RATE_PARENT,
1978 .ops = &clk_branch2_ops,
1979 },
1980 },
1981 };
1982
1983 static struct clk_branch mdss_mdp_clk = {
1984 .halt_reg = 0x231c,
1985 .clkr = {
1986 .enable_reg = 0x231c,
1987 .enable_mask = BIT(0),
1988 .hw.init = &(struct clk_init_data){
1989 .name = "mdss_mdp_clk",
1990 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1991 .num_parents = 1,
1992 .flags = CLK_SET_RATE_PARENT,
1993 .ops = &clk_branch2_ops,
1994 },
1995 },
1996 };
1997
1998 static struct clk_branch mdss_pclk0_clk = {
1999 .halt_reg = 0x2314,
2000 .clkr = {
2001 .enable_reg = 0x2314,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "mdss_pclk0_clk",
2005 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
2006 .num_parents = 1,
2007 .flags = CLK_SET_RATE_PARENT,
2008 .ops = &clk_branch2_ops,
2009 },
2010 },
2011 };
2012
2013 static struct clk_branch mdss_pclk1_clk = {
2014 .halt_reg = 0x2318,
2015 .clkr = {
2016 .enable_reg = 0x2318,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "mdss_pclk1_clk",
2020 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
2021 .num_parents = 1,
2022 .flags = CLK_SET_RATE_PARENT,
2023 .ops = &clk_branch2_ops,
2024 },
2025 },
2026 };
2027
2028 static struct clk_branch mdss_vsync_clk = {
2029 .halt_reg = 0x2328,
2030 .clkr = {
2031 .enable_reg = 0x2328,
2032 .enable_mask = BIT(0),
2033 .hw.init = &(struct clk_init_data){
2034 .name = "mdss_vsync_clk",
2035 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
2036 .num_parents = 1,
2037 .flags = CLK_SET_RATE_PARENT,
2038 .ops = &clk_branch2_ops,
2039 },
2040 },
2041 };
2042
2043 static struct clk_branch mmss_misc_ahb_clk = {
2044 .halt_reg = 0x502c,
2045 .clkr = {
2046 .enable_reg = 0x502c,
2047 .enable_mask = BIT(0),
2048 .hw.init = &(struct clk_init_data){
2049 .name = "mmss_misc_ahb_clk",
2050 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2051 .num_parents = 1,
2052 .flags = CLK_SET_RATE_PARENT,
2053 .ops = &clk_branch2_ops,
2054 },
2055 },
2056 };
2057
2058 static struct clk_branch mmss_mmssnoc_axi_clk = {
2059 .halt_reg = 0x506c,
2060 .clkr = {
2061 .enable_reg = 0x506c,
2062 .enable_mask = BIT(0),
2063 .hw.init = &(struct clk_init_data){
2064 .name = "mmss_mmssnoc_axi_clk",
2065 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2066 .num_parents = 1,
2067 /* Gating this clock will wreck havoc among MMSS! */
2068 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2069 .ops = &clk_branch2_ops,
2070 },
2071 },
2072 };
2073
2074 static struct clk_branch mmss_s0_axi_clk = {
2075 .halt_reg = 0x5064,
2076 .clkr = {
2077 .enable_reg = 0x5064,
2078 .enable_mask = BIT(0),
2079 .hw.init = &(struct clk_init_data){
2080 .name = "mmss_s0_axi_clk",
2081 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw, },
2082 .num_parents = 1,
2083 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2084 .ops = &clk_branch2_ops,
2085 },
2086 },
2087 };
2088
2089 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2090 .halt_reg = 0x4058,
2091 .clkr = {
2092 .enable_reg = 0x4058,
2093 .enable_mask = BIT(0),
2094 .hw.init = &(struct clk_init_data){
2095 .name = "ocmemcx_ocmemnoc_clk",
2096 .parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
2097 .num_parents = 1,
2098 .flags = CLK_SET_RATE_PARENT,
2099 .ops = &clk_branch2_ops,
2100 },
2101 },
2102 };
2103
2104 static struct clk_branch oxili_gfx3d_clk = {
2105 .halt_reg = 0x4028,
2106 .clkr = {
2107 .enable_reg = 0x4028,
2108 .enable_mask = BIT(0),
2109 .hw.init = &(struct clk_init_data){
2110 .name = "oxili_gfx3d_clk",
2111 .parent_data = &(const struct clk_parent_data){
2112 .fw_name = "oxili_gfx3d_clk_src",
2113 .name = "oxili_gfx3d_clk_src"
2114 },
2115 .num_parents = 1,
2116 .flags = CLK_SET_RATE_PARENT,
2117 .ops = &clk_branch2_ops,
2118 },
2119 },
2120 };
2121
2122 static struct clk_branch oxili_rbbmtimer_clk = {
2123 .halt_reg = 0x40b0,
2124 .clkr = {
2125 .enable_reg = 0x40b0,
2126 .enable_mask = BIT(0),
2127 .hw.init = &(struct clk_init_data){
2128 .name = "oxili_rbbmtimer_clk",
2129 .parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw },
2130 .num_parents = 1,
2131 .flags = CLK_SET_RATE_PARENT,
2132 .ops = &clk_branch2_ops,
2133 },
2134 },
2135 };
2136
2137 static struct clk_branch oxilicx_ahb_clk = {
2138 .halt_reg = 0x403c,
2139 .clkr = {
2140 .enable_reg = 0x403c,
2141 .enable_mask = BIT(0),
2142 .hw.init = &(struct clk_init_data){
2143 .name = "oxilicx_ahb_clk",
2144 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2145 .num_parents = 1,
2146 .flags = CLK_SET_RATE_PARENT,
2147 .ops = &clk_branch2_ops,
2148 },
2149 },
2150 };
2151
2152 static struct clk_branch venus0_ahb_clk = {
2153 .halt_reg = 0x1030,
2154 .clkr = {
2155 .enable_reg = 0x1030,
2156 .enable_mask = BIT(0),
2157 .hw.init = &(struct clk_init_data){
2158 .name = "venus0_ahb_clk",
2159 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2160 .num_parents = 1,
2161 .flags = CLK_SET_RATE_PARENT,
2162 .ops = &clk_branch2_ops,
2163 },
2164 },
2165 };
2166
2167 static struct clk_branch venus0_axi_clk = {
2168 .halt_reg = 0x1034,
2169 .clkr = {
2170 .enable_reg = 0x1034,
2171 .enable_mask = BIT(0),
2172 .hw.init = &(struct clk_init_data){
2173 .name = "venus0_axi_clk",
2174 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2175 .num_parents = 1,
2176 .ops = &clk_branch2_ops,
2177 },
2178 },
2179 };
2180
2181 static struct clk_branch venus0_ocmemnoc_clk = {
2182 .halt_reg = 0x1038,
2183 .clkr = {
2184 .enable_reg = 0x1038,
2185 .enable_mask = BIT(0),
2186 .hw.init = &(struct clk_init_data){
2187 .name = "venus0_ocmemnoc_clk",
2188 .parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
2189 .num_parents = 1,
2190 .flags = CLK_SET_RATE_PARENT,
2191 .ops = &clk_branch2_ops,
2192 },
2193 },
2194 };
2195
2196 static struct clk_branch venus0_vcodec0_clk = {
2197 .halt_reg = 0x1028,
2198 .clkr = {
2199 .enable_reg = 0x1028,
2200 .enable_mask = BIT(0),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "venus0_vcodec0_clk",
2203 .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2204 .num_parents = 1,
2205 .flags = CLK_SET_RATE_PARENT,
2206 .ops = &clk_branch2_ops,
2207 },
2208 },
2209 };
2210
2211 static struct clk_branch venus0_core0_vcodec_clk = {
2212 .halt_reg = 0x1048,
2213 .clkr = {
2214 .enable_reg = 0x1048,
2215 .enable_mask = BIT(0),
2216 .hw.init = &(struct clk_init_data){
2217 .name = "venus0_core0_vcodec_clk",
2218 .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2219 .num_parents = 1,
2220 .flags = CLK_SET_RATE_PARENT,
2221 .ops = &clk_branch2_ops,
2222 },
2223 },
2224 };
2225
2226 static struct clk_branch venus0_core1_vcodec_clk = {
2227 .halt_reg = 0x104c,
2228 .clkr = {
2229 .enable_reg = 0x104c,
2230 .enable_mask = BIT(0),
2231 .hw.init = &(struct clk_init_data){
2232 .name = "venus0_core1_vcodec_clk",
2233 .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2234 .num_parents = 1,
2235 .flags = CLK_SET_RATE_PARENT,
2236 .ops = &clk_branch2_ops,
2237 },
2238 },
2239 };
2240
2241 static struct clk_branch venus0_core2_vcodec_clk = {
2242 .halt_reg = 0x1054,
2243 .clkr = {
2244 .enable_reg = 0x1054,
2245 .enable_mask = BIT(0),
2246 .hw.init = &(struct clk_init_data){
2247 .name = "venus0_core2_vcodec_clk",
2248 .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2249 .num_parents = 1,
2250 .flags = CLK_SET_RATE_PARENT,
2251 .ops = &clk_branch2_ops,
2252 },
2253 },
2254 };
2255
2256 static struct gdsc venus_gdsc = {
2257 .gdscr = 0x1024,
2258 .cxcs = (unsigned int []){ 0x1038, 0x1034, 0x1048 },
2259 .cxc_count = 3,
2260 .pd = {
2261 .name = "venus_gdsc",
2262 },
2263 .pwrsts = PWRSTS_OFF_ON,
2264 };
2265
2266 static struct gdsc venus_core0_gdsc = {
2267 .gdscr = 0x1040,
2268 .cxcs = (unsigned int []){ 0x1048 },
2269 .cxc_count = 1,
2270 .pd = {
2271 .name = "venus_core0_gdsc",
2272 },
2273 .pwrsts = PWRSTS_OFF_ON,
2274 .flags = HW_CTRL,
2275 };
2276
2277 static struct gdsc venus_core1_gdsc = {
2278 .gdscr = 0x1044,
2279 .cxcs = (unsigned int []){ 0x104c },
2280 .cxc_count = 1,
2281 .pd = {
2282 .name = "venus_core1_gdsc",
2283 },
2284 .pwrsts = PWRSTS_OFF_ON,
2285 .flags = HW_CTRL,
2286 };
2287
2288 static struct gdsc venus_core2_gdsc = {
2289 .gdscr = 0x1050,
2290 .cxcs = (unsigned int []){ 0x1054 },
2291 .cxc_count = 1,
2292 .pd = {
2293 .name = "venus_core2_gdsc",
2294 },
2295 .pwrsts = PWRSTS_OFF_ON,
2296 .flags = HW_CTRL,
2297 };
2298
2299 static struct gdsc mdss_gdsc = {
2300 .gdscr = 0x2304,
2301 .cxcs = (unsigned int []){ 0x2310, 0x231c },
2302 .cxc_count = 2,
2303 .pd = {
2304 .name = "mdss_gdsc",
2305 },
2306 .pwrsts = PWRSTS_OFF_ON,
2307 };
2308
2309 static struct gdsc camss_top_gdsc = {
2310 .gdscr = 0x34a0,
2311 .cxcs = (unsigned int []){ 0x3704, 0x3714, 0x3494 },
2312 .cxc_count = 3,
2313 .pd = {
2314 .name = "camss_top_gdsc",
2315 },
2316 .pwrsts = PWRSTS_OFF_ON,
2317 };
2318
2319 static struct gdsc jpeg_gdsc = {
2320 .gdscr = 0x35a4,
2321 .cxcs = (unsigned int []){ 0x35a8 },
2322 .cxc_count = 1,
2323 .pd = {
2324 .name = "jpeg_gdsc",
2325 },
2326 .parent = &camss_top_gdsc.pd,
2327 .pwrsts = PWRSTS_OFF_ON,
2328 };
2329
2330 static struct gdsc vfe_gdsc = {
2331 .gdscr = 0x36a4,
2332 .cxcs = (unsigned int []){ 0x36bc },
2333 .cxc_count = 1,
2334 .pd = {
2335 .name = "vfe_gdsc",
2336 },
2337 .parent = &camss_top_gdsc.pd,
2338 .pwrsts = PWRSTS_OFF_ON,
2339 };
2340
2341 static struct gdsc cpp_gdsc = {
2342 .gdscr = 0x36d4,
2343 .cxcs = (unsigned int []){ 0x36c4, 0x36b0 },
2344 .cxc_count = 2,
2345 .pd = {
2346 .name = "cpp_gdsc",
2347 },
2348 .parent = &camss_top_gdsc.pd,
2349 .pwrsts = PWRSTS_OFF_ON,
2350 };
2351
2352 static struct gdsc fd_gdsc = {
2353 .gdscr = 0x3b64,
2354 .cxcs = (unsigned int []){ 0x3b70, 0x3b68 },
2355 .pd = {
2356 .name = "fd_gdsc",
2357 },
2358 .pwrsts = PWRSTS_OFF_ON,
2359 };
2360
2361 static struct gdsc oxili_cx_gdsc = {
2362 .gdscr = 0x4034,
2363 .pd = {
2364 .name = "oxili_cx_gdsc",
2365 },
2366 .pwrsts = PWRSTS_OFF_ON,
2367 .flags = VOTABLE,
2368 };
2369
2370 static struct gdsc oxili_gx_gdsc = {
2371 .gdscr = 0x4024,
2372 .cxcs = (unsigned int []){ 0x4028 },
2373 .cxc_count = 1,
2374 .pd = {
2375 .name = "oxili_gx_gdsc",
2376 },
2377 .pwrsts = PWRSTS_OFF_ON,
2378 .parent = &oxili_cx_gdsc.pd,
2379 .flags = CLAMP_IO,
2380 .supply = "VDD_GFX",
2381 };
2382
2383 static struct clk_regmap *mmcc_msm8994_clocks[] = {
2384 [MMPLL0_EARLY] = &mmpll0_early.clkr,
2385 [MMPLL0_PLL] = &mmpll0.clkr,
2386 [MMPLL1_EARLY] = &mmpll1_early.clkr,
2387 [MMPLL1_PLL] = &mmpll1.clkr,
2388 [MMPLL3_EARLY] = &mmpll3_early.clkr,
2389 [MMPLL3_PLL] = &mmpll3.clkr,
2390 [MMPLL4_EARLY] = &mmpll4_early.clkr,
2391 [MMPLL4_PLL] = &mmpll4.clkr,
2392 [MMPLL5_EARLY] = &mmpll5_early.clkr,
2393 [MMPLL5_PLL] = &mmpll5.clkr,
2394 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2395 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2396 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2397 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2398 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2399 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2400 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2401 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2402 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2403 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2404 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2405 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2406 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2407 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2408 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2409 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2410 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2411 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2412 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2413 [MMSS_GP0_CLK_SRC] = &mmss_gp0_clk_src.clkr,
2414 [MMSS_GP1_CLK_SRC] = &mmss_gp1_clk_src.clkr,
2415 [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
2416 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2417 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2418 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2419 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2420 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2421 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2422 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2423 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2424 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2425 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2426 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2427 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2428 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2429 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2430 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2431 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
2432 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2433 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2434 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2435 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2436 [CAMSS_VFE_CPP_AXI_CLK] = &camss_vfe_cpp_axi_clk.clkr,
2437 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2438 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2439 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2440 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2441 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2442 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2443 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2444 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2445 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2446 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2447 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2448 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2449 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2450 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2451 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2452 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2453 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2454 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2455 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2456 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2457 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2458 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2459 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2460 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2461 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2462 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2463 [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
2464 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2465 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2466 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2467 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2468 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2469 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2470 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2471 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2472 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2473 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2474 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2475 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2476 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2477 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2478 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2479 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2480 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2481 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2482 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
2483 [FD_AXI_CLK] = &fd_axi_clk.clkr,
2484 [FD_CORE_CLK] = &fd_core_clk.clkr,
2485 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2486 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2487 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2488 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2489 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2490 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2491 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2492 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2493 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2494 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2495 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2496 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2497 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2498 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2499 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2500 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2501 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2502 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
2503 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2504 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2505 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2506 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2507 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2508 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
2509 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
2510 [VENUS0_CORE2_VCODEC_CLK] = &venus0_core2_vcodec_clk.clkr,
2511 };
2512
2513 static struct gdsc *mmcc_msm8994_gdscs[] = {
2514 [VENUS_GDSC] = &venus_gdsc,
2515 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
2516 [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
2517 [VENUS_CORE2_GDSC] = &venus_core2_gdsc,
2518 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2519 [MDSS_GDSC] = &mdss_gdsc,
2520 [JPEG_GDSC] = &jpeg_gdsc,
2521 [VFE_GDSC] = &vfe_gdsc,
2522 [CPP_GDSC] = &cpp_gdsc,
2523 [OXILI_GX_GDSC] = &oxili_gx_gdsc,
2524 [OXILI_CX_GDSC] = &oxili_cx_gdsc,
2525 [FD_GDSC] = &fd_gdsc,
2526 };
2527
2528 static const struct qcom_reset_map mmcc_msm8994_resets[] = {
2529 [CAMSS_MICRO_BCR] = { 0x3490 },
2530 };
2531
2532 static const struct regmap_config mmcc_msm8994_regmap_config = {
2533 .reg_bits = 32,
2534 .reg_stride = 4,
2535 .val_bits = 32,
2536 .max_register = 0x5200,
2537 .fast_io = true,
2538 };
2539
2540 static const struct qcom_cc_desc mmcc_msm8994_desc = {
2541 .config = &mmcc_msm8994_regmap_config,
2542 .clks = mmcc_msm8994_clocks,
2543 .num_clks = ARRAY_SIZE(mmcc_msm8994_clocks),
2544 .resets = mmcc_msm8994_resets,
2545 .num_resets = ARRAY_SIZE(mmcc_msm8994_resets),
2546 .gdscs = mmcc_msm8994_gdscs,
2547 .num_gdscs = ARRAY_SIZE(mmcc_msm8994_gdscs),
2548 };
2549
2550 static const struct of_device_id mmcc_msm8994_match_table[] = {
2551 { .compatible = "qcom,mmcc-msm8992" },
2552 { .compatible = "qcom,mmcc-msm8994" }, /* V2 and V2.1 */
2553 { }
2554 };
2555 MODULE_DEVICE_TABLE(of, mmcc_msm8994_match_table);
2556
mmcc_msm8994_probe(struct platform_device * pdev)2557 static int mmcc_msm8994_probe(struct platform_device *pdev)
2558 {
2559 struct regmap *regmap;
2560
2561 if (of_device_is_compatible(pdev->dev.of_node, "qcom,mmcc-msm8992")) {
2562 /* MSM8992 features less clocks and some have different freq tables */
2563 mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG1_CLK] = NULL;
2564 mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG2_CLK] = NULL;
2565 mmcc_msm8994_desc.clks[FD_CORE_CLK_SRC] = NULL;
2566 mmcc_msm8994_desc.clks[FD_CORE_CLK] = NULL;
2567 mmcc_msm8994_desc.clks[FD_CORE_UAR_CLK] = NULL;
2568 mmcc_msm8994_desc.clks[FD_AXI_CLK] = NULL;
2569 mmcc_msm8994_desc.clks[FD_AHB_CLK] = NULL;
2570 mmcc_msm8994_desc.clks[JPEG1_CLK_SRC] = NULL;
2571 mmcc_msm8994_desc.clks[JPEG2_CLK_SRC] = NULL;
2572 mmcc_msm8994_desc.clks[VENUS0_CORE2_VCODEC_CLK] = NULL;
2573
2574 mmcc_msm8994_desc.gdscs[FD_GDSC] = NULL;
2575 mmcc_msm8994_desc.gdscs[VENUS_CORE2_GDSC] = NULL;
2576
2577 axi_clk_src.freq_tbl = ftbl_axi_clk_src_8992;
2578 cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_8992;
2579 csi0_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2580 csi1_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2581 csi2_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2582 csi3_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2583 mclk0_clk_src.freq_tbl = ftbl_mclk0_clk_src_8992;
2584 mclk1_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2585 mclk2_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2586 mclk3_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2587 mdp_clk_src.freq_tbl = ftbl_mdp_clk_src_8992;
2588 ocmemnoc_clk_src.freq_tbl = ftbl_ocmemnoc_clk_src_8992;
2589 vcodec0_clk_src.freq_tbl = ftbl_vcodec0_clk_src_8992;
2590 vfe0_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992;
2591 vfe1_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992;
2592 }
2593
2594 regmap = qcom_cc_map(pdev, &mmcc_msm8994_desc);
2595 if (IS_ERR(regmap))
2596 return PTR_ERR(regmap);
2597
2598 clk_alpha_pll_configure(&mmpll0_early, regmap, &mmpll_p_config);
2599 clk_alpha_pll_configure(&mmpll1_early, regmap, &mmpll_p_config);
2600 clk_alpha_pll_configure(&mmpll3_early, regmap, &mmpll_p_config);
2601 clk_alpha_pll_configure(&mmpll5_early, regmap, &mmpll_p_config);
2602
2603 return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8994_desc, regmap);
2604 }
2605
2606 static struct platform_driver mmcc_msm8994_driver = {
2607 .probe = mmcc_msm8994_probe,
2608 .driver = {
2609 .name = "mmcc-msm8994",
2610 .of_match_table = mmcc_msm8994_match_table,
2611 },
2612 };
2613 module_platform_driver(mmcc_msm8994_driver);
2614
2615 MODULE_DESCRIPTION("QCOM MMCC MSM8994 Driver");
2616 MODULE_LICENSE("GPL v2");
2617 MODULE_ALIAS("platform:mmcc-msm8994");
2618