1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/firmware/imx/sm.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/pm_qos.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/time.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 24 25 #include "fsl_sai.h" 26 #include "fsl_utils.h" 27 #include "imx-pcm.h" 28 29 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 30 FSL_SAI_CSR_FEIE) 31 32 static const unsigned int fsl_sai_rates[] = { 33 8000, 11025, 12000, 16000, 22050, 34 24000, 32000, 44100, 48000, 64000, 35 88200, 96000, 176400, 192000, 352800, 36 384000, 705600, 768000, 1411200, 2822400, 37 }; 38 39 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 40 .count = ARRAY_SIZE(fsl_sai_rates), 41 .list = fsl_sai_rates, 42 }; 43 44 static const char * const inc_mode[] = { 45 "On enabled and bitcount increment", "On enabled" 46 }; 47 48 static SOC_ENUM_SINGLE_DECL(transmit_tstmp_enum, 49 FSL_SAI_TTCTL, FSL_SAI_xTCTL_TSINC_SHIFT, inc_mode); 50 static SOC_ENUM_SINGLE_DECL(receive_tstmp_enum, 51 FSL_SAI_RTCTL, FSL_SAI_xTCTL_TSINC_SHIFT, inc_mode); 52 53 static const struct snd_kcontrol_new fsl_sai_timestamp_ctrls[] = { 54 FSL_ASOC_SINGLE_EXT("Transmit Timestamp Control Switch", FSL_SAI_TTCTL, 55 FSL_SAI_xTCTL_TSEN_SHIFT, 1, 0, 56 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 57 FSL_ASOC_ENUM_EXT("Transmit Timestamp Increment", transmit_tstmp_enum, 58 fsl_asoc_get_enum_double, fsl_asoc_put_enum_double), 59 FSL_ASOC_SINGLE_EXT("Transmit Timestamp Reset Switch", FSL_SAI_TTCTL, 60 FSL_SAI_xTCTL_RTSC_SHIFT, 1, 0, 61 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 62 FSL_ASOC_SINGLE_EXT("Transmit Bit Counter Reset Switch", FSL_SAI_TTCTL, 63 FSL_SAI_xTCTL_RBC_SHIFT, 1, 0, 64 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 65 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Timestamp Counter", FSL_SAI_TTCTN, 66 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 67 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Counter", FSL_SAI_TBCTN, 68 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 69 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Latched Timestamp Counter", FSL_SAI_TTCAP, 70 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 71 FSL_ASOC_SINGLE_EXT("Receive Timestamp Control Switch", FSL_SAI_RTCTL, 72 FSL_SAI_xTCTL_TSEN_SHIFT, 1, 0, 73 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 74 FSL_ASOC_ENUM_EXT("Receive Timestamp Increment", receive_tstmp_enum, 75 fsl_asoc_get_enum_double, fsl_asoc_put_enum_double), 76 FSL_ASOC_SINGLE_EXT("Receive Timestamp Reset Switch", FSL_SAI_RTCTL, 77 FSL_SAI_xTCTL_RTSC_SHIFT, 1, 0, 78 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 79 FSL_ASOC_SINGLE_EXT("Receive Bit Counter Reset Switch", FSL_SAI_RTCTL, 80 FSL_SAI_xTCTL_RBC_SHIFT, 1, 0, 81 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 82 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Timestamp Counter", FSL_SAI_RTCTN, 83 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 84 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Counter", FSL_SAI_RBCTN, 85 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 86 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Latched Timestamp Counter", FSL_SAI_RTCAP, 87 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 88 }; 89 90 /** 91 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 92 * 93 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 94 * or Receiver's for both streams. This function is used to check if clocks of 95 * the stream's are synced by the opposite stream. 96 * 97 * @sai: SAI context 98 * @dir: stream direction 99 */ 100 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 101 { 102 int adir = (dir == TX) ? RX : TX; 103 104 /* current dir in async mode while opposite dir in sync mode */ 105 return !sai->synchronous[dir] && sai->synchronous[adir]; 106 } 107 108 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 109 { 110 struct pinctrl_state *state = NULL; 111 112 if (sai->is_pdm_mode) { 113 /* DSD512@44.1kHz, DSD512@48kHz */ 114 if (bclk >= 22579200) 115 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 116 117 /* Get default DSD state */ 118 if (IS_ERR_OR_NULL(state)) 119 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 120 } else { 121 /* 706k32b2c, 768k32b2c, etc */ 122 if (bclk >= 45158400) 123 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 124 } 125 126 /* Get default state */ 127 if (IS_ERR_OR_NULL(state)) 128 state = pinctrl_lookup_state(sai->pinctrl, "default"); 129 130 return state; 131 } 132 133 static irqreturn_t fsl_sai_isr(int irq, void *devid) 134 { 135 struct fsl_sai *sai = (struct fsl_sai *)devid; 136 unsigned int ofs = sai->soc_data->reg_offset; 137 struct device *dev = &sai->pdev->dev; 138 u32 flags, xcsr, mask; 139 irqreturn_t iret = IRQ_NONE; 140 141 /* 142 * Both IRQ status bits and IRQ mask bits are in the xCSR but 143 * different shifts. And we here create a mask only for those 144 * IRQs that we activated. 145 */ 146 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 147 148 /* Tx IRQ */ 149 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 150 flags = xcsr & mask; 151 152 if (flags) 153 iret = IRQ_HANDLED; 154 else 155 goto irq_rx; 156 157 if (flags & FSL_SAI_CSR_WSF) 158 dev_dbg(dev, "isr: Start of Tx word detected\n"); 159 160 if (flags & FSL_SAI_CSR_SEF) 161 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 162 163 if (flags & FSL_SAI_CSR_FEF) 164 dev_dbg(dev, "isr: Transmit underrun detected\n"); 165 166 if (flags & FSL_SAI_CSR_FWF) 167 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 168 169 if (flags & FSL_SAI_CSR_FRF) 170 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 171 172 flags &= FSL_SAI_CSR_xF_W_MASK; 173 xcsr &= ~FSL_SAI_CSR_xF_MASK; 174 175 if (flags) 176 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 177 178 irq_rx: 179 /* Rx IRQ */ 180 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 181 flags = xcsr & mask; 182 183 if (flags) 184 iret = IRQ_HANDLED; 185 else 186 goto out; 187 188 if (flags & FSL_SAI_CSR_WSF) 189 dev_dbg(dev, "isr: Start of Rx word detected\n"); 190 191 if (flags & FSL_SAI_CSR_SEF) 192 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 193 194 if (flags & FSL_SAI_CSR_FEF) 195 dev_dbg(dev, "isr: Receive overflow detected\n"); 196 197 if (flags & FSL_SAI_CSR_FWF) 198 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 199 200 if (flags & FSL_SAI_CSR_FRF) 201 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 202 203 flags &= FSL_SAI_CSR_xF_W_MASK; 204 xcsr &= ~FSL_SAI_CSR_xF_MASK; 205 206 if (flags) 207 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 208 209 out: 210 return iret; 211 } 212 213 static int fsl_sai_set_dai_tdm_slot_tx(struct snd_soc_dai *cpu_dai, u32 tx_mask, 214 u32 rx_mask, int slots, int slot_width) 215 { 216 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 217 bool tx = true; 218 219 sai->slots[tx] = slots; 220 sai->slot_width[tx] = slot_width; 221 222 return 0; 223 } 224 225 static int fsl_sai_set_dai_tdm_slot_rx(struct snd_soc_dai *cpu_dai, u32 tx_mask, 226 u32 rx_mask, int slots, int slot_width) 227 { 228 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 229 bool tx = false; 230 231 sai->slots[tx] = slots; 232 sai->slot_width[tx] = slot_width; 233 234 return 0; 235 } 236 237 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 238 u32 rx_mask, int slots, int slot_width) 239 { 240 int ret; 241 242 ret = fsl_sai_set_dai_tdm_slot_tx(cpu_dai, tx_mask, rx_mask, slots, slot_width); 243 if (ret) 244 return ret; 245 246 return fsl_sai_set_dai_tdm_slot_rx(cpu_dai, tx_mask, rx_mask, slots, slot_width); 247 } 248 249 static int fsl_sai_xlate_tdm_slot_mask(unsigned int slots, 250 unsigned int *tx_mask, unsigned int *rx_mask) 251 { 252 /* Leave it empty, don't change the value of tx_mask and rx_mask */ 253 return 0; 254 } 255 256 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 257 unsigned int ratio) 258 { 259 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 260 261 sai->bclk_ratio = ratio; 262 263 return 0; 264 } 265 266 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 267 int clk_id, unsigned int freq, bool tx) 268 { 269 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 270 unsigned int ofs = sai->soc_data->reg_offset; 271 u32 val_cr2 = 0; 272 273 switch (clk_id) { 274 case FSL_SAI_CLK_BUS: 275 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 276 break; 277 case FSL_SAI_CLK_MAST1: 278 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 279 break; 280 case FSL_SAI_CLK_MAST2: 281 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 282 break; 283 case FSL_SAI_CLK_MAST3: 284 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 285 break; 286 default: 287 return -EINVAL; 288 } 289 290 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 291 FSL_SAI_CR2_MSEL_MASK, val_cr2); 292 293 return 0; 294 } 295 296 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 297 { 298 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 299 int ret; 300 301 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 302 sai->pll8k_clk, sai->pll11k_clk, freq); 303 304 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 305 if (ret < 0) 306 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 307 308 return ret; 309 } 310 311 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 312 int clk_id, unsigned int freq, int dir) 313 { 314 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 315 int ret; 316 317 if (dir == SND_SOC_CLOCK_IN) 318 return 0; 319 320 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 321 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 322 return -EINVAL; 323 } 324 325 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 326 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 327 return -EINVAL; 328 } 329 330 if (sai->mclk_streams == 0 && freq > 0) { 331 ret = fsl_sai_set_mclk_rate(cpu_dai, 332 clk_id ? clk_id : FSL_SAI_CLK_MAST1, 333 freq); 334 if (ret < 0) 335 return ret; 336 } 337 338 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 339 if (ret) { 340 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 341 return ret; 342 } 343 344 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 345 if (ret) 346 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 347 348 return ret; 349 } 350 351 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 352 unsigned int fmt, bool tx) 353 { 354 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 355 unsigned int ofs = sai->soc_data->reg_offset; 356 u32 val_cr2 = 0, val_cr4 = 0; 357 358 if (!sai->is_lsb_first) 359 val_cr4 |= FSL_SAI_CR4_MF; 360 361 sai->is_pdm_mode = false; 362 sai->is_dsp_mode[tx] = false; 363 /* DAI mode */ 364 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 365 case SND_SOC_DAIFMT_I2S: 366 /* 367 * Frame low, 1clk before data, one word length for frame sync, 368 * frame sync starts one serial clock cycle earlier, 369 * that is, together with the last bit of the previous 370 * data word. 371 */ 372 val_cr2 |= FSL_SAI_CR2_BCP; 373 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 374 break; 375 case SND_SOC_DAIFMT_LEFT_J: 376 /* 377 * Frame high, one word length for frame sync, 378 * frame sync asserts with the first bit of the frame. 379 */ 380 val_cr2 |= FSL_SAI_CR2_BCP; 381 break; 382 case SND_SOC_DAIFMT_DSP_A: 383 /* 384 * Frame high, 1clk before data, one bit for frame sync, 385 * frame sync starts one serial clock cycle earlier, 386 * that is, together with the last bit of the previous 387 * data word. 388 */ 389 val_cr2 |= FSL_SAI_CR2_BCP; 390 val_cr4 |= FSL_SAI_CR4_FSE; 391 sai->is_dsp_mode[tx] = true; 392 break; 393 case SND_SOC_DAIFMT_DSP_B: 394 /* 395 * Frame high, one bit for frame sync, 396 * frame sync asserts with the first bit of the frame. 397 */ 398 val_cr2 |= FSL_SAI_CR2_BCP; 399 sai->is_dsp_mode[tx] = true; 400 break; 401 case SND_SOC_DAIFMT_PDM: 402 val_cr2 |= FSL_SAI_CR2_BCP; 403 sai->is_pdm_mode = true; 404 break; 405 case SND_SOC_DAIFMT_RIGHT_J: 406 /* To be done */ 407 default: 408 return -EINVAL; 409 } 410 411 /* DAI clock inversion */ 412 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 413 case SND_SOC_DAIFMT_IB_IF: 414 /* Invert both clocks */ 415 val_cr2 ^= FSL_SAI_CR2_BCP; 416 val_cr4 ^= FSL_SAI_CR4_FSP; 417 break; 418 case SND_SOC_DAIFMT_IB_NF: 419 /* Invert bit clock */ 420 val_cr2 ^= FSL_SAI_CR2_BCP; 421 break; 422 case SND_SOC_DAIFMT_NB_IF: 423 /* Invert frame clock */ 424 val_cr4 ^= FSL_SAI_CR4_FSP; 425 break; 426 case SND_SOC_DAIFMT_NB_NF: 427 /* Nothing to do for both normal cases */ 428 break; 429 default: 430 return -EINVAL; 431 } 432 433 /* DAI clock provider masks */ 434 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 435 case SND_SOC_DAIFMT_BP_FP: 436 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 437 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 438 sai->is_consumer_mode[tx] = false; 439 break; 440 case SND_SOC_DAIFMT_BC_FC: 441 sai->is_consumer_mode[tx] = true; 442 break; 443 case SND_SOC_DAIFMT_BP_FC: 444 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 445 sai->is_consumer_mode[tx] = false; 446 break; 447 case SND_SOC_DAIFMT_BC_FP: 448 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 449 sai->is_consumer_mode[tx] = true; 450 break; 451 default: 452 return -EINVAL; 453 } 454 455 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 456 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 457 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 458 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 459 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 460 461 return 0; 462 } 463 464 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 465 { 466 int ret; 467 468 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 469 if (ret) { 470 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 471 return ret; 472 } 473 474 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 475 if (ret) 476 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 477 478 return ret; 479 } 480 481 static int fsl_sai_set_dai_fmt_tx(struct snd_soc_dai *cpu_dai, unsigned int fmt) 482 { 483 return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 484 } 485 486 static int fsl_sai_set_dai_fmt_rx(struct snd_soc_dai *cpu_dai, unsigned int fmt) 487 { 488 return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 489 } 490 491 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 492 { 493 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 494 unsigned int reg, ofs = sai->soc_data->reg_offset; 495 unsigned long clk_rate; 496 u32 savediv = 0, ratio, bestdiff = freq; 497 int adir = tx ? RX : TX; 498 int dir = tx ? TX : RX; 499 u32 id; 500 bool support_1_1_ratio = sai->verid.version >= 0x0301; 501 502 /* Don't apply to consumer mode */ 503 if (sai->is_consumer_mode[tx]) 504 return 0; 505 506 /* 507 * There is no point in polling MCLK0 if it is identical to MCLK1. 508 * And given that MQS use case has to use MCLK1 though two clocks 509 * are the same, we simply skip MCLK0 and start to find from MCLK1. 510 */ 511 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 512 513 for (; id < FSL_SAI_MCLK_MAX; id++) { 514 int diff; 515 516 clk_rate = clk_get_rate(sai->mclk_clk[id]); 517 if (!clk_rate) 518 continue; 519 520 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 521 if (!ratio || ratio > 512) 522 continue; 523 if (ratio == 1 && !support_1_1_ratio) 524 continue; 525 if ((ratio & 1) && ratio > 1) 526 continue; 527 528 diff = abs((long)clk_rate - ratio * freq); 529 530 /* 531 * Drop the source that can not be 532 * divided into the required rate. 533 */ 534 if (diff != 0 && clk_rate / diff < 1000) 535 continue; 536 537 dev_dbg(dai->dev, 538 "ratio %d for freq %dHz based on clock %ldHz\n", 539 ratio, freq, clk_rate); 540 541 542 if (diff < bestdiff) { 543 savediv = ratio; 544 sai->mclk_id[tx] = id; 545 bestdiff = diff; 546 } 547 548 if (diff == 0) 549 break; 550 } 551 552 if (savediv == 0) { 553 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 554 tx ? 'T' : 'R', freq); 555 return -EINVAL; 556 } 557 558 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 559 sai->mclk_id[tx], savediv, bestdiff); 560 561 /* 562 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 563 * set TCR2 register for playback. 564 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 565 * and capture. 566 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 567 * and capture. 568 * 4) For Tx and Rx are both Synchronous with another SAI, we just 569 * ignore it. 570 */ 571 if (fsl_sai_dir_is_synced(sai, adir)) 572 reg = FSL_SAI_xCR2(!tx, ofs); 573 else if (!sai->synchronous[dir]) 574 reg = FSL_SAI_xCR2(tx, ofs); 575 else 576 return 0; 577 578 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 579 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 580 581 if (savediv == 1) { 582 regmap_update_bits(sai->regmap, reg, 583 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 584 FSL_SAI_CR2_BYP); 585 if (fsl_sai_dir_is_synced(sai, adir)) 586 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 587 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI); 588 else 589 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 590 FSL_SAI_CR2_BCI, 0); 591 } else { 592 regmap_update_bits(sai->regmap, reg, 593 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 594 savediv / 2 - 1); 595 } 596 597 return 0; 598 } 599 600 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 601 struct snd_pcm_hw_params *params, 602 struct snd_soc_dai *cpu_dai) 603 { 604 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 605 unsigned int ofs = sai->soc_data->reg_offset; 606 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 607 unsigned int channels = params_channels(params); 608 struct snd_dmaengine_dai_dma_data *dma_params; 609 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 610 u32 word_width = params_width(params); 611 int trce_mask = 0, dl_cfg_idx = 0; 612 int dl_cfg_cnt = sai->dl_cfg_cnt; 613 u32 dl_type = FSL_SAI_DL_I2S; 614 u32 val_cr4 = 0, val_cr5 = 0; 615 u32 slots = (channels == 1) ? 2 : channels; 616 u32 slot_width = word_width; 617 int adir = tx ? RX : TX; 618 u32 pins, bclk; 619 u32 watermark; 620 int ret, i; 621 622 if (sai->slot_width[tx]) 623 slot_width = sai->slot_width[tx]; 624 625 if (sai->slots[tx]) 626 slots = sai->slots[tx]; 627 else if (sai->bclk_ratio) 628 slots = sai->bclk_ratio / slot_width; 629 630 pins = DIV_ROUND_UP(channels, slots); 631 632 /* 633 * PDM mode, channels are independent 634 * each channels are on one dataline/FIFO. 635 */ 636 if (sai->is_pdm_mode) { 637 pins = channels; 638 dl_type = FSL_SAI_DL_PDM; 639 } 640 641 for (i = 0; i < dl_cfg_cnt; i++) { 642 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 643 dl_cfg_idx = i; 644 break; 645 } 646 } 647 648 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 649 dev_err(cpu_dai->dev, "channel not supported\n"); 650 return -EINVAL; 651 } 652 653 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 654 655 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 656 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 657 if (!IS_ERR_OR_NULL(sai->pins_state)) { 658 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 659 if (ret) { 660 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 661 return ret; 662 } 663 } 664 } 665 666 if (!sai->is_consumer_mode[tx]) { 667 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 668 if (ret) 669 return ret; 670 671 /* Do not enable the clock if it is already enabled */ 672 if (!(sai->mclk_streams & BIT(substream->stream))) { 673 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 674 if (ret) 675 return ret; 676 677 sai->mclk_streams |= BIT(substream->stream); 678 } 679 } 680 681 if (!sai->is_dsp_mode[tx] && !sai->is_pdm_mode) 682 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 683 684 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 685 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 686 687 if (sai->is_lsb_first) 688 val_cr5 |= FSL_SAI_CR5_FBT(0); 689 else 690 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 691 692 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 693 694 /* Set to avoid channel swap */ 695 val_cr4 |= FSL_SAI_CR4_FCONT; 696 697 /* Set to output mode to avoid tri-stated data pins */ 698 if (tx) 699 val_cr4 |= FSL_SAI_CR4_CHMOD; 700 701 /* 702 * When Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will provide bclk and 703 * frame clock for Tx(Rx). We should set RCR4(TCR4), RCR5(TCR5) 704 * for playback(capture), or there will be sync error. 705 */ 706 707 if (fsl_sai_dir_is_synced(sai, adir)) { 708 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 709 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 710 FSL_SAI_CR4_CHMOD_MASK, 711 val_cr4); 712 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 713 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 714 FSL_SAI_CR5_FBT_MASK, val_cr5); 715 } 716 717 /* 718 * Combine mode has limation: 719 * - Can't used for singel dataline/FIFO case except the FIFO0 720 * - Can't used for multi dataline/FIFO case except the enabled FIFOs 721 * are successive and start from FIFO0 722 * 723 * So for common usage, all multi fifo case disable the combine mode. 724 */ 725 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) 726 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 727 FSL_SAI_CR4_FCOMB_MASK, 0); 728 else 729 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 730 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 731 732 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 733 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 734 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 735 736 if (sai->is_multi_fifo_dma) { 737 sai->audio_config[tx].words_per_fifo = min(slots, channels); 738 if (tx) { 739 sai->audio_config[tx].n_fifos_dst = pins; 740 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; 741 } else { 742 sai->audio_config[tx].n_fifos_src = pins; 743 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; 744 } 745 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; 746 dma_params->peripheral_config = &sai->audio_config[tx]; 747 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); 748 749 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : 750 (dma_params->maxburst - 1); 751 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), 752 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 753 watermark); 754 } 755 756 /* Find a proper tcre setting */ 757 for (i = 0; i < sai->soc_data->pins; i++) { 758 trce_mask = (1 << (i + 1)) - 1; 759 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 760 break; 761 } 762 763 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 764 FSL_SAI_CR3_TRCE_MASK, 765 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 766 767 /* 768 * When the TERE and FSD_MSTR enabled before configuring the word width 769 * There will be no frame sync clock issue, because word width impact 770 * the generation of frame sync clock. 771 * 772 * TERE enabled earlier only for i.MX8MP case for the hardware limitation, 773 * We need to disable FSD_MSTR before configuring word width, then enable 774 * FSD_MSTR bit for this specific case. 775 */ 776 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 777 !sai->is_consumer_mode[tx]) 778 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 779 FSL_SAI_CR4_FSD_MSTR, 0); 780 781 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 782 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 783 FSL_SAI_CR4_CHMOD_MASK | FSL_SAI_CR4_FCONT_MASK, 784 val_cr4); 785 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 786 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 787 FSL_SAI_CR5_FBT_MASK, val_cr5); 788 789 /* Enable FSD_MSTR after configuring word width */ 790 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 791 !sai->is_consumer_mode[tx]) 792 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 793 FSL_SAI_CR4_FSD_MSTR, FSL_SAI_CR4_FSD_MSTR); 794 795 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 796 ~0UL - ((1 << min(channels, slots)) - 1)); 797 798 return 0; 799 } 800 801 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 802 struct snd_soc_dai *cpu_dai) 803 { 804 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 805 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 806 unsigned int ofs = sai->soc_data->reg_offset; 807 808 /* Clear xMR to avoid channel swap with mclk_with_tere enabled case */ 809 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0); 810 811 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 812 FSL_SAI_CR3_TRCE_MASK, 0); 813 814 if (!sai->is_consumer_mode[tx] && 815 sai->mclk_streams & BIT(substream->stream)) { 816 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 817 sai->mclk_streams &= ~BIT(substream->stream); 818 } 819 820 return 0; 821 } 822 823 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 824 { 825 unsigned int ofs = sai->soc_data->reg_offset; 826 bool tx = dir == TX; 827 u32 xcsr, count = 100, mask; 828 829 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 830 mask = FSL_SAI_CSR_TERE; 831 else 832 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE; 833 834 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 835 mask, 0); 836 837 /* TERE will remain set till the end of current frame */ 838 do { 839 udelay(10); 840 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 841 } while (--count && xcsr & FSL_SAI_CSR_TERE); 842 843 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 844 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 845 846 /* 847 * For sai master mode, after several open/close sai, 848 * there will be no frame clock, and can't recover 849 * anymore. Add software reset to fix this issue. 850 * This is a hardware bug, and will be fix in the 851 * next sai version. 852 * 853 * In consumer mode, this can happen even after a 854 * single open/close, especially if both tx and rx 855 * are running concurrently. 856 */ 857 /* Software Reset */ 858 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 859 /* Clear SR bit to finish the reset */ 860 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR, 0); 861 } 862 863 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 864 struct snd_soc_dai *cpu_dai) 865 { 866 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 867 unsigned int ofs = sai->soc_data->reg_offset; 868 869 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 870 int adir = tx ? RX : TX; 871 int dir = tx ? TX : RX; 872 u32 xcsr; 873 874 /* 875 * Asynchronous mode: Clear SYNC for both Tx and Rx. 876 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 877 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 878 */ 879 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 880 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 881 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 882 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 883 884 /* 885 * It is recommended that the transmitter is the last enabled 886 * and the first disabled. 887 */ 888 switch (cmd) { 889 case SNDRV_PCM_TRIGGER_START: 890 case SNDRV_PCM_TRIGGER_RESUME: 891 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 892 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 893 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 894 895 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 896 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 897 /* 898 * Enable the opposite direction for synchronous mode 899 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 900 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 901 * 902 * RM recommends to enable RE after TE for case 1 and to enable 903 * TE after RE for case 2, but we here may not always guarantee 904 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 905 * TE after RE, which is against what RM recommends but should 906 * be safe to do, judging by years of testing results. 907 */ 908 if (fsl_sai_dir_is_synced(sai, adir)) 909 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 910 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 911 912 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 913 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 914 break; 915 case SNDRV_PCM_TRIGGER_STOP: 916 case SNDRV_PCM_TRIGGER_SUSPEND: 917 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 918 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 919 FSL_SAI_CSR_FRDE, 0); 920 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 921 FSL_SAI_CSR_xIE_MASK, 0); 922 923 /* Check if the opposite FRDE is also disabled */ 924 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 925 926 /* 927 * If opposite stream provides clocks for synchronous mode and 928 * it is inactive, disable it before disabling the current one 929 */ 930 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 931 fsl_sai_config_disable(sai, adir); 932 933 /* 934 * Disable current stream if either of: 935 * 1. current stream doesn't provide clocks for synchronous mode 936 * 2. current stream provides clocks for synchronous mode but no 937 * more stream is active. 938 */ 939 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 940 fsl_sai_config_disable(sai, dir); 941 942 break; 943 default: 944 return -EINVAL; 945 } 946 947 return 0; 948 } 949 950 static int fsl_sai_startup(struct snd_pcm_substream *substream, 951 struct snd_soc_dai *cpu_dai) 952 { 953 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 954 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 955 int ret; 956 957 /* 958 * EDMA controller needs period size to be a multiple of 959 * tx/rx maxburst 960 */ 961 if (sai->soc_data->use_edma) 962 snd_pcm_hw_constraint_step(substream->runtime, 0, 963 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 964 tx ? sai->dma_params_tx.maxburst : 965 sai->dma_params_rx.maxburst); 966 967 if (sai->is_consumer_mode[tx]) 968 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 969 SNDRV_PCM_HW_PARAM_RATE, 970 &fsl_sai_rate_constraints); 971 else 972 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 973 SNDRV_PCM_HW_PARAM_RATE, 974 &sai->constraint_rates); 975 976 return ret; 977 } 978 979 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 980 { 981 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 982 unsigned int ofs = sai->soc_data->reg_offset; 983 984 /* Software Reset for both Tx and Rx */ 985 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 986 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 987 /* Clear SR bit to finish the reset */ 988 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, 0); 989 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, 0); 990 991 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 992 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 993 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst); 994 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 995 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 996 sai->dma_params_rx.maxburst - 1); 997 998 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 999 &sai->dma_params_rx); 1000 1001 return 0; 1002 } 1003 1004 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 1005 .probe = fsl_sai_dai_probe, 1006 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 1007 .set_sysclk = fsl_sai_set_dai_sysclk, 1008 .set_fmt = fsl_sai_set_dai_fmt, 1009 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 1010 .hw_params = fsl_sai_hw_params, 1011 .hw_free = fsl_sai_hw_free, 1012 .trigger = fsl_sai_trigger, 1013 .startup = fsl_sai_startup, 1014 }; 1015 1016 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_tx_ops = { 1017 .probe = fsl_sai_dai_probe, 1018 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 1019 .set_sysclk = fsl_sai_set_dai_sysclk, 1020 .set_fmt = fsl_sai_set_dai_fmt_tx, 1021 .set_tdm_slot = fsl_sai_set_dai_tdm_slot_tx, 1022 .xlate_tdm_slot_mask = fsl_sai_xlate_tdm_slot_mask, 1023 .hw_params = fsl_sai_hw_params, 1024 .hw_free = fsl_sai_hw_free, 1025 .trigger = fsl_sai_trigger, 1026 .startup = fsl_sai_startup, 1027 }; 1028 1029 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_rx_ops = { 1030 .probe = fsl_sai_dai_probe, 1031 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 1032 .set_sysclk = fsl_sai_set_dai_sysclk, 1033 .set_fmt = fsl_sai_set_dai_fmt_rx, 1034 .set_tdm_slot = fsl_sai_set_dai_tdm_slot_rx, 1035 .xlate_tdm_slot_mask = fsl_sai_xlate_tdm_slot_mask, 1036 .hw_params = fsl_sai_hw_params, 1037 .hw_free = fsl_sai_hw_free, 1038 .trigger = fsl_sai_trigger, 1039 .startup = fsl_sai_startup, 1040 }; 1041 1042 static int fsl_sai_dai_resume(struct snd_soc_component *component) 1043 { 1044 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 1045 struct device *dev = &sai->pdev->dev; 1046 int ret; 1047 1048 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 1049 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 1050 if (ret) { 1051 dev_err(dev, "failed to set proper pins state: %d\n", ret); 1052 return ret; 1053 } 1054 } 1055 1056 return 0; 1057 } 1058 1059 static int fsl_sai_component_probe(struct snd_soc_component *component) 1060 { 1061 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 1062 1063 if (sai->verid.feature & FSL_SAI_VERID_TSTMP_EN) 1064 snd_soc_add_component_controls(component, fsl_sai_timestamp_ctrls, 1065 ARRAY_SIZE(fsl_sai_timestamp_ctrls)); 1066 1067 return 0; 1068 } 1069 1070 static struct snd_soc_dai_driver fsl_sai_dai_template[] = { 1071 { 1072 .name = "sai-tx-rx", 1073 .playback = { 1074 .stream_name = "CPU-Playback", 1075 .channels_min = 1, 1076 .channels_max = 32, 1077 .rate_min = 8000, 1078 .rate_max = 2822400, 1079 .rates = SNDRV_PCM_RATE_KNOT, 1080 .formats = FSL_SAI_FORMATS, 1081 }, 1082 .capture = { 1083 .stream_name = "CPU-Capture", 1084 .channels_min = 1, 1085 .channels_max = 32, 1086 .rate_min = 8000, 1087 .rate_max = 2822400, 1088 .rates = SNDRV_PCM_RATE_KNOT, 1089 .formats = FSL_SAI_FORMATS, 1090 }, 1091 .ops = &fsl_sai_pcm_dai_ops, 1092 }, 1093 { 1094 .name = "sai-tx", 1095 .playback = { 1096 .stream_name = "SAI-Playback", 1097 .channels_min = 1, 1098 .channels_max = 32, 1099 .rate_min = 8000, 1100 .rate_max = 2822400, 1101 .rates = SNDRV_PCM_RATE_KNOT, 1102 .formats = FSL_SAI_FORMATS, 1103 }, 1104 .ops = &fsl_sai_pcm_dai_tx_ops, 1105 }, 1106 { 1107 .name = "sai-rx", 1108 .capture = { 1109 .stream_name = "SAI-Capture", 1110 .channels_min = 1, 1111 .channels_max = 32, 1112 .rate_min = 8000, 1113 .rate_max = 2822400, 1114 .rates = SNDRV_PCM_RATE_KNOT, 1115 .formats = FSL_SAI_FORMATS, 1116 }, 1117 .ops = &fsl_sai_pcm_dai_rx_ops, 1118 }, 1119 }; 1120 1121 static const struct snd_soc_component_driver fsl_component = { 1122 .name = "fsl-sai", 1123 .probe = fsl_sai_component_probe, 1124 .resume = fsl_sai_dai_resume, 1125 .legacy_dai_naming = 1, 1126 }; 1127 1128 static const struct reg_default fsl_sai_reg_defaults_ofs0[] = { 1129 {FSL_SAI_TCR1(0), 0}, 1130 {FSL_SAI_TCR2(0), 0}, 1131 {FSL_SAI_TCR3(0), 0}, 1132 {FSL_SAI_TCR4(0), 0}, 1133 {FSL_SAI_TCR5(0), 0}, 1134 {FSL_SAI_TDR0, 0}, 1135 {FSL_SAI_TDR1, 0}, 1136 {FSL_SAI_TDR2, 0}, 1137 {FSL_SAI_TDR3, 0}, 1138 {FSL_SAI_TDR4, 0}, 1139 {FSL_SAI_TDR5, 0}, 1140 {FSL_SAI_TDR6, 0}, 1141 {FSL_SAI_TDR7, 0}, 1142 {FSL_SAI_TMR, 0}, 1143 {FSL_SAI_TTCTL, 0}, 1144 {FSL_SAI_RCR1(0), 0}, 1145 {FSL_SAI_RCR2(0), 0}, 1146 {FSL_SAI_RCR3(0), 0}, 1147 {FSL_SAI_RCR4(0), 0}, 1148 {FSL_SAI_RCR5(0), 0}, 1149 {FSL_SAI_RMR, 0}, 1150 }; 1151 1152 static const struct reg_default fsl_sai_reg_defaults_ofs8[] = { 1153 {FSL_SAI_TCR1(8), 0}, 1154 {FSL_SAI_TCR2(8), 0}, 1155 {FSL_SAI_TCR3(8), 0}, 1156 {FSL_SAI_TCR4(8), 0}, 1157 {FSL_SAI_TCR5(8), 0}, 1158 {FSL_SAI_TDR0, 0}, 1159 {FSL_SAI_TDR1, 0}, 1160 {FSL_SAI_TDR2, 0}, 1161 {FSL_SAI_TDR3, 0}, 1162 {FSL_SAI_TDR4, 0}, 1163 {FSL_SAI_TDR5, 0}, 1164 {FSL_SAI_TDR6, 0}, 1165 {FSL_SAI_TDR7, 0}, 1166 {FSL_SAI_TMR, 0}, 1167 {FSL_SAI_TTCTL, 0}, 1168 {FSL_SAI_RCR1(8), 0}, 1169 {FSL_SAI_RCR2(8), 0}, 1170 {FSL_SAI_RCR3(8), 0}, 1171 {FSL_SAI_RCR4(8), 0}, 1172 {FSL_SAI_RCR5(8), 0}, 1173 {FSL_SAI_RMR, 0}, 1174 {FSL_SAI_RTCTL, 0}, 1175 {FSL_SAI_MCTL, 0}, 1176 {FSL_SAI_MDIV, 0}, 1177 }; 1178 1179 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 1180 { 1181 struct fsl_sai *sai = dev_get_drvdata(dev); 1182 unsigned int ofs = sai->soc_data->reg_offset; 1183 1184 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1185 return true; 1186 1187 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1188 return true; 1189 1190 switch (reg) { 1191 case FSL_SAI_TFR0: 1192 case FSL_SAI_TFR1: 1193 case FSL_SAI_TFR2: 1194 case FSL_SAI_TFR3: 1195 case FSL_SAI_TFR4: 1196 case FSL_SAI_TFR5: 1197 case FSL_SAI_TFR6: 1198 case FSL_SAI_TFR7: 1199 case FSL_SAI_TMR: 1200 case FSL_SAI_RDR0: 1201 case FSL_SAI_RDR1: 1202 case FSL_SAI_RDR2: 1203 case FSL_SAI_RDR3: 1204 case FSL_SAI_RDR4: 1205 case FSL_SAI_RDR5: 1206 case FSL_SAI_RDR6: 1207 case FSL_SAI_RDR7: 1208 case FSL_SAI_RFR0: 1209 case FSL_SAI_RFR1: 1210 case FSL_SAI_RFR2: 1211 case FSL_SAI_RFR3: 1212 case FSL_SAI_RFR4: 1213 case FSL_SAI_RFR5: 1214 case FSL_SAI_RFR6: 1215 case FSL_SAI_RFR7: 1216 case FSL_SAI_RMR: 1217 case FSL_SAI_MCTL: 1218 case FSL_SAI_MDIV: 1219 case FSL_SAI_VERID: 1220 case FSL_SAI_PARAM: 1221 case FSL_SAI_TTCTN: 1222 case FSL_SAI_RTCTN: 1223 case FSL_SAI_TTCTL: 1224 case FSL_SAI_TBCTN: 1225 case FSL_SAI_TTCAP: 1226 case FSL_SAI_RTCTL: 1227 case FSL_SAI_RBCTN: 1228 case FSL_SAI_RTCAP: 1229 return true; 1230 default: 1231 return false; 1232 } 1233 } 1234 1235 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1236 { 1237 struct fsl_sai *sai = dev_get_drvdata(dev); 1238 unsigned int ofs = sai->soc_data->reg_offset; 1239 1240 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1241 return true; 1242 1243 /* Set VERID and PARAM be volatile for reading value in probe */ 1244 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1245 return true; 1246 1247 switch (reg) { 1248 case FSL_SAI_TFR0: 1249 case FSL_SAI_TFR1: 1250 case FSL_SAI_TFR2: 1251 case FSL_SAI_TFR3: 1252 case FSL_SAI_TFR4: 1253 case FSL_SAI_TFR5: 1254 case FSL_SAI_TFR6: 1255 case FSL_SAI_TFR7: 1256 case FSL_SAI_RFR0: 1257 case FSL_SAI_RFR1: 1258 case FSL_SAI_RFR2: 1259 case FSL_SAI_RFR3: 1260 case FSL_SAI_RFR4: 1261 case FSL_SAI_RFR5: 1262 case FSL_SAI_RFR6: 1263 case FSL_SAI_RFR7: 1264 case FSL_SAI_RDR0: 1265 case FSL_SAI_RDR1: 1266 case FSL_SAI_RDR2: 1267 case FSL_SAI_RDR3: 1268 case FSL_SAI_RDR4: 1269 case FSL_SAI_RDR5: 1270 case FSL_SAI_RDR6: 1271 case FSL_SAI_RDR7: 1272 case FSL_SAI_TTCTN: 1273 case FSL_SAI_RTCTN: 1274 case FSL_SAI_TTCTL: 1275 case FSL_SAI_TBCTN: 1276 case FSL_SAI_TTCAP: 1277 case FSL_SAI_RTCTL: 1278 case FSL_SAI_RBCTN: 1279 case FSL_SAI_RTCAP: 1280 return true; 1281 default: 1282 return false; 1283 } 1284 } 1285 1286 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1287 { 1288 struct fsl_sai *sai = dev_get_drvdata(dev); 1289 unsigned int ofs = sai->soc_data->reg_offset; 1290 1291 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1292 return true; 1293 1294 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1295 return true; 1296 1297 switch (reg) { 1298 case FSL_SAI_TDR0: 1299 case FSL_SAI_TDR1: 1300 case FSL_SAI_TDR2: 1301 case FSL_SAI_TDR3: 1302 case FSL_SAI_TDR4: 1303 case FSL_SAI_TDR5: 1304 case FSL_SAI_TDR6: 1305 case FSL_SAI_TDR7: 1306 case FSL_SAI_TMR: 1307 case FSL_SAI_RMR: 1308 case FSL_SAI_MCTL: 1309 case FSL_SAI_MDIV: 1310 case FSL_SAI_TTCTL: 1311 case FSL_SAI_RTCTL: 1312 return true; 1313 default: 1314 return false; 1315 } 1316 } 1317 1318 static struct regmap_config fsl_sai_regmap_config = { 1319 .reg_bits = 32, 1320 .reg_stride = 4, 1321 .val_bits = 32, 1322 1323 .max_register = FSL_SAI_RMR, 1324 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1325 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1326 .readable_reg = fsl_sai_readable_reg, 1327 .volatile_reg = fsl_sai_volatile_reg, 1328 .writeable_reg = fsl_sai_writeable_reg, 1329 .cache_type = REGCACHE_FLAT, 1330 }; 1331 1332 static int fsl_sai_check_version(struct device *dev) 1333 { 1334 struct fsl_sai *sai = dev_get_drvdata(dev); 1335 unsigned char ofs = sai->soc_data->reg_offset; 1336 unsigned int val; 1337 int ret; 1338 1339 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1340 return 0; 1341 1342 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1343 if (ret < 0) 1344 return ret; 1345 1346 dev_dbg(dev, "VERID: 0x%016X\n", val); 1347 1348 sai->verid.version = val & 1349 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1350 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT; 1351 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1352 1353 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1354 if (ret < 0) 1355 return ret; 1356 1357 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1358 1359 /* Max slots per frame, power of 2 */ 1360 sai->param.slot_num = 1 << 1361 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1362 1363 /* Words per fifo, power of 2 */ 1364 sai->param.fifo_depth = 1 << 1365 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1366 1367 /* Number of datalines implemented */ 1368 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1369 1370 return 0; 1371 } 1372 1373 /* 1374 * Calculate the offset between first two datalines, don't 1375 * different offset in one case. 1376 */ 1377 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1378 { 1379 int fbidx, nbidx, offset; 1380 1381 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1382 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1383 offset = nbidx - fbidx - 1; 1384 1385 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1386 } 1387 1388 /* 1389 * read the fsl,dataline property from dts file. 1390 * It has 3 value for each configuration, first one means the type: 1391 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1392 * dataline mask for 'tx'. for example 1393 * 1394 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1395 * 1396 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1397 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1398 * 1399 */ 1400 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1401 { 1402 struct platform_device *pdev = sai->pdev; 1403 struct device_node *np = pdev->dev.of_node; 1404 struct device *dev = &pdev->dev; 1405 int ret, elems, i, index, num_cfg; 1406 char *propname = "fsl,dataline"; 1407 struct fsl_sai_dl_cfg *cfg; 1408 unsigned long dl_mask; 1409 unsigned int soc_dl; 1410 u32 rx, tx, type; 1411 1412 elems = of_property_count_u32_elems(np, propname); 1413 1414 if (elems <= 0) { 1415 elems = 0; 1416 } else if (elems % 3) { 1417 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1418 return -EINVAL; 1419 } 1420 1421 num_cfg = elems / 3; 1422 /* Add one more for default value */ 1423 cfg = devm_kcalloc(&pdev->dev, num_cfg + 1, sizeof(*cfg), GFP_KERNEL); 1424 if (!cfg) 1425 return -ENOMEM; 1426 1427 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1428 soc_dl = BIT(sai->soc_data->pins) - 1; 1429 cfg[0].type = FSL_SAI_DL_DEFAULT; 1430 cfg[0].pins[0] = sai->soc_data->pins; 1431 cfg[0].mask[0] = soc_dl; 1432 cfg[0].start_off[0] = 0; 1433 cfg[0].next_off[0] = 0; 1434 1435 cfg[0].pins[1] = sai->soc_data->pins; 1436 cfg[0].mask[1] = soc_dl; 1437 cfg[0].start_off[1] = 0; 1438 cfg[0].next_off[1] = 0; 1439 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1440 /* 1441 * type of dataline 1442 * 0 means default mode 1443 * 1 means I2S mode 1444 * 2 means PDM mode 1445 */ 1446 ret = of_property_read_u32_index(np, propname, index++, &type); 1447 if (ret) 1448 return -EINVAL; 1449 1450 ret = of_property_read_u32_index(np, propname, index++, &rx); 1451 if (ret) 1452 return -EINVAL; 1453 1454 ret = of_property_read_u32_index(np, propname, index++, &tx); 1455 if (ret) 1456 return -EINVAL; 1457 1458 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1459 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1460 return -EINVAL; 1461 } 1462 1463 rx = rx & soc_dl; 1464 tx = tx & soc_dl; 1465 1466 cfg[i].type = type; 1467 cfg[i].pins[0] = hweight8(rx); 1468 cfg[i].mask[0] = rx; 1469 dl_mask = rx; 1470 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1471 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1472 1473 cfg[i].pins[1] = hweight8(tx); 1474 cfg[i].mask[1] = tx; 1475 dl_mask = tx; 1476 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1477 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1478 } 1479 1480 sai->dl_cfg = cfg; 1481 sai->dl_cfg_cnt = num_cfg + 1; 1482 return 0; 1483 } 1484 1485 static int fsl_sai_runtime_suspend(struct device *dev); 1486 static int fsl_sai_runtime_resume(struct device *dev); 1487 1488 static int fsl_sai_probe(struct platform_device *pdev) 1489 { 1490 struct device_node *np = pdev->dev.of_node; 1491 struct device *dev = &pdev->dev; 1492 struct fsl_sai *sai; 1493 struct regmap *gpr; 1494 void __iomem *base; 1495 const char *str = NULL; 1496 char tmp[8]; 1497 int irq, ret, i; 1498 int index; 1499 u32 dmas[4]; 1500 u32 val; 1501 1502 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1503 if (!sai) 1504 return -ENOMEM; 1505 1506 sai->pdev = pdev; 1507 sai->soc_data = of_device_get_match_data(dev); 1508 1509 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1510 1511 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1512 if (IS_ERR(base)) 1513 return PTR_ERR(base); 1514 1515 if (sai->soc_data->reg_offset == 8) { 1516 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1517 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1518 fsl_sai_regmap_config.num_reg_defaults = 1519 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1520 } 1521 1522 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1523 if (IS_ERR(sai->regmap)) { 1524 dev_err(dev, "regmap init failed\n"); 1525 return PTR_ERR(sai->regmap); 1526 } 1527 1528 sai->bus_clk = devm_clk_get(dev, "bus"); 1529 /* Compatible with old DTB cases */ 1530 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1531 sai->bus_clk = devm_clk_get(dev, "sai"); 1532 if (IS_ERR(sai->bus_clk)) { 1533 dev_err(dev, "failed to get bus clock: %ld\n", 1534 PTR_ERR(sai->bus_clk)); 1535 /* -EPROBE_DEFER */ 1536 return PTR_ERR(sai->bus_clk); 1537 } 1538 1539 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1540 sprintf(tmp, "mclk%d", i); 1541 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1542 if (IS_ERR(sai->mclk_clk[i])) { 1543 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1544 i, PTR_ERR(sai->mclk_clk[i])); 1545 sai->mclk_clk[i] = NULL; 1546 } 1547 } 1548 1549 if (sai->soc_data->mclk0_is_mclk1) 1550 sai->mclk_clk[0] = sai->mclk_clk[1]; 1551 else 1552 sai->mclk_clk[0] = sai->bus_clk; 1553 1554 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1555 &sai->pll11k_clk); 1556 1557 fsl_asoc_constrain_rates(&sai->constraint_rates, 1558 &fsl_sai_rate_constraints, 1559 sai->pll8k_clk, sai->pll11k_clk, NULL, 1560 sai->constraint_rates_list); 1561 1562 /* Use Multi FIFO mode depending on the support from SDMA script */ 1563 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1564 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) 1565 sai->is_multi_fifo_dma = true; 1566 1567 /* read dataline mask for rx and tx*/ 1568 ret = fsl_sai_read_dlcfg(sai); 1569 if (ret < 0) { 1570 dev_err(dev, "failed to read dlcfg %d\n", ret); 1571 return ret; 1572 } 1573 1574 irq = platform_get_irq(pdev, 0); 1575 if (irq < 0) 1576 return irq; 1577 1578 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1579 np->name, sai); 1580 if (ret) { 1581 dev_err(dev, "failed to claim irq %u\n", irq); 1582 return ret; 1583 } 1584 1585 memcpy(&sai->cpu_dai_drv, fsl_sai_dai_template, 1586 sizeof(*fsl_sai_dai_template) * ARRAY_SIZE(fsl_sai_dai_template)); 1587 1588 /* Sync Tx with Rx as default by following old DT binding */ 1589 sai->synchronous[RX] = true; 1590 sai->synchronous[TX] = false; 1591 sai->cpu_dai_drv[0].symmetric_rate = 1; 1592 sai->cpu_dai_drv[0].symmetric_channels = 1; 1593 sai->cpu_dai_drv[0].symmetric_sample_bits = 1; 1594 1595 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") && 1596 of_property_read_bool(np, "fsl,sai-asynchronous")) { 1597 /* error out if both synchronous and asynchronous are present */ 1598 dev_err(dev, "invalid binding for synchronous mode\n"); 1599 return -EINVAL; 1600 } 1601 1602 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) { 1603 /* Sync Rx with Tx */ 1604 sai->synchronous[RX] = false; 1605 sai->synchronous[TX] = true; 1606 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) { 1607 /* Discard all settings for asynchronous mode */ 1608 sai->synchronous[RX] = false; 1609 sai->synchronous[TX] = false; 1610 sai->cpu_dai_drv[0].symmetric_rate = 0; 1611 sai->cpu_dai_drv[0].symmetric_channels = 0; 1612 sai->cpu_dai_drv[0].symmetric_sample_bits = 0; 1613 } 1614 1615 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output"); 1616 1617 if (sai->mclk_direction_output && 1618 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1619 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1620 if (IS_ERR(gpr)) { 1621 dev_err(dev, "cannot find iomuxc registers\n"); 1622 return PTR_ERR(gpr); 1623 } 1624 1625 index = of_alias_get_id(np, "sai"); 1626 if (index < 0) 1627 return index; 1628 1629 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1630 MCLK_DIR(index)); 1631 } 1632 1633 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1634 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1635 sai->dma_params_rx.maxburst = 1636 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX; 1637 sai->dma_params_tx.maxburst = 1638 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX; 1639 1640 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1641 1642 platform_set_drvdata(pdev, sai); 1643 pm_runtime_enable(dev); 1644 if (!pm_runtime_enabled(dev)) { 1645 ret = fsl_sai_runtime_resume(dev); 1646 if (ret) 1647 goto err_pm_disable; 1648 } 1649 1650 ret = pm_runtime_resume_and_get(dev); 1651 if (ret < 0) 1652 goto err_pm_get_sync; 1653 1654 /* Get sai version */ 1655 ret = fsl_sai_check_version(dev); 1656 if (ret < 0) 1657 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1658 1659 /* Select MCLK direction */ 1660 if (sai->mclk_direction_output && 1661 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1662 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1663 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1664 } 1665 1666 ret = pm_runtime_put_sync(dev); 1667 if (ret < 0 && ret != -ENOSYS) 1668 goto err_pm_get_sync; 1669 1670 if (of_device_is_compatible(np, "fsl,imx952-sai") && 1671 !of_property_read_string(np, "fsl,sai-amix-mode", &str)) { 1672 if (!strcmp(str, "bypass")) 1673 val = FSL_SAI_AMIX_BYPASS; 1674 else if (!strcmp(str, "audmix")) 1675 val = FSL_SAI_AMIX_AUDMIX; 1676 else 1677 val = FSL_SAI_AMIX_NONE; 1678 1679 if (val < FSL_SAI_AMIX_NONE) { 1680 ret = scmi_imx_misc_ctrl_set(SCMI_IMX952_CTRL_BYPASS_AUDMIX, val); 1681 if (ret) { 1682 dev_err_probe(dev, ret, "Error setting audmix mode\n"); 1683 goto err_pm_get_sync; 1684 } 1685 } 1686 } 1687 1688 /* 1689 * Register platform component before registering cpu dai for there 1690 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1691 */ 1692 if (sai->soc_data->use_imx_pcm) { 1693 ret = imx_pcm_dma_init(pdev); 1694 if (ret) { 1695 dev_err_probe(dev, ret, "PCM DMA init failed\n"); 1696 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1697 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1698 goto err_pm_get_sync; 1699 } 1700 } else { 1701 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1702 if (ret) { 1703 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n"); 1704 goto err_pm_get_sync; 1705 } 1706 } 1707 1708 ret = devm_snd_soc_register_component(dev, &fsl_component, 1709 sai->cpu_dai_drv, ARRAY_SIZE(fsl_sai_dai_template)); 1710 if (ret) 1711 goto err_pm_get_sync; 1712 1713 return ret; 1714 1715 err_pm_get_sync: 1716 if (!pm_runtime_status_suspended(dev)) 1717 fsl_sai_runtime_suspend(dev); 1718 err_pm_disable: 1719 pm_runtime_disable(dev); 1720 1721 return ret; 1722 } 1723 1724 static void fsl_sai_remove(struct platform_device *pdev) 1725 { 1726 pm_runtime_disable(&pdev->dev); 1727 if (!pm_runtime_status_suspended(&pdev->dev)) 1728 fsl_sai_runtime_suspend(&pdev->dev); 1729 } 1730 1731 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1732 .use_imx_pcm = false, 1733 .use_edma = false, 1734 .fifo_depth = 32, 1735 .pins = 1, 1736 .reg_offset = 0, 1737 .mclk0_is_mclk1 = false, 1738 .flags = 0, 1739 .max_register = FSL_SAI_RMR, 1740 }; 1741 1742 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1743 .use_imx_pcm = true, 1744 .use_edma = false, 1745 .fifo_depth = 32, 1746 .pins = 1, 1747 .reg_offset = 0, 1748 .mclk0_is_mclk1 = true, 1749 .flags = 0, 1750 .max_register = FSL_SAI_RMR, 1751 }; 1752 1753 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1754 .use_imx_pcm = true, 1755 .use_edma = false, 1756 .fifo_depth = 16, 1757 .pins = 2, 1758 .reg_offset = 8, 1759 .mclk0_is_mclk1 = false, 1760 .flags = PMQOS_CPU_LATENCY, 1761 .max_register = FSL_SAI_RMR, 1762 }; 1763 1764 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1765 .use_imx_pcm = true, 1766 .use_edma = false, 1767 .fifo_depth = 128, 1768 .pins = 8, 1769 .reg_offset = 8, 1770 .mclk0_is_mclk1 = false, 1771 .flags = 0, 1772 .max_register = FSL_SAI_RMR, 1773 }; 1774 1775 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1776 .use_imx_pcm = true, 1777 .use_edma = true, 1778 .fifo_depth = 64, 1779 .pins = 4, 1780 .reg_offset = 0, 1781 .mclk0_is_mclk1 = false, 1782 .flags = 0, 1783 .max_register = FSL_SAI_RMR, 1784 }; 1785 1786 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1787 .use_imx_pcm = true, 1788 .use_edma = false, 1789 .fifo_depth = 128, 1790 .reg_offset = 8, 1791 .mclk0_is_mclk1 = false, 1792 .pins = 8, 1793 .flags = 0, 1794 .max_register = FSL_SAI_MCTL, 1795 }; 1796 1797 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = { 1798 .use_imx_pcm = true, 1799 .use_edma = false, 1800 .fifo_depth = 128, 1801 .reg_offset = 8, 1802 .mclk0_is_mclk1 = false, 1803 .pins = 8, 1804 .flags = 0, 1805 .max_register = FSL_SAI_MDIV, 1806 }; 1807 1808 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1809 .use_imx_pcm = true, 1810 .use_edma = false, 1811 .fifo_depth = 128, 1812 .reg_offset = 8, 1813 .mclk0_is_mclk1 = false, 1814 .pins = 8, 1815 .flags = 0, 1816 .max_register = FSL_SAI_MDIV, 1817 .mclk_with_tere = true, 1818 }; 1819 1820 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1821 .use_imx_pcm = true, 1822 .use_edma = true, 1823 .fifo_depth = 16, 1824 .reg_offset = 8, 1825 .mclk0_is_mclk1 = false, 1826 .pins = 4, 1827 .flags = PMQOS_CPU_LATENCY, 1828 .max_register = FSL_SAI_RTCAP, 1829 }; 1830 1831 static const struct fsl_sai_soc_data fsl_sai_imx93_data = { 1832 .use_imx_pcm = true, 1833 .use_edma = true, 1834 .fifo_depth = 128, 1835 .reg_offset = 8, 1836 .mclk0_is_mclk1 = false, 1837 .pins = 4, 1838 .flags = 0, 1839 .max_register = FSL_SAI_MCTL, 1840 .max_burst = {8, 8}, 1841 }; 1842 1843 static const struct fsl_sai_soc_data fsl_sai_imx95_data = { 1844 .use_imx_pcm = true, 1845 .use_edma = true, 1846 .fifo_depth = 128, 1847 .reg_offset = 8, 1848 .mclk0_is_mclk1 = false, 1849 .pins = 8, 1850 .flags = 0, 1851 .max_register = FSL_SAI_MCTL, 1852 .max_burst = {8, 8}, 1853 }; 1854 1855 static const struct of_device_id fsl_sai_ids[] = { 1856 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1857 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1858 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1859 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1860 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1861 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1862 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1863 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1864 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1865 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data }, 1866 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data }, 1867 { .compatible = "fsl,imx95-sai", .data = &fsl_sai_imx95_data }, 1868 { /* sentinel */ } 1869 }; 1870 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1871 1872 static int fsl_sai_runtime_suspend(struct device *dev) 1873 { 1874 struct fsl_sai *sai = dev_get_drvdata(dev); 1875 1876 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1877 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1878 1879 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1880 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1881 1882 clk_disable_unprepare(sai->bus_clk); 1883 1884 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1885 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1886 1887 regcache_cache_only(sai->regmap, true); 1888 1889 return 0; 1890 } 1891 1892 static int fsl_sai_runtime_resume(struct device *dev) 1893 { 1894 struct fsl_sai *sai = dev_get_drvdata(dev); 1895 unsigned int ofs = sai->soc_data->reg_offset; 1896 int ret; 1897 1898 ret = clk_prepare_enable(sai->bus_clk); 1899 if (ret) { 1900 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1901 return ret; 1902 } 1903 1904 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1905 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1906 if (ret) 1907 goto disable_bus_clk; 1908 } 1909 1910 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1911 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1912 if (ret) 1913 goto disable_tx_clk; 1914 } 1915 1916 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1917 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1918 1919 regcache_cache_only(sai->regmap, false); 1920 regcache_mark_dirty(sai->regmap); 1921 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 1922 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 1923 usleep_range(1000, 2000); 1924 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, 0); 1925 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, 0); 1926 1927 ret = regcache_sync(sai->regmap); 1928 if (ret) 1929 goto disable_rx_clk; 1930 1931 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 1932 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), 1933 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 1934 1935 return 0; 1936 1937 disable_rx_clk: 1938 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1939 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1940 disable_tx_clk: 1941 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1942 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1943 disable_bus_clk: 1944 clk_disable_unprepare(sai->bus_clk); 1945 1946 return ret; 1947 } 1948 1949 static const struct dev_pm_ops fsl_sai_pm_ops = { 1950 RUNTIME_PM_OPS(fsl_sai_runtime_suspend, fsl_sai_runtime_resume, NULL) 1951 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1952 }; 1953 1954 static struct platform_driver fsl_sai_driver = { 1955 .probe = fsl_sai_probe, 1956 .remove = fsl_sai_remove, 1957 .driver = { 1958 .name = "fsl-sai", 1959 .pm = pm_ptr(&fsl_sai_pm_ops), 1960 .of_match_table = fsl_sai_ids, 1961 }, 1962 }; 1963 module_platform_driver(fsl_sai_driver); 1964 1965 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1966 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1967 MODULE_ALIAS("platform:fsl-sai"); 1968 MODULE_LICENSE("GPL"); 1969