1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 // Copyright 2018 NXP
3
4 #include <linux/bitfield.h>
5 #include <linux/clk.h>
6 #include <linux/device.h>
7 #include <linux/interrupt.h>
8 #include <linux/kobject.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_platform.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/sysfs.h>
18 #include <linux/types.h>
19 #include <linux/dma/imx-dma.h>
20 #include <linux/log2.h>
21 #include <sound/dmaengine_pcm.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/tlv.h>
26 #include <sound/core.h>
27
28 #include "fsl_micfil.h"
29 #include "fsl_utils.h"
30
31 #define MICFIL_OSR_DEFAULT 16
32
33 #define MICFIL_NUM_RATES 7
34 #define MICFIL_CLK_SRC_NUM 3
35 /* clock source ids */
36 #define MICFIL_AUDIO_PLL1 0
37 #define MICFIL_AUDIO_PLL2 1
38 #define MICFIL_CLK_EXT3 2
39
40 static const unsigned int fsl_micfil_rates[] = {
41 8000, 11025, 16000, 22050, 32000, 44100, 48000,
42 };
43
44 static const struct snd_pcm_hw_constraint_list fsl_micfil_rate_constraints = {
45 .count = ARRAY_SIZE(fsl_micfil_rates),
46 .list = fsl_micfil_rates,
47 };
48
49 enum quality {
50 QUALITY_HIGH,
51 QUALITY_MEDIUM,
52 QUALITY_LOW,
53 QUALITY_VLOW0,
54 QUALITY_VLOW1,
55 QUALITY_VLOW2,
56 };
57
58 struct fsl_micfil {
59 struct platform_device *pdev;
60 struct regmap *regmap;
61 const struct fsl_micfil_soc_data *soc;
62 struct clk *busclk;
63 struct clk *mclk;
64 struct clk *pll8k_clk;
65 struct clk *pll11k_clk;
66 struct clk *clk_src[MICFIL_CLK_SRC_NUM];
67 struct snd_dmaengine_dai_dma_data dma_params_rx;
68 struct sdma_peripheral_config sdmacfg;
69 struct snd_soc_card *card;
70 struct snd_pcm_hw_constraint_list constraint_rates;
71 unsigned int constraint_rates_list[MICFIL_NUM_RATES];
72 unsigned int dataline;
73 char name[32];
74 int irq[MICFIL_IRQ_LINES];
75 enum quality quality;
76 int dc_remover;
77 int vad_init_mode;
78 int vad_enabled;
79 int vad_detected;
80 struct fsl_micfil_verid verid;
81 struct fsl_micfil_param param;
82 bool mclk_flag; /* mclk enable flag */
83 bool dec_bypass;
84 };
85
86 struct fsl_micfil_soc_data {
87 unsigned int fifos;
88 unsigned int fifo_depth;
89 unsigned int dataline;
90 bool imx;
91 bool use_edma;
92 bool use_verid;
93 bool volume_sx;
94 u64 formats;
95 int fifo_offset;
96 enum quality default_quality;
97 /* stores const value in formula to calculate range */
98 int rangeadj_const[3][2];
99 };
100
101 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
102 .imx = true,
103 .fifos = 8,
104 .fifo_depth = 8,
105 .dataline = 0xf,
106 .formats = SNDRV_PCM_FMTBIT_S16_LE,
107 .volume_sx = true,
108 .fifo_offset = 0,
109 .default_quality = QUALITY_VLOW0,
110 };
111
112 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
113 .imx = true,
114 .fifos = 8,
115 .fifo_depth = 32,
116 .dataline = 0xf,
117 .formats = SNDRV_PCM_FMTBIT_S32_LE,
118 .volume_sx = false,
119 .fifo_offset = 0,
120 .default_quality = QUALITY_MEDIUM,
121 .rangeadj_const = {{27, 7}, {27, 7}, {26, 7}},
122 };
123
124 static struct fsl_micfil_soc_data fsl_micfil_imx93 = {
125 .imx = true,
126 .fifos = 8,
127 .fifo_depth = 32,
128 .dataline = 0xf,
129 .formats = SNDRV_PCM_FMTBIT_S32_LE,
130 .use_edma = true,
131 .use_verid = true,
132 .volume_sx = false,
133 .fifo_offset = 0,
134 .default_quality = QUALITY_MEDIUM,
135 .rangeadj_const = {{30, 6}, {30, 6}, {29, 6}},
136 };
137
138 static struct fsl_micfil_soc_data fsl_micfil_imx943 = {
139 .imx = true,
140 .fifos = 8,
141 .fifo_depth = 32,
142 .dataline = 0xf,
143 .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_DSD_U32_LE,
144 .use_edma = true,
145 .use_verid = true,
146 .volume_sx = false,
147 .fifo_offset = -4,
148 .default_quality = QUALITY_MEDIUM,
149 .rangeadj_const = {{34, 6}, {34, 6}, {33, 6}},
150 };
151
152 static const struct of_device_id fsl_micfil_dt_ids[] = {
153 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
154 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
155 { .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 },
156 { .compatible = "fsl,imx943-micfil", .data = &fsl_micfil_imx943 },
157 {}
158 };
159 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
160
161 static const char * const micfil_quality_select_texts[] = {
162 [QUALITY_HIGH] = "High",
163 [QUALITY_MEDIUM] = "Medium",
164 [QUALITY_LOW] = "Low",
165 [QUALITY_VLOW0] = "VLow0",
166 [QUALITY_VLOW1] = "Vlow1",
167 [QUALITY_VLOW2] = "Vlow2",
168 };
169
170 static const struct soc_enum fsl_micfil_quality_enum =
171 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
172 micfil_quality_select_texts);
173
174 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
175
micfil_get_max_range(struct fsl_micfil * micfil)176 static int micfil_get_max_range(struct fsl_micfil *micfil)
177 {
178 int max_range;
179
180 switch (micfil->quality) {
181 case QUALITY_HIGH:
182 case QUALITY_VLOW0:
183 max_range = micfil->soc->rangeadj_const[0][0] - micfil->soc->rangeadj_const[0][1] *
184 ilog2(2 * MICFIL_OSR_DEFAULT);
185 break;
186 case QUALITY_MEDIUM:
187 case QUALITY_VLOW1:
188 max_range = micfil->soc->rangeadj_const[1][0] - micfil->soc->rangeadj_const[1][1] *
189 ilog2(MICFIL_OSR_DEFAULT);
190 break;
191 case QUALITY_LOW:
192 case QUALITY_VLOW2:
193 max_range = micfil->soc->rangeadj_const[2][0] - micfil->soc->rangeadj_const[2][1] *
194 ilog2(MICFIL_OSR_DEFAULT);
195 break;
196 default:
197 return 0;
198 }
199 max_range = max_range < 0 ? 0 : max_range;
200
201 return max_range;
202 }
203
micfil_range_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)204 static int micfil_range_set(struct snd_kcontrol *kcontrol,
205 struct snd_ctl_elem_value *ucontrol)
206 {
207 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
208 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
209 struct soc_mixer_control *mc =
210 (struct soc_mixer_control *)kcontrol->private_value;
211 unsigned int shift = mc->shift;
212 int max_range, new_range;
213
214 new_range = ucontrol->value.integer.value[0];
215 max_range = micfil_get_max_range(micfil);
216 if (new_range > max_range)
217 dev_warn(&micfil->pdev->dev, "range makes channel %d data unreliable\n", shift / 4);
218
219 regmap_update_bits(micfil->regmap, REG_MICFIL_OUT_CTRL, 0xF << shift, new_range << shift);
220
221 return 0;
222 }
223
micfil_set_quality(struct fsl_micfil * micfil)224 static int micfil_set_quality(struct fsl_micfil *micfil)
225 {
226 int range, max_range;
227 u32 qsel, val;
228 int i;
229
230 if (!micfil->soc->volume_sx) {
231 regmap_read(micfil->regmap, REG_MICFIL_OUT_CTRL, &val);
232 max_range = micfil_get_max_range(micfil);
233 for (i = 0; i < micfil->soc->fifos; i++) {
234 range = (val >> MICFIL_OUTGAIN_CHX_SHIFT(i)) & 0xF;
235 if (range > max_range)
236 dev_warn(&micfil->pdev->dev, "please reset channel %d range\n", i);
237 }
238 }
239
240 switch (micfil->quality) {
241 case QUALITY_HIGH:
242 qsel = MICFIL_QSEL_HIGH_QUALITY;
243 break;
244 case QUALITY_MEDIUM:
245 qsel = MICFIL_QSEL_MEDIUM_QUALITY;
246 break;
247 case QUALITY_LOW:
248 qsel = MICFIL_QSEL_LOW_QUALITY;
249 break;
250 case QUALITY_VLOW0:
251 qsel = MICFIL_QSEL_VLOW0_QUALITY;
252 break;
253 case QUALITY_VLOW1:
254 qsel = MICFIL_QSEL_VLOW1_QUALITY;
255 break;
256 case QUALITY_VLOW2:
257 qsel = MICFIL_QSEL_VLOW2_QUALITY;
258 break;
259 default:
260 return -EINVAL;
261 }
262
263 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
264 MICFIL_CTRL2_QSEL,
265 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
266 }
267
micfil_quality_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)268 static int micfil_quality_get(struct snd_kcontrol *kcontrol,
269 struct snd_ctl_elem_value *ucontrol)
270 {
271 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
272 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
273
274 ucontrol->value.integer.value[0] = micfil->quality;
275
276 return 0;
277 }
278
micfil_quality_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)279 static int micfil_quality_set(struct snd_kcontrol *kcontrol,
280 struct snd_ctl_elem_value *ucontrol)
281 {
282 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
283 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
284
285 micfil->quality = ucontrol->value.integer.value[0];
286
287 return micfil_set_quality(micfil);
288 }
289
290 static const char * const micfil_hwvad_enable[] = {
291 "Disable (Record only)",
292 "Enable (Record with Vad)",
293 };
294
295 static const char * const micfil_hwvad_init_mode[] = {
296 "Envelope mode", "Energy mode",
297 };
298
299 static const char * const micfil_hwvad_hpf_texts[] = {
300 "Filter bypass",
301 "Cut-off @1750Hz",
302 "Cut-off @215Hz",
303 "Cut-off @102Hz",
304 };
305
306 /*
307 * DC Remover Control
308 * Filter Bypassed 1 1
309 * Cut-off @21Hz 0 0
310 * Cut-off @83Hz 0 1
311 * Cut-off @152HZ 1 0
312 */
313 static const char * const micfil_dc_remover_texts[] = {
314 "Cut-off @21Hz", "Cut-off @83Hz",
315 "Cut-off @152Hz", "Bypass",
316 };
317
318 static const struct soc_enum hwvad_enable_enum =
319 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable),
320 micfil_hwvad_enable);
321 static const struct soc_enum hwvad_init_mode_enum =
322 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode),
323 micfil_hwvad_init_mode);
324 static const struct soc_enum hwvad_hpf_enum =
325 SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0,
326 ARRAY_SIZE(micfil_hwvad_hpf_texts),
327 micfil_hwvad_hpf_texts);
328 static const struct soc_enum fsl_micfil_dc_remover_enum =
329 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts),
330 micfil_dc_remover_texts);
331
micfil_put_dc_remover_state(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)332 static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol,
333 struct snd_ctl_elem_value *ucontrol)
334 {
335 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
336 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
337 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
338 unsigned int *item = ucontrol->value.enumerated.item;
339 int val = snd_soc_enum_item_to_val(e, item[0]);
340 int i = 0, ret = 0;
341 u32 reg_val = 0;
342
343 if (val < 0 || val > 3)
344 return -EINVAL;
345
346 micfil->dc_remover = val;
347
348 /* Calculate total value for all channels */
349 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
350 reg_val |= val << MICFIL_DC_CHX_SHIFT(i);
351
352 /* Update DC Remover mode for all channels */
353 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL,
354 MICFIL_DC_CTRL_CONFIG, reg_val);
355 if (ret < 0)
356 return ret;
357
358 return 0;
359 }
360
micfil_get_dc_remover_state(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)361 static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol,
362 struct snd_ctl_elem_value *ucontrol)
363 {
364 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
365 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
366
367 ucontrol->value.enumerated.item[0] = micfil->dc_remover;
368
369 return 0;
370 }
371
hwvad_put_enable(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)372 static int hwvad_put_enable(struct snd_kcontrol *kcontrol,
373 struct snd_ctl_elem_value *ucontrol)
374 {
375 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
376 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
377 unsigned int *item = ucontrol->value.enumerated.item;
378 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
379 int val = snd_soc_enum_item_to_val(e, item[0]);
380
381 micfil->vad_enabled = val;
382
383 return 0;
384 }
385
hwvad_get_enable(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)386 static int hwvad_get_enable(struct snd_kcontrol *kcontrol,
387 struct snd_ctl_elem_value *ucontrol)
388 {
389 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
390 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
391
392 ucontrol->value.enumerated.item[0] = micfil->vad_enabled;
393
394 return 0;
395 }
396
hwvad_put_init_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)397 static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol,
398 struct snd_ctl_elem_value *ucontrol)
399 {
400 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
401 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
402 unsigned int *item = ucontrol->value.enumerated.item;
403 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
404 int val = snd_soc_enum_item_to_val(e, item[0]);
405
406 /* 0 - Envelope-based Mode
407 * 1 - Energy-based Mode
408 */
409 micfil->vad_init_mode = val;
410
411 return 0;
412 }
413
hwvad_get_init_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)414 static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol,
415 struct snd_ctl_elem_value *ucontrol)
416 {
417 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
418 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
419
420 ucontrol->value.enumerated.item[0] = micfil->vad_init_mode;
421
422 return 0;
423 }
424
hwvad_detected(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)425 static int hwvad_detected(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427 {
428 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
429 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
430
431 ucontrol->value.enumerated.item[0] = micfil->vad_detected;
432
433 return 0;
434 }
435
436 static const struct snd_kcontrol_new fsl_micfil_range_controls[] = {
437 SOC_SINGLE_EXT("CH0 Range", REG_MICFIL_OUT_CTRL,
438 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0,
439 snd_soc_get_volsw, micfil_range_set),
440 SOC_SINGLE_EXT("CH1 Range", REG_MICFIL_OUT_CTRL,
441 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0,
442 snd_soc_get_volsw, micfil_range_set),
443 SOC_SINGLE_EXT("CH2 Range", REG_MICFIL_OUT_CTRL,
444 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0,
445 snd_soc_get_volsw, micfil_range_set),
446 SOC_SINGLE_EXT("CH3 Range", REG_MICFIL_OUT_CTRL,
447 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0,
448 snd_soc_get_volsw, micfil_range_set),
449 SOC_SINGLE_EXT("CH4 Range", REG_MICFIL_OUT_CTRL,
450 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0,
451 snd_soc_get_volsw, micfil_range_set),
452 SOC_SINGLE_EXT("CH5 Range", REG_MICFIL_OUT_CTRL,
453 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0,
454 snd_soc_get_volsw, micfil_range_set),
455 SOC_SINGLE_EXT("CH6 Range", REG_MICFIL_OUT_CTRL,
456 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0,
457 snd_soc_get_volsw, micfil_range_set),
458 SOC_SINGLE_EXT("CH7 Range", REG_MICFIL_OUT_CTRL,
459 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0,
460 snd_soc_get_volsw, micfil_range_set),
461 };
462
463 static const struct snd_kcontrol_new fsl_micfil_volume_sx_controls[] = {
464 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
465 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv),
466 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
467 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv),
468 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
469 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv),
470 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
471 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv),
472 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
473 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv),
474 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
475 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv),
476 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
477 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv),
478 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
479 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),
480 };
481
482 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
483 SOC_ENUM_EXT("MICFIL Quality Select",
484 fsl_micfil_quality_enum,
485 micfil_quality_get, micfil_quality_set),
486 SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum,
487 hwvad_get_enable, hwvad_put_enable),
488 SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum,
489 hwvad_get_init_mode, hwvad_put_init_mode),
490 SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum),
491 SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0),
492 SOC_SINGLE("HWVAD ZCD Auto Threshold Switch",
493 REG_MICFIL_VAD0_ZCD, 2, 1, 0),
494 SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum,
495 micfil_get_dc_remover_state, micfil_put_dc_remover_state),
496 SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0),
497 SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0),
498 SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0),
499 SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0),
500 SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0),
501 SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0),
502 SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0),
503 SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0),
504 SOC_SINGLE("HWVAD ZCD And Behavior Switch",
505 REG_MICFIL_VAD0_ZCD, 4, 1, 0),
506 SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL),
507 };
508
fsl_micfil_use_verid(struct device * dev)509 static int fsl_micfil_use_verid(struct device *dev)
510 {
511 struct fsl_micfil *micfil = dev_get_drvdata(dev);
512 unsigned int val;
513 int ret;
514
515 if (!micfil->soc->use_verid)
516 return 0;
517
518 ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val);
519 if (ret < 0)
520 return ret;
521
522 dev_dbg(dev, "VERID: 0x%016X\n", val);
523
524 micfil->verid.version = val &
525 (MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK);
526 micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT;
527 micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK;
528
529 ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val);
530 if (ret < 0)
531 return ret;
532
533 dev_dbg(dev, "PARAM: 0x%016X\n", val);
534
535 micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >>
536 MICFIL_PARAM_NUM_HWVAD_SHIFT;
537 micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD;
538 micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE;
539 micfil->param.hwvad = val & MICFIL_PARAM_HWVAD;
540 micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS;
541 micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS;
542 micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER;
543 micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH;
544 micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >>
545 MICFIL_PARAM_FIFO_PTRWID_SHIFT;
546 micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >>
547 MICFIL_PARAM_NPAIR_SHIFT;
548
549 return 0;
550 }
551
552 /* The SRES is a self-negated bit which provides the CPU with the
553 * capability to initialize the PDM Interface module through the
554 * slave-bus interface. This bit always reads as zero, and this
555 * bit is only effective when MDIS is cleared
556 */
fsl_micfil_reset(struct device * dev)557 static int fsl_micfil_reset(struct device *dev)
558 {
559 struct fsl_micfil *micfil = dev_get_drvdata(dev);
560 int ret;
561
562 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
563 MICFIL_CTRL1_MDIS);
564 if (ret)
565 return ret;
566
567 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
568 MICFIL_CTRL1_SRES);
569 if (ret)
570 return ret;
571
572 /*
573 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
574 * as non-volatile register, so SRES still remain in regmap
575 * cache after set, that every update of REG_MICFIL_CTRL1,
576 * software reset happens. so clear it explicitly.
577 */
578 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
579 MICFIL_CTRL1_SRES);
580 if (ret)
581 return ret;
582
583 /*
584 * Set SRES should clear CHnF flags, But even add delay here
585 * the CHnF may not be cleared sometimes, so clear CHnF explicitly.
586 */
587 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
588 if (ret)
589 return ret;
590
591 return 0;
592 }
593
fsl_micfil_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)594 static int fsl_micfil_startup(struct snd_pcm_substream *substream,
595 struct snd_soc_dai *dai)
596 {
597 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
598
599 if (!micfil) {
600 dev_err(dai->dev, "micfil dai priv_data not set\n");
601 return -EINVAL;
602 }
603
604 if (micfil->constraint_rates.count > 0)
605 snd_pcm_hw_constraint_list(substream->runtime, 0,
606 SNDRV_PCM_HW_PARAM_RATE,
607 &micfil->constraint_rates);
608
609 return 0;
610 }
611
612 /* Enable/disable hwvad interrupts */
fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil * micfil,int enable)613 static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable)
614 {
615 u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0;
616 u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0;
617
618 /* Voice Activity Detector Error Interruption */
619 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
620 MICFIL_VAD0_CTRL1_ERIE, vaderie_reg);
621
622 /* Voice Activity Detector Interruption */
623 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
624 MICFIL_VAD0_CTRL1_IE, vadie_reg);
625
626 return 0;
627 }
628
629 /* Configuration done only in energy-based initialization mode */
fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil * micfil)630 static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil)
631 {
632 /* Keep the VADFRENDIS bitfield cleared. */
633 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
634 MICFIL_VAD0_CTRL2_FRENDIS);
635
636 /* Keep the VADPREFEN bitfield cleared. */
637 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
638 MICFIL_VAD0_CTRL2_PREFEN);
639
640 /* Keep the VADSFILEN bitfield cleared. */
641 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
642 MICFIL_VAD0_SCONFIG_SFILEN);
643
644 /* Keep the VADSMAXEN bitfield cleared. */
645 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
646 MICFIL_VAD0_SCONFIG_SMAXEN);
647
648 /* Keep the VADNFILAUTO bitfield asserted. */
649 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
650 MICFIL_VAD0_NCONFIG_NFILAUT);
651
652 /* Keep the VADNMINEN bitfield cleared. */
653 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
654 MICFIL_VAD0_NCONFIG_NMINEN);
655
656 /* Keep the VADNDECEN bitfield cleared. */
657 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
658 MICFIL_VAD0_NCONFIG_NDECEN);
659
660 /* Keep the VADNOREN bitfield cleared. */
661 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
662 MICFIL_VAD0_NCONFIG_NOREN);
663
664 return 0;
665 }
666
667 /* Configuration done only in envelope-based initialization mode */
fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil * micfil)668 static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil)
669 {
670 /* Assert the VADFRENDIS bitfield */
671 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
672 MICFIL_VAD0_CTRL2_FRENDIS);
673
674 /* Assert the VADPREFEN bitfield. */
675 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
676 MICFIL_VAD0_CTRL2_PREFEN);
677
678 /* Assert the VADSFILEN bitfield. */
679 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
680 MICFIL_VAD0_SCONFIG_SFILEN);
681
682 /* Assert the VADSMAXEN bitfield. */
683 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
684 MICFIL_VAD0_SCONFIG_SMAXEN);
685
686 /* Clear the VADNFILAUTO bitfield */
687 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
688 MICFIL_VAD0_NCONFIG_NFILAUT);
689
690 /* Assert the VADNMINEN bitfield. */
691 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
692 MICFIL_VAD0_NCONFIG_NMINEN);
693
694 /* Assert the VADNDECEN bitfield. */
695 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
696 MICFIL_VAD0_NCONFIG_NDECEN);
697
698 /* Assert VADNOREN bitfield. */
699 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
700 MICFIL_VAD0_NCONFIG_NOREN);
701
702 return 0;
703 }
704
705 /*
706 * Hardware Voice Active Detection: The HWVAD takes data from the input
707 * of a selected PDM microphone to detect if there is any
708 * voice activity. When a voice activity is detected, an interrupt could
709 * be delivered to the system. Initialization in section 8.4:
710 * Can work in two modes:
711 * -> Eneveope-based mode (section 8.4.1)
712 * -> Energy-based mode (section 8.4.2)
713 *
714 * It is important to remark that the HWVAD detector could be enabled
715 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL
716 * bit in STAT register is cleared
717 */
fsl_micfil_hwvad_enable(struct fsl_micfil * micfil)718 static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil)
719 {
720 int ret;
721
722 micfil->vad_detected = 0;
723
724 /* envelope-based specific initialization */
725 if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE)
726 ret = fsl_micfil_init_hwvad_envelope_mode(micfil);
727 else
728 ret = fsl_micfil_init_hwvad_energy_mode(micfil);
729 if (ret)
730 return ret;
731
732 /* Voice Activity Detector Internal Filters Initialization*/
733 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
734 MICFIL_VAD0_CTRL1_ST10);
735
736 /* Voice Activity Detector Internal Filter */
737 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
738 MICFIL_VAD0_CTRL1_ST10);
739
740 /* Enable Interrupts */
741 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1);
742 if (ret)
743 return ret;
744
745 /* Voice Activity Detector Reset */
746 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
747 MICFIL_VAD0_CTRL1_RST);
748
749 /* Voice Activity Detector Enabled */
750 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
751 MICFIL_VAD0_CTRL1_EN);
752
753 return 0;
754 }
755
fsl_micfil_hwvad_disable(struct fsl_micfil * micfil)756 static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil)
757 {
758 struct device *dev = &micfil->pdev->dev;
759 int ret = 0;
760
761 /* Disable HWVAD */
762 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
763 MICFIL_VAD0_CTRL1_EN);
764
765 /* Disable hwvad interrupts */
766 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0);
767 if (ret)
768 dev_err(dev, "Failed to disable interrupts\n");
769
770 return ret;
771 }
772
fsl_micfil_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)773 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
774 struct snd_soc_dai *dai)
775 {
776 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
777 struct device *dev = &micfil->pdev->dev;
778 int ret;
779
780 switch (cmd) {
781 case SNDRV_PCM_TRIGGER_START:
782 case SNDRV_PCM_TRIGGER_RESUME:
783 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
784 ret = fsl_micfil_reset(dev);
785 if (ret) {
786 dev_err(dev, "failed to soft reset\n");
787 return ret;
788 }
789
790 /* DMA Interrupt Selection - DISEL bits
791 * 00 - DMA and IRQ disabled
792 * 01 - DMA req enabled
793 * 10 - IRQ enabled
794 * 11 - reserved
795 */
796 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
797 MICFIL_CTRL1_DISEL,
798 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
799 if (ret)
800 return ret;
801
802 /* Enable the module */
803 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
804 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN);
805 if (ret)
806 return ret;
807
808 if (micfil->vad_enabled && !micfil->dec_bypass)
809 fsl_micfil_hwvad_enable(micfil);
810
811 break;
812 case SNDRV_PCM_TRIGGER_STOP:
813 case SNDRV_PCM_TRIGGER_SUSPEND:
814 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
815 if (micfil->vad_enabled && !micfil->dec_bypass)
816 fsl_micfil_hwvad_disable(micfil);
817
818 /* Disable the module */
819 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
820 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN);
821 if (ret)
822 return ret;
823
824 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
825 MICFIL_CTRL1_DISEL,
826 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
827 if (ret)
828 return ret;
829 break;
830 default:
831 return -EINVAL;
832 }
833 return 0;
834 }
835
fsl_micfil_reparent_rootclk(struct fsl_micfil * micfil,unsigned int sample_rate)836 static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)
837 {
838 struct device *dev = &micfil->pdev->dev;
839 u64 ratio = sample_rate;
840 struct clk *clk;
841 int ret;
842
843 /* Get root clock */
844 clk = micfil->mclk;
845
846 /* Disable clock first, for it was enabled by pm_runtime */
847 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
848 micfil->pll11k_clk, ratio);
849 ret = clk_prepare_enable(clk);
850 if (ret)
851 return ret;
852
853 return 0;
854 }
855
fsl_micfil_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)856 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
857 struct snd_pcm_hw_params *params,
858 struct snd_soc_dai *dai)
859 {
860 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
861 unsigned int channels = params_channels(params);
862 snd_pcm_format_t format = params_format(params);
863 unsigned int rate = params_rate(params);
864 int clk_div = 8, mclk_rate, div_multiply_k;
865 int osr = MICFIL_OSR_DEFAULT;
866 int ret;
867
868 /* 1. Disable the module */
869 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
870 MICFIL_CTRL1_PDMIEN);
871 if (ret)
872 return ret;
873
874 /* enable channels */
875 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
876 0xFF, ((1 << channels) - 1));
877 if (ret)
878 return ret;
879
880 ret = fsl_micfil_reparent_rootclk(micfil, rate);
881 if (ret)
882 return ret;
883
884 micfil->mclk_flag = true;
885
886 /* floor(K * CLKDIV) */
887 switch (micfil->quality) {
888 case QUALITY_HIGH:
889 div_multiply_k = clk_div >> 1;
890 break;
891 case QUALITY_LOW:
892 case QUALITY_VLOW1:
893 div_multiply_k = clk_div << 1;
894 break;
895 case QUALITY_VLOW2:
896 div_multiply_k = clk_div << 2;
897 break;
898 case QUALITY_MEDIUM:
899 case QUALITY_VLOW0:
900 default:
901 div_multiply_k = clk_div;
902 break;
903 }
904
905 if (format == SNDRV_PCM_FORMAT_DSD_U32_LE) {
906 micfil->dec_bypass = true;
907 /*
908 * According to equation 29 in RM:
909 * MCLK_CLK_ROOT = PDM CLK rate * 2 * floor(K * CLKDIV)
910 * PDM CLK rate = rate * physical bit width (32)
911 */
912 mclk_rate = rate * div_multiply_k * 32 * 2;
913 } else {
914 micfil->dec_bypass = false;
915 mclk_rate = rate * clk_div * osr * 8;
916 }
917
918 ret = clk_set_rate(micfil->mclk, mclk_rate);
919 if (ret)
920 return ret;
921
922 ret = micfil_set_quality(micfil);
923 if (ret)
924 return ret;
925
926 regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
927 MICFIL_CTRL2_DEC_BYPASS,
928 micfil->dec_bypass ? MICFIL_CTRL2_DEC_BYPASS : 0);
929
930 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
931 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
932 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
933 FIELD_PREP(MICFIL_CTRL2_CICOSR, 32 - osr));
934
935 /* Configure CIC OSR in VADCICOSR */
936 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
937 MICFIL_VAD0_CTRL1_CICOSR,
938 FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr));
939
940 /* Configure source channel in VADCHSEL */
941 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
942 MICFIL_VAD0_CTRL1_CHSEL,
943 FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1)));
944
945 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
946 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
947 micfil->sdmacfg.n_fifos_src = channels;
948 micfil->sdmacfg.sw_done = true;
949 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
950 if (micfil->soc->use_edma)
951 micfil->dma_params_rx.maxburst = channels;
952
953 return 0;
954 }
955
fsl_micfil_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)956 static int fsl_micfil_hw_free(struct snd_pcm_substream *substream,
957 struct snd_soc_dai *dai)
958 {
959 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
960
961 clk_disable_unprepare(micfil->mclk);
962 micfil->mclk_flag = false;
963
964 return 0;
965 }
966
fsl_micfil_dai_probe(struct snd_soc_dai * cpu_dai)967 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
968 {
969 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
970 struct device *dev = cpu_dai->dev;
971 unsigned int val = 0;
972 int ret, i, max_range;
973
974 micfil->quality = micfil->soc->default_quality;
975 micfil->card = cpu_dai->component->card;
976
977 /* set default gain to 2 */
978 if (micfil->soc->volume_sx) {
979 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);
980 } else {
981 max_range = micfil_get_max_range(micfil);
982 for (i = 1; i < micfil->soc->fifos; i++)
983 max_range |= max_range << 4;
984 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, max_range);
985 }
986
987 /* set DC Remover in bypass mode*/
988 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
989 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
990 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,
991 MICFIL_DC_CTRL_CONFIG, val);
992 if (ret) {
993 dev_err(dev, "failed to set DC Remover mode bits\n");
994 return ret;
995 }
996 micfil->dc_remover = MICFIL_DC_BYPASS;
997
998 snd_soc_dai_init_dma_data(cpu_dai, NULL,
999 &micfil->dma_params_rx);
1000
1001 /* FIFO Watermark Control - FIFOWMK*/
1002 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
1003 MICFIL_FIFO_CTRL_FIFOWMK,
1004 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
1005 if (ret)
1006 return ret;
1007
1008 return 0;
1009 }
1010
fsl_micfil_component_probe(struct snd_soc_component * component)1011 static int fsl_micfil_component_probe(struct snd_soc_component *component)
1012 {
1013 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(component);
1014
1015 if (micfil->soc->volume_sx)
1016 snd_soc_add_component_controls(component, fsl_micfil_volume_sx_controls,
1017 ARRAY_SIZE(fsl_micfil_volume_sx_controls));
1018 else
1019 snd_soc_add_component_controls(component, fsl_micfil_range_controls,
1020 ARRAY_SIZE(fsl_micfil_range_controls));
1021
1022 return 0;
1023 }
1024
1025 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
1026 .probe = fsl_micfil_dai_probe,
1027 .startup = fsl_micfil_startup,
1028 .trigger = fsl_micfil_trigger,
1029 .hw_params = fsl_micfil_hw_params,
1030 .hw_free = fsl_micfil_hw_free,
1031 };
1032
1033 static struct snd_soc_dai_driver fsl_micfil_dai = {
1034 .capture = {
1035 .stream_name = "CPU-Capture",
1036 .channels_min = 1,
1037 .channels_max = 8,
1038 .rates = SNDRV_PCM_RATE_8000_48000,
1039 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1040 },
1041 .ops = &fsl_micfil_dai_ops,
1042 };
1043
1044 static const struct snd_soc_component_driver fsl_micfil_component = {
1045 .name = "fsl-micfil-dai",
1046 .probe = fsl_micfil_component_probe,
1047 .controls = fsl_micfil_snd_controls,
1048 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
1049 .legacy_dai_naming = 1,
1050 };
1051
1052 /* REGMAP */
1053 static const struct reg_default fsl_micfil_reg_defaults[] = {
1054 {REG_MICFIL_CTRL1, 0x00000000},
1055 {REG_MICFIL_CTRL2, 0x00000000},
1056 {REG_MICFIL_STAT, 0x00000000},
1057 {REG_MICFIL_FIFO_CTRL, 0x0000001F},
1058 {REG_MICFIL_FIFO_STAT, 0x00000000},
1059 {REG_MICFIL_DATACH0, 0x00000000},
1060 {REG_MICFIL_DATACH1, 0x00000000},
1061 {REG_MICFIL_DATACH2, 0x00000000},
1062 {REG_MICFIL_DATACH3, 0x00000000},
1063 {REG_MICFIL_DATACH4, 0x00000000},
1064 {REG_MICFIL_DATACH5, 0x00000000},
1065 {REG_MICFIL_DATACH6, 0x00000000},
1066 {REG_MICFIL_DATACH7, 0x00000000},
1067 {REG_MICFIL_DC_CTRL, 0x00000000},
1068 {REG_MICFIL_OUT_CTRL, 0x00000000},
1069 {REG_MICFIL_OUT_STAT, 0x00000000},
1070 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
1071 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
1072 {REG_MICFIL_VAD0_STAT, 0x00000000},
1073 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
1074 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
1075 {REG_MICFIL_VAD0_NDATA, 0x00000000},
1076 {REG_MICFIL_VAD0_ZCD, 0x00000004},
1077 };
1078
1079 static const struct reg_default fsl_micfil_reg_defaults_v2[] = {
1080 {REG_MICFIL_CTRL1, 0x00000000},
1081 {REG_MICFIL_CTRL2, 0x00000000},
1082 {REG_MICFIL_STAT, 0x00000000},
1083 {REG_MICFIL_FIFO_CTRL, 0x0000001F},
1084 {REG_MICFIL_FIFO_STAT, 0x00000000},
1085 {REG_MICFIL_DATACH0 - 0x4, 0x00000000},
1086 {REG_MICFIL_DATACH1 - 0x4, 0x00000000},
1087 {REG_MICFIL_DATACH2 - 0x4, 0x00000000},
1088 {REG_MICFIL_DATACH3 - 0x4, 0x00000000},
1089 {REG_MICFIL_DATACH4 - 0x4, 0x00000000},
1090 {REG_MICFIL_DATACH5 - 0x4, 0x00000000},
1091 {REG_MICFIL_DATACH6 - 0x4, 0x00000000},
1092 {REG_MICFIL_DATACH7 - 0x4, 0x00000000},
1093 {REG_MICFIL_DC_CTRL, 0x00000000},
1094 {REG_MICFIL_OUT_CTRL, 0x00000000},
1095 {REG_MICFIL_OUT_STAT, 0x00000000},
1096 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
1097 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
1098 {REG_MICFIL_VAD0_STAT, 0x00000000},
1099 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
1100 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
1101 {REG_MICFIL_VAD0_NDATA, 0x00000000},
1102 {REG_MICFIL_VAD0_ZCD, 0x00000004},
1103 };
1104
fsl_micfil_readable_reg(struct device * dev,unsigned int reg)1105 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
1106 {
1107 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1108 int ofs = micfil->soc->fifo_offset;
1109
1110 if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs))
1111 return true;
1112
1113 switch (reg) {
1114 case REG_MICFIL_CTRL1:
1115 case REG_MICFIL_CTRL2:
1116 case REG_MICFIL_STAT:
1117 case REG_MICFIL_FIFO_CTRL:
1118 case REG_MICFIL_FIFO_STAT:
1119 case REG_MICFIL_DC_CTRL:
1120 case REG_MICFIL_OUT_CTRL:
1121 case REG_MICFIL_OUT_STAT:
1122 case REG_MICFIL_VAD0_CTRL1:
1123 case REG_MICFIL_VAD0_CTRL2:
1124 case REG_MICFIL_VAD0_STAT:
1125 case REG_MICFIL_VAD0_SCONFIG:
1126 case REG_MICFIL_VAD0_NCONFIG:
1127 case REG_MICFIL_VAD0_NDATA:
1128 case REG_MICFIL_VAD0_ZCD:
1129 return true;
1130 case REG_MICFIL_FSYNC_CTRL:
1131 case REG_MICFIL_VERID:
1132 case REG_MICFIL_PARAM:
1133 if (micfil->soc->use_verid)
1134 return true;
1135 fallthrough;
1136 default:
1137 return false;
1138 }
1139 }
1140
fsl_micfil_writeable_reg(struct device * dev,unsigned int reg)1141 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
1142 {
1143 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1144
1145 switch (reg) {
1146 case REG_MICFIL_CTRL1:
1147 case REG_MICFIL_CTRL2:
1148 case REG_MICFIL_STAT: /* Write 1 to Clear */
1149 case REG_MICFIL_FIFO_CTRL:
1150 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
1151 case REG_MICFIL_DC_CTRL:
1152 case REG_MICFIL_OUT_CTRL:
1153 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
1154 case REG_MICFIL_VAD0_CTRL1:
1155 case REG_MICFIL_VAD0_CTRL2:
1156 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
1157 case REG_MICFIL_VAD0_SCONFIG:
1158 case REG_MICFIL_VAD0_NCONFIG:
1159 case REG_MICFIL_VAD0_ZCD:
1160 return true;
1161 case REG_MICFIL_FSYNC_CTRL:
1162 if (micfil->soc->use_verid)
1163 return true;
1164 fallthrough;
1165 default:
1166 return false;
1167 }
1168 }
1169
fsl_micfil_volatile_reg(struct device * dev,unsigned int reg)1170 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
1171 {
1172 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1173 int ofs = micfil->soc->fifo_offset;
1174
1175 if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs))
1176 return true;
1177
1178 switch (reg) {
1179 case REG_MICFIL_STAT:
1180 case REG_MICFIL_FIFO_STAT:
1181 case REG_MICFIL_OUT_STAT:
1182 case REG_MICFIL_VERID:
1183 case REG_MICFIL_PARAM:
1184 case REG_MICFIL_VAD0_STAT:
1185 case REG_MICFIL_VAD0_NDATA:
1186 return true;
1187 default:
1188 return false;
1189 }
1190 }
1191
1192 static const struct regmap_config fsl_micfil_regmap_config = {
1193 .reg_bits = 32,
1194 .reg_stride = 4,
1195 .val_bits = 32,
1196
1197 .max_register = REG_MICFIL_VAD0_ZCD,
1198 .reg_defaults = fsl_micfil_reg_defaults,
1199 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
1200 .readable_reg = fsl_micfil_readable_reg,
1201 .volatile_reg = fsl_micfil_volatile_reg,
1202 .writeable_reg = fsl_micfil_writeable_reg,
1203 .cache_type = REGCACHE_MAPLE,
1204 };
1205
1206 static const struct regmap_config fsl_micfil_regmap_config_v2 = {
1207 .reg_bits = 32,
1208 .reg_stride = 4,
1209 .val_bits = 32,
1210
1211 .max_register = REG_MICFIL_VAD0_ZCD,
1212 .reg_defaults = fsl_micfil_reg_defaults_v2,
1213 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults_v2),
1214 .readable_reg = fsl_micfil_readable_reg,
1215 .volatile_reg = fsl_micfil_volatile_reg,
1216 .writeable_reg = fsl_micfil_writeable_reg,
1217 .cache_type = REGCACHE_MAPLE,
1218 };
1219
1220 /* END OF REGMAP */
1221
micfil_isr(int irq,void * devid)1222 static irqreturn_t micfil_isr(int irq, void *devid)
1223 {
1224 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1225 struct platform_device *pdev = micfil->pdev;
1226 u32 stat_reg;
1227 u32 fifo_stat_reg;
1228 u32 ctrl1_reg;
1229 bool dma_enabled;
1230 int i;
1231
1232 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1233 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
1234 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
1235
1236 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
1237
1238 /* Channel 0-7 Output Data Flags */
1239 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
1240 if (stat_reg & MICFIL_STAT_CHXF(i))
1241 dev_dbg(&pdev->dev,
1242 "Data available in Data Channel %d\n", i);
1243 /* if DMA is not enabled, field must be written with 1
1244 * to clear
1245 */
1246 if (!dma_enabled)
1247 regmap_write_bits(micfil->regmap,
1248 REG_MICFIL_STAT,
1249 MICFIL_STAT_CHXF(i),
1250 MICFIL_STAT_CHXF(i));
1251 }
1252
1253 for (i = 0; i < MICFIL_FIFO_NUM; i++) {
1254 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
1255 dev_dbg(&pdev->dev,
1256 "FIFO Overflow Exception flag for channel %d\n",
1257 i);
1258
1259 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
1260 dev_dbg(&pdev->dev,
1261 "FIFO Underflow Exception flag for channel %d\n",
1262 i);
1263 }
1264
1265 return IRQ_HANDLED;
1266 }
1267
micfil_err_isr(int irq,void * devid)1268 static irqreturn_t micfil_err_isr(int irq, void *devid)
1269 {
1270 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1271 struct platform_device *pdev = micfil->pdev;
1272 u32 fifo_stat_reg;
1273 u32 out_stat_reg;
1274 u32 stat_reg;
1275
1276 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1277
1278 if (stat_reg & MICFIL_STAT_BSY_FIL)
1279 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
1280
1281 if (stat_reg & MICFIL_STAT_FIR_RDY)
1282 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
1283
1284 if (stat_reg & MICFIL_STAT_LOWFREQF) {
1285 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
1286 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
1287 MICFIL_STAT_LOWFREQF, MICFIL_STAT_LOWFREQF);
1288 }
1289
1290 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
1291 regmap_write_bits(micfil->regmap, REG_MICFIL_FIFO_STAT,
1292 fifo_stat_reg, fifo_stat_reg);
1293
1294 regmap_read(micfil->regmap, REG_MICFIL_OUT_STAT, &out_stat_reg);
1295 regmap_write_bits(micfil->regmap, REG_MICFIL_OUT_STAT,
1296 out_stat_reg, out_stat_reg);
1297
1298 return IRQ_HANDLED;
1299 }
1300
voice_detected_fn(int irq,void * devid)1301 static irqreturn_t voice_detected_fn(int irq, void *devid)
1302 {
1303 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1304 struct snd_kcontrol *kctl;
1305
1306 if (!micfil->card)
1307 return IRQ_HANDLED;
1308
1309 kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected");
1310 if (!kctl)
1311 return IRQ_HANDLED;
1312
1313 if (micfil->vad_detected)
1314 snd_ctl_notify(micfil->card->snd_card,
1315 SNDRV_CTL_EVENT_MASK_VALUE,
1316 &kctl->id);
1317
1318 return IRQ_HANDLED;
1319 }
1320
hwvad_isr(int irq,void * devid)1321 static irqreturn_t hwvad_isr(int irq, void *devid)
1322 {
1323 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1324 struct device *dev = &micfil->pdev->dev;
1325 u32 vad0_reg;
1326 int ret;
1327
1328 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1329
1330 /*
1331 * The only difference between MICFIL_VAD0_STAT_EF and
1332 * MICFIL_VAD0_STAT_IF is that the former requires Write
1333 * 1 to Clear. Since both flags are set, it is enough
1334 * to only read one of them
1335 */
1336 if (vad0_reg & MICFIL_VAD0_STAT_IF) {
1337 /* Write 1 to clear */
1338 regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT,
1339 MICFIL_VAD0_STAT_IF,
1340 MICFIL_VAD0_STAT_IF);
1341
1342 micfil->vad_detected = 1;
1343 }
1344
1345 ret = fsl_micfil_hwvad_disable(micfil);
1346 if (ret)
1347 dev_err(dev, "Failed to disable hwvad\n");
1348
1349 return IRQ_WAKE_THREAD;
1350 }
1351
hwvad_err_isr(int irq,void * devid)1352 static irqreturn_t hwvad_err_isr(int irq, void *devid)
1353 {
1354 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1355 struct device *dev = &micfil->pdev->dev;
1356 u32 vad0_reg;
1357
1358 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1359
1360 if (vad0_reg & MICFIL_VAD0_STAT_INSATF)
1361 dev_dbg(dev, "voice activity input overflow/underflow detected\n");
1362
1363 return IRQ_HANDLED;
1364 }
1365
1366 static int fsl_micfil_runtime_suspend(struct device *dev);
1367 static int fsl_micfil_runtime_resume(struct device *dev);
1368
fsl_micfil_probe(struct platform_device * pdev)1369 static int fsl_micfil_probe(struct platform_device *pdev)
1370 {
1371 struct device_node *np = pdev->dev.of_node;
1372 struct fsl_micfil *micfil;
1373 struct resource *res;
1374 void __iomem *regs;
1375 int ret, i;
1376
1377 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
1378 if (!micfil)
1379 return -ENOMEM;
1380
1381 micfil->pdev = pdev;
1382 strscpy(micfil->name, np->name, sizeof(micfil->name));
1383
1384 micfil->soc = of_device_get_match_data(&pdev->dev);
1385
1386 /* ipg_clk is used to control the registers
1387 * ipg_clk_app is used to operate the filter
1388 */
1389 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
1390 if (IS_ERR(micfil->mclk)) {
1391 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
1392 PTR_ERR(micfil->mclk));
1393 return PTR_ERR(micfil->mclk);
1394 }
1395
1396 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
1397 if (IS_ERR(micfil->busclk)) {
1398 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
1399 PTR_ERR(micfil->busclk));
1400 return PTR_ERR(micfil->busclk);
1401 }
1402
1403 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk,
1404 &micfil->pll11k_clk);
1405
1406 micfil->clk_src[MICFIL_AUDIO_PLL1] = micfil->pll8k_clk;
1407 micfil->clk_src[MICFIL_AUDIO_PLL2] = micfil->pll11k_clk;
1408 micfil->clk_src[MICFIL_CLK_EXT3] = devm_clk_get(&pdev->dev, "clkext3");
1409 if (IS_ERR(micfil->clk_src[MICFIL_CLK_EXT3]))
1410 micfil->clk_src[MICFIL_CLK_EXT3] = NULL;
1411
1412 fsl_asoc_constrain_rates(&micfil->constraint_rates,
1413 &fsl_micfil_rate_constraints,
1414 micfil->clk_src[MICFIL_AUDIO_PLL1],
1415 micfil->clk_src[MICFIL_AUDIO_PLL2],
1416 micfil->clk_src[MICFIL_CLK_EXT3],
1417 micfil->constraint_rates_list);
1418
1419 /* init regmap */
1420 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1421 if (IS_ERR(regs))
1422 return PTR_ERR(regs);
1423
1424 if (of_device_is_compatible(np, "fsl,imx943-micfil"))
1425 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1426 regs,
1427 &fsl_micfil_regmap_config_v2);
1428 else
1429 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1430 regs,
1431 &fsl_micfil_regmap_config);
1432 if (IS_ERR(micfil->regmap)) {
1433 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
1434 PTR_ERR(micfil->regmap));
1435 return PTR_ERR(micfil->regmap);
1436 }
1437
1438 /* dataline mask for RX */
1439 ret = of_property_read_u32_index(np,
1440 "fsl,dataline",
1441 0,
1442 &micfil->dataline);
1443 if (ret)
1444 micfil->dataline = 1;
1445
1446 if (micfil->dataline & ~micfil->soc->dataline) {
1447 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
1448 micfil->soc->dataline);
1449 return -EINVAL;
1450 }
1451
1452 /* get IRQs */
1453 for (i = 0; i < MICFIL_IRQ_LINES; i++) {
1454 micfil->irq[i] = platform_get_irq(pdev, i);
1455 if (micfil->irq[i] < 0)
1456 return micfil->irq[i];
1457 }
1458
1459 /* Digital Microphone interface interrupt */
1460 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
1461 micfil_isr, IRQF_SHARED,
1462 micfil->name, micfil);
1463 if (ret) {
1464 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
1465 micfil->irq[0]);
1466 return ret;
1467 }
1468
1469 /* Digital Microphone interface error interrupt */
1470 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
1471 micfil_err_isr, IRQF_SHARED,
1472 micfil->name, micfil);
1473 if (ret) {
1474 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
1475 micfil->irq[1]);
1476 return ret;
1477 }
1478
1479 /* Digital Microphone interface voice activity detector event */
1480 ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2],
1481 hwvad_isr, voice_detected_fn,
1482 IRQF_SHARED, micfil->name, micfil);
1483 if (ret) {
1484 dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n",
1485 micfil->irq[0]);
1486 return ret;
1487 }
1488
1489 /* Digital Microphone interface voice activity detector error */
1490 ret = devm_request_irq(&pdev->dev, micfil->irq[3],
1491 hwvad_err_isr, IRQF_SHARED,
1492 micfil->name, micfil);
1493 if (ret) {
1494 dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n",
1495 micfil->irq[1]);
1496 return ret;
1497 }
1498
1499 micfil->dma_params_rx.chan_name = "rx";
1500 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0 + micfil->soc->fifo_offset;
1501 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
1502
1503 platform_set_drvdata(pdev, micfil);
1504
1505 pm_runtime_enable(&pdev->dev);
1506 if (!pm_runtime_enabled(&pdev->dev)) {
1507 ret = fsl_micfil_runtime_resume(&pdev->dev);
1508 if (ret)
1509 goto err_pm_disable;
1510 }
1511
1512 ret = pm_runtime_resume_and_get(&pdev->dev);
1513 if (ret < 0)
1514 goto err_pm_get_sync;
1515
1516 /* Get micfil version */
1517 ret = fsl_micfil_use_verid(&pdev->dev);
1518 if (ret < 0)
1519 dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret);
1520
1521 ret = pm_runtime_put_sync(&pdev->dev);
1522 if (ret < 0 && ret != -ENOSYS)
1523 goto err_pm_get_sync;
1524
1525 regcache_cache_only(micfil->regmap, true);
1526
1527 /*
1528 * Register platform component before registering cpu dai for there
1529 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1530 */
1531 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1532 if (ret) {
1533 dev_err(&pdev->dev, "failed to pcm register\n");
1534 goto err_pm_disable;
1535 }
1536
1537 fsl_micfil_dai.capture.formats = micfil->soc->formats;
1538
1539 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
1540 &fsl_micfil_dai, 1);
1541 if (ret) {
1542 dev_err(&pdev->dev, "failed to register component %s\n",
1543 fsl_micfil_component.name);
1544 goto err_pm_disable;
1545 }
1546
1547 return ret;
1548
1549 err_pm_get_sync:
1550 if (!pm_runtime_status_suspended(&pdev->dev))
1551 fsl_micfil_runtime_suspend(&pdev->dev);
1552 err_pm_disable:
1553 pm_runtime_disable(&pdev->dev);
1554
1555 return ret;
1556 }
1557
fsl_micfil_remove(struct platform_device * pdev)1558 static void fsl_micfil_remove(struct platform_device *pdev)
1559 {
1560 pm_runtime_disable(&pdev->dev);
1561 }
1562
fsl_micfil_runtime_suspend(struct device * dev)1563 static int fsl_micfil_runtime_suspend(struct device *dev)
1564 {
1565 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1566
1567 regcache_cache_only(micfil->regmap, true);
1568
1569 if (micfil->mclk_flag)
1570 clk_disable_unprepare(micfil->mclk);
1571 clk_disable_unprepare(micfil->busclk);
1572
1573 return 0;
1574 }
1575
fsl_micfil_runtime_resume(struct device * dev)1576 static int fsl_micfil_runtime_resume(struct device *dev)
1577 {
1578 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1579 int ret;
1580
1581 ret = clk_prepare_enable(micfil->busclk);
1582 if (ret < 0)
1583 return ret;
1584
1585 if (micfil->mclk_flag) {
1586 ret = clk_prepare_enable(micfil->mclk);
1587 if (ret < 0) {
1588 clk_disable_unprepare(micfil->busclk);
1589 return ret;
1590 }
1591 }
1592
1593 regcache_cache_only(micfil->regmap, false);
1594 regcache_mark_dirty(micfil->regmap);
1595 regcache_sync(micfil->regmap);
1596
1597 return 0;
1598 }
1599
1600 static const struct dev_pm_ops fsl_micfil_pm_ops = {
1601 RUNTIME_PM_OPS(fsl_micfil_runtime_suspend, fsl_micfil_runtime_resume, NULL)
1602 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1603 };
1604
1605 static struct platform_driver fsl_micfil_driver = {
1606 .probe = fsl_micfil_probe,
1607 .remove = fsl_micfil_remove,
1608 .driver = {
1609 .name = "fsl-micfil-dai",
1610 .pm = pm_ptr(&fsl_micfil_pm_ops),
1611 .of_match_table = fsl_micfil_dt_ids,
1612 },
1613 };
1614 module_platform_driver(fsl_micfil_driver);
1615
1616 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
1617 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
1618 MODULE_LICENSE("Dual BSD/GPL");
1619