1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale DMA ALSA SoC PCM driver 4 // 5 // Author: Timur Tabi <timur@freescale.com> 6 // 7 // Copyright 2007-2010 Freescale Semiconductor, Inc. 8 // 9 // This driver implements ASoC support for the Elo DMA controller, which is 10 // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 11 // the PCM driver is what handles the DMA buffer. 12 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/platform_device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/interrupt.h> 18 #include <linux/delay.h> 19 #include <linux/gfp.h> 20 #include <linux/of_address.h> 21 #include <linux/list.h> 22 #include <linux/slab.h> 23 24 #include <sound/core.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 29 #include <asm/io.h> 30 31 #include "fsl_dma.h" 32 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */ 33 34 #define DRV_NAME "fsl_dma" 35 36 /* 37 * The formats that the DMA controller supports, which is anything 38 * that is 8, 16, or 32 bits. 39 */ 40 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 41 SNDRV_PCM_FMTBIT_U8 | \ 42 SNDRV_PCM_FMTBIT_S16_LE | \ 43 SNDRV_PCM_FMTBIT_S16_BE | \ 44 SNDRV_PCM_FMTBIT_U16_LE | \ 45 SNDRV_PCM_FMTBIT_U16_BE | \ 46 SNDRV_PCM_FMTBIT_S24_LE | \ 47 SNDRV_PCM_FMTBIT_S24_BE | \ 48 SNDRV_PCM_FMTBIT_U24_LE | \ 49 SNDRV_PCM_FMTBIT_U24_BE | \ 50 SNDRV_PCM_FMTBIT_S32_LE | \ 51 SNDRV_PCM_FMTBIT_S32_BE | \ 52 SNDRV_PCM_FMTBIT_U32_LE | \ 53 SNDRV_PCM_FMTBIT_U32_BE) 54 struct dma_object { 55 struct snd_soc_component_driver dai; 56 dma_addr_t ssi_stx_phys; 57 dma_addr_t ssi_srx_phys; 58 unsigned int ssi_fifo_depth; 59 struct ccsr_dma_channel __iomem *channel; 60 unsigned int irq; 61 bool assigned; 62 }; 63 64 /* 65 * The number of DMA links to use. Two is the bare minimum, but if you 66 * have really small links you might need more. 67 */ 68 #define NUM_DMA_LINKS 2 69 70 /** fsl_dma_private: p-substream DMA data 71 * 72 * Each substream has a 1-to-1 association with a DMA channel. 73 * 74 * The link[] array is first because it needs to be aligned on a 32-byte 75 * boundary, so putting it first will ensure alignment without padding the 76 * structure. 77 * 78 * @link[]: array of link descriptors 79 * @dma_channel: pointer to the DMA channel's registers 80 * @irq: IRQ for this DMA channel 81 * @substream: pointer to the substream object, needed by the ISR 82 * @ssi_sxx_phys: bus address of the STX or SRX register to use 83 * @ld_buf_phys: physical address of the LD buffer 84 * @current_link: index into link[] of the link currently being processed 85 * @dma_buf_phys: physical address of the DMA buffer 86 * @dma_buf_next: physical address of the next period to process 87 * @dma_buf_end: physical address of the byte after the end of the DMA 88 * @buffer period_size: the size of a single period 89 * @num_periods: the number of periods in the DMA buffer 90 */ 91 struct fsl_dma_private { 92 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 93 struct ccsr_dma_channel __iomem *dma_channel; 94 unsigned int irq; 95 struct snd_pcm_substream *substream; 96 dma_addr_t ssi_sxx_phys; 97 unsigned int ssi_fifo_depth; 98 dma_addr_t ld_buf_phys; 99 unsigned int current_link; 100 dma_addr_t dma_buf_phys; 101 dma_addr_t dma_buf_next; 102 dma_addr_t dma_buf_end; 103 size_t period_size; 104 unsigned int num_periods; 105 }; 106 107 /** 108 * fsl_dma_hardare: define characteristics of the PCM hardware. 109 * 110 * The PCM hardware is the Freescale DMA controller. This structure defines 111 * the capabilities of that hardware. 112 * 113 * Since the sampling rate and data format are not controlled by the DMA 114 * controller, we specify no limits for those values. The only exception is 115 * period_bytes_min, which is set to a reasonably low value to prevent the 116 * DMA controller from generating too many interrupts per second. 117 * 118 * Since each link descriptor has a 32-bit byte count field, we set 119 * period_bytes_max to the largest 32-bit number. We also have no maximum 120 * number of periods. 121 * 122 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 123 * limitation in the SSI driver requires the sample rates for playback and 124 * capture to be the same. 125 */ 126 static const struct snd_pcm_hardware fsl_dma_hardware = { 127 128 .info = SNDRV_PCM_INFO_INTERLEAVED | 129 SNDRV_PCM_INFO_MMAP | 130 SNDRV_PCM_INFO_MMAP_VALID | 131 SNDRV_PCM_INFO_JOINT_DUPLEX | 132 SNDRV_PCM_INFO_PAUSE, 133 .formats = FSLDMA_PCM_FORMATS, 134 .period_bytes_min = 512, /* A reasonable limit */ 135 .period_bytes_max = (u32) -1, 136 .periods_min = NUM_DMA_LINKS, 137 .periods_max = (unsigned int) -1, 138 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 139 }; 140 141 /** 142 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 143 * 144 * This function should be called by the ISR whenever the DMA controller 145 * halts data transfer. 146 */ 147 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 148 { 149 snd_pcm_stop_xrun(substream); 150 } 151 152 /** 153 * fsl_dma_update_pointers - update LD pointers to point to the next period 154 * 155 * As each period is completed, this function changes the link 156 * descriptor pointers for that period to point to the next period. 157 */ 158 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 159 { 160 struct fsl_dma_link_descriptor *link = 161 &dma_private->link[dma_private->current_link]; 162 163 /* Update our link descriptors to point to the next period. On a 36-bit 164 * system, we also need to update the ESAD bits. We also set (keep) the 165 * snoop bits. See the comments in fsl_dma_hw_params() about snooping. 166 */ 167 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 168 link->source_addr = cpu_to_be32(dma_private->dma_buf_next); 169 #ifdef CONFIG_PHYS_64BIT 170 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 171 upper_32_bits(dma_private->dma_buf_next)); 172 #endif 173 } else { 174 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next); 175 #ifdef CONFIG_PHYS_64BIT 176 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 177 upper_32_bits(dma_private->dma_buf_next)); 178 #endif 179 } 180 181 /* Update our variables for next time */ 182 dma_private->dma_buf_next += dma_private->period_size; 183 184 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 185 dma_private->dma_buf_next = dma_private->dma_buf_phys; 186 187 if (++dma_private->current_link >= NUM_DMA_LINKS) 188 dma_private->current_link = 0; 189 } 190 191 /** 192 * fsl_dma_isr: interrupt handler for the DMA controller 193 * 194 * @irq: IRQ of the DMA channel 195 * @dev_id: pointer to the dma_private structure for this DMA channel 196 */ 197 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 198 { 199 struct fsl_dma_private *dma_private = dev_id; 200 struct snd_pcm_substream *substream = dma_private->substream; 201 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 202 struct device *dev = rtd->dev; 203 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 204 irqreturn_t ret = IRQ_NONE; 205 u32 sr, sr2 = 0; 206 207 /* We got an interrupt, so read the status register to see what we 208 were interrupted for. 209 */ 210 sr = in_be32(&dma_channel->sr); 211 212 if (sr & CCSR_DMA_SR_TE) { 213 dev_err(dev, "dma transmit error\n"); 214 fsl_dma_abort_stream(substream); 215 sr2 |= CCSR_DMA_SR_TE; 216 ret = IRQ_HANDLED; 217 } 218 219 if (sr & CCSR_DMA_SR_CH) 220 ret = IRQ_HANDLED; 221 222 if (sr & CCSR_DMA_SR_PE) { 223 dev_err(dev, "dma programming error\n"); 224 fsl_dma_abort_stream(substream); 225 sr2 |= CCSR_DMA_SR_PE; 226 ret = IRQ_HANDLED; 227 } 228 229 if (sr & CCSR_DMA_SR_EOLNI) { 230 sr2 |= CCSR_DMA_SR_EOLNI; 231 ret = IRQ_HANDLED; 232 } 233 234 if (sr & CCSR_DMA_SR_CB) 235 ret = IRQ_HANDLED; 236 237 if (sr & CCSR_DMA_SR_EOSI) { 238 /* Tell ALSA we completed a period. */ 239 snd_pcm_period_elapsed(substream); 240 241 /* 242 * Update our link descriptors to point to the next period. We 243 * only need to do this if the number of periods is not equal to 244 * the number of links. 245 */ 246 if (dma_private->num_periods != NUM_DMA_LINKS) 247 fsl_dma_update_pointers(dma_private); 248 249 sr2 |= CCSR_DMA_SR_EOSI; 250 ret = IRQ_HANDLED; 251 } 252 253 if (sr & CCSR_DMA_SR_EOLSI) { 254 sr2 |= CCSR_DMA_SR_EOLSI; 255 ret = IRQ_HANDLED; 256 } 257 258 /* Clear the bits that we set */ 259 if (sr2) 260 out_be32(&dma_channel->sr, sr2); 261 262 return ret; 263 } 264 265 /** 266 * fsl_dma_new: initialize this PCM driver. 267 * 268 * This function is called by soc_new_pcm(), once for each DAI link 269 * in the machine driver's snd_soc_card structure. 270 * 271 * Regardless of where the memory is actually allocated, since the device can 272 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36. 273 */ 274 static int fsl_dma_new(struct snd_soc_component *component, 275 struct snd_soc_pcm_runtime *rtd) 276 { 277 struct snd_card *card = rtd->card->snd_card; 278 struct snd_pcm *pcm = rtd->pcm; 279 int ret; 280 281 ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36)); 282 if (ret) 283 return ret; 284 285 return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 286 card->dev, 287 fsl_dma_hardware.buffer_bytes_max); 288 } 289 290 /** 291 * fsl_dma_open: open a new substream. 292 * 293 * Each substream has its own DMA buffer. 294 * 295 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 296 * descriptors that ping-pong from one period to the next. For example, if 297 * there are six periods and two link descriptors, this is how they look 298 * before playback starts: 299 * 300 * The last link descriptor 301 * ____________ points back to the first 302 * | | 303 * V | 304 * ___ ___ | 305 * | |->| |->| 306 * |___| |___| 307 * | | 308 * | | 309 * V V 310 * _________________________________________ 311 * | | | | | | | The DMA buffer is 312 * | | | | | | | divided into 6 parts 313 * |______|______|______|______|______|______| 314 * 315 * and here's how they look after the first period is finished playing: 316 * 317 * ____________ 318 * | | 319 * V | 320 * ___ ___ | 321 * | |->| |->| 322 * |___| |___| 323 * | | 324 * |______________ 325 * | | 326 * V V 327 * _________________________________________ 328 * | | | | | | | 329 * | | | | | | | 330 * |______|______|______|______|______|______| 331 * 332 * The first link descriptor now points to the third period. The DMA 333 * controller is currently playing the second period. When it finishes, it 334 * will jump back to the first descriptor and play the third period. 335 * 336 * There are four reasons we do this: 337 * 338 * 1. The only way to get the DMA controller to automatically restart the 339 * transfer when it gets to the end of the buffer is to use chaining 340 * mode. Basic direct mode doesn't offer that feature. 341 * 2. We need to receive an interrupt at the end of every period. The DMA 342 * controller can generate an interrupt at the end of every link transfer 343 * (aka segment). Making each period into a DMA segment will give us the 344 * interrupts we need. 345 * 3. By creating only two link descriptors, regardless of the number of 346 * periods, we do not need to reallocate the link descriptors if the 347 * number of periods changes. 348 * 4. All of the audio data is still stored in a single, contiguous DMA 349 * buffer, which is what ALSA expects. We're just dividing it into 350 * contiguous parts, and creating a link descriptor for each one. 351 */ 352 static int fsl_dma_open(struct snd_soc_component *component, 353 struct snd_pcm_substream *substream) 354 { 355 struct snd_pcm_runtime *runtime = substream->runtime; 356 struct device *dev = component->dev; 357 struct dma_object *dma = 358 container_of(component->driver, struct dma_object, dai); 359 struct fsl_dma_private *dma_private; 360 struct ccsr_dma_channel __iomem *dma_channel; 361 dma_addr_t ld_buf_phys; 362 u64 temp_link; /* Pointer to next link descriptor */ 363 u32 mr; 364 int ret = 0; 365 unsigned int i; 366 367 /* 368 * Reject any DMA buffer whose size is not a multiple of the period 369 * size. We need to make sure that the DMA buffer can be evenly divided 370 * into periods. 371 */ 372 ret = snd_pcm_hw_constraint_integer(runtime, 373 SNDRV_PCM_HW_PARAM_PERIODS); 374 if (ret < 0) { 375 dev_err(dev, "invalid buffer size\n"); 376 return ret; 377 } 378 379 if (dma->assigned) { 380 dev_err(dev, "dma channel already assigned\n"); 381 return -EBUSY; 382 } 383 384 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private), 385 &ld_buf_phys, GFP_KERNEL); 386 if (!dma_private) { 387 dev_err(dev, "can't allocate dma private data\n"); 388 return -ENOMEM; 389 } 390 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 391 dma_private->ssi_sxx_phys = dma->ssi_stx_phys; 392 else 393 dma_private->ssi_sxx_phys = dma->ssi_srx_phys; 394 395 dma_private->ssi_fifo_depth = dma->ssi_fifo_depth; 396 dma_private->dma_channel = dma->channel; 397 dma_private->irq = dma->irq; 398 dma_private->substream = substream; 399 dma_private->ld_buf_phys = ld_buf_phys; 400 dma_private->dma_buf_phys = substream->dma_buffer.addr; 401 402 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio", 403 dma_private); 404 if (ret) { 405 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 406 dma_private->irq, ret); 407 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 408 dma_private, dma_private->ld_buf_phys); 409 return ret; 410 } 411 412 dma->assigned = true; 413 414 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 415 runtime->private_data = dma_private; 416 417 /* Program the fixed DMA controller parameters */ 418 419 dma_channel = dma_private->dma_channel; 420 421 temp_link = dma_private->ld_buf_phys + 422 sizeof(struct fsl_dma_link_descriptor); 423 424 for (i = 0; i < NUM_DMA_LINKS; i++) { 425 dma_private->link[i].next = cpu_to_be64(temp_link); 426 427 temp_link += sizeof(struct fsl_dma_link_descriptor); 428 } 429 /* The last link descriptor points to the first */ 430 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 431 432 /* Tell the DMA controller where the first link descriptor is */ 433 out_be32(&dma_channel->clndar, 434 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 435 out_be32(&dma_channel->eclndar, 436 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 437 438 /* The manual says the BCR must be clear before enabling EMP */ 439 out_be32(&dma_channel->bcr, 0); 440 441 /* 442 * Program the mode register for interrupts, external master control, 443 * and source/destination hold. Also clear the Channel Abort bit. 444 */ 445 mr = in_be32(&dma_channel->mr) & 446 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 447 448 /* 449 * We want External Master Start and External Master Pause enabled, 450 * because the SSI is controlling the DMA controller. We want the DMA 451 * controller to be set up in advance, and then we signal only the SSI 452 * to start transferring. 453 * 454 * We want End-Of-Segment Interrupts enabled, because this will generate 455 * an interrupt at the end of each segment (each link descriptor 456 * represents one segment). Each DMA segment is the same thing as an 457 * ALSA period, so this is how we get an interrupt at the end of every 458 * period. 459 * 460 * We want Error Interrupt enabled, so that we can get an error if 461 * the DMA controller is mis-programmed somehow. 462 */ 463 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 464 CCSR_DMA_MR_EMS_EN; 465 466 /* For playback, we want the destination address to be held. For 467 capture, set the source address to be held. */ 468 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 469 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 470 471 out_be32(&dma_channel->mr, mr); 472 473 return 0; 474 } 475 476 /** 477 * fsl_dma_hw_params: continue initializing the DMA links 478 * 479 * This function obtains hardware parameters about the opened stream and 480 * programs the DMA controller accordingly. 481 * 482 * One drawback of big-endian is that when copying integers of different 483 * sizes to a fixed-sized register, the address to which the integer must be 484 * copied is dependent on the size of the integer. 485 * 486 * For example, if P is the address of a 32-bit register, and X is a 32-bit 487 * integer, then X should be copied to address P. However, if X is a 16-bit 488 * integer, then it should be copied to P+2. If X is an 8-bit register, 489 * then it should be copied to P+3. 490 * 491 * So for playback of 8-bit samples, the DMA controller must transfer single 492 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 493 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 494 * 495 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 496 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 497 * and 8 bytes at a time). So we do not support packed 24-bit samples. 498 * 24-bit data must be padded to 32 bits. 499 */ 500 static int fsl_dma_hw_params(struct snd_soc_component *component, 501 struct snd_pcm_substream *substream, 502 struct snd_pcm_hw_params *hw_params) 503 { 504 struct snd_pcm_runtime *runtime = substream->runtime; 505 struct fsl_dma_private *dma_private = runtime->private_data; 506 struct device *dev = component->dev; 507 508 /* Number of bits per sample */ 509 unsigned int sample_bits = 510 snd_pcm_format_physical_width(params_format(hw_params)); 511 512 /* Number of bytes per frame */ 513 unsigned int sample_bytes = sample_bits / 8; 514 515 /* Bus address of SSI STX register */ 516 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 517 518 /* Size of the DMA buffer, in bytes */ 519 size_t buffer_size = params_buffer_bytes(hw_params); 520 521 /* Number of bytes per period */ 522 size_t period_size = params_period_bytes(hw_params); 523 524 /* Pointer to next period */ 525 dma_addr_t temp_addr = substream->dma_buffer.addr; 526 527 /* Pointer to DMA controller */ 528 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 529 530 u32 mr; /* DMA Mode Register */ 531 532 unsigned int i; 533 534 /* Initialize our DMA tracking variables */ 535 dma_private->period_size = period_size; 536 dma_private->num_periods = params_periods(hw_params); 537 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 538 dma_private->dma_buf_next = dma_private->dma_buf_phys + 539 (NUM_DMA_LINKS * period_size); 540 541 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 542 /* This happens if the number of periods == NUM_DMA_LINKS */ 543 dma_private->dma_buf_next = dma_private->dma_buf_phys; 544 545 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 546 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 547 548 /* Due to a quirk of the SSI's STX register, the target address 549 * for the DMA operations depends on the sample size. So we calculate 550 * that offset here. While we're at it, also tell the DMA controller 551 * how much data to transfer per sample. 552 */ 553 switch (sample_bits) { 554 case 8: 555 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 556 ssi_sxx_phys += 3; 557 break; 558 case 16: 559 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 560 ssi_sxx_phys += 2; 561 break; 562 case 32: 563 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 564 break; 565 default: 566 /* We should never get here */ 567 dev_err(dev, "unsupported sample size %u\n", sample_bits); 568 return -EINVAL; 569 } 570 571 /* 572 * BWC determines how many bytes are sent/received before the DMA 573 * controller checks the SSI to see if it needs to stop. BWC should 574 * always be a multiple of the frame size, so that we always transmit 575 * whole frames. Each frame occupies two slots in the FIFO. The 576 * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two 577 * (MR[BWC] can only represent even powers of two). 578 * 579 * To simplify the process, we set BWC to the largest value that is 580 * less than or equal to the FIFO watermark. For playback, this ensures 581 * that we transfer the maximum amount without overrunning the FIFO. 582 * For capture, this ensures that we transfer the maximum amount without 583 * underrunning the FIFO. 584 * 585 * f = SSI FIFO depth 586 * w = SSI watermark value (which equals f - 2) 587 * b = DMA bandwidth count (in bytes) 588 * s = sample size (in bytes, which equals frame_size * 2) 589 * 590 * For playback, we never transmit more than the transmit FIFO 591 * watermark, otherwise we might write more data than the FIFO can hold. 592 * The watermark is equal to the FIFO depth minus two. 593 * 594 * For capture, two equations must hold: 595 * w > f - (b / s) 596 * w >= b / s 597 * 598 * So, b > 2 * s, but b must also be <= s * w. To simplify, we set 599 * b = s * w, which is equal to 600 * (dma_private->ssi_fifo_depth - 2) * sample_bytes. 601 */ 602 mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes); 603 604 out_be32(&dma_channel->mr, mr); 605 606 for (i = 0; i < NUM_DMA_LINKS; i++) { 607 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 608 609 link->count = cpu_to_be32(period_size); 610 611 /* The snoop bit tells the DMA controller whether it should tell 612 * the ECM to snoop during a read or write to an address. For 613 * audio, we use DMA to transfer data between memory and an I/O 614 * device (the SSI's STX0 or SRX0 register). Snooping is only 615 * needed if there is a cache, so we need to snoop memory 616 * addresses only. For playback, that means we snoop the source 617 * but not the destination. For capture, we snoop the 618 * destination but not the source. 619 * 620 * Note that failing to snoop properly is unlikely to cause 621 * cache incoherency if the period size is larger than the 622 * size of L1 cache. This is because filling in one period will 623 * flush out the data for the previous period. So if you 624 * increased period_bytes_min to a large enough size, you might 625 * get more performance by not snooping, and you'll still be 626 * okay. You'll need to update fsl_dma_update_pointers() also. 627 */ 628 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 629 link->source_addr = cpu_to_be32(temp_addr); 630 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 631 upper_32_bits(temp_addr)); 632 633 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 634 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 635 upper_32_bits(ssi_sxx_phys)); 636 } else { 637 link->source_addr = cpu_to_be32(ssi_sxx_phys); 638 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 639 upper_32_bits(ssi_sxx_phys)); 640 641 link->dest_addr = cpu_to_be32(temp_addr); 642 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 643 upper_32_bits(temp_addr)); 644 } 645 646 temp_addr += period_size; 647 } 648 649 return 0; 650 } 651 652 /** 653 * fsl_dma_pointer: determine the current position of the DMA transfer 654 * 655 * This function is called by ALSA when ALSA wants to know where in the 656 * stream buffer the hardware currently is. 657 * 658 * For playback, the SAR register contains the physical address of the most 659 * recent DMA transfer. For capture, the value is in the DAR register. 660 * 661 * The base address of the buffer is stored in the source_addr field of the 662 * first link descriptor. 663 */ 664 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_soc_component *component, 665 struct snd_pcm_substream *substream) 666 { 667 struct snd_pcm_runtime *runtime = substream->runtime; 668 struct fsl_dma_private *dma_private = runtime->private_data; 669 struct device *dev = component->dev; 670 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 671 dma_addr_t position; 672 snd_pcm_uframes_t frames; 673 674 /* Obtain the current DMA pointer, but don't read the ESAD bits if we 675 * only have 32-bit DMA addresses. This function is typically called 676 * in interrupt context, so we need to optimize it. 677 */ 678 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 679 position = in_be32(&dma_channel->sar); 680 #ifdef CONFIG_PHYS_64BIT 681 position |= (u64)(in_be32(&dma_channel->satr) & 682 CCSR_DMA_ATR_ESAD_MASK) << 32; 683 #endif 684 } else { 685 position = in_be32(&dma_channel->dar); 686 #ifdef CONFIG_PHYS_64BIT 687 position |= (u64)(in_be32(&dma_channel->datr) & 688 CCSR_DMA_ATR_ESAD_MASK) << 32; 689 #endif 690 } 691 692 /* 693 * When capture is started, the SSI immediately starts to fill its FIFO. 694 * This means that the DMA controller is not started until the FIFO is 695 * full. However, ALSA calls this function before that happens, when 696 * MR.DAR is still zero. In this case, just return zero to indicate 697 * that nothing has been received yet. 698 */ 699 if (!position) 700 return 0; 701 702 if ((position < dma_private->dma_buf_phys) || 703 (position > dma_private->dma_buf_end)) { 704 dev_err(dev, "dma pointer is out of range, halting stream\n"); 705 return SNDRV_PCM_POS_XRUN; 706 } 707 708 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 709 710 /* 711 * If the current address is just past the end of the buffer, wrap it 712 * around. 713 */ 714 if (frames == runtime->buffer_size) 715 frames = 0; 716 717 return frames; 718 } 719 720 /** 721 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 722 * 723 * Release the resources allocated in fsl_dma_hw_params() and de-program the 724 * registers. 725 * 726 * This function can be called multiple times. 727 */ 728 static int fsl_dma_hw_free(struct snd_soc_component *component, 729 struct snd_pcm_substream *substream) 730 { 731 struct snd_pcm_runtime *runtime = substream->runtime; 732 struct fsl_dma_private *dma_private = runtime->private_data; 733 734 if (dma_private) { 735 struct ccsr_dma_channel __iomem *dma_channel; 736 737 dma_channel = dma_private->dma_channel; 738 739 /* Stop the DMA */ 740 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 741 out_be32(&dma_channel->mr, 0); 742 743 /* Reset all the other registers */ 744 out_be32(&dma_channel->sr, -1); 745 out_be32(&dma_channel->clndar, 0); 746 out_be32(&dma_channel->eclndar, 0); 747 out_be32(&dma_channel->satr, 0); 748 out_be32(&dma_channel->sar, 0); 749 out_be32(&dma_channel->datr, 0); 750 out_be32(&dma_channel->dar, 0); 751 out_be32(&dma_channel->bcr, 0); 752 out_be32(&dma_channel->nlndar, 0); 753 out_be32(&dma_channel->enlndar, 0); 754 } 755 756 return 0; 757 } 758 759 /** 760 * fsl_dma_close: close the stream. 761 */ 762 static int fsl_dma_close(struct snd_soc_component *component, 763 struct snd_pcm_substream *substream) 764 { 765 struct snd_pcm_runtime *runtime = substream->runtime; 766 struct fsl_dma_private *dma_private = runtime->private_data; 767 struct device *dev = component->dev; 768 struct dma_object *dma = 769 container_of(component->driver, struct dma_object, dai); 770 771 if (dma_private) { 772 if (dma_private->irq) 773 free_irq(dma_private->irq, dma_private); 774 775 /* Deallocate the fsl_dma_private structure */ 776 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 777 dma_private, dma_private->ld_buf_phys); 778 substream->runtime->private_data = NULL; 779 } 780 781 dma->assigned = false; 782 783 return 0; 784 } 785 786 /** 787 * find_ssi_node -- returns the SSI node that points to its DMA channel node 788 * 789 * Although this DMA driver attempts to operate independently of the other 790 * devices, it still needs to determine some information about the SSI device 791 * that it's working with. Unfortunately, the device tree does not contain 792 * a pointer from the DMA channel node to the SSI node -- the pointer goes the 793 * other way. So we need to scan the device tree for SSI nodes until we find 794 * the one that points to the given DMA channel node. It's ugly, but at least 795 * it's contained in this one function. 796 */ 797 static struct device_node *find_ssi_node(struct device_node *dma_channel_np) 798 { 799 struct device_node *ssi_np, *np; 800 801 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") { 802 /* Check each DMA phandle to see if it points to us. We 803 * assume that device_node pointers are a valid comparison. 804 */ 805 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0); 806 of_node_put(np); 807 if (np == dma_channel_np) 808 return ssi_np; 809 810 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0); 811 of_node_put(np); 812 if (np == dma_channel_np) 813 return ssi_np; 814 } 815 816 return NULL; 817 } 818 819 static int fsl_soc_dma_probe(struct platform_device *pdev) 820 { 821 struct dma_object *dma; 822 struct device_node *np = pdev->dev.of_node; 823 struct device_node *ssi_np; 824 struct resource res; 825 void __iomem *channel; 826 const uint32_t *iprop; 827 int irq; 828 int ret; 829 830 channel = devm_platform_ioremap_resource(pdev, 0); 831 if (IS_ERR(channel)) 832 return PTR_ERR(channel); 833 834 irq = platform_get_irq(pdev, 0); 835 if (irq < 0) 836 return irq; 837 838 dma = devm_kzalloc(&pdev->dev, sizeof(*dma), GFP_KERNEL); 839 if (!dma) 840 return -ENOMEM; 841 842 dma->dai.name = DRV_NAME; 843 dma->dai.open = fsl_dma_open; 844 dma->dai.close = fsl_dma_close; 845 dma->dai.hw_params = fsl_dma_hw_params; 846 dma->dai.hw_free = fsl_dma_hw_free; 847 dma->dai.pointer = fsl_dma_pointer; 848 dma->dai.pcm_new = fsl_dma_new; 849 850 dma->channel = channel; 851 dma->irq = irq; 852 853 /* Find the SSI node that points to us. */ 854 ssi_np = find_ssi_node(np); 855 if (!ssi_np) { 856 dev_err(&pdev->dev, "cannot find parent SSI node\n"); 857 return -ENODEV; 858 } 859 860 ret = of_address_to_resource(ssi_np, 0, &res); 861 if (ret) { 862 dev_err(&pdev->dev, "could not determine resources for %pOF\n", 863 ssi_np); 864 of_node_put(ssi_np); 865 return ret; 866 } 867 868 /* Store the SSI-specific information that we need */ 869 dma->ssi_stx_phys = res.start + REG_SSI_STX0; 870 dma->ssi_srx_phys = res.start + REG_SSI_SRX0; 871 872 iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL); 873 of_node_put(ssi_np); 874 if (iprop) 875 dma->ssi_fifo_depth = be32_to_cpup(iprop); 876 else 877 /* Older 8610 DTs didn't have the fifo-depth property */ 878 dma->ssi_fifo_depth = 8; 879 880 return devm_snd_soc_register_component(&pdev->dev, &dma->dai, NULL, 0); 881 } 882 883 static const struct of_device_id fsl_soc_dma_ids[] = { 884 { .compatible = "fsl,ssi-dma-channel", }, 885 {} 886 }; 887 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids); 888 889 static struct platform_driver fsl_soc_dma_driver = { 890 .driver = { 891 .name = "fsl-pcm-audio", 892 .of_match_table = fsl_soc_dma_ids, 893 }, 894 .probe = fsl_soc_dma_probe, 895 }; 896 897 module_platform_driver(fsl_soc_dma_driver); 898 899 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 900 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver"); 901 MODULE_LICENSE("GPL v2"); 902