1 /*- 2 * Copyright (c) 2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef DPAA_ETH_H_ 28 #define DPAA_ETH_H_ 29 30 #include <netinet/tcp_lro.h> 31 32 /* * TX csum-offload hwassist mask for dTSEC and mEMAC. */ 33 #define DPAA_CSUM_TX_OFFLOAD \ 34 (CSUM_IP | CSUM_DELAY_DATA | CSUM_DELAY_DATA_IPV6) 35 36 struct dpaa_pcpu_cnt { 37 u_int cnt; 38 } __aligned(CACHE_LINE_SIZE); 39 40 struct dpaa_eth_softc; 41 42 /* 43 * Per RX Frame Queue state. Today there is exactly one of these per 44 * port; a follow-on adds FMan KeyGen-driven hash distribution across 45 * N per-CPU FQs and this struct becomes the per-CPU RX slot. The 46 * back-pointer keeps the RX callback signature single-argument. 47 */ 48 struct dpaa_eth_rx_fq { 49 struct qman_fq *fq; 50 uint32_t fqid; 51 int cpu; /* CPU pin, or -1 if unpinned */ 52 struct dpaa_eth_softc *sc; 53 /* 54 * Frame count. Written by the RX callback which is affine to 55 * one CPU per FQ, so plain uint64 without atomics is safe. 56 * Sysctl readers get advisory (torn on 32-bit hosts) values. 57 */ 58 uint64_t frames_in; 59 60 /* 61 * Batched-input state. The RX callback appends non-LRO mbufs 62 * onto rx_head via m_nextpkt; the per-FQ flush hook hands the 63 * whole chain to if_input() and then runs tcp_lro_flush_all(). 64 * Both fields are only touched from the affine CPU. 65 */ 66 struct mbuf *rx_head; 67 struct mbuf **rx_tailp; 68 struct lro_ctrl lro; 69 bool lro_inited; 70 }; 71 72 struct dpaa_eth_softc { 73 /* XXX MII bus requires that struct ifnet is first!!! */ 74 if_t sc_ifnet; 75 76 device_t sc_dev; 77 struct resource *sc_mem; 78 struct mtx sc_lock; 79 80 int sc_mac_enet_mode; 81 82 /* RX Pool */ 83 struct bman_pool *sc_rx_pool; 84 uint8_t sc_rx_bpid; 85 uma_zone_t sc_rx_zone; 86 char sc_rx_zname[64]; 87 struct dpaa_pcpu_cnt *sc_rx_pool_check_cnt; /* per-CPU */ 88 89 /* RX Frame Queues (array of sc_nrxfqs entries). */ 90 struct dpaa_eth_rx_fq *sc_rx_fqs; 91 int sc_nrxfqs; 92 uint32_t sc_rx_fqid_base; 93 94 /* TX Frame Queue */ 95 struct qman_fq *sc_tx_fq; 96 volatile u_int sc_tx_fq_full; 97 u_int sc_tx_queue_check_cnt; 98 struct qman_fq *sc_tx_conf_fq; 99 uint32_t sc_tx_conf_fqid; 100 u_int sc_tx_conf_check_cnt; 101 102 /* Methods */ 103 int (*sc_port_rx_init) 104 (struct dpaa_eth_softc *sc, int unit); 105 int (*sc_port_tx_init) 106 (struct dpaa_eth_softc *sc, int unit); 107 void (*sc_start_locked) 108 (struct dpaa_eth_softc *sc); 109 110 /* dTSEC data */ 111 uint8_t sc_eth_id; /* Ethernet ID within its frame manager */ 112 uintptr_t sc_mac_mem_offset; 113 int sc_mac_mdio_irq; 114 uint8_t sc_mac_addr[6]; 115 int sc_port_rx_hw_id; 116 int sc_port_tx_hw_id; 117 uint32_t sc_port_tx_qman_chan; 118 int sc_phy_addr; 119 bool sc_hidden; 120 device_t sc_mdio; 121 int sc_rev_major; 122 int sc_rev_minor; 123 124 device_t sc_rx_port; 125 device_t sc_tx_port; 126 127 int sc_rx_channel; 128 129 /* MII data */ 130 struct mii_data *sc_mii; 131 device_t sc_mii_dev; 132 struct mtx sc_mii_lock; 133 134 struct callout sc_tick_callout; 135 136 /* Frame Info Zone */ 137 uma_zone_t sc_fi_zone; 138 char sc_fi_zname[64]; 139 }; 140 141 /** 142 * @group dTSEC Regular Mode API. 143 * @{ 144 */ 145 int dpaa_eth_fm_port_rx_init(struct dpaa_eth_softc *sc); 146 int dpaa_eth_fm_port_tx_init(struct dpaa_eth_softc *sc); 147 148 void dpaa_eth_if_start_locked(struct dpaa_eth_softc *sc); 149 150 int dpaa_eth_pool_rx_init(struct dpaa_eth_softc *sc); 151 void dpaa_eth_pool_rx_free(struct dpaa_eth_softc *sc); 152 153 int dpaa_eth_fi_pool_init(struct dpaa_eth_softc *sc); 154 void dpaa_eth_fi_pool_free(struct dpaa_eth_softc *sc); 155 156 int dpaa_eth_fq_rx_init(struct dpaa_eth_softc *sc); 157 int dpaa_eth_fq_tx_init(struct dpaa_eth_softc *sc); 158 void dpaa_eth_fq_rx_free(struct dpaa_eth_softc *sc); 159 void dpaa_eth_fq_tx_free(struct dpaa_eth_softc *sc); 160 /** @} */ 161 162 #endif /* DPAA_ETH_H_ */ 163