1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ARM64_KVM_HYP_SWITCH_H__
8 #define __ARM64_KVM_HYP_SWITCH_H__
9
10 #include <hyp/adjust_pc.h>
11 #include <hyp/fault.h>
12
13 #include <linux/arm-smccc.h>
14 #include <linux/kvm_host.h>
15 #include <linux/types.h>
16 #include <linux/jump_label.h>
17 #include <uapi/linux/psci.h>
18
19 #include <kvm/arm_psci.h>
20
21 #include <asm/barrier.h>
22 #include <asm/cpufeature.h>
23 #include <asm/extable.h>
24 #include <asm/kprobes.h>
25 #include <asm/kvm_asm.h>
26 #include <asm/kvm_emulate.h>
27 #include <asm/kvm_hyp.h>
28 #include <asm/kvm_mmu.h>
29 #include <asm/kvm_nested.h>
30 #include <asm/fpsimd.h>
31 #include <asm/debug-monitors.h>
32 #include <asm/processor.h>
33 #include <asm/traps.h>
34
35 struct kvm_exception_table_entry {
36 int insn, fixup;
37 };
38
39 extern struct kvm_exception_table_entry __start___kvm_ex_table;
40 extern struct kvm_exception_table_entry __stop___kvm_ex_table;
41
42 /* Save the 32-bit only FPSIMD system register state */
__fpsimd_save_fpexc32(struct kvm_vcpu * vcpu)43 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
44 {
45 if (!vcpu_el1_is_32bit(vcpu))
46 return;
47
48 __vcpu_assign_sys_reg(vcpu, FPEXC32_EL2, read_sysreg(fpexc32_el2));
49 }
50
__activate_traps_fpsimd32(struct kvm_vcpu * vcpu)51 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
52 {
53 /*
54 * We are about to set CPTR_EL2.TFP to trap all floating point
55 * register accesses to EL2, however, the ARM ARM clearly states that
56 * traps are only taken to EL2 if the operation would not otherwise
57 * trap to EL1. Therefore, always make sure that for 32-bit guests,
58 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
59 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
60 * it will cause an exception.
61 */
62 if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
63 write_sysreg(1 << 30, fpexc32_el2);
64 isb();
65 }
66 }
67
__activate_cptr_traps_nvhe(struct kvm_vcpu * vcpu)68 static inline void __activate_cptr_traps_nvhe(struct kvm_vcpu *vcpu)
69 {
70 u64 val = CPTR_NVHE_EL2_RES1 | CPTR_EL2_TAM | CPTR_EL2_TTA;
71
72 /*
73 * Always trap SME since it's not supported in KVM.
74 * TSM is RES1 if SME isn't implemented.
75 */
76 val |= CPTR_EL2_TSM;
77
78 if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs())
79 val |= CPTR_EL2_TZ;
80
81 if (!guest_owns_fp_regs())
82 val |= CPTR_EL2_TFP;
83
84 write_sysreg(val, cptr_el2);
85 }
86
__activate_cptr_traps_vhe(struct kvm_vcpu * vcpu)87 static inline void __activate_cptr_traps_vhe(struct kvm_vcpu *vcpu)
88 {
89 /*
90 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
91 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
92 * except for some missing controls, such as TAM.
93 * In this case, CPTR_EL2.TAM has the same position with or without
94 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
95 * shift value for trapping the AMU accesses.
96 */
97 u64 val = CPTR_EL2_TAM | CPACR_EL1_TTA;
98 u64 cptr;
99
100 if (guest_owns_fp_regs()) {
101 val |= CPACR_EL1_FPEN;
102 if (vcpu_has_sve(vcpu))
103 val |= CPACR_EL1_ZEN;
104 }
105
106 if (!vcpu_has_nv(vcpu))
107 goto write;
108
109 /*
110 * The architecture is a bit crap (what a surprise): an EL2 guest
111 * writing to CPTR_EL2 via CPACR_EL1 can't set any of TCPAC or TTA,
112 * as they are RES0 in the guest's view. To work around it, trap the
113 * sucker using the very same bit it can't set...
114 */
115 if (vcpu_el2_e2h_is_set(vcpu) && is_hyp_ctxt(vcpu))
116 val |= CPTR_EL2_TCPAC;
117
118 /*
119 * Layer the guest hypervisor's trap configuration on top of our own if
120 * we're in a nested context.
121 */
122 if (is_hyp_ctxt(vcpu))
123 goto write;
124
125 cptr = vcpu_sanitised_cptr_el2(vcpu);
126
127 /*
128 * Pay attention, there's some interesting detail here.
129 *
130 * The CPTR_EL2.xEN fields are 2 bits wide, although there are only two
131 * meaningful trap states when HCR_EL2.TGE = 0 (running a nested guest):
132 *
133 * - CPTR_EL2.xEN = x0, traps are enabled
134 * - CPTR_EL2.xEN = x1, traps are disabled
135 *
136 * In other words, bit[0] determines if guest accesses trap or not. In
137 * the interest of simplicity, clear the entire field if the guest
138 * hypervisor has traps enabled to dispel any illusion of something more
139 * complicated taking place.
140 */
141 if (!(SYS_FIELD_GET(CPACR_EL1, FPEN, cptr) & BIT(0)))
142 val &= ~CPACR_EL1_FPEN;
143 if (!(SYS_FIELD_GET(CPACR_EL1, ZEN, cptr) & BIT(0)))
144 val &= ~CPACR_EL1_ZEN;
145
146 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S2POE, IMP))
147 val |= cptr & CPACR_EL1_E0POE;
148
149 val |= cptr & CPTR_EL2_TCPAC;
150
151 write:
152 write_sysreg(val, cpacr_el1);
153 }
154
__activate_cptr_traps(struct kvm_vcpu * vcpu)155 static inline void __activate_cptr_traps(struct kvm_vcpu *vcpu)
156 {
157 if (!guest_owns_fp_regs())
158 __activate_traps_fpsimd32(vcpu);
159
160 if (has_vhe() || has_hvhe())
161 __activate_cptr_traps_vhe(vcpu);
162 else
163 __activate_cptr_traps_nvhe(vcpu);
164 }
165
__deactivate_cptr_traps_nvhe(struct kvm_vcpu * vcpu)166 static inline void __deactivate_cptr_traps_nvhe(struct kvm_vcpu *vcpu)
167 {
168 u64 val = CPTR_NVHE_EL2_RES1;
169
170 if (!cpus_have_final_cap(ARM64_SVE))
171 val |= CPTR_EL2_TZ;
172 if (!cpus_have_final_cap(ARM64_SME))
173 val |= CPTR_EL2_TSM;
174
175 write_sysreg(val, cptr_el2);
176 }
177
__deactivate_cptr_traps_vhe(struct kvm_vcpu * vcpu)178 static inline void __deactivate_cptr_traps_vhe(struct kvm_vcpu *vcpu)
179 {
180 u64 val = CPACR_EL1_FPEN;
181
182 if (cpus_have_final_cap(ARM64_SVE))
183 val |= CPACR_EL1_ZEN;
184 if (cpus_have_final_cap(ARM64_SME))
185 val |= CPACR_EL1_SMEN;
186
187 write_sysreg(val, cpacr_el1);
188 }
189
__deactivate_cptr_traps(struct kvm_vcpu * vcpu)190 static inline void __deactivate_cptr_traps(struct kvm_vcpu *vcpu)
191 {
192 if (has_vhe() || has_hvhe())
193 __deactivate_cptr_traps_vhe(vcpu);
194 else
195 __deactivate_cptr_traps_nvhe(vcpu);
196 }
197
198 #define reg_to_fgt_masks(reg) \
199 ({ \
200 struct fgt_masks *m; \
201 switch(reg) { \
202 case HFGRTR_EL2: \
203 m = &hfgrtr_masks; \
204 break; \
205 case HFGWTR_EL2: \
206 m = &hfgwtr_masks; \
207 break; \
208 case HFGITR_EL2: \
209 m = &hfgitr_masks; \
210 break; \
211 case HDFGRTR_EL2: \
212 m = &hdfgrtr_masks; \
213 break; \
214 case HDFGWTR_EL2: \
215 m = &hdfgwtr_masks; \
216 break; \
217 case HAFGRTR_EL2: \
218 m = &hafgrtr_masks; \
219 break; \
220 case HFGRTR2_EL2: \
221 m = &hfgrtr2_masks; \
222 break; \
223 case HFGWTR2_EL2: \
224 m = &hfgwtr2_masks; \
225 break; \
226 case HFGITR2_EL2: \
227 m = &hfgitr2_masks; \
228 break; \
229 case HDFGRTR2_EL2: \
230 m = &hdfgrtr2_masks; \
231 break; \
232 case HDFGWTR2_EL2: \
233 m = &hdfgwtr2_masks; \
234 break; \
235 default: \
236 BUILD_BUG_ON(1); \
237 } \
238 \
239 m; \
240 })
241
242 #define compute_clr_set(vcpu, reg, clr, set) \
243 do { \
244 u64 hfg = __vcpu_sys_reg(vcpu, reg); \
245 struct fgt_masks *m = reg_to_fgt_masks(reg); \
246 set |= hfg & m->mask; \
247 clr |= ~hfg & m->nmask; \
248 } while(0)
249
250 #define reg_to_fgt_group_id(reg) \
251 ({ \
252 enum fgt_group_id id; \
253 switch(reg) { \
254 case HFGRTR_EL2: \
255 case HFGWTR_EL2: \
256 id = HFGRTR_GROUP; \
257 break; \
258 case HFGITR_EL2: \
259 id = HFGITR_GROUP; \
260 break; \
261 case HDFGRTR_EL2: \
262 case HDFGWTR_EL2: \
263 id = HDFGRTR_GROUP; \
264 break; \
265 case HAFGRTR_EL2: \
266 id = HAFGRTR_GROUP; \
267 break; \
268 case HFGRTR2_EL2: \
269 case HFGWTR2_EL2: \
270 id = HFGRTR2_GROUP; \
271 break; \
272 case HFGITR2_EL2: \
273 id = HFGITR2_GROUP; \
274 break; \
275 case HDFGRTR2_EL2: \
276 case HDFGWTR2_EL2: \
277 id = HDFGRTR2_GROUP; \
278 break; \
279 default: \
280 BUILD_BUG_ON(1); \
281 } \
282 \
283 id; \
284 })
285
286 #define compute_undef_clr_set(vcpu, kvm, reg, clr, set) \
287 do { \
288 u64 hfg = kvm->arch.fgu[reg_to_fgt_group_id(reg)]; \
289 struct fgt_masks *m = reg_to_fgt_masks(reg); \
290 set |= hfg & m->mask; \
291 clr |= hfg & m->nmask; \
292 } while(0)
293
294 #define update_fgt_traps_cs(hctxt, vcpu, kvm, reg, clr, set) \
295 do { \
296 struct fgt_masks *m = reg_to_fgt_masks(reg); \
297 u64 c = clr, s = set; \
298 u64 val; \
299 \
300 ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg); \
301 if (is_nested_ctxt(vcpu)) \
302 compute_clr_set(vcpu, reg, c, s); \
303 \
304 compute_undef_clr_set(vcpu, kvm, reg, c, s); \
305 \
306 val = m->nmask; \
307 val |= s; \
308 val &= ~c; \
309 write_sysreg_s(val, SYS_ ## reg); \
310 } while(0)
311
312 #define update_fgt_traps(hctxt, vcpu, kvm, reg) \
313 update_fgt_traps_cs(hctxt, vcpu, kvm, reg, 0, 0)
314
cpu_has_amu(void)315 static inline bool cpu_has_amu(void)
316 {
317 u64 pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
318
319 return cpuid_feature_extract_unsigned_field(pfr0,
320 ID_AA64PFR0_EL1_AMU_SHIFT);
321 }
322
__activate_traps_hfgxtr(struct kvm_vcpu * vcpu)323 static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
324 {
325 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
326 struct kvm *kvm = kern_hyp_va(vcpu->kvm);
327
328 if (!cpus_have_final_cap(ARM64_HAS_FGT))
329 return;
330
331 update_fgt_traps(hctxt, vcpu, kvm, HFGRTR_EL2);
332 update_fgt_traps_cs(hctxt, vcpu, kvm, HFGWTR_EL2, 0,
333 cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) ?
334 HFGWTR_EL2_TCR_EL1_MASK : 0);
335 update_fgt_traps(hctxt, vcpu, kvm, HFGITR_EL2);
336 update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR_EL2);
337 update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR_EL2);
338
339 if (cpu_has_amu())
340 update_fgt_traps(hctxt, vcpu, kvm, HAFGRTR_EL2);
341
342 if (!cpus_have_final_cap(ARM64_HAS_FGT2))
343 return;
344
345 update_fgt_traps(hctxt, vcpu, kvm, HFGRTR2_EL2);
346 update_fgt_traps(hctxt, vcpu, kvm, HFGWTR2_EL2);
347 update_fgt_traps(hctxt, vcpu, kvm, HFGITR2_EL2);
348 update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR2_EL2);
349 update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR2_EL2);
350 }
351
352 #define __deactivate_fgt(htcxt, vcpu, reg) \
353 do { \
354 write_sysreg_s(ctxt_sys_reg(hctxt, reg), \
355 SYS_ ## reg); \
356 } while(0)
357
__deactivate_traps_hfgxtr(struct kvm_vcpu * vcpu)358 static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
359 {
360 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
361
362 if (!cpus_have_final_cap(ARM64_HAS_FGT))
363 return;
364
365 __deactivate_fgt(hctxt, vcpu, HFGRTR_EL2);
366 __deactivate_fgt(hctxt, vcpu, HFGWTR_EL2);
367 __deactivate_fgt(hctxt, vcpu, HFGITR_EL2);
368 __deactivate_fgt(hctxt, vcpu, HDFGRTR_EL2);
369 __deactivate_fgt(hctxt, vcpu, HDFGWTR_EL2);
370
371 if (cpu_has_amu())
372 __deactivate_fgt(hctxt, vcpu, HAFGRTR_EL2);
373
374 if (!cpus_have_final_cap(ARM64_HAS_FGT2))
375 return;
376
377 __deactivate_fgt(hctxt, vcpu, HFGRTR2_EL2);
378 __deactivate_fgt(hctxt, vcpu, HFGWTR2_EL2);
379 __deactivate_fgt(hctxt, vcpu, HFGITR2_EL2);
380 __deactivate_fgt(hctxt, vcpu, HDFGRTR2_EL2);
381 __deactivate_fgt(hctxt, vcpu, HDFGWTR2_EL2);
382 }
383
__activate_traps_mpam(struct kvm_vcpu * vcpu)384 static inline void __activate_traps_mpam(struct kvm_vcpu *vcpu)
385 {
386 u64 r = MPAM2_EL2_TRAPMPAM0EL1 | MPAM2_EL2_TRAPMPAM1EL1;
387
388 if (!system_supports_mpam())
389 return;
390
391 /* trap guest access to MPAMIDR_EL1 */
392 if (system_supports_mpam_hcr()) {
393 write_sysreg_s(MPAMHCR_EL2_TRAP_MPAMIDR_EL1, SYS_MPAMHCR_EL2);
394 } else {
395 /* From v1.1 TIDR can trap MPAMIDR, set it unconditionally */
396 r |= MPAM2_EL2_TIDR;
397 }
398
399 write_sysreg_s(r, SYS_MPAM2_EL2);
400 }
401
__deactivate_traps_mpam(void)402 static inline void __deactivate_traps_mpam(void)
403 {
404 if (!system_supports_mpam())
405 return;
406
407 write_sysreg_s(0, SYS_MPAM2_EL2);
408
409 if (system_supports_mpam_hcr())
410 write_sysreg_s(MPAMHCR_HOST_FLAGS, SYS_MPAMHCR_EL2);
411 }
412
__activate_traps_common(struct kvm_vcpu * vcpu)413 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
414 {
415 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
416
417 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
418 write_sysreg(1 << 15, hstr_el2);
419
420 /*
421 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
422 * PMSELR_EL0 to make sure it never contains the cycle
423 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
424 * EL1 instead of being trapped to EL2.
425 */
426 if (system_supports_pmuv3()) {
427 write_sysreg(0, pmselr_el0);
428
429 ctxt_sys_reg(hctxt, PMUSERENR_EL0) = read_sysreg(pmuserenr_el0);
430 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
431 vcpu_set_flag(vcpu, PMUSERENR_ON_CPU);
432 }
433
434 if (cpus_have_final_cap(ARM64_HAS_HCX)) {
435 u64 hcrx = vcpu->arch.hcrx_el2;
436 if (is_nested_ctxt(vcpu)) {
437 u64 val = __vcpu_sys_reg(vcpu, HCRX_EL2);
438 hcrx |= val & __HCRX_EL2_MASK;
439 hcrx &= ~(~val & __HCRX_EL2_nMASK);
440 }
441
442 ctxt_sys_reg(hctxt, HCRX_EL2) = read_sysreg_s(SYS_HCRX_EL2);
443 write_sysreg_s(hcrx, SYS_HCRX_EL2);
444 }
445
446 __activate_traps_hfgxtr(vcpu);
447 __activate_traps_mpam(vcpu);
448 }
449
__deactivate_traps_common(struct kvm_vcpu * vcpu)450 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
451 {
452 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
453
454 write_sysreg(0, hstr_el2);
455 if (system_supports_pmuv3()) {
456 write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0);
457 vcpu_clear_flag(vcpu, PMUSERENR_ON_CPU);
458 }
459
460 if (cpus_have_final_cap(ARM64_HAS_HCX))
461 write_sysreg_s(ctxt_sys_reg(hctxt, HCRX_EL2), SYS_HCRX_EL2);
462
463 __deactivate_traps_hfgxtr(vcpu);
464 __deactivate_traps_mpam();
465 }
466
___activate_traps(struct kvm_vcpu * vcpu,u64 hcr)467 static inline void ___activate_traps(struct kvm_vcpu *vcpu, u64 hcr)
468 {
469 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
470 hcr |= HCR_TVM;
471
472 write_sysreg_hcr(hcr);
473
474 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE)) {
475 u64 vsesr;
476
477 /*
478 * When HCR_EL2.AMO is set, physical SErrors are taken to EL2
479 * and vSError injection is enabled for EL1. Conveniently, for
480 * NV this means that it is never the case where a 'physical'
481 * SError (injected by KVM or userspace) and vSError are
482 * deliverable to the same context.
483 *
484 * As such, we can trivially select between the host or guest's
485 * VSESR_EL2. Except for the case that FEAT_RAS hasn't been
486 * exposed to the guest, where ESR propagation in hardware
487 * occurs unconditionally.
488 *
489 * Paper over the architectural wart and use an IMPLEMENTATION
490 * DEFINED ESR value in case FEAT_RAS is hidden from the guest.
491 */
492 if (!vserror_state_is_nested(vcpu))
493 vsesr = vcpu->arch.vsesr_el2;
494 else if (kvm_has_ras(kern_hyp_va(vcpu->kvm)))
495 vsesr = __vcpu_sys_reg(vcpu, VSESR_EL2);
496 else
497 vsesr = ESR_ELx_ISV;
498
499 write_sysreg_s(vsesr, SYS_VSESR_EL2);
500 }
501 }
502
___deactivate_traps(struct kvm_vcpu * vcpu)503 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu)
504 {
505 u64 *hcr;
506
507 if (vserror_state_is_nested(vcpu))
508 hcr = __ctxt_sys_reg(&vcpu->arch.ctxt, HCR_EL2);
509 else
510 hcr = &vcpu->arch.hcr_el2;
511
512 /*
513 * If we pended a virtual abort, preserve it until it gets
514 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
515 * the crucial bit is "On taking a vSError interrupt,
516 * HCR_EL2.VSE is cleared to 0."
517 *
518 * Additionally, when in a nested context we need to propagate the
519 * updated state to the guest hypervisor's HCR_EL2.
520 */
521 if (*hcr & HCR_VSE) {
522 *hcr &= ~HCR_VSE;
523 *hcr |= read_sysreg(hcr_el2) & HCR_VSE;
524 }
525 }
526
__populate_fault_info(struct kvm_vcpu * vcpu)527 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)
528 {
529 return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault);
530 }
531
kvm_hyp_handle_mops(struct kvm_vcpu * vcpu,u64 * exit_code)532 static inline bool kvm_hyp_handle_mops(struct kvm_vcpu *vcpu, u64 *exit_code)
533 {
534 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
535 arm64_mops_reset_regs(vcpu_gp_regs(vcpu), vcpu->arch.fault.esr_el2);
536 write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
537
538 /*
539 * Finish potential single step before executing the prologue
540 * instruction.
541 */
542 *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
543 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
544
545 return true;
546 }
547
__hyp_sve_restore_guest(struct kvm_vcpu * vcpu)548 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu)
549 {
550 /*
551 * The vCPU's saved SVE state layout always matches the max VL of the
552 * vCPU. Start off with the max VL so we can load the SVE state.
553 */
554 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2);
555 __sve_restore_state(vcpu_sve_pffr(vcpu),
556 &vcpu->arch.ctxt.fp_regs.fpsr,
557 true);
558
559 /*
560 * The effective VL for a VM could differ from the max VL when running a
561 * nested guest, as the guest hypervisor could select a smaller VL. Slap
562 * that into hardware before wrapping up.
563 */
564 if (is_nested_ctxt(vcpu))
565 sve_cond_update_zcr_vq(__vcpu_sys_reg(vcpu, ZCR_EL2), SYS_ZCR_EL2);
566
567 write_sysreg_el1(__vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu)), SYS_ZCR);
568 }
569
__hyp_sve_save_host(void)570 static inline void __hyp_sve_save_host(void)
571 {
572 struct cpu_sve_state *sve_state = *host_data_ptr(sve_state);
573
574 sve_state->zcr_el1 = read_sysreg_el1(SYS_ZCR);
575 write_sysreg_s(sve_vq_from_vl(kvm_host_sve_max_vl) - 1, SYS_ZCR_EL2);
576 __sve_save_state(sve_state->sve_regs + sve_ffr_offset(kvm_host_sve_max_vl),
577 &sve_state->fpsr,
578 true);
579 }
580
fpsimd_lazy_switch_to_guest(struct kvm_vcpu * vcpu)581 static inline void fpsimd_lazy_switch_to_guest(struct kvm_vcpu *vcpu)
582 {
583 u64 zcr_el1, zcr_el2;
584
585 if (!guest_owns_fp_regs())
586 return;
587
588 if (vcpu_has_sve(vcpu)) {
589 /* A guest hypervisor may restrict the effective max VL. */
590 if (is_nested_ctxt(vcpu))
591 zcr_el2 = __vcpu_sys_reg(vcpu, ZCR_EL2);
592 else
593 zcr_el2 = vcpu_sve_max_vq(vcpu) - 1;
594
595 write_sysreg_el2(zcr_el2, SYS_ZCR);
596
597 zcr_el1 = __vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu));
598 write_sysreg_el1(zcr_el1, SYS_ZCR);
599 }
600 }
601
fpsimd_lazy_switch_to_host(struct kvm_vcpu * vcpu)602 static inline void fpsimd_lazy_switch_to_host(struct kvm_vcpu *vcpu)
603 {
604 u64 zcr_el1, zcr_el2;
605
606 if (!guest_owns_fp_regs())
607 return;
608
609 /*
610 * When the guest owns the FP regs, we know that guest+hyp traps for
611 * any FPSIMD/SVE/SME features exposed to the guest have been disabled
612 * by either fpsimd_lazy_switch_to_guest() or kvm_hyp_handle_fpsimd()
613 * prior to __guest_entry(). As __guest_entry() guarantees a context
614 * synchronization event, we don't need an ISB here to avoid taking
615 * traps for anything that was exposed to the guest.
616 */
617 if (vcpu_has_sve(vcpu)) {
618 zcr_el1 = read_sysreg_el1(SYS_ZCR);
619 __vcpu_assign_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu), zcr_el1);
620
621 /*
622 * The guest's state is always saved using the guest's max VL.
623 * Ensure that the host has the guest's max VL active such that
624 * the host can save the guest's state lazily, but don't
625 * artificially restrict the host to the guest's max VL.
626 */
627 if (has_vhe()) {
628 zcr_el2 = vcpu_sve_max_vq(vcpu) - 1;
629 write_sysreg_el2(zcr_el2, SYS_ZCR);
630 } else {
631 zcr_el2 = sve_vq_from_vl(kvm_host_sve_max_vl) - 1;
632 write_sysreg_el2(zcr_el2, SYS_ZCR);
633
634 zcr_el1 = vcpu_sve_max_vq(vcpu) - 1;
635 write_sysreg_el1(zcr_el1, SYS_ZCR);
636 }
637 }
638 }
639
kvm_hyp_save_fpsimd_host(struct kvm_vcpu * vcpu)640 static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *vcpu)
641 {
642 /*
643 * Non-protected kvm relies on the host restoring its sve state.
644 * Protected kvm restores the host's sve state as not to reveal that
645 * fpsimd was used by a guest nor leak upper sve bits.
646 */
647 if (system_supports_sve()) {
648 __hyp_sve_save_host();
649 } else {
650 __fpsimd_save_state(host_data_ptr(host_ctxt.fp_regs));
651 }
652
653 if (kvm_has_fpmr(kern_hyp_va(vcpu->kvm)))
654 *host_data_ptr(fpmr) = read_sysreg_s(SYS_FPMR);
655 }
656
657
658 /*
659 * We trap the first access to the FP/SIMD to save the host context and
660 * restore the guest context lazily.
661 * If FP/SIMD is not implemented, handle the trap and inject an undefined
662 * instruction exception to the guest. Similarly for trapped SVE accesses.
663 */
kvm_hyp_handle_fpsimd(struct kvm_vcpu * vcpu,u64 * exit_code)664 static inline bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
665 {
666 bool sve_guest;
667 u8 esr_ec;
668
669 if (!system_supports_fpsimd())
670 return false;
671
672 sve_guest = vcpu_has_sve(vcpu);
673 esr_ec = kvm_vcpu_trap_get_class(vcpu);
674
675 /* Only handle traps the vCPU can support here: */
676 switch (esr_ec) {
677 case ESR_ELx_EC_FP_ASIMD:
678 /* Forward traps to the guest hypervisor as required */
679 if (guest_hyp_fpsimd_traps_enabled(vcpu))
680 return false;
681 break;
682 case ESR_ELx_EC_SYS64:
683 if (WARN_ON_ONCE(!is_hyp_ctxt(vcpu)))
684 return false;
685 fallthrough;
686 case ESR_ELx_EC_SVE:
687 if (!sve_guest)
688 return false;
689 if (guest_hyp_sve_traps_enabled(vcpu))
690 return false;
691 break;
692 default:
693 return false;
694 }
695
696 /* Valid trap. Switch the context: */
697
698 /* First disable enough traps to allow us to update the registers */
699 __deactivate_cptr_traps(vcpu);
700 isb();
701
702 /* Write out the host state if it's in the registers */
703 if (is_protected_kvm_enabled() && host_owns_fp_regs())
704 kvm_hyp_save_fpsimd_host(vcpu);
705
706 /* Restore the guest state */
707 if (sve_guest)
708 __hyp_sve_restore_guest(vcpu);
709 else
710 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs);
711
712 if (kvm_has_fpmr(kern_hyp_va(vcpu->kvm)))
713 write_sysreg_s(__vcpu_sys_reg(vcpu, FPMR), SYS_FPMR);
714
715 /* Skip restoring fpexc32 for AArch64 guests */
716 if (!(read_sysreg(hcr_el2) & HCR_RW))
717 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2);
718
719 *host_data_ptr(fp_owner) = FP_STATE_GUEST_OWNED;
720
721 /*
722 * Re-enable traps necessary for the current state of the guest, e.g.
723 * those enabled by a guest hypervisor. The ERET to the guest will
724 * provide the necessary context synchronization.
725 */
726 __activate_cptr_traps(vcpu);
727
728 return true;
729 }
730
handle_tx2_tvm(struct kvm_vcpu * vcpu)731 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu)
732 {
733 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
734 int rt = kvm_vcpu_sys_get_rt(vcpu);
735 u64 val = vcpu_get_reg(vcpu, rt);
736
737 /*
738 * The normal sysreg handling code expects to see the traps,
739 * let's not do anything here.
740 */
741 if (vcpu->arch.hcr_el2 & HCR_TVM)
742 return false;
743
744 switch (sysreg) {
745 case SYS_SCTLR_EL1:
746 write_sysreg_el1(val, SYS_SCTLR);
747 break;
748 case SYS_TTBR0_EL1:
749 write_sysreg_el1(val, SYS_TTBR0);
750 break;
751 case SYS_TTBR1_EL1:
752 write_sysreg_el1(val, SYS_TTBR1);
753 break;
754 case SYS_TCR_EL1:
755 write_sysreg_el1(val, SYS_TCR);
756 break;
757 case SYS_ESR_EL1:
758 write_sysreg_el1(val, SYS_ESR);
759 break;
760 case SYS_FAR_EL1:
761 write_sysreg_el1(val, SYS_FAR);
762 break;
763 case SYS_AFSR0_EL1:
764 write_sysreg_el1(val, SYS_AFSR0);
765 break;
766 case SYS_AFSR1_EL1:
767 write_sysreg_el1(val, SYS_AFSR1);
768 break;
769 case SYS_MAIR_EL1:
770 write_sysreg_el1(val, SYS_MAIR);
771 break;
772 case SYS_AMAIR_EL1:
773 write_sysreg_el1(val, SYS_AMAIR);
774 break;
775 case SYS_CONTEXTIDR_EL1:
776 write_sysreg_el1(val, SYS_CONTEXTIDR);
777 break;
778 default:
779 return false;
780 }
781
782 __kvm_skip_instr(vcpu);
783 return true;
784 }
785
786 /* Open-coded version of timer_get_offset() to allow for kern_hyp_va() */
hyp_timer_get_offset(struct arch_timer_context * ctxt)787 static inline u64 hyp_timer_get_offset(struct arch_timer_context *ctxt)
788 {
789 u64 offset = 0;
790
791 if (ctxt->offset.vm_offset)
792 offset += *kern_hyp_va(ctxt->offset.vm_offset);
793 if (ctxt->offset.vcpu_offset)
794 offset += *kern_hyp_va(ctxt->offset.vcpu_offset);
795
796 return offset;
797 }
798
compute_counter_value(struct arch_timer_context * ctxt)799 static inline u64 compute_counter_value(struct arch_timer_context *ctxt)
800 {
801 return arch_timer_read_cntpct_el0() - hyp_timer_get_offset(ctxt);
802 }
803
kvm_handle_cntxct(struct kvm_vcpu * vcpu)804 static bool kvm_handle_cntxct(struct kvm_vcpu *vcpu)
805 {
806 struct arch_timer_context *ctxt;
807 u32 sysreg;
808 u64 val;
809
810 /*
811 * We only get here for 64bit guests, 32bit guests will hit
812 * the long and winding road all the way to the standard
813 * handling. Yes, it sucks to be irrelevant.
814 *
815 * Also, we only deal with non-hypervisor context here (either
816 * an EL1 guest, or a non-HYP context of an EL2 guest).
817 */
818 if (is_hyp_ctxt(vcpu))
819 return false;
820
821 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
822
823 switch (sysreg) {
824 case SYS_CNTPCT_EL0:
825 case SYS_CNTPCTSS_EL0:
826 if (vcpu_has_nv(vcpu)) {
827 /* Check for guest hypervisor trapping */
828 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
829 if (!vcpu_el2_e2h_is_set(vcpu))
830 val = (val & CNTHCTL_EL1PCTEN) << 10;
831
832 if (!(val & (CNTHCTL_EL1PCTEN << 10)))
833 return false;
834 }
835
836 ctxt = vcpu_ptimer(vcpu);
837 break;
838 case SYS_CNTVCT_EL0:
839 case SYS_CNTVCTSS_EL0:
840 if (vcpu_has_nv(vcpu)) {
841 /* Check for guest hypervisor trapping */
842 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
843
844 if (val & CNTHCTL_EL1TVCT)
845 return false;
846 }
847
848 ctxt = vcpu_vtimer(vcpu);
849 break;
850 default:
851 return false;
852 }
853
854 val = compute_counter_value(ctxt);
855
856 vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
857 __kvm_skip_instr(vcpu);
858 return true;
859 }
860
handle_ampere1_tcr(struct kvm_vcpu * vcpu)861 static bool handle_ampere1_tcr(struct kvm_vcpu *vcpu)
862 {
863 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
864 int rt = kvm_vcpu_sys_get_rt(vcpu);
865 u64 val = vcpu_get_reg(vcpu, rt);
866
867 if (sysreg != SYS_TCR_EL1)
868 return false;
869
870 /*
871 * Affected parts do not advertise support for hardware Access Flag /
872 * Dirty state management in ID_AA64MMFR1_EL1.HAFDBS, but the underlying
873 * control bits are still functional. The architecture requires these be
874 * RES0 on systems that do not implement FEAT_HAFDBS.
875 *
876 * Uphold the requirements of the architecture by masking guest writes
877 * to TCR_EL1.{HA,HD} here.
878 */
879 val &= ~(TCR_HD | TCR_HA);
880 write_sysreg_el1(val, SYS_TCR);
881 __kvm_skip_instr(vcpu);
882 return true;
883 }
884
kvm_hyp_handle_sysreg(struct kvm_vcpu * vcpu,u64 * exit_code)885 static inline bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
886 {
887 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
888 handle_tx2_tvm(vcpu))
889 return true;
890
891 if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) &&
892 handle_ampere1_tcr(vcpu))
893 return true;
894
895 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
896 __vgic_v3_perform_cpuif_access(vcpu) == 1)
897 return true;
898
899 if (kvm_handle_cntxct(vcpu))
900 return true;
901
902 return false;
903 }
904
kvm_hyp_handle_cp15_32(struct kvm_vcpu * vcpu,u64 * exit_code)905 static inline bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code)
906 {
907 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
908 __vgic_v3_perform_cpuif_access(vcpu) == 1)
909 return true;
910
911 return false;
912 }
913
kvm_hyp_handle_memory_fault(struct kvm_vcpu * vcpu,u64 * exit_code)914 static inline bool kvm_hyp_handle_memory_fault(struct kvm_vcpu *vcpu,
915 u64 *exit_code)
916 {
917 if (!__populate_fault_info(vcpu))
918 return true;
919
920 return false;
921 }
922 #define kvm_hyp_handle_iabt_low kvm_hyp_handle_memory_fault
923 #define kvm_hyp_handle_watchpt_low kvm_hyp_handle_memory_fault
924
kvm_hyp_handle_dabt_low(struct kvm_vcpu * vcpu,u64 * exit_code)925 static inline bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
926 {
927 if (kvm_hyp_handle_memory_fault(vcpu, exit_code))
928 return true;
929
930 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
931 bool valid;
932
933 valid = kvm_vcpu_trap_is_translation_fault(vcpu) &&
934 kvm_vcpu_dabt_isvalid(vcpu) &&
935 !kvm_vcpu_abt_issea(vcpu) &&
936 !kvm_vcpu_abt_iss1tw(vcpu);
937
938 if (valid) {
939 int ret = __vgic_v2_perform_cpuif_access(vcpu);
940
941 if (ret == 1)
942 return true;
943
944 /* Promote an illegal access to an SError.*/
945 if (ret == -1)
946 *exit_code = ARM_EXCEPTION_EL1_SERROR;
947 }
948 }
949
950 return false;
951 }
952
953 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *);
954
955 /*
956 * Allow the hypervisor to handle the exit with an exit handler if it has one.
957 *
958 * Returns true if the hypervisor handled the exit, and control should go back
959 * to the guest, or false if it hasn't.
960 */
kvm_hyp_handle_exit(struct kvm_vcpu * vcpu,u64 * exit_code,const exit_handler_fn * handlers)961 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code,
962 const exit_handler_fn *handlers)
963 {
964 exit_handler_fn fn = handlers[kvm_vcpu_trap_get_class(vcpu)];
965 if (fn)
966 return fn(vcpu, exit_code);
967
968 return false;
969 }
970
synchronize_vcpu_pstate(struct kvm_vcpu * vcpu,u64 * exit_code)971 static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code)
972 {
973 /*
974 * Check for the conditions of Cortex-A510's #2077057. When these occur
975 * SPSR_EL2 can't be trusted, but isn't needed either as it is
976 * unchanged from the value in vcpu_gp_regs(vcpu)->pstate.
977 * Are we single-stepping the guest, and took a PAC exception from the
978 * active-not-pending state?
979 */
980 if (cpus_have_final_cap(ARM64_WORKAROUND_2077057) &&
981 vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
982 *vcpu_cpsr(vcpu) & DBG_SPSR_SS &&
983 ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC)
984 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
985
986 vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
987 }
988
989 /*
990 * Return true when we were able to fixup the guest exit and should return to
991 * the guest, false when we should restore the host state and return to the
992 * main run loop.
993 */
__fixup_guest_exit(struct kvm_vcpu * vcpu,u64 * exit_code,const exit_handler_fn * handlers)994 static inline bool __fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code,
995 const exit_handler_fn *handlers)
996 {
997 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
998 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
999
1000 if (ARM_SERROR_PENDING(*exit_code) &&
1001 ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) {
1002 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
1003
1004 /*
1005 * HVC already have an adjusted PC, which we need to
1006 * correct in order to return to after having injected
1007 * the SError.
1008 *
1009 * SMC, on the other hand, is *trapped*, meaning its
1010 * preferred return address is the SMC itself.
1011 */
1012 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64)
1013 write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR);
1014 }
1015
1016 /*
1017 * We're using the raw exception code in order to only process
1018 * the trap if no SError is pending. We will come back to the
1019 * same PC once the SError has been injected, and replay the
1020 * trapping instruction.
1021 */
1022 if (*exit_code != ARM_EXCEPTION_TRAP)
1023 goto exit;
1024
1025 /* Check if there's an exit handler and allow it to handle the exit. */
1026 if (kvm_hyp_handle_exit(vcpu, exit_code, handlers))
1027 goto guest;
1028 exit:
1029 /* Return to the host kernel and handle the exit */
1030 return false;
1031
1032 guest:
1033 /* Re-enter the guest */
1034 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
1035 return true;
1036 }
1037
__kvm_unexpected_el2_exception(void)1038 static inline void __kvm_unexpected_el2_exception(void)
1039 {
1040 extern char __guest_exit_restore_elr_and_panic[];
1041 unsigned long addr, fixup;
1042 struct kvm_exception_table_entry *entry, *end;
1043 unsigned long elr_el2 = read_sysreg(elr_el2);
1044
1045 entry = &__start___kvm_ex_table;
1046 end = &__stop___kvm_ex_table;
1047
1048 while (entry < end) {
1049 addr = (unsigned long)&entry->insn + entry->insn;
1050 fixup = (unsigned long)&entry->fixup + entry->fixup;
1051
1052 if (addr != elr_el2) {
1053 entry++;
1054 continue;
1055 }
1056
1057 write_sysreg(fixup, elr_el2);
1058 return;
1059 }
1060
1061 /* Trigger a panic after restoring the hyp context. */
1062 this_cpu_ptr(&kvm_hyp_ctxt)->sys_regs[ELR_EL2] = elr_el2;
1063 write_sysreg(__guest_exit_restore_elr_and_panic, elr_el2);
1064 }
1065
1066 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */
1067