1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright © 2022-2024 Rivos Inc. 4 * Copyright © 2023 FORTH-ICS/CARV 5 * 6 * Authors 7 * Tomasz Jeznach <tjeznach@rivosinc.com> 8 * Nick Kossifidis <mick@ics.forth.gr> 9 */ 10 11 #ifndef _RISCV_IOMMU_H_ 12 #define _RISCV_IOMMU_H_ 13 14 #include <linux/iommu.h> 15 #include <linux/spinlock.h> 16 #include <linux/types.h> 17 #include <linux/iopoll.h> 18 19 #include "iommu-bits.h" 20 21 struct riscv_iommu_device; 22 23 struct riscv_iommu_queue { 24 atomic_t prod; /* unbounded producer allocation index */ 25 atomic_t head; /* unbounded shadow ring buffer consumer index */ 26 atomic_t tail; /* unbounded shadow ring buffer producer index */ 27 raw_spinlock_t lock; /* serialize queue publishing */ 28 unsigned int mask; /* index mask, queue length - 1 */ 29 unsigned int irq; /* allocated interrupt number */ 30 struct riscv_iommu_device *iommu; /* iommu device handling the queue when active */ 31 void *base; /* ring buffer kernel pointer */ 32 dma_addr_t phys; /* ring buffer physical address */ 33 u16 qbr; /* base register offset, head and tail reference */ 34 u16 qcr; /* control and status register offset */ 35 u8 qid; /* queue identifier, same as RISCV_IOMMU_INTR_XX */ 36 }; 37 38 struct riscv_iommu_device { 39 /* iommu core interface */ 40 struct iommu_device iommu; 41 42 /* iommu hardware */ 43 struct device *dev; 44 45 /* hardware control register space */ 46 void __iomem *reg; 47 48 /* supported and enabled hardware capabilities */ 49 u64 caps; 50 u32 fctl; 51 52 /* available interrupt numbers, MSI or WSI */ 53 unsigned int irqs[RISCV_IOMMU_INTR_COUNT]; 54 unsigned int irqs_count; 55 unsigned int icvec; 56 57 /* hardware queues */ 58 struct riscv_iommu_queue cmdq; 59 struct riscv_iommu_queue fltq; 60 61 /* device directory */ 62 unsigned int ddt_mode; 63 dma_addr_t ddt_phys; 64 u64 *ddt_root; 65 }; 66 67 int riscv_iommu_init(struct riscv_iommu_device *iommu); 68 void riscv_iommu_remove(struct riscv_iommu_device *iommu); 69 void riscv_iommu_disable(struct riscv_iommu_device *iommu); 70 71 #define riscv_iommu_readl(iommu, addr) \ 72 readl_relaxed((iommu)->reg + (addr)) 73 74 #define riscv_iommu_readq(iommu, addr) \ 75 readq_relaxed((iommu)->reg + (addr)) 76 77 #define riscv_iommu_writel(iommu, addr, val) \ 78 writel_relaxed((val), (iommu)->reg + (addr)) 79 80 #define riscv_iommu_writeq(iommu, addr, val) \ 81 writeq_relaxed((val), (iommu)->reg + (addr)) 82 83 #define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ 84 readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \ 85 delay_us, timeout_us) 86 87 #define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ 88 readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \ 89 delay_us, timeout_us) 90 91 #endif 92