1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
10 */
11
12 #ifndef _UFSHCD_H
13 #define _UFSHCD_H
14
15 #include <linux/bitfield.h>
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-mq.h>
18 #include <linux/devfreq.h>
19 #include <linux/fault-inject.h>
20 #include <linux/debugfs.h>
21 #include <linux/msi.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/dma-direction.h>
24 #include <scsi/scsi_device.h>
25 #include <scsi/scsi_host.h>
26 #include <ufs/unipro.h>
27 #include <ufs/ufs.h>
28 #include <ufs/ufs_quirks.h>
29 #include <ufs/ufshci.h>
30
31 #define UFSHCD "ufshcd"
32
33 struct scsi_device;
34 struct ufs_hba;
35
36 enum dev_cmd_type {
37 DEV_CMD_TYPE_NOP = 0x0,
38 DEV_CMD_TYPE_QUERY = 0x1,
39 DEV_CMD_TYPE_RPMB = 0x2,
40 };
41
42 enum ufs_event_type {
43 /* uic specific errors */
44 UFS_EVT_PA_ERR = 0,
45 UFS_EVT_DL_ERR,
46 UFS_EVT_NL_ERR,
47 UFS_EVT_TL_ERR,
48 UFS_EVT_DME_ERR,
49
50 /* fatal errors */
51 UFS_EVT_AUTO_HIBERN8_ERR,
52 UFS_EVT_FATAL_ERR,
53 UFS_EVT_LINK_STARTUP_FAIL,
54 UFS_EVT_RESUME_ERR,
55 UFS_EVT_SUSPEND_ERR,
56 UFS_EVT_WL_SUSP_ERR,
57 UFS_EVT_WL_RES_ERR,
58
59 /* abnormal events */
60 UFS_EVT_DEV_RESET,
61 UFS_EVT_HOST_RESET,
62 UFS_EVT_ABORT,
63
64 UFS_EVT_CNT,
65 };
66
67 /**
68 * struct uic_command - UIC command structure
69 * @command: UIC command
70 * @argument1: UIC command argument 1
71 * @argument2: UIC command argument 2
72 * @argument3: UIC command argument 3
73 * @cmd_active: Indicate if UIC command is outstanding
74 * @done: UIC command completion
75 */
76 struct uic_command {
77 const u32 command;
78 const u32 argument1;
79 u32 argument2;
80 u32 argument3;
81 bool cmd_active;
82 struct completion done;
83 };
84
85 /* Used to differentiate the power management options */
86 enum ufs_pm_op {
87 UFS_RUNTIME_PM,
88 UFS_SYSTEM_PM,
89 UFS_SHUTDOWN_PM,
90 };
91
92 /* Host <-> Device UniPro Link state */
93 enum uic_link_state {
94 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
95 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
96 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
97 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */
98 };
99
100 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
101 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
102 UIC_LINK_ACTIVE_STATE)
103 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
104 UIC_LINK_HIBERN8_STATE)
105 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
106 UIC_LINK_BROKEN_STATE)
107 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
108 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
109 UIC_LINK_ACTIVE_STATE)
110 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
111 UIC_LINK_HIBERN8_STATE)
112 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
113 UIC_LINK_BROKEN_STATE)
114
115 #define ufshcd_set_ufs_dev_active(h) \
116 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
117 #define ufshcd_set_ufs_dev_sleep(h) \
118 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
119 #define ufshcd_set_ufs_dev_poweroff(h) \
120 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
121 #define ufshcd_set_ufs_dev_deepsleep(h) \
122 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
123 #define ufshcd_is_ufs_dev_active(h) \
124 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
125 #define ufshcd_is_ufs_dev_sleep(h) \
126 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
127 #define ufshcd_is_ufs_dev_poweroff(h) \
128 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
129 #define ufshcd_is_ufs_dev_deepsleep(h) \
130 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
131
132 /*
133 * UFS Power management levels.
134 * Each level is in increasing order of power savings, except DeepSleep
135 * which is lower than PowerDown with power on but not PowerDown with
136 * power off.
137 */
138 enum ufs_pm_level {
139 UFS_PM_LVL_0,
140 UFS_PM_LVL_1,
141 UFS_PM_LVL_2,
142 UFS_PM_LVL_3,
143 UFS_PM_LVL_4,
144 UFS_PM_LVL_5,
145 UFS_PM_LVL_6,
146 UFS_PM_LVL_MAX
147 };
148
149 struct ufs_pm_lvl_states {
150 enum ufs_dev_pwr_mode dev_state;
151 enum uic_link_state link_state;
152 };
153
154 /**
155 * struct ufshcd_lrb - local reference block
156 * @utr_descriptor_ptr: UTRD address of the command
157 * @ucd_req_ptr: UCD address of the command
158 * @ucd_rsp_ptr: Response UPIU address for this command
159 * @ucd_prdt_ptr: PRDT address of the command
160 * @utrd_dma_addr: UTRD dma address for debug
161 * @ucd_prdt_dma_addr: PRDT dma address for debug
162 * @ucd_rsp_dma_addr: UPIU response dma address for debug
163 * @ucd_req_dma_addr: UPIU request dma address for debug
164 * @scsi_status: SCSI status of the command
165 * @command_type: SCSI, UFS, Query.
166 * @task_tag: Task tag of the command
167 * @lun: LUN of the command
168 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
169 * @req_abort_skip: skip request abort task flag
170 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC)
171 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock)
172 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC)
173 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock)
174 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
175 * @data_unit_num: the data unit number for the first block for inline crypto
176 */
177 struct ufshcd_lrb {
178 struct utp_transfer_req_desc *utr_descriptor_ptr;
179 struct utp_upiu_req *ucd_req_ptr;
180 struct utp_upiu_rsp *ucd_rsp_ptr;
181 struct ufshcd_sg_entry *ucd_prdt_ptr;
182
183 dma_addr_t utrd_dma_addr;
184 dma_addr_t ucd_req_dma_addr;
185 dma_addr_t ucd_rsp_dma_addr;
186 dma_addr_t ucd_prdt_dma_addr;
187
188 int scsi_status;
189
190 int command_type;
191 u8 lun; /* UPIU LUN id field is only 8-bit wide */
192 bool intr_cmd;
193 bool req_abort_skip;
194 ktime_t issue_time_stamp;
195 u64 issue_time_stamp_local_clock;
196 ktime_t compl_time_stamp;
197 u64 compl_time_stamp_local_clock;
198 #ifdef CONFIG_SCSI_UFS_CRYPTO
199 int crypto_key_slot;
200 u64 data_unit_num;
201 #endif
202 };
203
204 /**
205 * struct ufs_query_req - parameters for building a query request
206 * @query_func: UPIU header query function
207 * @upiu_req: the query request data
208 */
209 struct ufs_query_req {
210 u8 query_func;
211 struct utp_upiu_query upiu_req;
212 };
213
214 /**
215 * struct ufs_query_resp - UPIU QUERY
216 * @response: device response code
217 * @upiu_res: query response data
218 */
219 struct ufs_query_res {
220 struct utp_upiu_query upiu_res;
221 };
222
223 /**
224 * struct ufs_query - holds relevant data structures for query request
225 * @request: request upiu and function
226 * @descriptor: buffer for sending/receiving descriptor
227 * @response: response upiu and response
228 */
229 struct ufs_query {
230 struct ufs_query_req request;
231 u8 *descriptor;
232 struct ufs_query_res response;
233 };
234
235 /**
236 * struct ufs_dev_cmd - all assosiated fields with device management commands
237 * @type: device management command type - Query, NOP OUT
238 * @lock: lock to allow one command at a time
239 * @query: Device management query information
240 */
241 struct ufs_dev_cmd {
242 enum dev_cmd_type type;
243 struct mutex lock;
244 struct ufs_query query;
245 };
246
247 /**
248 * struct ufs_clk_info - UFS clock related info
249 * @list: list headed by hba->clk_list_head
250 * @clk: clock node
251 * @name: clock name
252 * @max_freq: maximum frequency supported by the clock
253 * @min_freq: min frequency that can be used for clock scaling
254 * @curr_freq: indicates the current frequency that it is set to
255 * @keep_link_active: indicates that the clk should not be disabled if
256 * link is active
257 * @enabled: variable to check against multiple enable/disable
258 */
259 struct ufs_clk_info {
260 struct list_head list;
261 struct clk *clk;
262 const char *name;
263 u32 max_freq;
264 u32 min_freq;
265 u32 curr_freq;
266 bool keep_link_active;
267 bool enabled;
268 };
269
270 enum ufs_notify_change_status {
271 PRE_CHANGE,
272 POST_CHANGE,
273 };
274
275 struct ufs_pa_layer_attr {
276 u32 gear_rx;
277 u32 gear_tx;
278 u32 lane_rx;
279 u32 lane_tx;
280 u32 pwr_rx;
281 u32 pwr_tx;
282 u32 hs_rate;
283 };
284
285 struct ufs_pwr_mode_info {
286 bool is_valid;
287 struct ufs_pa_layer_attr info;
288 };
289
290 /**
291 * struct ufs_hba_variant_ops - variant specific callbacks
292 * @name: variant name
293 * @max_num_rtt: maximum RTT supported by the host
294 * @init: called when the driver is initialized
295 * @exit: called to cleanup everything done in init
296 * @set_dma_mask: For setting another DMA mask than indicated by the 64AS
297 * capability bit.
298 * @get_ufs_hci_version: called to get UFS HCI version
299 * @clk_scale_notify: notifies that clks are scaled up/down
300 * @setup_clocks: called before touching any of the controller registers
301 * @hce_enable_notify: called before and after HCE enable bit is set to allow
302 * variant specific Uni-Pro initialization.
303 * @link_startup_notify: called before and after Link startup is carried out
304 * to allow variant specific Uni-Pro initialization.
305 * @pwr_change_notify: called before and after a power mode change
306 * is carried out to allow vendor spesific capabilities
307 * to be set. PRE_CHANGE can modify final_params based
308 * on desired_pwr_mode, but POST_CHANGE must not alter
309 * the final_params parameter
310 * @setup_xfer_req: called before any transfer request is issued
311 * to set some things
312 * @setup_task_mgmt: called before any task management request is issued
313 * to set some things
314 * @hibern8_notify: called around hibern8 enter/exit
315 * @apply_dev_quirks: called to apply device specific quirks
316 * @fixup_dev_quirks: called to modify device specific quirks
317 * @suspend: called during host controller PM callback
318 * @resume: called during host controller PM callback
319 * @dbg_register_dump: used to dump controller debug information
320 * @phy_initialization: used to initialize phys
321 * @device_reset: called to issue a reset pulse on the UFS device
322 * @config_scaling_param: called to configure clock scaling parameters
323 * @fill_crypto_prdt: initialize crypto-related fields in the PRDT
324 * @event_notify: called to notify important events
325 * @mcq_config_resource: called to configure MCQ platform resources
326 * @get_hba_mac: reports maximum number of outstanding commands supported by
327 * the controller. Should be implemented for UFSHCI 4.0 or later
328 * controllers that are not compliant with the UFSHCI 4.0 specification.
329 * @op_runtime_config: called to config Operation and runtime regs Pointers
330 * @get_outstanding_cqs: called to get outstanding completion queues
331 * @config_esi: called to config Event Specific Interrupt
332 * @config_scsi_dev: called to configure SCSI device parameters
333 * @freq_to_gear_speed: called to map clock frequency to the max supported gear speed
334 */
335 struct ufs_hba_variant_ops {
336 const char *name;
337 int max_num_rtt;
338 int (*init)(struct ufs_hba *);
339 void (*exit)(struct ufs_hba *);
340 u32 (*get_ufs_hci_version)(struct ufs_hba *);
341 int (*set_dma_mask)(struct ufs_hba *);
342 int (*clk_scale_notify)(struct ufs_hba *, bool, unsigned long,
343 enum ufs_notify_change_status);
344 int (*setup_clocks)(struct ufs_hba *, bool,
345 enum ufs_notify_change_status);
346 int (*hce_enable_notify)(struct ufs_hba *,
347 enum ufs_notify_change_status);
348 int (*link_startup_notify)(struct ufs_hba *,
349 enum ufs_notify_change_status);
350 int (*pwr_change_notify)(struct ufs_hba *,
351 enum ufs_notify_change_status status,
352 const struct ufs_pa_layer_attr *desired_pwr_mode,
353 struct ufs_pa_layer_attr *final_params);
354 void (*setup_xfer_req)(struct ufs_hba *hba, int tag,
355 bool is_scsi_cmd);
356 void (*setup_task_mgmt)(struct ufs_hba *, int, u8);
357 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
358 enum ufs_notify_change_status);
359 int (*apply_dev_quirks)(struct ufs_hba *hba);
360 void (*fixup_dev_quirks)(struct ufs_hba *hba);
361 int (*suspend)(struct ufs_hba *, enum ufs_pm_op,
362 enum ufs_notify_change_status);
363 int (*resume)(struct ufs_hba *, enum ufs_pm_op);
364 void (*dbg_register_dump)(struct ufs_hba *hba);
365 int (*phy_initialization)(struct ufs_hba *);
366 int (*device_reset)(struct ufs_hba *hba);
367 void (*config_scaling_param)(struct ufs_hba *hba,
368 struct devfreq_dev_profile *profile,
369 struct devfreq_simple_ondemand_data *data);
370 int (*fill_crypto_prdt)(struct ufs_hba *hba,
371 const struct bio_crypt_ctx *crypt_ctx,
372 void *prdt, unsigned int num_segments);
373 void (*event_notify)(struct ufs_hba *hba,
374 enum ufs_event_type evt, void *data);
375 int (*mcq_config_resource)(struct ufs_hba *hba);
376 int (*get_hba_mac)(struct ufs_hba *hba);
377 int (*op_runtime_config)(struct ufs_hba *hba);
378 int (*get_outstanding_cqs)(struct ufs_hba *hba,
379 unsigned long *ocqs);
380 int (*config_esi)(struct ufs_hba *hba);
381 void (*config_scsi_dev)(struct scsi_device *sdev);
382 u32 (*freq_to_gear_speed)(struct ufs_hba *hba, unsigned long freq);
383 };
384
385 /* clock gating state */
386 enum clk_gating_state {
387 CLKS_OFF,
388 CLKS_ON,
389 REQ_CLKS_OFF,
390 REQ_CLKS_ON,
391 };
392
393 /**
394 * struct ufs_clk_gating - UFS clock gating related info
395 * @gate_work: worker to turn off clocks after some delay as specified in
396 * delay_ms
397 * @ungate_work: worker to turn on clocks that will be used in case of
398 * interrupt context
399 * @clk_gating_workq: workqueue for clock gating work.
400 * @lock: serialize access to some struct ufs_clk_gating members. An outer lock
401 * relative to the host lock
402 * @state: the current clocks state
403 * @delay_ms: gating delay in ms
404 * @is_suspended: clk gating is suspended when set to 1 which can be used
405 * during suspend/resume
406 * @delay_attr: sysfs attribute to control delay_attr
407 * @enable_attr: sysfs attribute to enable/disable clock gating
408 * @is_enabled: Indicates the current status of clock gating
409 * @is_initialized: Indicates whether clock gating is initialized or not
410 * @active_reqs: number of requests that are pending and should be waited for
411 * completion before gating clocks.
412 */
413 struct ufs_clk_gating {
414 struct delayed_work gate_work;
415 struct work_struct ungate_work;
416 struct workqueue_struct *clk_gating_workq;
417
418 spinlock_t lock;
419
420 enum clk_gating_state state;
421 unsigned long delay_ms;
422 bool is_suspended;
423 struct device_attribute delay_attr;
424 struct device_attribute enable_attr;
425 bool is_enabled;
426 bool is_initialized;
427 int active_reqs;
428 };
429
430 /**
431 * struct ufs_clk_scaling - UFS clock scaling related data
432 * @workq: workqueue to schedule devfreq suspend/resume work
433 * @suspend_work: worker to suspend devfreq
434 * @resume_work: worker to resume devfreq
435 * @lock: serialize access to some struct ufs_clk_scaling members
436 * @active_reqs: number of requests that are pending. If this is zero when
437 * devfreq ->target() function is called then schedule "suspend_work" to
438 * suspend devfreq.
439 * @tot_busy_t: Total busy time in current polling window
440 * @window_start_t: Start time (in jiffies) of the current polling window
441 * @busy_start_t: Start time of current busy period
442 * @enable_attr: sysfs attribute to enable/disable clock scaling
443 * @saved_pwr_info: UFS power mode may also be changed during scaling and this
444 * one keeps track of previous power mode.
445 * @target_freq: frequency requested by devfreq framework
446 * @min_gear: lowest HS gear to scale down to
447 * @wb_gear: enable Write Booster when HS gear scales above or equal to it, else
448 * disable Write Booster
449 * @is_enabled: tracks if scaling is currently enabled or not, controlled by
450 * clkscale_enable sysfs node
451 * @is_allowed: tracks if scaling is currently allowed or not, used to block
452 * clock scaling which is not invoked from devfreq governor
453 * @is_initialized: Indicates whether clock scaling is initialized or not
454 * @is_busy_started: tracks if busy period has started or not
455 * @is_suspended: tracks if devfreq is suspended or not
456 */
457 struct ufs_clk_scaling {
458 struct workqueue_struct *workq;
459 struct work_struct suspend_work;
460 struct work_struct resume_work;
461
462 spinlock_t lock;
463
464 int active_reqs;
465 unsigned long tot_busy_t;
466 ktime_t window_start_t;
467 ktime_t busy_start_t;
468 struct device_attribute enable_attr;
469 struct ufs_pa_layer_attr saved_pwr_info;
470 unsigned long target_freq;
471 u32 min_gear;
472 u32 wb_gear;
473 bool is_enabled;
474 bool is_allowed;
475 bool is_initialized;
476 bool is_busy_started;
477 bool is_suspended;
478 bool suspend_on_no_request;
479 };
480
481 #define UFS_EVENT_HIST_LENGTH 8
482 /**
483 * struct ufs_event_hist - keeps history of errors
484 * @pos: index to indicate cyclic buffer position
485 * @val: cyclic buffer for registers value
486 * @tstamp: cyclic buffer for time stamp
487 * @cnt: error counter
488 */
489 struct ufs_event_hist {
490 int pos;
491 u32 val[UFS_EVENT_HIST_LENGTH];
492 u64 tstamp[UFS_EVENT_HIST_LENGTH];
493 unsigned long long cnt;
494 };
495
496 /**
497 * struct ufs_stats - keeps usage/err statistics
498 * @hibern8_exit_cnt: Counter to keep track of number of exits,
499 * reset this after link-startup.
500 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
501 * Clear after the first successful command completion.
502 * @event: array with event history.
503 */
504 struct ufs_stats {
505 u32 hibern8_exit_cnt;
506 u64 last_hibern8_exit_tstamp;
507 struct ufs_event_hist event[UFS_EVT_CNT];
508 };
509
510 /**
511 * enum ufshcd_state - UFS host controller state
512 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command
513 * processing.
514 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process
515 * SCSI commands.
516 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled.
517 * SCSI commands may be submitted to the controller.
518 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail
519 * newly submitted SCSI commands with error code DID_BAD_TARGET.
520 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery
521 * failed. Fail all SCSI commands with error code DID_ERROR.
522 */
523 enum ufshcd_state {
524 UFSHCD_STATE_RESET,
525 UFSHCD_STATE_OPERATIONAL,
526 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,
527 UFSHCD_STATE_EH_SCHEDULED_FATAL,
528 UFSHCD_STATE_ERROR,
529 };
530
531 enum ufshcd_quirks {
532 /* Interrupt aggregation support is broken */
533 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0,
534
535 /*
536 * delay before each dme command is required as the unipro
537 * layer has shown instabilities
538 */
539 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1,
540
541 /*
542 * If UFS host controller is having issue in processing LCC (Line
543 * Control Command) coming from device then enable this quirk.
544 * When this quirk is enabled, host controller driver should disable
545 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
546 * attribute of device to 0).
547 */
548 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2,
549
550 /*
551 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
552 * inbound Link supports unterminated line in HS mode. Setting this
553 * attribute to 1 fixes moving to HS gear.
554 */
555 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3,
556
557 /*
558 * This quirk needs to be enabled if the host controller only allows
559 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
560 * SLOW AUTO).
561 */
562 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4,
563
564 /*
565 * This quirk needs to be enabled if the host controller doesn't
566 * advertise the correct version in UFS_VER register. If this quirk
567 * is enabled, standard UFS host driver will call the vendor specific
568 * ops (get_ufs_hci_version) to get the correct version.
569 */
570 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
571
572 /*
573 * Clear handling for transfer/task request list is just opposite.
574 */
575 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6,
576
577 /*
578 * This quirk needs to be enabled if host controller doesn't allow
579 * that the interrupt aggregation timer and counter are reset by s/w.
580 */
581 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
582
583 /*
584 * This quirks needs to be enabled if host controller cannot be
585 * enabled via HCE register.
586 */
587 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
588
589 /*
590 * This quirk needs to be enabled if the host controller regards
591 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
592 */
593 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
594
595 /*
596 * This quirk needs to be enabled if the host controller reports
597 * OCS FATAL ERROR with device error through sense data
598 */
599 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,
600
601 /*
602 * This quirk needs to be enabled if the host controller has
603 * auto-hibernate capability but it doesn't work.
604 */
605 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11,
606
607 /*
608 * This quirk needs to disable manual flush for write booster
609 */
610 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12,
611
612 /*
613 * This quirk needs to disable unipro timeout values
614 * before power mode change
615 */
616 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
617
618 /*
619 * This quirk needs to be enabled if the host controller does not
620 * support UIC command
621 */
622 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15,
623
624 /*
625 * This quirk needs to be enabled if the host controller cannot
626 * support physical host configuration.
627 */
628 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16,
629
630 /*
631 * This quirk needs to be enabled if the host controller has
632 * auto-hibernate capability but it's FASTAUTO only.
633 */
634 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18,
635
636 /*
637 * This quirk needs to be enabled if the host controller needs
638 * to reinit the device after switching to maximum gear.
639 */
640 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19,
641
642 /*
643 * Some host raises interrupt (per queue) in addition to
644 * CQES (traditional) when ESI is disabled.
645 * Enable this quirk will disable CQES and use per queue interrupt.
646 */
647 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20,
648
649 /*
650 * Some host does not implement SQ Run Time Command (SQRTC) register
651 * thus need this quirk to skip related flow.
652 */
653 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21,
654
655 /*
656 * This quirk needs to be enabled if the host controller supports inline
657 * encryption but it needs to initialize the crypto capabilities in a
658 * nonstandard way and/or needs to override blk_crypto_ll_ops. If
659 * enabled, the standard code won't initialize the blk_crypto_profile;
660 * ufs_hba_variant_ops::init() must do it instead.
661 */
662 UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE = 1 << 22,
663
664 /*
665 * This quirk needs to be enabled if the host controller supports inline
666 * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e.
667 * host controller initialization fails if that bit is set.
668 */
669 UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE = 1 << 23,
670
671 /*
672 * This quirk needs to be enabled if the host controller driver copies
673 * cryptographic keys into the PRDT in order to send them to hardware,
674 * and therefore the PRDT should be zeroized after each request (as per
675 * the standard best practice for managing keys).
676 */
677 UFSHCD_QUIRK_KEYS_IN_PRDT = 1 << 24,
678
679 /*
680 * This quirk indicates that the controller reports the value 1 (not
681 * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the
682 * Controller Capabilities register although it supports the legacy
683 * single doorbell mode.
684 */
685 UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25,
686
687 /*
688 * This quirk indicates that DME_LINKSTARTUP should not be issued a 2nd
689 * time (refer link_startup_again) after the 1st time was successful,
690 * because it causes link startup to become unreliable.
691 */
692 UFSHCD_QUIRK_PERFORM_LINK_STARTUP_ONCE = 1 << 26,
693 };
694
695 enum ufshcd_caps {
696 /* Allow dynamic clk gating */
697 UFSHCD_CAP_CLK_GATING = 1 << 0,
698
699 /* Allow hiberb8 with clk gating */
700 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1,
701
702 /* Allow dynamic clk scaling */
703 UFSHCD_CAP_CLK_SCALING = 1 << 2,
704
705 /* Allow auto bkops to enabled during runtime suspend */
706 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3,
707
708 /*
709 * This capability allows host controller driver to use the UFS HCI's
710 * interrupt aggregation capability.
711 * CAUTION: Enabling this might reduce overall UFS throughput.
712 */
713 UFSHCD_CAP_INTR_AGGR = 1 << 4,
714
715 /*
716 * This capability allows the device auto-bkops to be always enabled
717 * except during suspend (both runtime and suspend).
718 * Enabling this capability means that device will always be allowed
719 * to do background operation when it's active but it might degrade
720 * the performance of ongoing read/write operations.
721 */
722 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,
723
724 /*
725 * This capability allows host controller driver to automatically
726 * enable runtime power management by itself instead of waiting
727 * for userspace to control the power management.
728 */
729 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6,
730
731 /*
732 * This capability allows the host controller driver to turn-on
733 * WriteBooster, if the underlying device supports it and is
734 * provisioned to be used. This would increase the write performance.
735 */
736 UFSHCD_CAP_WB_EN = 1 << 7,
737
738 /*
739 * This capability allows the host controller driver to use the
740 * inline crypto engine, if it is present
741 */
742 UFSHCD_CAP_CRYPTO = 1 << 8,
743
744 /*
745 * This capability allows the controller regulators to be put into
746 * lpm mode aggressively during clock gating.
747 * This would increase power savings.
748 */
749 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9,
750
751 /*
752 * This capability allows the host controller driver to use DeepSleep,
753 * if it is supported by the UFS device. The host controller driver must
754 * support device hardware reset via the hba->device_reset() callback,
755 * in order to exit DeepSleep state.
756 */
757 UFSHCD_CAP_DEEPSLEEP = 1 << 10,
758
759 /*
760 * This capability allows the host controller driver to use temperature
761 * notification if it is supported by the UFS device.
762 */
763 UFSHCD_CAP_TEMP_NOTIF = 1 << 11,
764
765 /*
766 * Enable WriteBooster when scaling up the clock and disable
767 * WriteBooster when scaling the clock down.
768 */
769 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12,
770 };
771
772 struct ufs_hba_variant_params {
773 struct devfreq_dev_profile devfreq_profile;
774 struct devfreq_simple_ondemand_data ondemand_data;
775 u16 hba_enable_delay_us;
776 u32 wb_flush_threshold;
777 };
778
779 struct ufs_hba_monitor {
780 unsigned long chunk_size;
781
782 unsigned long nr_sec_rw[2];
783 ktime_t total_busy[2];
784
785 unsigned long nr_req[2];
786 /* latencies*/
787 ktime_t lat_sum[2];
788 ktime_t lat_max[2];
789 ktime_t lat_min[2];
790
791 u32 nr_queued[2];
792 ktime_t busy_start_ts[2];
793
794 ktime_t enabled_ts;
795 bool enabled;
796 };
797
798 /**
799 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
800 *
801 * @offset: Doorbell Address Offset
802 * @stride: Steps proportional to queue [0...31]
803 * @base: base address
804 */
805 struct ufshcd_mcq_opr_info_t {
806 unsigned long offset;
807 unsigned long stride;
808 void __iomem *base;
809 };
810
811 enum ufshcd_mcq_opr {
812 OPR_SQD,
813 OPR_SQIS,
814 OPR_CQD,
815 OPR_CQIS,
816 OPR_MAX,
817 };
818
819 /**
820 * struct ufs_hba - per adapter private structure
821 * @mmio_base: UFSHCI base register address
822 * @ucdl_base_addr: UFS Command Descriptor base address
823 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
824 * @utmrdl_base_addr: UTP Task Management Descriptor base address
825 * @ucdl_dma_addr: UFS Command Descriptor DMA address
826 * @utrdl_dma_addr: UTRDL DMA address
827 * @utmrdl_dma_addr: UTMRDL DMA address
828 * @host: Scsi_Host instance of the driver
829 * @dev: device handle
830 * @ufs_device_wlun: WLUN that controls the entire UFS device.
831 * @ufs_rpmb_wlun: RPMB WLUN SCSI device
832 * @hwmon_device: device instance registered with the hwmon core.
833 * @curr_dev_pwr_mode: active UFS device power mode.
834 * @uic_link_state: active state of the link to the UFS device.
835 * @rpm_lvl: desired UFS power management level during runtime PM.
836 * @spm_lvl: desired UFS power management level during system PM.
837 * @pm_op_in_progress: whether or not a PM operation is in progress.
838 * @ahit: value of Auto-Hibernate Idle Timer register.
839 * @outstanding_tasks: Bits representing outstanding task requests
840 * @outstanding_lock: Protects @outstanding_reqs.
841 * @outstanding_reqs: Bits representing outstanding transfer requests
842 * @capabilities: UFS Controller Capabilities
843 * @mcq_capabilities: UFS Multi Circular Queue capabilities
844 * @nutrs: Transfer Request Queue depth supported by controller
845 * @nortt - Max outstanding RTTs supported by controller
846 * @nutmrs: Task Management Queue depth supported by controller
847 * @ufs_version: UFS Version to which controller complies
848 * @vops: pointer to variant specific operations
849 * @vps: pointer to variant specific parameters
850 * @priv: pointer to variant specific private data
851 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields)
852 * @irq: Irq number of the controller
853 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled.
854 * @dev_ref_clk_freq: reference clock frequency
855 * @quirks: bitmask with information about deviations from the UFSHCI standard.
856 * @dev_quirks: bitmask with information about deviations from the UFS standard.
857 * @tmf_tag_set: TMF tag set.
858 * @tmf_queue: Used to allocate TMF tags.
859 * @tmf_rqs: array with pointers to TMF requests while these are in progress.
860 * @active_uic_cmd: pointer to active UIC command.
861 * @uic_cmd_mutex: mutex used for serializing UIC command processing.
862 * @uic_async_done: completion used to wait for power mode or hibernation state
863 * changes.
864 * @ufshcd_state: UFSHCD state
865 * @eh_flags: Error handling flags
866 * @intr_mask: Interrupt Mask Bits
867 * @ee_ctrl_mask: Exception event control mask
868 * @ee_drv_mask: Exception event mask for driver
869 * @ee_usr_mask: Exception event mask for user (set via debugfs)
870 * @ee_ctrl_mutex: Used to serialize exception event information.
871 * @is_powered: flag to check if HBA is powered
872 * @shutting_down: flag to check if shutdown has been invoked
873 * @host_sem: semaphore used to serialize concurrent contexts
874 * @eh_wq: Workqueue that eh_work works on
875 * @eh_work: Worker to handle UFS errors that require s/w attention
876 * @eeh_work: Worker to handle exception events
877 * @errors: HBA errors
878 * @uic_error: UFS interconnect layer error status
879 * @saved_err: sticky error mask
880 * @saved_uic_err: sticky UIC error mask
881 * @ufs_stats: various error counters
882 * @force_reset: flag to force eh_work perform a full reset
883 * @force_pmc: flag to force a power mode change
884 * @silence_err_logs: flag to silence error logs
885 * @dev_cmd: ufs device management command information
886 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
887 * @nop_out_timeout: NOP OUT timeout value
888 * @dev_info: information about the UFS device
889 * @auto_bkops_enabled: to track whether bkops is enabled in device
890 * @vreg_info: UFS device voltage regulator information
891 * @clk_list_head: UFS host controller clocks list node head
892 * @use_pm_opp: Indicates whether OPP based scaling is used or not
893 * @req_abort_count: number of times ufshcd_abort() has been called
894 * @lanes_per_direction: number of lanes per data direction between the UFS
895 * controller and the UFS device.
896 * @pwr_info: holds current power mode
897 * @max_pwr_info: keeps the device max valid pwm
898 * @clk_gating: information related to clock gating
899 * @caps: bitmask with information about UFS controller capabilities
900 * @devfreq: frequency scaling information owned by the devfreq core
901 * @clk_scaling: frequency scaling information owned by the UFS driver
902 * @system_suspending: system suspend has been started and system resume has
903 * not yet finished.
904 * @is_sys_suspended: UFS device has been suspended because of system suspend
905 * @urgent_bkops_lvl: keeps track of urgent bkops level for device
906 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
907 * device is known or not.
908 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling
909 * @clk_scaling_lock: used to serialize device commands and clock scaling
910 * @desc_size: descriptor sizes reported by device
911 * @bsg_dev: struct device associated with the BSG queue
912 * @bsg_queue: BSG queue associated with the UFS controller
913 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power
914 * management) after the UFS device has finished a WriteBooster buffer
915 * flush or auto BKOP.
916 * @monitor: statistics about UFS commands
917 * @crypto_capabilities: Content of crypto capabilities register (0x100)
918 * @crypto_cap_array: Array of crypto capabilities
919 * @crypto_cfg_register: Start of the crypto cfg array
920 * @crypto_profile: the crypto profile of this hba (if applicable)
921 * @debugfs_root: UFS controller debugfs root directory
922 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay
923 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore
924 * ee_ctrl_mask
925 * @luns_avail: number of regular and well known LUNs supported by the UFS
926 * device
927 * @nr_hw_queues: number of hardware queues configured
928 * @nr_queues: number of Queues of different queue types
929 * @complete_put: whether or not to call ufshcd_rpm_put() from inside
930 * ufshcd_resume_complete()
931 * @mcq_sup: is mcq supported by UFSHC
932 * @mcq_enabled: is mcq ready to accept requests
933 * @mcq_esi_enabled: is mcq ESI configured
934 * @res: array of resource info of MCQ registers
935 * @mcq_base: Multi circular queue registers base address
936 * @uhq: array of supported hardware queues
937 * @mcq_opr: MCQ operation and runtime registers
938 * @ufs_rtc_update_work: A work for UFS RTC periodic update
939 * @pm_qos_req: PM QoS request handle
940 * @pm_qos_enabled: flag to check if pm qos is enabled
941 * @pm_qos_mutex: synchronizes PM QoS request and status updates
942 * @critical_health_count: count of critical health exceptions
943 * @dev_lvl_exception_count: count of device level exceptions since last reset
944 * @dev_lvl_exception_id: vendor specific information about the device level exception event.
945 * @rpmbs: list of OP-TEE RPMB devices (one per RPMB region)
946 */
947 struct ufs_hba {
948 void __iomem *mmio_base;
949
950 /* Virtual memory reference */
951 struct utp_transfer_cmd_desc *ucdl_base_addr;
952 struct utp_transfer_req_desc *utrdl_base_addr;
953 struct utp_task_req_desc *utmrdl_base_addr;
954
955 /* DMA memory reference */
956 dma_addr_t ucdl_dma_addr;
957 dma_addr_t utrdl_dma_addr;
958 dma_addr_t utmrdl_dma_addr;
959
960 struct Scsi_Host *host;
961 struct device *dev;
962 struct scsi_device *ufs_device_wlun;
963 struct scsi_device *ufs_rpmb_wlun;
964
965 #ifdef CONFIG_SCSI_UFS_HWMON
966 struct device *hwmon_device;
967 #endif
968
969 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
970 enum uic_link_state uic_link_state;
971 /* Desired UFS power management level during runtime PM */
972 enum ufs_pm_level rpm_lvl;
973 /* Desired UFS power management level during system PM */
974 enum ufs_pm_level spm_lvl;
975 int pm_op_in_progress;
976
977 /* Auto-Hibernate Idle Timer register value */
978 u32 ahit;
979
980 unsigned long outstanding_tasks;
981 spinlock_t outstanding_lock;
982 unsigned long outstanding_reqs;
983
984 u32 capabilities;
985 int nutrs;
986 int nortt;
987 u32 mcq_capabilities;
988 int nutmrs;
989 u32 ufs_version;
990 const struct ufs_hba_variant_ops *vops;
991 struct ufs_hba_variant_params *vps;
992 void *priv;
993 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
994 size_t sg_entry_size;
995 #endif
996 unsigned int irq;
997 bool is_irq_enabled;
998 enum ufs_ref_clk_freq dev_ref_clk_freq;
999
1000 unsigned int quirks; /* Deviations from standard UFSHCI spec. */
1001
1002 /* Device deviations from standard UFS device spec. */
1003 unsigned int dev_quirks;
1004
1005 struct blk_mq_tag_set tmf_tag_set;
1006 struct request_queue *tmf_queue;
1007 struct request **tmf_rqs;
1008
1009 struct uic_command *active_uic_cmd;
1010 struct mutex uic_cmd_mutex;
1011 struct completion *uic_async_done;
1012
1013 enum ufshcd_state ufshcd_state;
1014 u32 eh_flags;
1015 u32 intr_mask;
1016 u16 ee_ctrl_mask;
1017 u16 ee_drv_mask;
1018 u16 ee_usr_mask;
1019 struct mutex ee_ctrl_mutex;
1020 bool is_powered;
1021 bool shutting_down;
1022 struct semaphore host_sem;
1023
1024 /* Work Queues */
1025 struct workqueue_struct *eh_wq;
1026 struct work_struct eh_work;
1027 struct work_struct eeh_work;
1028
1029 /* HBA Errors */
1030 u32 errors;
1031 u32 uic_error;
1032 u32 saved_err;
1033 u32 saved_uic_err;
1034 struct ufs_stats ufs_stats;
1035 bool force_reset;
1036 bool force_pmc;
1037 bool silence_err_logs;
1038
1039 /* Device management request data */
1040 struct ufs_dev_cmd dev_cmd;
1041 ktime_t last_dme_cmd_tstamp;
1042 int nop_out_timeout;
1043
1044 /* Keeps information of the UFS device connected to this host */
1045 struct ufs_dev_info dev_info;
1046 bool auto_bkops_enabled;
1047 struct ufs_vreg_info vreg_info;
1048 struct list_head clk_list_head;
1049 bool use_pm_opp;
1050
1051 /* Number of requests aborts */
1052 int req_abort_count;
1053
1054 /* Number of lanes available (1 or 2) for Rx/Tx */
1055 u32 lanes_per_direction;
1056 struct ufs_pa_layer_attr pwr_info;
1057 struct ufs_pwr_mode_info max_pwr_info;
1058
1059 struct ufs_clk_gating clk_gating;
1060 /* Control to enable/disable host capabilities */
1061 u32 caps;
1062
1063 struct devfreq *devfreq;
1064 struct ufs_clk_scaling clk_scaling;
1065 bool system_suspending;
1066 bool is_sys_suspended;
1067
1068 enum bkops_status urgent_bkops_lvl;
1069 bool is_urgent_bkops_lvl_checked;
1070
1071 struct mutex wb_mutex;
1072 struct rw_semaphore clk_scaling_lock;
1073
1074 struct device bsg_dev;
1075 struct request_queue *bsg_queue;
1076 struct delayed_work rpm_dev_flush_recheck_work;
1077
1078 struct ufs_hba_monitor monitor;
1079
1080 #ifdef CONFIG_SCSI_UFS_CRYPTO
1081 union ufs_crypto_capabilities crypto_capabilities;
1082 union ufs_crypto_cap_entry *crypto_cap_array;
1083 u32 crypto_cfg_register;
1084 struct blk_crypto_profile crypto_profile;
1085 #endif
1086 #ifdef CONFIG_DEBUG_FS
1087 struct dentry *debugfs_root;
1088 struct delayed_work debugfs_ee_work;
1089 u32 debugfs_ee_rate_limit_ms;
1090 #endif
1091 #ifdef CONFIG_SCSI_UFS_FAULT_INJECTION
1092 struct fault_attr trigger_eh_attr;
1093 struct fault_attr timeout_attr;
1094 #endif
1095 u32 luns_avail;
1096 unsigned int nr_hw_queues;
1097 unsigned int nr_queues[HCTX_MAX_TYPES];
1098 bool complete_put;
1099 bool scsi_host_added;
1100 bool mcq_sup;
1101 bool lsdb_sup;
1102 bool mcq_enabled;
1103 bool mcq_esi_enabled;
1104 void __iomem *mcq_base;
1105 struct ufs_hw_queue *uhq;
1106 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX];
1107
1108 struct delayed_work ufs_rtc_update_work;
1109 struct pm_qos_request pm_qos_req;
1110 bool pm_qos_enabled;
1111 /* synchronizes PM QoS request and status updates */
1112 struct mutex pm_qos_mutex;
1113
1114 int critical_health_count;
1115 atomic_t dev_lvl_exception_count;
1116 u64 dev_lvl_exception_id;
1117 u32 vcc_off_delay_us;
1118 struct list_head rpmbs;
1119 };
1120
1121 /**
1122 * struct ufs_hw_queue - per hardware queue structure
1123 * @mcq_sq_head: base address of submission queue head pointer
1124 * @mcq_sq_tail: base address of submission queue tail pointer
1125 * @mcq_cq_head: base address of completion queue head pointer
1126 * @mcq_cq_tail: base address of completion queue tail pointer
1127 * @sqe_base_addr: submission queue entry base address
1128 * @sqe_dma_addr: submission queue dma address
1129 * @cqe_base_addr: completion queue base address
1130 * @cqe_dma_addr: completion queue dma address
1131 * @max_entries: max number of slots in this hardware queue
1132 * @id: hardware queue ID
1133 * @sq_tp_slot: current slot to which SQ tail pointer is pointing
1134 * @sq_lock: serialize submission queue access
1135 * @cq_tail_slot: current slot to which CQ tail pointer is pointing
1136 * @cq_head_slot: current slot to which CQ head pointer is pointing
1137 * @cq_lock: Synchronize between multiple polling instances
1138 * @sq_mutex: prevent submission queue concurrent access
1139 */
1140 struct ufs_hw_queue {
1141 void __iomem *mcq_sq_head;
1142 void __iomem *mcq_sq_tail;
1143 void __iomem *mcq_cq_head;
1144 void __iomem *mcq_cq_tail;
1145
1146 struct utp_transfer_req_desc *sqe_base_addr;
1147 dma_addr_t sqe_dma_addr;
1148 struct cq_entry *cqe_base_addr;
1149 dma_addr_t cqe_dma_addr;
1150 u32 max_entries;
1151 u32 id;
1152 u32 sq_tail_slot;
1153 spinlock_t sq_lock;
1154 u32 cq_tail_slot;
1155 u32 cq_head_slot;
1156 spinlock_t cq_lock;
1157 /* prevent concurrent access to submission queue */
1158 struct mutex sq_mutex;
1159 };
1160
1161 #define MCQ_QCFG_SIZE 0x40
1162
ufshcd_mcq_opr_offset(struct ufs_hba * hba,enum ufshcd_mcq_opr opr,int idx)1163 static inline unsigned int ufshcd_mcq_opr_offset(struct ufs_hba *hba,
1164 enum ufshcd_mcq_opr opr, int idx)
1165 {
1166 return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx;
1167 }
1168
ufshcd_mcq_cfg_offset(unsigned int reg,int idx)1169 static inline unsigned int ufshcd_mcq_cfg_offset(unsigned int reg, int idx)
1170 {
1171 return reg + MCQ_QCFG_SIZE * idx;
1172 }
1173
1174 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
ufshcd_sg_entry_size(const struct ufs_hba * hba)1175 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1176 {
1177 return hba->sg_entry_size;
1178 }
1179
ufshcd_set_sg_entry_size(struct ufs_hba * hba,size_t sg_entry_size)1180 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size)
1181 {
1182 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry));
1183 hba->sg_entry_size = sg_entry_size;
1184 }
1185 #else
ufshcd_sg_entry_size(const struct ufs_hba * hba)1186 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1187 {
1188 return sizeof(struct ufshcd_sg_entry);
1189 }
1190
1191 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \
1192 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); })
1193 #endif
1194
1195 #ifdef CONFIG_SCSI_UFS_CRYPTO
1196 static inline struct ufs_hba *
ufs_hba_from_crypto_profile(struct blk_crypto_profile * profile)1197 ufs_hba_from_crypto_profile(struct blk_crypto_profile *profile)
1198 {
1199 return container_of(profile, struct ufs_hba, crypto_profile);
1200 }
1201 #endif
1202
ufshcd_get_ucd_size(const struct ufs_hba * hba)1203 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba)
1204 {
1205 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba);
1206 }
1207
1208 /* Returns true if clocks can be gated. Otherwise false */
ufshcd_is_clkgating_allowed(struct ufs_hba * hba)1209 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
1210 {
1211 return hba->caps & UFSHCD_CAP_CLK_GATING;
1212 }
ufshcd_can_hibern8_during_gating(struct ufs_hba * hba)1213 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
1214 {
1215 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1216 }
ufshcd_is_clkscaling_supported(struct ufs_hba * hba)1217 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
1218 {
1219 return hba->caps & UFSHCD_CAP_CLK_SCALING;
1220 }
ufshcd_can_autobkops_during_suspend(struct ufs_hba * hba)1221 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
1222 {
1223 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1224 }
ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba * hba)1225 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
1226 {
1227 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
1228 }
1229
ufshcd_is_intr_aggr_allowed(struct ufs_hba * hba)1230 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
1231 {
1232 return (hba->caps & UFSHCD_CAP_INTR_AGGR) &&
1233 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR);
1234 }
1235
ufshcd_can_aggressive_pc(struct ufs_hba * hba)1236 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba)
1237 {
1238 return !!(ufshcd_is_link_hibern8(hba) &&
1239 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));
1240 }
1241
ufshcd_is_auto_hibern8_supported(struct ufs_hba * hba)1242 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
1243 {
1244 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&
1245 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);
1246 }
1247
ufshcd_is_auto_hibern8_enabled(struct ufs_hba * hba)1248 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)
1249 {
1250 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit);
1251 }
1252
ufshcd_is_wb_allowed(struct ufs_hba * hba)1253 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)
1254 {
1255 return hba->caps & UFSHCD_CAP_WB_EN;
1256 }
1257
ufshcd_enable_wb_if_scaling_up(struct ufs_hba * hba)1258 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba)
1259 {
1260 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;
1261 }
1262
1263 #define ufsmcq_writel(hba, val, reg) \
1264 writel((val), (hba)->mcq_base + (reg))
1265 #define ufsmcq_readl(hba, reg) \
1266 readl((hba)->mcq_base + (reg))
1267
1268 #define ufsmcq_writelx(hba, val, reg) \
1269 writel_relaxed((val), (hba)->mcq_base + (reg))
1270 #define ufsmcq_readlx(hba, reg) \
1271 readl_relaxed((hba)->mcq_base + (reg))
1272
1273 #define ufshcd_writel(hba, val, reg) \
1274 writel((val), (hba)->mmio_base + (reg))
1275 #define ufshcd_readl(hba, reg) \
1276 readl((hba)->mmio_base + (reg))
1277
1278 /**
1279 * ufshcd_rmwl - perform read/modify/write for a controller register
1280 * @hba: per adapter instance
1281 * @mask: mask to apply on read value
1282 * @val: actual value to write
1283 * @reg: register address
1284 */
ufshcd_rmwl(struct ufs_hba * hba,u32 mask,u32 val,u32 reg)1285 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
1286 {
1287 u32 tmp;
1288
1289 tmp = ufshcd_readl(hba, reg);
1290 tmp &= ~mask;
1291 tmp |= (val & mask);
1292 ufshcd_writel(hba, tmp, reg);
1293 }
1294
1295 void ufshcd_enable_irq(struct ufs_hba *hba);
1296 void ufshcd_disable_irq(struct ufs_hba *hba);
1297 int ufshcd_alloc_host(struct device *, struct ufs_hba **);
1298 int ufshcd_hba_enable(struct ufs_hba *hba);
1299 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
1300 int ufshcd_link_recovery(struct ufs_hba *hba);
1301 int ufshcd_make_hba_operational(struct ufs_hba *hba);
1302 void ufshcd_remove(struct ufs_hba *);
1303 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
1304 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
1305 void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
1306 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
1307 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);
1308 void ufshcd_hba_stop(struct ufs_hba *hba);
1309 void ufshcd_schedule_eh_work(struct ufs_hba *hba);
1310 void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds);
1311 unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba);
1312 u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i);
1313 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i);
1314 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,
1315 struct ufs_hw_queue *hwq);
1316 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba);
1317 void ufshcd_mcq_enable(struct ufs_hba *hba);
1318 void ufshcd_mcq_enable_esi(struct ufs_hba *hba);
1319 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);
1320
1321 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
1322 struct dev_pm_opp *opp, void *data,
1323 bool scaling_down);
1324 /**
1325 * ufshcd_set_variant - set variant specific data to the hba
1326 * @hba: per adapter instance
1327 * @variant: pointer to variant specific data
1328 */
ufshcd_set_variant(struct ufs_hba * hba,void * variant)1329 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
1330 {
1331 BUG_ON(!hba);
1332 hba->priv = variant;
1333 }
1334
1335 /**
1336 * ufshcd_get_variant - get variant specific data from the hba
1337 * @hba: per adapter instance
1338 */
ufshcd_get_variant(struct ufs_hba * hba)1339 static inline void *ufshcd_get_variant(struct ufs_hba *hba)
1340 {
1341 BUG_ON(!hba);
1342 return hba->priv;
1343 }
1344
1345 #ifdef CONFIG_PM
1346 extern int ufshcd_runtime_suspend(struct device *dev);
1347 extern int ufshcd_runtime_resume(struct device *dev);
1348 #endif
1349 #ifdef CONFIG_PM_SLEEP
1350 extern int ufshcd_system_suspend(struct device *dev);
1351 extern int ufshcd_system_resume(struct device *dev);
1352 extern int ufshcd_system_freeze(struct device *dev);
1353 extern int ufshcd_system_thaw(struct device *dev);
1354 extern int ufshcd_system_restore(struct device *dev);
1355 #endif
1356
1357 extern int ufshcd_dme_reset(struct ufs_hba *hba);
1358 extern int ufshcd_dme_enable(struct ufs_hba *hba);
1359 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
1360 int agreed_gear,
1361 int adapt_val);
1362 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
1363 u8 attr_set, u32 mib_val, u8 peer);
1364 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
1365 u32 *mib_val, u8 peer);
1366 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
1367 struct ufs_pa_layer_attr *desired_pwr_mode);
1368 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode);
1369
1370 /* UIC command interfaces for DME primitives */
1371 #define DME_LOCAL 0
1372 #define DME_PEER 1
1373 #define ATTR_SET_NOR 0 /* NORMAL */
1374 #define ATTR_SET_ST 1 /* STATIC */
1375
ufshcd_dme_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1376 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
1377 u32 mib_val)
1378 {
1379 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1380 mib_val, DME_LOCAL);
1381 }
1382
ufshcd_dme_st_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1383 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
1384 u32 mib_val)
1385 {
1386 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1387 mib_val, DME_LOCAL);
1388 }
1389
ufshcd_dme_peer_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1390 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
1391 u32 mib_val)
1392 {
1393 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1394 mib_val, DME_PEER);
1395 }
1396
ufshcd_dme_peer_st_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1397 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
1398 u32 mib_val)
1399 {
1400 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1401 mib_val, DME_PEER);
1402 }
1403
ufshcd_dme_get(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val)1404 static inline int ufshcd_dme_get(struct ufs_hba *hba,
1405 u32 attr_sel, u32 *mib_val)
1406 {
1407 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
1408 }
1409
ufshcd_dme_peer_get(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val)1410 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
1411 u32 attr_sel, u32 *mib_val)
1412 {
1413 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
1414 }
1415
ufshcd_is_hs_mode(const struct ufs_pa_layer_attr * pwr_info)1416 static inline bool ufshcd_is_hs_mode(const struct ufs_pa_layer_attr *pwr_info)
1417 {
1418 return (pwr_info->pwr_rx == FAST_MODE ||
1419 pwr_info->pwr_rx == FASTAUTO_MODE) &&
1420 (pwr_info->pwr_tx == FAST_MODE ||
1421 pwr_info->pwr_tx == FASTAUTO_MODE);
1422 }
1423
ufshcd_disable_host_tx_lcc(struct ufs_hba * hba)1424 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)
1425 {
1426 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
1427 }
1428
1429 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
1430 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
1431 const struct ufs_dev_quirk *fixups);
1432
1433 void ufshcd_hold(struct ufs_hba *hba);
1434 void ufshcd_release(struct ufs_hba *hba);
1435
1436 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value);
1437
1438 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg);
1439
1440 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
1441
1442 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
1443 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req,
1444 struct ufs_ehs *ehs_rsp, int sg_cnt,
1445 struct scatterlist *sg_list, enum dma_data_direction dir);
1446 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);
1447 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable);
1448 int ufshcd_wb_set_resize_en(struct ufs_hba *hba, enum wb_resize_en en_mode);
1449 int ufshcd_suspend_prepare(struct device *dev);
1450 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm);
1451 void ufshcd_resume_complete(struct device *dev);
1452 bool ufshcd_is_hba_active(struct ufs_hba *hba);
1453 void ufshcd_pm_qos_init(struct ufs_hba *hba);
1454 void ufshcd_pm_qos_exit(struct ufs_hba *hba);
1455 int ufshcd_dme_rmw(struct ufs_hba *hba, u32 mask, u32 val, u32 attr);
1456
1457 /* Wrapper functions for safely calling variant operations */
ufshcd_vops_init(struct ufs_hba * hba)1458 static inline int ufshcd_vops_init(struct ufs_hba *hba)
1459 {
1460 if (hba->vops && hba->vops->init)
1461 return hba->vops->init(hba);
1462
1463 return 0;
1464 }
1465
ufshcd_vops_phy_initialization(struct ufs_hba * hba)1466 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba)
1467 {
1468 if (hba->vops && hba->vops->phy_initialization)
1469 return hba->vops->phy_initialization(hba);
1470
1471 return 0;
1472 }
1473
1474 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1475
1476 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1477 const char *prefix);
1478
1479 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask);
1480 int ufshcd_write_ee_control(struct ufs_hba *hba);
1481 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
1482 const u16 *other_mask, u16 set, u16 clr);
1483 void ufshcd_force_error_recovery(struct ufs_hba *hba);
1484 void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on);
1485 u32 ufshcd_us_to_ahit(unsigned int timer);
1486
1487 #endif /* End of Header */
1488