1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 #include <linux/kvm_host.h> 18 19 #include <asm/cpufeature.h> 20 #include <asm/cpuid/api.h> 21 #include <asm/debugreg.h> 22 #include <asm/hardirq.h> 23 #include <asm/intel-family.h> 24 #include <asm/intel_pt.h> 25 #include <asm/apic.h> 26 #include <asm/cpu_device_id.h> 27 #include <asm/msr.h> 28 29 #include "../perf_event.h" 30 31 /* 32 * Intel PerfMon, used on Core and later. 33 */ 34 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 35 { 36 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 37 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 38 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 39 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 40 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 41 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 42 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 43 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 44 }; 45 46 static struct event_constraint intel_core_event_constraints[] __read_mostly = 47 { 48 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 49 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 50 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 51 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 52 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 53 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 54 EVENT_CONSTRAINT_END 55 }; 56 57 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 58 { 59 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 60 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 61 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 62 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 63 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 64 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 65 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 66 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 67 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 68 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 69 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 70 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 71 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 72 EVENT_CONSTRAINT_END 73 }; 74 75 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 76 { 77 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 78 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 79 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 80 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 81 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 82 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 83 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 84 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 85 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 86 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 87 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 88 EVENT_CONSTRAINT_END 89 }; 90 91 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 92 { 93 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 94 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 95 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 96 EVENT_EXTRA_END 97 }; 98 99 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 100 { 101 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 102 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 103 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 104 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 105 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 106 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 107 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 108 EVENT_CONSTRAINT_END 109 }; 110 111 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 112 { 113 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 114 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 115 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 117 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 118 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 119 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 120 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 121 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 122 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 123 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 124 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 125 126 /* 127 * When HT is off these events can only run on the bottom 4 counters 128 * When HT is on, they are impacted by the HT bug and require EXCL access 129 */ 130 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 131 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 132 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 133 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 134 135 EVENT_CONSTRAINT_END 136 }; 137 138 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 139 { 140 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 141 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 142 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 143 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 144 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 145 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 146 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 147 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 148 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 149 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 150 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 151 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 152 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 153 154 /* 155 * When HT is off these events can only run on the bottom 4 counters 156 * When HT is on, they are impacted by the HT bug and require EXCL access 157 */ 158 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 159 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 160 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 161 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 162 163 EVENT_CONSTRAINT_END 164 }; 165 166 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 167 { 168 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 169 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 170 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 171 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 172 EVENT_EXTRA_END 173 }; 174 175 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 176 { 177 EVENT_CONSTRAINT_END 178 }; 179 180 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 181 { 182 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 183 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 184 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 185 EVENT_CONSTRAINT_END 186 }; 187 188 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly = 189 { 190 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 191 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 192 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 193 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 194 FIXED_EVENT_CONSTRAINT(0x0500, 4), 195 FIXED_EVENT_CONSTRAINT(0x0600, 5), 196 FIXED_EVENT_CONSTRAINT(0x0700, 6), 197 FIXED_EVENT_CONSTRAINT(0x0800, 7), 198 FIXED_EVENT_CONSTRAINT(0x0900, 8), 199 FIXED_EVENT_CONSTRAINT(0x0a00, 9), 200 FIXED_EVENT_CONSTRAINT(0x0b00, 10), 201 FIXED_EVENT_CONSTRAINT(0x0c00, 11), 202 FIXED_EVENT_CONSTRAINT(0x0d00, 12), 203 FIXED_EVENT_CONSTRAINT(0x0e00, 13), 204 FIXED_EVENT_CONSTRAINT(0x0f00, 14), 205 FIXED_EVENT_CONSTRAINT(0x1000, 15), 206 EVENT_CONSTRAINT_END 207 }; 208 209 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 210 { 211 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 212 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 213 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 214 EVENT_CONSTRAINT_END 215 }; 216 217 static struct event_constraint intel_grt_event_constraints[] __read_mostly = { 218 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 219 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */ 220 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 221 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */ 222 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */ 223 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 224 EVENT_CONSTRAINT_END 225 }; 226 227 static struct event_constraint intel_skt_event_constraints[] __read_mostly = { 228 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 229 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */ 230 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 231 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */ 232 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */ 233 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 234 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */ 235 FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */ 236 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */ 237 FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */ 238 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */ 239 FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */ 240 EVENT_CONSTRAINT_END 241 }; 242 243 static struct event_constraint intel_arw_event_constraints[] __read_mostly = { 244 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 245 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */ 246 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 247 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */ 248 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */ 249 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 250 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */ 251 FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */ 252 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */ 253 FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */ 254 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */ 255 FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */ 256 INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1), 257 INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2), 258 INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4), 259 INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8), 260 INTEL_UEVENT_CONSTRAINT(0x0175, 0x1), 261 INTEL_UEVENT_CONSTRAINT(0x0275, 0x2), 262 INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1), 263 INTEL_UEVENT_CONSTRAINT(0x22d3, 0x1), 264 EVENT_CONSTRAINT_END 265 }; 266 267 static struct event_constraint intel_skl_event_constraints[] = { 268 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 269 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 270 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 271 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 272 273 /* 274 * when HT is off, these can only run on the bottom 4 counters 275 */ 276 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 277 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 278 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 279 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 280 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 281 282 EVENT_CONSTRAINT_END 283 }; 284 285 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 286 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 287 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 288 EVENT_EXTRA_END 289 }; 290 291 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 292 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 293 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 294 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 295 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 296 EVENT_EXTRA_END 297 }; 298 299 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 300 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 301 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 302 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 303 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 304 EVENT_EXTRA_END 305 }; 306 307 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 308 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 309 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 310 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 311 /* 312 * Note the low 8 bits eventsel code is not a continuous field, containing 313 * some #GPing bits. These are masked out. 314 */ 315 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 316 EVENT_EXTRA_END 317 }; 318 319 static struct event_constraint intel_icl_event_constraints[] = { 320 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 321 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 322 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */ 323 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 324 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */ 325 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */ 326 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */ 327 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 328 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 329 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 330 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 331 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 332 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 333 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 334 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf), 335 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 336 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 337 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 338 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 339 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 340 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 341 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 342 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 343 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 344 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 345 EVENT_CONSTRAINT_END 346 }; 347 348 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 349 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 350 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 351 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 352 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 353 EVENT_EXTRA_END 354 }; 355 356 static struct extra_reg intel_glc_extra_regs[] __read_mostly = { 357 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 358 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 359 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 360 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 361 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 362 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 363 EVENT_EXTRA_END 364 }; 365 366 static struct event_constraint intel_glc_event_constraints[] = { 367 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 368 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */ 369 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 370 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */ 371 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */ 372 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 373 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */ 374 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 375 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 376 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 377 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 378 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 379 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 380 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 381 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 382 383 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 384 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 385 /* 386 * Generally event codes < 0x90 are restricted to counters 0-3. 387 * The 0x2E and 0x3C are exception, which has no restriction. 388 */ 389 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 390 391 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 392 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 393 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), 394 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), 395 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 396 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0xf), 397 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 398 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 399 INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfe), 400 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 401 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 402 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 403 /* 404 * Generally event codes >= 0x90 are likely to have no restrictions. 405 * The exception are defined as above. 406 */ 407 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 408 409 EVENT_CONSTRAINT_END 410 }; 411 412 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = { 413 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 414 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 415 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 416 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 417 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 418 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 419 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 420 EVENT_EXTRA_END 421 }; 422 423 static struct event_constraint intel_lnc_event_constraints[] = { 424 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 425 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */ 426 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 427 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */ 428 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */ 429 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 430 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */ 431 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 432 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 433 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 434 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 435 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 436 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 437 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 438 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 439 440 INTEL_EVENT_CONSTRAINT(0x20, 0xf), 441 442 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), 443 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4), 444 445 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff), 446 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff), 447 448 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 449 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 450 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 451 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 452 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x8), 453 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8), 454 INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc), 455 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3), 456 457 INTEL_UEVENT_CONSTRAINT(0x87d0, 0x3ff), 458 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 459 460 EVENT_CONSTRAINT_END 461 }; 462 463 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = { 464 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0), 465 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1), 466 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 467 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 468 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 469 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE), 470 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 471 EVENT_EXTRA_END 472 }; 473 474 static struct event_constraint intel_pnc_event_constraints[] = { 475 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 476 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */ 477 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 478 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */ 479 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */ 480 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 481 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */ 482 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 483 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 484 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 485 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 486 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 487 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 488 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 489 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 490 491 INTEL_EVENT_CONSTRAINT(0x20, 0xf), 492 INTEL_EVENT_CONSTRAINT(0x79, 0xf), 493 494 INTEL_UEVENT_CONSTRAINT(0x0275, 0xf), 495 INTEL_UEVENT_CONSTRAINT(0x0176, 0xf), 496 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 497 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 498 INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfc), 499 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3), 500 501 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), 502 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), 503 INTEL_EVENT_CONSTRAINT(0xd4, 0xf), 504 INTEL_EVENT_CONSTRAINT(0xd6, 0xf), 505 INTEL_EVENT_CONSTRAINT(0xdf, 0xf), 506 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 507 508 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8), 509 INTEL_UEVENT_CONSTRAINT(0x01b2, 0xf), 510 INTEL_UEVENT_CONSTRAINT(0x02b2, 0xf), 511 INTEL_UEVENT_CONSTRAINT(0x0847, 0xf), 512 INTEL_UEVENT_CONSTRAINT(0x0446, 0xf), 513 INTEL_UEVENT_CONSTRAINT(0x0846, 0xf), 514 INTEL_UEVENT_CONSTRAINT(0x0148, 0xf), 515 516 EVENT_CONSTRAINT_END 517 }; 518 519 static struct extra_reg intel_pnc_extra_regs[] __read_mostly = { 520 /* must define OMR_X first, see intel_alt_er() */ 521 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0), 522 INTEL_UEVENT_EXTRA_REG(0x022a, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1), 523 INTEL_UEVENT_EXTRA_REG(0x042a, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2), 524 INTEL_UEVENT_EXTRA_REG(0x082a, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3), 525 INTEL_UEVENT_EXTRA_REG(0x014f, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0), 526 INTEL_UEVENT_EXTRA_REG(0x024f, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1), 527 INTEL_UEVENT_EXTRA_REG(0x044f, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2), 528 INTEL_UEVENT_EXTRA_REG(0x084f, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3), 529 INTEL_UEVENT_EXTRA_REG(0x01d6, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0), 530 INTEL_UEVENT_EXTRA_REG(0x02d6, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1), 531 INTEL_UEVENT_EXTRA_REG(0x04d6, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2), 532 INTEL_UEVENT_EXTRA_REG(0x08d6, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3), 533 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 534 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 535 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 536 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE), 537 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 538 EVENT_EXTRA_END 539 }; 540 541 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 542 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 543 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 544 545 static struct attribute *nhm_mem_events_attrs[] = { 546 EVENT_PTR(mem_ld_nhm), 547 NULL, 548 }; 549 550 /* 551 * topdown events for Intel Core CPUs. 552 * 553 * The events are all in slots, which is a free slot in a 4 wide 554 * pipeline. Some events are already reported in slots, for cycle 555 * events we multiply by the pipeline width (4). 556 * 557 * With Hyper Threading on, topdown metrics are either summed or averaged 558 * between the threads of a core: (count_t0 + count_t1). 559 * 560 * For the average case the metric is always scaled to pipeline width, 561 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 562 */ 563 564 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 565 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 566 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 567 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 568 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 569 "event=0xe,umask=0x1"); /* uops_issued.any */ 570 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 571 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 572 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 573 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 574 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 575 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 576 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 577 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 578 "4", "2"); 579 580 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 581 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 582 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 583 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 584 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 585 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 586 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 587 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 588 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 589 590 static struct attribute *snb_events_attrs[] = { 591 EVENT_PTR(td_slots_issued), 592 EVENT_PTR(td_slots_retired), 593 EVENT_PTR(td_fetch_bubbles), 594 EVENT_PTR(td_total_slots), 595 EVENT_PTR(td_total_slots_scale), 596 EVENT_PTR(td_recovery_bubbles), 597 EVENT_PTR(td_recovery_bubbles_scale), 598 NULL, 599 }; 600 601 static struct attribute *snb_mem_events_attrs[] = { 602 EVENT_PTR(mem_ld_snb), 603 EVENT_PTR(mem_st_snb), 604 NULL, 605 }; 606 607 static struct event_constraint intel_hsw_event_constraints[] = { 608 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 609 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 610 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 611 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 612 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 613 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 614 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 615 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 616 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 617 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 618 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 619 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 620 621 /* 622 * When HT is off these events can only run on the bottom 4 counters 623 * When HT is on, they are impacted by the HT bug and require EXCL access 624 */ 625 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 626 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 627 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 628 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 629 630 EVENT_CONSTRAINT_END 631 }; 632 633 static struct event_constraint intel_bdw_event_constraints[] = { 634 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 635 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 636 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 637 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 638 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 639 /* 640 * when HT is off, these can only run on the bottom 4 counters 641 */ 642 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 643 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 644 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 645 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 646 EVENT_CONSTRAINT_END 647 }; 648 649 static u64 intel_pmu_event_map(int hw_event) 650 { 651 return intel_perfmon_event_map[hw_event]; 652 } 653 654 static __initconst const u64 glc_hw_cache_event_ids 655 [PERF_COUNT_HW_CACHE_MAX] 656 [PERF_COUNT_HW_CACHE_OP_MAX] 657 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 658 { 659 [ C(L1D ) ] = { 660 [ C(OP_READ) ] = { 661 [ C(RESULT_ACCESS) ] = 0x81d0, 662 [ C(RESULT_MISS) ] = 0xe124, 663 }, 664 [ C(OP_WRITE) ] = { 665 [ C(RESULT_ACCESS) ] = 0x82d0, 666 }, 667 }, 668 [ C(L1I ) ] = { 669 [ C(OP_READ) ] = { 670 [ C(RESULT_MISS) ] = 0xe424, 671 }, 672 [ C(OP_WRITE) ] = { 673 [ C(RESULT_ACCESS) ] = -1, 674 [ C(RESULT_MISS) ] = -1, 675 }, 676 }, 677 [ C(LL ) ] = { 678 [ C(OP_READ) ] = { 679 [ C(RESULT_ACCESS) ] = 0x12a, 680 [ C(RESULT_MISS) ] = 0x12a, 681 }, 682 [ C(OP_WRITE) ] = { 683 [ C(RESULT_ACCESS) ] = 0x12a, 684 [ C(RESULT_MISS) ] = 0x12a, 685 }, 686 }, 687 [ C(DTLB) ] = { 688 [ C(OP_READ) ] = { 689 [ C(RESULT_ACCESS) ] = 0x81d0, 690 [ C(RESULT_MISS) ] = 0xe12, 691 }, 692 [ C(OP_WRITE) ] = { 693 [ C(RESULT_ACCESS) ] = 0x82d0, 694 [ C(RESULT_MISS) ] = 0xe13, 695 }, 696 }, 697 [ C(ITLB) ] = { 698 [ C(OP_READ) ] = { 699 [ C(RESULT_ACCESS) ] = -1, 700 [ C(RESULT_MISS) ] = 0xe11, 701 }, 702 [ C(OP_WRITE) ] = { 703 [ C(RESULT_ACCESS) ] = -1, 704 [ C(RESULT_MISS) ] = -1, 705 }, 706 [ C(OP_PREFETCH) ] = { 707 [ C(RESULT_ACCESS) ] = -1, 708 [ C(RESULT_MISS) ] = -1, 709 }, 710 }, 711 [ C(BPU ) ] = { 712 [ C(OP_READ) ] = { 713 [ C(RESULT_ACCESS) ] = 0x4c4, 714 [ C(RESULT_MISS) ] = 0x4c5, 715 }, 716 [ C(OP_WRITE) ] = { 717 [ C(RESULT_ACCESS) ] = -1, 718 [ C(RESULT_MISS) ] = -1, 719 }, 720 [ C(OP_PREFETCH) ] = { 721 [ C(RESULT_ACCESS) ] = -1, 722 [ C(RESULT_MISS) ] = -1, 723 }, 724 }, 725 [ C(NODE) ] = { 726 [ C(OP_READ) ] = { 727 [ C(RESULT_ACCESS) ] = 0x12a, 728 [ C(RESULT_MISS) ] = 0x12a, 729 }, 730 }, 731 }; 732 733 /* ADL P-core (Golden cove) specific event code. */ 734 static __initconst const u64 adl_glc_hw_cache_event_ids 735 [PERF_COUNT_HW_CACHE_MAX] 736 [PERF_COUNT_HW_CACHE_OP_MAX] 737 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 738 { 739 [ C(L1D ) ] = { 740 [ C(OP_READ) ] = { 741 [ C(RESULT_ACCESS) ] = 0x81d0, 742 [ C(RESULT_MISS) ] = 0xe124, 743 }, 744 [ C(OP_WRITE) ] = { 745 [ C(RESULT_ACCESS) ] = 0x82d0, 746 }, 747 }, 748 [ C(L1I ) ] = { 749 [ C(OP_READ) ] = { 750 [ C(RESULT_MISS) ] = 0xe424, 751 }, 752 [ C(OP_WRITE) ] = { 753 [ C(RESULT_ACCESS) ] = -1, 754 [ C(RESULT_MISS) ] = -1, 755 }, 756 }, 757 [ C(LL ) ] = { 758 [ C(OP_READ) ] = { 759 [ C(RESULT_ACCESS) ] = 0x12a, 760 [ C(RESULT_MISS) ] = 0x12a, 761 }, 762 [ C(OP_WRITE) ] = { 763 [ C(RESULT_ACCESS) ] = 0x12a, 764 [ C(RESULT_MISS) ] = 0x12a, 765 }, 766 }, 767 [ C(DTLB) ] = { 768 [ C(OP_READ) ] = { 769 [ C(RESULT_ACCESS) ] = 0x81d0, 770 [ C(RESULT_MISS) ] = 0xe12, 771 }, 772 [ C(OP_WRITE) ] = { 773 [ C(RESULT_ACCESS) ] = 0x82d0, 774 [ C(RESULT_MISS) ] = 0xe13, 775 }, 776 }, 777 [ C(ITLB) ] = { 778 [ C(OP_READ) ] = { 779 [ C(RESULT_ACCESS) ] = -1, 780 [ C(RESULT_MISS) ] = 0xe11, 781 }, 782 [ C(OP_WRITE) ] = { 783 [ C(RESULT_ACCESS) ] = -1, 784 [ C(RESULT_MISS) ] = -1, 785 }, 786 [ C(OP_PREFETCH) ] = { 787 [ C(RESULT_ACCESS) ] = -1, 788 [ C(RESULT_MISS) ] = -1, 789 }, 790 }, 791 [ C(BPU ) ] = { 792 [ C(OP_READ) ] = { 793 [ C(RESULT_ACCESS) ] = 0x4c4, 794 [ C(RESULT_MISS) ] = 0x4c5, 795 }, 796 [ C(OP_WRITE) ] = { 797 [ C(RESULT_ACCESS) ] = -1, 798 [ C(RESULT_MISS) ] = -1, 799 }, 800 [ C(OP_PREFETCH) ] = { 801 [ C(RESULT_ACCESS) ] = -1, 802 [ C(RESULT_MISS) ] = -1, 803 }, 804 }, 805 }; 806 807 static __initconst const u64 glc_hw_cache_extra_regs 808 [PERF_COUNT_HW_CACHE_MAX] 809 [PERF_COUNT_HW_CACHE_OP_MAX] 810 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 811 { 812 [ C(LL ) ] = { 813 [ C(OP_READ) ] = { 814 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ 815 [ C(RESULT_MISS) ] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */ 816 }, 817 [ C(OP_WRITE) ] = { 818 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ 819 [ C(RESULT_MISS) ] = 0x3f3fc00002, /* OCR.DEMAND_RFO.L3_MISS */ 820 }, 821 }, 822 [ C(NODE) ] = { 823 [ C(OP_READ) ] = { 824 [ C(RESULT_ACCESS) ] = 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */ 825 [ C(RESULT_MISS) ] = 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */ 826 }, 827 }, 828 }; 829 830 /* ADL P-core (Golden cove) specific extra regs value. */ 831 static __initconst const u64 adl_glc_hw_cache_extra_regs 832 [PERF_COUNT_HW_CACHE_MAX] 833 [PERF_COUNT_HW_CACHE_OP_MAX] 834 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 835 { 836 [ C(LL ) ] = { 837 [ C(OP_READ) ] = { 838 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ 839 [ C(RESULT_MISS) ] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */ 840 }, 841 [ C(OP_WRITE) ] = { 842 [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ 843 [ C(RESULT_MISS) ] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */ 844 }, 845 }, 846 }; 847 848 static __initconst const u64 lnc_hw_cache_extra_regs 849 [PERF_COUNT_HW_CACHE_MAX] 850 [PERF_COUNT_HW_CACHE_OP_MAX] 851 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 852 { 853 [ C(LL ) ] = { 854 [ C(OP_READ) ] = { 855 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ 856 [ C(RESULT_MISS) ] = 0x9E7FA000001, /* OCR.DEMAND_DATA_RD.L3_MISS */ 857 }, 858 [ C(OP_WRITE) ] = { 859 [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ 860 [ C(RESULT_MISS) ] = 0x9E7FA000002, /* OCR.DEMAND_RFO.L3_MISS */ 861 }, 862 }, 863 }; 864 865 /* ARL specific lioncove hw_cache_extra_regs[] variant. */ 866 static __initconst const u64 arl_lnc_hw_cache_extra_regs 867 [PERF_COUNT_HW_CACHE_MAX] 868 [PERF_COUNT_HW_CACHE_OP_MAX] 869 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 870 { 871 [ C(LL ) ] = { 872 [ C(OP_READ) ] = { 873 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ 874 [ C(RESULT_MISS) ] = 0xFE7F8000001, /* OCR.DEMAND_DATA_RD.L3_MISS */ 875 }, 876 [ C(OP_WRITE) ] = { 877 [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ 878 [ C(RESULT_MISS) ] = 0xFE7F8000002, /* OCR.DEMAND_RFO.L3_MISS */ 879 }, 880 }, 881 }; 882 883 static __initconst const u64 pnc_hw_cache_event_ids 884 [PERF_COUNT_HW_CACHE_MAX] 885 [PERF_COUNT_HW_CACHE_OP_MAX] 886 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 887 { 888 [ C(L1D ) ] = { 889 [ C(OP_READ) ] = { 890 [ C(RESULT_ACCESS) ] = 0x81d0, 891 [ C(RESULT_MISS) ] = 0xe124, 892 }, 893 [ C(OP_WRITE) ] = { 894 [ C(RESULT_ACCESS) ] = 0x82d0, 895 }, 896 }, 897 [ C(L1I ) ] = { 898 [ C(OP_READ) ] = { 899 [ C(RESULT_MISS) ] = 0xe424, 900 }, 901 [ C(OP_WRITE) ] = { 902 [ C(RESULT_ACCESS) ] = -1, 903 [ C(RESULT_MISS) ] = -1, 904 }, 905 }, 906 [ C(LL ) ] = { 907 [ C(OP_READ) ] = { 908 [ C(RESULT_ACCESS) ] = 0x12a, 909 [ C(RESULT_MISS) ] = 0x12a, 910 }, 911 [ C(OP_WRITE) ] = { 912 [ C(RESULT_ACCESS) ] = 0x12a, 913 [ C(RESULT_MISS) ] = 0x12a, 914 }, 915 }, 916 [ C(DTLB) ] = { 917 [ C(OP_READ) ] = { 918 [ C(RESULT_ACCESS) ] = 0x81d0, 919 [ C(RESULT_MISS) ] = 0xe12, 920 }, 921 [ C(OP_WRITE) ] = { 922 [ C(RESULT_ACCESS) ] = 0x82d0, 923 [ C(RESULT_MISS) ] = 0xe13, 924 }, 925 }, 926 [ C(ITLB) ] = { 927 [ C(OP_READ) ] = { 928 [ C(RESULT_ACCESS) ] = -1, 929 [ C(RESULT_MISS) ] = 0xe11, 930 }, 931 [ C(OP_WRITE) ] = { 932 [ C(RESULT_ACCESS) ] = -1, 933 [ C(RESULT_MISS) ] = -1, 934 }, 935 [ C(OP_PREFETCH) ] = { 936 [ C(RESULT_ACCESS) ] = -1, 937 [ C(RESULT_MISS) ] = -1, 938 }, 939 }, 940 [ C(BPU ) ] = { 941 [ C(OP_READ) ] = { 942 [ C(RESULT_ACCESS) ] = 0x4c4, 943 [ C(RESULT_MISS) ] = 0x4c5, 944 }, 945 [ C(OP_WRITE) ] = { 946 [ C(RESULT_ACCESS) ] = -1, 947 [ C(RESULT_MISS) ] = -1, 948 }, 949 [ C(OP_PREFETCH) ] = { 950 [ C(RESULT_ACCESS) ] = -1, 951 [ C(RESULT_MISS) ] = -1, 952 }, 953 }, 954 [ C(NODE) ] = { 955 [ C(OP_READ) ] = { 956 [ C(RESULT_ACCESS) ] = -1, 957 [ C(RESULT_MISS) ] = -1, 958 }, 959 }, 960 }; 961 962 static __initconst const u64 pnc_hw_cache_extra_regs 963 [PERF_COUNT_HW_CACHE_MAX] 964 [PERF_COUNT_HW_CACHE_OP_MAX] 965 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 966 { 967 [ C(LL ) ] = { 968 [ C(OP_READ) ] = { 969 [ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */ 970 [ C(RESULT_MISS) ] = 0xFFFFF000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */ 971 }, 972 [ C(OP_WRITE) ] = { 973 [ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */ 974 [ C(RESULT_MISS) ] = 0xFFFFF000000002, /* OMR.DEMAND_RFO.L3_MISS */ 975 }, 976 }, 977 }; 978 979 static __initconst const u64 cyc_hw_cache_extra_regs 980 [PERF_COUNT_HW_CACHE_MAX] 981 [PERF_COUNT_HW_CACHE_OP_MAX] 982 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 983 { 984 [ C(LL ) ] = { 985 [ C(OP_READ) ] = { 986 [ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */ 987 [ C(RESULT_MISS) ] = 0xFF03F000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */ 988 }, 989 [ C(OP_WRITE) ] = { 990 [ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */ 991 [ C(RESULT_MISS) ] = 0xFF03F000000002, /* OMR.DEMAND_RFO.L3_MISS */ 992 }, 993 }, 994 }; 995 996 /* 997 * Notes on the events: 998 * - data reads do not include code reads (comparable to earlier tables) 999 * - data counts include speculative execution (except L1 write, dtlb, bpu) 1000 * - remote node access includes remote memory, remote cache, remote mmio. 1001 * - prefetches are not included in the counts. 1002 * - icache miss does not include decoded icache 1003 */ 1004 1005 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 1006 #define SKL_DEMAND_RFO BIT_ULL(1) 1007 #define SKL_ANY_RESPONSE BIT_ULL(16) 1008 #define SKL_SUPPLIER_NONE BIT_ULL(17) 1009 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 1010 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 1011 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 1012 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 1013 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 1014 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 1015 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 1016 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 1017 #define SKL_SPL_HIT BIT_ULL(30) 1018 #define SKL_SNOOP_NONE BIT_ULL(31) 1019 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 1020 #define SKL_SNOOP_MISS BIT_ULL(33) 1021 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 1022 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 1023 #define SKL_SNOOP_HITM BIT_ULL(36) 1024 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 1025 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 1026 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 1027 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 1028 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 1029 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 1030 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 1031 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 1032 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 1033 SKL_SNOOP_HITM|SKL_SPL_HIT) 1034 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 1035 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 1036 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 1037 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 1038 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 1039 1040 static __initconst const u64 skl_hw_cache_event_ids 1041 [PERF_COUNT_HW_CACHE_MAX] 1042 [PERF_COUNT_HW_CACHE_OP_MAX] 1043 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1044 { 1045 [ C(L1D ) ] = { 1046 [ C(OP_READ) ] = { 1047 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 1048 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 1049 }, 1050 [ C(OP_WRITE) ] = { 1051 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 1052 [ C(RESULT_MISS) ] = 0x0, 1053 }, 1054 [ C(OP_PREFETCH) ] = { 1055 [ C(RESULT_ACCESS) ] = 0x0, 1056 [ C(RESULT_MISS) ] = 0x0, 1057 }, 1058 }, 1059 [ C(L1I ) ] = { 1060 [ C(OP_READ) ] = { 1061 [ C(RESULT_ACCESS) ] = 0x0, 1062 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 1063 }, 1064 [ C(OP_WRITE) ] = { 1065 [ C(RESULT_ACCESS) ] = -1, 1066 [ C(RESULT_MISS) ] = -1, 1067 }, 1068 [ C(OP_PREFETCH) ] = { 1069 [ C(RESULT_ACCESS) ] = 0x0, 1070 [ C(RESULT_MISS) ] = 0x0, 1071 }, 1072 }, 1073 [ C(LL ) ] = { 1074 [ C(OP_READ) ] = { 1075 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1076 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1077 }, 1078 [ C(OP_WRITE) ] = { 1079 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1080 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1081 }, 1082 [ C(OP_PREFETCH) ] = { 1083 [ C(RESULT_ACCESS) ] = 0x0, 1084 [ C(RESULT_MISS) ] = 0x0, 1085 }, 1086 }, 1087 [ C(DTLB) ] = { 1088 [ C(OP_READ) ] = { 1089 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 1090 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1091 }, 1092 [ C(OP_WRITE) ] = { 1093 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 1094 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1095 }, 1096 [ C(OP_PREFETCH) ] = { 1097 [ C(RESULT_ACCESS) ] = 0x0, 1098 [ C(RESULT_MISS) ] = 0x0, 1099 }, 1100 }, 1101 [ C(ITLB) ] = { 1102 [ C(OP_READ) ] = { 1103 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 1104 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 1105 }, 1106 [ C(OP_WRITE) ] = { 1107 [ C(RESULT_ACCESS) ] = -1, 1108 [ C(RESULT_MISS) ] = -1, 1109 }, 1110 [ C(OP_PREFETCH) ] = { 1111 [ C(RESULT_ACCESS) ] = -1, 1112 [ C(RESULT_MISS) ] = -1, 1113 }, 1114 }, 1115 [ C(BPU ) ] = { 1116 [ C(OP_READ) ] = { 1117 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1118 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1119 }, 1120 [ C(OP_WRITE) ] = { 1121 [ C(RESULT_ACCESS) ] = -1, 1122 [ C(RESULT_MISS) ] = -1, 1123 }, 1124 [ C(OP_PREFETCH) ] = { 1125 [ C(RESULT_ACCESS) ] = -1, 1126 [ C(RESULT_MISS) ] = -1, 1127 }, 1128 }, 1129 [ C(NODE) ] = { 1130 [ C(OP_READ) ] = { 1131 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1132 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1133 }, 1134 [ C(OP_WRITE) ] = { 1135 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1136 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1137 }, 1138 [ C(OP_PREFETCH) ] = { 1139 [ C(RESULT_ACCESS) ] = 0x0, 1140 [ C(RESULT_MISS) ] = 0x0, 1141 }, 1142 }, 1143 }; 1144 1145 static __initconst const u64 skl_hw_cache_extra_regs 1146 [PERF_COUNT_HW_CACHE_MAX] 1147 [PERF_COUNT_HW_CACHE_OP_MAX] 1148 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1149 { 1150 [ C(LL ) ] = { 1151 [ C(OP_READ) ] = { 1152 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 1153 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 1154 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 1155 SKL_L3_MISS|SKL_ANY_SNOOP| 1156 SKL_SUPPLIER_NONE, 1157 }, 1158 [ C(OP_WRITE) ] = { 1159 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 1160 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 1161 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 1162 SKL_L3_MISS|SKL_ANY_SNOOP| 1163 SKL_SUPPLIER_NONE, 1164 }, 1165 [ C(OP_PREFETCH) ] = { 1166 [ C(RESULT_ACCESS) ] = 0x0, 1167 [ C(RESULT_MISS) ] = 0x0, 1168 }, 1169 }, 1170 [ C(NODE) ] = { 1171 [ C(OP_READ) ] = { 1172 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 1173 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 1174 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 1175 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 1176 }, 1177 [ C(OP_WRITE) ] = { 1178 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 1179 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 1180 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 1181 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 1182 }, 1183 [ C(OP_PREFETCH) ] = { 1184 [ C(RESULT_ACCESS) ] = 0x0, 1185 [ C(RESULT_MISS) ] = 0x0, 1186 }, 1187 }, 1188 }; 1189 1190 static __initconst const u64 snc_hw_cache_extra_regs 1191 [PERF_COUNT_HW_CACHE_MAX] 1192 [PERF_COUNT_HW_CACHE_OP_MAX] 1193 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1194 { 1195 [ C(LL ) ] = { 1196 [ C(OP_READ) ] = { 1197 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ 1198 [ C(RESULT_MISS) ] = 0x3FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */ 1199 }, 1200 [ C(OP_WRITE) ] = { 1201 [ C(RESULT_ACCESS) ] = 0x3F3FFC0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ 1202 [ C(RESULT_MISS) ] = 0x3F3FC00002, /* OCR.DEMAND_RFO.L3_MISS */ 1203 }, 1204 [ C(OP_PREFETCH) ] = { 1205 [ C(RESULT_ACCESS) ] = 0x0, 1206 [ C(RESULT_MISS) ] = 0x0, 1207 }, 1208 }, 1209 [ C(NODE) ] = { 1210 [ C(OP_READ) ] = { 1211 [ C(RESULT_ACCESS) ] = 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */ 1212 [ C(RESULT_MISS) ] = 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */ 1213 }, 1214 [ C(OP_WRITE) ] = { 1215 [ C(RESULT_ACCESS) ] = 0x104000002, /* OCR.DEMAND_RFO.LOCAL_DRAM */ 1216 [ C(RESULT_MISS) ] = 0x730000002, /* OCR.DEMAND_RFO.REMOTE_DRAM */ 1217 }, 1218 [ C(OP_PREFETCH) ] = { 1219 [ C(RESULT_ACCESS) ] = 0x0, 1220 [ C(RESULT_MISS) ] = 0x0, 1221 }, 1222 }, 1223 }; 1224 1225 #define SNB_DMND_DATA_RD (1ULL << 0) 1226 #define SNB_DMND_RFO (1ULL << 1) 1227 #define SNB_DMND_IFETCH (1ULL << 2) 1228 #define SNB_DMND_WB (1ULL << 3) 1229 #define SNB_PF_DATA_RD (1ULL << 4) 1230 #define SNB_PF_RFO (1ULL << 5) 1231 #define SNB_PF_IFETCH (1ULL << 6) 1232 #define SNB_LLC_DATA_RD (1ULL << 7) 1233 #define SNB_LLC_RFO (1ULL << 8) 1234 #define SNB_LLC_IFETCH (1ULL << 9) 1235 #define SNB_BUS_LOCKS (1ULL << 10) 1236 #define SNB_STRM_ST (1ULL << 11) 1237 #define SNB_OTHER (1ULL << 15) 1238 #define SNB_RESP_ANY (1ULL << 16) 1239 #define SNB_NO_SUPP (1ULL << 17) 1240 #define SNB_LLC_HITM (1ULL << 18) 1241 #define SNB_LLC_HITE (1ULL << 19) 1242 #define SNB_LLC_HITS (1ULL << 20) 1243 #define SNB_LLC_HITF (1ULL << 21) 1244 #define SNB_LOCAL (1ULL << 22) 1245 #define SNB_REMOTE (0xffULL << 23) 1246 #define SNB_SNP_NONE (1ULL << 31) 1247 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 1248 #define SNB_SNP_MISS (1ULL << 33) 1249 #define SNB_NO_FWD (1ULL << 34) 1250 #define SNB_SNP_FWD (1ULL << 35) 1251 #define SNB_HITM (1ULL << 36) 1252 #define SNB_NON_DRAM (1ULL << 37) 1253 1254 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 1255 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 1256 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1257 1258 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 1259 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 1260 SNB_HITM) 1261 1262 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 1263 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 1264 1265 #define SNB_L3_ACCESS SNB_RESP_ANY 1266 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 1267 1268 static __initconst const u64 snb_hw_cache_extra_regs 1269 [PERF_COUNT_HW_CACHE_MAX] 1270 [PERF_COUNT_HW_CACHE_OP_MAX] 1271 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1272 { 1273 [ C(LL ) ] = { 1274 [ C(OP_READ) ] = { 1275 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 1276 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 1277 }, 1278 [ C(OP_WRITE) ] = { 1279 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 1280 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 1281 }, 1282 [ C(OP_PREFETCH) ] = { 1283 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 1284 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 1285 }, 1286 }, 1287 [ C(NODE) ] = { 1288 [ C(OP_READ) ] = { 1289 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 1290 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 1291 }, 1292 [ C(OP_WRITE) ] = { 1293 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 1294 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 1295 }, 1296 [ C(OP_PREFETCH) ] = { 1297 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 1298 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 1299 }, 1300 }, 1301 }; 1302 1303 static __initconst const u64 snb_hw_cache_event_ids 1304 [PERF_COUNT_HW_CACHE_MAX] 1305 [PERF_COUNT_HW_CACHE_OP_MAX] 1306 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1307 { 1308 [ C(L1D) ] = { 1309 [ C(OP_READ) ] = { 1310 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 1311 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 1312 }, 1313 [ C(OP_WRITE) ] = { 1314 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 1315 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 1316 }, 1317 [ C(OP_PREFETCH) ] = { 1318 [ C(RESULT_ACCESS) ] = 0x0, 1319 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 1320 }, 1321 }, 1322 [ C(L1I ) ] = { 1323 [ C(OP_READ) ] = { 1324 [ C(RESULT_ACCESS) ] = 0x0, 1325 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 1326 }, 1327 [ C(OP_WRITE) ] = { 1328 [ C(RESULT_ACCESS) ] = -1, 1329 [ C(RESULT_MISS) ] = -1, 1330 }, 1331 [ C(OP_PREFETCH) ] = { 1332 [ C(RESULT_ACCESS) ] = 0x0, 1333 [ C(RESULT_MISS) ] = 0x0, 1334 }, 1335 }, 1336 [ C(LL ) ] = { 1337 [ C(OP_READ) ] = { 1338 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1339 [ C(RESULT_ACCESS) ] = 0x01b7, 1340 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1341 [ C(RESULT_MISS) ] = 0x01b7, 1342 }, 1343 [ C(OP_WRITE) ] = { 1344 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1345 [ C(RESULT_ACCESS) ] = 0x01b7, 1346 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1347 [ C(RESULT_MISS) ] = 0x01b7, 1348 }, 1349 [ C(OP_PREFETCH) ] = { 1350 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1351 [ C(RESULT_ACCESS) ] = 0x01b7, 1352 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1353 [ C(RESULT_MISS) ] = 0x01b7, 1354 }, 1355 }, 1356 [ C(DTLB) ] = { 1357 [ C(OP_READ) ] = { 1358 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 1359 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 1360 }, 1361 [ C(OP_WRITE) ] = { 1362 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 1363 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1364 }, 1365 [ C(OP_PREFETCH) ] = { 1366 [ C(RESULT_ACCESS) ] = 0x0, 1367 [ C(RESULT_MISS) ] = 0x0, 1368 }, 1369 }, 1370 [ C(ITLB) ] = { 1371 [ C(OP_READ) ] = { 1372 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 1373 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 1374 }, 1375 [ C(OP_WRITE) ] = { 1376 [ C(RESULT_ACCESS) ] = -1, 1377 [ C(RESULT_MISS) ] = -1, 1378 }, 1379 [ C(OP_PREFETCH) ] = { 1380 [ C(RESULT_ACCESS) ] = -1, 1381 [ C(RESULT_MISS) ] = -1, 1382 }, 1383 }, 1384 [ C(BPU ) ] = { 1385 [ C(OP_READ) ] = { 1386 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1387 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1388 }, 1389 [ C(OP_WRITE) ] = { 1390 [ C(RESULT_ACCESS) ] = -1, 1391 [ C(RESULT_MISS) ] = -1, 1392 }, 1393 [ C(OP_PREFETCH) ] = { 1394 [ C(RESULT_ACCESS) ] = -1, 1395 [ C(RESULT_MISS) ] = -1, 1396 }, 1397 }, 1398 [ C(NODE) ] = { 1399 [ C(OP_READ) ] = { 1400 [ C(RESULT_ACCESS) ] = 0x01b7, 1401 [ C(RESULT_MISS) ] = 0x01b7, 1402 }, 1403 [ C(OP_WRITE) ] = { 1404 [ C(RESULT_ACCESS) ] = 0x01b7, 1405 [ C(RESULT_MISS) ] = 0x01b7, 1406 }, 1407 [ C(OP_PREFETCH) ] = { 1408 [ C(RESULT_ACCESS) ] = 0x01b7, 1409 [ C(RESULT_MISS) ] = 0x01b7, 1410 }, 1411 }, 1412 1413 }; 1414 1415 /* 1416 * Notes on the events: 1417 * - data reads do not include code reads (comparable to earlier tables) 1418 * - data counts include speculative execution (except L1 write, dtlb, bpu) 1419 * - remote node access includes remote memory, remote cache, remote mmio. 1420 * - prefetches are not included in the counts because they are not 1421 * reliably counted. 1422 */ 1423 1424 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 1425 #define HSW_DEMAND_RFO BIT_ULL(1) 1426 #define HSW_ANY_RESPONSE BIT_ULL(16) 1427 #define HSW_SUPPLIER_NONE BIT_ULL(17) 1428 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 1429 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 1430 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 1431 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 1432 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 1433 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1434 HSW_L3_MISS_REMOTE_HOP2P) 1435 #define HSW_SNOOP_NONE BIT_ULL(31) 1436 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 1437 #define HSW_SNOOP_MISS BIT_ULL(33) 1438 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 1439 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 1440 #define HSW_SNOOP_HITM BIT_ULL(36) 1441 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 1442 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 1443 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 1444 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 1445 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 1446 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 1447 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 1448 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 1449 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 1450 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 1451 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 1452 1453 #define BDW_L3_MISS_LOCAL BIT(26) 1454 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 1455 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1456 HSW_L3_MISS_REMOTE_HOP2P) 1457 1458 1459 static __initconst const u64 hsw_hw_cache_event_ids 1460 [PERF_COUNT_HW_CACHE_MAX] 1461 [PERF_COUNT_HW_CACHE_OP_MAX] 1462 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1463 { 1464 [ C(L1D ) ] = { 1465 [ C(OP_READ) ] = { 1466 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1467 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 1468 }, 1469 [ C(OP_WRITE) ] = { 1470 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1471 [ C(RESULT_MISS) ] = 0x0, 1472 }, 1473 [ C(OP_PREFETCH) ] = { 1474 [ C(RESULT_ACCESS) ] = 0x0, 1475 [ C(RESULT_MISS) ] = 0x0, 1476 }, 1477 }, 1478 [ C(L1I ) ] = { 1479 [ C(OP_READ) ] = { 1480 [ C(RESULT_ACCESS) ] = 0x0, 1481 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 1482 }, 1483 [ C(OP_WRITE) ] = { 1484 [ C(RESULT_ACCESS) ] = -1, 1485 [ C(RESULT_MISS) ] = -1, 1486 }, 1487 [ C(OP_PREFETCH) ] = { 1488 [ C(RESULT_ACCESS) ] = 0x0, 1489 [ C(RESULT_MISS) ] = 0x0, 1490 }, 1491 }, 1492 [ C(LL ) ] = { 1493 [ C(OP_READ) ] = { 1494 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1495 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1496 }, 1497 [ C(OP_WRITE) ] = { 1498 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1499 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1500 }, 1501 [ C(OP_PREFETCH) ] = { 1502 [ C(RESULT_ACCESS) ] = 0x0, 1503 [ C(RESULT_MISS) ] = 0x0, 1504 }, 1505 }, 1506 [ C(DTLB) ] = { 1507 [ C(OP_READ) ] = { 1508 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1509 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1510 }, 1511 [ C(OP_WRITE) ] = { 1512 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1513 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1514 }, 1515 [ C(OP_PREFETCH) ] = { 1516 [ C(RESULT_ACCESS) ] = 0x0, 1517 [ C(RESULT_MISS) ] = 0x0, 1518 }, 1519 }, 1520 [ C(ITLB) ] = { 1521 [ C(OP_READ) ] = { 1522 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1523 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1524 }, 1525 [ C(OP_WRITE) ] = { 1526 [ C(RESULT_ACCESS) ] = -1, 1527 [ C(RESULT_MISS) ] = -1, 1528 }, 1529 [ C(OP_PREFETCH) ] = { 1530 [ C(RESULT_ACCESS) ] = -1, 1531 [ C(RESULT_MISS) ] = -1, 1532 }, 1533 }, 1534 [ C(BPU ) ] = { 1535 [ C(OP_READ) ] = { 1536 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1537 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1538 }, 1539 [ C(OP_WRITE) ] = { 1540 [ C(RESULT_ACCESS) ] = -1, 1541 [ C(RESULT_MISS) ] = -1, 1542 }, 1543 [ C(OP_PREFETCH) ] = { 1544 [ C(RESULT_ACCESS) ] = -1, 1545 [ C(RESULT_MISS) ] = -1, 1546 }, 1547 }, 1548 [ C(NODE) ] = { 1549 [ C(OP_READ) ] = { 1550 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1551 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1552 }, 1553 [ C(OP_WRITE) ] = { 1554 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1555 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1556 }, 1557 [ C(OP_PREFETCH) ] = { 1558 [ C(RESULT_ACCESS) ] = 0x0, 1559 [ C(RESULT_MISS) ] = 0x0, 1560 }, 1561 }, 1562 }; 1563 1564 static __initconst const u64 hsw_hw_cache_extra_regs 1565 [PERF_COUNT_HW_CACHE_MAX] 1566 [PERF_COUNT_HW_CACHE_OP_MAX] 1567 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1568 { 1569 [ C(LL ) ] = { 1570 [ C(OP_READ) ] = { 1571 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1572 HSW_LLC_ACCESS, 1573 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1574 HSW_L3_MISS|HSW_ANY_SNOOP, 1575 }, 1576 [ C(OP_WRITE) ] = { 1577 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1578 HSW_LLC_ACCESS, 1579 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1580 HSW_L3_MISS|HSW_ANY_SNOOP, 1581 }, 1582 [ C(OP_PREFETCH) ] = { 1583 [ C(RESULT_ACCESS) ] = 0x0, 1584 [ C(RESULT_MISS) ] = 0x0, 1585 }, 1586 }, 1587 [ C(NODE) ] = { 1588 [ C(OP_READ) ] = { 1589 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1590 HSW_L3_MISS_LOCAL_DRAM| 1591 HSW_SNOOP_DRAM, 1592 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1593 HSW_L3_MISS_REMOTE| 1594 HSW_SNOOP_DRAM, 1595 }, 1596 [ C(OP_WRITE) ] = { 1597 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1598 HSW_L3_MISS_LOCAL_DRAM| 1599 HSW_SNOOP_DRAM, 1600 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1601 HSW_L3_MISS_REMOTE| 1602 HSW_SNOOP_DRAM, 1603 }, 1604 [ C(OP_PREFETCH) ] = { 1605 [ C(RESULT_ACCESS) ] = 0x0, 1606 [ C(RESULT_MISS) ] = 0x0, 1607 }, 1608 }, 1609 }; 1610 1611 static __initconst const u64 westmere_hw_cache_event_ids 1612 [PERF_COUNT_HW_CACHE_MAX] 1613 [PERF_COUNT_HW_CACHE_OP_MAX] 1614 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1615 { 1616 [ C(L1D) ] = { 1617 [ C(OP_READ) ] = { 1618 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1619 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1620 }, 1621 [ C(OP_WRITE) ] = { 1622 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1623 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1624 }, 1625 [ C(OP_PREFETCH) ] = { 1626 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1627 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1628 }, 1629 }, 1630 [ C(L1I ) ] = { 1631 [ C(OP_READ) ] = { 1632 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1633 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1634 }, 1635 [ C(OP_WRITE) ] = { 1636 [ C(RESULT_ACCESS) ] = -1, 1637 [ C(RESULT_MISS) ] = -1, 1638 }, 1639 [ C(OP_PREFETCH) ] = { 1640 [ C(RESULT_ACCESS) ] = 0x0, 1641 [ C(RESULT_MISS) ] = 0x0, 1642 }, 1643 }, 1644 [ C(LL ) ] = { 1645 [ C(OP_READ) ] = { 1646 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1647 [ C(RESULT_ACCESS) ] = 0x01b7, 1648 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1649 [ C(RESULT_MISS) ] = 0x01b7, 1650 }, 1651 /* 1652 * Use RFO, not WRITEBACK, because a write miss would typically occur 1653 * on RFO. 1654 */ 1655 [ C(OP_WRITE) ] = { 1656 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1657 [ C(RESULT_ACCESS) ] = 0x01b7, 1658 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1659 [ C(RESULT_MISS) ] = 0x01b7, 1660 }, 1661 [ C(OP_PREFETCH) ] = { 1662 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1663 [ C(RESULT_ACCESS) ] = 0x01b7, 1664 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1665 [ C(RESULT_MISS) ] = 0x01b7, 1666 }, 1667 }, 1668 [ C(DTLB) ] = { 1669 [ C(OP_READ) ] = { 1670 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1671 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1672 }, 1673 [ C(OP_WRITE) ] = { 1674 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1675 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1676 }, 1677 [ C(OP_PREFETCH) ] = { 1678 [ C(RESULT_ACCESS) ] = 0x0, 1679 [ C(RESULT_MISS) ] = 0x0, 1680 }, 1681 }, 1682 [ C(ITLB) ] = { 1683 [ C(OP_READ) ] = { 1684 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1685 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1686 }, 1687 [ C(OP_WRITE) ] = { 1688 [ C(RESULT_ACCESS) ] = -1, 1689 [ C(RESULT_MISS) ] = -1, 1690 }, 1691 [ C(OP_PREFETCH) ] = { 1692 [ C(RESULT_ACCESS) ] = -1, 1693 [ C(RESULT_MISS) ] = -1, 1694 }, 1695 }, 1696 [ C(BPU ) ] = { 1697 [ C(OP_READ) ] = { 1698 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1699 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1700 }, 1701 [ C(OP_WRITE) ] = { 1702 [ C(RESULT_ACCESS) ] = -1, 1703 [ C(RESULT_MISS) ] = -1, 1704 }, 1705 [ C(OP_PREFETCH) ] = { 1706 [ C(RESULT_ACCESS) ] = -1, 1707 [ C(RESULT_MISS) ] = -1, 1708 }, 1709 }, 1710 [ C(NODE) ] = { 1711 [ C(OP_READ) ] = { 1712 [ C(RESULT_ACCESS) ] = 0x01b7, 1713 [ C(RESULT_MISS) ] = 0x01b7, 1714 }, 1715 [ C(OP_WRITE) ] = { 1716 [ C(RESULT_ACCESS) ] = 0x01b7, 1717 [ C(RESULT_MISS) ] = 0x01b7, 1718 }, 1719 [ C(OP_PREFETCH) ] = { 1720 [ C(RESULT_ACCESS) ] = 0x01b7, 1721 [ C(RESULT_MISS) ] = 0x01b7, 1722 }, 1723 }, 1724 }; 1725 1726 /* 1727 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1728 * See IA32 SDM Vol 3B 30.6.1.3 1729 */ 1730 1731 #define NHM_DMND_DATA_RD (1 << 0) 1732 #define NHM_DMND_RFO (1 << 1) 1733 #define NHM_DMND_IFETCH (1 << 2) 1734 #define NHM_DMND_WB (1 << 3) 1735 #define NHM_PF_DATA_RD (1 << 4) 1736 #define NHM_PF_DATA_RFO (1 << 5) 1737 #define NHM_PF_IFETCH (1 << 6) 1738 #define NHM_OFFCORE_OTHER (1 << 7) 1739 #define NHM_UNCORE_HIT (1 << 8) 1740 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1741 #define NHM_OTHER_CORE_HITM (1 << 10) 1742 /* reserved */ 1743 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1744 #define NHM_REMOTE_DRAM (1 << 13) 1745 #define NHM_LOCAL_DRAM (1 << 14) 1746 #define NHM_NON_DRAM (1 << 15) 1747 1748 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1749 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1750 1751 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1752 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1753 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1754 1755 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1756 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1757 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1758 1759 static __initconst const u64 nehalem_hw_cache_extra_regs 1760 [PERF_COUNT_HW_CACHE_MAX] 1761 [PERF_COUNT_HW_CACHE_OP_MAX] 1762 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1763 { 1764 [ C(LL ) ] = { 1765 [ C(OP_READ) ] = { 1766 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1767 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1768 }, 1769 [ C(OP_WRITE) ] = { 1770 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1771 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1772 }, 1773 [ C(OP_PREFETCH) ] = { 1774 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1775 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1776 }, 1777 }, 1778 [ C(NODE) ] = { 1779 [ C(OP_READ) ] = { 1780 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1781 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1782 }, 1783 [ C(OP_WRITE) ] = { 1784 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1785 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1786 }, 1787 [ C(OP_PREFETCH) ] = { 1788 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1789 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1790 }, 1791 }, 1792 }; 1793 1794 static __initconst const u64 nehalem_hw_cache_event_ids 1795 [PERF_COUNT_HW_CACHE_MAX] 1796 [PERF_COUNT_HW_CACHE_OP_MAX] 1797 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1798 { 1799 [ C(L1D) ] = { 1800 [ C(OP_READ) ] = { 1801 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1802 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1803 }, 1804 [ C(OP_WRITE) ] = { 1805 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1806 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1807 }, 1808 [ C(OP_PREFETCH) ] = { 1809 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1810 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1811 }, 1812 }, 1813 [ C(L1I ) ] = { 1814 [ C(OP_READ) ] = { 1815 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1816 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1817 }, 1818 [ C(OP_WRITE) ] = { 1819 [ C(RESULT_ACCESS) ] = -1, 1820 [ C(RESULT_MISS) ] = -1, 1821 }, 1822 [ C(OP_PREFETCH) ] = { 1823 [ C(RESULT_ACCESS) ] = 0x0, 1824 [ C(RESULT_MISS) ] = 0x0, 1825 }, 1826 }, 1827 [ C(LL ) ] = { 1828 [ C(OP_READ) ] = { 1829 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1830 [ C(RESULT_ACCESS) ] = 0x01b7, 1831 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1832 [ C(RESULT_MISS) ] = 0x01b7, 1833 }, 1834 /* 1835 * Use RFO, not WRITEBACK, because a write miss would typically occur 1836 * on RFO. 1837 */ 1838 [ C(OP_WRITE) ] = { 1839 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1840 [ C(RESULT_ACCESS) ] = 0x01b7, 1841 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1842 [ C(RESULT_MISS) ] = 0x01b7, 1843 }, 1844 [ C(OP_PREFETCH) ] = { 1845 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1846 [ C(RESULT_ACCESS) ] = 0x01b7, 1847 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1848 [ C(RESULT_MISS) ] = 0x01b7, 1849 }, 1850 }, 1851 [ C(DTLB) ] = { 1852 [ C(OP_READ) ] = { 1853 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1854 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1855 }, 1856 [ C(OP_WRITE) ] = { 1857 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1858 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1859 }, 1860 [ C(OP_PREFETCH) ] = { 1861 [ C(RESULT_ACCESS) ] = 0x0, 1862 [ C(RESULT_MISS) ] = 0x0, 1863 }, 1864 }, 1865 [ C(ITLB) ] = { 1866 [ C(OP_READ) ] = { 1867 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1868 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1869 }, 1870 [ C(OP_WRITE) ] = { 1871 [ C(RESULT_ACCESS) ] = -1, 1872 [ C(RESULT_MISS) ] = -1, 1873 }, 1874 [ C(OP_PREFETCH) ] = { 1875 [ C(RESULT_ACCESS) ] = -1, 1876 [ C(RESULT_MISS) ] = -1, 1877 }, 1878 }, 1879 [ C(BPU ) ] = { 1880 [ C(OP_READ) ] = { 1881 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1882 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1883 }, 1884 [ C(OP_WRITE) ] = { 1885 [ C(RESULT_ACCESS) ] = -1, 1886 [ C(RESULT_MISS) ] = -1, 1887 }, 1888 [ C(OP_PREFETCH) ] = { 1889 [ C(RESULT_ACCESS) ] = -1, 1890 [ C(RESULT_MISS) ] = -1, 1891 }, 1892 }, 1893 [ C(NODE) ] = { 1894 [ C(OP_READ) ] = { 1895 [ C(RESULT_ACCESS) ] = 0x01b7, 1896 [ C(RESULT_MISS) ] = 0x01b7, 1897 }, 1898 [ C(OP_WRITE) ] = { 1899 [ C(RESULT_ACCESS) ] = 0x01b7, 1900 [ C(RESULT_MISS) ] = 0x01b7, 1901 }, 1902 [ C(OP_PREFETCH) ] = { 1903 [ C(RESULT_ACCESS) ] = 0x01b7, 1904 [ C(RESULT_MISS) ] = 0x01b7, 1905 }, 1906 }, 1907 }; 1908 1909 static __initconst const u64 core2_hw_cache_event_ids 1910 [PERF_COUNT_HW_CACHE_MAX] 1911 [PERF_COUNT_HW_CACHE_OP_MAX] 1912 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1913 { 1914 [ C(L1D) ] = { 1915 [ C(OP_READ) ] = { 1916 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1917 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1918 }, 1919 [ C(OP_WRITE) ] = { 1920 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1921 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1922 }, 1923 [ C(OP_PREFETCH) ] = { 1924 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1925 [ C(RESULT_MISS) ] = 0, 1926 }, 1927 }, 1928 [ C(L1I ) ] = { 1929 [ C(OP_READ) ] = { 1930 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1931 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1932 }, 1933 [ C(OP_WRITE) ] = { 1934 [ C(RESULT_ACCESS) ] = -1, 1935 [ C(RESULT_MISS) ] = -1, 1936 }, 1937 [ C(OP_PREFETCH) ] = { 1938 [ C(RESULT_ACCESS) ] = 0, 1939 [ C(RESULT_MISS) ] = 0, 1940 }, 1941 }, 1942 [ C(LL ) ] = { 1943 [ C(OP_READ) ] = { 1944 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1945 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1946 }, 1947 [ C(OP_WRITE) ] = { 1948 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1949 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1950 }, 1951 [ C(OP_PREFETCH) ] = { 1952 [ C(RESULT_ACCESS) ] = 0, 1953 [ C(RESULT_MISS) ] = 0, 1954 }, 1955 }, 1956 [ C(DTLB) ] = { 1957 [ C(OP_READ) ] = { 1958 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1959 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1960 }, 1961 [ C(OP_WRITE) ] = { 1962 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1963 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1964 }, 1965 [ C(OP_PREFETCH) ] = { 1966 [ C(RESULT_ACCESS) ] = 0, 1967 [ C(RESULT_MISS) ] = 0, 1968 }, 1969 }, 1970 [ C(ITLB) ] = { 1971 [ C(OP_READ) ] = { 1972 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1973 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1974 }, 1975 [ C(OP_WRITE) ] = { 1976 [ C(RESULT_ACCESS) ] = -1, 1977 [ C(RESULT_MISS) ] = -1, 1978 }, 1979 [ C(OP_PREFETCH) ] = { 1980 [ C(RESULT_ACCESS) ] = -1, 1981 [ C(RESULT_MISS) ] = -1, 1982 }, 1983 }, 1984 [ C(BPU ) ] = { 1985 [ C(OP_READ) ] = { 1986 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1987 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1988 }, 1989 [ C(OP_WRITE) ] = { 1990 [ C(RESULT_ACCESS) ] = -1, 1991 [ C(RESULT_MISS) ] = -1, 1992 }, 1993 [ C(OP_PREFETCH) ] = { 1994 [ C(RESULT_ACCESS) ] = -1, 1995 [ C(RESULT_MISS) ] = -1, 1996 }, 1997 }, 1998 }; 1999 2000 static __initconst const u64 atom_hw_cache_event_ids 2001 [PERF_COUNT_HW_CACHE_MAX] 2002 [PERF_COUNT_HW_CACHE_OP_MAX] 2003 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 2004 { 2005 [ C(L1D) ] = { 2006 [ C(OP_READ) ] = { 2007 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 2008 [ C(RESULT_MISS) ] = 0, 2009 }, 2010 [ C(OP_WRITE) ] = { 2011 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 2012 [ C(RESULT_MISS) ] = 0, 2013 }, 2014 [ C(OP_PREFETCH) ] = { 2015 [ C(RESULT_ACCESS) ] = 0x0, 2016 [ C(RESULT_MISS) ] = 0, 2017 }, 2018 }, 2019 [ C(L1I ) ] = { 2020 [ C(OP_READ) ] = { 2021 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 2022 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 2023 }, 2024 [ C(OP_WRITE) ] = { 2025 [ C(RESULT_ACCESS) ] = -1, 2026 [ C(RESULT_MISS) ] = -1, 2027 }, 2028 [ C(OP_PREFETCH) ] = { 2029 [ C(RESULT_ACCESS) ] = 0, 2030 [ C(RESULT_MISS) ] = 0, 2031 }, 2032 }, 2033 [ C(LL ) ] = { 2034 [ C(OP_READ) ] = { 2035 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 2036 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 2037 }, 2038 [ C(OP_WRITE) ] = { 2039 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 2040 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 2041 }, 2042 [ C(OP_PREFETCH) ] = { 2043 [ C(RESULT_ACCESS) ] = 0, 2044 [ C(RESULT_MISS) ] = 0, 2045 }, 2046 }, 2047 [ C(DTLB) ] = { 2048 [ C(OP_READ) ] = { 2049 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 2050 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 2051 }, 2052 [ C(OP_WRITE) ] = { 2053 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 2054 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 2055 }, 2056 [ C(OP_PREFETCH) ] = { 2057 [ C(RESULT_ACCESS) ] = 0, 2058 [ C(RESULT_MISS) ] = 0, 2059 }, 2060 }, 2061 [ C(ITLB) ] = { 2062 [ C(OP_READ) ] = { 2063 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 2064 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 2065 }, 2066 [ C(OP_WRITE) ] = { 2067 [ C(RESULT_ACCESS) ] = -1, 2068 [ C(RESULT_MISS) ] = -1, 2069 }, 2070 [ C(OP_PREFETCH) ] = { 2071 [ C(RESULT_ACCESS) ] = -1, 2072 [ C(RESULT_MISS) ] = -1, 2073 }, 2074 }, 2075 [ C(BPU ) ] = { 2076 [ C(OP_READ) ] = { 2077 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 2078 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 2079 }, 2080 [ C(OP_WRITE) ] = { 2081 [ C(RESULT_ACCESS) ] = -1, 2082 [ C(RESULT_MISS) ] = -1, 2083 }, 2084 [ C(OP_PREFETCH) ] = { 2085 [ C(RESULT_ACCESS) ] = -1, 2086 [ C(RESULT_MISS) ] = -1, 2087 }, 2088 }, 2089 }; 2090 2091 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 2092 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 2093 /* no_alloc_cycles.not_delivered */ 2094 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 2095 "event=0xca,umask=0x50"); 2096 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 2097 /* uops_retired.all */ 2098 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 2099 "event=0xc2,umask=0x10"); 2100 /* uops_retired.all */ 2101 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 2102 "event=0xc2,umask=0x10"); 2103 2104 static struct attribute *slm_events_attrs[] = { 2105 EVENT_PTR(td_total_slots_slm), 2106 EVENT_PTR(td_total_slots_scale_slm), 2107 EVENT_PTR(td_fetch_bubbles_slm), 2108 EVENT_PTR(td_fetch_bubbles_scale_slm), 2109 EVENT_PTR(td_slots_issued_slm), 2110 EVENT_PTR(td_slots_retired_slm), 2111 NULL 2112 }; 2113 2114 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 2115 { 2116 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2117 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 2118 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 2119 EVENT_EXTRA_END 2120 }; 2121 2122 #define SLM_DMND_READ SNB_DMND_DATA_RD 2123 #define SLM_DMND_WRITE SNB_DMND_RFO 2124 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 2125 2126 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 2127 #define SLM_LLC_ACCESS SNB_RESP_ANY 2128 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 2129 2130 static __initconst const u64 slm_hw_cache_extra_regs 2131 [PERF_COUNT_HW_CACHE_MAX] 2132 [PERF_COUNT_HW_CACHE_OP_MAX] 2133 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 2134 { 2135 [ C(LL ) ] = { 2136 [ C(OP_READ) ] = { 2137 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 2138 [ C(RESULT_MISS) ] = 0, 2139 }, 2140 [ C(OP_WRITE) ] = { 2141 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 2142 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 2143 }, 2144 [ C(OP_PREFETCH) ] = { 2145 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 2146 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 2147 }, 2148 }, 2149 }; 2150 2151 static __initconst const u64 slm_hw_cache_event_ids 2152 [PERF_COUNT_HW_CACHE_MAX] 2153 [PERF_COUNT_HW_CACHE_OP_MAX] 2154 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 2155 { 2156 [ C(L1D) ] = { 2157 [ C(OP_READ) ] = { 2158 [ C(RESULT_ACCESS) ] = 0, 2159 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 2160 }, 2161 [ C(OP_WRITE) ] = { 2162 [ C(RESULT_ACCESS) ] = 0, 2163 [ C(RESULT_MISS) ] = 0, 2164 }, 2165 [ C(OP_PREFETCH) ] = { 2166 [ C(RESULT_ACCESS) ] = 0, 2167 [ C(RESULT_MISS) ] = 0, 2168 }, 2169 }, 2170 [ C(L1I ) ] = { 2171 [ C(OP_READ) ] = { 2172 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 2173 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 2174 }, 2175 [ C(OP_WRITE) ] = { 2176 [ C(RESULT_ACCESS) ] = -1, 2177 [ C(RESULT_MISS) ] = -1, 2178 }, 2179 [ C(OP_PREFETCH) ] = { 2180 [ C(RESULT_ACCESS) ] = 0, 2181 [ C(RESULT_MISS) ] = 0, 2182 }, 2183 }, 2184 [ C(LL ) ] = { 2185 [ C(OP_READ) ] = { 2186 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 2187 [ C(RESULT_ACCESS) ] = 0x01b7, 2188 [ C(RESULT_MISS) ] = 0, 2189 }, 2190 [ C(OP_WRITE) ] = { 2191 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 2192 [ C(RESULT_ACCESS) ] = 0x01b7, 2193 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 2194 [ C(RESULT_MISS) ] = 0x01b7, 2195 }, 2196 [ C(OP_PREFETCH) ] = { 2197 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 2198 [ C(RESULT_ACCESS) ] = 0x01b7, 2199 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 2200 [ C(RESULT_MISS) ] = 0x01b7, 2201 }, 2202 }, 2203 [ C(DTLB) ] = { 2204 [ C(OP_READ) ] = { 2205 [ C(RESULT_ACCESS) ] = 0, 2206 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 2207 }, 2208 [ C(OP_WRITE) ] = { 2209 [ C(RESULT_ACCESS) ] = 0, 2210 [ C(RESULT_MISS) ] = 0, 2211 }, 2212 [ C(OP_PREFETCH) ] = { 2213 [ C(RESULT_ACCESS) ] = 0, 2214 [ C(RESULT_MISS) ] = 0, 2215 }, 2216 }, 2217 [ C(ITLB) ] = { 2218 [ C(OP_READ) ] = { 2219 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 2220 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 2221 }, 2222 [ C(OP_WRITE) ] = { 2223 [ C(RESULT_ACCESS) ] = -1, 2224 [ C(RESULT_MISS) ] = -1, 2225 }, 2226 [ C(OP_PREFETCH) ] = { 2227 [ C(RESULT_ACCESS) ] = -1, 2228 [ C(RESULT_MISS) ] = -1, 2229 }, 2230 }, 2231 [ C(BPU ) ] = { 2232 [ C(OP_READ) ] = { 2233 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 2234 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 2235 }, 2236 [ C(OP_WRITE) ] = { 2237 [ C(RESULT_ACCESS) ] = -1, 2238 [ C(RESULT_MISS) ] = -1, 2239 }, 2240 [ C(OP_PREFETCH) ] = { 2241 [ C(RESULT_ACCESS) ] = -1, 2242 [ C(RESULT_MISS) ] = -1, 2243 }, 2244 }, 2245 }; 2246 2247 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 2248 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 2249 /* UOPS_NOT_DELIVERED.ANY */ 2250 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 2251 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 2252 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 2253 /* UOPS_RETIRED.ANY */ 2254 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 2255 /* UOPS_ISSUED.ANY */ 2256 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 2257 2258 static struct attribute *glm_events_attrs[] = { 2259 EVENT_PTR(td_total_slots_glm), 2260 EVENT_PTR(td_total_slots_scale_glm), 2261 EVENT_PTR(td_fetch_bubbles_glm), 2262 EVENT_PTR(td_recovery_bubbles_glm), 2263 EVENT_PTR(td_slots_issued_glm), 2264 EVENT_PTR(td_slots_retired_glm), 2265 NULL 2266 }; 2267 2268 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 2269 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2270 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 2271 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 2272 EVENT_EXTRA_END 2273 }; 2274 2275 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 2276 #define GLM_DEMAND_RFO BIT_ULL(1) 2277 #define GLM_ANY_RESPONSE BIT_ULL(16) 2278 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 2279 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 2280 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 2281 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 2282 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 2283 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 2284 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 2285 2286 static __initconst const u64 glm_hw_cache_event_ids 2287 [PERF_COUNT_HW_CACHE_MAX] 2288 [PERF_COUNT_HW_CACHE_OP_MAX] 2289 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2290 [C(L1D)] = { 2291 [C(OP_READ)] = { 2292 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2293 [C(RESULT_MISS)] = 0x0, 2294 }, 2295 [C(OP_WRITE)] = { 2296 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2297 [C(RESULT_MISS)] = 0x0, 2298 }, 2299 [C(OP_PREFETCH)] = { 2300 [C(RESULT_ACCESS)] = 0x0, 2301 [C(RESULT_MISS)] = 0x0, 2302 }, 2303 }, 2304 [C(L1I)] = { 2305 [C(OP_READ)] = { 2306 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 2307 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 2308 }, 2309 [C(OP_WRITE)] = { 2310 [C(RESULT_ACCESS)] = -1, 2311 [C(RESULT_MISS)] = -1, 2312 }, 2313 [C(OP_PREFETCH)] = { 2314 [C(RESULT_ACCESS)] = 0x0, 2315 [C(RESULT_MISS)] = 0x0, 2316 }, 2317 }, 2318 [C(LL)] = { 2319 [C(OP_READ)] = { 2320 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2321 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2322 }, 2323 [C(OP_WRITE)] = { 2324 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2325 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2326 }, 2327 [C(OP_PREFETCH)] = { 2328 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2329 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2330 }, 2331 }, 2332 [C(DTLB)] = { 2333 [C(OP_READ)] = { 2334 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2335 [C(RESULT_MISS)] = 0x0, 2336 }, 2337 [C(OP_WRITE)] = { 2338 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2339 [C(RESULT_MISS)] = 0x0, 2340 }, 2341 [C(OP_PREFETCH)] = { 2342 [C(RESULT_ACCESS)] = 0x0, 2343 [C(RESULT_MISS)] = 0x0, 2344 }, 2345 }, 2346 [C(ITLB)] = { 2347 [C(OP_READ)] = { 2348 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2349 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2350 }, 2351 [C(OP_WRITE)] = { 2352 [C(RESULT_ACCESS)] = -1, 2353 [C(RESULT_MISS)] = -1, 2354 }, 2355 [C(OP_PREFETCH)] = { 2356 [C(RESULT_ACCESS)] = -1, 2357 [C(RESULT_MISS)] = -1, 2358 }, 2359 }, 2360 [C(BPU)] = { 2361 [C(OP_READ)] = { 2362 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2363 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2364 }, 2365 [C(OP_WRITE)] = { 2366 [C(RESULT_ACCESS)] = -1, 2367 [C(RESULT_MISS)] = -1, 2368 }, 2369 [C(OP_PREFETCH)] = { 2370 [C(RESULT_ACCESS)] = -1, 2371 [C(RESULT_MISS)] = -1, 2372 }, 2373 }, 2374 }; 2375 2376 static __initconst const u64 glm_hw_cache_extra_regs 2377 [PERF_COUNT_HW_CACHE_MAX] 2378 [PERF_COUNT_HW_CACHE_OP_MAX] 2379 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2380 [C(LL)] = { 2381 [C(OP_READ)] = { 2382 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2383 GLM_LLC_ACCESS, 2384 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2385 GLM_LLC_MISS, 2386 }, 2387 [C(OP_WRITE)] = { 2388 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2389 GLM_LLC_ACCESS, 2390 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2391 GLM_LLC_MISS, 2392 }, 2393 [C(OP_PREFETCH)] = { 2394 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 2395 GLM_LLC_ACCESS, 2396 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 2397 GLM_LLC_MISS, 2398 }, 2399 }, 2400 }; 2401 2402 static __initconst const u64 glp_hw_cache_event_ids 2403 [PERF_COUNT_HW_CACHE_MAX] 2404 [PERF_COUNT_HW_CACHE_OP_MAX] 2405 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2406 [C(L1D)] = { 2407 [C(OP_READ)] = { 2408 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2409 [C(RESULT_MISS)] = 0x0, 2410 }, 2411 [C(OP_WRITE)] = { 2412 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2413 [C(RESULT_MISS)] = 0x0, 2414 }, 2415 [C(OP_PREFETCH)] = { 2416 [C(RESULT_ACCESS)] = 0x0, 2417 [C(RESULT_MISS)] = 0x0, 2418 }, 2419 }, 2420 [C(L1I)] = { 2421 [C(OP_READ)] = { 2422 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 2423 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 2424 }, 2425 [C(OP_WRITE)] = { 2426 [C(RESULT_ACCESS)] = -1, 2427 [C(RESULT_MISS)] = -1, 2428 }, 2429 [C(OP_PREFETCH)] = { 2430 [C(RESULT_ACCESS)] = 0x0, 2431 [C(RESULT_MISS)] = 0x0, 2432 }, 2433 }, 2434 [C(LL)] = { 2435 [C(OP_READ)] = { 2436 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2437 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2438 }, 2439 [C(OP_WRITE)] = { 2440 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2441 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2442 }, 2443 [C(OP_PREFETCH)] = { 2444 [C(RESULT_ACCESS)] = 0x0, 2445 [C(RESULT_MISS)] = 0x0, 2446 }, 2447 }, 2448 [C(DTLB)] = { 2449 [C(OP_READ)] = { 2450 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2451 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 2452 }, 2453 [C(OP_WRITE)] = { 2454 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2455 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 2456 }, 2457 [C(OP_PREFETCH)] = { 2458 [C(RESULT_ACCESS)] = 0x0, 2459 [C(RESULT_MISS)] = 0x0, 2460 }, 2461 }, 2462 [C(ITLB)] = { 2463 [C(OP_READ)] = { 2464 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2465 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2466 }, 2467 [C(OP_WRITE)] = { 2468 [C(RESULT_ACCESS)] = -1, 2469 [C(RESULT_MISS)] = -1, 2470 }, 2471 [C(OP_PREFETCH)] = { 2472 [C(RESULT_ACCESS)] = -1, 2473 [C(RESULT_MISS)] = -1, 2474 }, 2475 }, 2476 [C(BPU)] = { 2477 [C(OP_READ)] = { 2478 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2479 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2480 }, 2481 [C(OP_WRITE)] = { 2482 [C(RESULT_ACCESS)] = -1, 2483 [C(RESULT_MISS)] = -1, 2484 }, 2485 [C(OP_PREFETCH)] = { 2486 [C(RESULT_ACCESS)] = -1, 2487 [C(RESULT_MISS)] = -1, 2488 }, 2489 }, 2490 }; 2491 2492 static __initconst const u64 glp_hw_cache_extra_regs 2493 [PERF_COUNT_HW_CACHE_MAX] 2494 [PERF_COUNT_HW_CACHE_OP_MAX] 2495 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2496 [C(LL)] = { 2497 [C(OP_READ)] = { 2498 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2499 GLM_LLC_ACCESS, 2500 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2501 GLM_LLC_MISS, 2502 }, 2503 [C(OP_WRITE)] = { 2504 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2505 GLM_LLC_ACCESS, 2506 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2507 GLM_LLC_MISS, 2508 }, 2509 [C(OP_PREFETCH)] = { 2510 [C(RESULT_ACCESS)] = 0x0, 2511 [C(RESULT_MISS)] = 0x0, 2512 }, 2513 }, 2514 }; 2515 2516 #define TNT_LOCAL_DRAM BIT_ULL(26) 2517 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2518 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2519 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2520 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2521 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2522 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2523 2524 static __initconst const u64 tnt_hw_cache_extra_regs 2525 [PERF_COUNT_HW_CACHE_MAX] 2526 [PERF_COUNT_HW_CACHE_OP_MAX] 2527 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2528 [C(LL)] = { 2529 [C(OP_READ)] = { 2530 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2531 TNT_LLC_ACCESS, 2532 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2533 TNT_LLC_MISS, 2534 }, 2535 [C(OP_WRITE)] = { 2536 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2537 TNT_LLC_ACCESS, 2538 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2539 TNT_LLC_MISS, 2540 }, 2541 [C(OP_PREFETCH)] = { 2542 [C(RESULT_ACCESS)] = 0x0, 2543 [C(RESULT_MISS)] = 0x0, 2544 }, 2545 }, 2546 }; 2547 2548 static __initconst const u64 grt_hw_cache_extra_regs 2549 [PERF_COUNT_HW_CACHE_MAX] 2550 [PERF_COUNT_HW_CACHE_OP_MAX] 2551 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2552 [C(LL)] = { 2553 [C(OP_READ)] = { 2554 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ 2555 [C(RESULT_MISS)] = 0x3F84400001, /* OCR.DEMAND_DATA_RD.L3_MISS */ 2556 }, 2557 [C(OP_WRITE)] = { 2558 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ 2559 [C(RESULT_MISS)] = 0x3F84400002, /* OCR.DEMAND_RFO.L3_MISS */ 2560 }, 2561 }, 2562 }; 2563 2564 static __initconst const u64 cmt_hw_cache_extra_regs 2565 [PERF_COUNT_HW_CACHE_MAX] 2566 [PERF_COUNT_HW_CACHE_OP_MAX] 2567 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2568 [C(LL)] = { 2569 [C(OP_READ)] = { 2570 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ 2571 [C(RESULT_MISS)] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */ 2572 }, 2573 [C(OP_WRITE)] = { 2574 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ 2575 [C(RESULT_MISS)] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */ 2576 }, 2577 }, 2578 }; 2579 2580 static __initconst const u64 skt_hw_cache_extra_regs 2581 [PERF_COUNT_HW_CACHE_MAX] 2582 [PERF_COUNT_HW_CACHE_OP_MAX] 2583 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2584 [C(LL)] = { 2585 [C(OP_READ)] = { 2586 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ 2587 [C(RESULT_MISS)] = 0x13FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */ 2588 }, 2589 [C(OP_WRITE)] = { 2590 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ 2591 [C(RESULT_MISS)] = 0x13FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */ 2592 }, 2593 }, 2594 }; 2595 2596 static __initconst const u64 dkt_hw_cache_extra_regs 2597 [PERF_COUNT_HW_CACHE_MAX] 2598 [PERF_COUNT_HW_CACHE_OP_MAX] 2599 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2600 [C(LL)] = { 2601 [C(OP_READ)] = { 2602 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ 2603 [C(RESULT_MISS)] = 0x33FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */ 2604 }, 2605 [C(OP_WRITE)] = { 2606 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ 2607 [C(RESULT_MISS)] = 0x33FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */ 2608 }, 2609 }, 2610 }; 2611 2612 static __initconst const u64 arw_hw_cache_extra_regs 2613 [PERF_COUNT_HW_CACHE_MAX] 2614 [PERF_COUNT_HW_CACHE_OP_MAX] 2615 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2616 [C(LL)] = { 2617 [C(OP_READ)] = { 2618 [C(RESULT_ACCESS)] = 0x4000000000000009, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */ 2619 [C(RESULT_MISS)] = 0xFF03F000000009, /* OMR.DEMAND_DATA_RD.L3_MISS */ 2620 }, 2621 [C(OP_WRITE)] = { 2622 [C(RESULT_ACCESS)] = 0x400000000000000A, /* OMR.DEMAND_RFO.ANY_RESPONSE */ 2623 [C(RESULT_MISS)] = 0xFF03F00000000A, /* OMR.DEMAND_RFO.L3_MISS */ 2624 }, 2625 }, 2626 }; 2627 2628 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2629 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2630 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2631 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2632 2633 static struct attribute *tnt_events_attrs[] = { 2634 EVENT_PTR(td_fe_bound_tnt), 2635 EVENT_PTR(td_retiring_tnt), 2636 EVENT_PTR(td_bad_spec_tnt), 2637 EVENT_PTR(td_be_bound_tnt), 2638 NULL, 2639 }; 2640 2641 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2642 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2643 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2644 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2645 EVENT_EXTRA_END 2646 }; 2647 2648 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3"); 2649 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6"); 2650 2651 static struct attribute *grt_mem_attrs[] = { 2652 EVENT_PTR(mem_ld_grt), 2653 EVENT_PTR(mem_st_grt), 2654 NULL 2655 }; 2656 2657 static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2658 /* 2659 * Must define OFFCORE_RSP_X first, see intel_fixup_er(). 2660 * Bit 63 only valid on OFFCORE_RSP_0 MSR. 2661 */ 2662 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x8003f03fffffffffull, RSP_0), 2663 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3f03fffffffffull, RSP_1), 2664 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2665 EVENT_EXTRA_END 2666 }; 2667 2668 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0"); 2669 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0"); 2670 2671 static struct attribute *cmt_events_attrs[] = { 2672 EVENT_PTR(td_fe_bound_tnt), 2673 EVENT_PTR(td_retiring_cmt), 2674 EVENT_PTR(td_bad_spec_cmt), 2675 EVENT_PTR(td_be_bound_tnt), 2676 NULL 2677 }; 2678 2679 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = { 2680 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2681 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0), 2682 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1), 2683 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2684 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2685 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), 2686 EVENT_EXTRA_END 2687 }; 2688 2689 static struct extra_reg intel_arw_extra_regs[] __read_mostly = { 2690 /* must define OMR_X first, see intel_alt_er() */ 2691 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0), 2692 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1), 2693 INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2), 2694 INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3), 2695 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2696 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2697 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), 2698 EVENT_EXTRA_END 2699 }; 2700 2701 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_skt, "event=0x9c,umask=0x01"); 2702 EVENT_ATTR_STR(topdown-retiring, td_retiring_skt, "event=0xc2,umask=0x02"); 2703 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_skt, "event=0xa4,umask=0x02"); 2704 2705 static struct attribute *skt_events_attrs[] = { 2706 EVENT_PTR(td_fe_bound_skt), 2707 EVENT_PTR(td_retiring_skt), 2708 EVENT_PTR(td_bad_spec_cmt), 2709 EVENT_PTR(td_be_bound_skt), 2710 NULL, 2711 }; 2712 2713 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2714 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2715 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 2716 #define KNL_MCDRAM_FAR BIT_ULL(22) 2717 #define KNL_DDR_LOCAL BIT_ULL(23) 2718 #define KNL_DDR_FAR BIT_ULL(24) 2719 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2720 KNL_DDR_LOCAL | KNL_DDR_FAR) 2721 #define KNL_L2_READ SLM_DMND_READ 2722 #define KNL_L2_WRITE SLM_DMND_WRITE 2723 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2724 #define KNL_L2_ACCESS SLM_LLC_ACCESS 2725 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2726 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2727 SNB_NON_DRAM) 2728 2729 static __initconst const u64 knl_hw_cache_extra_regs 2730 [PERF_COUNT_HW_CACHE_MAX] 2731 [PERF_COUNT_HW_CACHE_OP_MAX] 2732 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2733 [C(LL)] = { 2734 [C(OP_READ)] = { 2735 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2736 [C(RESULT_MISS)] = 0, 2737 }, 2738 [C(OP_WRITE)] = { 2739 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2740 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2741 }, 2742 [C(OP_PREFETCH)] = { 2743 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2744 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2745 }, 2746 }, 2747 }; 2748 2749 /* 2750 * Used from PMIs where the LBRs are already disabled. 2751 * 2752 * This function could be called consecutively. It is required to remain in 2753 * disabled state if called consecutively. 2754 * 2755 * During consecutive calls, the same disable value will be written to related 2756 * registers, so the PMU state remains unchanged. 2757 * 2758 * intel_bts events don't coexist with intel PMU's BTS events because of 2759 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2760 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2761 * 2762 * Avoid PEBS_ENABLE MSR access in PMIs. 2763 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2764 * It doesn't matter if the PEBS is enabled or not. 2765 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2766 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2767 * However, there are some cases which may change PEBS status, e.g. PMI 2768 * throttle. The PEBS_ENABLE should be updated where the status changes. 2769 */ 2770 static __always_inline void __intel_pmu_disable_all(bool bts) 2771 { 2772 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2773 2774 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2775 2776 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2777 intel_pmu_disable_bts(); 2778 } 2779 2780 static __always_inline void intel_pmu_disable_all(void) 2781 { 2782 __intel_pmu_disable_all(true); 2783 static_call_cond(x86_pmu_pebs_disable_all)(); 2784 intel_pmu_lbr_disable_all(); 2785 } 2786 2787 static void __intel_pmu_enable_all(int added, bool pmi) 2788 { 2789 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2790 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2791 2792 intel_pmu_lbr_enable_all(pmi); 2793 2794 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) { 2795 wrmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val); 2796 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val; 2797 } 2798 2799 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 2800 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2801 2802 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2803 struct perf_event *event = 2804 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2805 2806 if (WARN_ON_ONCE(!event)) 2807 return; 2808 2809 intel_pmu_enable_bts(event->hw.config); 2810 } 2811 } 2812 2813 static void intel_pmu_enable_all(int added) 2814 { 2815 static_call_cond(x86_pmu_pebs_enable_all)(); 2816 __intel_pmu_enable_all(added, false); 2817 } 2818 2819 static noinline int 2820 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2821 unsigned int cnt, unsigned long flags) 2822 { 2823 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2824 2825 intel_pmu_lbr_read(); 2826 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2827 2828 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2829 intel_pmu_enable_all(0); 2830 local_irq_restore(flags); 2831 return cnt; 2832 } 2833 2834 static int 2835 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2836 { 2837 unsigned long flags; 2838 2839 /* must not have branches... */ 2840 local_irq_save(flags); 2841 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2842 __intel_pmu_lbr_disable(); 2843 /* ... until here */ 2844 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2845 } 2846 2847 static int 2848 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2849 { 2850 unsigned long flags; 2851 2852 /* must not have branches... */ 2853 local_irq_save(flags); 2854 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2855 __intel_pmu_arch_lbr_disable(); 2856 /* ... until here */ 2857 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2858 } 2859 2860 /* 2861 * Workaround for: 2862 * Intel Errata AAK100 (model 26) 2863 * Intel Errata AAP53 (model 30) 2864 * Intel Errata BD53 (model 44) 2865 * 2866 * The official story: 2867 * These chips need to be 'reset' when adding counters by programming the 2868 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2869 * in sequence on the same PMC or on different PMCs. 2870 * 2871 * In practice it appears some of these events do in fact count, and 2872 * we need to program all 4 events. 2873 */ 2874 static void intel_pmu_nhm_workaround(void) 2875 { 2876 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2877 static const unsigned long nhm_magic[4] = { 2878 0x4300B5, 2879 0x4300D2, 2880 0x4300B1, 2881 0x4300B1 2882 }; 2883 struct perf_event *event; 2884 int i; 2885 2886 /* 2887 * The Errata requires below steps: 2888 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2889 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2890 * the corresponding PMCx; 2891 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2892 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2893 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2894 */ 2895 2896 /* 2897 * The real steps we choose are a little different from above. 2898 * A) To reduce MSR operations, we don't run step 1) as they 2899 * are already cleared before this function is called; 2900 * B) Call x86_perf_event_update to save PMCx before configuring 2901 * PERFEVTSELx with magic number; 2902 * C) With step 5), we do clear only when the PERFEVTSELx is 2903 * not used currently. 2904 * D) Call x86_perf_event_set_period to restore PMCx; 2905 */ 2906 2907 /* We always operate 4 pairs of PERF Counters */ 2908 for (i = 0; i < 4; i++) { 2909 event = cpuc->events[i]; 2910 if (event) 2911 static_call(x86_pmu_update)(event); 2912 } 2913 2914 for (i = 0; i < 4; i++) { 2915 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2916 wrmsrq(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2917 } 2918 2919 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2920 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2921 2922 for (i = 0; i < 4; i++) { 2923 event = cpuc->events[i]; 2924 2925 if (event) { 2926 static_call(x86_pmu_set_period)(event); 2927 __x86_pmu_enable_event(&event->hw, 2928 ARCH_PERFMON_EVENTSEL_ENABLE); 2929 } else 2930 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2931 } 2932 } 2933 2934 static void intel_pmu_nhm_enable_all(int added) 2935 { 2936 if (added) 2937 intel_pmu_nhm_workaround(); 2938 intel_pmu_enable_all(added); 2939 } 2940 2941 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2942 { 2943 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2944 2945 if (cpuc->tfa_shadow != val) { 2946 cpuc->tfa_shadow = val; 2947 wrmsrq(MSR_TSX_FORCE_ABORT, val); 2948 } 2949 } 2950 2951 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2952 { 2953 /* 2954 * We're going to use PMC3, make sure TFA is set before we touch it. 2955 */ 2956 if (cntr == 3) 2957 intel_set_tfa(cpuc, true); 2958 } 2959 2960 static void intel_tfa_pmu_enable_all(int added) 2961 { 2962 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2963 2964 /* 2965 * If we find PMC3 is no longer used when we enable the PMU, we can 2966 * clear TFA. 2967 */ 2968 if (!test_bit(3, cpuc->active_mask)) 2969 intel_set_tfa(cpuc, false); 2970 2971 intel_pmu_enable_all(added); 2972 } 2973 2974 static inline u64 intel_pmu_get_status(void) 2975 { 2976 u64 status; 2977 2978 rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); 2979 2980 return status; 2981 } 2982 2983 static inline void intel_pmu_ack_status(u64 ack) 2984 { 2985 wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2986 } 2987 2988 static inline bool event_is_checkpointed(struct perf_event *event) 2989 { 2990 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2991 } 2992 2993 static inline void intel_set_masks(struct perf_event *event, int idx) 2994 { 2995 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2996 2997 if (event->attr.exclude_host) 2998 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2999 if (event->attr.exclude_guest) 3000 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 3001 if (event_is_checkpointed(event)) 3002 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 3003 } 3004 3005 static inline void intel_clear_masks(struct perf_event *event, int idx) 3006 { 3007 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3008 3009 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 3010 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 3011 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 3012 } 3013 3014 static void intel_pmu_disable_fixed(struct perf_event *event) 3015 { 3016 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3017 struct hw_perf_event *hwc = &event->hw; 3018 int idx = hwc->idx; 3019 u64 mask; 3020 3021 if (is_topdown_idx(idx)) { 3022 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3023 3024 /* 3025 * When there are other active TopDown events, 3026 * don't disable the fixed counter 3. 3027 */ 3028 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 3029 return; 3030 idx = INTEL_PMC_IDX_FIXED_SLOTS; 3031 } 3032 3033 intel_clear_masks(event, idx); 3034 3035 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK); 3036 cpuc->fixed_ctrl_val &= ~mask; 3037 } 3038 3039 static inline void __intel_pmu_update_event_ext(int idx, u64 ext) 3040 { 3041 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3042 u32 msr; 3043 3044 if (idx < INTEL_PMC_IDX_FIXED) { 3045 msr = MSR_IA32_PMC_V6_GP0_CFG_C + 3046 x86_pmu.addr_offset(idx, false); 3047 } else { 3048 msr = MSR_IA32_PMC_V6_FX0_CFG_C + 3049 x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false); 3050 } 3051 3052 cpuc->cfg_c_val[idx] = ext; 3053 wrmsrq(msr, ext); 3054 } 3055 3056 static void intel_pmu_disable_event_ext(struct perf_event *event) 3057 { 3058 /* 3059 * Only clear CFG_C MSR for PEBS counter group events, 3060 * it avoids the HW counter's value to be added into 3061 * other PEBS records incorrectly after PEBS counter 3062 * group events are disabled. 3063 * 3064 * For other events, it's unnecessary to clear CFG_C MSRs 3065 * since CFG_C doesn't take effect if counter is in 3066 * disabled state. That helps to reduce the WRMSR overhead 3067 * in context switches. 3068 */ 3069 if (!is_pebs_counter_event_group(event)) 3070 return; 3071 3072 __intel_pmu_update_event_ext(event->hw.idx, 0); 3073 } 3074 3075 DEFINE_STATIC_CALL_NULL(intel_pmu_disable_event_ext, intel_pmu_disable_event_ext); 3076 3077 static void intel_pmu_disable_event(struct perf_event *event) 3078 { 3079 struct hw_perf_event *hwc = &event->hw; 3080 int idx = hwc->idx; 3081 3082 switch (idx) { 3083 case 0 ... INTEL_PMC_IDX_FIXED - 1: 3084 intel_clear_masks(event, idx); 3085 static_call_cond(intel_pmu_disable_event_ext)(event); 3086 x86_pmu_disable_event(event); 3087 break; 3088 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 3089 static_call_cond(intel_pmu_disable_event_ext)(event); 3090 fallthrough; 3091 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 3092 intel_pmu_disable_fixed(event); 3093 break; 3094 case INTEL_PMC_IDX_FIXED_BTS: 3095 intel_pmu_disable_bts(); 3096 intel_pmu_drain_bts_buffer(); 3097 return; 3098 case INTEL_PMC_IDX_FIXED_VLBR: 3099 intel_clear_masks(event, idx); 3100 break; 3101 default: 3102 intel_clear_masks(event, idx); 3103 pr_warn("Failed to disable the event with invalid index %d\n", 3104 idx); 3105 return; 3106 } 3107 3108 /* 3109 * Needs to be called after x86_pmu_disable_event, 3110 * so we don't trigger the event without PEBS bit set. 3111 */ 3112 if (unlikely(event->attr.precise_ip)) 3113 static_call(x86_pmu_pebs_disable)(event); 3114 } 3115 3116 static void intel_pmu_assign_event(struct perf_event *event, int idx) 3117 { 3118 if (is_pebs_pt(event)) 3119 perf_report_aux_output_id(event, idx); 3120 } 3121 3122 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event) 3123 { 3124 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK; 3125 } 3126 3127 static void intel_pmu_del_event(struct perf_event *event) 3128 { 3129 if (intel_pmu_needs_branch_stack(event)) 3130 intel_pmu_lbr_del(event); 3131 if (event->attr.precise_ip) 3132 intel_pmu_pebs_del(event); 3133 if (is_pebs_counter_event_group(event) || 3134 is_acr_event_group(event)) 3135 this_cpu_ptr(&cpu_hw_events)->n_late_setup--; 3136 } 3137 3138 int __intel_pmu_quiesce(void) 3139 { 3140 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3141 int pmu_enabled = cpuc->enabled; 3142 3143 cpuc->enabled = 0; 3144 if (pmu_enabled) 3145 intel_pmu_disable_all(); 3146 3147 return pmu_enabled; 3148 } 3149 3150 void __intel_pmu_resume(int pmu_enabled) 3151 { 3152 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3153 3154 cpuc->enabled = pmu_enabled; 3155 if (pmu_enabled) 3156 intel_pmu_enable_all(0); 3157 } 3158 3159 static int icl_set_topdown_event_period(struct perf_event *event) 3160 { 3161 struct hw_perf_event *hwc = &event->hw; 3162 s64 left = local64_read(&hwc->period_left); 3163 3164 /* 3165 * The values in PERF_METRICS MSR are derived from fixed counter 3. 3166 * Software should start both registers, PERF_METRICS and fixed 3167 * counter 3, from zero. 3168 * Clear PERF_METRICS and Fixed counter 3 in initialization. 3169 * After that, both MSRs will be cleared for each read. 3170 * Don't need to clear them again. 3171 */ 3172 if (left == x86_pmu.max_period) { 3173 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0); 3174 wrmsrq(MSR_PERF_METRICS, 0); 3175 hwc->saved_slots = 0; 3176 hwc->saved_metric = 0; 3177 } 3178 3179 if ((hwc->saved_slots) && is_slots_event(event)) { 3180 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 3181 wrmsrq(MSR_PERF_METRICS, hwc->saved_metric); 3182 } 3183 3184 perf_event_update_userpage(event); 3185 3186 return 0; 3187 } 3188 3189 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period); 3190 3191 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 3192 { 3193 u32 val; 3194 3195 /* 3196 * The metric is reported as an 8bit integer fraction 3197 * summing up to 0xff. 3198 * slots-in-metric = (Metric / 0xff) * slots 3199 */ 3200 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 3201 return mul_u64_u32_div(slots, val, 0xff); 3202 } 3203 3204 static u64 icl_get_topdown_value(struct perf_event *event, 3205 u64 slots, u64 metrics) 3206 { 3207 int idx = event->hw.idx; 3208 u64 delta; 3209 3210 if (is_metric_idx(idx)) 3211 delta = icl_get_metrics_event_value(metrics, slots, idx); 3212 else 3213 delta = slots; 3214 3215 return delta; 3216 } 3217 3218 static void __icl_update_topdown_event(struct perf_event *event, 3219 u64 slots, u64 metrics, 3220 u64 last_slots, u64 last_metrics) 3221 { 3222 u64 delta, last = 0; 3223 3224 delta = icl_get_topdown_value(event, slots, metrics); 3225 if (last_slots) 3226 last = icl_get_topdown_value(event, last_slots, last_metrics); 3227 3228 /* 3229 * The 8bit integer fraction of metric may be not accurate, 3230 * especially when the changes is very small. 3231 * For example, if only a few bad_spec happens, the fraction 3232 * may be reduced from 1 to 0. If so, the bad_spec event value 3233 * will be 0 which is definitely less than the last value. 3234 * Avoid update event->count for this case. 3235 */ 3236 if (delta > last) { 3237 delta -= last; 3238 local64_add(delta, &event->count); 3239 } 3240 } 3241 3242 static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 3243 u64 metrics, int metric_end) 3244 { 3245 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3246 struct perf_event *other; 3247 int idx; 3248 3249 event->hw.saved_slots = slots; 3250 event->hw.saved_metric = metrics; 3251 3252 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 3253 if (!is_topdown_idx(idx)) 3254 continue; 3255 other = cpuc->events[idx]; 3256 other->hw.saved_slots = slots; 3257 other->hw.saved_metric = metrics; 3258 } 3259 } 3260 3261 /* 3262 * Update all active Topdown events. 3263 * 3264 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 3265 * modify by a NMI. PMU has to be disabled before calling this function. 3266 */ 3267 3268 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end, u64 *val) 3269 { 3270 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3271 struct perf_event *other; 3272 u64 slots, metrics; 3273 bool reset = true; 3274 int idx; 3275 3276 if (!val) { 3277 /* read Fixed counter 3 */ 3278 slots = rdpmc(3 | INTEL_PMC_FIXED_RDPMC_BASE); 3279 if (!slots) 3280 return 0; 3281 3282 /* read PERF_METRICS */ 3283 metrics = rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS); 3284 } else { 3285 slots = val[0]; 3286 metrics = val[1]; 3287 /* 3288 * Don't reset the PERF_METRICS and Fixed counter 3 3289 * for each PEBS record read. Utilize the RDPMC metrics 3290 * clear mode. 3291 */ 3292 reset = false; 3293 } 3294 3295 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 3296 if (!is_topdown_idx(idx)) 3297 continue; 3298 other = cpuc->events[idx]; 3299 __icl_update_topdown_event(other, slots, metrics, 3300 event ? event->hw.saved_slots : 0, 3301 event ? event->hw.saved_metric : 0); 3302 } 3303 3304 /* 3305 * Check and update this event, which may have been cleared 3306 * in active_mask e.g. x86_pmu_stop() 3307 */ 3308 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 3309 __icl_update_topdown_event(event, slots, metrics, 3310 event->hw.saved_slots, 3311 event->hw.saved_metric); 3312 3313 /* 3314 * In x86_pmu_stop(), the event is cleared in active_mask first, 3315 * then drain the delta, which indicates context switch for 3316 * counting. 3317 * Save metric and slots for context switch. 3318 * Don't need to reset the PERF_METRICS and Fixed counter 3. 3319 * Because the values will be restored in next schedule in. 3320 */ 3321 update_saved_topdown_regs(event, slots, metrics, metric_end); 3322 reset = false; 3323 } 3324 3325 if (reset) { 3326 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 3327 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0); 3328 wrmsrq(MSR_PERF_METRICS, 0); 3329 if (event) 3330 update_saved_topdown_regs(event, 0, 0, metric_end); 3331 } 3332 3333 return slots; 3334 } 3335 3336 static u64 icl_update_topdown_event(struct perf_event *event, u64 *val) 3337 { 3338 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 3339 x86_pmu.num_topdown_events - 1, 3340 val); 3341 } 3342 3343 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update); 3344 3345 static void intel_pmu_read_event(struct perf_event *event) 3346 { 3347 if (event->hw.flags & (PERF_X86_EVENT_AUTO_RELOAD | PERF_X86_EVENT_TOPDOWN) || 3348 is_pebs_counter_event_group(event)) { 3349 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3350 int pmu_enabled; 3351 3352 /* Only need to call update_topdown_event() once for group read. */ 3353 if (is_metric_event(event) && (cpuc->txn_flags & PERF_PMU_TXN_READ)) 3354 return; 3355 3356 pmu_enabled = __intel_pmu_quiesce(); 3357 /* 3358 * If the PEBS counters snapshotting is enabled, 3359 * the topdown event is available in PEBS records. 3360 */ 3361 if (is_topdown_count(event) && !is_pebs_counter_event_group(event)) 3362 static_call(intel_pmu_update_topdown_event)(event, NULL); 3363 else 3364 intel_pmu_drain_pebs_buffer(); 3365 __intel_pmu_resume(pmu_enabled); 3366 3367 return; 3368 } 3369 3370 x86_perf_event_update(event); 3371 } 3372 3373 static void intel_pmu_enable_fixed(struct perf_event *event) 3374 { 3375 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3376 struct hw_perf_event *hwc = &event->hw; 3377 int idx = hwc->idx; 3378 u64 bits = 0; 3379 3380 if (is_topdown_idx(idx)) { 3381 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3382 /* 3383 * When there are other active TopDown events, 3384 * don't enable the fixed counter 3 again. 3385 */ 3386 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 3387 return; 3388 3389 idx = INTEL_PMC_IDX_FIXED_SLOTS; 3390 3391 if (event->attr.config1 & INTEL_TD_CFG_METRIC_CLEAR) 3392 bits |= INTEL_FIXED_3_METRICS_CLEAR; 3393 } 3394 3395 intel_set_masks(event, idx); 3396 3397 /* 3398 * Enable IRQ generation (0x8), if not PEBS or self-reloaded 3399 * ACR event, and enable ring-3 counting (0x2) and ring-0 3400 * counting (0x1) if requested: 3401 */ 3402 if (!event->attr.precise_ip && !is_acr_self_reload_event(event)) 3403 bits |= INTEL_FIXED_0_ENABLE_PMI; 3404 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 3405 bits |= INTEL_FIXED_0_USER; 3406 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 3407 bits |= INTEL_FIXED_0_KERNEL; 3408 if (hwc->config & ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE) 3409 bits |= INTEL_FIXED_0_RDPMC_USER_DISABLE; 3410 3411 /* 3412 * ANY bit is supported in v3 and up 3413 */ 3414 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 3415 bits |= INTEL_FIXED_0_ANYTHREAD; 3416 3417 idx -= INTEL_PMC_IDX_FIXED; 3418 bits = intel_fixed_bits_by_idx(idx, bits); 3419 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) 3420 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 3421 3422 cpuc->fixed_ctrl_val &= ~intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK); 3423 cpuc->fixed_ctrl_val |= bits; 3424 } 3425 3426 static void intel_pmu_config_acr(int idx, u64 mask, u32 reload) 3427 { 3428 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3429 int msr_b, msr_c; 3430 int msr_offset; 3431 3432 if (!mask && !cpuc->acr_cfg_b[idx]) 3433 return; 3434 3435 if (idx < INTEL_PMC_IDX_FIXED) { 3436 msr_b = MSR_IA32_PMC_V6_GP0_CFG_B; 3437 msr_c = MSR_IA32_PMC_V6_GP0_CFG_C; 3438 msr_offset = x86_pmu.addr_offset(idx, false); 3439 } else { 3440 msr_b = MSR_IA32_PMC_V6_FX0_CFG_B; 3441 msr_c = MSR_IA32_PMC_V6_FX0_CFG_C; 3442 msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false); 3443 } 3444 3445 if (cpuc->acr_cfg_b[idx] != mask) { 3446 wrmsrq(msr_b + msr_offset, mask); 3447 cpuc->acr_cfg_b[idx] = mask; 3448 } 3449 /* Only update CFG_C reload when ACR is actively enabled (mask != 0) */ 3450 if (mask && ((cpuc->cfg_c_val[idx] & ARCH_PEBS_RELOAD) != reload)) { 3451 wrmsrq(msr_c + msr_offset, reload); 3452 cpuc->cfg_c_val[idx] = reload; 3453 } 3454 } 3455 3456 static void intel_pmu_enable_acr(struct perf_event *event) 3457 { 3458 struct hw_perf_event *hwc = &event->hw; 3459 3460 if (!is_acr_event_group(event) || !event->attr.config2) { 3461 /* 3462 * The disable doesn't clear the ACR CFG register. 3463 * Check and clear the ACR CFG register. 3464 */ 3465 intel_pmu_config_acr(hwc->idx, 0, 0); 3466 return; 3467 } 3468 3469 intel_pmu_config_acr(hwc->idx, hwc->config1, -hwc->sample_period); 3470 } 3471 3472 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 3473 3474 static void intel_pmu_enable_event_ext(struct perf_event *event) 3475 { 3476 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3477 struct hw_perf_event *hwc = &event->hw; 3478 u64 ext = 0; 3479 3480 if (is_acr_event_group(event)) 3481 ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD; 3482 3483 if (event->attr.precise_ip) { 3484 u64 pebs_data_cfg = intel_get_arch_pebs_data_config(event); 3485 struct arch_pebs_cap cap = hybrid(cpuc->pmu, arch_pebs_cap); 3486 union arch_pebs_index old, new; 3487 3488 ext |= ARCH_PEBS_EN; 3489 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) 3490 ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD; 3491 3492 if (pebs_data_cfg && cap.caps) { 3493 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO) 3494 ext |= ARCH_PEBS_AUX & cap.caps; 3495 3496 if (pebs_data_cfg & PEBS_DATACFG_GP) 3497 ext |= ARCH_PEBS_GPR & cap.caps; 3498 3499 if (pebs_data_cfg & PEBS_DATACFG_XMMS) 3500 ext |= ARCH_PEBS_VECR_XMM & cap.caps; 3501 3502 if (pebs_data_cfg & PEBS_DATACFG_LBRS) 3503 ext |= ARCH_PEBS_LBR & cap.caps; 3504 3505 if (pebs_data_cfg & 3506 (PEBS_DATACFG_CNTR_MASK << PEBS_DATACFG_CNTR_SHIFT)) 3507 ext |= ARCH_PEBS_CNTR_GP & cap.caps; 3508 3509 if (pebs_data_cfg & 3510 (PEBS_DATACFG_FIX_MASK << PEBS_DATACFG_FIX_SHIFT)) 3511 ext |= ARCH_PEBS_CNTR_FIXED & cap.caps; 3512 3513 if (pebs_data_cfg & PEBS_DATACFG_METRICS) 3514 ext |= ARCH_PEBS_CNTR_METRICS & cap.caps; 3515 } 3516 3517 if (cpuc->n_pebs == cpuc->n_large_pebs) 3518 new.thresh = ARCH_PEBS_THRESH_MULTI; 3519 else 3520 new.thresh = ARCH_PEBS_THRESH_SINGLE; 3521 3522 rdmsrq(MSR_IA32_PEBS_INDEX, old.whole); 3523 if (new.thresh != old.thresh || !old.en) { 3524 if (old.thresh == ARCH_PEBS_THRESH_MULTI && old.wr > 0) { 3525 /* 3526 * Large PEBS was enabled. 3527 * Drain PEBS buffer before applying the single PEBS. 3528 */ 3529 intel_pmu_drain_pebs_buffer(); 3530 } else { 3531 new.wr = 0; 3532 new.full = 0; 3533 new.en = 1; 3534 wrmsrq(MSR_IA32_PEBS_INDEX, new.whole); 3535 } 3536 } 3537 } 3538 3539 if (is_pebs_counter_event_group(event)) 3540 ext |= ARCH_PEBS_CNTR_ALLOW; 3541 3542 if (cpuc->cfg_c_val[hwc->idx] != ext) 3543 __intel_pmu_update_event_ext(hwc->idx, ext); 3544 } 3545 3546 static void intel_pmu_update_rdpmc_user_disable(struct perf_event *event) 3547 { 3548 if (!x86_pmu_has_rdpmc_user_disable(event->pmu)) 3549 return; 3550 3551 /* 3552 * Counter scope's user-space rdpmc is disabled by default 3553 * except two cases. 3554 * a. rdpmc = 2 (user space rdpmc enabled unconditionally) 3555 * b. rdpmc = 1 and the event is not a system-wide event. 3556 * The count of non-system-wide events would be cleared when 3557 * context switches, so no count data is leaked. 3558 */ 3559 if (x86_pmu.attr_rdpmc == X86_USER_RDPMC_ALWAYS_ENABLE || 3560 (x86_pmu.attr_rdpmc == X86_USER_RDPMC_CONDITIONAL_ENABLE && 3561 (event->attach_state & PERF_ATTACH_TASK))) 3562 event->hw.config &= ~ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE; 3563 else 3564 event->hw.config |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE; 3565 } 3566 3567 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_event_ext, intel_pmu_enable_event_ext); 3568 3569 static void intel_pmu_enable_event(struct perf_event *event) 3570 { 3571 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE; 3572 struct hw_perf_event *hwc = &event->hw; 3573 int idx = hwc->idx; 3574 3575 if (unlikely(event->attr.precise_ip)) 3576 static_call(x86_pmu_pebs_enable)(event); 3577 3578 switch (idx) { 3579 case 0 ... INTEL_PMC_IDX_FIXED - 1: 3580 if (branch_sample_counters(event)) 3581 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR; 3582 intel_set_masks(event, idx); 3583 static_call_cond(intel_pmu_enable_acr_event)(event); 3584 static_call_cond(intel_pmu_enable_event_ext)(event); 3585 /* 3586 * For self-reloaded ACR event, don't enable PMI since 3587 * HW won't set overflow bit in GLOBAL_STATUS. Otherwise, 3588 * the PMI would be recognized as a suspicious NMI. 3589 */ 3590 if (is_acr_self_reload_event(event)) 3591 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; 3592 else if (!event->attr.precise_ip) 3593 hwc->config |= ARCH_PERFMON_EVENTSEL_INT; 3594 __x86_pmu_enable_event(hwc, enable_mask); 3595 break; 3596 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 3597 static_call_cond(intel_pmu_enable_acr_event)(event); 3598 static_call_cond(intel_pmu_enable_event_ext)(event); 3599 fallthrough; 3600 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 3601 intel_pmu_enable_fixed(event); 3602 break; 3603 case INTEL_PMC_IDX_FIXED_BTS: 3604 if (!__this_cpu_read(cpu_hw_events.enabled)) 3605 return; 3606 intel_pmu_enable_bts(hwc->config); 3607 break; 3608 case INTEL_PMC_IDX_FIXED_VLBR: 3609 intel_set_masks(event, idx); 3610 break; 3611 default: 3612 pr_warn("Failed to enable the event with invalid index %d\n", 3613 idx); 3614 } 3615 } 3616 3617 static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc) 3618 { 3619 struct perf_event *event, *leader; 3620 int i, j, k, bit, idx; 3621 3622 /* 3623 * FIXME: ACR mask parsing relies on cpuc->event_list[] (active events only). 3624 * Disabling an ACR event causes bit-shifting errors in the acr_mask of 3625 * remaining group members. As ACR sampling requires all events to be active, 3626 * this limitation is acceptable for now. Revisit if independent event toggling 3627 * is required. 3628 */ 3629 for (i = 0; i < cpuc->n_events; i++) { 3630 leader = cpuc->event_list[i]; 3631 if (!is_acr_event_group(leader)) 3632 continue; 3633 3634 /* Find the last event of the ACR group. */ 3635 for (j = i; j < cpuc->n_events; j++) { 3636 event = cpuc->event_list[j]; 3637 if (event->group_leader != leader->group_leader) 3638 break; 3639 } 3640 3641 /* 3642 * Translate the user-space ACR mask (attr.config2) into the physical 3643 * counter bitmask (hw.config1) for each ACR event in the group. 3644 * NOTE: ACR event contiguity is guaranteed by intel_pmu_hw_config(). 3645 */ 3646 for (k = i; k < j; k++) { 3647 event = cpuc->event_list[k]; 3648 event->hw.config1 = 0; 3649 for_each_set_bit(bit, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) { 3650 idx = i + bit; 3651 /* Event index of ACR group must locate in [i, j). */ 3652 if (idx >= j || !is_acr_event_group(cpuc->event_list[idx])) 3653 continue; 3654 __set_bit(cpuc->assign[idx], (unsigned long *)&event->hw.config1); 3655 } 3656 } 3657 i = j - 1; 3658 } 3659 } 3660 3661 void intel_pmu_late_setup(void) 3662 { 3663 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3664 3665 if (!cpuc->n_late_setup) 3666 return; 3667 3668 intel_pmu_pebs_late_setup(cpuc); 3669 intel_pmu_acr_late_setup(cpuc); 3670 } 3671 3672 static void intel_pmu_add_event(struct perf_event *event) 3673 { 3674 if (event->attr.precise_ip) 3675 intel_pmu_pebs_add(event); 3676 if (intel_pmu_needs_branch_stack(event)) 3677 intel_pmu_lbr_add(event); 3678 if (is_pebs_counter_event_group(event) || 3679 is_acr_event_group(event)) 3680 this_cpu_ptr(&cpu_hw_events)->n_late_setup++; 3681 } 3682 3683 /* 3684 * Save and restart an expired event. Called by NMI contexts, 3685 * so it has to be careful about preempting normal event ops: 3686 */ 3687 int intel_pmu_save_and_restart(struct perf_event *event) 3688 { 3689 static_call(x86_pmu_update)(event); 3690 /* 3691 * For a checkpointed counter always reset back to 0. This 3692 * avoids a situation where the counter overflows, aborts the 3693 * transaction and is then set back to shortly before the 3694 * overflow, and overflows and aborts again. 3695 */ 3696 if (unlikely(event_is_checkpointed(event))) { 3697 /* No race with NMIs because the counter should not be armed */ 3698 wrmsrq(event->hw.event_base, 0); 3699 local64_set(&event->hw.prev_count, 0); 3700 } 3701 return static_call(x86_pmu_set_period)(event); 3702 } 3703 3704 static int intel_pmu_set_period(struct perf_event *event) 3705 { 3706 if (unlikely(is_topdown_count(event))) 3707 return static_call(intel_pmu_set_topdown_event_period)(event); 3708 3709 return x86_perf_event_set_period(event); 3710 } 3711 3712 static u64 intel_pmu_update(struct perf_event *event) 3713 { 3714 if (unlikely(is_topdown_count(event))) 3715 return static_call(intel_pmu_update_topdown_event)(event, NULL); 3716 3717 return x86_perf_event_update(event); 3718 } 3719 3720 static void intel_pmu_reset(void) 3721 { 3722 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 3723 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3724 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); 3725 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); 3726 unsigned long flags; 3727 int idx; 3728 3729 if (!*(u64 *)cntr_mask) 3730 return; 3731 3732 local_irq_save(flags); 3733 3734 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 3735 3736 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { 3737 wrmsrq_safe(x86_pmu_config_addr(idx), 0ull); 3738 wrmsrq_safe(x86_pmu_event_addr(idx), 0ull); 3739 } 3740 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) { 3741 wrmsrq_safe(x86_pmu_fixed_ctr_addr(idx), 0ull); 3742 } 3743 3744 if (ds) 3745 ds->bts_index = ds->bts_buffer_base; 3746 3747 /* Ack all overflows and disable fixed counters */ 3748 if (x86_pmu.version >= 2) { 3749 intel_pmu_ack_status(intel_pmu_get_status()); 3750 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 3751 } 3752 3753 /* Reset LBRs and LBR freezing */ 3754 if (x86_pmu.lbr_nr) { 3755 update_debugctlmsr(get_debugctlmsr() & 3756 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 3757 } 3758 3759 local_irq_restore(flags); 3760 } 3761 3762 /* 3763 * We may be running with guest PEBS events created by KVM, and the 3764 * PEBS records are logged into the guest's DS and invisible to host. 3765 * 3766 * In the case of guest PEBS overflow, we only trigger a fake event 3767 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM. 3768 * The guest will then vm-entry and check the guest DS area to read 3769 * the guest PEBS records. 3770 * 3771 * The contents and other behavior of the guest event do not matter. 3772 */ 3773 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs, 3774 struct perf_sample_data *data) 3775 { 3776 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3777 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask; 3778 struct perf_event *event = NULL; 3779 int bit; 3780 3781 if (!unlikely(perf_guest_state())) 3782 return; 3783 3784 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || 3785 !guest_pebs_idxs) 3786 return; 3787 3788 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) { 3789 event = cpuc->events[bit]; 3790 if (!event->attr.precise_ip) 3791 continue; 3792 3793 perf_sample_data_init(data, 0, event->hw.last_period); 3794 perf_event_overflow(event, data, regs); 3795 3796 /* Inject one fake event is enough. */ 3797 break; 3798 } 3799 } 3800 3801 static int handle_pmi_common(struct pt_regs *regs, u64 status) 3802 { 3803 struct perf_sample_data data; 3804 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3805 int bit; 3806 int handled = 0; 3807 3808 inc_perf_irq_stat(); 3809 3810 /* 3811 * Ignore a range of extra bits in status that do not indicate 3812 * overflow by themselves. 3813 */ 3814 status &= ~(GLOBAL_STATUS_COND_CHG | 3815 GLOBAL_STATUS_ASIF | 3816 GLOBAL_STATUS_LBRS_FROZEN); 3817 if (!status) 3818 return 0; 3819 /* 3820 * In case multiple PEBS events are sampled at the same time, 3821 * it is possible to have GLOBAL_STATUS bit 62 set indicating 3822 * PEBS buffer overflow and also seeing at most 3 PEBS counters 3823 * having their bits set in the status register. This is a sign 3824 * that there was at least one PEBS record pending at the time 3825 * of the PMU interrupt. PEBS counters must only be processed 3826 * via the drain_pebs() calls and not via the regular sample 3827 * processing loop coming after that the function, otherwise 3828 * phony regular samples may be generated in the sampling buffer 3829 * not marked with the EXACT tag. Another possibility is to have 3830 * one PEBS event and at least one non-PEBS event which overflows 3831 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 3832 * not be set, yet the overflow status bit for the PEBS counter will 3833 * be on Skylake. 3834 * 3835 * To avoid this problem, we systematically ignore the PEBS-enabled 3836 * counters from the GLOBAL_STATUS mask and we always process PEBS 3837 * events via drain_pebs(). 3838 */ 3839 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable); 3840 3841 /* 3842 * PEBS overflow sets bit 62 in the global status register 3843 */ 3844 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 3845 u64 pebs_enabled = cpuc->pebs_enabled; 3846 3847 handled++; 3848 x86_pmu_handle_guest_pebs(regs, &data); 3849 static_call(x86_pmu_drain_pebs)(regs, &data); 3850 3851 /* 3852 * PMI throttle may be triggered, which stops the PEBS event. 3853 * Although cpuc->pebs_enabled is updated accordingly, the 3854 * MSR_IA32_PEBS_ENABLE is not updated. Because the 3855 * cpuc->enabled has been forced to 0 in PMI. 3856 * Update the MSR if pebs_enabled is changed. 3857 */ 3858 if (pebs_enabled != cpuc->pebs_enabled) 3859 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 3860 3861 /* 3862 * Above PEBS handler (PEBS counters snapshotting) has updated fixed 3863 * counter 3 and perf metrics counts if they are in counter group, 3864 * unnecessary to update again. 3865 */ 3866 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] && 3867 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS])) 3868 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT; 3869 } 3870 3871 /* 3872 * Arch PEBS sets bit 54 in the global status register 3873 */ 3874 if (__test_and_clear_bit(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT, 3875 (unsigned long *)&status)) { 3876 handled++; 3877 static_call(x86_pmu_drain_pebs)(regs, &data); 3878 3879 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] && 3880 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS])) 3881 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT; 3882 } 3883 3884 /* 3885 * Intel PT 3886 */ 3887 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 3888 handled++; 3889 if (!perf_guest_handle_intel_pt_intr()) 3890 intel_pt_interrupt(); 3891 } 3892 3893 /* 3894 * Intel Perf metrics 3895 */ 3896 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 3897 handled++; 3898 static_call(intel_pmu_update_topdown_event)(NULL, NULL); 3899 } 3900 3901 status &= hybrid(cpuc->pmu, intel_ctrl); 3902 3903 /* 3904 * Checkpointed counters can lead to 'spurious' PMIs because the 3905 * rollback caused by the PMI will have cleared the overflow status 3906 * bit. Therefore always force probe these counters. 3907 */ 3908 status |= cpuc->intel_cp_status; 3909 3910 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 3911 struct perf_event *event = cpuc->events[bit]; 3912 u64 last_period; 3913 3914 handled++; 3915 3916 if (!test_bit(bit, cpuc->active_mask)) 3917 continue; 3918 /* Event may have already been cleared: */ 3919 if (!event) 3920 continue; 3921 3922 /* 3923 * There may be unprocessed PEBS records in the PEBS buffer, 3924 * which still stores the previous values. 3925 * Process those records first before handling the latest value. 3926 * For example, 3927 * A is a regular counter 3928 * B is a PEBS event which reads A 3929 * C is a PEBS event 3930 * 3931 * The following can happen: 3932 * B-assist A=1 3933 * C A=2 3934 * B-assist A=3 3935 * A-overflow-PMI A=4 3936 * C-assist-PMI (PEBS buffer) A=5 3937 * 3938 * The PEBS buffer has to be drained before handling the A-PMI 3939 */ 3940 if (is_pebs_counter_event_group(event)) 3941 static_call(x86_pmu_drain_pebs)(regs, &data); 3942 3943 last_period = event->hw.last_period; 3944 3945 if (!intel_pmu_save_and_restart(event)) 3946 continue; 3947 3948 perf_sample_data_init(&data, 0, last_period); 3949 3950 if (has_branch_stack(event)) 3951 intel_pmu_lbr_save_brstack(&data, cpuc, event); 3952 3953 perf_event_overflow(event, &data, regs); 3954 } 3955 3956 return handled; 3957 } 3958 3959 /* 3960 * This handler is triggered by the local APIC, so the APIC IRQ handling 3961 * rules apply: 3962 */ 3963 static int intel_pmu_handle_irq(struct pt_regs *regs) 3964 { 3965 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3966 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 3967 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 3968 int loops; 3969 u64 status; 3970 int handled; 3971 int pmu_enabled; 3972 3973 /* 3974 * Save the PMU state. 3975 * It needs to be restored when leaving the handler. 3976 */ 3977 pmu_enabled = cpuc->enabled; 3978 /* 3979 * In general, the early ACK is only applied for old platforms. 3980 * For the big core starts from Haswell, the late ACK should be 3981 * applied. 3982 * For the small core after Tremont, we have to do the ACK right 3983 * before re-enabling counters, which is in the middle of the 3984 * NMI handler. 3985 */ 3986 if (!late_ack && !mid_ack) 3987 apic_write(APIC_LVTPC, APIC_DM_NMI); 3988 intel_bts_disable_local(); 3989 cpuc->enabled = 0; 3990 __intel_pmu_disable_all(true); 3991 handled = intel_pmu_drain_bts_buffer(); 3992 handled += intel_bts_interrupt(); 3993 status = intel_pmu_get_status(); 3994 if (!status) 3995 goto done; 3996 3997 loops = 0; 3998 again: 3999 intel_pmu_lbr_read(); 4000 intel_pmu_ack_status(status); 4001 if (++loops > 100) { 4002 static bool warned; 4003 4004 if (!warned) { 4005 WARN(1, "perfevents: irq loop stuck!\n"); 4006 perf_event_print_debug(); 4007 warned = true; 4008 } 4009 intel_pmu_reset(); 4010 goto done; 4011 } 4012 4013 handled += handle_pmi_common(regs, status); 4014 4015 /* 4016 * Repeat if there is more work to be done: 4017 */ 4018 status = intel_pmu_get_status(); 4019 if (status) 4020 goto again; 4021 4022 done: 4023 if (mid_ack) 4024 apic_write(APIC_LVTPC, APIC_DM_NMI); 4025 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 4026 cpuc->enabled = pmu_enabled; 4027 if (pmu_enabled) 4028 __intel_pmu_enable_all(0, true); 4029 intel_bts_enable_local(); 4030 4031 /* 4032 * Only unmask the NMI after the overflow counters 4033 * have been reset. This avoids spurious NMIs on 4034 * Haswell CPUs. 4035 */ 4036 if (late_ack) 4037 apic_write(APIC_LVTPC, APIC_DM_NMI); 4038 return handled; 4039 } 4040 4041 static struct event_constraint * 4042 intel_bts_constraints(struct perf_event *event) 4043 { 4044 if (unlikely(intel_pmu_has_bts(event))) 4045 return &bts_constraint; 4046 4047 return NULL; 4048 } 4049 4050 /* 4051 * Note: matches a fake event, like Fixed2. 4052 */ 4053 static struct event_constraint * 4054 intel_vlbr_constraints(struct perf_event *event) 4055 { 4056 struct event_constraint *c = &vlbr_constraint; 4057 4058 if (unlikely(constraint_match(c, event->hw.config))) { 4059 event->hw.flags |= c->flags; 4060 return c; 4061 } 4062 4063 return NULL; 4064 } 4065 4066 static int intel_alt_er(struct cpu_hw_events *cpuc, 4067 int idx, u64 config) 4068 { 4069 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 4070 int alt_idx = idx; 4071 4072 switch (idx) { 4073 case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1: 4074 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 4075 return idx; 4076 if (++alt_idx > EXTRA_REG_RSP_1) 4077 alt_idx = EXTRA_REG_RSP_0; 4078 if (config & ~extra_regs[alt_idx].valid_mask) 4079 return idx; 4080 break; 4081 4082 case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3: 4083 if (!(x86_pmu.flags & PMU_FL_HAS_OMR)) 4084 return idx; 4085 if (++alt_idx > EXTRA_REG_OMR_3) 4086 alt_idx = EXTRA_REG_OMR_0; 4087 /* 4088 * Subtracting EXTRA_REG_OMR_0 ensures to get correct 4089 * OMR extra_reg entries which start from 0. 4090 */ 4091 if (config & ~extra_regs[alt_idx - EXTRA_REG_OMR_0].valid_mask) 4092 return idx; 4093 break; 4094 4095 default: 4096 break; 4097 } 4098 4099 return alt_idx; 4100 } 4101 4102 static void intel_fixup_er(struct perf_event *event, int idx) 4103 { 4104 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 4105 int er_idx; 4106 4107 event->hw.extra_reg.idx = idx; 4108 switch (idx) { 4109 case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1: 4110 er_idx = idx - EXTRA_REG_RSP_0; 4111 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 4112 event->hw.config |= extra_regs[er_idx].event; 4113 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0 + er_idx; 4114 break; 4115 4116 case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3: 4117 er_idx = idx - EXTRA_REG_OMR_0; 4118 event->hw.config &= ~ARCH_PERFMON_EVENTSEL_UMASK; 4119 event->hw.config |= 1ULL << (8 + er_idx); 4120 event->hw.extra_reg.reg = MSR_OMR_0 + er_idx; 4121 break; 4122 4123 default: 4124 pr_warn("The extra reg idx %d is not supported.\n", idx); 4125 } 4126 } 4127 4128 /* 4129 * manage allocation of shared extra msr for certain events 4130 * 4131 * sharing can be: 4132 * per-cpu: to be shared between the various events on a single PMU 4133 * per-core: per-cpu + shared by HT threads 4134 */ 4135 static struct event_constraint * 4136 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 4137 struct perf_event *event, 4138 struct hw_perf_event_extra *reg) 4139 { 4140 struct event_constraint *c = &emptyconstraint; 4141 struct er_account *era; 4142 unsigned long flags; 4143 int idx = reg->idx; 4144 4145 /* 4146 * reg->alloc can be set due to existing state, so for fake cpuc we 4147 * need to ignore this, otherwise we might fail to allocate proper fake 4148 * state for this extra reg constraint. Also see the comment below. 4149 */ 4150 if (reg->alloc && !cpuc->is_fake) 4151 return NULL; /* call x86_get_event_constraint() */ 4152 4153 again: 4154 era = &cpuc->shared_regs->regs[idx]; 4155 /* 4156 * we use spin_lock_irqsave() to avoid lockdep issues when 4157 * passing a fake cpuc 4158 */ 4159 raw_spin_lock_irqsave(&era->lock, flags); 4160 4161 if (!atomic_read(&era->ref) || era->config == reg->config) { 4162 4163 /* 4164 * If its a fake cpuc -- as per validate_{group,event}() we 4165 * shouldn't touch event state and we can avoid doing so 4166 * since both will only call get_event_constraints() once 4167 * on each event, this avoids the need for reg->alloc. 4168 * 4169 * Not doing the ER fixup will only result in era->reg being 4170 * wrong, but since we won't actually try and program hardware 4171 * this isn't a problem either. 4172 */ 4173 if (!cpuc->is_fake) { 4174 if (idx != reg->idx) 4175 intel_fixup_er(event, idx); 4176 4177 /* 4178 * x86_schedule_events() can call get_event_constraints() 4179 * multiple times on events in the case of incremental 4180 * scheduling(). reg->alloc ensures we only do the ER 4181 * allocation once. 4182 */ 4183 reg->alloc = 1; 4184 } 4185 4186 /* lock in msr value */ 4187 era->config = reg->config; 4188 era->reg = reg->reg; 4189 4190 /* one more user */ 4191 atomic_inc(&era->ref); 4192 4193 /* 4194 * need to call x86_get_event_constraint() 4195 * to check if associated event has constraints 4196 */ 4197 c = NULL; 4198 } else { 4199 idx = intel_alt_er(cpuc, idx, reg->config); 4200 if (idx != reg->idx) { 4201 raw_spin_unlock_irqrestore(&era->lock, flags); 4202 goto again; 4203 } 4204 } 4205 raw_spin_unlock_irqrestore(&era->lock, flags); 4206 4207 return c; 4208 } 4209 4210 static void 4211 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 4212 struct hw_perf_event_extra *reg) 4213 { 4214 struct er_account *era; 4215 4216 /* 4217 * Only put constraint if extra reg was actually allocated. Also takes 4218 * care of event which do not use an extra shared reg. 4219 * 4220 * Also, if this is a fake cpuc we shouldn't touch any event state 4221 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 4222 * either since it'll be thrown out. 4223 */ 4224 if (!reg->alloc || cpuc->is_fake) 4225 return; 4226 4227 era = &cpuc->shared_regs->regs[reg->idx]; 4228 4229 /* one fewer user */ 4230 atomic_dec(&era->ref); 4231 4232 /* allocate again next time */ 4233 reg->alloc = 0; 4234 } 4235 4236 static struct event_constraint * 4237 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 4238 struct perf_event *event) 4239 { 4240 struct event_constraint *c = NULL, *d; 4241 struct hw_perf_event_extra *xreg, *breg; 4242 4243 xreg = &event->hw.extra_reg; 4244 if (xreg->idx != EXTRA_REG_NONE) { 4245 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 4246 if (c == &emptyconstraint) 4247 return c; 4248 } 4249 breg = &event->hw.branch_reg; 4250 if (breg->idx != EXTRA_REG_NONE) { 4251 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 4252 if (d == &emptyconstraint) { 4253 __intel_shared_reg_put_constraints(cpuc, xreg); 4254 c = d; 4255 } 4256 } 4257 return c; 4258 } 4259 4260 struct event_constraint * 4261 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4262 struct perf_event *event) 4263 { 4264 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 4265 struct event_constraint *c; 4266 4267 if (event_constraints) { 4268 for_each_event_constraint(c, event_constraints) { 4269 if (constraint_match(c, event->hw.config)) { 4270 event->hw.flags |= c->flags; 4271 return c; 4272 } 4273 } 4274 } 4275 4276 return &hybrid_var(cpuc->pmu, unconstrained); 4277 } 4278 4279 static struct event_constraint * 4280 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4281 struct perf_event *event) 4282 { 4283 struct event_constraint *c; 4284 4285 c = intel_vlbr_constraints(event); 4286 if (c) 4287 return c; 4288 4289 c = intel_bts_constraints(event); 4290 if (c) 4291 return c; 4292 4293 c = intel_shared_regs_constraints(cpuc, event); 4294 if (c) 4295 return c; 4296 4297 c = intel_pebs_constraints(event); 4298 if (c) 4299 return c; 4300 4301 return x86_get_event_constraints(cpuc, idx, event); 4302 } 4303 4304 static void 4305 intel_start_scheduling(struct cpu_hw_events *cpuc) 4306 { 4307 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 4308 struct intel_excl_states *xl; 4309 int tid = cpuc->excl_thread_id; 4310 4311 /* 4312 * nothing needed if in group validation mode 4313 */ 4314 if (cpuc->is_fake || !is_ht_workaround_enabled()) 4315 return; 4316 4317 /* 4318 * no exclusion needed 4319 */ 4320 if (WARN_ON_ONCE(!excl_cntrs)) 4321 return; 4322 4323 xl = &excl_cntrs->states[tid]; 4324 4325 xl->sched_started = true; 4326 /* 4327 * lock shared state until we are done scheduling 4328 * in stop_event_scheduling() 4329 * makes scheduling appear as a transaction 4330 */ 4331 raw_spin_lock(&excl_cntrs->lock); 4332 } 4333 4334 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 4335 { 4336 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 4337 struct event_constraint *c = cpuc->event_constraint[idx]; 4338 struct intel_excl_states *xl; 4339 int tid = cpuc->excl_thread_id; 4340 4341 if (cpuc->is_fake || !is_ht_workaround_enabled()) 4342 return; 4343 4344 if (WARN_ON_ONCE(!excl_cntrs)) 4345 return; 4346 4347 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 4348 return; 4349 4350 xl = &excl_cntrs->states[tid]; 4351 4352 lockdep_assert_held(&excl_cntrs->lock); 4353 4354 if (c->flags & PERF_X86_EVENT_EXCL) 4355 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 4356 else 4357 xl->state[cntr] = INTEL_EXCL_SHARED; 4358 } 4359 4360 static void 4361 intel_stop_scheduling(struct cpu_hw_events *cpuc) 4362 { 4363 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 4364 struct intel_excl_states *xl; 4365 int tid = cpuc->excl_thread_id; 4366 4367 /* 4368 * nothing needed if in group validation mode 4369 */ 4370 if (cpuc->is_fake || !is_ht_workaround_enabled()) 4371 return; 4372 /* 4373 * no exclusion needed 4374 */ 4375 if (WARN_ON_ONCE(!excl_cntrs)) 4376 return; 4377 4378 xl = &excl_cntrs->states[tid]; 4379 4380 xl->sched_started = false; 4381 /* 4382 * release shared state lock (acquired in intel_start_scheduling()) 4383 */ 4384 raw_spin_unlock(&excl_cntrs->lock); 4385 } 4386 4387 static struct event_constraint * 4388 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 4389 { 4390 WARN_ON_ONCE(!cpuc->constraint_list); 4391 4392 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 4393 struct event_constraint *cx; 4394 4395 /* 4396 * grab pre-allocated constraint entry 4397 */ 4398 cx = &cpuc->constraint_list[idx]; 4399 4400 /* 4401 * initialize dynamic constraint 4402 * with static constraint 4403 */ 4404 *cx = *c; 4405 4406 /* 4407 * mark constraint as dynamic 4408 */ 4409 cx->flags |= PERF_X86_EVENT_DYNAMIC; 4410 c = cx; 4411 } 4412 4413 return c; 4414 } 4415 4416 static struct event_constraint * 4417 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 4418 int idx, struct event_constraint *c) 4419 { 4420 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 4421 struct intel_excl_states *xlo; 4422 int tid = cpuc->excl_thread_id; 4423 int is_excl, i, w; 4424 4425 /* 4426 * validating a group does not require 4427 * enforcing cross-thread exclusion 4428 */ 4429 if (cpuc->is_fake || !is_ht_workaround_enabled()) 4430 return c; 4431 4432 /* 4433 * no exclusion needed 4434 */ 4435 if (WARN_ON_ONCE(!excl_cntrs)) 4436 return c; 4437 4438 /* 4439 * because we modify the constraint, we need 4440 * to make a copy. Static constraints come 4441 * from static const tables. 4442 * 4443 * only needed when constraint has not yet 4444 * been cloned (marked dynamic) 4445 */ 4446 c = dyn_constraint(cpuc, c, idx); 4447 4448 /* 4449 * From here on, the constraint is dynamic. 4450 * Either it was just allocated above, or it 4451 * was allocated during a earlier invocation 4452 * of this function 4453 */ 4454 4455 /* 4456 * state of sibling HT 4457 */ 4458 xlo = &excl_cntrs->states[tid ^ 1]; 4459 4460 /* 4461 * event requires exclusive counter access 4462 * across HT threads 4463 */ 4464 is_excl = c->flags & PERF_X86_EVENT_EXCL; 4465 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 4466 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 4467 if (!cpuc->n_excl++) 4468 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 4469 } 4470 4471 /* 4472 * Modify static constraint with current dynamic 4473 * state of thread 4474 * 4475 * EXCLUSIVE: sibling counter measuring exclusive event 4476 * SHARED : sibling counter measuring non-exclusive event 4477 * UNUSED : sibling counter unused 4478 */ 4479 w = c->weight; 4480 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 4481 /* 4482 * exclusive event in sibling counter 4483 * our corresponding counter cannot be used 4484 * regardless of our event 4485 */ 4486 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 4487 __clear_bit(i, c->idxmsk); 4488 w--; 4489 continue; 4490 } 4491 /* 4492 * if measuring an exclusive event, sibling 4493 * measuring non-exclusive, then counter cannot 4494 * be used 4495 */ 4496 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 4497 __clear_bit(i, c->idxmsk); 4498 w--; 4499 continue; 4500 } 4501 } 4502 4503 /* 4504 * if we return an empty mask, then switch 4505 * back to static empty constraint to avoid 4506 * the cost of freeing later on 4507 */ 4508 if (!w) 4509 c = &emptyconstraint; 4510 4511 c->weight = w; 4512 4513 return c; 4514 } 4515 4516 static struct event_constraint * 4517 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4518 struct perf_event *event) 4519 { 4520 struct event_constraint *c1, *c2; 4521 4522 c1 = cpuc->event_constraint[idx]; 4523 4524 /* 4525 * first time only 4526 * - static constraint: no change across incremental scheduling calls 4527 * - dynamic constraint: handled by intel_get_excl_constraints() 4528 */ 4529 c2 = __intel_get_event_constraints(cpuc, idx, event); 4530 if (c1) { 4531 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 4532 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 4533 c1->weight = c2->weight; 4534 c2 = c1; 4535 } 4536 4537 if (cpuc->excl_cntrs) 4538 return intel_get_excl_constraints(cpuc, event, idx, c2); 4539 4540 if (event->hw.dyn_constraint != ~0ULL) { 4541 c2 = dyn_constraint(cpuc, c2, idx); 4542 c2->idxmsk64 &= event->hw.dyn_constraint; 4543 c2->weight = hweight64(c2->idxmsk64); 4544 } 4545 4546 return c2; 4547 } 4548 4549 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 4550 struct perf_event *event) 4551 { 4552 struct hw_perf_event *hwc = &event->hw; 4553 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 4554 int tid = cpuc->excl_thread_id; 4555 struct intel_excl_states *xl; 4556 4557 /* 4558 * nothing needed if in group validation mode 4559 */ 4560 if (cpuc->is_fake) 4561 return; 4562 4563 if (WARN_ON_ONCE(!excl_cntrs)) 4564 return; 4565 4566 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 4567 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 4568 if (!--cpuc->n_excl) 4569 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 4570 } 4571 4572 /* 4573 * If event was actually assigned, then mark the counter state as 4574 * unused now. 4575 */ 4576 if (hwc->idx >= 0) { 4577 xl = &excl_cntrs->states[tid]; 4578 4579 /* 4580 * put_constraint may be called from x86_schedule_events() 4581 * which already has the lock held so here make locking 4582 * conditional. 4583 */ 4584 if (!xl->sched_started) 4585 raw_spin_lock(&excl_cntrs->lock); 4586 4587 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 4588 4589 if (!xl->sched_started) 4590 raw_spin_unlock(&excl_cntrs->lock); 4591 } 4592 } 4593 4594 static void 4595 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 4596 struct perf_event *event) 4597 { 4598 struct hw_perf_event_extra *reg; 4599 4600 reg = &event->hw.extra_reg; 4601 if (reg->idx != EXTRA_REG_NONE) 4602 __intel_shared_reg_put_constraints(cpuc, reg); 4603 4604 reg = &event->hw.branch_reg; 4605 if (reg->idx != EXTRA_REG_NONE) 4606 __intel_shared_reg_put_constraints(cpuc, reg); 4607 } 4608 4609 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 4610 struct perf_event *event) 4611 { 4612 intel_put_shared_regs_event_constraints(cpuc, event); 4613 4614 /* 4615 * is PMU has exclusive counter restrictions, then 4616 * all events are subject to and must call the 4617 * put_excl_constraints() routine 4618 */ 4619 if (cpuc->excl_cntrs) 4620 intel_put_excl_constraints(cpuc, event); 4621 } 4622 4623 static void intel_pebs_aliases_core2(struct perf_event *event) 4624 { 4625 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 4626 /* 4627 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 4628 * (0x003c) so that we can use it with PEBS. 4629 * 4630 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 4631 * PEBS capable. However we can use INST_RETIRED.ANY_P 4632 * (0x00c0), which is a PEBS capable event, to get the same 4633 * count. 4634 * 4635 * INST_RETIRED.ANY_P counts the number of cycles that retires 4636 * CNTMASK instructions. By setting CNTMASK to a value (16) 4637 * larger than the maximum number of instructions that can be 4638 * retired per cycle (4) and then inverting the condition, we 4639 * count all cycles that retire 16 or less instructions, which 4640 * is every cycle. 4641 * 4642 * Thereby we gain a PEBS capable cycle counter. 4643 */ 4644 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 4645 4646 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 4647 event->hw.config = alt_config; 4648 } 4649 } 4650 4651 static void intel_pebs_aliases_snb(struct perf_event *event) 4652 { 4653 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 4654 /* 4655 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 4656 * (0x003c) so that we can use it with PEBS. 4657 * 4658 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 4659 * PEBS capable. However we can use UOPS_RETIRED.ALL 4660 * (0x01c2), which is a PEBS capable event, to get the same 4661 * count. 4662 * 4663 * UOPS_RETIRED.ALL counts the number of cycles that retires 4664 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 4665 * larger than the maximum number of micro-ops that can be 4666 * retired per cycle (4) and then inverting the condition, we 4667 * count all cycles that retire 16 or less micro-ops, which 4668 * is every cycle. 4669 * 4670 * Thereby we gain a PEBS capable cycle counter. 4671 */ 4672 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 4673 4674 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 4675 event->hw.config = alt_config; 4676 } 4677 } 4678 4679 static void intel_pebs_aliases_precdist(struct perf_event *event) 4680 { 4681 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 4682 /* 4683 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 4684 * (0x003c) so that we can use it with PEBS. 4685 * 4686 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 4687 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 4688 * (0x01c0), which is a PEBS capable event, to get the same 4689 * count. 4690 * 4691 * The PREC_DIST event has special support to minimize sample 4692 * shadowing effects. One drawback is that it can be 4693 * only programmed on counter 1, but that seems like an 4694 * acceptable trade off. 4695 */ 4696 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 4697 4698 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 4699 event->hw.config = alt_config; 4700 } 4701 } 4702 4703 static void intel_pebs_aliases_ivb(struct perf_event *event) 4704 { 4705 if (event->attr.precise_ip < 3) 4706 return intel_pebs_aliases_snb(event); 4707 return intel_pebs_aliases_precdist(event); 4708 } 4709 4710 static void intel_pebs_aliases_skl(struct perf_event *event) 4711 { 4712 if (event->attr.precise_ip < 3) 4713 return intel_pebs_aliases_core2(event); 4714 return intel_pebs_aliases_precdist(event); 4715 } 4716 4717 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 4718 { 4719 unsigned long flags = x86_pmu.large_pebs_flags; 4720 4721 if (event->attr.use_clockid) 4722 flags &= ~PERF_SAMPLE_TIME; 4723 if (!event->attr.exclude_kernel) 4724 flags &= ~PERF_SAMPLE_REGS_USER; 4725 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 4726 flags &= ~PERF_SAMPLE_REGS_USER; 4727 if (event->attr.sample_regs_intr & ~PEBS_GP_REGS) 4728 flags &= ~PERF_SAMPLE_REGS_INTR; 4729 return flags; 4730 } 4731 4732 static int intel_pmu_bts_config(struct perf_event *event) 4733 { 4734 struct perf_event_attr *attr = &event->attr; 4735 4736 if (unlikely(intel_pmu_has_bts(event))) { 4737 /* BTS is not supported by this architecture. */ 4738 if (!x86_pmu.bts_active) 4739 return -EOPNOTSUPP; 4740 4741 /* BTS is currently only allowed for user-mode. */ 4742 if (!attr->exclude_kernel) 4743 return -EOPNOTSUPP; 4744 4745 /* BTS is not allowed for precise events. */ 4746 if (attr->precise_ip) 4747 return -EOPNOTSUPP; 4748 4749 /* disallow bts if conflicting events are present */ 4750 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 4751 return -EBUSY; 4752 4753 event->destroy = hw_perf_lbr_event_destroy; 4754 } 4755 4756 return 0; 4757 } 4758 4759 static int core_pmu_hw_config(struct perf_event *event) 4760 { 4761 int ret = x86_pmu_hw_config(event); 4762 4763 if (ret) 4764 return ret; 4765 4766 return intel_pmu_bts_config(event); 4767 } 4768 4769 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 4770 ((x86_pmu.num_topdown_events - 1) << 8)) 4771 4772 static bool is_available_metric_event(struct perf_event *event) 4773 { 4774 return is_metric_event(event) && 4775 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 4776 } 4777 4778 static inline bool is_mem_loads_event(struct perf_event *event) 4779 { 4780 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 4781 } 4782 4783 static inline bool is_mem_loads_aux_event(struct perf_event *event) 4784 { 4785 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 4786 } 4787 4788 static inline bool require_mem_loads_aux_event(struct perf_event *event) 4789 { 4790 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 4791 return false; 4792 4793 if (is_hybrid()) 4794 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big; 4795 4796 return true; 4797 } 4798 4799 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 4800 { 4801 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 4802 4803 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 4804 } 4805 4806 static u64 intel_pmu_freq_start_period(struct perf_event *event) 4807 { 4808 int type = event->attr.type; 4809 u64 config, factor; 4810 s64 start; 4811 4812 /* 4813 * The 127 is the lowest possible recommended SAV (sample after value) 4814 * for a 4000 freq (default freq), according to the event list JSON file. 4815 * Also, assume the workload is idle 50% time. 4816 */ 4817 factor = 64 * 4000; 4818 if (type != PERF_TYPE_HARDWARE && type != PERF_TYPE_HW_CACHE) 4819 goto end; 4820 4821 /* 4822 * The estimation of the start period in the freq mode is 4823 * based on the below assumption. 4824 * 4825 * For a cycles or an instructions event, 1GHZ of the 4826 * underlying platform, 1 IPC. The workload is idle 50% time. 4827 * The start period = 1,000,000,000 * 1 / freq / 2. 4828 * = 500,000,000 / freq 4829 * 4830 * Usually, the branch-related events occur less than the 4831 * instructions event. According to the Intel event list JSON 4832 * file, the SAV (sample after value) of a branch-related event 4833 * is usually 1/4 of an instruction event. 4834 * The start period of branch-related events = 125,000,000 / freq. 4835 * 4836 * The cache-related events occurs even less. The SAV is usually 4837 * 1/20 of an instruction event. 4838 * The start period of cache-related events = 25,000,000 / freq. 4839 */ 4840 config = event->attr.config & PERF_HW_EVENT_MASK; 4841 if (type == PERF_TYPE_HARDWARE) { 4842 switch (config) { 4843 case PERF_COUNT_HW_CPU_CYCLES: 4844 case PERF_COUNT_HW_INSTRUCTIONS: 4845 case PERF_COUNT_HW_BUS_CYCLES: 4846 case PERF_COUNT_HW_STALLED_CYCLES_FRONTEND: 4847 case PERF_COUNT_HW_STALLED_CYCLES_BACKEND: 4848 case PERF_COUNT_HW_REF_CPU_CYCLES: 4849 factor = 500000000; 4850 break; 4851 case PERF_COUNT_HW_BRANCH_INSTRUCTIONS: 4852 case PERF_COUNT_HW_BRANCH_MISSES: 4853 factor = 125000000; 4854 break; 4855 case PERF_COUNT_HW_CACHE_REFERENCES: 4856 case PERF_COUNT_HW_CACHE_MISSES: 4857 factor = 25000000; 4858 break; 4859 default: 4860 goto end; 4861 } 4862 } 4863 4864 if (type == PERF_TYPE_HW_CACHE) 4865 factor = 25000000; 4866 end: 4867 /* 4868 * Usually, a prime or a number with less factors (close to prime) 4869 * is chosen as an SAV, which makes it less likely that the sampling 4870 * period synchronizes with some periodic event in the workload. 4871 * Minus 1 to make it at least avoiding values near power of twos 4872 * for the default freq. 4873 */ 4874 start = DIV_ROUND_UP_ULL(factor, event->attr.sample_freq) - 1; 4875 4876 if (start > x86_pmu.max_period) 4877 start = x86_pmu.max_period; 4878 4879 if (x86_pmu.limit_period) 4880 x86_pmu.limit_period(event, &start); 4881 4882 return start; 4883 } 4884 4885 static inline bool intel_pmu_has_acr(struct pmu *pmu) 4886 { 4887 return !!hybrid(pmu, acr_cause_mask64); 4888 } 4889 4890 static bool intel_pmu_is_acr_group(struct perf_event *event) 4891 { 4892 /* The group leader has the ACR flag set */ 4893 if (is_acr_event_group(event)) 4894 return true; 4895 4896 /* The acr_mask is set */ 4897 if (event->attr.config2) 4898 return true; 4899 4900 return false; 4901 } 4902 4903 static inline bool intel_pmu_has_pebs_counter_group(struct pmu *pmu) 4904 { 4905 u64 caps; 4906 4907 if (x86_pmu.intel_cap.pebs_format >= 6 && x86_pmu.intel_cap.pebs_baseline) 4908 return true; 4909 4910 caps = hybrid(pmu, arch_pebs_cap).caps; 4911 if (x86_pmu.arch_pebs && (caps & ARCH_PEBS_CNTR_MASK)) 4912 return true; 4913 4914 return false; 4915 } 4916 4917 static inline void intel_pmu_set_acr_cntr_constr(struct perf_event *event, 4918 u64 *cause_mask, int *num) 4919 { 4920 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cntr_mask64); 4921 *cause_mask |= event->attr.config2; 4922 *num += 1; 4923 } 4924 4925 static inline void intel_pmu_set_acr_caused_constr(struct perf_event *event, 4926 int idx, u64 cause_mask) 4927 { 4928 if (test_bit(idx, (unsigned long *)&cause_mask)) 4929 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cause_mask64); 4930 } 4931 4932 static inline int intel_set_branch_counter_constr(struct perf_event *event, 4933 int *num) 4934 { 4935 if (branch_sample_call_stack(event)) 4936 return -EINVAL; 4937 if (branch_sample_counters(event)) { 4938 (*num)++; 4939 event->hw.dyn_constraint &= x86_pmu.lbr_counters; 4940 } 4941 4942 return 0; 4943 } 4944 4945 static int intel_pmu_hw_config(struct perf_event *event) 4946 { 4947 int ret = x86_pmu_hw_config(event); 4948 4949 if (ret) 4950 return ret; 4951 4952 ret = intel_pmu_bts_config(event); 4953 if (ret) 4954 return ret; 4955 4956 if (event->attr.freq && event->attr.sample_freq) { 4957 event->hw.sample_period = intel_pmu_freq_start_period(event); 4958 event->hw.last_period = event->hw.sample_period; 4959 local64_set(&event->hw.period_left, event->hw.sample_period); 4960 } 4961 4962 if (event->attr.precise_ip) { 4963 struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap); 4964 4965 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 4966 return -EINVAL; 4967 4968 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 4969 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 4970 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) && 4971 !has_aux_action(event)) { 4972 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 4973 event->attach_state |= PERF_ATTACH_SCHED_CB; 4974 } 4975 } 4976 if (x86_pmu.pebs_aliases) 4977 x86_pmu.pebs_aliases(event); 4978 4979 if (x86_pmu.arch_pebs) { 4980 u64 cntr_mask = hybrid(event->pmu, intel_ctrl) & 4981 ~GLOBAL_CTRL_EN_PERF_METRICS; 4982 u64 pebs_mask = event->attr.precise_ip >= 3 ? 4983 pebs_cap.pdists : pebs_cap.counters; 4984 if (cntr_mask != pebs_mask) 4985 event->hw.dyn_constraint &= pebs_mask; 4986 } 4987 } 4988 4989 if (needs_branch_stack(event)) { 4990 /* Avoid branch stack setup for counting events in SAMPLE READ */ 4991 if (is_sampling_event(event) || 4992 !(event->attr.sample_type & PERF_SAMPLE_READ)) 4993 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK; 4994 } 4995 4996 if (branch_sample_counters(event)) { 4997 struct perf_event *leader, *sibling; 4998 int num = 0; 4999 5000 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) || 5001 (event->attr.config & ~INTEL_ARCH_EVENT_MASK)) 5002 return -EINVAL; 5003 5004 /* 5005 * The branch counter logging is not supported in the call stack 5006 * mode yet, since we cannot simply flush the LBR during e.g., 5007 * multiplexing. Also, there is no obvious usage with the call 5008 * stack mode. Simply forbids it for now. 5009 * 5010 * If any events in the group enable the branch counter logging 5011 * feature, the group is treated as a branch counter logging 5012 * group, which requires the extra space to store the counters. 5013 */ 5014 leader = event->group_leader; 5015 if (intel_set_branch_counter_constr(leader, &num)) 5016 return -EINVAL; 5017 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS; 5018 5019 for_each_sibling_event(sibling, leader) { 5020 if (intel_set_branch_counter_constr(sibling, &num)) 5021 return -EINVAL; 5022 } 5023 5024 /* event isn't installed as a sibling yet. */ 5025 if (event != leader) { 5026 if (intel_set_branch_counter_constr(event, &num)) 5027 return -EINVAL; 5028 } 5029 5030 if (num > fls(x86_pmu.lbr_counters)) 5031 return -EINVAL; 5032 /* 5033 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't 5034 * require any branch stack setup. 5035 * Clear the bit to avoid unnecessary branch stack setup. 5036 */ 5037 if (0 == (event->attr.branch_sample_type & 5038 ~(PERF_SAMPLE_BRANCH_PLM_ALL | 5039 PERF_SAMPLE_BRANCH_COUNTERS))) 5040 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK; 5041 5042 /* 5043 * Force the leader to be a LBR event. So LBRs can be reset 5044 * with the leader event. See intel_pmu_lbr_del() for details. 5045 */ 5046 if (!intel_pmu_needs_branch_stack(leader)) 5047 return -EINVAL; 5048 } 5049 5050 if (intel_pmu_needs_branch_stack(event)) { 5051 ret = intel_pmu_setup_lbr_filter(event); 5052 if (ret) 5053 return ret; 5054 event->attach_state |= PERF_ATTACH_SCHED_CB; 5055 5056 /* 5057 * BTS is set up earlier in this path, so don't account twice 5058 */ 5059 if (!unlikely(intel_pmu_has_bts(event))) { 5060 /* disallow lbr if conflicting events are present */ 5061 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 5062 return -EBUSY; 5063 5064 event->destroy = hw_perf_lbr_event_destroy; 5065 } 5066 } 5067 5068 if (event->attr.aux_output) { 5069 if (!event->attr.precise_ip) 5070 return -EINVAL; 5071 5072 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 5073 } 5074 5075 if ((event->attr.sample_type & PERF_SAMPLE_READ) && 5076 intel_pmu_has_pebs_counter_group(event->pmu) && 5077 is_sampling_event(event) && 5078 event->attr.precise_ip) 5079 event->group_leader->hw.flags |= PERF_X86_EVENT_PEBS_CNTR; 5080 5081 if (intel_pmu_has_acr(event->pmu) && intel_pmu_is_acr_group(event)) { 5082 struct perf_event *sibling, *leader = event->group_leader; 5083 struct pmu *pmu = event->pmu; 5084 bool has_sw_event = false; 5085 int num = 0, idx = 0; 5086 u64 cause_mask = 0; 5087 5088 /* Not support perf metrics */ 5089 if (is_metric_event(event)) 5090 return -EINVAL; 5091 5092 /* Not support freq mode */ 5093 if (event->attr.freq) 5094 return -EINVAL; 5095 5096 /* PDist is not supported */ 5097 if (event->attr.config2 && event->attr.precise_ip > 2) 5098 return -EINVAL; 5099 5100 /* The reload value cannot exceeds the max period */ 5101 if (event->attr.sample_period > x86_pmu.max_period) 5102 return -EINVAL; 5103 /* 5104 * The counter-constraints of each event cannot be finalized 5105 * unless the whole group is scanned. However, it's hard 5106 * to know whether the event is the last one of the group. 5107 * Recalculate the counter-constraints for each event when 5108 * adding a new event. 5109 * 5110 * The group is traversed twice, which may be optimized later. 5111 * In the first round, 5112 * - Find all events which do reload when other events 5113 * overflow and set the corresponding counter-constraints 5114 * - Add all events, which can cause other events reload, 5115 * in the cause_mask 5116 * - Error out if the number of events exceeds the HW limit 5117 * - The ACR events must be contiguous. 5118 * Error out if there are non-X86 events between ACR events. 5119 * This is not a HW limit, but a SW limit. 5120 * With the assumption, the intel_pmu_acr_late_setup() can 5121 * easily convert the event idx to counter idx without 5122 * traversing the whole event list. 5123 */ 5124 if (!is_x86_event(leader)) 5125 return -EINVAL; 5126 5127 if (leader->attr.config2) 5128 intel_pmu_set_acr_cntr_constr(leader, &cause_mask, &num); 5129 5130 if (leader->nr_siblings) { 5131 for_each_sibling_event(sibling, leader) { 5132 if (!is_x86_event(sibling)) { 5133 has_sw_event = true; 5134 continue; 5135 } 5136 if (!sibling->attr.config2) 5137 continue; 5138 if (has_sw_event) 5139 return -EINVAL; 5140 intel_pmu_set_acr_cntr_constr(sibling, &cause_mask, &num); 5141 } 5142 } 5143 if (leader != event && event->attr.config2) { 5144 if (has_sw_event) 5145 return -EINVAL; 5146 intel_pmu_set_acr_cntr_constr(event, &cause_mask, &num); 5147 } 5148 5149 if (hweight64(cause_mask) > hweight64(hybrid(pmu, acr_cause_mask64)) || 5150 num > hweight64(hybrid(event->pmu, acr_cntr_mask64))) 5151 return -EINVAL; 5152 /* 5153 * In the second round, apply the counter-constraints for 5154 * the events which can cause other events reload. 5155 */ 5156 intel_pmu_set_acr_caused_constr(leader, idx++, cause_mask); 5157 5158 if (leader->nr_siblings) { 5159 for_each_sibling_event(sibling, leader) { 5160 if (is_x86_event(sibling)) 5161 intel_pmu_set_acr_caused_constr(sibling, idx++, cause_mask); 5162 } 5163 } 5164 5165 if (leader != event) 5166 intel_pmu_set_acr_caused_constr(event, idx, cause_mask); 5167 5168 leader->hw.flags |= PERF_X86_EVENT_ACR; 5169 } 5170 5171 intel_pmu_update_rdpmc_user_disable(event); 5172 5173 if ((event->attr.type == PERF_TYPE_HARDWARE) || 5174 (event->attr.type == PERF_TYPE_HW_CACHE)) 5175 return 0; 5176 5177 /* 5178 * Config Topdown slots and metric events 5179 * 5180 * The slots event on Fixed Counter 3 can support sampling, 5181 * which will be handled normally in x86_perf_event_update(). 5182 * 5183 * Metric events don't support sampling and require being paired 5184 * with a slots event as group leader. When the slots event 5185 * is used in a metrics group, it too cannot support sampling. 5186 */ 5187 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 5188 /* The metrics_clear can only be set for the slots event */ 5189 if (event->attr.config1 && 5190 (!is_slots_event(event) || (event->attr.config1 & ~INTEL_TD_CFG_METRIC_CLEAR))) 5191 return -EINVAL; 5192 5193 if (event->attr.config2) 5194 return -EINVAL; 5195 5196 /* 5197 * The TopDown metrics events and slots event don't 5198 * support any filters. 5199 */ 5200 if (event->attr.config & X86_ALL_EVENT_FLAGS) 5201 return -EINVAL; 5202 5203 if (is_available_metric_event(event)) { 5204 struct perf_event *leader = event->group_leader; 5205 5206 /* The metric events don't support sampling. */ 5207 if (is_sampling_event(event)) 5208 return -EINVAL; 5209 5210 /* The metric events require a slots group leader. */ 5211 if (!is_slots_event(leader)) 5212 return -EINVAL; 5213 5214 /* 5215 * The leader/SLOTS must not be a sampling event for 5216 * metric use; hardware requires it starts at 0 when used 5217 * in conjunction with MSR_PERF_METRICS. 5218 */ 5219 if (is_sampling_event(leader)) 5220 return -EINVAL; 5221 5222 event->event_caps |= PERF_EV_CAP_SIBLING; 5223 /* 5224 * Only once we have a METRICs sibling do we 5225 * need TopDown magic. 5226 */ 5227 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 5228 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 5229 } 5230 } 5231 5232 /* 5233 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 5234 * doesn't function quite right. As a work-around it needs to always be 5235 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 5236 * The actual count of this second event is irrelevant it just needs 5237 * to be active to make the first event function correctly. 5238 * 5239 * In a group, the auxiliary event must be in front of the load latency 5240 * event. The rule is to simplify the implementation of the check. 5241 * That's because perf cannot have a complete group at the moment. 5242 */ 5243 if (require_mem_loads_aux_event(event) && 5244 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 5245 is_mem_loads_event(event)) { 5246 struct perf_event *leader = event->group_leader; 5247 struct perf_event *sibling = NULL; 5248 5249 /* 5250 * When this memload event is also the first event (no group 5251 * exists yet), then there is no aux event before it. 5252 */ 5253 if (leader == event) 5254 return -ENODATA; 5255 5256 if (!is_mem_loads_aux_event(leader)) { 5257 for_each_sibling_event(sibling, leader) { 5258 if (is_mem_loads_aux_event(sibling)) 5259 break; 5260 } 5261 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 5262 return -ENODATA; 5263 } 5264 } 5265 5266 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 5267 return 0; 5268 5269 if (x86_pmu.version < 3) 5270 return -EINVAL; 5271 5272 ret = perf_allow_cpu(); 5273 if (ret) 5274 return ret; 5275 5276 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 5277 5278 return 0; 5279 } 5280 5281 /* 5282 * Currently, the only caller of this function is the atomic_switch_perf_msrs(). 5283 * The host perf context helps to prepare the values of the real hardware for 5284 * a set of msrs that need to be switched atomically in a vmx transaction. 5285 * 5286 * For example, the pseudocode needed to add a new msr should look like: 5287 * 5288 * arr[(*nr)++] = (struct perf_guest_switch_msr){ 5289 * .msr = the hardware msr address, 5290 * .host = the value the hardware has when it doesn't run a guest, 5291 * .guest = the value the hardware has when it runs a guest, 5292 * }; 5293 * 5294 * These values have nothing to do with the emulated values the guest sees 5295 * when it uses {RD,WR}MSR, which should be handled by the KVM context, 5296 * specifically in the intel_pmu_{get,set}_msr(). 5297 */ 5298 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) 5299 { 5300 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5301 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 5302 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data; 5303 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 5304 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; 5305 u64 guest_pebs_mask; 5306 int global_ctrl; 5307 5308 /* 5309 * In addition to obeying exclude_guest/exclude_host, remove bits being 5310 * used for PEBS when running a guest, because PEBS writes to virtual 5311 * addresses (not physical addresses). If the guest wants to utilize 5312 * PEBS, and PEBS can be safely enabled in the guest, bits for the guest's 5313 * PEBS-enabled counters will be OR'd back in as appropriate. 5314 */ 5315 *nr = 0; 5316 global_ctrl = (*nr)++; 5317 arr[global_ctrl] = (struct perf_guest_switch_msr){ 5318 .msr = MSR_CORE_PERF_GLOBAL_CTRL, 5319 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, 5320 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask, 5321 }; 5322 5323 if (!x86_pmu.ds_pebs) 5324 return arr; 5325 5326 /* 5327 * If PMU counter has PEBS enabled it is not enough to 5328 * disable counter on a guest entry since PEBS memory 5329 * write can overshoot guest entry and corrupt guest 5330 * memory. Disabling PEBS solves the problem. 5331 * 5332 * Don't do this if the CPU already enforces it. 5333 */ 5334 if (x86_pmu.pebs_no_isolation) { 5335 arr[(*nr)++] = (struct perf_guest_switch_msr){ 5336 .msr = MSR_IA32_PEBS_ENABLE, 5337 .host = cpuc->pebs_enabled, 5338 .guest = 0, 5339 }; 5340 return arr; 5341 } 5342 5343 /* 5344 * If the CPU doesn't support PEBS in the guest, then there's nothing 5345 * more to do as disabling PMCs via PERF_GLOBAL_CTRL is sufficient on 5346 * CPUs with guest/host isolation. 5347 */ 5348 if (!x86_pmu.pebs_ept) 5349 return arr; 5350 5351 /* 5352 * Restrict guest PEBS events to counters that (a) perf supports, (b) 5353 * the guest wants to use for PEBS, (c) are not excluded from counting 5354 * in the guest, and (d) _are_ excluded from counting in the host. 5355 */ 5356 guest_pebs_mask = pebs_mask & intel_ctrl & kvm_pmu->pebs_enable & 5357 ~cpuc->intel_ctrl_host_mask & 5358 cpuc->intel_ctrl_guest_mask; 5359 5360 /* 5361 * Disable counters where the guest PMC is different than the host PMC 5362 * being used on behalf of the guest, as the PEBS record includes 5363 * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the 5364 * wrong counter(s). 5365 */ 5366 guest_pebs_mask &= ~kvm_pmu->host_cross_mapped_mask; 5367 5368 /* 5369 * FIXME: Allow guest and host usage of PEBS events to co-exist instead 5370 * of disabling guest PEBS entirely if the host is using PEBS. 5371 * What exactly goes wrong if guest and host are using PEBS is 5372 * unknown. 5373 */ 5374 if (pebs_mask & ~cpuc->intel_ctrl_guest_mask) 5375 guest_pebs_mask = 0; 5376 5377 /* 5378 * Context switch DS_AREA and PEBS_DATA_CFG if and only if PEBS will be 5379 * active in the guest; if no records will be generated while the guest 5380 * is running, then simply keep the host values resident in hardware. 5381 */ 5382 arr[(*nr)++] = (struct perf_guest_switch_msr){ 5383 .msr = MSR_IA32_DS_AREA, 5384 .host = (unsigned long)cpuc->ds, 5385 .guest = guest_pebs_mask ? kvm_pmu->ds_area : (unsigned long)cpuc->ds, 5386 }; 5387 5388 if (x86_pmu.intel_cap.pebs_baseline) { 5389 arr[(*nr)++] = (struct perf_guest_switch_msr){ 5390 .msr = MSR_PEBS_DATA_CFG, 5391 .host = cpuc->active_pebs_data_cfg, 5392 .guest = guest_pebs_mask ? kvm_pmu->pebs_data_cfg : 5393 cpuc->active_pebs_data_cfg, 5394 }; 5395 } 5396 5397 /* 5398 * Do NOT mess with PEBS_ENABLED. As above, disabling counters via 5399 * PERF_GLOBAL_CTRL is sufficient, and loading a stale PEBS_ENABLED, 5400 * e.g. on VM-Exit, can put the system in a bad state. Simply enable 5401 * counters in PERF_GLOBAL_CTRL, as perf load PEBS_ENABLED with the 5402 * full value, i.e. perf *also* relies on PERF_GLOBAL_CTRL. 5403 */ 5404 arr[global_ctrl].guest |= guest_pebs_mask; 5405 return arr; 5406 } 5407 5408 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data) 5409 { 5410 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5411 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 5412 int idx; 5413 5414 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 5415 struct perf_event *event = cpuc->events[idx]; 5416 5417 arr[idx].msr = x86_pmu_config_addr(idx); 5418 arr[idx].host = arr[idx].guest = 0; 5419 5420 if (!test_bit(idx, cpuc->active_mask)) 5421 continue; 5422 5423 arr[idx].host = arr[idx].guest = 5424 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 5425 5426 if (event->attr.exclude_host) 5427 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 5428 else if (event->attr.exclude_guest) 5429 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 5430 } 5431 5432 *nr = x86_pmu_max_num_counters(cpuc->pmu); 5433 return arr; 5434 } 5435 5436 static void core_pmu_enable_event(struct perf_event *event) 5437 { 5438 if (!event->attr.exclude_host) 5439 x86_pmu_enable_event(event); 5440 } 5441 5442 static void core_pmu_enable_all(int added) 5443 { 5444 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 5445 int idx; 5446 5447 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 5448 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 5449 5450 if (!test_bit(idx, cpuc->active_mask) || 5451 cpuc->events[idx]->attr.exclude_host) 5452 continue; 5453 5454 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 5455 } 5456 } 5457 5458 static int hsw_hw_config(struct perf_event *event) 5459 { 5460 int ret = intel_pmu_hw_config(event); 5461 5462 if (ret) 5463 return ret; 5464 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 5465 return 0; 5466 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 5467 5468 /* 5469 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 5470 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 5471 * this combination. 5472 */ 5473 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 5474 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 5475 event->attr.precise_ip > 0)) 5476 return -EOPNOTSUPP; 5477 5478 if (event_is_checkpointed(event)) { 5479 /* 5480 * Sampling of checkpointed events can cause situations where 5481 * the CPU constantly aborts because of a overflow, which is 5482 * then checkpointed back and ignored. Forbid checkpointing 5483 * for sampling. 5484 * 5485 * But still allow a long sampling period, so that perf stat 5486 * from KVM works. 5487 */ 5488 if (event->attr.sample_period > 0 && 5489 event->attr.sample_period < 0x7fffffff) 5490 return -EOPNOTSUPP; 5491 } 5492 return 0; 5493 } 5494 5495 static struct event_constraint counter0_constraint = 5496 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 5497 5498 static struct event_constraint counter1_constraint = 5499 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2); 5500 5501 static struct event_constraint counter0_1_constraint = 5502 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3); 5503 5504 static struct event_constraint counter2_constraint = 5505 EVENT_CONSTRAINT(0, 0x4, 0); 5506 5507 static struct event_constraint fixed0_constraint = 5508 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 5509 5510 static struct event_constraint fixed0_counter0_constraint = 5511 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 5512 5513 static struct event_constraint fixed0_counter0_1_constraint = 5514 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); 5515 5516 static struct event_constraint counters_1_7_constraint = 5517 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL); 5518 5519 static struct event_constraint * 5520 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5521 struct perf_event *event) 5522 { 5523 struct event_constraint *c; 5524 5525 c = intel_get_event_constraints(cpuc, idx, event); 5526 5527 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 5528 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 5529 if (c->idxmsk64 & (1U << 2)) 5530 return &counter2_constraint; 5531 return &emptyconstraint; 5532 } 5533 5534 return c; 5535 } 5536 5537 static struct event_constraint * 5538 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5539 struct perf_event *event) 5540 { 5541 /* 5542 * Fixed counter 0 has less skid. 5543 * Force instruction:ppp in Fixed counter 0 5544 */ 5545 if ((event->attr.precise_ip == 3) && 5546 constraint_match(&fixed0_constraint, event->hw.config)) 5547 return &fixed0_constraint; 5548 5549 return hsw_get_event_constraints(cpuc, idx, event); 5550 } 5551 5552 static struct event_constraint * 5553 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5554 struct perf_event *event) 5555 { 5556 struct event_constraint *c; 5557 5558 c = icl_get_event_constraints(cpuc, idx, event); 5559 5560 /* 5561 * The :ppp indicates the Precise Distribution (PDist) facility, which 5562 * is only supported on the GP counter 0. If a :ppp event which is not 5563 * available on the GP counter 0, error out. 5564 * Exception: Instruction PDIR is only available on the fixed counter 0. 5565 */ 5566 if ((event->attr.precise_ip == 3) && 5567 !constraint_match(&fixed0_constraint, event->hw.config)) { 5568 if (c->idxmsk64 & BIT_ULL(0)) 5569 return &counter0_constraint; 5570 5571 return &emptyconstraint; 5572 } 5573 5574 return c; 5575 } 5576 5577 static struct event_constraint * 5578 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5579 struct perf_event *event) 5580 { 5581 struct event_constraint *c; 5582 5583 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 5584 if (event->attr.precise_ip == 3) 5585 return &counter0_constraint; 5586 5587 c = intel_get_event_constraints(cpuc, idx, event); 5588 5589 return c; 5590 } 5591 5592 static struct event_constraint * 5593 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5594 struct perf_event *event) 5595 { 5596 struct event_constraint *c; 5597 5598 c = intel_get_event_constraints(cpuc, idx, event); 5599 5600 /* 5601 * :ppp means to do reduced skid PEBS, 5602 * which is available on PMC0 and fixed counter 0. 5603 */ 5604 if (event->attr.precise_ip == 3) { 5605 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 5606 if (constraint_match(&fixed0_constraint, event->hw.config)) 5607 return &fixed0_counter0_constraint; 5608 5609 return &counter0_constraint; 5610 } 5611 5612 return c; 5613 } 5614 5615 static bool allow_tsx_force_abort = true; 5616 5617 static struct event_constraint * 5618 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5619 struct perf_event *event) 5620 { 5621 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 5622 5623 /* 5624 * Without TFA we must not use PMC3. 5625 */ 5626 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 5627 c = dyn_constraint(cpuc, c, idx); 5628 c->idxmsk64 &= ~(1ULL << 3); 5629 c->weight--; 5630 } 5631 5632 return c; 5633 } 5634 5635 static struct event_constraint * 5636 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5637 struct perf_event *event) 5638 { 5639 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5640 5641 if (pmu->pmu_type == hybrid_big) 5642 return glc_get_event_constraints(cpuc, idx, event); 5643 else if (pmu->pmu_type == hybrid_small) 5644 return tnt_get_event_constraints(cpuc, idx, event); 5645 5646 WARN_ON(1); 5647 return &emptyconstraint; 5648 } 5649 5650 static struct event_constraint * 5651 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5652 struct perf_event *event) 5653 { 5654 struct event_constraint *c; 5655 5656 c = intel_get_event_constraints(cpuc, idx, event); 5657 5658 /* 5659 * The :ppp indicates the Precise Distribution (PDist) facility, which 5660 * is only supported on the GP counter 0 & 1 and Fixed counter 0. 5661 * If a :ppp event which is not available on the above eligible counters, 5662 * error out. 5663 */ 5664 if (event->attr.precise_ip == 3) { 5665 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */ 5666 if (constraint_match(&fixed0_constraint, event->hw.config)) { 5667 /* The fixed counter 0 doesn't support LBR event logging. */ 5668 if (branch_sample_counters(event)) 5669 return &counter0_1_constraint; 5670 else 5671 return &fixed0_counter0_1_constraint; 5672 } 5673 5674 switch (c->idxmsk64 & 0x3ull) { 5675 case 0x1: 5676 return &counter0_constraint; 5677 case 0x2: 5678 return &counter1_constraint; 5679 case 0x3: 5680 return &counter0_1_constraint; 5681 } 5682 return &emptyconstraint; 5683 } 5684 5685 return c; 5686 } 5687 5688 static struct event_constraint * 5689 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5690 struct perf_event *event) 5691 { 5692 struct event_constraint *c; 5693 5694 c = glc_get_event_constraints(cpuc, idx, event); 5695 5696 /* The Retire Latency is not supported by the fixed counter 0. */ 5697 if (event->attr.precise_ip && 5698 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) && 5699 constraint_match(&fixed0_constraint, event->hw.config)) { 5700 /* 5701 * The Instruction PDIR is only available 5702 * on the fixed counter 0. Error out for this case. 5703 */ 5704 if (event->attr.precise_ip == 3) 5705 return &emptyconstraint; 5706 return &counters_1_7_constraint; 5707 } 5708 5709 return c; 5710 } 5711 5712 static struct event_constraint * 5713 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5714 struct perf_event *event) 5715 { 5716 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5717 5718 if (pmu->pmu_type == hybrid_big) 5719 return rwc_get_event_constraints(cpuc, idx, event); 5720 if (pmu->pmu_type == hybrid_small) 5721 return cmt_get_event_constraints(cpuc, idx, event); 5722 5723 WARN_ON(1); 5724 return &emptyconstraint; 5725 } 5726 5727 static int adl_hw_config(struct perf_event *event) 5728 { 5729 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5730 5731 if (pmu->pmu_type == hybrid_big) 5732 return hsw_hw_config(event); 5733 else if (pmu->pmu_type == hybrid_small) 5734 return intel_pmu_hw_config(event); 5735 5736 WARN_ON(1); 5737 return -EOPNOTSUPP; 5738 } 5739 5740 static enum intel_cpu_type adl_get_hybrid_cpu_type(void) 5741 { 5742 return INTEL_CPU_TYPE_CORE; 5743 } 5744 5745 static inline bool erratum_hsw11(struct perf_event *event) 5746 { 5747 return (event->hw.config & INTEL_ARCH_EVENT_MASK) == 5748 X86_CONFIG(.event=0xc0, .umask=0x01); 5749 } 5750 5751 static struct event_constraint * 5752 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5753 struct perf_event *event) 5754 { 5755 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5756 5757 if (pmu->pmu_type == hybrid_tiny) 5758 return cmt_get_event_constraints(cpuc, idx, event); 5759 5760 return mtl_get_event_constraints(cpuc, idx, event); 5761 } 5762 5763 static int arl_h_hw_config(struct perf_event *event) 5764 { 5765 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5766 5767 if (pmu->pmu_type == hybrid_tiny) 5768 return intel_pmu_hw_config(event); 5769 5770 return adl_hw_config(event); 5771 } 5772 5773 /* 5774 * The HSW11 requires a period larger than 100 which is the same as the BDM11. 5775 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL. 5776 * 5777 * The message 'interrupt took too long' can be observed on any counter which 5778 * was armed with a period < 32 and two events expired in the same NMI. 5779 * A minimum period of 32 is enforced for the rest of the events. 5780 */ 5781 static void hsw_limit_period(struct perf_event *event, s64 *left) 5782 { 5783 *left = max(*left, erratum_hsw11(event) ? 128 : 32); 5784 } 5785 5786 /* 5787 * Broadwell: 5788 * 5789 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 5790 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 5791 * the two to enforce a minimum period of 128 (the smallest value that has bits 5792 * 0-5 cleared and >= 100). 5793 * 5794 * Because of how the code in x86_perf_event_set_period() works, the truncation 5795 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 5796 * to make up for the 'lost' events due to carrying the 'error' in period_left. 5797 * 5798 * Therefore the effective (average) period matches the requested period, 5799 * despite coarser hardware granularity. 5800 */ 5801 static void bdw_limit_period(struct perf_event *event, s64 *left) 5802 { 5803 if (erratum_hsw11(event)) { 5804 if (*left < 128) 5805 *left = 128; 5806 *left &= ~0x3fULL; 5807 } 5808 } 5809 5810 static void nhm_limit_period(struct perf_event *event, s64 *left) 5811 { 5812 *left = max(*left, 32LL); 5813 } 5814 5815 static void glc_limit_period(struct perf_event *event, s64 *left) 5816 { 5817 if (event->attr.precise_ip == 3) 5818 *left = max(*left, 128LL); 5819 } 5820 5821 PMU_FORMAT_ATTR(event, "config:0-7" ); 5822 PMU_FORMAT_ATTR(umask, "config:8-15" ); 5823 PMU_FORMAT_ATTR(edge, "config:18" ); 5824 PMU_FORMAT_ATTR(pc, "config:19" ); 5825 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 5826 PMU_FORMAT_ATTR(inv, "config:23" ); 5827 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 5828 PMU_FORMAT_ATTR(in_tx, "config:32" ); 5829 PMU_FORMAT_ATTR(in_tx_cp, "config:33" ); 5830 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */ 5831 5832 PMU_FORMAT_ATTR(metrics_clear, "config1:0"); /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */ 5833 5834 static ssize_t umask2_show(struct device *dev, 5835 struct device_attribute *attr, 5836 char *page) 5837 { 5838 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2; 5839 5840 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2) 5841 return sprintf(page, "config:8-15,40-47\n"); 5842 5843 /* Roll back to the old format if umask2 is not supported. */ 5844 return sprintf(page, "config:8-15\n"); 5845 } 5846 5847 static struct device_attribute format_attr_umask2 = 5848 __ATTR(umask, 0444, umask2_show, NULL); 5849 5850 static struct attribute *format_evtsel_ext_attrs[] = { 5851 &format_attr_umask2.attr, 5852 &format_attr_eq.attr, 5853 &format_attr_metrics_clear.attr, 5854 NULL 5855 }; 5856 5857 static umode_t 5858 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5859 { 5860 struct device *dev = kobj_to_dev(kobj); 5861 u64 mask; 5862 5863 /* 5864 * The umask and umask2 have different formats but share the 5865 * same attr name. In update mode, the previous value of the 5866 * umask is unconditionally removed before is_visible. If 5867 * umask2 format is not enumerated, it's impossible to roll 5868 * back to the old format. 5869 * Does the check in umask2_show rather than is_visible. 5870 */ 5871 if (i == 0) 5872 return attr->mode; 5873 5874 mask = hybrid(dev_get_drvdata(dev), config_mask); 5875 if (i == 1) 5876 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0; 5877 5878 /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */ 5879 if (i == 2) { 5880 union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap); 5881 5882 return intel_cap.rdpmc_metrics_clear ? attr->mode : 0; 5883 } 5884 5885 return 0; 5886 } 5887 5888 static struct attribute *intel_arch_formats_attr[] = { 5889 &format_attr_event.attr, 5890 &format_attr_umask.attr, 5891 &format_attr_edge.attr, 5892 &format_attr_pc.attr, 5893 &format_attr_inv.attr, 5894 &format_attr_cmask.attr, 5895 NULL, 5896 }; 5897 5898 ssize_t intel_event_sysfs_show(char *page, u64 config) 5899 { 5900 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 5901 5902 return x86_event_sysfs_show(page, config, event); 5903 } 5904 5905 static struct intel_shared_regs *allocate_shared_regs(int cpu) 5906 { 5907 struct intel_shared_regs *regs; 5908 int i; 5909 5910 regs = kzalloc_node(sizeof(struct intel_shared_regs), 5911 GFP_KERNEL, cpu_to_node(cpu)); 5912 if (regs) { 5913 /* 5914 * initialize the locks to keep lockdep happy 5915 */ 5916 for (i = 0; i < EXTRA_REG_MAX; i++) 5917 raw_spin_lock_init(®s->regs[i].lock); 5918 5919 regs->core_id = -1; 5920 } 5921 return regs; 5922 } 5923 5924 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 5925 { 5926 struct intel_excl_cntrs *c; 5927 5928 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 5929 GFP_KERNEL, cpu_to_node(cpu)); 5930 if (c) { 5931 raw_spin_lock_init(&c->lock); 5932 c->core_id = -1; 5933 } 5934 return c; 5935 } 5936 5937 5938 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 5939 { 5940 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 5941 5942 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 5943 cpuc->shared_regs = allocate_shared_regs(cpu); 5944 if (!cpuc->shared_regs) 5945 goto err; 5946 } 5947 5948 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_DYN_CONSTRAINT)) { 5949 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 5950 5951 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 5952 if (!cpuc->constraint_list) 5953 goto err_shared_regs; 5954 } 5955 5956 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 5957 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 5958 if (!cpuc->excl_cntrs) 5959 goto err_constraint_list; 5960 5961 cpuc->excl_thread_id = 0; 5962 } 5963 5964 return 0; 5965 5966 err_constraint_list: 5967 kfree(cpuc->constraint_list); 5968 cpuc->constraint_list = NULL; 5969 5970 err_shared_regs: 5971 kfree(cpuc->shared_regs); 5972 cpuc->shared_regs = NULL; 5973 5974 err: 5975 return -ENOMEM; 5976 } 5977 5978 static int intel_pmu_cpu_prepare(int cpu) 5979 { 5980 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5981 int ret; 5982 5983 ret = intel_cpuc_prepare(cpuc, cpu); 5984 if (ret) 5985 return ret; 5986 5987 ret = alloc_arch_pebs_buf_on_cpu(cpu); 5988 if (ret) { 5989 intel_cpuc_finish(cpuc); 5990 return ret; 5991 } 5992 5993 return 0; 5994 } 5995 5996 static void flip_smm_bit(void *data) 5997 { 5998 unsigned long set = *(unsigned long *)data; 5999 6000 if (set > 0) { 6001 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 6002 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 6003 } else { 6004 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 6005 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 6006 } 6007 } 6008 6009 static void intel_pmu_check_counters_mask(u64 *cntr_mask, 6010 u64 *fixed_cntr_mask, 6011 u64 *intel_ctrl) 6012 { 6013 unsigned int bit; 6014 6015 bit = fls64(*cntr_mask); 6016 if (bit > INTEL_PMC_MAX_GENERIC) { 6017 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 6018 bit, INTEL_PMC_MAX_GENERIC); 6019 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); 6020 } 6021 *intel_ctrl = *cntr_mask; 6022 6023 bit = fls64(*fixed_cntr_mask); 6024 if (bit > INTEL_PMC_MAX_FIXED) { 6025 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 6026 bit, INTEL_PMC_MAX_FIXED); 6027 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 6028 } 6029 6030 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED; 6031 } 6032 6033 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 6034 u64 cntr_mask, 6035 u64 fixed_cntr_mask, 6036 u64 intel_ctrl); 6037 6038 enum dyn_constr_type { 6039 DYN_CONSTR_NONE, 6040 DYN_CONSTR_BR_CNTR, 6041 DYN_CONSTR_ACR_CNTR, 6042 DYN_CONSTR_ACR_CAUSE, 6043 DYN_CONSTR_PEBS, 6044 DYN_CONSTR_PDIST, 6045 6046 DYN_CONSTR_MAX, 6047 }; 6048 6049 static const char * const dyn_constr_type_name[] = { 6050 [DYN_CONSTR_NONE] = "a normal event", 6051 [DYN_CONSTR_BR_CNTR] = "a branch counter logging event", 6052 [DYN_CONSTR_ACR_CNTR] = "an auto-counter reload event", 6053 [DYN_CONSTR_ACR_CAUSE] = "an auto-counter reload cause event", 6054 [DYN_CONSTR_PEBS] = "a PEBS event", 6055 [DYN_CONSTR_PDIST] = "a PEBS PDIST event", 6056 }; 6057 6058 static void __intel_pmu_check_dyn_constr(struct event_constraint *constr, 6059 enum dyn_constr_type type, u64 mask) 6060 { 6061 struct event_constraint *c1, *c2; 6062 int new_weight, check_weight; 6063 u64 new_mask, check_mask; 6064 6065 for_each_event_constraint(c1, constr) { 6066 new_mask = c1->idxmsk64 & mask; 6067 new_weight = hweight64(new_mask); 6068 6069 /* ignore topdown perf metrics event */ 6070 if (c1->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) 6071 continue; 6072 6073 if (!new_weight && fls64(c1->idxmsk64) < INTEL_PMC_IDX_FIXED) { 6074 pr_info("The event 0x%llx is not supported as %s.\n", 6075 c1->code, dyn_constr_type_name[type]); 6076 } 6077 6078 if (new_weight <= 1) 6079 continue; 6080 6081 for_each_event_constraint(c2, c1 + 1) { 6082 bool check_fail = false; 6083 6084 check_mask = c2->idxmsk64 & mask; 6085 check_weight = hweight64(check_mask); 6086 6087 if (c2->idxmsk64 & INTEL_PMC_MSK_TOPDOWN || 6088 !check_weight) 6089 continue; 6090 6091 /* The same constraints or no overlap */ 6092 if (new_mask == check_mask || 6093 (new_mask ^ check_mask) == (new_mask | check_mask)) 6094 continue; 6095 6096 /* 6097 * A scheduler issue may be triggered in the following cases. 6098 * - Two overlap constraints have the same weight. 6099 * E.g., A constraints: 0x3, B constraints: 0x6 6100 * event counter failure case 6101 * B PMC[2:1] 1 6102 * A PMC[1:0] 0 6103 * A PMC[1:0] FAIL 6104 * - Two overlap constraints have different weight. 6105 * The constraint has a low weight, but has high last bit. 6106 * E.g., A constraints: 0x7, B constraints: 0xC 6107 * event counter failure case 6108 * B PMC[3:2] 2 6109 * A PMC[2:0] 0 6110 * A PMC[2:0] 1 6111 * A PMC[2:0] FAIL 6112 */ 6113 if (new_weight == check_weight) { 6114 check_fail = true; 6115 } else if (new_weight < check_weight) { 6116 if ((new_mask | check_mask) != check_mask && 6117 fls64(new_mask) > fls64(check_mask)) 6118 check_fail = true; 6119 } else { 6120 if ((new_mask | check_mask) != new_mask && 6121 fls64(new_mask) < fls64(check_mask)) 6122 check_fail = true; 6123 } 6124 6125 if (check_fail) { 6126 pr_warn("The two events 0x%llx and 0x%llx may not be " 6127 "fully scheduled under some circumstances as " 6128 "%s.\n", 6129 c1->code, c2->code, dyn_constr_type_name[type]); 6130 } 6131 } 6132 } 6133 } 6134 6135 static void intel_pmu_check_dyn_constr(struct pmu *pmu, 6136 struct event_constraint *constr, 6137 u64 cntr_mask) 6138 { 6139 u64 gp_mask = GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); 6140 enum dyn_constr_type i; 6141 u64 mask; 6142 6143 for (i = DYN_CONSTR_NONE; i < DYN_CONSTR_MAX; i++) { 6144 mask = 0; 6145 switch (i) { 6146 case DYN_CONSTR_NONE: 6147 mask = cntr_mask; 6148 break; 6149 case DYN_CONSTR_BR_CNTR: 6150 if (x86_pmu.flags & PMU_FL_BR_CNTR) 6151 mask = x86_pmu.lbr_counters; 6152 break; 6153 case DYN_CONSTR_ACR_CNTR: 6154 mask = hybrid(pmu, acr_cntr_mask64) & gp_mask; 6155 break; 6156 case DYN_CONSTR_ACR_CAUSE: 6157 if (hybrid(pmu, acr_cntr_mask64) == 6158 hybrid(pmu, acr_cause_mask64)) 6159 continue; 6160 mask = hybrid(pmu, acr_cause_mask64) & gp_mask; 6161 break; 6162 case DYN_CONSTR_PEBS: 6163 if (x86_pmu.arch_pebs) { 6164 mask = hybrid(pmu, arch_pebs_cap).counters & 6165 gp_mask; 6166 } 6167 break; 6168 case DYN_CONSTR_PDIST: 6169 if (x86_pmu.arch_pebs) { 6170 mask = hybrid(pmu, arch_pebs_cap).pdists & 6171 gp_mask; 6172 } 6173 break; 6174 default: 6175 pr_warn("Unsupported dynamic constraint type %d\n", i); 6176 } 6177 6178 if (mask) 6179 __intel_pmu_check_dyn_constr(constr, i, mask); 6180 } 6181 } 6182 6183 static void intel_pmu_check_event_constraints_all(struct pmu *pmu) 6184 { 6185 struct event_constraint *event_constraints = hybrid(pmu, event_constraints); 6186 struct event_constraint *pebs_constraints = hybrid(pmu, pebs_constraints); 6187 u64 cntr_mask = hybrid(pmu, cntr_mask64); 6188 u64 fixed_cntr_mask = hybrid(pmu, fixed_cntr_mask64); 6189 u64 intel_ctrl = hybrid(pmu, intel_ctrl); 6190 6191 intel_pmu_check_event_constraints(event_constraints, cntr_mask, 6192 fixed_cntr_mask, intel_ctrl); 6193 6194 if (event_constraints) 6195 intel_pmu_check_dyn_constr(pmu, event_constraints, cntr_mask); 6196 6197 if (pebs_constraints) 6198 intel_pmu_check_dyn_constr(pmu, pebs_constraints, cntr_mask); 6199 } 6200 6201 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs); 6202 6203 static inline bool intel_pmu_broken_perf_cap(void) 6204 { 6205 /* 6206 * The Perf Metric (Bit 15) is always cleared on P-core of 6207 * RPL and MTL. Details can be found in RPL018 erratum. 6208 */ 6209 if (boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE || 6210 boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE_P || 6211 boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE_S || 6212 boot_cpu_data.x86_vfm == INTEL_METEORLAKE || 6213 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L) 6214 return true; 6215 6216 return false; 6217 } 6218 6219 static inline void __intel_update_pmu_caps(struct pmu *pmu) 6220 { 6221 struct pmu *dest_pmu = pmu ? pmu : x86_get_pmu(smp_processor_id()); 6222 6223 if (hybrid(pmu, arch_pebs_cap).caps & ARCH_PEBS_VECR_XMM) 6224 dest_pmu->capabilities |= PERF_PMU_CAP_EXTENDED_REGS; 6225 } 6226 6227 static inline void __intel_update_large_pebs_flags(struct pmu *pmu) 6228 { 6229 u64 caps = hybrid(pmu, arch_pebs_cap).caps; 6230 6231 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; 6232 if (caps & ARCH_PEBS_LBR) 6233 x86_pmu.large_pebs_flags |= PERF_SAMPLE_BRANCH_STACK; 6234 if (caps & ARCH_PEBS_CNTR_MASK) 6235 x86_pmu.large_pebs_flags |= PERF_SAMPLE_READ; 6236 6237 if (!(caps & ARCH_PEBS_AUX)) 6238 x86_pmu.large_pebs_flags &= ~PERF_SAMPLE_DATA_SRC; 6239 if (!(caps & ARCH_PEBS_GPR)) { 6240 x86_pmu.large_pebs_flags &= 6241 ~(PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER); 6242 } 6243 } 6244 6245 #define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) << INTEL_PMC_IDX_FIXED)) 6246 6247 static void update_pmu_cap_from_perfmonext(struct pmu *pmu) 6248 { 6249 unsigned int eax, ebx, ecx, edx; 6250 union cpuid35_eax eax_0; 6251 union cpuid35_ebx ebx_0; 6252 u64 cntrs_mask = 0; 6253 u64 pebs_mask = 0; 6254 u64 pdists_mask = 0; 6255 6256 cpuid(ARCH_PERFMON_EXT_LEAF, &eax_0.full, &ebx_0.full, &ecx, &edx); 6257 6258 if (ebx_0.split.umask2) 6259 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2; 6260 if (ebx_0.split.eq) 6261 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ; 6262 if (ebx_0.split.rdpmc_user_disable) 6263 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE; 6264 6265 if (eax_0.split.cntr_subleaf) { 6266 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, 6267 &eax, &ebx, &ecx, &edx); 6268 hybrid(pmu, cntr_mask64) = eax; 6269 hybrid(pmu, fixed_cntr_mask64) = ebx; 6270 cntrs_mask = counter_mask(eax, ebx); 6271 } 6272 6273 if (eax_0.split.acr_subleaf) { 6274 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_ACR_LEAF, 6275 &eax, &ebx, &ecx, &edx); 6276 /* The mask of the counters which can be reloaded */ 6277 hybrid(pmu, acr_cntr_mask64) = counter_mask(eax, ebx); 6278 /* The mask of the counters which can cause a reload of reloadable counters */ 6279 hybrid(pmu, acr_cause_mask64) = counter_mask(ecx, edx); 6280 } 6281 6282 /* Bits[5:4] should be set simultaneously if arch-PEBS is supported */ 6283 if (eax_0.split.pebs_caps_subleaf && eax_0.split.pebs_cnts_subleaf) { 6284 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_CAP_LEAF, 6285 &eax, &ebx, &ecx, &edx); 6286 hybrid(pmu, arch_pebs_cap).caps = (u64)ebx << 32; 6287 6288 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_COUNTER_LEAF, 6289 &eax, &ebx, &ecx, &edx); 6290 pebs_mask = counter_mask(eax, ecx); 6291 pdists_mask = counter_mask(ebx, edx); 6292 hybrid(pmu, arch_pebs_cap).counters = pebs_mask; 6293 hybrid(pmu, arch_pebs_cap).pdists = pdists_mask; 6294 6295 if (WARN_ON((pebs_mask | pdists_mask) & ~cntrs_mask)) { 6296 x86_pmu.arch_pebs = 0; 6297 } else { 6298 __intel_update_pmu_caps(pmu); 6299 __intel_update_large_pebs_flags(pmu); 6300 } 6301 } else { 6302 WARN_ON(x86_pmu.arch_pebs == 1); 6303 x86_pmu.arch_pebs = 0; 6304 } 6305 } 6306 6307 static void intel_update_pmu_caps(struct pmu *pmu) 6308 { 6309 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) 6310 update_pmu_cap_from_perfmonext(pmu); 6311 6312 if (is_hybrid() && this_cpu_has(X86_FEATURE_PDCM)) { 6313 rdmsrq(MSR_IA32_PERF_CAPABILITIES, 6314 hybrid(pmu, intel_cap).capabilities); 6315 6316 /* 6317 * Restore perf_metrics on platforms with broken 6318 * perf_capablities. 6319 */ 6320 if (intel_pmu_broken_perf_cap() && 6321 hybrid_pmu(pmu)->pmu_type == hybrid_big) 6322 hybrid(pmu, intel_cap).perf_metrics = 1; 6323 } 6324 } 6325 6326 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) 6327 { 6328 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64, 6329 &pmu->intel_ctrl); 6330 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 6331 pmu->unconstrained = (struct event_constraint) 6332 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 6333 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 6334 6335 if (pmu->intel_cap.perf_metrics) 6336 pmu->intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS; 6337 else 6338 pmu->intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS; 6339 6340 pmu->pmu.capabilities |= PERF_PMU_CAP_MEDIATED_VPMU; 6341 6342 intel_pmu_check_event_constraints_all(&pmu->pmu); 6343 6344 intel_pmu_check_extra_regs(pmu->extra_regs); 6345 } 6346 6347 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void) 6348 { 6349 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 6350 enum intel_cpu_type cpu_type = c->topo.intel_type; 6351 int i; 6352 6353 /* 6354 * This is running on a CPU model that is known to have hybrid 6355 * configurations. But the CPU told us it is not hybrid, shame 6356 * on it. There should be a fixup function provided for these 6357 * troublesome CPUs (->get_hybrid_cpu_type). 6358 */ 6359 if (cpu_type == INTEL_CPU_TYPE_UNKNOWN) { 6360 if (x86_pmu.get_hybrid_cpu_type) 6361 cpu_type = x86_pmu.get_hybrid_cpu_type(); 6362 else 6363 return NULL; 6364 } 6365 6366 /* 6367 * This essentially just maps between the 'hybrid_cpu_type' 6368 * and 'hybrid_pmu_type' enums except for ARL-H processor 6369 * which needs to compare atom uarch native id since ARL-H 6370 * contains two different atom uarchs. 6371 */ 6372 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 6373 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type; 6374 u32 native_id; 6375 6376 if (cpu_type == INTEL_CPU_TYPE_CORE && pmu_type == hybrid_big) 6377 return &x86_pmu.hybrid_pmu[i]; 6378 if (cpu_type == INTEL_CPU_TYPE_ATOM) { 6379 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small) 6380 return &x86_pmu.hybrid_pmu[i]; 6381 6382 native_id = c->topo.intel_native_model_id; 6383 if (native_id == INTEL_ATOM_SKT_NATIVE_ID && pmu_type == hybrid_small) 6384 return &x86_pmu.hybrid_pmu[i]; 6385 if (native_id == INTEL_ATOM_CMT_NATIVE_ID && pmu_type == hybrid_tiny) 6386 return &x86_pmu.hybrid_pmu[i]; 6387 } 6388 } 6389 6390 return NULL; 6391 } 6392 6393 static bool init_hybrid_pmu(int cpu) 6394 { 6395 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 6396 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu(); 6397 6398 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 6399 cpuc->pmu = NULL; 6400 return false; 6401 } 6402 6403 /* Only check and dump the PMU information for the first CPU */ 6404 if (!cpumask_empty(&pmu->supported_cpus)) 6405 goto end; 6406 6407 intel_update_pmu_caps(&pmu->pmu); 6408 intel_pmu_check_hybrid_pmus(pmu); 6409 6410 if (!check_hw_exists(pmu->cntr_mask, pmu->fixed_cntr_mask)) { 6411 cpuc->pmu = NULL; 6412 return false; 6413 } 6414 6415 pr_info("%s PMU driver: ", pmu->name); 6416 6417 pr_cont("\n"); 6418 6419 x86_pmu_show_pmu_cap(&pmu->pmu); 6420 6421 end: 6422 cpumask_set_cpu(cpu, &pmu->supported_cpus); 6423 cpuc->pmu = &pmu->pmu; 6424 6425 return true; 6426 } 6427 6428 static void intel_pmu_cpu_starting(int cpu) 6429 { 6430 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 6431 int core_id = topology_core_id(cpu); 6432 int i; 6433 6434 if (is_hybrid() && !init_hybrid_pmu(cpu)) 6435 return; 6436 6437 init_debug_store_on_cpu(cpu); 6438 init_arch_pebs_on_cpu(cpu); 6439 /* 6440 * Deal with CPUs that don't clear their LBRs on power-up, and that may 6441 * even boot with LBRs enabled. 6442 */ 6443 if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr) 6444 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT); 6445 intel_pmu_lbr_reset(); 6446 6447 cpuc->lbr_sel = NULL; 6448 6449 if (x86_pmu.flags & PMU_FL_TFA) { 6450 WARN_ON_ONCE(cpuc->tfa_shadow); 6451 cpuc->tfa_shadow = ~0ULL; 6452 intel_set_tfa(cpuc, false); 6453 } 6454 6455 if (x86_pmu.version > 1) 6456 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 6457 6458 /* 6459 * Disable perf metrics if any added CPU doesn't support it. 6460 * 6461 * Turn off the check for a hybrid architecture, because the 6462 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 6463 * the architecture features. The perf metrics is a model-specific 6464 * feature for now. The corresponding bit should always be 0 on 6465 * a hybrid platform, e.g., Alder Lake. 6466 */ 6467 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 6468 union perf_capabilities perf_cap; 6469 6470 rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 6471 if (!perf_cap.perf_metrics) { 6472 x86_pmu.intel_cap.perf_metrics = 0; 6473 x86_pmu.intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS; 6474 } 6475 } 6476 6477 __intel_update_pmu_caps(cpuc->pmu); 6478 6479 if (!cpuc->shared_regs) 6480 return; 6481 6482 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 6483 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 6484 struct intel_shared_regs *pc; 6485 6486 pc = per_cpu(cpu_hw_events, i).shared_regs; 6487 if (pc && pc->core_id == core_id) { 6488 cpuc->kfree_on_online[0] = cpuc->shared_regs; 6489 cpuc->shared_regs = pc; 6490 break; 6491 } 6492 } 6493 cpuc->shared_regs->core_id = core_id; 6494 cpuc->shared_regs->refcnt++; 6495 } 6496 6497 if (x86_pmu.lbr_sel_map) 6498 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 6499 6500 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 6501 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 6502 struct cpu_hw_events *sibling; 6503 struct intel_excl_cntrs *c; 6504 6505 sibling = &per_cpu(cpu_hw_events, i); 6506 c = sibling->excl_cntrs; 6507 if (c && c->core_id == core_id) { 6508 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 6509 cpuc->excl_cntrs = c; 6510 if (!sibling->excl_thread_id) 6511 cpuc->excl_thread_id = 1; 6512 break; 6513 } 6514 } 6515 cpuc->excl_cntrs->core_id = core_id; 6516 cpuc->excl_cntrs->refcnt++; 6517 } 6518 } 6519 6520 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 6521 { 6522 struct intel_excl_cntrs *c; 6523 6524 c = cpuc->excl_cntrs; 6525 if (c) { 6526 if (c->core_id == -1 || --c->refcnt == 0) 6527 kfree(c); 6528 cpuc->excl_cntrs = NULL; 6529 } 6530 6531 kfree(cpuc->constraint_list); 6532 cpuc->constraint_list = NULL; 6533 } 6534 6535 static void intel_pmu_cpu_dying(int cpu) 6536 { 6537 fini_debug_store_on_cpu(cpu); 6538 fini_arch_pebs_on_cpu(cpu); 6539 } 6540 6541 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 6542 { 6543 struct intel_shared_regs *pc; 6544 6545 pc = cpuc->shared_regs; 6546 if (pc) { 6547 if (pc->core_id == -1 || --pc->refcnt == 0) 6548 kfree(pc); 6549 cpuc->shared_regs = NULL; 6550 } 6551 6552 free_excl_cntrs(cpuc); 6553 } 6554 6555 static void intel_pmu_cpu_dead(int cpu) 6556 { 6557 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 6558 struct pmu *pmu = x86_get_static_pmu(); 6559 6560 release_arch_pebs_buf_on_cpu(cpu); 6561 intel_cpuc_finish(cpuc); 6562 6563 if (is_hybrid() && cpuc->pmu && cpuc->pmu != pmu) 6564 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 6565 } 6566 6567 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, 6568 struct task_struct *task, bool sched_in) 6569 { 6570 intel_pmu_pebs_sched_task(pmu_ctx, sched_in); 6571 intel_pmu_lbr_sched_task(pmu_ctx, task, sched_in); 6572 } 6573 6574 static int intel_pmu_check_period(struct perf_event *event, u64 value) 6575 { 6576 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 6577 } 6578 6579 static void intel_aux_output_init(void) 6580 { 6581 /* Refer also intel_pmu_aux_output_match() */ 6582 if (x86_pmu.intel_cap.pebs_output_pt_available) 6583 x86_pmu.assign = intel_pmu_assign_event; 6584 } 6585 6586 static int intel_pmu_aux_output_match(struct perf_event *event) 6587 { 6588 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 6589 if (!x86_pmu.intel_cap.pebs_output_pt_available) 6590 return 0; 6591 6592 return is_intel_pt_event(event); 6593 } 6594 6595 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret) 6596 { 6597 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu); 6598 6599 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus); 6600 } 6601 6602 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 6603 6604 PMU_FORMAT_ATTR(offmodule_rsp, "config1:0-63"); 6605 6606 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 6607 6608 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 6609 6610 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63"); 6611 6612 static struct attribute *intel_arch3_formats_attr[] = { 6613 &format_attr_event.attr, 6614 &format_attr_umask.attr, 6615 &format_attr_edge.attr, 6616 &format_attr_pc.attr, 6617 &format_attr_any.attr, 6618 &format_attr_inv.attr, 6619 &format_attr_cmask.attr, 6620 NULL, 6621 }; 6622 6623 static struct attribute *hsw_format_attr[] = { 6624 &format_attr_in_tx.attr, 6625 &format_attr_in_tx_cp.attr, 6626 &format_attr_offcore_rsp.attr, 6627 &format_attr_ldlat.attr, 6628 NULL 6629 }; 6630 6631 static struct attribute *nhm_format_attr[] = { 6632 &format_attr_offcore_rsp.attr, 6633 &format_attr_ldlat.attr, 6634 NULL 6635 }; 6636 6637 static struct attribute *slm_format_attr[] = { 6638 &format_attr_offcore_rsp.attr, 6639 NULL 6640 }; 6641 6642 static struct attribute *cmt_format_attr[] = { 6643 &format_attr_offcore_rsp.attr, 6644 &format_attr_ldlat.attr, 6645 &format_attr_snoop_rsp.attr, 6646 NULL 6647 }; 6648 6649 static struct attribute *skl_format_attr[] = { 6650 &format_attr_frontend.attr, 6651 NULL, 6652 }; 6653 6654 static struct attribute *pnc_format_attr_rtm[] = { 6655 &format_attr_in_tx.attr, 6656 &format_attr_in_tx_cp.attr, 6657 &format_attr_offmodule_rsp.attr, 6658 &format_attr_ldlat.attr, 6659 NULL 6660 }; 6661 6662 static struct attribute *pnc_format_attr[] = { 6663 &format_attr_offmodule_rsp.attr, 6664 &format_attr_ldlat.attr, 6665 NULL 6666 }; 6667 6668 static __initconst const struct x86_pmu core_pmu = { 6669 .name = "core", 6670 .handle_irq = x86_pmu_handle_irq, 6671 .disable_all = x86_pmu_disable_all, 6672 .enable_all = core_pmu_enable_all, 6673 .enable = core_pmu_enable_event, 6674 .disable = x86_pmu_disable_event, 6675 .hw_config = core_pmu_hw_config, 6676 .schedule_events = x86_schedule_events, 6677 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 6678 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 6679 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 6680 .event_map = intel_pmu_event_map, 6681 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 6682 .apic = 1, 6683 .large_pebs_flags = LARGE_PEBS_FLAGS, 6684 6685 /* 6686 * Intel PMCs cannot be accessed sanely above 32-bit width, 6687 * so we install an artificial 1<<31 period regardless of 6688 * the generic event period: 6689 */ 6690 .max_period = (1ULL<<31) - 1, 6691 .get_event_constraints = intel_get_event_constraints, 6692 .put_event_constraints = intel_put_event_constraints, 6693 .event_constraints = intel_core_event_constraints, 6694 .guest_get_msrs = core_guest_get_msrs, 6695 .format_attrs = intel_arch_formats_attr, 6696 .events_sysfs_show = intel_event_sysfs_show, 6697 6698 /* 6699 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 6700 * together with PMU version 1 and thus be using core_pmu with 6701 * shared_regs. We need following callbacks here to allocate 6702 * it properly. 6703 */ 6704 .cpu_prepare = intel_pmu_cpu_prepare, 6705 .cpu_starting = intel_pmu_cpu_starting, 6706 .cpu_dying = intel_pmu_cpu_dying, 6707 .cpu_dead = intel_pmu_cpu_dead, 6708 6709 .check_period = intel_pmu_check_period, 6710 6711 .lbr_reset = intel_pmu_lbr_reset_64, 6712 .lbr_read = intel_pmu_lbr_read_64, 6713 .lbr_save = intel_pmu_lbr_save, 6714 .lbr_restore = intel_pmu_lbr_restore, 6715 }; 6716 6717 static __initconst const struct x86_pmu intel_pmu = { 6718 .name = "Intel", 6719 .handle_irq = intel_pmu_handle_irq, 6720 .disable_all = intel_pmu_disable_all, 6721 .enable_all = intel_pmu_enable_all, 6722 .enable = intel_pmu_enable_event, 6723 .disable = intel_pmu_disable_event, 6724 .add = intel_pmu_add_event, 6725 .del = intel_pmu_del_event, 6726 .read = intel_pmu_read_event, 6727 .set_period = intel_pmu_set_period, 6728 .update = intel_pmu_update, 6729 .hw_config = intel_pmu_hw_config, 6730 .schedule_events = x86_schedule_events, 6731 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 6732 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 6733 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 6734 .event_map = intel_pmu_event_map, 6735 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 6736 .apic = 1, 6737 .large_pebs_flags = LARGE_PEBS_FLAGS, 6738 /* 6739 * Intel PMCs cannot be accessed sanely above 32 bit width, 6740 * so we install an artificial 1<<31 period regardless of 6741 * the generic event period: 6742 */ 6743 .max_period = (1ULL << 31) - 1, 6744 .get_event_constraints = intel_get_event_constraints, 6745 .put_event_constraints = intel_put_event_constraints, 6746 .pebs_aliases = intel_pebs_aliases_core2, 6747 6748 .format_attrs = intel_arch3_formats_attr, 6749 .events_sysfs_show = intel_event_sysfs_show, 6750 6751 .cpu_prepare = intel_pmu_cpu_prepare, 6752 .cpu_starting = intel_pmu_cpu_starting, 6753 .cpu_dying = intel_pmu_cpu_dying, 6754 .cpu_dead = intel_pmu_cpu_dead, 6755 6756 .guest_get_msrs = intel_guest_get_msrs, 6757 .sched_task = intel_pmu_sched_task, 6758 6759 .check_period = intel_pmu_check_period, 6760 6761 .aux_output_match = intel_pmu_aux_output_match, 6762 6763 .lbr_reset = intel_pmu_lbr_reset_64, 6764 .lbr_read = intel_pmu_lbr_read_64, 6765 .lbr_save = intel_pmu_lbr_save, 6766 .lbr_restore = intel_pmu_lbr_restore, 6767 6768 /* 6769 * SMM has access to all 4 rings and while traditionally SMM code only 6770 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM. 6771 * 6772 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction 6773 * between SMM or not, this results in what should be pure userspace 6774 * counters including SMM data. 6775 * 6776 * This is a clear privilege issue, therefore globally disable 6777 * counting SMM by default. 6778 */ 6779 .attr_freeze_on_smi = 1, 6780 }; 6781 6782 static __init void intel_clovertown_quirk(void) 6783 { 6784 /* 6785 * PEBS is unreliable due to: 6786 * 6787 * AJ67 - PEBS may experience CPL leaks 6788 * AJ68 - PEBS PMI may be delayed by one event 6789 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 6790 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 6791 * 6792 * AJ67 could be worked around by restricting the OS/USR flags. 6793 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 6794 * 6795 * AJ106 could possibly be worked around by not allowing LBR 6796 * usage from PEBS, including the fixup. 6797 * AJ68 could possibly be worked around by always programming 6798 * a pebs_event_reset[0] value and coping with the lost events. 6799 * 6800 * But taken together it might just make sense to not enable PEBS on 6801 * these chips. 6802 */ 6803 pr_warn("PEBS disabled due to CPU errata\n"); 6804 x86_pmu.ds_pebs = 0; 6805 x86_pmu.pebs_constraints = NULL; 6806 } 6807 6808 static const struct x86_cpu_id isolation_ucodes[] = { 6809 X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f), 6810 X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e), 6811 X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015), 6812 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037), 6813 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a), 6814 X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023), 6815 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014), 6816 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010), 6817 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009), 6818 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009), 6819 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002), 6820 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014), 6821 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021), 6822 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000), 6823 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000), 6824 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c), 6825 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c), 6826 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e), 6827 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e), 6828 {} 6829 }; 6830 6831 static void intel_check_pebs_isolation(void) 6832 { 6833 x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes); 6834 } 6835 6836 static __init void intel_pebs_isolation_quirk(void) 6837 { 6838 WARN_ON_ONCE(x86_pmu.check_microcode); 6839 x86_pmu.check_microcode = intel_check_pebs_isolation; 6840 intel_check_pebs_isolation(); 6841 } 6842 6843 static const struct x86_cpu_id pebs_ucodes[] = { 6844 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028), 6845 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618), 6846 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c), 6847 {} 6848 }; 6849 6850 static bool intel_snb_pebs_broken(void) 6851 { 6852 return !x86_match_min_microcode_rev(pebs_ucodes); 6853 } 6854 6855 static void intel_snb_check_microcode(void) 6856 { 6857 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 6858 return; 6859 6860 /* 6861 * Serialized by the microcode lock.. 6862 */ 6863 if (x86_pmu.pebs_broken) { 6864 pr_info("PEBS enabled due to microcode update\n"); 6865 x86_pmu.pebs_broken = 0; 6866 } else { 6867 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 6868 x86_pmu.pebs_broken = 1; 6869 } 6870 } 6871 6872 static bool is_lbr_from(unsigned long msr) 6873 { 6874 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 6875 6876 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 6877 } 6878 6879 /* 6880 * Under certain circumstances, access certain MSR may cause #GP. 6881 * The function tests if the input MSR can be safely accessed. 6882 */ 6883 static bool check_msr(unsigned long msr, u64 mask) 6884 { 6885 u64 val_old, val_new, val_tmp; 6886 6887 /* 6888 * Disable the check for real HW, so we don't 6889 * mess with potentially enabled registers: 6890 */ 6891 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 6892 return true; 6893 6894 /* 6895 * Read the current value, change it and read it back to see if it 6896 * matches, this is needed to detect certain hardware emulators 6897 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 6898 */ 6899 if (rdmsrq_safe(msr, &val_old)) 6900 return false; 6901 6902 /* 6903 * Only change the bits which can be updated by wrmsrq. 6904 */ 6905 val_tmp = val_old ^ mask; 6906 6907 if (is_lbr_from(msr)) 6908 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 6909 6910 if (wrmsrq_safe(msr, val_tmp) || 6911 rdmsrq_safe(msr, &val_new)) 6912 return false; 6913 6914 /* 6915 * Quirk only affects validation in wrmsr(), so wrmsrq()'s value 6916 * should equal rdmsrq()'s even with the quirk. 6917 */ 6918 if (val_new != val_tmp) 6919 return false; 6920 6921 if (is_lbr_from(msr)) 6922 val_old = lbr_from_signext_quirk_wr(val_old); 6923 6924 /* Here it's sure that the MSR can be safely accessed. 6925 * Restore the old value and return. 6926 */ 6927 wrmsrq(msr, val_old); 6928 6929 return true; 6930 } 6931 6932 static __init void intel_sandybridge_quirk(void) 6933 { 6934 x86_pmu.check_microcode = intel_snb_check_microcode; 6935 cpus_read_lock(); 6936 intel_snb_check_microcode(); 6937 cpus_read_unlock(); 6938 } 6939 6940 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 6941 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 6942 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 6943 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 6944 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 6945 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 6946 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 6947 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 6948 }; 6949 6950 static __init void intel_arch_events_quirk(void) 6951 { 6952 int bit; 6953 6954 /* disable event that reported as not present by cpuid */ 6955 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 6956 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 6957 pr_warn("CPUID marked event: \'%s\' unavailable\n", 6958 intel_arch_events_map[bit].name); 6959 } 6960 } 6961 6962 static __init void intel_nehalem_quirk(void) 6963 { 6964 union cpuid10_ebx ebx; 6965 6966 ebx.full = x86_pmu.events_maskl; 6967 if (ebx.split.no_branch_misses_retired) { 6968 /* 6969 * Erratum AAJ80 detected, we work it around by using 6970 * the BR_MISP_EXEC.ANY event. This will over-count 6971 * branch-misses, but it's still much better than the 6972 * architectural event which is often completely bogus: 6973 */ 6974 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 6975 ebx.split.no_branch_misses_retired = 0; 6976 x86_pmu.events_maskl = ebx.full; 6977 pr_info("CPU erratum AAJ80 worked around\n"); 6978 } 6979 } 6980 6981 /* 6982 * enable software workaround for errata: 6983 * SNB: BJ122 6984 * IVB: BV98 6985 * HSW: HSD29 6986 * 6987 * Only needed when HT is enabled. However detecting 6988 * if HT is enabled is difficult (model specific). So instead, 6989 * we enable the workaround in the early boot, and verify if 6990 * it is needed in a later initcall phase once we have valid 6991 * topology information to check if HT is actually enabled 6992 */ 6993 static __init void intel_ht_bug(void) 6994 { 6995 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 6996 6997 x86_pmu.start_scheduling = intel_start_scheduling; 6998 x86_pmu.commit_scheduling = intel_commit_scheduling; 6999 x86_pmu.stop_scheduling = intel_stop_scheduling; 7000 } 7001 7002 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 7003 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 7004 7005 /* Haswell special events */ 7006 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 7007 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 7008 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 7009 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 7010 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 7011 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 7012 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 7013 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 7014 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 7015 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 7016 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 7017 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 7018 7019 static struct attribute *hsw_events_attrs[] = { 7020 EVENT_PTR(td_slots_issued), 7021 EVENT_PTR(td_slots_retired), 7022 EVENT_PTR(td_fetch_bubbles), 7023 EVENT_PTR(td_total_slots), 7024 EVENT_PTR(td_total_slots_scale), 7025 EVENT_PTR(td_recovery_bubbles), 7026 EVENT_PTR(td_recovery_bubbles_scale), 7027 NULL 7028 }; 7029 7030 static struct attribute *hsw_mem_events_attrs[] = { 7031 EVENT_PTR(mem_ld_hsw), 7032 EVENT_PTR(mem_st_hsw), 7033 NULL, 7034 }; 7035 7036 static struct attribute *hsw_tsx_events_attrs[] = { 7037 EVENT_PTR(tx_start), 7038 EVENT_PTR(tx_commit), 7039 EVENT_PTR(tx_abort), 7040 EVENT_PTR(tx_capacity), 7041 EVENT_PTR(tx_conflict), 7042 EVENT_PTR(el_start), 7043 EVENT_PTR(el_commit), 7044 EVENT_PTR(el_abort), 7045 EVENT_PTR(el_capacity), 7046 EVENT_PTR(el_conflict), 7047 EVENT_PTR(cycles_t), 7048 EVENT_PTR(cycles_ct), 7049 NULL 7050 }; 7051 7052 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 7053 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 7054 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 7055 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 7056 7057 static struct attribute *icl_events_attrs[] = { 7058 EVENT_PTR(mem_ld_hsw), 7059 EVENT_PTR(mem_st_hsw), 7060 NULL, 7061 }; 7062 7063 static struct attribute *icl_td_events_attrs[] = { 7064 EVENT_PTR(slots), 7065 EVENT_PTR(td_retiring), 7066 EVENT_PTR(td_bad_spec), 7067 EVENT_PTR(td_fe_bound), 7068 EVENT_PTR(td_be_bound), 7069 NULL, 7070 }; 7071 7072 static struct attribute *icl_tsx_events_attrs[] = { 7073 EVENT_PTR(tx_start), 7074 EVENT_PTR(tx_abort), 7075 EVENT_PTR(tx_commit), 7076 EVENT_PTR(tx_capacity_read), 7077 EVENT_PTR(tx_capacity_write), 7078 EVENT_PTR(tx_conflict), 7079 EVENT_PTR(el_start), 7080 EVENT_PTR(el_abort), 7081 EVENT_PTR(el_commit), 7082 EVENT_PTR(el_capacity_read), 7083 EVENT_PTR(el_capacity_write), 7084 EVENT_PTR(el_conflict), 7085 EVENT_PTR(cycles_t), 7086 EVENT_PTR(cycles_ct), 7087 NULL, 7088 }; 7089 7090 7091 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 7092 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 7093 7094 static struct attribute *glc_events_attrs[] = { 7095 EVENT_PTR(mem_ld_hsw), 7096 EVENT_PTR(mem_st_spr), 7097 EVENT_PTR(mem_ld_aux), 7098 NULL, 7099 }; 7100 7101 static struct attribute *glc_td_events_attrs[] = { 7102 EVENT_PTR(slots), 7103 EVENT_PTR(td_retiring), 7104 EVENT_PTR(td_bad_spec), 7105 EVENT_PTR(td_fe_bound), 7106 EVENT_PTR(td_be_bound), 7107 EVENT_PTR(td_heavy_ops), 7108 EVENT_PTR(td_br_mispredict), 7109 EVENT_PTR(td_fetch_lat), 7110 EVENT_PTR(td_mem_bound), 7111 NULL, 7112 }; 7113 7114 static struct attribute *glc_tsx_events_attrs[] = { 7115 EVENT_PTR(tx_start), 7116 EVENT_PTR(tx_abort), 7117 EVENT_PTR(tx_commit), 7118 EVENT_PTR(tx_capacity_read), 7119 EVENT_PTR(tx_capacity_write), 7120 EVENT_PTR(tx_conflict), 7121 EVENT_PTR(cycles_t), 7122 EVENT_PTR(cycles_ct), 7123 NULL, 7124 }; 7125 7126 static ssize_t freeze_on_smi_show(struct device *cdev, 7127 struct device_attribute *attr, 7128 char *buf) 7129 { 7130 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 7131 } 7132 7133 static DEFINE_MUTEX(freeze_on_smi_mutex); 7134 7135 static ssize_t freeze_on_smi_store(struct device *cdev, 7136 struct device_attribute *attr, 7137 const char *buf, size_t count) 7138 { 7139 unsigned long val; 7140 ssize_t ret; 7141 7142 ret = kstrtoul(buf, 0, &val); 7143 if (ret) 7144 return ret; 7145 7146 if (val > 1) 7147 return -EINVAL; 7148 7149 mutex_lock(&freeze_on_smi_mutex); 7150 7151 if (x86_pmu.attr_freeze_on_smi == val) 7152 goto done; 7153 7154 x86_pmu.attr_freeze_on_smi = val; 7155 7156 cpus_read_lock(); 7157 on_each_cpu(flip_smm_bit, &val, 1); 7158 cpus_read_unlock(); 7159 done: 7160 mutex_unlock(&freeze_on_smi_mutex); 7161 7162 return count; 7163 } 7164 7165 static void update_tfa_sched(void *ignored) 7166 { 7167 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 7168 7169 /* 7170 * check if PMC3 is used 7171 * and if so force schedule out for all event types all contexts 7172 */ 7173 if (test_bit(3, cpuc->active_mask)) 7174 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 7175 } 7176 7177 static ssize_t show_sysctl_tfa(struct device *cdev, 7178 struct device_attribute *attr, 7179 char *buf) 7180 { 7181 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 7182 } 7183 7184 static ssize_t set_sysctl_tfa(struct device *cdev, 7185 struct device_attribute *attr, 7186 const char *buf, size_t count) 7187 { 7188 bool val; 7189 ssize_t ret; 7190 7191 ret = kstrtobool(buf, &val); 7192 if (ret) 7193 return ret; 7194 7195 /* no change */ 7196 if (val == allow_tsx_force_abort) 7197 return count; 7198 7199 allow_tsx_force_abort = val; 7200 7201 cpus_read_lock(); 7202 on_each_cpu(update_tfa_sched, NULL, 1); 7203 cpus_read_unlock(); 7204 7205 return count; 7206 } 7207 7208 7209 static DEVICE_ATTR_RW(freeze_on_smi); 7210 7211 static ssize_t branches_show(struct device *cdev, 7212 struct device_attribute *attr, 7213 char *buf) 7214 { 7215 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 7216 } 7217 7218 static DEVICE_ATTR_RO(branches); 7219 7220 static ssize_t branch_counter_nr_show(struct device *cdev, 7221 struct device_attribute *attr, 7222 char *buf) 7223 { 7224 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters)); 7225 } 7226 7227 static DEVICE_ATTR_RO(branch_counter_nr); 7228 7229 static ssize_t branch_counter_width_show(struct device *cdev, 7230 struct device_attribute *attr, 7231 char *buf) 7232 { 7233 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS); 7234 } 7235 7236 static DEVICE_ATTR_RO(branch_counter_width); 7237 7238 static struct attribute *lbr_attrs[] = { 7239 &dev_attr_branches.attr, 7240 &dev_attr_branch_counter_nr.attr, 7241 &dev_attr_branch_counter_width.attr, 7242 NULL 7243 }; 7244 7245 static umode_t 7246 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 7247 { 7248 /* branches */ 7249 if (i == 0) 7250 return x86_pmu.lbr_nr ? attr->mode : 0; 7251 7252 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0; 7253 } 7254 7255 static char pmu_name_str[30]; 7256 7257 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str); 7258 7259 static struct attribute *intel_pmu_caps_attrs[] = { 7260 &dev_attr_pmu_name.attr.attr, 7261 NULL 7262 }; 7263 7264 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 7265 show_sysctl_tfa, 7266 set_sysctl_tfa); 7267 7268 static struct attribute *intel_pmu_attrs[] = { 7269 &dev_attr_freeze_on_smi.attr, 7270 &dev_attr_allow_tsx_force_abort.attr, 7271 NULL, 7272 }; 7273 7274 static umode_t 7275 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 7276 { 7277 if (attr == &dev_attr_allow_tsx_force_abort.attr) 7278 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 7279 7280 return attr->mode; 7281 } 7282 7283 static umode_t 7284 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 7285 { 7286 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 7287 } 7288 7289 static umode_t 7290 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 7291 { 7292 return intel_pmu_has_pebs() ? attr->mode : 0; 7293 } 7294 7295 static umode_t 7296 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i) 7297 { 7298 if (attr == &event_attr_mem_ld_aux.attr.attr) 7299 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0; 7300 7301 return pebs_is_visible(kobj, attr, i); 7302 } 7303 7304 static umode_t 7305 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 7306 { 7307 return x86_pmu.version >= 2 ? attr->mode : 0; 7308 } 7309 7310 static umode_t 7311 td_is_visible(struct kobject *kobj, struct attribute *attr, int i) 7312 { 7313 /* 7314 * Hide the perf metrics topdown events 7315 * if the feature is not enumerated. 7316 */ 7317 if (x86_pmu.num_topdown_events) 7318 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0; 7319 7320 return attr->mode; 7321 } 7322 7323 PMU_FORMAT_ATTR(acr_mask, "config2:0-63"); 7324 7325 static struct attribute *format_acr_attrs[] = { 7326 &format_attr_acr_mask.attr, 7327 NULL 7328 }; 7329 7330 static umode_t 7331 acr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 7332 { 7333 struct device *dev = kobj_to_dev(kobj); 7334 7335 return intel_pmu_has_acr(dev_get_drvdata(dev)) ? attr->mode : 0; 7336 } 7337 7338 static struct attribute_group group_events_td = { 7339 .name = "events", 7340 .is_visible = td_is_visible, 7341 }; 7342 7343 static struct attribute_group group_events_mem = { 7344 .name = "events", 7345 .is_visible = mem_is_visible, 7346 }; 7347 7348 static struct attribute_group group_events_tsx = { 7349 .name = "events", 7350 .is_visible = tsx_is_visible, 7351 }; 7352 7353 static struct attribute_group group_caps_gen = { 7354 .name = "caps", 7355 .attrs = intel_pmu_caps_attrs, 7356 }; 7357 7358 static struct attribute_group group_caps_lbr = { 7359 .name = "caps", 7360 .attrs = lbr_attrs, 7361 .is_visible = lbr_is_visible, 7362 }; 7363 7364 static struct attribute_group group_format_extra = { 7365 .name = "format", 7366 .is_visible = exra_is_visible, 7367 }; 7368 7369 static struct attribute_group group_format_extra_skl = { 7370 .name = "format", 7371 .is_visible = exra_is_visible, 7372 }; 7373 7374 static struct attribute_group group_format_evtsel_ext = { 7375 .name = "format", 7376 .attrs = format_evtsel_ext_attrs, 7377 .is_visible = evtsel_ext_is_visible, 7378 }; 7379 7380 static struct attribute_group group_format_acr = { 7381 .name = "format", 7382 .attrs = format_acr_attrs, 7383 .is_visible = acr_is_visible, 7384 }; 7385 7386 static struct attribute_group group_default = { 7387 .attrs = intel_pmu_attrs, 7388 .is_visible = default_is_visible, 7389 }; 7390 7391 static const struct attribute_group *attr_update[] = { 7392 &group_events_td, 7393 &group_events_mem, 7394 &group_events_tsx, 7395 &group_caps_gen, 7396 &group_caps_lbr, 7397 &group_format_extra, 7398 &group_format_extra_skl, 7399 &group_format_evtsel_ext, 7400 &group_format_acr, 7401 &group_default, 7402 NULL, 7403 }; 7404 7405 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 7406 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 7407 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 7408 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 7409 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 7410 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 7411 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 7412 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 7413 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 7414 7415 static struct attribute *adl_hybrid_events_attrs[] = { 7416 EVENT_PTR(slots_adl), 7417 EVENT_PTR(td_retiring_adl), 7418 EVENT_PTR(td_bad_spec_adl), 7419 EVENT_PTR(td_fe_bound_adl), 7420 EVENT_PTR(td_be_bound_adl), 7421 EVENT_PTR(td_heavy_ops_adl), 7422 EVENT_PTR(td_br_mis_adl), 7423 EVENT_PTR(td_fetch_lat_adl), 7424 EVENT_PTR(td_mem_bound_adl), 7425 NULL, 7426 }; 7427 7428 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small); 7429 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small); 7430 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small); 7431 7432 static struct attribute *lnl_hybrid_events_attrs[] = { 7433 EVENT_PTR(slots_adl), 7434 EVENT_PTR(td_retiring_lnl), 7435 EVENT_PTR(td_bad_spec_adl), 7436 EVENT_PTR(td_fe_bound_lnl), 7437 EVENT_PTR(td_be_bound_lnl), 7438 EVENT_PTR(td_heavy_ops_adl), 7439 EVENT_PTR(td_br_mis_adl), 7440 EVENT_PTR(td_fetch_lat_adl), 7441 EVENT_PTR(td_mem_bound_adl), 7442 NULL 7443 }; 7444 7445 /* The event string must be in PMU IDX order. */ 7446 EVENT_ATTR_STR_HYBRID(topdown-retiring, 7447 td_retiring_arl_h, 7448 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0", 7449 hybrid_big_small_tiny); 7450 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, 7451 td_bad_spec_arl_h, 7452 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0", 7453 hybrid_big_small_tiny); 7454 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, 7455 td_fe_bound_arl_h, 7456 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0", 7457 hybrid_big_small_tiny); 7458 EVENT_ATTR_STR_HYBRID(topdown-be-bound, 7459 td_be_bound_arl_h, 7460 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0", 7461 hybrid_big_small_tiny); 7462 7463 static struct attribute *arl_h_hybrid_events_attrs[] = { 7464 EVENT_PTR(slots_adl), 7465 EVENT_PTR(td_retiring_arl_h), 7466 EVENT_PTR(td_bad_spec_arl_h), 7467 EVENT_PTR(td_fe_bound_arl_h), 7468 EVENT_PTR(td_be_bound_arl_h), 7469 EVENT_PTR(td_heavy_ops_adl), 7470 EVENT_PTR(td_br_mis_adl), 7471 EVENT_PTR(td_fetch_lat_adl), 7472 EVENT_PTR(td_mem_bound_adl), 7473 NULL, 7474 }; 7475 7476 /* Must be in IDX order */ 7477 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 7478 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 7479 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 7480 7481 static struct attribute *adl_hybrid_mem_attrs[] = { 7482 EVENT_PTR(mem_ld_adl), 7483 EVENT_PTR(mem_st_adl), 7484 EVENT_PTR(mem_ld_aux_adl), 7485 NULL, 7486 }; 7487 7488 static struct attribute *mtl_hybrid_mem_attrs[] = { 7489 EVENT_PTR(mem_ld_adl), 7490 EVENT_PTR(mem_st_adl), 7491 NULL 7492 }; 7493 7494 EVENT_ATTR_STR_HYBRID(mem-loads, 7495 mem_ld_arl_h, 7496 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3", 7497 hybrid_big_small_tiny); 7498 EVENT_ATTR_STR_HYBRID(mem-stores, 7499 mem_st_arl_h, 7500 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6", 7501 hybrid_big_small_tiny); 7502 7503 static struct attribute *arl_h_hybrid_mem_attrs[] = { 7504 EVENT_PTR(mem_ld_arl_h), 7505 EVENT_PTR(mem_st_arl_h), 7506 NULL, 7507 }; 7508 7509 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 7510 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 7511 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 7512 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 7513 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 7514 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 7515 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 7516 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 7517 7518 static struct attribute *adl_hybrid_tsx_attrs[] = { 7519 EVENT_PTR(tx_start_adl), 7520 EVENT_PTR(tx_abort_adl), 7521 EVENT_PTR(tx_commit_adl), 7522 EVENT_PTR(tx_capacity_read_adl), 7523 EVENT_PTR(tx_capacity_write_adl), 7524 EVENT_PTR(tx_conflict_adl), 7525 EVENT_PTR(cycles_t_adl), 7526 EVENT_PTR(cycles_ct_adl), 7527 NULL, 7528 }; 7529 7530 FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 7531 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 7532 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny); 7533 FORMAT_ATTR_HYBRID(offmodule_rsp, hybrid_big_small_tiny); 7534 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny); 7535 FORMAT_ATTR_HYBRID(frontend, hybrid_big); 7536 7537 #define ADL_HYBRID_RTM_FORMAT_ATTR \ 7538 FORMAT_HYBRID_PTR(in_tx), \ 7539 FORMAT_HYBRID_PTR(in_tx_cp) 7540 7541 #define ADL_HYBRID_FORMAT_ATTR \ 7542 FORMAT_HYBRID_PTR(offcore_rsp), \ 7543 FORMAT_HYBRID_PTR(ldlat), \ 7544 FORMAT_HYBRID_PTR(frontend) 7545 7546 static struct attribute *adl_hybrid_extra_attr_rtm[] = { 7547 ADL_HYBRID_RTM_FORMAT_ATTR, 7548 ADL_HYBRID_FORMAT_ATTR, 7549 NULL 7550 }; 7551 7552 static struct attribute *adl_hybrid_extra_attr[] = { 7553 ADL_HYBRID_FORMAT_ATTR, 7554 NULL 7555 }; 7556 7557 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny); 7558 7559 static struct attribute *mtl_hybrid_extra_attr_rtm[] = { 7560 ADL_HYBRID_RTM_FORMAT_ATTR, 7561 ADL_HYBRID_FORMAT_ATTR, 7562 FORMAT_HYBRID_PTR(snoop_rsp), 7563 NULL 7564 }; 7565 7566 static struct attribute *mtl_hybrid_extra_attr[] = { 7567 ADL_HYBRID_FORMAT_ATTR, 7568 FORMAT_HYBRID_PTR(snoop_rsp), 7569 NULL 7570 }; 7571 7572 static struct attribute *nvl_hybrid_extra_attr_rtm[] = { 7573 ADL_HYBRID_RTM_FORMAT_ATTR, 7574 FORMAT_HYBRID_PTR(offmodule_rsp), 7575 FORMAT_HYBRID_PTR(ldlat), 7576 FORMAT_HYBRID_PTR(frontend), 7577 FORMAT_HYBRID_PTR(snoop_rsp), 7578 NULL 7579 }; 7580 7581 static struct attribute *nvl_hybrid_extra_attr[] = { 7582 FORMAT_HYBRID_PTR(offmodule_rsp), 7583 FORMAT_HYBRID_PTR(ldlat), 7584 FORMAT_HYBRID_PTR(frontend), 7585 FORMAT_HYBRID_PTR(snoop_rsp), 7586 NULL 7587 }; 7588 7589 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 7590 { 7591 struct device *dev = kobj_to_dev(kobj); 7592 struct x86_hybrid_pmu *pmu = 7593 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 7594 struct perf_pmu_events_hybrid_attr *pmu_attr = 7595 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 7596 7597 return pmu->pmu_type & pmu_attr->pmu_type; 7598 } 7599 7600 static umode_t hybrid_events_is_visible(struct kobject *kobj, 7601 struct attribute *attr, int i) 7602 { 7603 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 7604 } 7605 7606 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 7607 { 7608 int cpu = cpumask_first(&pmu->supported_cpus); 7609 7610 return (cpu >= nr_cpu_ids) ? -1 : cpu; 7611 } 7612 7613 static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 7614 struct attribute *attr, int i) 7615 { 7616 struct device *dev = kobj_to_dev(kobj); 7617 struct x86_hybrid_pmu *pmu = 7618 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 7619 int cpu = hybrid_find_supported_cpu(pmu); 7620 7621 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 7622 } 7623 7624 static umode_t hybrid_format_is_visible(struct kobject *kobj, 7625 struct attribute *attr, int i) 7626 { 7627 struct device *dev = kobj_to_dev(kobj); 7628 struct x86_hybrid_pmu *pmu = 7629 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 7630 struct perf_pmu_format_hybrid_attr *pmu_attr = 7631 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 7632 int cpu = hybrid_find_supported_cpu(pmu); 7633 7634 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0; 7635 } 7636 7637 static umode_t hybrid_td_is_visible(struct kobject *kobj, 7638 struct attribute *attr, int i) 7639 { 7640 struct device *dev = kobj_to_dev(kobj); 7641 struct x86_hybrid_pmu *pmu = 7642 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 7643 7644 if (!is_attr_for_this_pmu(kobj, attr)) 7645 return 0; 7646 7647 7648 /* Only the big core supports perf metrics */ 7649 if (pmu->pmu_type == hybrid_big) 7650 return pmu->intel_cap.perf_metrics ? attr->mode : 0; 7651 7652 return attr->mode; 7653 } 7654 7655 static struct attribute_group hybrid_group_events_td = { 7656 .name = "events", 7657 .is_visible = hybrid_td_is_visible, 7658 }; 7659 7660 static struct attribute_group hybrid_group_events_mem = { 7661 .name = "events", 7662 .is_visible = hybrid_events_is_visible, 7663 }; 7664 7665 static struct attribute_group hybrid_group_events_tsx = { 7666 .name = "events", 7667 .is_visible = hybrid_tsx_is_visible, 7668 }; 7669 7670 static struct attribute_group hybrid_group_format_extra = { 7671 .name = "format", 7672 .is_visible = hybrid_format_is_visible, 7673 }; 7674 7675 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 7676 struct device_attribute *attr, 7677 char *buf) 7678 { 7679 struct x86_hybrid_pmu *pmu = 7680 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 7681 7682 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(&pmu->supported_cpus)); 7683 } 7684 7685 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 7686 static struct attribute *intel_hybrid_cpus_attrs[] = { 7687 &dev_attr_cpus.attr, 7688 NULL, 7689 }; 7690 7691 static struct attribute_group hybrid_group_cpus = { 7692 .attrs = intel_hybrid_cpus_attrs, 7693 }; 7694 7695 static const struct attribute_group *hybrid_attr_update[] = { 7696 &hybrid_group_events_td, 7697 &hybrid_group_events_mem, 7698 &hybrid_group_events_tsx, 7699 &group_caps_gen, 7700 &group_caps_lbr, 7701 &hybrid_group_format_extra, 7702 &group_format_evtsel_ext, 7703 &group_format_acr, 7704 &group_default, 7705 &hybrid_group_cpus, 7706 NULL, 7707 }; 7708 7709 static struct attribute *empty_attrs; 7710 7711 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 7712 u64 cntr_mask, 7713 u64 fixed_cntr_mask, 7714 u64 intel_ctrl) 7715 { 7716 struct event_constraint *c; 7717 7718 if (!event_constraints) 7719 return; 7720 7721 /* 7722 * event on fixed counter2 (REF_CYCLES) only works on this 7723 * counter, so do not extend mask to generic counters 7724 */ 7725 for_each_event_constraint(c, event_constraints) { 7726 /* 7727 * Don't extend the topdown slots and metrics 7728 * events to the generic counters. 7729 */ 7730 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 7731 /* 7732 * Disable topdown slots and metrics events, 7733 * if slots event is not in CPUID. 7734 */ 7735 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 7736 c->idxmsk64 = 0; 7737 c->weight = hweight64(c->idxmsk64); 7738 continue; 7739 } 7740 7741 if (c->cmask == FIXED_EVENT_FLAGS) { 7742 /* Disabled fixed counters which are not in CPUID */ 7743 c->idxmsk64 &= intel_ctrl; 7744 7745 /* 7746 * Don't extend the pseudo-encoding to the 7747 * generic counters 7748 */ 7749 if (!use_fixed_pseudo_encoding(c->code)) 7750 c->idxmsk64 |= cntr_mask; 7751 } 7752 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED); 7753 c->weight = hweight64(c->idxmsk64); 7754 } 7755 } 7756 7757 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 7758 { 7759 struct extra_reg *er; 7760 7761 /* 7762 * Access extra MSR may cause #GP under certain circumstances. 7763 * E.g. KVM doesn't support offcore event 7764 * Check all extra_regs here. 7765 */ 7766 if (!extra_regs) 7767 return; 7768 7769 for (er = extra_regs; er->msr; er++) { 7770 er->extra_msr_access = check_msr(er->msr, 0x11UL); 7771 /* Disable LBR select mapping */ 7772 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 7773 x86_pmu.lbr_sel_map = NULL; 7774 } 7775 } 7776 7777 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel) 7778 { 7779 return MSR_IA32_PMC_V6_STEP * index; 7780 } 7781 7782 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = { 7783 { hybrid_small, "cpu_atom" }, 7784 { hybrid_big, "cpu_core" }, 7785 { hybrid_tiny, "cpu_lowpower" }, 7786 }; 7787 7788 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus) 7789 { 7790 unsigned long pmus_mask = pmus; 7791 struct x86_hybrid_pmu *pmu; 7792 int idx = 0, bit; 7793 7794 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask); 7795 x86_pmu.hybrid_pmu = kzalloc_objs(struct x86_hybrid_pmu, 7796 x86_pmu.num_hybrid_pmus); 7797 if (!x86_pmu.hybrid_pmu) { 7798 x86_pmu.num_hybrid_pmus = 0; 7799 return -ENOMEM; 7800 } 7801 7802 static_branch_enable(&perf_is_hybrid); 7803 x86_pmu.filter = intel_pmu_filter; 7804 7805 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) { 7806 pmu = &x86_pmu.hybrid_pmu[idx++]; 7807 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id; 7808 pmu->name = intel_hybrid_pmu_type_map[bit].name; 7809 7810 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7811 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7812 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 7813 pmu->config_mask = X86_RAW_EVENT_MASK; 7814 pmu->unconstrained = (struct event_constraint) 7815 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 7816 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 7817 7818 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 7819 if (pmu->pmu_type & hybrid_small_tiny) { 7820 pmu->intel_cap.perf_metrics = 0; 7821 pmu->mid_ack = true; 7822 } else if (pmu->pmu_type & hybrid_big) { 7823 pmu->intel_cap.perf_metrics = 1; 7824 pmu->late_ack = true; 7825 } 7826 } 7827 7828 return 0; 7829 } 7830 7831 static __always_inline void intel_pmu_ref_cycles_ext(void) 7832 { 7833 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED))) 7834 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c; 7835 } 7836 7837 static __always_inline void intel_pmu_init_glc(struct pmu *pmu) 7838 { 7839 x86_pmu.late_ack = true; 7840 x86_pmu.limit_period = glc_limit_period; 7841 x86_pmu.pebs_aliases = NULL; 7842 x86_pmu.pebs_prec_dist = true; 7843 x86_pmu.pebs_block = true; 7844 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7845 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7846 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 7847 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 7848 x86_pmu.lbr_pt_coexist = true; 7849 x86_pmu.num_topdown_events = 8; 7850 static_call_update(intel_pmu_update_topdown_event, 7851 &icl_update_topdown_event); 7852 static_call_update(intel_pmu_set_topdown_event_period, 7853 &icl_set_topdown_event_period); 7854 7855 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7856 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7857 hybrid(pmu, event_constraints) = intel_glc_event_constraints; 7858 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints; 7859 7860 intel_pmu_ref_cycles_ext(); 7861 } 7862 7863 static __always_inline void intel_pmu_init_glc_hybrid(struct pmu *pmu) 7864 { 7865 intel_pmu_init_glc(pmu); 7866 7867 /* ADL has different extra MSR values from Server for the L3 or node OCR/OMR events. */ 7868 memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7869 memcpy(hybrid_var(pmu, hw_cache_extra_regs), adl_glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7870 } 7871 7872 static __always_inline void intel_pmu_init_grt(struct pmu *pmu) 7873 { 7874 x86_pmu.mid_ack = true; 7875 x86_pmu.limit_period = glc_limit_period; 7876 x86_pmu.pebs_aliases = NULL; 7877 x86_pmu.pebs_prec_dist = true; 7878 x86_pmu.pebs_block = true; 7879 x86_pmu.lbr_pt_coexist = true; 7880 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7881 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 7882 7883 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7884 memcpy(hybrid_var(pmu, hw_cache_extra_regs), grt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7885 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 7886 hybrid(pmu, event_constraints) = intel_grt_event_constraints; 7887 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints; 7888 hybrid(pmu, extra_regs) = intel_grt_extra_regs; 7889 7890 intel_pmu_ref_cycles_ext(); 7891 } 7892 7893 static __always_inline void intel_pmu_init_cmt(struct pmu *pmu) 7894 { 7895 intel_pmu_init_grt(pmu); 7896 memcpy(hybrid_var(pmu, hw_cache_extra_regs), 7897 cmt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7898 hybrid(pmu, pebs_constraints) = intel_cmt_pebs_event_constraints; 7899 hybrid(pmu, extra_regs) = intel_cmt_extra_regs; 7900 } 7901 7902 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu) 7903 { 7904 intel_pmu_init_glc(pmu); 7905 hybrid(pmu, event_constraints) = intel_lnc_event_constraints; 7906 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints; 7907 hybrid(pmu, extra_regs) = intel_lnc_extra_regs; 7908 7909 memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7910 memcpy(hybrid_var(pmu, hw_cache_extra_regs), lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7911 } 7912 7913 static __always_inline void intel_pmu_init_pnc(struct pmu *pmu) 7914 { 7915 intel_pmu_init_glc(pmu); 7916 x86_pmu.flags &= ~PMU_FL_HAS_RSP_1; 7917 x86_pmu.flags |= PMU_FL_HAS_OMR; 7918 memcpy(hybrid_var(pmu, hw_cache_event_ids), 7919 pnc_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7920 memcpy(hybrid_var(pmu, hw_cache_extra_regs), 7921 pnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7922 hybrid(pmu, event_constraints) = intel_pnc_event_constraints; 7923 hybrid(pmu, pebs_constraints) = intel_pnc_pebs_event_constraints; 7924 hybrid(pmu, extra_regs) = intel_pnc_extra_regs; 7925 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 7926 } 7927 7928 static __always_inline void intel_pmu_init_cyc(struct pmu *pmu) 7929 { 7930 intel_pmu_init_pnc(pmu); 7931 memcpy(hybrid_var(pmu, hw_cache_extra_regs), 7932 cyc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7933 } 7934 7935 static __always_inline void intel_pmu_init_skt(struct pmu *pmu) 7936 { 7937 intel_pmu_init_cmt(pmu); 7938 hybrid(pmu, event_constraints) = intel_skt_event_constraints; 7939 memcpy(hybrid_var(pmu, hw_cache_extra_regs), 7940 skt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7941 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 7942 } 7943 7944 /* Hybrid client variant. */ 7945 static __always_inline void intel_pmu_init_dkt_hybrid(struct pmu *pmu) 7946 { 7947 intel_pmu_init_skt(pmu); 7948 hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints; 7949 } 7950 7951 /* 7952 * Darkmont is used by the CWF and PTL E-cores, but their L3 OCR 7953 * events require different extra MSR values. Keep a separate init 7954 * function for the non-hybrid server variant. 7955 */ 7956 static __always_inline void intel_pmu_init_dkt(struct pmu *pmu) 7957 { 7958 intel_pmu_init_dkt_hybrid(pmu); 7959 memcpy(hybrid_var(pmu, hw_cache_extra_regs), 7960 dkt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7961 } 7962 7963 static __always_inline void intel_pmu_init_arw(struct pmu *pmu) 7964 { 7965 intel_pmu_init_grt(pmu); 7966 x86_pmu.flags &= ~PMU_FL_HAS_RSP_1; 7967 x86_pmu.flags |= PMU_FL_HAS_OMR; 7968 memcpy(hybrid_var(pmu, hw_cache_extra_regs), 7969 arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7970 hybrid(pmu, event_constraints) = intel_arw_event_constraints; 7971 hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints; 7972 hybrid(pmu, extra_regs) = intel_arw_extra_regs; 7973 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 7974 } 7975 7976 __init int intel_pmu_init(void) 7977 { 7978 struct attribute **extra_skl_attr = &empty_attrs; 7979 struct attribute **extra_attr = &empty_attrs; 7980 struct attribute **td_attr = &empty_attrs; 7981 struct attribute **mem_attr = &empty_attrs; 7982 struct attribute **tsx_attr = &empty_attrs; 7983 struct x86_hybrid_pmu *pmu; 7984 unsigned int fixed_mask; 7985 union cpuid10_edx edx; 7986 union cpuid10_eax eax; 7987 union cpuid10_ebx ebx; 7988 int version, i, ret; 7989 bool pmem = false; 7990 char *name; 7991 7992 /* Architectural Perfmon was introduced starting with Core "Yonah" */ 7993 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 7994 switch (boot_cpu_data.x86) { 7995 case 6: 7996 if (boot_cpu_data.x86_vfm < INTEL_CORE_YONAH) 7997 return p6_pmu_init(); 7998 break; 7999 case 11: 8000 return knc_pmu_init(); 8001 case 15: 8002 return p4_pmu_init(); 8003 } 8004 8005 pr_cont("unsupported CPU family %d model %d ", 8006 boot_cpu_data.x86, boot_cpu_data.x86_model); 8007 return -ENODEV; 8008 } 8009 8010 /* 8011 * Check whether the Architectural PerfMon supports 8012 * Branch Misses Retired hw_event or not. 8013 */ 8014 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 8015 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 8016 return -ENODEV; 8017 8018 version = eax.split.version_id; 8019 if (version < 2) 8020 x86_pmu = core_pmu; 8021 else 8022 x86_pmu = intel_pmu; 8023 8024 x86_pmu.version = version; 8025 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0); 8026 x86_pmu.cntval_bits = eax.split.bit_width; 8027 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 8028 8029 x86_pmu.events_maskl = ebx.full; 8030 x86_pmu.events_mask_len = eax.split.mask_length; 8031 8032 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64); 8033 x86_pmu.pebs_capable = PEBS_COUNTER_MASK; 8034 x86_pmu.config_mask = X86_RAW_EVENT_MASK; 8035 8036 /* 8037 * Quirk: v2 perfmon does not report fixed-purpose events, so 8038 * assume at least 3 events, when not running in a hypervisor: 8039 */ 8040 if (version > 1 && version < 5) { 8041 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 8042 8043 x86_pmu.fixed_cntr_mask64 = 8044 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0); 8045 } else if (version >= 5) 8046 x86_pmu.fixed_cntr_mask64 = fixed_mask; 8047 8048 if (boot_cpu_has(X86_FEATURE_PDCM)) { 8049 u64 capabilities; 8050 8051 rdmsrq(MSR_IA32_PERF_CAPABILITIES, capabilities); 8052 x86_pmu.intel_cap.capabilities = capabilities; 8053 } 8054 8055 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 8056 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 8057 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 8058 } 8059 8060 intel_pebs_init(); 8061 8062 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 8063 8064 /* The perf side of core PMU is ready to support the mediated vPMU. */ 8065 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_MEDIATED_VPMU; 8066 8067 /* 8068 * Many features on and after V6 require dynamic constraint, 8069 * e.g., Arch PEBS, ACR. 8070 */ 8071 if (version >= 6) { 8072 x86_pmu.flags |= PMU_FL_DYN_CONSTRAINT; 8073 x86_pmu.late_setup = intel_pmu_late_setup; 8074 } 8075 8076 /* 8077 * Install the hw-cache-events table: 8078 */ 8079 switch (boot_cpu_data.x86_vfm) { 8080 case INTEL_CORE_YONAH: 8081 pr_cont("Core events, "); 8082 name = "core"; 8083 break; 8084 8085 case INTEL_CORE2_MEROM: 8086 x86_add_quirk(intel_clovertown_quirk); 8087 fallthrough; 8088 8089 case INTEL_CORE2_MEROM_L: 8090 case INTEL_CORE2_PENRYN: 8091 case INTEL_CORE2_DUNNINGTON: 8092 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 8093 sizeof(hw_cache_event_ids)); 8094 8095 intel_pmu_lbr_init_core(); 8096 8097 x86_pmu.event_constraints = intel_core2_event_constraints; 8098 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 8099 pr_cont("Core2 events, "); 8100 name = "core2"; 8101 break; 8102 8103 case INTEL_NEHALEM: 8104 case INTEL_NEHALEM_EP: 8105 case INTEL_NEHALEM_EX: 8106 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 8107 sizeof(hw_cache_event_ids)); 8108 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 8109 sizeof(hw_cache_extra_regs)); 8110 8111 intel_pmu_lbr_init_nhm(); 8112 8113 x86_pmu.event_constraints = intel_nehalem_event_constraints; 8114 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 8115 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 8116 x86_pmu.extra_regs = intel_nehalem_extra_regs; 8117 x86_pmu.limit_period = nhm_limit_period; 8118 8119 mem_attr = nhm_mem_events_attrs; 8120 8121 /* UOPS_ISSUED.STALLED_CYCLES */ 8122 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 8123 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 8124 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 8125 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 8126 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 8127 8128 intel_pmu_pebs_data_source_nhm(); 8129 x86_add_quirk(intel_nehalem_quirk); 8130 x86_pmu.pebs_no_tlb = 1; 8131 extra_attr = nhm_format_attr; 8132 8133 pr_cont("Nehalem events, "); 8134 name = "nehalem"; 8135 break; 8136 8137 case INTEL_ATOM_BONNELL: 8138 case INTEL_ATOM_BONNELL_MID: 8139 case INTEL_ATOM_SALTWELL: 8140 case INTEL_ATOM_SALTWELL_MID: 8141 case INTEL_ATOM_SALTWELL_TABLET: 8142 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 8143 sizeof(hw_cache_event_ids)); 8144 8145 intel_pmu_lbr_init_atom(); 8146 8147 x86_pmu.event_constraints = intel_gen_event_constraints; 8148 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 8149 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 8150 pr_cont("Atom events, "); 8151 name = "bonnell"; 8152 break; 8153 8154 case INTEL_ATOM_SILVERMONT: 8155 case INTEL_ATOM_SILVERMONT_D: 8156 case INTEL_ATOM_SILVERMONT_MID: 8157 case INTEL_ATOM_AIRMONT: 8158 case INTEL_ATOM_AIRMONT_NP: 8159 case INTEL_ATOM_SILVERMONT_MID2: 8160 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 8161 sizeof(hw_cache_event_ids)); 8162 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 8163 sizeof(hw_cache_extra_regs)); 8164 8165 intel_pmu_lbr_init_slm(); 8166 8167 x86_pmu.event_constraints = intel_slm_event_constraints; 8168 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 8169 x86_pmu.extra_regs = intel_slm_extra_regs; 8170 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8171 td_attr = slm_events_attrs; 8172 extra_attr = slm_format_attr; 8173 pr_cont("Silvermont events, "); 8174 name = "silvermont"; 8175 break; 8176 8177 case INTEL_ATOM_GOLDMONT: 8178 case INTEL_ATOM_GOLDMONT_D: 8179 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 8180 sizeof(hw_cache_event_ids)); 8181 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 8182 sizeof(hw_cache_extra_regs)); 8183 8184 intel_pmu_lbr_init_skl(); 8185 8186 x86_pmu.event_constraints = intel_slm_event_constraints; 8187 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 8188 x86_pmu.extra_regs = intel_glm_extra_regs; 8189 /* 8190 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 8191 * for precise cycles. 8192 * :pp is identical to :ppp 8193 */ 8194 x86_pmu.pebs_aliases = NULL; 8195 x86_pmu.pebs_prec_dist = true; 8196 x86_pmu.lbr_pt_coexist = true; 8197 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8198 td_attr = glm_events_attrs; 8199 extra_attr = slm_format_attr; 8200 pr_cont("Goldmont events, "); 8201 name = "goldmont"; 8202 break; 8203 8204 case INTEL_ATOM_GOLDMONT_PLUS: 8205 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 8206 sizeof(hw_cache_event_ids)); 8207 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 8208 sizeof(hw_cache_extra_regs)); 8209 8210 intel_pmu_lbr_init_skl(); 8211 8212 x86_pmu.event_constraints = intel_slm_event_constraints; 8213 x86_pmu.extra_regs = intel_glm_extra_regs; 8214 /* 8215 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 8216 * for precise cycles. 8217 */ 8218 x86_pmu.pebs_aliases = NULL; 8219 x86_pmu.pebs_prec_dist = true; 8220 x86_pmu.lbr_pt_coexist = true; 8221 x86_pmu.pebs_capable = ~0ULL; 8222 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8223 x86_pmu.flags |= PMU_FL_PEBS_ALL; 8224 x86_pmu.get_event_constraints = glp_get_event_constraints; 8225 td_attr = glm_events_attrs; 8226 /* Goldmont Plus has 4-wide pipeline */ 8227 event_attr_td_total_slots_scale_glm.event_str = "4"; 8228 extra_attr = slm_format_attr; 8229 pr_cont("Goldmont plus events, "); 8230 name = "goldmont_plus"; 8231 break; 8232 8233 case INTEL_ATOM_TREMONT_D: 8234 case INTEL_ATOM_TREMONT: 8235 case INTEL_ATOM_TREMONT_L: 8236 x86_pmu.late_ack = true; 8237 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 8238 sizeof(hw_cache_event_ids)); 8239 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 8240 sizeof(hw_cache_extra_regs)); 8241 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 8242 8243 intel_pmu_lbr_init_skl(); 8244 8245 x86_pmu.event_constraints = intel_slm_event_constraints; 8246 x86_pmu.extra_regs = intel_tnt_extra_regs; 8247 /* 8248 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 8249 * for precise cycles. 8250 */ 8251 x86_pmu.pebs_aliases = NULL; 8252 x86_pmu.pebs_prec_dist = true; 8253 x86_pmu.lbr_pt_coexist = true; 8254 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8255 x86_pmu.get_event_constraints = tnt_get_event_constraints; 8256 td_attr = tnt_events_attrs; 8257 extra_attr = slm_format_attr; 8258 pr_cont("Tremont events, "); 8259 name = "Tremont"; 8260 break; 8261 8262 case INTEL_ATOM_GRACEMONT: 8263 intel_pmu_init_grt(NULL); 8264 intel_pmu_pebs_data_source_grt(); 8265 x86_pmu.pebs_latency_data = grt_latency_data; 8266 x86_pmu.get_event_constraints = tnt_get_event_constraints; 8267 td_attr = tnt_events_attrs; 8268 mem_attr = grt_mem_attrs; 8269 extra_attr = nhm_format_attr; 8270 pr_cont("Gracemont events, "); 8271 name = "gracemont"; 8272 break; 8273 8274 case INTEL_ATOM_CRESTMONT: 8275 case INTEL_ATOM_CRESTMONT_X: 8276 intel_pmu_init_cmt(NULL); 8277 intel_pmu_pebs_data_source_cmt(); 8278 x86_pmu.pebs_latency_data = cmt_latency_data; 8279 x86_pmu.get_event_constraints = cmt_get_event_constraints; 8280 td_attr = cmt_events_attrs; 8281 mem_attr = grt_mem_attrs; 8282 extra_attr = cmt_format_attr; 8283 pr_cont("Crestmont events, "); 8284 name = "crestmont"; 8285 break; 8286 8287 case INTEL_ATOM_DARKMONT_X: 8288 intel_pmu_init_dkt(NULL); 8289 intel_pmu_pebs_data_source_cmt(); 8290 x86_pmu.pebs_latency_data = cmt_latency_data; 8291 x86_pmu.get_event_constraints = cmt_get_event_constraints; 8292 td_attr = skt_events_attrs; 8293 mem_attr = grt_mem_attrs; 8294 extra_attr = cmt_format_attr; 8295 pr_cont("Darkmont events, "); 8296 name = "darkmont"; 8297 break; 8298 8299 case INTEL_WESTMERE: 8300 case INTEL_WESTMERE_EP: 8301 case INTEL_WESTMERE_EX: 8302 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 8303 sizeof(hw_cache_event_ids)); 8304 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 8305 sizeof(hw_cache_extra_regs)); 8306 8307 intel_pmu_lbr_init_nhm(); 8308 8309 x86_pmu.event_constraints = intel_westmere_event_constraints; 8310 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 8311 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 8312 x86_pmu.extra_regs = intel_westmere_extra_regs; 8313 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8314 8315 mem_attr = nhm_mem_events_attrs; 8316 8317 /* UOPS_ISSUED.STALLED_CYCLES */ 8318 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 8319 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 8320 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 8321 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 8322 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 8323 8324 intel_pmu_pebs_data_source_nhm(); 8325 extra_attr = nhm_format_attr; 8326 pr_cont("Westmere events, "); 8327 name = "westmere"; 8328 break; 8329 8330 case INTEL_SANDYBRIDGE: 8331 case INTEL_SANDYBRIDGE_X: 8332 x86_add_quirk(intel_sandybridge_quirk); 8333 x86_add_quirk(intel_ht_bug); 8334 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 8335 sizeof(hw_cache_event_ids)); 8336 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 8337 sizeof(hw_cache_extra_regs)); 8338 8339 intel_pmu_lbr_init_snb(); 8340 8341 x86_pmu.event_constraints = intel_snb_event_constraints; 8342 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 8343 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 8344 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X) 8345 x86_pmu.extra_regs = intel_snbep_extra_regs; 8346 else 8347 x86_pmu.extra_regs = intel_snb_extra_regs; 8348 8349 8350 /* all extra regs are per-cpu when HT is on */ 8351 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8352 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 8353 8354 td_attr = snb_events_attrs; 8355 mem_attr = snb_mem_events_attrs; 8356 8357 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 8358 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 8359 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 8360 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 8361 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 8362 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 8363 8364 extra_attr = nhm_format_attr; 8365 8366 pr_cont("SandyBridge events, "); 8367 name = "sandybridge"; 8368 break; 8369 8370 case INTEL_IVYBRIDGE: 8371 case INTEL_IVYBRIDGE_X: 8372 x86_add_quirk(intel_ht_bug); 8373 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 8374 sizeof(hw_cache_event_ids)); 8375 /* dTLB-load-misses on IVB is different than SNB */ 8376 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 8377 8378 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 8379 sizeof(hw_cache_extra_regs)); 8380 8381 intel_pmu_lbr_init_snb(); 8382 8383 x86_pmu.event_constraints = intel_ivb_event_constraints; 8384 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 8385 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 8386 x86_pmu.pebs_prec_dist = true; 8387 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X) 8388 x86_pmu.extra_regs = intel_snbep_extra_regs; 8389 else 8390 x86_pmu.extra_regs = intel_snb_extra_regs; 8391 /* all extra regs are per-cpu when HT is on */ 8392 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8393 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 8394 8395 td_attr = snb_events_attrs; 8396 mem_attr = snb_mem_events_attrs; 8397 8398 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 8399 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 8400 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 8401 8402 extra_attr = nhm_format_attr; 8403 8404 pr_cont("IvyBridge events, "); 8405 name = "ivybridge"; 8406 break; 8407 8408 8409 case INTEL_HASWELL: 8410 case INTEL_HASWELL_X: 8411 case INTEL_HASWELL_L: 8412 case INTEL_HASWELL_G: 8413 x86_add_quirk(intel_ht_bug); 8414 x86_add_quirk(intel_pebs_isolation_quirk); 8415 x86_pmu.late_ack = true; 8416 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 8417 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 8418 8419 intel_pmu_lbr_init_hsw(); 8420 8421 x86_pmu.event_constraints = intel_hsw_event_constraints; 8422 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 8423 x86_pmu.extra_regs = intel_snbep_extra_regs; 8424 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 8425 x86_pmu.pebs_prec_dist = true; 8426 /* all extra regs are per-cpu when HT is on */ 8427 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8428 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 8429 8430 x86_pmu.hw_config = hsw_hw_config; 8431 x86_pmu.get_event_constraints = hsw_get_event_constraints; 8432 x86_pmu.limit_period = hsw_limit_period; 8433 x86_pmu.lbr_double_abort = true; 8434 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8435 hsw_format_attr : nhm_format_attr; 8436 td_attr = hsw_events_attrs; 8437 mem_attr = hsw_mem_events_attrs; 8438 tsx_attr = hsw_tsx_events_attrs; 8439 pr_cont("Haswell events, "); 8440 name = "haswell"; 8441 break; 8442 8443 case INTEL_BROADWELL: 8444 case INTEL_BROADWELL_D: 8445 case INTEL_BROADWELL_G: 8446 case INTEL_BROADWELL_X: 8447 x86_add_quirk(intel_pebs_isolation_quirk); 8448 x86_pmu.late_ack = true; 8449 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 8450 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 8451 8452 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 8453 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 8454 BDW_L3_MISS|HSW_SNOOP_DRAM; 8455 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 8456 HSW_SNOOP_DRAM; 8457 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 8458 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 8459 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 8460 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 8461 8462 intel_pmu_lbr_init_hsw(); 8463 8464 x86_pmu.event_constraints = intel_bdw_event_constraints; 8465 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 8466 x86_pmu.extra_regs = intel_snbep_extra_regs; 8467 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 8468 x86_pmu.pebs_prec_dist = true; 8469 /* all extra regs are per-cpu when HT is on */ 8470 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8471 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 8472 8473 x86_pmu.hw_config = hsw_hw_config; 8474 x86_pmu.get_event_constraints = hsw_get_event_constraints; 8475 x86_pmu.limit_period = bdw_limit_period; 8476 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8477 hsw_format_attr : nhm_format_attr; 8478 td_attr = hsw_events_attrs; 8479 mem_attr = hsw_mem_events_attrs; 8480 tsx_attr = hsw_tsx_events_attrs; 8481 pr_cont("Broadwell events, "); 8482 name = "broadwell"; 8483 break; 8484 8485 case INTEL_XEON_PHI_KNL: 8486 case INTEL_XEON_PHI_KNM: 8487 memcpy(hw_cache_event_ids, 8488 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 8489 memcpy(hw_cache_extra_regs, 8490 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 8491 intel_pmu_lbr_init_knl(); 8492 8493 x86_pmu.event_constraints = intel_slm_event_constraints; 8494 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 8495 x86_pmu.extra_regs = intel_knl_extra_regs; 8496 8497 /* all extra regs are per-cpu when HT is on */ 8498 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8499 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 8500 extra_attr = slm_format_attr; 8501 pr_cont("Knights Landing/Mill events, "); 8502 name = "knights-landing"; 8503 break; 8504 8505 case INTEL_SKYLAKE_X: 8506 pmem = true; 8507 fallthrough; 8508 case INTEL_SKYLAKE_L: 8509 case INTEL_SKYLAKE: 8510 case INTEL_KABYLAKE_L: 8511 case INTEL_KABYLAKE: 8512 case INTEL_COMETLAKE_L: 8513 case INTEL_COMETLAKE: 8514 x86_add_quirk(intel_pebs_isolation_quirk); 8515 x86_pmu.late_ack = true; 8516 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 8517 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 8518 intel_pmu_lbr_init_skl(); 8519 8520 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 8521 event_attr_td_recovery_bubbles.event_str_noht = 8522 "event=0xd,umask=0x1,cmask=1"; 8523 event_attr_td_recovery_bubbles.event_str_ht = 8524 "event=0xd,umask=0x1,cmask=1,any=1"; 8525 8526 x86_pmu.event_constraints = intel_skl_event_constraints; 8527 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 8528 x86_pmu.extra_regs = intel_skl_extra_regs; 8529 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 8530 x86_pmu.pebs_prec_dist = true; 8531 /* all extra regs are per-cpu when HT is on */ 8532 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8533 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 8534 8535 x86_pmu.hw_config = hsw_hw_config; 8536 x86_pmu.get_event_constraints = hsw_get_event_constraints; 8537 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8538 hsw_format_attr : nhm_format_attr; 8539 extra_skl_attr = skl_format_attr; 8540 td_attr = hsw_events_attrs; 8541 mem_attr = hsw_mem_events_attrs; 8542 tsx_attr = hsw_tsx_events_attrs; 8543 intel_pmu_pebs_data_source_skl(pmem); 8544 8545 /* 8546 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 8547 * TSX force abort hooks are not required on these systems. Only deploy 8548 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 8549 */ 8550 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 8551 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 8552 x86_pmu.flags |= PMU_FL_TFA; 8553 x86_pmu.get_event_constraints = tfa_get_event_constraints; 8554 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 8555 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 8556 } 8557 8558 pr_cont("Skylake events, "); 8559 name = "skylake"; 8560 break; 8561 8562 case INTEL_ICELAKE_X: 8563 case INTEL_ICELAKE_D: 8564 memcpy(hw_cache_extra_regs, snc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 8565 x86_pmu.pebs_ept = 1; 8566 pmem = true; 8567 goto snc_common; 8568 case INTEL_ICELAKE_L: 8569 case INTEL_ICELAKE: 8570 case INTEL_TIGERLAKE_L: 8571 case INTEL_TIGERLAKE: 8572 case INTEL_ROCKETLAKE: 8573 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 8574 snc_common: 8575 x86_pmu.late_ack = true; 8576 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 8577 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 8578 intel_pmu_lbr_init_skl(); 8579 8580 x86_pmu.event_constraints = intel_icl_event_constraints; 8581 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 8582 x86_pmu.extra_regs = intel_icl_extra_regs; 8583 x86_pmu.pebs_aliases = NULL; 8584 x86_pmu.pebs_prec_dist = true; 8585 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 8586 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 8587 8588 x86_pmu.hw_config = hsw_hw_config; 8589 x86_pmu.get_event_constraints = icl_get_event_constraints; 8590 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8591 hsw_format_attr : nhm_format_attr; 8592 extra_skl_attr = skl_format_attr; 8593 mem_attr = icl_events_attrs; 8594 td_attr = icl_td_events_attrs; 8595 tsx_attr = icl_tsx_events_attrs; 8596 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 8597 x86_pmu.lbr_pt_coexist = true; 8598 intel_pmu_pebs_data_source_skl(pmem); 8599 x86_pmu.num_topdown_events = 4; 8600 static_call_update(intel_pmu_update_topdown_event, 8601 &icl_update_topdown_event); 8602 static_call_update(intel_pmu_set_topdown_event_period, 8603 &icl_set_topdown_event_period); 8604 pr_cont("Icelake events, "); 8605 name = "icelake"; 8606 break; 8607 8608 case INTEL_SAPPHIRERAPIDS_X: 8609 case INTEL_EMERALDRAPIDS_X: 8610 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 8611 x86_pmu.extra_regs = intel_glc_extra_regs; 8612 pr_cont("Sapphire Rapids events, "); 8613 name = "sapphire_rapids"; 8614 goto glc_common; 8615 8616 case INTEL_GRANITERAPIDS_X: 8617 case INTEL_GRANITERAPIDS_D: 8618 x86_pmu.extra_regs = intel_rwc_extra_regs; 8619 pr_cont("Granite Rapids events, "); 8620 name = "granite_rapids"; 8621 goto glc_common; 8622 8623 case INTEL_DIAMONDRAPIDS_X: 8624 intel_pmu_init_pnc(NULL); 8625 x86_pmu.pebs_latency_data = pnc_latency_data; 8626 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8627 pnc_format_attr_rtm : pnc_format_attr; 8628 8629 pr_cont("Panthercove events, "); 8630 name = "panthercove"; 8631 goto glc_base; 8632 8633 glc_common: 8634 intel_pmu_init_glc(NULL); 8635 intel_pmu_pebs_data_source_skl(true); 8636 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8637 hsw_format_attr : nhm_format_attr; 8638 glc_base: 8639 x86_pmu.pebs_ept = 1; 8640 x86_pmu.hw_config = hsw_hw_config; 8641 x86_pmu.get_event_constraints = glc_get_event_constraints; 8642 extra_skl_attr = skl_format_attr; 8643 mem_attr = glc_events_attrs; 8644 td_attr = glc_td_events_attrs; 8645 tsx_attr = glc_tsx_events_attrs; 8646 break; 8647 8648 case INTEL_ALDERLAKE: 8649 case INTEL_ALDERLAKE_L: 8650 case INTEL_RAPTORLAKE: 8651 case INTEL_RAPTORLAKE_P: 8652 case INTEL_RAPTORLAKE_S: 8653 /* 8654 * Alder Lake has 2 types of CPU, core and atom. 8655 * 8656 * Initialize the common PerfMon capabilities here. 8657 */ 8658 ret = intel_pmu_init_hybrid(hybrid_big_small); 8659 if (ret) 8660 return ret; 8661 8662 x86_pmu.pebs_latency_data = grt_latency_data; 8663 x86_pmu.get_event_constraints = adl_get_event_constraints; 8664 x86_pmu.hw_config = adl_hw_config; 8665 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 8666 8667 td_attr = adl_hybrid_events_attrs; 8668 mem_attr = adl_hybrid_mem_attrs; 8669 tsx_attr = adl_hybrid_tsx_attrs; 8670 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8671 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 8672 8673 /* Initialize big core specific PerfMon capabilities.*/ 8674 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8675 intel_pmu_init_glc_hybrid(&pmu->pmu); 8676 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 8677 pmu->cntr_mask64 <<= 2; 8678 pmu->cntr_mask64 |= 0x3; 8679 pmu->fixed_cntr_mask64 <<= 1; 8680 pmu->fixed_cntr_mask64 |= 0x1; 8681 } else { 8682 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 8683 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 8684 } 8685 8686 /* 8687 * Quirk: For some Alder Lake machine, when all E-cores are disabled in 8688 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, 8689 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will 8690 * mistakenly add extra counters for P-cores. Correct the number of 8691 * counters here. 8692 */ 8693 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) { 8694 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 8695 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 8696 } 8697 8698 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 8699 pmu->unconstrained = (struct event_constraint) 8700 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 8701 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 8702 8703 pmu->extra_regs = intel_glc_extra_regs; 8704 8705 /* Initialize Atom core specific PerfMon capabilities.*/ 8706 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8707 intel_pmu_init_grt(&pmu->pmu); 8708 8709 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 8710 intel_pmu_pebs_data_source_adl(); 8711 pr_cont("Alderlake Hybrid events, "); 8712 name = "alderlake_hybrid"; 8713 break; 8714 8715 case INTEL_METEORLAKE: 8716 case INTEL_METEORLAKE_L: 8717 case INTEL_ARROWLAKE_U: 8718 ret = intel_pmu_init_hybrid(hybrid_big_small); 8719 if (ret) 8720 return ret; 8721 8722 x86_pmu.pebs_latency_data = cmt_latency_data; 8723 x86_pmu.get_event_constraints = mtl_get_event_constraints; 8724 x86_pmu.hw_config = adl_hw_config; 8725 8726 td_attr = adl_hybrid_events_attrs; 8727 mem_attr = mtl_hybrid_mem_attrs; 8728 tsx_attr = adl_hybrid_tsx_attrs; 8729 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8730 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 8731 8732 /* Initialize big core specific PerfMon capabilities.*/ 8733 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8734 intel_pmu_init_glc_hybrid(&pmu->pmu); 8735 pmu->extra_regs = intel_rwc_extra_regs; 8736 8737 /* Initialize Atom core specific PerfMon capabilities.*/ 8738 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8739 intel_pmu_init_cmt(&pmu->pmu); 8740 8741 intel_pmu_pebs_data_source_mtl(); 8742 pr_cont("Meteorlake Hybrid events, "); 8743 name = "meteorlake_hybrid"; 8744 break; 8745 8746 case INTEL_PANTHERLAKE_L: 8747 case INTEL_WILDCATLAKE_L: 8748 pr_cont("Pantherlake Hybrid events, "); 8749 name = "pantherlake_hybrid"; 8750 8751 ret = intel_pmu_init_hybrid(hybrid_big_small); 8752 if (ret) 8753 return ret; 8754 8755 /* Initialize big core specific PerfMon capabilities.*/ 8756 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8757 intel_pmu_init_lnc(&pmu->pmu); 8758 /* Initialize Atom core specific PerfMon capabilities.*/ 8759 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8760 intel_pmu_init_dkt_hybrid(&pmu->pmu); 8761 8762 goto lnl_common; 8763 8764 case INTEL_ARROWLAKE: 8765 pr_cont("Arrowlake Hybrid events, "); 8766 name = "arrowlake_hybrid"; 8767 8768 ret = intel_pmu_init_hybrid(hybrid_big_small); 8769 if (ret) 8770 return ret; 8771 8772 /* Initialize big core specific PerfMon capabilities.*/ 8773 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8774 intel_pmu_init_lnc(&pmu->pmu); 8775 memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs), 8776 arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 8777 /* Initialize Atom core specific PerfMon capabilities.*/ 8778 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8779 intel_pmu_init_skt(&pmu->pmu); 8780 8781 goto lnl_common; 8782 8783 case INTEL_LUNARLAKE_M: 8784 pr_cont("Lunarlake Hybrid events, "); 8785 name = "lunarlake_hybrid"; 8786 8787 ret = intel_pmu_init_hybrid(hybrid_big_small); 8788 if (ret) 8789 return ret; 8790 8791 /* Initialize big core specific PerfMon capabilities.*/ 8792 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8793 intel_pmu_init_lnc(&pmu->pmu); 8794 /* Initialize Atom core specific PerfMon capabilities.*/ 8795 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8796 intel_pmu_init_skt(&pmu->pmu); 8797 8798 lnl_common: 8799 8800 x86_pmu.pebs_latency_data = lnl_latency_data; 8801 x86_pmu.get_event_constraints = mtl_get_event_constraints; 8802 x86_pmu.hw_config = adl_hw_config; 8803 8804 td_attr = lnl_hybrid_events_attrs; 8805 mem_attr = mtl_hybrid_mem_attrs; 8806 tsx_attr = adl_hybrid_tsx_attrs; 8807 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8808 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 8809 8810 intel_pmu_pebs_data_source_lnl(); 8811 break; 8812 8813 case INTEL_ARROWLAKE_H: 8814 ret = intel_pmu_init_hybrid(hybrid_big_small_tiny); 8815 if (ret) 8816 return ret; 8817 8818 x86_pmu.pebs_latency_data = arl_h_latency_data; 8819 x86_pmu.get_event_constraints = arl_h_get_event_constraints; 8820 x86_pmu.hw_config = arl_h_hw_config; 8821 8822 td_attr = arl_h_hybrid_events_attrs; 8823 mem_attr = arl_h_hybrid_mem_attrs; 8824 tsx_attr = adl_hybrid_tsx_attrs; 8825 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8826 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 8827 8828 /* Initialize big core specific PerfMon capabilities. */ 8829 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8830 intel_pmu_init_lnc(&pmu->pmu); 8831 memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs), 8832 arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 8833 8834 /* Initialize Atom core specific PerfMon capabilities. */ 8835 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8836 intel_pmu_init_skt(&pmu->pmu); 8837 8838 /* Initialize Lower Power Atom specific PerfMon capabilities. */ 8839 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX]; 8840 intel_pmu_init_cmt(&pmu->pmu); 8841 8842 intel_pmu_pebs_data_source_arl_h(); 8843 pr_cont("ArrowLake-H Hybrid events, "); 8844 name = "arrowlake_h_hybrid"; 8845 break; 8846 8847 case INTEL_NOVALAKE: 8848 case INTEL_NOVALAKE_L: 8849 pr_cont("Novalake Hybrid events, "); 8850 name = "novalake_hybrid"; 8851 ret = intel_pmu_init_hybrid(hybrid_big_small); 8852 if (ret) 8853 return ret; 8854 8855 x86_pmu.pebs_latency_data = nvl_latency_data; 8856 x86_pmu.get_event_constraints = mtl_get_event_constraints; 8857 x86_pmu.hw_config = adl_hw_config; 8858 8859 td_attr = lnl_hybrid_events_attrs; 8860 mem_attr = mtl_hybrid_mem_attrs; 8861 tsx_attr = adl_hybrid_tsx_attrs; 8862 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8863 nvl_hybrid_extra_attr_rtm : nvl_hybrid_extra_attr; 8864 8865 /* Initialize big core specific PerfMon capabilities.*/ 8866 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8867 intel_pmu_init_cyc(&pmu->pmu); 8868 8869 /* Initialize Atom core specific PerfMon capabilities.*/ 8870 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8871 intel_pmu_init_arw(&pmu->pmu); 8872 break; 8873 8874 default: 8875 switch (x86_pmu.version) { 8876 case 1: 8877 x86_pmu.event_constraints = intel_v1_event_constraints; 8878 pr_cont("generic architected perfmon v1, "); 8879 name = "generic_arch_v1"; 8880 break; 8881 case 2: 8882 case 3: 8883 case 4: 8884 /* 8885 * default constraints for v2 and up 8886 */ 8887 x86_pmu.event_constraints = intel_gen_event_constraints; 8888 pr_cont("generic architected perfmon, "); 8889 name = "generic_arch_v2+"; 8890 break; 8891 default: 8892 /* 8893 * The default constraints for v5 and up can support up to 8894 * 16 fixed counters. For the fixed counters 4 and later, 8895 * the pseudo-encoding is applied. 8896 * The constraints may be cut according to the CPUID enumeration 8897 * by inserting the EVENT_CONSTRAINT_END. 8898 */ 8899 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED) 8900 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 8901 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1; 8902 x86_pmu.event_constraints = intel_v5_gen_event_constraints; 8903 pr_cont("generic architected perfmon, "); 8904 name = "generic_arch_v5+"; 8905 break; 8906 } 8907 } 8908 8909 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 8910 8911 if (!is_hybrid()) { 8912 group_events_td.attrs = td_attr; 8913 group_events_mem.attrs = mem_attr; 8914 group_events_tsx.attrs = tsx_attr; 8915 group_format_extra.attrs = extra_attr; 8916 group_format_extra_skl.attrs = extra_skl_attr; 8917 8918 x86_pmu.attr_update = attr_update; 8919 } else { 8920 hybrid_group_events_td.attrs = td_attr; 8921 hybrid_group_events_mem.attrs = mem_attr; 8922 hybrid_group_events_tsx.attrs = tsx_attr; 8923 hybrid_group_format_extra.attrs = extra_attr; 8924 8925 x86_pmu.attr_update = hybrid_attr_update; 8926 } 8927 8928 /* 8929 * The archPerfmonExt (0x23) includes an enhanced enumeration of 8930 * PMU architectural features with a per-core view. For non-hybrid, 8931 * each core has the same PMU capabilities. It's good enough to 8932 * update the x86_pmu from the booting CPU. For hybrid, the x86_pmu 8933 * is used to keep the common capabilities. Still keep the values 8934 * from the leaf 0xa. The core specific update will be done later 8935 * when a new type is online. 8936 */ 8937 if (!is_hybrid()) 8938 intel_update_pmu_caps(NULL); 8939 8940 if (x86_pmu.arch_pebs) { 8941 static_call_update(intel_pmu_disable_event_ext, 8942 intel_pmu_disable_event_ext); 8943 static_call_update(intel_pmu_enable_event_ext, 8944 intel_pmu_enable_event_ext); 8945 pr_cont("Architectural PEBS, "); 8946 } 8947 8948 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64, 8949 &x86_pmu.fixed_cntr_mask64, 8950 &x86_pmu.intel_ctrl); 8951 8952 /* AnyThread may be deprecated on arch perfmon v5 or later */ 8953 if (version >= 5 && edx.split.anythread_deprecated) { 8954 x86_pmu.format_attrs = intel_arch_formats_attr; 8955 pr_cont("AnyThread deprecated, "); 8956 } 8957 8958 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 8959 intel_pmu_arch_lbr_init(); 8960 8961 intel_pmu_check_event_constraints_all(NULL); 8962 8963 /* 8964 * Access LBR MSR may cause #GP under certain circumstances. 8965 * Check all LBR MSR here. 8966 * Disable LBR access if any LBR MSRs can not be accessed. 8967 */ 8968 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 8969 x86_pmu.lbr_nr = 0; 8970 for (i = 0; i < x86_pmu.lbr_nr; i++) { 8971 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 8972 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 8973 x86_pmu.lbr_nr = 0; 8974 } 8975 8976 if (x86_pmu.lbr_nr) { 8977 intel_pmu_lbr_init(); 8978 8979 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 8980 8981 /* only support branch_stack snapshot for perfmon >= v2 */ 8982 if (x86_pmu.disable_all == intel_pmu_disable_all) { 8983 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 8984 static_call_update(perf_snapshot_branch_stack, 8985 intel_pmu_snapshot_arch_branch_stack); 8986 } else { 8987 static_call_update(perf_snapshot_branch_stack, 8988 intel_pmu_snapshot_branch_stack); 8989 } 8990 } 8991 } 8992 8993 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 8994 8995 /* Support full width counters using alternative MSR range */ 8996 if (x86_pmu.intel_cap.full_width_write) { 8997 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 8998 x86_pmu.perfctr = MSR_IA32_PMC0; 8999 pr_cont("full-width counters, "); 9000 } 9001 9002 /* Support V6+ MSR Aliasing */ 9003 if (x86_pmu.version >= 6) { 9004 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR; 9005 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A; 9006 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR; 9007 x86_pmu.addr_offset = intel_pmu_v6_addr_offset; 9008 } 9009 9010 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 9011 x86_pmu.intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS; 9012 9013 if (x86_pmu.intel_cap.pebs_timing_info) 9014 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY; 9015 9016 intel_aux_output_init(); 9017 9018 return 0; 9019 } 9020 9021 /* 9022 * HT bug: phase 2 init 9023 * Called once we have valid topology information to check 9024 * whether or not HT is enabled 9025 * If HT is off, then we disable the workaround 9026 */ 9027 static __init int fixup_ht_bug(void) 9028 { 9029 int c; 9030 /* 9031 * problem not present on this CPU model, nothing to do 9032 */ 9033 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 9034 return 0; 9035 9036 if (topology_max_smt_threads() > 1) { 9037 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 9038 return 0; 9039 } 9040 9041 cpus_read_lock(); 9042 9043 hardlockup_detector_perf_stop(); 9044 9045 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 9046 9047 x86_pmu.start_scheduling = NULL; 9048 x86_pmu.commit_scheduling = NULL; 9049 x86_pmu.stop_scheduling = NULL; 9050 9051 hardlockup_detector_perf_restart(); 9052 9053 for_each_online_cpu(c) 9054 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 9055 9056 cpus_read_unlock(); 9057 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 9058 return 0; 9059 } 9060 subsys_initcall(fixup_ht_bug) 9061