1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Microchip LAN966x outbound interrupt controller
4 *
5 * Copyright (c) 2024 Technology Inc. and its subsidiaries.
6 *
7 * Authors:
8 * Horatiu Vultur <horatiu.vultur@microchip.com>
9 * Clément Léger <clement.leger@bootlin.com>
10 * Herve Codina <herve.codina@bootlin.com>
11 */
12
13 #include <linux/interrupt.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqchip.h>
16 #include <linux/irq.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20
21 struct lan966x_oic_chip_regs {
22 int reg_off_ena_set;
23 int reg_off_ena_clr;
24 int reg_off_sticky;
25 int reg_off_ident;
26 int reg_off_map;
27 };
28
29 struct lan966x_oic_data {
30 void __iomem *regs;
31 int irq;
32 };
33
34 #define LAN966X_OIC_NR_IRQ 86
35
36 /* Interrupt sticky status */
37 #define LAN966X_OIC_INTR_STICKY 0x30
38 #define LAN966X_OIC_INTR_STICKY1 0x34
39 #define LAN966X_OIC_INTR_STICKY2 0x38
40
41 /* Interrupt enable */
42 #define LAN966X_OIC_INTR_ENA 0x48
43 #define LAN966X_OIC_INTR_ENA1 0x4c
44 #define LAN966X_OIC_INTR_ENA2 0x50
45
46 /* Atomic clear of interrupt enable */
47 #define LAN966X_OIC_INTR_ENA_CLR 0x54
48 #define LAN966X_OIC_INTR_ENA_CLR1 0x58
49 #define LAN966X_OIC_INTR_ENA_CLR2 0x5c
50
51 /* Atomic set of interrupt */
52 #define LAN966X_OIC_INTR_ENA_SET 0x60
53 #define LAN966X_OIC_INTR_ENA_SET1 0x64
54 #define LAN966X_OIC_INTR_ENA_SET2 0x68
55
56 /* Mapping of source to destination interrupts (_n = 0..8) */
57 #define LAN966X_OIC_DST_INTR_MAP(_n) (0x78 + (_n) * 4)
58 #define LAN966X_OIC_DST_INTR_MAP1(_n) (0x9c + (_n) * 4)
59 #define LAN966X_OIC_DST_INTR_MAP2(_n) (0xc0 + (_n) * 4)
60
61 /* Currently active interrupt sources per destination (_n = 0..8) */
62 #define LAN966X_OIC_DST_INTR_IDENT(_n) (0xe4 + (_n) * 4)
63 #define LAN966X_OIC_DST_INTR_IDENT1(_n) (0x108 + (_n) * 4)
64 #define LAN966X_OIC_DST_INTR_IDENT2(_n) (0x12c + (_n) * 4)
65
lan966x_oic_irq_startup(struct irq_data * data)66 static unsigned int lan966x_oic_irq_startup(struct irq_data *data)
67 {
68 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
69 struct irq_chip_type *ct = irq_data_get_chip_type(data);
70 struct lan966x_oic_chip_regs *chip_regs = gc->private;
71 u32 map;
72
73 scoped_guard (raw_spinlock, &gc->lock) {
74 /* Map the source interrupt to the destination */
75 map = irq_reg_readl(gc, chip_regs->reg_off_map);
76 map |= data->mask;
77 irq_reg_writel(gc, map, chip_regs->reg_off_map);
78 }
79
80 ct->chip.irq_ack(data);
81 ct->chip.irq_unmask(data);
82
83 return 0;
84 }
85
lan966x_oic_irq_shutdown(struct irq_data * data)86 static void lan966x_oic_irq_shutdown(struct irq_data *data)
87 {
88 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
89 struct irq_chip_type *ct = irq_data_get_chip_type(data);
90 struct lan966x_oic_chip_regs *chip_regs = gc->private;
91 u32 map;
92
93 ct->chip.irq_mask(data);
94
95 guard(raw_spinlock)(&gc->lock);
96
97 /* Unmap the interrupt */
98 map = irq_reg_readl(gc, chip_regs->reg_off_map);
99 map &= ~data->mask;
100 irq_reg_writel(gc, map, chip_regs->reg_off_map);
101 }
102
lan966x_oic_irq_set_type(struct irq_data * data,unsigned int flow_type)103 static int lan966x_oic_irq_set_type(struct irq_data *data,
104 unsigned int flow_type)
105 {
106 if (flow_type != IRQ_TYPE_LEVEL_HIGH) {
107 pr_err("lan966x oic doesn't support flow type %d\n", flow_type);
108 return -EINVAL;
109 }
110
111 return 0;
112 }
113
lan966x_oic_irq_handler_domain(struct irq_domain * d,u32 first_irq)114 static void lan966x_oic_irq_handler_domain(struct irq_domain *d, u32 first_irq)
115 {
116 struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, first_irq);
117 struct lan966x_oic_chip_regs *chip_regs = gc->private;
118 unsigned long ident;
119 unsigned int hwirq;
120
121 ident = irq_reg_readl(gc, chip_regs->reg_off_ident);
122 if (!ident)
123 return;
124
125 for_each_set_bit(hwirq, &ident, 32)
126 generic_handle_domain_irq(d, hwirq + first_irq);
127 }
128
lan966x_oic_irq_handler(struct irq_desc * desc)129 static void lan966x_oic_irq_handler(struct irq_desc *desc)
130 {
131 struct irq_domain *d = irq_desc_get_handler_data(desc);
132 struct irq_chip *chip = irq_desc_get_chip(desc);
133
134 chained_irq_enter(chip, desc);
135 lan966x_oic_irq_handler_domain(d, 0);
136 lan966x_oic_irq_handler_domain(d, 32);
137 lan966x_oic_irq_handler_domain(d, 64);
138 chained_irq_exit(chip, desc);
139 }
140
141 static struct lan966x_oic_chip_regs lan966x_oic_chip_regs[3] = {
142 {
143 .reg_off_ena_set = LAN966X_OIC_INTR_ENA_SET,
144 .reg_off_ena_clr = LAN966X_OIC_INTR_ENA_CLR,
145 .reg_off_sticky = LAN966X_OIC_INTR_STICKY,
146 .reg_off_ident = LAN966X_OIC_DST_INTR_IDENT(0),
147 .reg_off_map = LAN966X_OIC_DST_INTR_MAP(0),
148 }, {
149 .reg_off_ena_set = LAN966X_OIC_INTR_ENA_SET1,
150 .reg_off_ena_clr = LAN966X_OIC_INTR_ENA_CLR1,
151 .reg_off_sticky = LAN966X_OIC_INTR_STICKY1,
152 .reg_off_ident = LAN966X_OIC_DST_INTR_IDENT1(0),
153 .reg_off_map = LAN966X_OIC_DST_INTR_MAP1(0),
154 }, {
155 .reg_off_ena_set = LAN966X_OIC_INTR_ENA_SET2,
156 .reg_off_ena_clr = LAN966X_OIC_INTR_ENA_CLR2,
157 .reg_off_sticky = LAN966X_OIC_INTR_STICKY2,
158 .reg_off_ident = LAN966X_OIC_DST_INTR_IDENT2(0),
159 .reg_off_map = LAN966X_OIC_DST_INTR_MAP2(0),
160 }
161 };
162
lan966x_oic_chip_init(struct irq_chip_generic * gc)163 static int lan966x_oic_chip_init(struct irq_chip_generic *gc)
164 {
165 struct lan966x_oic_data *lan966x_oic = gc->domain->host_data;
166 struct lan966x_oic_chip_regs *chip_regs;
167
168 chip_regs = &lan966x_oic_chip_regs[gc->irq_base / 32];
169
170 gc->reg_base = lan966x_oic->regs;
171 gc->chip_types[0].regs.enable = chip_regs->reg_off_ena_set;
172 gc->chip_types[0].regs.disable = chip_regs->reg_off_ena_clr;
173 gc->chip_types[0].regs.ack = chip_regs->reg_off_sticky;
174 gc->chip_types[0].chip.irq_startup = lan966x_oic_irq_startup;
175 gc->chip_types[0].chip.irq_shutdown = lan966x_oic_irq_shutdown;
176 gc->chip_types[0].chip.irq_set_type = lan966x_oic_irq_set_type;
177 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
178 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
179 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
180 gc->private = chip_regs;
181
182 /* Disable all interrupts handled by this chip */
183 irq_reg_writel(gc, ~0U, chip_regs->reg_off_ena_clr);
184
185 return 0;
186 }
187
lan966x_oic_chip_exit(struct irq_chip_generic * gc)188 static void lan966x_oic_chip_exit(struct irq_chip_generic *gc)
189 {
190 /* Disable and ack all interrupts handled by this chip */
191 irq_reg_writel(gc, ~0U, gc->chip_types[0].regs.disable);
192 irq_reg_writel(gc, ~0U, gc->chip_types[0].regs.ack);
193 }
194
lan966x_oic_domain_init(struct irq_domain * d)195 static int lan966x_oic_domain_init(struct irq_domain *d)
196 {
197 struct lan966x_oic_data *lan966x_oic = d->host_data;
198
199 irq_set_chained_handler_and_data(lan966x_oic->irq, lan966x_oic_irq_handler, d);
200
201 return 0;
202 }
203
lan966x_oic_domain_exit(struct irq_domain * d)204 static void lan966x_oic_domain_exit(struct irq_domain *d)
205 {
206 struct lan966x_oic_data *lan966x_oic = d->host_data;
207
208 irq_set_chained_handler_and_data(lan966x_oic->irq, NULL, NULL);
209 }
210
lan966x_oic_probe(struct platform_device * pdev)211 static int lan966x_oic_probe(struct platform_device *pdev)
212 {
213 struct irq_domain_chip_generic_info dgc_info = {
214 .name = "lan966x-oic",
215 .handler = handle_level_irq,
216 .irqs_per_chip = 32,
217 .num_ct = 1,
218 .init = lan966x_oic_chip_init,
219 .exit = lan966x_oic_chip_exit,
220 };
221 struct irq_domain_info d_info = {
222 .fwnode = of_fwnode_handle(pdev->dev.of_node),
223 .domain_flags = IRQ_DOMAIN_FLAG_DESTROY_GC,
224 .size = LAN966X_OIC_NR_IRQ,
225 .hwirq_max = LAN966X_OIC_NR_IRQ,
226 .ops = &irq_generic_chip_ops,
227 .dgc_info = &dgc_info,
228 .init = lan966x_oic_domain_init,
229 .exit = lan966x_oic_domain_exit,
230 };
231 struct lan966x_oic_data *lan966x_oic;
232 struct device *dev = &pdev->dev;
233 struct irq_domain *domain;
234
235 lan966x_oic = devm_kmalloc(dev, sizeof(*lan966x_oic), GFP_KERNEL);
236 if (!lan966x_oic)
237 return -ENOMEM;
238
239 lan966x_oic->regs = devm_platform_ioremap_resource(pdev, 0);
240 if (IS_ERR(lan966x_oic->regs))
241 return dev_err_probe(dev, PTR_ERR(lan966x_oic->regs),
242 "failed to map resource\n");
243
244 lan966x_oic->irq = platform_get_irq(pdev, 0);
245 if (lan966x_oic->irq < 0)
246 return dev_err_probe(dev, lan966x_oic->irq, "failed to get the IRQ\n");
247
248 d_info.host_data = lan966x_oic;
249 domain = devm_irq_domain_instantiate(dev, &d_info);
250 if (IS_ERR(domain))
251 return dev_err_probe(dev, PTR_ERR(domain),
252 "failed to instantiate the IRQ domain\n");
253 return 0;
254 }
255
256 static const struct of_device_id lan966x_oic_of_match[] = {
257 { .compatible = "microchip,lan966x-oic" },
258 {} /* sentinel */
259 };
260 MODULE_DEVICE_TABLE(of, lan966x_oic_of_match);
261
262 static struct platform_driver lan966x_oic_driver = {
263 .probe = lan966x_oic_probe,
264 .driver = {
265 .name = "lan966x-oic",
266 .of_match_table = lan966x_oic_of_match,
267 },
268 };
269 module_platform_driver(lan966x_oic_driver);
270
271 MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
272 MODULE_DESCRIPTION("Microchip LAN966x OIC driver");
273 MODULE_LICENSE("GPL");
274