1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright(c) 2021 Intel Corporation. All rights reserved.
3
4 #include <linux/platform_device.h>
5 #include <linux/genalloc.h>
6 #include <linux/module.h>
7 #include <linux/mutex.h>
8 #include <linux/acpi.h>
9 #include <linux/pci.h>
10 #include <linux/mm.h>
11 #include <cxlmem.h>
12
13 #include "../watermark.h"
14 #include "mock.h"
15
16 static int interleave_arithmetic;
17
18 #define FAKE_QTG_ID 42
19
20 #define NR_CXL_HOST_BRIDGES 2
21 #define NR_CXL_SINGLE_HOST 1
22 #define NR_CXL_RCH 1
23 #define NR_CXL_ROOT_PORTS 2
24 #define NR_CXL_SWITCH_PORTS 2
25 #define NR_CXL_PORT_DECODERS 8
26 #define NR_BRIDGES (NR_CXL_HOST_BRIDGES + NR_CXL_SINGLE_HOST + NR_CXL_RCH)
27
28 static struct platform_device *cxl_acpi;
29 static struct platform_device *cxl_host_bridge[NR_CXL_HOST_BRIDGES];
30 #define NR_MULTI_ROOT (NR_CXL_HOST_BRIDGES * NR_CXL_ROOT_PORTS)
31 static struct platform_device *cxl_root_port[NR_MULTI_ROOT];
32 static struct platform_device *cxl_switch_uport[NR_MULTI_ROOT];
33 #define NR_MEM_MULTI \
34 (NR_CXL_HOST_BRIDGES * NR_CXL_ROOT_PORTS * NR_CXL_SWITCH_PORTS)
35 static struct platform_device *cxl_switch_dport[NR_MEM_MULTI];
36
37 static struct platform_device *cxl_hb_single[NR_CXL_SINGLE_HOST];
38 static struct platform_device *cxl_root_single[NR_CXL_SINGLE_HOST];
39 static struct platform_device *cxl_swu_single[NR_CXL_SINGLE_HOST];
40 #define NR_MEM_SINGLE (NR_CXL_SINGLE_HOST * NR_CXL_SWITCH_PORTS)
41 static struct platform_device *cxl_swd_single[NR_MEM_SINGLE];
42
43 struct platform_device *cxl_mem[NR_MEM_MULTI];
44 struct platform_device *cxl_mem_single[NR_MEM_SINGLE];
45
46 static struct platform_device *cxl_rch[NR_CXL_RCH];
47 static struct platform_device *cxl_rcd[NR_CXL_RCH];
48
is_multi_bridge(struct device * dev)49 static inline bool is_multi_bridge(struct device *dev)
50 {
51 int i;
52
53 for (i = 0; i < ARRAY_SIZE(cxl_host_bridge); i++)
54 if (&cxl_host_bridge[i]->dev == dev)
55 return true;
56 return false;
57 }
58
is_single_bridge(struct device * dev)59 static inline bool is_single_bridge(struct device *dev)
60 {
61 int i;
62
63 for (i = 0; i < ARRAY_SIZE(cxl_hb_single); i++)
64 if (&cxl_hb_single[i]->dev == dev)
65 return true;
66 return false;
67 }
68
69 static struct acpi_device acpi0017_mock;
70 static struct acpi_device host_bridge[NR_BRIDGES] = {
71 [0] = {
72 .handle = &host_bridge[0],
73 .pnp.unique_id = "0",
74 },
75 [1] = {
76 .handle = &host_bridge[1],
77 .pnp.unique_id = "1",
78 },
79 [2] = {
80 .handle = &host_bridge[2],
81 .pnp.unique_id = "2",
82 },
83 [3] = {
84 .handle = &host_bridge[3],
85 .pnp.unique_id = "3",
86 },
87 };
88
is_mock_dev(struct device * dev)89 static bool is_mock_dev(struct device *dev)
90 {
91 int i;
92
93 for (i = 0; i < ARRAY_SIZE(cxl_mem); i++)
94 if (dev == &cxl_mem[i]->dev)
95 return true;
96 for (i = 0; i < ARRAY_SIZE(cxl_mem_single); i++)
97 if (dev == &cxl_mem_single[i]->dev)
98 return true;
99 for (i = 0; i < ARRAY_SIZE(cxl_rcd); i++)
100 if (dev == &cxl_rcd[i]->dev)
101 return true;
102 if (dev == &cxl_acpi->dev)
103 return true;
104 return false;
105 }
106
is_mock_adev(struct acpi_device * adev)107 static bool is_mock_adev(struct acpi_device *adev)
108 {
109 int i;
110
111 if (adev == &acpi0017_mock)
112 return true;
113
114 for (i = 0; i < ARRAY_SIZE(host_bridge); i++)
115 if (adev == &host_bridge[i])
116 return true;
117
118 return false;
119 }
120
121 static struct {
122 struct acpi_table_cedt cedt;
123 struct acpi_cedt_chbs chbs[NR_BRIDGES];
124 struct {
125 struct acpi_cedt_cfmws cfmws;
126 u32 target[1];
127 } cfmws0;
128 struct {
129 struct acpi_cedt_cfmws cfmws;
130 u32 target[2];
131 } cfmws1;
132 struct {
133 struct acpi_cedt_cfmws cfmws;
134 u32 target[1];
135 } cfmws2;
136 struct {
137 struct acpi_cedt_cfmws cfmws;
138 u32 target[2];
139 } cfmws3;
140 struct {
141 struct acpi_cedt_cfmws cfmws;
142 u32 target[1];
143 } cfmws4;
144 struct {
145 struct acpi_cedt_cfmws cfmws;
146 u32 target[1];
147 } cfmws5;
148 struct {
149 struct acpi_cedt_cfmws cfmws;
150 u32 target[1];
151 } cfmws6;
152 struct {
153 struct acpi_cedt_cfmws cfmws;
154 u32 target[2];
155 } cfmws7;
156 struct {
157 struct acpi_cedt_cfmws cfmws;
158 u32 target[4];
159 } cfmws8;
160 struct {
161 struct acpi_cedt_cxims cxims;
162 u64 xormap_list[2];
163 } cxims0;
164 } __packed mock_cedt = {
165 .cedt = {
166 .header = {
167 .signature = "CEDT",
168 .length = sizeof(mock_cedt),
169 .revision = 1,
170 },
171 },
172 .chbs[0] = {
173 .header = {
174 .type = ACPI_CEDT_TYPE_CHBS,
175 .length = sizeof(mock_cedt.chbs[0]),
176 },
177 .uid = 0,
178 .cxl_version = ACPI_CEDT_CHBS_VERSION_CXL20,
179 },
180 .chbs[1] = {
181 .header = {
182 .type = ACPI_CEDT_TYPE_CHBS,
183 .length = sizeof(mock_cedt.chbs[0]),
184 },
185 .uid = 1,
186 .cxl_version = ACPI_CEDT_CHBS_VERSION_CXL20,
187 },
188 .chbs[2] = {
189 .header = {
190 .type = ACPI_CEDT_TYPE_CHBS,
191 .length = sizeof(mock_cedt.chbs[0]),
192 },
193 .uid = 2,
194 .cxl_version = ACPI_CEDT_CHBS_VERSION_CXL20,
195 },
196 .chbs[3] = {
197 .header = {
198 .type = ACPI_CEDT_TYPE_CHBS,
199 .length = sizeof(mock_cedt.chbs[0]),
200 },
201 .uid = 3,
202 .cxl_version = ACPI_CEDT_CHBS_VERSION_CXL11,
203 },
204 .cfmws0 = {
205 .cfmws = {
206 .header = {
207 .type = ACPI_CEDT_TYPE_CFMWS,
208 .length = sizeof(mock_cedt.cfmws0),
209 },
210 .interleave_ways = 0,
211 .granularity = 4,
212 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
213 ACPI_CEDT_CFMWS_RESTRICT_VOLATILE,
214 .qtg_id = FAKE_QTG_ID,
215 .window_size = SZ_256M * 4UL,
216 },
217 .target = { 0 },
218 },
219 .cfmws1 = {
220 .cfmws = {
221 .header = {
222 .type = ACPI_CEDT_TYPE_CFMWS,
223 .length = sizeof(mock_cedt.cfmws1),
224 },
225 .interleave_ways = 1,
226 .granularity = 4,
227 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
228 ACPI_CEDT_CFMWS_RESTRICT_VOLATILE,
229 .qtg_id = FAKE_QTG_ID,
230 .window_size = SZ_256M * 8UL,
231 },
232 .target = { 0, 1, },
233 },
234 .cfmws2 = {
235 .cfmws = {
236 .header = {
237 .type = ACPI_CEDT_TYPE_CFMWS,
238 .length = sizeof(mock_cedt.cfmws2),
239 },
240 .interleave_ways = 0,
241 .granularity = 4,
242 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
243 ACPI_CEDT_CFMWS_RESTRICT_PMEM,
244 .qtg_id = FAKE_QTG_ID,
245 .window_size = SZ_256M * 4UL,
246 },
247 .target = { 0 },
248 },
249 .cfmws3 = {
250 .cfmws = {
251 .header = {
252 .type = ACPI_CEDT_TYPE_CFMWS,
253 .length = sizeof(mock_cedt.cfmws3),
254 },
255 .interleave_ways = 1,
256 .granularity = 4,
257 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
258 ACPI_CEDT_CFMWS_RESTRICT_PMEM,
259 .qtg_id = FAKE_QTG_ID,
260 .window_size = SZ_256M * 8UL,
261 },
262 .target = { 0, 1, },
263 },
264 .cfmws4 = {
265 .cfmws = {
266 .header = {
267 .type = ACPI_CEDT_TYPE_CFMWS,
268 .length = sizeof(mock_cedt.cfmws4),
269 },
270 .interleave_ways = 0,
271 .granularity = 4,
272 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
273 ACPI_CEDT_CFMWS_RESTRICT_PMEM,
274 .qtg_id = FAKE_QTG_ID,
275 .window_size = SZ_256M * 4UL,
276 },
277 .target = { 2 },
278 },
279 .cfmws5 = {
280 .cfmws = {
281 .header = {
282 .type = ACPI_CEDT_TYPE_CFMWS,
283 .length = sizeof(mock_cedt.cfmws5),
284 },
285 .interleave_ways = 0,
286 .granularity = 4,
287 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
288 ACPI_CEDT_CFMWS_RESTRICT_VOLATILE,
289 .qtg_id = FAKE_QTG_ID,
290 .window_size = SZ_256M,
291 },
292 .target = { 3 },
293 },
294 /* .cfmws6,7,8 use ACPI_CEDT_CFMWS_ARITHMETIC_XOR */
295 .cfmws6 = {
296 .cfmws = {
297 .header = {
298 .type = ACPI_CEDT_TYPE_CFMWS,
299 .length = sizeof(mock_cedt.cfmws6),
300 },
301 .interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
302 .interleave_ways = 0,
303 .granularity = 4,
304 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
305 ACPI_CEDT_CFMWS_RESTRICT_PMEM,
306 .qtg_id = FAKE_QTG_ID,
307 .window_size = SZ_256M * 8UL,
308 },
309 .target = { 0, },
310 },
311 .cfmws7 = {
312 .cfmws = {
313 .header = {
314 .type = ACPI_CEDT_TYPE_CFMWS,
315 .length = sizeof(mock_cedt.cfmws7),
316 },
317 .interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
318 .interleave_ways = 1,
319 .granularity = 0,
320 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
321 ACPI_CEDT_CFMWS_RESTRICT_PMEM,
322 .qtg_id = FAKE_QTG_ID,
323 .window_size = SZ_256M * 8UL,
324 },
325 .target = { 0, 1, },
326 },
327 .cfmws8 = {
328 .cfmws = {
329 .header = {
330 .type = ACPI_CEDT_TYPE_CFMWS,
331 .length = sizeof(mock_cedt.cfmws8),
332 },
333 .interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
334 .interleave_ways = 2,
335 .granularity = 0,
336 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
337 ACPI_CEDT_CFMWS_RESTRICT_PMEM,
338 .qtg_id = FAKE_QTG_ID,
339 .window_size = SZ_256M * 16UL,
340 },
341 .target = { 0, 1, 0, 1, },
342 },
343 .cxims0 = {
344 .cxims = {
345 .header = {
346 .type = ACPI_CEDT_TYPE_CXIMS,
347 .length = sizeof(mock_cedt.cxims0),
348 },
349 .hbig = 0,
350 .nr_xormaps = 2,
351 },
352 .xormap_list = { 0x404100, 0x808200, },
353 },
354 };
355
356 struct acpi_cedt_cfmws *mock_cfmws[] = {
357 [0] = &mock_cedt.cfmws0.cfmws,
358 [1] = &mock_cedt.cfmws1.cfmws,
359 [2] = &mock_cedt.cfmws2.cfmws,
360 [3] = &mock_cedt.cfmws3.cfmws,
361 [4] = &mock_cedt.cfmws4.cfmws,
362 [5] = &mock_cedt.cfmws5.cfmws,
363 /* Modulo Math above, XOR Math below */
364 [6] = &mock_cedt.cfmws6.cfmws,
365 [7] = &mock_cedt.cfmws7.cfmws,
366 [8] = &mock_cedt.cfmws8.cfmws,
367 };
368
369 static int cfmws_start;
370 static int cfmws_end;
371 #define CFMWS_MOD_ARRAY_START 0
372 #define CFMWS_MOD_ARRAY_END 5
373 #define CFMWS_XOR_ARRAY_START 6
374 #define CFMWS_XOR_ARRAY_END 8
375
376 struct acpi_cedt_cxims *mock_cxims[1] = {
377 [0] = &mock_cedt.cxims0.cxims,
378 };
379
380 struct cxl_mock_res {
381 struct list_head list;
382 struct range range;
383 };
384
385 static LIST_HEAD(mock_res);
386 static DEFINE_MUTEX(mock_res_lock);
387 static struct gen_pool *cxl_mock_pool;
388
depopulate_all_mock_resources(void)389 static void depopulate_all_mock_resources(void)
390 {
391 struct cxl_mock_res *res, *_res;
392
393 mutex_lock(&mock_res_lock);
394 list_for_each_entry_safe(res, _res, &mock_res, list) {
395 gen_pool_free(cxl_mock_pool, res->range.start,
396 range_len(&res->range));
397 list_del(&res->list);
398 kfree(res);
399 }
400 mutex_unlock(&mock_res_lock);
401 }
402
alloc_mock_res(resource_size_t size,int align)403 static struct cxl_mock_res *alloc_mock_res(resource_size_t size, int align)
404 {
405 struct cxl_mock_res *res = kzalloc(sizeof(*res), GFP_KERNEL);
406 struct genpool_data_align data = {
407 .align = align,
408 };
409 unsigned long phys;
410
411 INIT_LIST_HEAD(&res->list);
412 phys = gen_pool_alloc_algo(cxl_mock_pool, size,
413 gen_pool_first_fit_align, &data);
414 if (!phys)
415 return NULL;
416
417 res->range = (struct range) {
418 .start = phys,
419 .end = phys + size - 1,
420 };
421 mutex_lock(&mock_res_lock);
422 list_add(&res->list, &mock_res);
423 mutex_unlock(&mock_res_lock);
424
425 return res;
426 }
427
populate_cedt(void)428 static int populate_cedt(void)
429 {
430 struct cxl_mock_res *res;
431 int i;
432
433 for (i = 0; i < ARRAY_SIZE(mock_cedt.chbs); i++) {
434 struct acpi_cedt_chbs *chbs = &mock_cedt.chbs[i];
435 resource_size_t size;
436
437 if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL20)
438 size = ACPI_CEDT_CHBS_LENGTH_CXL20;
439 else
440 size = ACPI_CEDT_CHBS_LENGTH_CXL11;
441
442 res = alloc_mock_res(size, size);
443 if (!res)
444 return -ENOMEM;
445 chbs->base = res->range.start;
446 chbs->length = size;
447 }
448
449 for (i = cfmws_start; i <= cfmws_end; i++) {
450 struct acpi_cedt_cfmws *window = mock_cfmws[i];
451
452 res = alloc_mock_res(window->window_size, SZ_256M);
453 if (!res)
454 return -ENOMEM;
455 window->base_hpa = res->range.start;
456 }
457
458 return 0;
459 }
460
461 static bool is_mock_port(struct device *dev);
462
463 /*
464 * WARNING, this hack assumes the format of 'struct cxl_cfmws_context'
465 * and 'struct cxl_chbs_context' share the property that the first
466 * struct member is a cxl_test device being probed by the cxl_acpi
467 * driver.
468 */
469 struct cxl_cedt_context {
470 struct device *dev;
471 };
472
mock_acpi_table_parse_cedt(enum acpi_cedt_type id,acpi_tbl_entry_handler_arg handler_arg,void * arg)473 static int mock_acpi_table_parse_cedt(enum acpi_cedt_type id,
474 acpi_tbl_entry_handler_arg handler_arg,
475 void *arg)
476 {
477 struct cxl_cedt_context *ctx = arg;
478 struct device *dev = ctx->dev;
479 union acpi_subtable_headers *h;
480 unsigned long end;
481 int i;
482
483 if (!is_mock_port(dev) && !is_mock_dev(dev))
484 return acpi_table_parse_cedt(id, handler_arg, arg);
485
486 if (id == ACPI_CEDT_TYPE_CHBS)
487 for (i = 0; i < ARRAY_SIZE(mock_cedt.chbs); i++) {
488 h = (union acpi_subtable_headers *)&mock_cedt.chbs[i];
489 end = (unsigned long)&mock_cedt.chbs[i + 1];
490 handler_arg(h, arg, end);
491 }
492
493 if (id == ACPI_CEDT_TYPE_CFMWS)
494 for (i = cfmws_start; i <= cfmws_end; i++) {
495 h = (union acpi_subtable_headers *) mock_cfmws[i];
496 end = (unsigned long) h + mock_cfmws[i]->header.length;
497 handler_arg(h, arg, end);
498 }
499
500 if (id == ACPI_CEDT_TYPE_CXIMS)
501 for (i = 0; i < ARRAY_SIZE(mock_cxims); i++) {
502 h = (union acpi_subtable_headers *)mock_cxims[i];
503 end = (unsigned long)h + mock_cxims[i]->header.length;
504 handler_arg(h, arg, end);
505 }
506
507 return 0;
508 }
509
is_mock_bridge(struct device * dev)510 static bool is_mock_bridge(struct device *dev)
511 {
512 int i;
513
514 for (i = 0; i < ARRAY_SIZE(cxl_host_bridge); i++)
515 if (dev == &cxl_host_bridge[i]->dev)
516 return true;
517 for (i = 0; i < ARRAY_SIZE(cxl_hb_single); i++)
518 if (dev == &cxl_hb_single[i]->dev)
519 return true;
520 for (i = 0; i < ARRAY_SIZE(cxl_rch); i++)
521 if (dev == &cxl_rch[i]->dev)
522 return true;
523
524 return false;
525 }
526
is_mock_port(struct device * dev)527 static bool is_mock_port(struct device *dev)
528 {
529 int i;
530
531 if (is_mock_bridge(dev))
532 return true;
533
534 for (i = 0; i < ARRAY_SIZE(cxl_root_port); i++)
535 if (dev == &cxl_root_port[i]->dev)
536 return true;
537
538 for (i = 0; i < ARRAY_SIZE(cxl_switch_uport); i++)
539 if (dev == &cxl_switch_uport[i]->dev)
540 return true;
541
542 for (i = 0; i < ARRAY_SIZE(cxl_switch_dport); i++)
543 if (dev == &cxl_switch_dport[i]->dev)
544 return true;
545
546 for (i = 0; i < ARRAY_SIZE(cxl_root_single); i++)
547 if (dev == &cxl_root_single[i]->dev)
548 return true;
549
550 for (i = 0; i < ARRAY_SIZE(cxl_swu_single); i++)
551 if (dev == &cxl_swu_single[i]->dev)
552 return true;
553
554 for (i = 0; i < ARRAY_SIZE(cxl_swd_single); i++)
555 if (dev == &cxl_swd_single[i]->dev)
556 return true;
557
558 if (is_cxl_memdev(dev))
559 return is_mock_dev(dev->parent);
560
561 return false;
562 }
563
host_bridge_index(struct acpi_device * adev)564 static int host_bridge_index(struct acpi_device *adev)
565 {
566 return adev - host_bridge;
567 }
568
find_host_bridge(acpi_handle handle)569 static struct acpi_device *find_host_bridge(acpi_handle handle)
570 {
571 int i;
572
573 for (i = 0; i < ARRAY_SIZE(host_bridge); i++)
574 if (handle == host_bridge[i].handle)
575 return &host_bridge[i];
576 return NULL;
577 }
578
579 static acpi_status
mock_acpi_evaluate_integer(acpi_handle handle,acpi_string pathname,struct acpi_object_list * arguments,unsigned long long * data)580 mock_acpi_evaluate_integer(acpi_handle handle, acpi_string pathname,
581 struct acpi_object_list *arguments,
582 unsigned long long *data)
583 {
584 struct acpi_device *adev = find_host_bridge(handle);
585
586 if (!adev || strcmp(pathname, METHOD_NAME__UID) != 0)
587 return acpi_evaluate_integer(handle, pathname, arguments, data);
588
589 *data = host_bridge_index(adev);
590 return AE_OK;
591 }
592
593 static struct pci_bus mock_pci_bus[NR_BRIDGES];
594 static struct acpi_pci_root mock_pci_root[ARRAY_SIZE(mock_pci_bus)] = {
595 [0] = {
596 .bus = &mock_pci_bus[0],
597 },
598 [1] = {
599 .bus = &mock_pci_bus[1],
600 },
601 [2] = {
602 .bus = &mock_pci_bus[2],
603 },
604 [3] = {
605 .bus = &mock_pci_bus[3],
606 },
607
608 };
609
is_mock_bus(struct pci_bus * bus)610 static bool is_mock_bus(struct pci_bus *bus)
611 {
612 int i;
613
614 for (i = 0; i < ARRAY_SIZE(mock_pci_bus); i++)
615 if (bus == &mock_pci_bus[i])
616 return true;
617 return false;
618 }
619
mock_acpi_pci_find_root(acpi_handle handle)620 static struct acpi_pci_root *mock_acpi_pci_find_root(acpi_handle handle)
621 {
622 struct acpi_device *adev = find_host_bridge(handle);
623
624 if (!adev)
625 return acpi_pci_find_root(handle);
626 return &mock_pci_root[host_bridge_index(adev)];
627 }
628
mock_cxl_setup_hdm(struct cxl_port * port,struct cxl_endpoint_dvsec_info * info)629 static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port,
630 struct cxl_endpoint_dvsec_info *info)
631 {
632 struct cxl_hdm *cxlhdm = devm_kzalloc(&port->dev, sizeof(*cxlhdm), GFP_KERNEL);
633 struct device *dev = &port->dev;
634
635 if (!cxlhdm)
636 return ERR_PTR(-ENOMEM);
637
638 cxlhdm->port = port;
639 cxlhdm->interleave_mask = ~0U;
640 cxlhdm->iw_cap_mask = ~0UL;
641 dev_set_drvdata(dev, cxlhdm);
642 return cxlhdm;
643 }
644
mock_cxl_add_passthrough_decoder(struct cxl_port * port)645 static int mock_cxl_add_passthrough_decoder(struct cxl_port *port)
646 {
647 dev_err(&port->dev, "unexpected passthrough decoder for cxl_test\n");
648 return -EOPNOTSUPP;
649 }
650
651
652 struct target_map_ctx {
653 int *target_map;
654 int index;
655 int target_count;
656 };
657
map_targets(struct device * dev,void * data)658 static int map_targets(struct device *dev, void *data)
659 {
660 struct platform_device *pdev = to_platform_device(dev);
661 struct target_map_ctx *ctx = data;
662
663 ctx->target_map[ctx->index++] = pdev->id;
664
665 if (ctx->index > ctx->target_count) {
666 dev_WARN_ONCE(dev, 1, "too many targets found?\n");
667 return -ENXIO;
668 }
669
670 return 0;
671 }
672
mock_decoder_commit(struct cxl_decoder * cxld)673 static int mock_decoder_commit(struct cxl_decoder *cxld)
674 {
675 struct cxl_port *port = to_cxl_port(cxld->dev.parent);
676 int id = cxld->id;
677
678 if (cxld->flags & CXL_DECODER_F_ENABLE)
679 return 0;
680
681 dev_dbg(&port->dev, "%s commit\n", dev_name(&cxld->dev));
682 if (cxl_num_decoders_committed(port) != id) {
683 dev_dbg(&port->dev,
684 "%s: out of order commit, expected decoder%d.%d\n",
685 dev_name(&cxld->dev), port->id,
686 cxl_num_decoders_committed(port));
687 return -EBUSY;
688 }
689
690 port->commit_end++;
691 cxld->flags |= CXL_DECODER_F_ENABLE;
692
693 return 0;
694 }
695
mock_decoder_reset(struct cxl_decoder * cxld)696 static int mock_decoder_reset(struct cxl_decoder *cxld)
697 {
698 struct cxl_port *port = to_cxl_port(cxld->dev.parent);
699 int id = cxld->id;
700
701 if ((cxld->flags & CXL_DECODER_F_ENABLE) == 0)
702 return 0;
703
704 dev_dbg(&port->dev, "%s reset\n", dev_name(&cxld->dev));
705 if (port->commit_end != id) {
706 dev_dbg(&port->dev,
707 "%s: out of order reset, expected decoder%d.%d\n",
708 dev_name(&cxld->dev), port->id, port->commit_end);
709 return -EBUSY;
710 }
711
712 port->commit_end--;
713 cxld->flags &= ~CXL_DECODER_F_ENABLE;
714
715 return 0;
716 }
717
default_mock_decoder(struct cxl_decoder * cxld)718 static void default_mock_decoder(struct cxl_decoder *cxld)
719 {
720 cxld->hpa_range = (struct range){
721 .start = 0,
722 .end = -1,
723 };
724
725 cxld->interleave_ways = 1;
726 cxld->interleave_granularity = 256;
727 cxld->target_type = CXL_DECODER_HOSTONLYMEM;
728 cxld->commit = mock_decoder_commit;
729 cxld->reset = mock_decoder_reset;
730 }
731
first_decoder(struct device * dev,void * data)732 static int first_decoder(struct device *dev, void *data)
733 {
734 struct cxl_decoder *cxld;
735
736 if (!is_switch_decoder(dev))
737 return 0;
738 cxld = to_cxl_decoder(dev);
739 if (cxld->id == 0)
740 return 1;
741 return 0;
742 }
743
mock_init_hdm_decoder(struct cxl_decoder * cxld)744 static void mock_init_hdm_decoder(struct cxl_decoder *cxld)
745 {
746 struct acpi_cedt_cfmws *window = mock_cfmws[0];
747 struct platform_device *pdev = NULL;
748 struct cxl_endpoint_decoder *cxled;
749 struct cxl_switch_decoder *cxlsd;
750 struct cxl_port *port, *iter;
751 const int size = SZ_512M;
752 struct cxl_memdev *cxlmd;
753 struct cxl_dport *dport;
754 struct device *dev;
755 bool hb0 = false;
756 u64 base;
757 int i;
758
759 if (is_endpoint_decoder(&cxld->dev)) {
760 cxled = to_cxl_endpoint_decoder(&cxld->dev);
761 cxlmd = cxled_to_memdev(cxled);
762 WARN_ON(!dev_is_platform(cxlmd->dev.parent));
763 pdev = to_platform_device(cxlmd->dev.parent);
764
765 /* check is endpoint is attach to host-bridge0 */
766 port = cxled_to_port(cxled);
767 do {
768 if (port->uport_dev == &cxl_host_bridge[0]->dev) {
769 hb0 = true;
770 break;
771 }
772 if (is_cxl_port(port->dev.parent))
773 port = to_cxl_port(port->dev.parent);
774 else
775 port = NULL;
776 } while (port);
777 port = cxled_to_port(cxled);
778 }
779
780 /*
781 * The first decoder on the first 2 devices on the first switch
782 * attached to host-bridge0 mock a fake / static RAM region. All
783 * other decoders are default disabled. Given the round robin
784 * assignment those devices are named cxl_mem.0, and cxl_mem.4.
785 *
786 * See 'cxl list -BMPu -m cxl_mem.0,cxl_mem.4'
787 */
788 if (!hb0 || pdev->id % 4 || pdev->id > 4 || cxld->id > 0) {
789 default_mock_decoder(cxld);
790 return;
791 }
792
793 base = window->base_hpa;
794 cxld->hpa_range = (struct range) {
795 .start = base,
796 .end = base + size - 1,
797 };
798
799 cxld->interleave_ways = 2;
800 eig_to_granularity(window->granularity, &cxld->interleave_granularity);
801 cxld->target_type = CXL_DECODER_HOSTONLYMEM;
802 cxld->flags = CXL_DECODER_F_ENABLE;
803 cxled->state = CXL_DECODER_STATE_AUTO;
804 port->commit_end = cxld->id;
805 devm_cxl_dpa_reserve(cxled, 0, size / cxld->interleave_ways, 0);
806 cxld->commit = mock_decoder_commit;
807 cxld->reset = mock_decoder_reset;
808
809 /*
810 * Now that endpoint decoder is set up, walk up the hierarchy
811 * and setup the switch and root port decoders targeting @cxlmd.
812 */
813 iter = port;
814 for (i = 0; i < 2; i++) {
815 dport = iter->parent_dport;
816 iter = dport->port;
817 dev = device_find_child(&iter->dev, NULL, first_decoder);
818 /*
819 * Ancestor ports are guaranteed to be enumerated before
820 * @port, and all ports have at least one decoder.
821 */
822 if (WARN_ON(!dev))
823 continue;
824 cxlsd = to_cxl_switch_decoder(dev);
825 if (i == 0) {
826 /* put cxl_mem.4 second in the decode order */
827 if (pdev->id == 4)
828 cxlsd->target[1] = dport;
829 else
830 cxlsd->target[0] = dport;
831 } else
832 cxlsd->target[0] = dport;
833 cxld = &cxlsd->cxld;
834 cxld->target_type = CXL_DECODER_HOSTONLYMEM;
835 cxld->flags = CXL_DECODER_F_ENABLE;
836 iter->commit_end = 0;
837 /*
838 * Switch targets 2 endpoints, while host bridge targets
839 * one root port
840 */
841 if (i == 0)
842 cxld->interleave_ways = 2;
843 else
844 cxld->interleave_ways = 1;
845 cxld->interleave_granularity = 4096;
846 cxld->hpa_range = (struct range) {
847 .start = base,
848 .end = base + size - 1,
849 };
850 put_device(dev);
851 }
852 }
853
mock_cxl_enumerate_decoders(struct cxl_hdm * cxlhdm,struct cxl_endpoint_dvsec_info * info)854 static int mock_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm,
855 struct cxl_endpoint_dvsec_info *info)
856 {
857 struct cxl_port *port = cxlhdm->port;
858 struct cxl_port *parent_port = to_cxl_port(port->dev.parent);
859 int target_count, i;
860
861 if (is_cxl_endpoint(port))
862 target_count = 0;
863 else if (is_cxl_root(parent_port))
864 target_count = NR_CXL_ROOT_PORTS;
865 else
866 target_count = NR_CXL_SWITCH_PORTS;
867
868 for (i = 0; i < NR_CXL_PORT_DECODERS; i++) {
869 int target_map[CXL_DECODER_MAX_INTERLEAVE] = { 0 };
870 struct target_map_ctx ctx = {
871 .target_map = target_map,
872 .target_count = target_count,
873 };
874 struct cxl_decoder *cxld;
875 int rc;
876
877 if (target_count) {
878 struct cxl_switch_decoder *cxlsd;
879
880 cxlsd = cxl_switch_decoder_alloc(port, target_count);
881 if (IS_ERR(cxlsd)) {
882 dev_warn(&port->dev,
883 "Failed to allocate the decoder\n");
884 return PTR_ERR(cxlsd);
885 }
886 cxld = &cxlsd->cxld;
887 } else {
888 struct cxl_endpoint_decoder *cxled;
889
890 cxled = cxl_endpoint_decoder_alloc(port);
891
892 if (IS_ERR(cxled)) {
893 dev_warn(&port->dev,
894 "Failed to allocate the decoder\n");
895 return PTR_ERR(cxled);
896 }
897 cxld = &cxled->cxld;
898 }
899
900 mock_init_hdm_decoder(cxld);
901
902 if (target_count) {
903 rc = device_for_each_child(port->uport_dev, &ctx,
904 map_targets);
905 if (rc) {
906 put_device(&cxld->dev);
907 return rc;
908 }
909 }
910
911 rc = cxl_decoder_add_locked(cxld, target_map);
912 if (rc) {
913 put_device(&cxld->dev);
914 dev_err(&port->dev, "Failed to add decoder\n");
915 return rc;
916 }
917
918 rc = cxl_decoder_autoremove(&port->dev, cxld);
919 if (rc)
920 return rc;
921 dev_dbg(&cxld->dev, "Added to port %s\n", dev_name(&port->dev));
922 }
923
924 return 0;
925 }
926
mock_cxl_port_enumerate_dports(struct cxl_port * port)927 static int mock_cxl_port_enumerate_dports(struct cxl_port *port)
928 {
929 struct platform_device **array;
930 int i, array_size;
931
932 if (port->depth == 1) {
933 if (is_multi_bridge(port->uport_dev)) {
934 array_size = ARRAY_SIZE(cxl_root_port);
935 array = cxl_root_port;
936 } else if (is_single_bridge(port->uport_dev)) {
937 array_size = ARRAY_SIZE(cxl_root_single);
938 array = cxl_root_single;
939 } else {
940 dev_dbg(&port->dev, "%s: unknown bridge type\n",
941 dev_name(port->uport_dev));
942 return -ENXIO;
943 }
944 } else if (port->depth == 2) {
945 struct cxl_port *parent = to_cxl_port(port->dev.parent);
946
947 if (is_multi_bridge(parent->uport_dev)) {
948 array_size = ARRAY_SIZE(cxl_switch_dport);
949 array = cxl_switch_dport;
950 } else if (is_single_bridge(parent->uport_dev)) {
951 array_size = ARRAY_SIZE(cxl_swd_single);
952 array = cxl_swd_single;
953 } else {
954 dev_dbg(&port->dev, "%s: unknown bridge type\n",
955 dev_name(port->uport_dev));
956 return -ENXIO;
957 }
958 } else {
959 dev_WARN_ONCE(&port->dev, 1, "unexpected depth %d\n",
960 port->depth);
961 return -ENXIO;
962 }
963
964 for (i = 0; i < array_size; i++) {
965 struct platform_device *pdev = array[i];
966 struct cxl_dport *dport;
967
968 if (pdev->dev.parent != port->uport_dev) {
969 dev_dbg(&port->dev, "%s: mismatch parent %s\n",
970 dev_name(port->uport_dev),
971 dev_name(pdev->dev.parent));
972 continue;
973 }
974
975 dport = devm_cxl_add_dport(port, &pdev->dev, pdev->id,
976 CXL_RESOURCE_NONE);
977
978 if (IS_ERR(dport))
979 return PTR_ERR(dport);
980 }
981
982 return 0;
983 }
984
985 /*
986 * Faking the cxl_dpa_perf for the memdev when appropriate.
987 */
dpa_perf_setup(struct cxl_port * endpoint,struct range * range,struct cxl_dpa_perf * dpa_perf)988 static void dpa_perf_setup(struct cxl_port *endpoint, struct range *range,
989 struct cxl_dpa_perf *dpa_perf)
990 {
991 dpa_perf->qos_class = FAKE_QTG_ID;
992 dpa_perf->dpa_range = *range;
993 for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
994 dpa_perf->coord[i].read_latency = 500;
995 dpa_perf->coord[i].write_latency = 500;
996 dpa_perf->coord[i].read_bandwidth = 1000;
997 dpa_perf->coord[i].write_bandwidth = 1000;
998 }
999 }
1000
mock_cxl_endpoint_parse_cdat(struct cxl_port * port)1001 static void mock_cxl_endpoint_parse_cdat(struct cxl_port *port)
1002 {
1003 struct cxl_root *cxl_root __free(put_cxl_root) =
1004 find_cxl_root(port);
1005 struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
1006 struct cxl_dev_state *cxlds = cxlmd->cxlds;
1007 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
1008 struct access_coordinate ep_c[ACCESS_COORDINATE_MAX];
1009 struct range pmem_range = {
1010 .start = cxlds->pmem_res.start,
1011 .end = cxlds->pmem_res.end,
1012 };
1013 struct range ram_range = {
1014 .start = cxlds->ram_res.start,
1015 .end = cxlds->ram_res.end,
1016 };
1017
1018 if (!cxl_root)
1019 return;
1020
1021 if (range_len(&ram_range))
1022 dpa_perf_setup(port, &ram_range, &mds->ram_perf);
1023
1024 if (range_len(&pmem_range))
1025 dpa_perf_setup(port, &pmem_range, &mds->pmem_perf);
1026
1027 cxl_memdev_update_perf(cxlmd);
1028
1029 /*
1030 * This function is here to only test the topology iterator. It serves
1031 * no other purpose.
1032 */
1033 cxl_endpoint_get_perf_coordinates(port, ep_c);
1034 }
1035
1036 static struct cxl_mock_ops cxl_mock_ops = {
1037 .is_mock_adev = is_mock_adev,
1038 .is_mock_bridge = is_mock_bridge,
1039 .is_mock_bus = is_mock_bus,
1040 .is_mock_port = is_mock_port,
1041 .is_mock_dev = is_mock_dev,
1042 .acpi_table_parse_cedt = mock_acpi_table_parse_cedt,
1043 .acpi_evaluate_integer = mock_acpi_evaluate_integer,
1044 .acpi_pci_find_root = mock_acpi_pci_find_root,
1045 .devm_cxl_port_enumerate_dports = mock_cxl_port_enumerate_dports,
1046 .devm_cxl_setup_hdm = mock_cxl_setup_hdm,
1047 .devm_cxl_add_passthrough_decoder = mock_cxl_add_passthrough_decoder,
1048 .devm_cxl_enumerate_decoders = mock_cxl_enumerate_decoders,
1049 .cxl_endpoint_parse_cdat = mock_cxl_endpoint_parse_cdat,
1050 .list = LIST_HEAD_INIT(cxl_mock_ops.list),
1051 };
1052
mock_companion(struct acpi_device * adev,struct device * dev)1053 static void mock_companion(struct acpi_device *adev, struct device *dev)
1054 {
1055 device_initialize(&adev->dev);
1056 fwnode_init(&adev->fwnode, NULL);
1057 dev->fwnode = &adev->fwnode;
1058 adev->fwnode.dev = dev;
1059 }
1060
1061 #ifndef SZ_64G
1062 #define SZ_64G (SZ_32G * 2)
1063 #endif
1064
cxl_rch_init(void)1065 static __init int cxl_rch_init(void)
1066 {
1067 int rc, i;
1068
1069 for (i = 0; i < ARRAY_SIZE(cxl_rch); i++) {
1070 int idx = NR_CXL_HOST_BRIDGES + NR_CXL_SINGLE_HOST + i;
1071 struct acpi_device *adev = &host_bridge[idx];
1072 struct platform_device *pdev;
1073
1074 pdev = platform_device_alloc("cxl_host_bridge", idx);
1075 if (!pdev)
1076 goto err_bridge;
1077
1078 mock_companion(adev, &pdev->dev);
1079 rc = platform_device_add(pdev);
1080 if (rc) {
1081 platform_device_put(pdev);
1082 goto err_bridge;
1083 }
1084
1085 cxl_rch[i] = pdev;
1086 mock_pci_bus[idx].bridge = &pdev->dev;
1087 rc = sysfs_create_link(&pdev->dev.kobj, &pdev->dev.kobj,
1088 "firmware_node");
1089 if (rc)
1090 goto err_bridge;
1091 }
1092
1093 for (i = 0; i < ARRAY_SIZE(cxl_rcd); i++) {
1094 int idx = NR_MEM_MULTI + NR_MEM_SINGLE + i;
1095 struct platform_device *rch = cxl_rch[i];
1096 struct platform_device *pdev;
1097
1098 pdev = platform_device_alloc("cxl_rcd", idx);
1099 if (!pdev)
1100 goto err_mem;
1101 pdev->dev.parent = &rch->dev;
1102 set_dev_node(&pdev->dev, i % 2);
1103
1104 rc = platform_device_add(pdev);
1105 if (rc) {
1106 platform_device_put(pdev);
1107 goto err_mem;
1108 }
1109 cxl_rcd[i] = pdev;
1110 }
1111
1112 return 0;
1113
1114 err_mem:
1115 for (i = ARRAY_SIZE(cxl_rcd) - 1; i >= 0; i--)
1116 platform_device_unregister(cxl_rcd[i]);
1117 err_bridge:
1118 for (i = ARRAY_SIZE(cxl_rch) - 1; i >= 0; i--) {
1119 struct platform_device *pdev = cxl_rch[i];
1120
1121 if (!pdev)
1122 continue;
1123 sysfs_remove_link(&pdev->dev.kobj, "firmware_node");
1124 platform_device_unregister(cxl_rch[i]);
1125 }
1126
1127 return rc;
1128 }
1129
cxl_rch_exit(void)1130 static void cxl_rch_exit(void)
1131 {
1132 int i;
1133
1134 for (i = ARRAY_SIZE(cxl_rcd) - 1; i >= 0; i--)
1135 platform_device_unregister(cxl_rcd[i]);
1136 for (i = ARRAY_SIZE(cxl_rch) - 1; i >= 0; i--) {
1137 struct platform_device *pdev = cxl_rch[i];
1138
1139 if (!pdev)
1140 continue;
1141 sysfs_remove_link(&pdev->dev.kobj, "firmware_node");
1142 platform_device_unregister(cxl_rch[i]);
1143 }
1144 }
1145
cxl_single_init(void)1146 static __init int cxl_single_init(void)
1147 {
1148 int i, rc;
1149
1150 for (i = 0; i < ARRAY_SIZE(cxl_hb_single); i++) {
1151 struct acpi_device *adev =
1152 &host_bridge[NR_CXL_HOST_BRIDGES + i];
1153 struct platform_device *pdev;
1154
1155 pdev = platform_device_alloc("cxl_host_bridge",
1156 NR_CXL_HOST_BRIDGES + i);
1157 if (!pdev)
1158 goto err_bridge;
1159
1160 mock_companion(adev, &pdev->dev);
1161 rc = platform_device_add(pdev);
1162 if (rc) {
1163 platform_device_put(pdev);
1164 goto err_bridge;
1165 }
1166
1167 cxl_hb_single[i] = pdev;
1168 mock_pci_bus[i + NR_CXL_HOST_BRIDGES].bridge = &pdev->dev;
1169 rc = sysfs_create_link(&pdev->dev.kobj, &pdev->dev.kobj,
1170 "physical_node");
1171 if (rc)
1172 goto err_bridge;
1173 }
1174
1175 for (i = 0; i < ARRAY_SIZE(cxl_root_single); i++) {
1176 struct platform_device *bridge =
1177 cxl_hb_single[i % ARRAY_SIZE(cxl_hb_single)];
1178 struct platform_device *pdev;
1179
1180 pdev = platform_device_alloc("cxl_root_port",
1181 NR_MULTI_ROOT + i);
1182 if (!pdev)
1183 goto err_port;
1184 pdev->dev.parent = &bridge->dev;
1185
1186 rc = platform_device_add(pdev);
1187 if (rc) {
1188 platform_device_put(pdev);
1189 goto err_port;
1190 }
1191 cxl_root_single[i] = pdev;
1192 }
1193
1194 for (i = 0; i < ARRAY_SIZE(cxl_swu_single); i++) {
1195 struct platform_device *root_port = cxl_root_single[i];
1196 struct platform_device *pdev;
1197
1198 pdev = platform_device_alloc("cxl_switch_uport",
1199 NR_MULTI_ROOT + i);
1200 if (!pdev)
1201 goto err_uport;
1202 pdev->dev.parent = &root_port->dev;
1203
1204 rc = platform_device_add(pdev);
1205 if (rc) {
1206 platform_device_put(pdev);
1207 goto err_uport;
1208 }
1209 cxl_swu_single[i] = pdev;
1210 }
1211
1212 for (i = 0; i < ARRAY_SIZE(cxl_swd_single); i++) {
1213 struct platform_device *uport =
1214 cxl_swu_single[i % ARRAY_SIZE(cxl_swu_single)];
1215 struct platform_device *pdev;
1216
1217 pdev = platform_device_alloc("cxl_switch_dport",
1218 i + NR_MEM_MULTI);
1219 if (!pdev)
1220 goto err_dport;
1221 pdev->dev.parent = &uport->dev;
1222
1223 rc = platform_device_add(pdev);
1224 if (rc) {
1225 platform_device_put(pdev);
1226 goto err_dport;
1227 }
1228 cxl_swd_single[i] = pdev;
1229 }
1230
1231 for (i = 0; i < ARRAY_SIZE(cxl_mem_single); i++) {
1232 struct platform_device *dport = cxl_swd_single[i];
1233 struct platform_device *pdev;
1234
1235 pdev = platform_device_alloc("cxl_mem", NR_MEM_MULTI + i);
1236 if (!pdev)
1237 goto err_mem;
1238 pdev->dev.parent = &dport->dev;
1239 set_dev_node(&pdev->dev, i % 2);
1240
1241 rc = platform_device_add(pdev);
1242 if (rc) {
1243 platform_device_put(pdev);
1244 goto err_mem;
1245 }
1246 cxl_mem_single[i] = pdev;
1247 }
1248
1249 return 0;
1250
1251 err_mem:
1252 for (i = ARRAY_SIZE(cxl_mem_single) - 1; i >= 0; i--)
1253 platform_device_unregister(cxl_mem_single[i]);
1254 err_dport:
1255 for (i = ARRAY_SIZE(cxl_swd_single) - 1; i >= 0; i--)
1256 platform_device_unregister(cxl_swd_single[i]);
1257 err_uport:
1258 for (i = ARRAY_SIZE(cxl_swu_single) - 1; i >= 0; i--)
1259 platform_device_unregister(cxl_swu_single[i]);
1260 err_port:
1261 for (i = ARRAY_SIZE(cxl_root_single) - 1; i >= 0; i--)
1262 platform_device_unregister(cxl_root_single[i]);
1263 err_bridge:
1264 for (i = ARRAY_SIZE(cxl_hb_single) - 1; i >= 0; i--) {
1265 struct platform_device *pdev = cxl_hb_single[i];
1266
1267 if (!pdev)
1268 continue;
1269 sysfs_remove_link(&pdev->dev.kobj, "physical_node");
1270 platform_device_unregister(cxl_hb_single[i]);
1271 }
1272
1273 return rc;
1274 }
1275
cxl_single_exit(void)1276 static void cxl_single_exit(void)
1277 {
1278 int i;
1279
1280 for (i = ARRAY_SIZE(cxl_mem_single) - 1; i >= 0; i--)
1281 platform_device_unregister(cxl_mem_single[i]);
1282 for (i = ARRAY_SIZE(cxl_swd_single) - 1; i >= 0; i--)
1283 platform_device_unregister(cxl_swd_single[i]);
1284 for (i = ARRAY_SIZE(cxl_swu_single) - 1; i >= 0; i--)
1285 platform_device_unregister(cxl_swu_single[i]);
1286 for (i = ARRAY_SIZE(cxl_root_single) - 1; i >= 0; i--)
1287 platform_device_unregister(cxl_root_single[i]);
1288 for (i = ARRAY_SIZE(cxl_hb_single) - 1; i >= 0; i--) {
1289 struct platform_device *pdev = cxl_hb_single[i];
1290
1291 if (!pdev)
1292 continue;
1293 sysfs_remove_link(&pdev->dev.kobj, "physical_node");
1294 platform_device_unregister(cxl_hb_single[i]);
1295 }
1296 }
1297
cxl_test_init(void)1298 static __init int cxl_test_init(void)
1299 {
1300 int rc, i;
1301
1302 cxl_acpi_test();
1303 cxl_core_test();
1304 cxl_mem_test();
1305 cxl_pmem_test();
1306 cxl_port_test();
1307
1308 register_cxl_mock_ops(&cxl_mock_ops);
1309
1310 cxl_mock_pool = gen_pool_create(ilog2(SZ_2M), NUMA_NO_NODE);
1311 if (!cxl_mock_pool) {
1312 rc = -ENOMEM;
1313 goto err_gen_pool_create;
1314 }
1315
1316 rc = gen_pool_add(cxl_mock_pool, iomem_resource.end + 1 - SZ_64G,
1317 SZ_64G, NUMA_NO_NODE);
1318 if (rc)
1319 goto err_gen_pool_add;
1320
1321 if (interleave_arithmetic == 1) {
1322 cfmws_start = CFMWS_XOR_ARRAY_START;
1323 cfmws_end = CFMWS_XOR_ARRAY_END;
1324 } else {
1325 cfmws_start = CFMWS_MOD_ARRAY_START;
1326 cfmws_end = CFMWS_MOD_ARRAY_END;
1327 }
1328
1329 rc = populate_cedt();
1330 if (rc)
1331 goto err_populate;
1332
1333 for (i = 0; i < ARRAY_SIZE(cxl_host_bridge); i++) {
1334 struct acpi_device *adev = &host_bridge[i];
1335 struct platform_device *pdev;
1336
1337 pdev = platform_device_alloc("cxl_host_bridge", i);
1338 if (!pdev)
1339 goto err_bridge;
1340
1341 mock_companion(adev, &pdev->dev);
1342 rc = platform_device_add(pdev);
1343 if (rc) {
1344 platform_device_put(pdev);
1345 goto err_bridge;
1346 }
1347
1348 cxl_host_bridge[i] = pdev;
1349 mock_pci_bus[i].bridge = &pdev->dev;
1350 rc = sysfs_create_link(&pdev->dev.kobj, &pdev->dev.kobj,
1351 "physical_node");
1352 if (rc)
1353 goto err_bridge;
1354 }
1355
1356 for (i = 0; i < ARRAY_SIZE(cxl_root_port); i++) {
1357 struct platform_device *bridge =
1358 cxl_host_bridge[i % ARRAY_SIZE(cxl_host_bridge)];
1359 struct platform_device *pdev;
1360
1361 pdev = platform_device_alloc("cxl_root_port", i);
1362 if (!pdev)
1363 goto err_port;
1364 pdev->dev.parent = &bridge->dev;
1365
1366 rc = platform_device_add(pdev);
1367 if (rc) {
1368 platform_device_put(pdev);
1369 goto err_port;
1370 }
1371 cxl_root_port[i] = pdev;
1372 }
1373
1374 BUILD_BUG_ON(ARRAY_SIZE(cxl_switch_uport) != ARRAY_SIZE(cxl_root_port));
1375 for (i = 0; i < ARRAY_SIZE(cxl_switch_uport); i++) {
1376 struct platform_device *root_port = cxl_root_port[i];
1377 struct platform_device *pdev;
1378
1379 pdev = platform_device_alloc("cxl_switch_uport", i);
1380 if (!pdev)
1381 goto err_uport;
1382 pdev->dev.parent = &root_port->dev;
1383
1384 rc = platform_device_add(pdev);
1385 if (rc) {
1386 platform_device_put(pdev);
1387 goto err_uport;
1388 }
1389 cxl_switch_uport[i] = pdev;
1390 }
1391
1392 for (i = 0; i < ARRAY_SIZE(cxl_switch_dport); i++) {
1393 struct platform_device *uport =
1394 cxl_switch_uport[i % ARRAY_SIZE(cxl_switch_uport)];
1395 struct platform_device *pdev;
1396
1397 pdev = platform_device_alloc("cxl_switch_dport", i);
1398 if (!pdev)
1399 goto err_dport;
1400 pdev->dev.parent = &uport->dev;
1401
1402 rc = platform_device_add(pdev);
1403 if (rc) {
1404 platform_device_put(pdev);
1405 goto err_dport;
1406 }
1407 cxl_switch_dport[i] = pdev;
1408 }
1409
1410 for (i = 0; i < ARRAY_SIZE(cxl_mem); i++) {
1411 struct platform_device *dport = cxl_switch_dport[i];
1412 struct platform_device *pdev;
1413
1414 pdev = platform_device_alloc("cxl_mem", i);
1415 if (!pdev)
1416 goto err_mem;
1417 pdev->dev.parent = &dport->dev;
1418 set_dev_node(&pdev->dev, i % 2);
1419
1420 rc = platform_device_add(pdev);
1421 if (rc) {
1422 platform_device_put(pdev);
1423 goto err_mem;
1424 }
1425 cxl_mem[i] = pdev;
1426 }
1427
1428 rc = cxl_single_init();
1429 if (rc)
1430 goto err_mem;
1431
1432 rc = cxl_rch_init();
1433 if (rc)
1434 goto err_single;
1435
1436 cxl_acpi = platform_device_alloc("cxl_acpi", 0);
1437 if (!cxl_acpi)
1438 goto err_rch;
1439
1440 mock_companion(&acpi0017_mock, &cxl_acpi->dev);
1441 acpi0017_mock.dev.bus = &platform_bus_type;
1442
1443 rc = platform_device_add(cxl_acpi);
1444 if (rc)
1445 goto err_add;
1446
1447 return 0;
1448
1449 err_add:
1450 platform_device_put(cxl_acpi);
1451 err_rch:
1452 cxl_rch_exit();
1453 err_single:
1454 cxl_single_exit();
1455 err_mem:
1456 for (i = ARRAY_SIZE(cxl_mem) - 1; i >= 0; i--)
1457 platform_device_unregister(cxl_mem[i]);
1458 err_dport:
1459 for (i = ARRAY_SIZE(cxl_switch_dport) - 1; i >= 0; i--)
1460 platform_device_unregister(cxl_switch_dport[i]);
1461 err_uport:
1462 for (i = ARRAY_SIZE(cxl_switch_uport) - 1; i >= 0; i--)
1463 platform_device_unregister(cxl_switch_uport[i]);
1464 err_port:
1465 for (i = ARRAY_SIZE(cxl_root_port) - 1; i >= 0; i--)
1466 platform_device_unregister(cxl_root_port[i]);
1467 err_bridge:
1468 for (i = ARRAY_SIZE(cxl_host_bridge) - 1; i >= 0; i--) {
1469 struct platform_device *pdev = cxl_host_bridge[i];
1470
1471 if (!pdev)
1472 continue;
1473 sysfs_remove_link(&pdev->dev.kobj, "physical_node");
1474 platform_device_unregister(cxl_host_bridge[i]);
1475 }
1476 err_populate:
1477 depopulate_all_mock_resources();
1478 err_gen_pool_add:
1479 gen_pool_destroy(cxl_mock_pool);
1480 err_gen_pool_create:
1481 unregister_cxl_mock_ops(&cxl_mock_ops);
1482 return rc;
1483 }
1484
cxl_test_exit(void)1485 static __exit void cxl_test_exit(void)
1486 {
1487 int i;
1488
1489 platform_device_unregister(cxl_acpi);
1490 cxl_rch_exit();
1491 cxl_single_exit();
1492 for (i = ARRAY_SIZE(cxl_mem) - 1; i >= 0; i--)
1493 platform_device_unregister(cxl_mem[i]);
1494 for (i = ARRAY_SIZE(cxl_switch_dport) - 1; i >= 0; i--)
1495 platform_device_unregister(cxl_switch_dport[i]);
1496 for (i = ARRAY_SIZE(cxl_switch_uport) - 1; i >= 0; i--)
1497 platform_device_unregister(cxl_switch_uport[i]);
1498 for (i = ARRAY_SIZE(cxl_root_port) - 1; i >= 0; i--)
1499 platform_device_unregister(cxl_root_port[i]);
1500 for (i = ARRAY_SIZE(cxl_host_bridge) - 1; i >= 0; i--) {
1501 struct platform_device *pdev = cxl_host_bridge[i];
1502
1503 if (!pdev)
1504 continue;
1505 sysfs_remove_link(&pdev->dev.kobj, "physical_node");
1506 platform_device_unregister(cxl_host_bridge[i]);
1507 }
1508 depopulate_all_mock_resources();
1509 gen_pool_destroy(cxl_mock_pool);
1510 unregister_cxl_mock_ops(&cxl_mock_ops);
1511 }
1512
1513 module_param(interleave_arithmetic, int, 0444);
1514 MODULE_PARM_DESC(interleave_arithmetic, "Modulo:0, XOR:1");
1515 module_init(cxl_test_init);
1516 module_exit(cxl_test_exit);
1517 MODULE_LICENSE("GPL v2");
1518 MODULE_IMPORT_NS(ACPI);
1519 MODULE_IMPORT_NS(CXL);
1520