1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * DPAA2 Ethernet Switch declarations
4 *
5 * Copyright 2014-2016 Freescale Semiconductor Inc.
6 * Copyright 2017-2021 NXP
7 *
8 */
9
10 #ifndef __ETHSW_H
11 #define __ETHSW_H
12
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/rtnetlink.h>
16 #include <linux/if_vlan.h>
17 #include <uapi/linux/if_bridge.h>
18 #include <net/switchdev.h>
19 #include <linux/if_bridge.h>
20 #include <linux/fsl/mc.h>
21 #include <net/pkt_cls.h>
22 #include <soc/fsl/dpaa2-io.h>
23
24 #include "dpaa2-mac.h"
25 #include "dpsw.h"
26
27 /* Number of IRQs supported */
28 #define DPSW_IRQ_NUM 2
29
30 /* Port is member of VLAN */
31 #define ETHSW_VLAN_MEMBER 1
32 /* VLAN to be treated as untagged on egress */
33 #define ETHSW_VLAN_UNTAGGED 2
34 /* Untagged frames will be assigned to this VLAN */
35 #define ETHSW_VLAN_PVID 4
36 /* VLAN configured on the switch */
37 #define ETHSW_VLAN_GLOBAL 8
38
39 /* Maximum Frame Length supported by HW (currently 10k) */
40 #define DPAA2_MFL (10 * 1024)
41 #define ETHSW_MAX_FRAME_LENGTH (DPAA2_MFL - VLAN_ETH_HLEN - ETH_FCS_LEN)
42 #define ETHSW_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN + ETH_FCS_LEN)
43
44 #define ETHSW_FEATURE_MAC_ADDR BIT(0)
45 #define ETHSW_FEATURE_LAG_OFFLOAD BIT(1)
46
47 /* Number of receive queues (one RX and one TX_CONF) */
48 #define DPAA2_SWITCH_RX_NUM_FQS 2
49
50 /* Hardware requires alignment for ingress/egress buffer addresses */
51 #define DPAA2_SWITCH_RX_BUF_RAW_SIZE PAGE_SIZE
52 #define DPAA2_SWITCH_RX_BUF_TAILROOM \
53 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
54 #define DPAA2_SWITCH_RX_BUF_SIZE \
55 (DPAA2_SWITCH_RX_BUF_RAW_SIZE - DPAA2_SWITCH_RX_BUF_TAILROOM)
56
57 #define DPAA2_SWITCH_STORE_SIZE 16
58
59 /* Buffer management */
60 #define BUFS_PER_CMD 7
61 #define DPAA2_ETHSW_NUM_BUFS (1024 * BUFS_PER_CMD)
62 #define DPAA2_ETHSW_REFILL_THRESH (DPAA2_ETHSW_NUM_BUFS * 5 / 6)
63
64 /* Number of times to retry DPIO portal operations while waiting
65 * for portal to finish executing current command and become
66 * available. We want to avoid being stuck in a while loop in case
67 * hardware becomes unresponsive, but not give up too easily if
68 * the portal really is busy for valid reasons
69 */
70 #define DPAA2_SWITCH_SWP_BUSY_RETRIES 1000
71
72 /* Hardware annotation buffer size */
73 #define DPAA2_SWITCH_HWA_SIZE 64
74 /* Software annotation buffer size */
75 #define DPAA2_SWITCH_SWA_SIZE 64
76
77 #define DPAA2_SWITCH_TX_BUF_ALIGN 64
78
79 #define DPAA2_SWITCH_TX_DATA_OFFSET \
80 (DPAA2_SWITCH_HWA_SIZE + DPAA2_SWITCH_SWA_SIZE)
81
82 #define DPAA2_SWITCH_NEEDED_HEADROOM \
83 (DPAA2_SWITCH_TX_DATA_OFFSET + DPAA2_SWITCH_TX_BUF_ALIGN)
84
85 #define DPAA2_ETHSW_PORT_MAX_ACL_ENTRIES 16
86 #define DPAA2_ETHSW_PORT_DEFAULT_TRAPS 1
87
88 #define DPAA2_ETHSW_PORT_ACL_CMD_BUF_SIZE 256
89
90 #define DPAA2_ETHSW_FLC_IF_ID(flc) (((flc) >> 32) & GENMASK(15, 0))
91 #define DPAA2_ETHSW_FLC_IMPRECISE_IF_ID(flc) ((flc) & BIT_ULL(63))
92
93 extern const struct ethtool_ops dpaa2_switch_port_ethtool_ops;
94
95 struct ethsw_core;
96
97 struct dpaa2_switch_fq {
98 struct ethsw_core *ethsw;
99 enum dpsw_queue_type type;
100 struct dpaa2_io_store *store;
101 struct dpaa2_io_notification_ctx nctx;
102 struct napi_struct napi;
103 u32 fqid;
104 };
105
106 struct dpaa2_mac_addr {
107 unsigned char addr[ETH_ALEN];
108 u16 vid;
109 refcount_t refcount;
110 struct list_head list;
111 };
112
113 struct dpaa2_switch_fdb {
114 struct net_device *bridge_dev;
115 u16 fdb_id;
116 bool in_use;
117 };
118
119 struct dpaa2_switch_lag {
120 struct ethsw_core *ethsw;
121 struct net_device *bond_dev;
122 bool in_use;
123 u8 id;
124 struct ethsw_port_priv *primary;
125 /* Protects the list of fdbs installed on this LAG */
126 struct mutex fdb_lock;
127 struct list_head fdbs;
128 };
129
130 struct dpaa2_switch_acl_entry {
131 struct list_head list;
132 u16 prio;
133 unsigned long cookie;
134
135 struct dpsw_acl_entry_cfg cfg;
136 struct dpsw_acl_key key;
137 };
138
139 struct dpaa2_switch_mirror_entry {
140 struct list_head list;
141 struct dpsw_reflection_cfg cfg;
142 unsigned long cookie;
143 u16 if_id;
144 };
145
146 struct dpaa2_switch_filter_block {
147 struct ethsw_core *ethsw;
148 u64 ports;
149 bool in_use;
150
151 struct list_head acl_entries;
152 u16 acl_id;
153 u8 num_acl_rules;
154
155 struct list_head mirror_entries;
156 };
157
158 static inline bool
dpaa2_switch_acl_tbl_is_full(struct dpaa2_switch_filter_block * filter_block)159 dpaa2_switch_acl_tbl_is_full(struct dpaa2_switch_filter_block *filter_block)
160 {
161 if ((filter_block->num_acl_rules + DPAA2_ETHSW_PORT_DEFAULT_TRAPS) >=
162 DPAA2_ETHSW_PORT_MAX_ACL_ENTRIES)
163 return true;
164 return false;
165 }
166
167 /* Per port private data */
168 struct ethsw_port_priv {
169 struct net_device *netdev;
170 u16 idx;
171 struct ethsw_core *ethsw_data;
172 u8 link_state;
173 u8 stp_state;
174
175 u8 vlans[VLAN_VID_MASK + 1];
176 u16 pvid;
177 u16 tx_qdid;
178
179 struct dpaa2_switch_fdb *fdb;
180 bool bcast_flood;
181 bool ucast_flood;
182 bool learn_ena;
183
184 struct dpaa2_switch_filter_block *filter_block;
185 struct dpaa2_mac *mac;
186 /* Protects against changes to port_priv->mac */
187 struct mutex mac_lock;
188
189 struct dpaa2_switch_lag __rcu *lag;
190 };
191
192 /* Switch data */
193 struct ethsw_core {
194 struct device *dev;
195 struct fsl_mc_io *mc_io;
196 u16 dpsw_handle;
197 struct dpsw_attr sw_attr;
198 u16 major, minor;
199 unsigned long features;
200 int dev_id;
201 struct ethsw_port_priv **ports;
202 struct iommu_domain *iommu_domain;
203
204 u8 vlans[VLAN_VID_MASK + 1];
205
206 struct workqueue_struct *workqueue;
207
208 struct dpaa2_switch_fq fq[DPAA2_SWITCH_RX_NUM_FQS];
209 struct fsl_mc_device *dpbp_dev;
210 int buf_count;
211 u16 bpid;
212 int napi_users;
213
214 struct dpaa2_switch_fdb *fdbs;
215 struct dpaa2_switch_filter_block *filter_blocks;
216 u16 mirror_port;
217
218 struct dpaa2_switch_lag *lags;
219 };
220
dpaa2_switch_get_index(struct ethsw_core * ethsw,struct net_device * netdev)221 static inline int dpaa2_switch_get_index(struct ethsw_core *ethsw,
222 struct net_device *netdev)
223 {
224 int i;
225
226 for (i = 0; i < ethsw->sw_attr.num_ifs; i++)
227 if (ethsw->ports[i]->netdev == netdev)
228 return ethsw->ports[i]->idx;
229
230 return -EINVAL;
231 }
232
dpaa2_switch_supports_cpu_traffic(struct ethsw_core * ethsw)233 static inline bool dpaa2_switch_supports_cpu_traffic(struct ethsw_core *ethsw)
234 {
235 if (ethsw->sw_attr.options & DPSW_OPT_CTRL_IF_DIS) {
236 dev_err(ethsw->dev, "Control Interface is disabled, cannot probe\n");
237 return false;
238 }
239
240 if (ethsw->sw_attr.flooding_cfg != DPSW_FLOODING_PER_FDB) {
241 dev_err(ethsw->dev, "Flooding domain is not per FDB, cannot probe\n");
242 return false;
243 }
244
245 if (ethsw->sw_attr.broadcast_cfg != DPSW_BROADCAST_PER_FDB) {
246 dev_err(ethsw->dev, "Broadcast domain is not per FDB, cannot probe\n");
247 return false;
248 }
249
250 if (ethsw->sw_attr.max_fdbs < ethsw->sw_attr.num_ifs) {
251 dev_err(ethsw->dev, "The number of FDBs is lower than the number of ports, cannot probe\n");
252 return false;
253 }
254
255 return true;
256 }
257
258 static inline bool
dpaa2_switch_port_is_type_phy(struct ethsw_port_priv * port_priv)259 dpaa2_switch_port_is_type_phy(struct ethsw_port_priv *port_priv)
260 {
261 return dpaa2_mac_is_type_phy(port_priv->mac);
262 }
263
dpaa2_switch_port_has_mac(struct ethsw_port_priv * port_priv)264 static inline bool dpaa2_switch_port_has_mac(struct ethsw_port_priv *port_priv)
265 {
266 return port_priv->mac ? true : false;
267 }
268
269 bool dpaa2_switch_port_dev_check(const struct net_device *netdev);
270
271 int dpaa2_switch_port_vlans_add(struct net_device *netdev,
272 const struct switchdev_obj_port_vlan *vlan);
273
274 int dpaa2_switch_port_vlans_del(struct net_device *netdev,
275 const struct switchdev_obj_port_vlan *vlan);
276
277 typedef int dpaa2_switch_fdb_cb_t(struct ethsw_port_priv *port_priv,
278 struct fdb_dump_entry *fdb_entry,
279 void *data);
280
281 /* TC offload */
282
283 int dpaa2_switch_cls_flower_replace(struct dpaa2_switch_filter_block *block,
284 struct flow_cls_offload *cls);
285
286 int dpaa2_switch_cls_flower_destroy(struct dpaa2_switch_filter_block *block,
287 struct flow_cls_offload *cls);
288
289 int dpaa2_switch_cls_matchall_replace(struct dpaa2_switch_filter_block *block,
290 struct tc_cls_matchall_offload *cls);
291
292 int dpaa2_switch_cls_matchall_destroy(struct dpaa2_switch_filter_block *block,
293 struct tc_cls_matchall_offload *cls);
294
295 int dpaa2_switch_acl_entry_add(struct dpaa2_switch_filter_block *block,
296 struct dpaa2_switch_acl_entry *entry);
297
298 int dpaa2_switch_block_offload_mirror(struct dpaa2_switch_filter_block *block,
299 struct ethsw_port_priv *port_priv);
300
301 int dpaa2_switch_block_unoffload_mirror(struct dpaa2_switch_filter_block *block,
302 struct ethsw_port_priv *port_priv);
303
304 static inline bool
dpaa2_switch_port_offloads_bridge_port(struct ethsw_port_priv * port_priv,const struct net_device * dev)305 dpaa2_switch_port_offloads_bridge_port(struct ethsw_port_priv *port_priv,
306 const struct net_device *dev)
307 {
308 struct dpaa2_switch_lag *lag = rcu_dereference_rtnl(port_priv->lag);
309
310 if (lag && lag->bond_dev == dev)
311 return true;
312 if (port_priv->netdev == dev)
313 return true;
314 return false;
315 }
316
317 #endif /* __ETHSW_H */
318