1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 #include <linux/irqchip/arm-gic-v3.h> 21 22 #include <asm/arm_pmuv3.h> 23 #include <asm/cacheflush.h> 24 #include <asm/cputype.h> 25 #include <asm/debug-monitors.h> 26 #include <asm/esr.h> 27 #include <asm/kvm_arm.h> 28 #include <asm/kvm_emulate.h> 29 #include <asm/kvm_hyp.h> 30 #include <asm/kvm_mmu.h> 31 #include <asm/kvm_nested.h> 32 #include <asm/perf_event.h> 33 #include <asm/sysreg.h> 34 35 #include <trace/events/kvm.h> 36 37 #include "sys_regs.h" 38 #include "vgic/vgic.h" 39 40 #include "trace.h" 41 42 /* 43 * For AArch32, we only take care of what is being trapped. Anything 44 * that has to do with init and userspace access has to go via the 45 * 64bit interface. 46 */ 47 48 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 49 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 50 u64 val); 51 52 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 53 const struct sys_reg_desc *r) 54 { 55 kvm_inject_undefined(vcpu); 56 return false; 57 } 58 59 static bool bad_trap(struct kvm_vcpu *vcpu, 60 struct sys_reg_params *params, 61 const struct sys_reg_desc *r, 62 const char *msg) 63 { 64 WARN_ONCE(1, "Unexpected %s\n", msg); 65 print_sys_reg_instr(params); 66 return undef_access(vcpu, params, r); 67 } 68 69 static bool read_from_write_only(struct kvm_vcpu *vcpu, 70 struct sys_reg_params *params, 71 const struct sys_reg_desc *r) 72 { 73 return bad_trap(vcpu, params, r, 74 "sys_reg read to write-only register"); 75 } 76 77 static bool write_to_read_only(struct kvm_vcpu *vcpu, 78 struct sys_reg_params *params, 79 const struct sys_reg_desc *r) 80 { 81 return bad_trap(vcpu, params, r, 82 "sys_reg write to read-only register"); 83 } 84 85 enum sr_loc_attr { 86 SR_LOC_MEMORY = 0, /* Register definitely in memory */ 87 SR_LOC_LOADED = BIT(0), /* Register on CPU, unless it cannot */ 88 SR_LOC_MAPPED = BIT(1), /* Register in a different CPU register */ 89 SR_LOC_XLATED = BIT(2), /* Register translated to fit another reg */ 90 SR_LOC_SPECIAL = BIT(3), /* Demanding register, implies loaded */ 91 }; 92 93 struct sr_loc { 94 enum sr_loc_attr loc; 95 enum vcpu_sysreg map_reg; 96 u64 (*xlate)(u64); 97 }; 98 99 static enum sr_loc_attr locate_direct_register(const struct kvm_vcpu *vcpu, 100 enum vcpu_sysreg reg) 101 { 102 switch (reg) { 103 case SCTLR_EL1: 104 case CPACR_EL1: 105 case TTBR0_EL1: 106 case TTBR1_EL1: 107 case TCR_EL1: 108 case TCR2_EL1: 109 case PIR_EL1: 110 case PIRE0_EL1: 111 case POR_EL1: 112 case ESR_EL1: 113 case AFSR0_EL1: 114 case AFSR1_EL1: 115 case FAR_EL1: 116 case MAIR_EL1: 117 case VBAR_EL1: 118 case CONTEXTIDR_EL1: 119 case AMAIR_EL1: 120 case CNTKCTL_EL1: 121 case ELR_EL1: 122 case SPSR_EL1: 123 case ZCR_EL1: 124 case SCTLR2_EL1: 125 /* 126 * EL1 registers which have an ELx2 mapping are loaded if 127 * we're not in hypervisor context. 128 */ 129 return is_hyp_ctxt(vcpu) ? SR_LOC_MEMORY : SR_LOC_LOADED; 130 131 case TPIDR_EL0: 132 case TPIDRRO_EL0: 133 case TPIDR_EL1: 134 case PAR_EL1: 135 case DACR32_EL2: 136 case IFSR32_EL2: 137 case DBGVCR32_EL2: 138 /* These registers are always loaded, no matter what */ 139 return SR_LOC_LOADED; 140 141 default: 142 /* Non-mapped EL2 registers are by definition in memory. */ 143 return SR_LOC_MEMORY; 144 } 145 } 146 147 static void locate_mapped_el2_register(const struct kvm_vcpu *vcpu, 148 enum vcpu_sysreg reg, 149 enum vcpu_sysreg map_reg, 150 u64 (*xlate)(u64), 151 struct sr_loc *loc) 152 { 153 if (!is_hyp_ctxt(vcpu)) { 154 loc->loc = SR_LOC_MEMORY; 155 return; 156 } 157 158 loc->loc = SR_LOC_LOADED | SR_LOC_MAPPED; 159 loc->map_reg = map_reg; 160 161 WARN_ON(locate_direct_register(vcpu, map_reg) != SR_LOC_MEMORY); 162 163 if (xlate != NULL && !vcpu_el2_e2h_is_set(vcpu)) { 164 loc->loc |= SR_LOC_XLATED; 165 loc->xlate = xlate; 166 } 167 } 168 169 #define MAPPED_EL2_SYSREG(r, m, t) \ 170 case r: { \ 171 locate_mapped_el2_register(vcpu, r, m, t, loc); \ 172 break; \ 173 } 174 175 static void locate_register(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg, 176 struct sr_loc *loc) 177 { 178 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) { 179 loc->loc = SR_LOC_MEMORY; 180 return; 181 } 182 183 switch (reg) { 184 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 185 translate_sctlr_el2_to_sctlr_el1 ); 186 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 187 translate_cptr_el2_to_cpacr_el1 ); 188 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 189 translate_ttbr0_el2_to_ttbr0_el1 ); 190 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 191 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 192 translate_tcr_el2_to_tcr_el1 ); 193 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 194 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 195 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 196 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 197 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 198 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 199 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL ); 200 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); 201 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); 202 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); 203 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 204 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 205 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 206 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 207 MAPPED_EL2_SYSREG(SCTLR2_EL2, SCTLR2_EL1, NULL ); 208 case CNTHCTL_EL2: 209 /* CNTHCTL_EL2 is super special, until we support NV2.1 */ 210 loc->loc = ((is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) ? 211 SR_LOC_SPECIAL : SR_LOC_MEMORY); 212 break; 213 default: 214 loc->loc = locate_direct_register(vcpu, reg); 215 } 216 } 217 218 static u64 read_sr_from_cpu(enum vcpu_sysreg reg) 219 { 220 u64 val = 0x8badf00d8badf00d; 221 222 switch (reg) { 223 case SCTLR_EL1: val = read_sysreg_s(SYS_SCTLR_EL12); break; 224 case CPACR_EL1: val = read_sysreg_s(SYS_CPACR_EL12); break; 225 case TTBR0_EL1: val = read_sysreg_s(SYS_TTBR0_EL12); break; 226 case TTBR1_EL1: val = read_sysreg_s(SYS_TTBR1_EL12); break; 227 case TCR_EL1: val = read_sysreg_s(SYS_TCR_EL12); break; 228 case TCR2_EL1: val = read_sysreg_s(SYS_TCR2_EL12); break; 229 case PIR_EL1: val = read_sysreg_s(SYS_PIR_EL12); break; 230 case PIRE0_EL1: val = read_sysreg_s(SYS_PIRE0_EL12); break; 231 case POR_EL1: val = read_sysreg_s(SYS_POR_EL12); break; 232 case ESR_EL1: val = read_sysreg_s(SYS_ESR_EL12); break; 233 case AFSR0_EL1: val = read_sysreg_s(SYS_AFSR0_EL12); break; 234 case AFSR1_EL1: val = read_sysreg_s(SYS_AFSR1_EL12); break; 235 case FAR_EL1: val = read_sysreg_s(SYS_FAR_EL12); break; 236 case MAIR_EL1: val = read_sysreg_s(SYS_MAIR_EL12); break; 237 case VBAR_EL1: val = read_sysreg_s(SYS_VBAR_EL12); break; 238 case CONTEXTIDR_EL1: val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 239 case AMAIR_EL1: val = read_sysreg_s(SYS_AMAIR_EL12); break; 240 case CNTKCTL_EL1: val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 241 case ELR_EL1: val = read_sysreg_s(SYS_ELR_EL12); break; 242 case SPSR_EL1: val = read_sysreg_s(SYS_SPSR_EL12); break; 243 case ZCR_EL1: val = read_sysreg_s(SYS_ZCR_EL12); break; 244 case SCTLR2_EL1: val = read_sysreg_s(SYS_SCTLR2_EL12); break; 245 case TPIDR_EL0: val = read_sysreg_s(SYS_TPIDR_EL0); break; 246 case TPIDRRO_EL0: val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 247 case TPIDR_EL1: val = read_sysreg_s(SYS_TPIDR_EL1); break; 248 case PAR_EL1: val = read_sysreg_par(); break; 249 case DACR32_EL2: val = read_sysreg_s(SYS_DACR32_EL2); break; 250 case IFSR32_EL2: val = read_sysreg_s(SYS_IFSR32_EL2); break; 251 case DBGVCR32_EL2: val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 252 default: WARN_ON_ONCE(1); 253 } 254 255 return val; 256 } 257 258 static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 val) 259 { 260 switch (reg) { 261 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 262 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 263 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 264 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 265 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 266 case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break; 267 case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break; 268 case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break; 269 case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break; 270 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 271 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 272 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 273 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 274 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 275 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 276 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 277 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 278 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 279 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 280 case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break; 281 case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break; 282 case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break; 283 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 284 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 285 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 286 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 287 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 288 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 289 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 290 default: WARN_ON_ONCE(1); 291 } 292 } 293 294 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg) 295 { 296 struct sr_loc loc = {}; 297 298 locate_register(vcpu, reg, &loc); 299 300 WARN_ON_ONCE(!has_vhe() && loc.loc != SR_LOC_MEMORY); 301 302 if (loc.loc & SR_LOC_SPECIAL) { 303 u64 val; 304 305 WARN_ON_ONCE(loc.loc & ~SR_LOC_SPECIAL); 306 307 /* 308 * CNTHCTL_EL2 requires some special treatment to account 309 * for the bits that can be set via CNTKCTL_EL1 when E2H==1. 310 */ 311 switch (reg) { 312 case CNTHCTL_EL2: 313 val = read_sysreg_el1(SYS_CNTKCTL); 314 val &= CNTKCTL_VALID_BITS; 315 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 316 return val; 317 default: 318 WARN_ON_ONCE(1); 319 } 320 } 321 322 if (loc.loc & SR_LOC_LOADED) { 323 enum vcpu_sysreg map_reg = reg; 324 325 if (loc.loc & SR_LOC_MAPPED) 326 map_reg = loc.map_reg; 327 328 if (!(loc.loc & SR_LOC_XLATED)) { 329 u64 val = read_sr_from_cpu(map_reg); 330 331 if (reg >= __SANITISED_REG_START__) 332 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 333 334 return val; 335 } 336 } 337 338 return __vcpu_sys_reg(vcpu, reg); 339 } 340 341 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, enum vcpu_sysreg reg) 342 { 343 struct sr_loc loc = {}; 344 345 locate_register(vcpu, reg, &loc); 346 347 WARN_ON_ONCE(!has_vhe() && loc.loc != SR_LOC_MEMORY); 348 349 if (loc.loc & SR_LOC_SPECIAL) { 350 351 WARN_ON_ONCE(loc.loc & ~SR_LOC_SPECIAL); 352 353 switch (reg) { 354 case CNTHCTL_EL2: 355 /* 356 * If E2H=1, some of the bits are backed by 357 * CNTKCTL_EL1, while the rest is kept in memory. 358 * Yes, this is fun stuff. 359 */ 360 write_sysreg_el1(val, SYS_CNTKCTL); 361 break; 362 default: 363 WARN_ON_ONCE(1); 364 } 365 } 366 367 if (loc.loc & SR_LOC_LOADED) { 368 enum vcpu_sysreg map_reg = reg; 369 u64 xlated_val; 370 371 if (reg >= __SANITISED_REG_START__) 372 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 373 374 if (loc.loc & SR_LOC_MAPPED) 375 map_reg = loc.map_reg; 376 377 if (loc.loc & SR_LOC_XLATED) 378 xlated_val = loc.xlate(val); 379 else 380 xlated_val = val; 381 382 write_sr_to_cpu(map_reg, xlated_val); 383 384 /* 385 * Fall through to write the backing store anyway, which 386 * allows translated registers to be directly read without a 387 * reverse translation. 388 */ 389 } 390 391 __vcpu_assign_sys_reg(vcpu, reg, val); 392 } 393 394 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 395 #define CSSELR_MAX 14 396 397 /* 398 * Returns the minimum line size for the selected cache, expressed as 399 * Log2(bytes). 400 */ 401 static u8 get_min_cache_line_size(bool icache) 402 { 403 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 404 u8 field; 405 406 if (icache) 407 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 408 else 409 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 410 411 /* 412 * Cache line size is represented as Log2(words) in CTR_EL0. 413 * Log2(bytes) can be derived with the following: 414 * 415 * Log2(words) + 2 = Log2(bytes / 4) + 2 416 * = Log2(bytes) - 2 + 2 417 * = Log2(bytes) 418 */ 419 return field + 2; 420 } 421 422 /* Which cache CCSIDR represents depends on CSSELR value. */ 423 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 424 { 425 u8 line_size; 426 427 if (vcpu->arch.ccsidr) 428 return vcpu->arch.ccsidr[csselr]; 429 430 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 431 432 /* 433 * Fabricate a CCSIDR value as the overriding value does not exist. 434 * The real CCSIDR value will not be used as it can vary by the 435 * physical CPU which the vcpu currently resides in. 436 * 437 * The line size is determined with get_min_cache_line_size(), which 438 * should be valid for all CPUs even if they have different cache 439 * configuration. 440 * 441 * The associativity bits are cleared, meaning the geometry of all data 442 * and unified caches (which are guaranteed to be PIPT and thus 443 * non-aliasing) are 1 set and 1 way. 444 * Guests should not be doing cache operations by set/way at all, and 445 * for this reason, we trap them and attempt to infer the intent, so 446 * that we can flush the entire guest's address space at the appropriate 447 * time. The exposed geometry minimizes the number of the traps. 448 * [If guests should attempt to infer aliasing properties from the 449 * geometry (which is not permitted by the architecture), they would 450 * only do so for virtually indexed caches.] 451 * 452 * We don't check if the cache level exists as it is allowed to return 453 * an UNKNOWN value if not. 454 */ 455 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 456 } 457 458 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 459 { 460 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 461 u32 *ccsidr = vcpu->arch.ccsidr; 462 u32 i; 463 464 if ((val & CCSIDR_EL1_RES0) || 465 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 466 return -EINVAL; 467 468 if (!ccsidr) { 469 if (val == get_ccsidr(vcpu, csselr)) 470 return 0; 471 472 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 473 if (!ccsidr) 474 return -ENOMEM; 475 476 for (i = 0; i < CSSELR_MAX; i++) 477 ccsidr[i] = get_ccsidr(vcpu, i); 478 479 vcpu->arch.ccsidr = ccsidr; 480 } 481 482 ccsidr[csselr] = val; 483 484 return 0; 485 } 486 487 static bool access_rw(struct kvm_vcpu *vcpu, 488 struct sys_reg_params *p, 489 const struct sys_reg_desc *r) 490 { 491 if (p->is_write) 492 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 493 else 494 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 495 496 return true; 497 } 498 499 /* 500 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 501 */ 502 static bool access_dcsw(struct kvm_vcpu *vcpu, 503 struct sys_reg_params *p, 504 const struct sys_reg_desc *r) 505 { 506 if (!p->is_write) 507 return read_from_write_only(vcpu, p, r); 508 509 /* 510 * Only track S/W ops if we don't have FWB. It still indicates 511 * that the guest is a bit broken (S/W operations should only 512 * be done by firmware, knowing that there is only a single 513 * CPU left in the system, and certainly not from non-secure 514 * software). 515 */ 516 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 517 kvm_set_way_flush(vcpu); 518 519 return true; 520 } 521 522 static bool access_dcgsw(struct kvm_vcpu *vcpu, 523 struct sys_reg_params *p, 524 const struct sys_reg_desc *r) 525 { 526 if (!kvm_has_mte(vcpu->kvm)) 527 return undef_access(vcpu, p, r); 528 529 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 530 return access_dcsw(vcpu, p, r); 531 } 532 533 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 534 { 535 switch (r->aarch32_map) { 536 case AA32_LO: 537 *mask = GENMASK_ULL(31, 0); 538 *shift = 0; 539 break; 540 case AA32_HI: 541 *mask = GENMASK_ULL(63, 32); 542 *shift = 32; 543 break; 544 default: 545 *mask = GENMASK_ULL(63, 0); 546 *shift = 0; 547 break; 548 } 549 } 550 551 /* 552 * Generic accessor for VM registers. Only called as long as HCR_TVM 553 * is set. If the guest enables the MMU, we stop trapping the VM 554 * sys_regs and leave it in complete control of the caches. 555 */ 556 static bool access_vm_reg(struct kvm_vcpu *vcpu, 557 struct sys_reg_params *p, 558 const struct sys_reg_desc *r) 559 { 560 bool was_enabled = vcpu_has_cache_enabled(vcpu); 561 u64 val, mask, shift; 562 563 BUG_ON(!p->is_write); 564 565 get_access_mask(r, &mask, &shift); 566 567 if (~mask) { 568 val = vcpu_read_sys_reg(vcpu, r->reg); 569 val &= ~mask; 570 } else { 571 val = 0; 572 } 573 574 val |= (p->regval & (mask >> shift)) << shift; 575 vcpu_write_sys_reg(vcpu, val, r->reg); 576 577 kvm_toggle_cache(vcpu, was_enabled); 578 return true; 579 } 580 581 static bool access_actlr(struct kvm_vcpu *vcpu, 582 struct sys_reg_params *p, 583 const struct sys_reg_desc *r) 584 { 585 u64 mask, shift; 586 587 if (p->is_write) 588 return ignore_write(vcpu, p); 589 590 get_access_mask(r, &mask, &shift); 591 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 592 593 return true; 594 } 595 596 /* 597 * Trap handler for the GICv3 SGI generation system register. 598 * Forward the request to the VGIC emulation. 599 * The cp15_64 code makes sure this automatically works 600 * for both AArch64 and AArch32 accesses. 601 */ 602 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 603 struct sys_reg_params *p, 604 const struct sys_reg_desc *r) 605 { 606 bool g1; 607 608 if (!kvm_has_gicv3(vcpu->kvm)) 609 return undef_access(vcpu, p, r); 610 611 if (!p->is_write) 612 return read_from_write_only(vcpu, p, r); 613 614 /* 615 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 616 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 617 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 618 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 619 * group. 620 */ 621 if (p->Op0 == 0) { /* AArch32 */ 622 switch (p->Op1) { 623 default: /* Keep GCC quiet */ 624 case 0: /* ICC_SGI1R */ 625 g1 = true; 626 break; 627 case 1: /* ICC_ASGI1R */ 628 case 2: /* ICC_SGI0R */ 629 g1 = false; 630 break; 631 } 632 } else { /* AArch64 */ 633 switch (p->Op2) { 634 default: /* Keep GCC quiet */ 635 case 5: /* ICC_SGI1R_EL1 */ 636 g1 = true; 637 break; 638 case 6: /* ICC_ASGI1R_EL1 */ 639 case 7: /* ICC_SGI0R_EL1 */ 640 g1 = false; 641 break; 642 } 643 } 644 645 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 646 647 return true; 648 } 649 650 static bool access_gic_sre(struct kvm_vcpu *vcpu, 651 struct sys_reg_params *p, 652 const struct sys_reg_desc *r) 653 { 654 if (!kvm_has_gicv3(vcpu->kvm)) 655 return undef_access(vcpu, p, r); 656 657 if (p->is_write) 658 return ignore_write(vcpu, p); 659 660 if (p->Op1 == 4) { /* ICC_SRE_EL2 */ 661 p->regval = KVM_ICC_SRE_EL2; 662 } else { /* ICC_SRE_EL1 */ 663 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 664 } 665 666 return true; 667 } 668 669 static bool access_gic_dir(struct kvm_vcpu *vcpu, 670 struct sys_reg_params *p, 671 const struct sys_reg_desc *r) 672 { 673 if (!kvm_has_gicv3(vcpu->kvm)) 674 return undef_access(vcpu, p, r); 675 676 if (!p->is_write) 677 return undef_access(vcpu, p, r); 678 679 vgic_v3_deactivate(vcpu, p->regval); 680 681 return true; 682 } 683 684 static bool access_gicv5_idr0(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 685 const struct sys_reg_desc *r) 686 { 687 if (p->is_write) 688 return undef_access(vcpu, p, r); 689 690 /* 691 * Expose KVM's priority- and ID-bits to the guest, but not GCIE_LEGACY. 692 * 693 * Note: for GICv5 the mimic the way that the num_pri_bits and 694 * num_id_bits fields are used with GICv3: 695 * - num_pri_bits stores the actual number of priority bits, whereas the 696 * register field stores num_pri_bits - 1. 697 * - num_id_bits stores the raw field value, which is 0b0000 for 16 bits 698 * and 0b0001 for 24 bits. 699 */ 700 p->regval = FIELD_PREP(ICC_IDR0_EL1_PRI_BITS, vcpu->arch.vgic_cpu.num_pri_bits - 1) | 701 FIELD_PREP(ICC_IDR0_EL1_ID_BITS, vcpu->arch.vgic_cpu.num_id_bits); 702 703 return true; 704 } 705 706 static bool access_gicv5_iaffid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 707 const struct sys_reg_desc *r) 708 { 709 if (p->is_write) 710 return undef_access(vcpu, p, r); 711 712 /* 713 * For GICv5 VMs, the IAFFID value is the same as the VPE ID. The VPE ID 714 * is the same as the VCPU's ID. 715 */ 716 p->regval = FIELD_PREP(ICC_IAFFIDR_EL1_IAFFID, vcpu->vcpu_id); 717 718 return true; 719 } 720 721 static bool access_gicv5_ppi_enabler(struct kvm_vcpu *vcpu, 722 struct sys_reg_params *p, 723 const struct sys_reg_desc *r) 724 { 725 unsigned long *mask = vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_mask; 726 struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5; 727 unsigned long reg = p->regval; 728 int i; 729 730 /* We never expect to get here with a read! */ 731 if (WARN_ON_ONCE(!p->is_write)) 732 return undef_access(vcpu, p, r); 733 734 /* 735 * As we're only handling architected PPIs, the guest writes to the 736 * enable for the non-architected PPIs just return as there's 737 * nothing to do at all. We don't even allocate the storage for them. 738 */ 739 if (p->Op2 % 2) 740 return true; 741 742 /* 743 * Merge the raw guest write into out bitmap, anded with our PPI mask. 744 */ 745 bitmap_and(cpu_if->vgic_ppi_enabler, ®, mask, VGIC_V5_NR_PRIVATE_IRQS); 746 747 /* 748 * Sync the change in enable states to the vgic_irqs. We consider all 749 * PPIs as we don't expose many to the guest. 750 */ 751 for_each_visible_v5_ppi(i, vcpu->kvm) { 752 u32 intid = vgic_v5_make_ppi(i); 753 struct vgic_irq *irq; 754 755 irq = vgic_get_vcpu_irq(vcpu, intid); 756 757 scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) 758 irq->enabled = test_bit(i, cpu_if->vgic_ppi_enabler); 759 760 vgic_put_irq(vcpu->kvm, irq); 761 } 762 763 return true; 764 } 765 766 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 767 struct sys_reg_params *p, 768 const struct sys_reg_desc *r) 769 { 770 if (p->is_write) 771 return ignore_write(vcpu, p); 772 else 773 return read_zero(vcpu, p); 774 } 775 776 /* 777 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 778 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 779 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 780 * treat it separately. 781 */ 782 static bool trap_loregion(struct kvm_vcpu *vcpu, 783 struct sys_reg_params *p, 784 const struct sys_reg_desc *r) 785 { 786 u32 sr = reg_to_encoding(r); 787 788 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 789 return undef_access(vcpu, p, r); 790 791 if (p->is_write && sr == SYS_LORID_EL1) 792 return write_to_read_only(vcpu, p, r); 793 794 return trap_raz_wi(vcpu, p, r); 795 } 796 797 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 798 struct sys_reg_params *p, 799 const struct sys_reg_desc *r) 800 { 801 if (!p->is_write) 802 return read_from_write_only(vcpu, p, r); 803 804 kvm_debug_handle_oslar(vcpu, p->regval); 805 return true; 806 } 807 808 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 809 struct sys_reg_params *p, 810 const struct sys_reg_desc *r) 811 { 812 if (p->is_write) 813 return write_to_read_only(vcpu, p, r); 814 815 p->regval = __vcpu_sys_reg(vcpu, r->reg); 816 return true; 817 } 818 819 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 820 u64 val) 821 { 822 /* 823 * The only modifiable bit is the OSLK bit. Refuse the write if 824 * userspace attempts to change any other bit in the register. 825 */ 826 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 827 return -EINVAL; 828 829 __vcpu_assign_sys_reg(vcpu, rd->reg, val); 830 return 0; 831 } 832 833 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 834 struct sys_reg_params *p, 835 const struct sys_reg_desc *r) 836 { 837 if (p->is_write) { 838 return ignore_write(vcpu, p); 839 } else { 840 p->regval = read_sysreg(dbgauthstatus_el1); 841 return true; 842 } 843 } 844 845 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 846 struct sys_reg_params *p, 847 const struct sys_reg_desc *r) 848 { 849 access_rw(vcpu, p, r); 850 851 kvm_debug_set_guest_ownership(vcpu); 852 return true; 853 } 854 855 /* 856 * reg_to_dbg/dbg_to_reg 857 * 858 * A 32 bit write to a debug register leave top bits alone 859 * A 32 bit read from a debug register only returns the bottom bits 860 */ 861 static void reg_to_dbg(struct kvm_vcpu *vcpu, 862 struct sys_reg_params *p, 863 const struct sys_reg_desc *rd, 864 u64 *dbg_reg) 865 { 866 u64 mask, shift, val; 867 868 get_access_mask(rd, &mask, &shift); 869 870 val = *dbg_reg; 871 val &= ~mask; 872 val |= (p->regval & (mask >> shift)) << shift; 873 *dbg_reg = val; 874 } 875 876 static void dbg_to_reg(struct kvm_vcpu *vcpu, 877 struct sys_reg_params *p, 878 const struct sys_reg_desc *rd, 879 u64 *dbg_reg) 880 { 881 u64 mask, shift; 882 883 get_access_mask(rd, &mask, &shift); 884 p->regval = (*dbg_reg & mask) >> shift; 885 } 886 887 static u64 *demux_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 888 { 889 struct kvm_guest_debug_arch *dbg = &vcpu->arch.vcpu_debug_state; 890 891 switch (rd->Op2) { 892 case 0b100: 893 return &dbg->dbg_bvr[rd->CRm]; 894 case 0b101: 895 return &dbg->dbg_bcr[rd->CRm]; 896 case 0b110: 897 return &dbg->dbg_wvr[rd->CRm]; 898 case 0b111: 899 return &dbg->dbg_wcr[rd->CRm]; 900 default: 901 KVM_BUG_ON(1, vcpu->kvm); 902 return NULL; 903 } 904 } 905 906 static bool trap_dbg_wb_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 907 const struct sys_reg_desc *rd) 908 { 909 u64 *reg = demux_wb_reg(vcpu, rd); 910 911 if (!reg) 912 return false; 913 914 if (p->is_write) 915 reg_to_dbg(vcpu, p, rd, reg); 916 else 917 dbg_to_reg(vcpu, p, rd, reg); 918 919 kvm_debug_set_guest_ownership(vcpu); 920 return true; 921 } 922 923 static int set_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 924 u64 val) 925 { 926 u64 *reg = demux_wb_reg(vcpu, rd); 927 928 if (!reg) 929 return -EINVAL; 930 931 *reg = val; 932 return 0; 933 } 934 935 static int get_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 936 u64 *val) 937 { 938 u64 *reg = demux_wb_reg(vcpu, rd); 939 940 if (!reg) 941 return -EINVAL; 942 943 *val = *reg; 944 return 0; 945 } 946 947 static u64 reset_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 948 { 949 u64 *reg = demux_wb_reg(vcpu, rd); 950 951 /* 952 * Bail early if we couldn't find storage for the register, the 953 * KVM_BUG_ON() in demux_wb_reg() will prevent this VM from ever 954 * being run. 955 */ 956 if (!reg) 957 return 0; 958 959 *reg = rd->val; 960 return rd->val; 961 } 962 963 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 964 { 965 u64 amair = read_sysreg(amair_el1); 966 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 967 return amair; 968 } 969 970 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 971 { 972 u64 actlr = read_sysreg(actlr_el1); 973 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 974 return actlr; 975 } 976 977 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 978 { 979 u64 mpidr; 980 981 /* 982 * Map the vcpu_id into the first three affinity level fields of 983 * the MPIDR. We limit the number of VCPUs in level 0 due to a 984 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 985 * of the GICv3 to be able to address each CPU directly when 986 * sending IPIs. 987 */ 988 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 989 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 990 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 991 mpidr |= (1ULL << 31); 992 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 993 994 return mpidr; 995 } 996 997 static unsigned int hidden_visibility(const struct kvm_vcpu *vcpu, 998 const struct sys_reg_desc *r) 999 { 1000 return REG_HIDDEN; 1001 } 1002 1003 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 1004 const struct sys_reg_desc *r) 1005 { 1006 if (kvm_vcpu_has_pmu(vcpu)) 1007 return 0; 1008 1009 return REG_HIDDEN; 1010 } 1011 1012 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1013 { 1014 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 1015 u8 n = vcpu->kvm->arch.nr_pmu_counters; 1016 1017 if (n) 1018 mask |= GENMASK(n - 1, 0); 1019 1020 reset_unknown(vcpu, r); 1021 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, mask); 1022 1023 return __vcpu_sys_reg(vcpu, r->reg); 1024 } 1025 1026 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1027 { 1028 reset_unknown(vcpu, r); 1029 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, GENMASK(31, 0)); 1030 1031 return __vcpu_sys_reg(vcpu, r->reg); 1032 } 1033 1034 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1035 { 1036 /* This thing will UNDEF, who cares about the reset value? */ 1037 if (!kvm_vcpu_has_pmu(vcpu)) 1038 return 0; 1039 1040 reset_unknown(vcpu, r); 1041 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, kvm_pmu_evtyper_mask(vcpu->kvm)); 1042 1043 return __vcpu_sys_reg(vcpu, r->reg); 1044 } 1045 1046 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1047 { 1048 reset_unknown(vcpu, r); 1049 __vcpu_rmw_sys_reg(vcpu, r->reg, &=, PMSELR_EL0_SEL_MASK); 1050 1051 return __vcpu_sys_reg(vcpu, r->reg); 1052 } 1053 1054 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1055 { 1056 u64 pmcr = 0; 1057 1058 if (!kvm_supports_32bit_el0()) 1059 pmcr |= ARMV8_PMU_PMCR_LC; 1060 1061 /* 1062 * The value of PMCR.N field is included when the 1063 * vCPU register is read via kvm_vcpu_read_pmcr(). 1064 */ 1065 __vcpu_assign_sys_reg(vcpu, r->reg, pmcr); 1066 1067 return __vcpu_sys_reg(vcpu, r->reg); 1068 } 1069 1070 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 1071 { 1072 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 1073 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 1074 1075 if (!enabled) 1076 kvm_inject_undefined(vcpu); 1077 1078 return !enabled; 1079 } 1080 1081 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 1082 { 1083 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 1084 } 1085 1086 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 1087 { 1088 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 1089 } 1090 1091 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 1092 { 1093 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 1094 } 1095 1096 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 1097 { 1098 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 1099 } 1100 1101 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1102 const struct sys_reg_desc *r) 1103 { 1104 u64 val; 1105 1106 if (pmu_access_el0_disabled(vcpu)) 1107 return false; 1108 1109 if (p->is_write) { 1110 /* 1111 * Only update writeable bits of PMCR (continuing into 1112 * kvm_pmu_handle_pmcr() as well) 1113 */ 1114 val = kvm_vcpu_read_pmcr(vcpu); 1115 val &= ~ARMV8_PMU_PMCR_MASK; 1116 val |= p->regval & ARMV8_PMU_PMCR_MASK; 1117 if (!kvm_supports_32bit_el0()) 1118 val |= ARMV8_PMU_PMCR_LC; 1119 kvm_pmu_handle_pmcr(vcpu, val); 1120 } else { 1121 /* PMCR.P & PMCR.C are RAZ */ 1122 val = kvm_vcpu_read_pmcr(vcpu) 1123 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 1124 p->regval = val; 1125 } 1126 1127 return true; 1128 } 1129 1130 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1131 const struct sys_reg_desc *r) 1132 { 1133 if (pmu_access_event_counter_el0_disabled(vcpu)) 1134 return false; 1135 1136 if (p->is_write) 1137 __vcpu_assign_sys_reg(vcpu, PMSELR_EL0, p->regval); 1138 else 1139 /* return PMSELR.SEL field */ 1140 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 1141 & PMSELR_EL0_SEL_MASK; 1142 1143 return true; 1144 } 1145 1146 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1147 const struct sys_reg_desc *r) 1148 { 1149 u64 pmceid, mask, shift; 1150 1151 BUG_ON(p->is_write); 1152 1153 if (pmu_access_el0_disabled(vcpu)) 1154 return false; 1155 1156 get_access_mask(r, &mask, &shift); 1157 1158 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 1159 pmceid &= mask; 1160 pmceid >>= shift; 1161 1162 p->regval = pmceid; 1163 1164 return true; 1165 } 1166 1167 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 1168 { 1169 u64 pmcr, val; 1170 1171 pmcr = kvm_vcpu_read_pmcr(vcpu); 1172 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 1173 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 1174 kvm_inject_undefined(vcpu); 1175 return false; 1176 } 1177 1178 return true; 1179 } 1180 1181 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1182 u64 *val) 1183 { 1184 u64 idx; 1185 1186 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1187 /* PMCCNTR_EL0 */ 1188 idx = ARMV8_PMU_CYCLE_IDX; 1189 else 1190 /* PMEVCNTRn_EL0 */ 1191 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1192 1193 *val = kvm_pmu_get_counter_value(vcpu, idx); 1194 return 0; 1195 } 1196 1197 static int set_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1198 u64 val) 1199 { 1200 u64 idx; 1201 1202 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 1203 /* PMCCNTR_EL0 */ 1204 idx = ARMV8_PMU_CYCLE_IDX; 1205 else 1206 /* PMEVCNTRn_EL0 */ 1207 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1208 1209 kvm_pmu_set_counter_value_user(vcpu, idx, val); 1210 return 0; 1211 } 1212 1213 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 1214 struct sys_reg_params *p, 1215 const struct sys_reg_desc *r) 1216 { 1217 u64 idx = ~0UL; 1218 1219 if (r->CRn == 9 && r->CRm == 13) { 1220 if (r->Op2 == 2) { 1221 /* PMXEVCNTR_EL0 */ 1222 if (pmu_access_event_counter_el0_disabled(vcpu)) 1223 return false; 1224 1225 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 1226 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1227 } else if (r->Op2 == 0) { 1228 /* PMCCNTR_EL0 */ 1229 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 1230 return false; 1231 1232 idx = ARMV8_PMU_CYCLE_IDX; 1233 } 1234 } else if (r->CRn == 0 && r->CRm == 9) { 1235 /* PMCCNTR */ 1236 if (pmu_access_event_counter_el0_disabled(vcpu)) 1237 return false; 1238 1239 idx = ARMV8_PMU_CYCLE_IDX; 1240 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 1241 /* PMEVCNTRn_EL0 */ 1242 if (pmu_access_event_counter_el0_disabled(vcpu)) 1243 return false; 1244 1245 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1246 } 1247 1248 /* Catch any decoding mistake */ 1249 WARN_ON(idx == ~0UL); 1250 1251 if (!pmu_counter_idx_valid(vcpu, idx)) 1252 return false; 1253 1254 if (p->is_write) { 1255 if (pmu_access_el0_disabled(vcpu)) 1256 return false; 1257 1258 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1259 } else { 1260 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1261 } 1262 1263 return true; 1264 } 1265 1266 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1267 const struct sys_reg_desc *r) 1268 { 1269 u64 idx, reg; 1270 1271 if (pmu_access_el0_disabled(vcpu)) 1272 return false; 1273 1274 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1275 /* PMXEVTYPER_EL0 */ 1276 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1277 reg = PMEVTYPER0_EL0 + idx; 1278 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1279 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1280 if (idx == ARMV8_PMU_CYCLE_IDX) 1281 reg = PMCCFILTR_EL0; 1282 else 1283 /* PMEVTYPERn_EL0 */ 1284 reg = PMEVTYPER0_EL0 + idx; 1285 } else { 1286 BUG(); 1287 } 1288 1289 if (!pmu_counter_idx_valid(vcpu, idx)) 1290 return false; 1291 1292 if (p->is_write) { 1293 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1294 kvm_vcpu_pmu_restore_guest(vcpu); 1295 } else { 1296 p->regval = __vcpu_sys_reg(vcpu, reg); 1297 } 1298 1299 return true; 1300 } 1301 1302 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1303 { 1304 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1305 1306 __vcpu_assign_sys_reg(vcpu, r->reg, val & mask); 1307 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 1308 1309 return 0; 1310 } 1311 1312 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1313 { 1314 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1315 1316 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1317 return 0; 1318 } 1319 1320 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1321 const struct sys_reg_desc *r) 1322 { 1323 u64 val, mask; 1324 1325 if (pmu_access_el0_disabled(vcpu)) 1326 return false; 1327 1328 mask = kvm_pmu_accessible_counter_mask(vcpu); 1329 if (p->is_write) { 1330 val = p->regval & mask; 1331 if (r->Op2 & 0x1) 1332 /* accessing PMCNTENSET_EL0 */ 1333 __vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, |=, val); 1334 else 1335 /* accessing PMCNTENCLR_EL0 */ 1336 __vcpu_rmw_sys_reg(vcpu, PMCNTENSET_EL0, &=, ~val); 1337 1338 kvm_pmu_reprogram_counter_mask(vcpu, val); 1339 } else { 1340 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1341 } 1342 1343 return true; 1344 } 1345 1346 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1347 const struct sys_reg_desc *r) 1348 { 1349 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1350 1351 if (check_pmu_access_disabled(vcpu, 0)) 1352 return false; 1353 1354 if (p->is_write) { 1355 u64 val = p->regval & mask; 1356 1357 if (r->Op2 & 0x1) 1358 /* accessing PMINTENSET_EL1 */ 1359 __vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, |=, val); 1360 else 1361 /* accessing PMINTENCLR_EL1 */ 1362 __vcpu_rmw_sys_reg(vcpu, PMINTENSET_EL1, &=, ~val); 1363 } else { 1364 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1365 } 1366 1367 return true; 1368 } 1369 1370 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1371 const struct sys_reg_desc *r) 1372 { 1373 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1374 1375 if (pmu_access_el0_disabled(vcpu)) 1376 return false; 1377 1378 if (p->is_write) { 1379 if (r->CRm & 0x2) 1380 /* accessing PMOVSSET_EL0 */ 1381 __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, |=, (p->regval & mask)); 1382 else 1383 /* accessing PMOVSCLR_EL0 */ 1384 __vcpu_rmw_sys_reg(vcpu, PMOVSSET_EL0, &=, ~(p->regval & mask)); 1385 } else { 1386 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1387 } 1388 1389 return true; 1390 } 1391 1392 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1393 const struct sys_reg_desc *r) 1394 { 1395 u64 mask; 1396 1397 if (!p->is_write) 1398 return read_from_write_only(vcpu, p, r); 1399 1400 if (pmu_write_swinc_el0_disabled(vcpu)) 1401 return false; 1402 1403 mask = kvm_pmu_accessible_counter_mask(vcpu); 1404 kvm_pmu_software_increment(vcpu, p->regval & mask); 1405 return true; 1406 } 1407 1408 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1409 const struct sys_reg_desc *r) 1410 { 1411 if (p->is_write) { 1412 if (!vcpu_mode_priv(vcpu)) 1413 return undef_access(vcpu, p, r); 1414 1415 __vcpu_assign_sys_reg(vcpu, PMUSERENR_EL0, 1416 (p->regval & ARMV8_PMU_USERENR_MASK)); 1417 } else { 1418 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1419 & ARMV8_PMU_USERENR_MASK; 1420 } 1421 1422 return true; 1423 } 1424 1425 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1426 u64 *val) 1427 { 1428 *val = kvm_vcpu_read_pmcr(vcpu); 1429 return 0; 1430 } 1431 1432 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1433 u64 val) 1434 { 1435 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1436 struct kvm *kvm = vcpu->kvm; 1437 1438 mutex_lock(&kvm->arch.config_lock); 1439 1440 /* 1441 * The vCPU can't have more counters than the PMU hardware 1442 * implements. Ignore this error to maintain compatibility 1443 * with the existing KVM behavior. 1444 */ 1445 if (!kvm_vm_has_ran_once(kvm) && 1446 !vcpu_has_nv(vcpu) && 1447 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1448 kvm->arch.nr_pmu_counters = new_n; 1449 1450 mutex_unlock(&kvm->arch.config_lock); 1451 1452 /* 1453 * Ignore writes to RES0 bits, read only bits that are cleared on 1454 * vCPU reset, and writable bits that KVM doesn't support yet. 1455 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1456 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1457 * But, we leave the bit as it is here, as the vCPU's PMUver might 1458 * be changed later (NOTE: the bit will be cleared on first vCPU run 1459 * if necessary). 1460 */ 1461 val &= ARMV8_PMU_PMCR_MASK; 1462 1463 /* The LC bit is RES1 when AArch32 is not supported */ 1464 if (!kvm_supports_32bit_el0()) 1465 val |= ARMV8_PMU_PMCR_LC; 1466 1467 __vcpu_assign_sys_reg(vcpu, r->reg, val); 1468 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 1469 1470 return 0; 1471 } 1472 1473 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1474 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1475 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1476 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1477 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1478 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1479 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1480 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1481 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1482 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1483 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1484 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1485 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1486 get_dbg_wb_reg, set_dbg_wb_reg } 1487 1488 #define PMU_SYS_REG(name) \ 1489 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1490 .visibility = pmu_visibility 1491 1492 /* Macro to expand the PMEVCNTRn_EL0 register */ 1493 #define PMU_PMEVCNTR_EL0(n) \ 1494 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1495 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1496 .set_user = set_pmu_evcntr, \ 1497 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1498 1499 /* Macro to expand the PMEVTYPERn_EL0 register */ 1500 #define PMU_PMEVTYPER_EL0(n) \ 1501 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1502 .reset = reset_pmevtyper, \ 1503 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1504 1505 /* Macro to expand the AMU counter and type registers*/ 1506 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1507 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1508 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1509 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1510 1511 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1512 const struct sys_reg_desc *rd) 1513 { 1514 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1515 } 1516 1517 /* 1518 * If we land here on a PtrAuth access, that is because we didn't 1519 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1520 * way this happens is when the guest does not have PtrAuth support 1521 * enabled. 1522 */ 1523 #define __PTRAUTH_KEY(k) \ 1524 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1525 .visibility = ptrauth_visibility} 1526 1527 #define PTRAUTH_KEY(k) \ 1528 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1529 __PTRAUTH_KEY(k ## KEYHI_EL1) 1530 1531 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1532 struct sys_reg_params *p, 1533 const struct sys_reg_desc *r) 1534 { 1535 enum kvm_arch_timers tmr; 1536 enum kvm_arch_timer_regs treg; 1537 u64 reg = reg_to_encoding(r); 1538 1539 switch (reg) { 1540 case SYS_CNTP_TVAL_EL0: 1541 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1542 tmr = TIMER_HPTIMER; 1543 else 1544 tmr = TIMER_PTIMER; 1545 treg = TIMER_REG_TVAL; 1546 break; 1547 1548 case SYS_CNTV_TVAL_EL0: 1549 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1550 tmr = TIMER_HVTIMER; 1551 else 1552 tmr = TIMER_VTIMER; 1553 treg = TIMER_REG_TVAL; 1554 break; 1555 1556 case SYS_AARCH32_CNTP_TVAL: 1557 case SYS_CNTP_TVAL_EL02: 1558 tmr = TIMER_PTIMER; 1559 treg = TIMER_REG_TVAL; 1560 break; 1561 1562 case SYS_CNTV_TVAL_EL02: 1563 tmr = TIMER_VTIMER; 1564 treg = TIMER_REG_TVAL; 1565 break; 1566 1567 case SYS_CNTHP_TVAL_EL2: 1568 tmr = TIMER_HPTIMER; 1569 treg = TIMER_REG_TVAL; 1570 break; 1571 1572 case SYS_CNTHV_TVAL_EL2: 1573 tmr = TIMER_HVTIMER; 1574 treg = TIMER_REG_TVAL; 1575 break; 1576 1577 case SYS_CNTP_CTL_EL0: 1578 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1579 tmr = TIMER_HPTIMER; 1580 else 1581 tmr = TIMER_PTIMER; 1582 treg = TIMER_REG_CTL; 1583 break; 1584 1585 case SYS_CNTV_CTL_EL0: 1586 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1587 tmr = TIMER_HVTIMER; 1588 else 1589 tmr = TIMER_VTIMER; 1590 treg = TIMER_REG_CTL; 1591 break; 1592 1593 case SYS_AARCH32_CNTP_CTL: 1594 case SYS_CNTP_CTL_EL02: 1595 tmr = TIMER_PTIMER; 1596 treg = TIMER_REG_CTL; 1597 break; 1598 1599 case SYS_CNTV_CTL_EL02: 1600 tmr = TIMER_VTIMER; 1601 treg = TIMER_REG_CTL; 1602 break; 1603 1604 case SYS_CNTHP_CTL_EL2: 1605 tmr = TIMER_HPTIMER; 1606 treg = TIMER_REG_CTL; 1607 break; 1608 1609 case SYS_CNTHV_CTL_EL2: 1610 tmr = TIMER_HVTIMER; 1611 treg = TIMER_REG_CTL; 1612 break; 1613 1614 case SYS_CNTP_CVAL_EL0: 1615 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1616 tmr = TIMER_HPTIMER; 1617 else 1618 tmr = TIMER_PTIMER; 1619 treg = TIMER_REG_CVAL; 1620 break; 1621 1622 case SYS_CNTV_CVAL_EL0: 1623 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1624 tmr = TIMER_HVTIMER; 1625 else 1626 tmr = TIMER_VTIMER; 1627 treg = TIMER_REG_CVAL; 1628 break; 1629 1630 case SYS_AARCH32_CNTP_CVAL: 1631 case SYS_CNTP_CVAL_EL02: 1632 tmr = TIMER_PTIMER; 1633 treg = TIMER_REG_CVAL; 1634 break; 1635 1636 case SYS_CNTV_CVAL_EL02: 1637 tmr = TIMER_VTIMER; 1638 treg = TIMER_REG_CVAL; 1639 break; 1640 1641 case SYS_CNTHP_CVAL_EL2: 1642 tmr = TIMER_HPTIMER; 1643 treg = TIMER_REG_CVAL; 1644 break; 1645 1646 case SYS_CNTHV_CVAL_EL2: 1647 tmr = TIMER_HVTIMER; 1648 treg = TIMER_REG_CVAL; 1649 break; 1650 1651 case SYS_CNTPCT_EL0: 1652 case SYS_CNTPCTSS_EL0: 1653 if (is_hyp_ctxt(vcpu)) 1654 tmr = TIMER_HPTIMER; 1655 else 1656 tmr = TIMER_PTIMER; 1657 treg = TIMER_REG_CNT; 1658 break; 1659 1660 case SYS_AARCH32_CNTPCT: 1661 case SYS_AARCH32_CNTPCTSS: 1662 tmr = TIMER_PTIMER; 1663 treg = TIMER_REG_CNT; 1664 break; 1665 1666 case SYS_CNTVCT_EL0: 1667 case SYS_CNTVCTSS_EL0: 1668 if (is_hyp_ctxt(vcpu)) 1669 tmr = TIMER_HVTIMER; 1670 else 1671 tmr = TIMER_VTIMER; 1672 treg = TIMER_REG_CNT; 1673 break; 1674 1675 case SYS_AARCH32_CNTVCT: 1676 case SYS_AARCH32_CNTVCTSS: 1677 tmr = TIMER_VTIMER; 1678 treg = TIMER_REG_CNT; 1679 break; 1680 1681 default: 1682 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1683 return undef_access(vcpu, p, r); 1684 } 1685 1686 if (p->is_write) 1687 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1688 else 1689 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1690 1691 return true; 1692 } 1693 1694 static int arch_timer_set_user(struct kvm_vcpu *vcpu, 1695 const struct sys_reg_desc *rd, 1696 u64 val) 1697 { 1698 switch (reg_to_encoding(rd)) { 1699 case SYS_CNTV_CTL_EL0: 1700 case SYS_CNTP_CTL_EL0: 1701 case SYS_CNTHV_CTL_EL2: 1702 case SYS_CNTHP_CTL_EL2: 1703 val &= ~ARCH_TIMER_CTRL_IT_STAT; 1704 break; 1705 case SYS_CNTVCT_EL0: 1706 if (!test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) 1707 timer_set_offset(vcpu_vtimer(vcpu), kvm_phys_timer_read() - val); 1708 return 0; 1709 case SYS_CNTPCT_EL0: 1710 if (!test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) 1711 timer_set_offset(vcpu_ptimer(vcpu), kvm_phys_timer_read() - val); 1712 return 0; 1713 } 1714 1715 __vcpu_assign_sys_reg(vcpu, rd->reg, val); 1716 return 0; 1717 } 1718 1719 static int arch_timer_get_user(struct kvm_vcpu *vcpu, 1720 const struct sys_reg_desc *rd, 1721 u64 *val) 1722 { 1723 switch (reg_to_encoding(rd)) { 1724 case SYS_CNTVCT_EL0: 1725 *val = kvm_phys_timer_read() - timer_get_offset(vcpu_vtimer(vcpu)); 1726 break; 1727 case SYS_CNTPCT_EL0: 1728 *val = kvm_phys_timer_read() - timer_get_offset(vcpu_ptimer(vcpu)); 1729 break; 1730 default: 1731 *val = __vcpu_sys_reg(vcpu, rd->reg); 1732 } 1733 1734 return 0; 1735 } 1736 1737 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1738 s64 new, s64 cur) 1739 { 1740 struct arm64_ftr_bits kvm_ftr = *ftrp; 1741 1742 /* Some features have different safe value type in KVM than host features */ 1743 switch (id) { 1744 case SYS_ID_AA64DFR0_EL1: 1745 switch (kvm_ftr.shift) { 1746 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1747 kvm_ftr.type = FTR_LOWER_SAFE; 1748 break; 1749 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1750 kvm_ftr.type = FTR_LOWER_SAFE; 1751 break; 1752 } 1753 break; 1754 case SYS_ID_DFR0_EL1: 1755 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1756 kvm_ftr.type = FTR_LOWER_SAFE; 1757 break; 1758 } 1759 1760 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1761 } 1762 1763 /* 1764 * arm64_check_features() - Check if a feature register value constitutes 1765 * a subset of features indicated by the idreg's KVM sanitised limit. 1766 * 1767 * This function will check if each feature field of @val is the "safe" value 1768 * against idreg's KVM sanitised limit return from reset() callback. 1769 * If a field value in @val is the same as the one in limit, it is always 1770 * considered the safe value regardless For register fields that are not in 1771 * writable, only the value in limit is considered the safe value. 1772 * 1773 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1774 */ 1775 static int arm64_check_features(struct kvm_vcpu *vcpu, 1776 const struct sys_reg_desc *rd, 1777 u64 val) 1778 { 1779 const struct arm64_ftr_reg *ftr_reg; 1780 const struct arm64_ftr_bits *ftrp = NULL; 1781 u32 id = reg_to_encoding(rd); 1782 u64 writable_mask = rd->val; 1783 u64 limit = rd->reset(vcpu, rd); 1784 u64 mask = 0; 1785 1786 /* 1787 * Hidden and unallocated ID registers may not have a corresponding 1788 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1789 * only safe value is 0. 1790 */ 1791 if (sysreg_visible_as_raz(vcpu, rd)) 1792 return val ? -E2BIG : 0; 1793 1794 ftr_reg = get_arm64_ftr_reg(id); 1795 if (!ftr_reg) 1796 return -EINVAL; 1797 1798 ftrp = ftr_reg->ftr_bits; 1799 1800 for (; ftrp && ftrp->width; ftrp++) { 1801 s64 f_val, f_lim, safe_val; 1802 u64 ftr_mask; 1803 1804 ftr_mask = arm64_ftr_mask(ftrp); 1805 if ((ftr_mask & writable_mask) != ftr_mask) 1806 continue; 1807 1808 f_val = arm64_ftr_value(ftrp, val); 1809 f_lim = arm64_ftr_value(ftrp, limit); 1810 mask |= ftr_mask; 1811 1812 if (f_val == f_lim) 1813 safe_val = f_val; 1814 else 1815 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1816 1817 if (safe_val != f_val) 1818 return -E2BIG; 1819 } 1820 1821 /* For fields that are not writable, values in limit are the safe values. */ 1822 if ((val & ~mask) != (limit & ~mask)) 1823 return -E2BIG; 1824 1825 return 0; 1826 } 1827 1828 static u8 pmuver_to_perfmon(u8 pmuver) 1829 { 1830 switch (pmuver) { 1831 case ID_AA64DFR0_EL1_PMUVer_IMP: 1832 return ID_DFR0_EL1_PerfMon_PMUv3; 1833 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1834 return ID_DFR0_EL1_PerfMon_IMPDEF; 1835 default: 1836 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1837 return pmuver; 1838 } 1839 } 1840 1841 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1842 static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val); 1843 static u64 sanitise_id_aa64pfr2_el1(const struct kvm_vcpu *vcpu, u64 val); 1844 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1845 1846 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1847 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1848 const struct sys_reg_desc *r) 1849 { 1850 u32 id = reg_to_encoding(r); 1851 u64 val; 1852 1853 if (sysreg_visible_as_raz(vcpu, r)) 1854 return 0; 1855 1856 val = read_sanitised_ftr_reg(id); 1857 1858 switch (id) { 1859 case SYS_ID_AA64DFR0_EL1: 1860 val = sanitise_id_aa64dfr0_el1(vcpu, val); 1861 break; 1862 case SYS_ID_AA64PFR0_EL1: 1863 val = sanitise_id_aa64pfr0_el1(vcpu, val); 1864 break; 1865 case SYS_ID_AA64PFR1_EL1: 1866 val = sanitise_id_aa64pfr1_el1(vcpu, val); 1867 break; 1868 case SYS_ID_AA64PFR2_EL1: 1869 val = sanitise_id_aa64pfr2_el1(vcpu, val); 1870 break; 1871 case SYS_ID_AA64ISAR1_EL1: 1872 if (!vcpu_has_ptrauth(vcpu)) 1873 val &= ~(ID_AA64ISAR1_EL1_APA | 1874 ID_AA64ISAR1_EL1_API | 1875 ID_AA64ISAR1_EL1_GPA | 1876 ID_AA64ISAR1_EL1_GPI); 1877 break; 1878 case SYS_ID_AA64ISAR2_EL1: 1879 if (!vcpu_has_ptrauth(vcpu)) 1880 val &= ~(ID_AA64ISAR2_EL1_APA3 | 1881 ID_AA64ISAR2_EL1_GPA3); 1882 if (!cpus_have_final_cap(ARM64_HAS_WFXT) || 1883 has_broken_cntvoff()) 1884 val &= ~ID_AA64ISAR2_EL1_WFxT; 1885 break; 1886 case SYS_ID_AA64ISAR3_EL1: 1887 val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_LSFE | 1888 ID_AA64ISAR3_EL1_FAMINMAX | ID_AA64ISAR3_EL1_LSUI; 1889 break; 1890 case SYS_ID_AA64MMFR2_EL1: 1891 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1892 val &= ~ID_AA64MMFR2_EL1_NV; 1893 break; 1894 case SYS_ID_AA64MMFR3_EL1: 1895 val &= ID_AA64MMFR3_EL1_TCRX | 1896 ID_AA64MMFR3_EL1_SCTLRX | 1897 ID_AA64MMFR3_EL1_S1POE | 1898 ID_AA64MMFR3_EL1_S1PIE; 1899 1900 if (!system_supports_poe()) 1901 val &= ~ID_AA64MMFR3_EL1_S1POE; 1902 break; 1903 case SYS_ID_MMFR4_EL1: 1904 val &= ~ID_MMFR4_EL1_CCIDX; 1905 break; 1906 } 1907 1908 if (vcpu_has_nv(vcpu)) 1909 val = limit_nv_id_reg(vcpu->kvm, id, val); 1910 1911 return val; 1912 } 1913 1914 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1915 const struct sys_reg_desc *r) 1916 { 1917 return __kvm_read_sanitised_id_reg(vcpu, r); 1918 } 1919 1920 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1921 { 1922 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1923 } 1924 1925 static bool is_feature_id_reg(u32 encoding) 1926 { 1927 return (sys_reg_Op0(encoding) == 3 && 1928 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1929 sys_reg_CRn(encoding) == 0 && 1930 sys_reg_CRm(encoding) <= 7); 1931 } 1932 1933 /* 1934 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1935 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1936 * registers KVM maintains on a per-VM basis. 1937 * 1938 * Additionally, the implementation ID registers and CTR_EL0 are handled as 1939 * per-VM registers. 1940 */ 1941 static inline bool is_vm_ftr_id_reg(u32 id) 1942 { 1943 switch (id) { 1944 case SYS_CTR_EL0: 1945 case SYS_MIDR_EL1: 1946 case SYS_REVIDR_EL1: 1947 case SYS_AIDR_EL1: 1948 return true; 1949 default: 1950 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1951 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1952 sys_reg_CRm(id) < 8); 1953 1954 } 1955 } 1956 1957 static inline bool is_vcpu_ftr_id_reg(u32 id) 1958 { 1959 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1960 } 1961 1962 static inline bool is_aa32_id_reg(u32 id) 1963 { 1964 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1965 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1966 sys_reg_CRm(id) <= 3); 1967 } 1968 1969 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1970 const struct sys_reg_desc *r) 1971 { 1972 u32 id = reg_to_encoding(r); 1973 1974 switch (id) { 1975 case SYS_ID_AA64ZFR0_EL1: 1976 if (!vcpu_has_sve(vcpu)) 1977 return REG_RAZ; 1978 break; 1979 } 1980 1981 return 0; 1982 } 1983 1984 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1985 const struct sys_reg_desc *r) 1986 { 1987 /* 1988 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1989 * EL. Promote to RAZ/WI in order to guarantee consistency between 1990 * systems. 1991 */ 1992 if (!kvm_supports_32bit_el0()) 1993 return REG_RAZ | REG_USER_WI; 1994 1995 return id_visibility(vcpu, r); 1996 } 1997 1998 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1999 const struct sys_reg_desc *r) 2000 { 2001 return REG_RAZ; 2002 } 2003 2004 /* cpufeature ID register access trap handlers */ 2005 2006 static bool access_id_reg(struct kvm_vcpu *vcpu, 2007 struct sys_reg_params *p, 2008 const struct sys_reg_desc *r) 2009 { 2010 if (p->is_write) 2011 return write_to_read_only(vcpu, p, r); 2012 2013 p->regval = read_id_reg(vcpu, r); 2014 2015 return true; 2016 } 2017 2018 /* Visibility overrides for SVE-specific control registers */ 2019 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 2020 const struct sys_reg_desc *rd) 2021 { 2022 if (vcpu_has_sve(vcpu)) 2023 return 0; 2024 2025 return REG_HIDDEN; 2026 } 2027 2028 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 2029 const struct sys_reg_desc *rd) 2030 { 2031 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 2032 return 0; 2033 2034 return REG_HIDDEN; 2035 } 2036 2037 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 2038 const struct sys_reg_desc *rd) 2039 { 2040 if (kvm_has_fpmr(vcpu->kvm)) 2041 return 0; 2042 2043 return REG_HIDDEN; 2044 } 2045 2046 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 2047 { 2048 if (!vcpu_has_sve(vcpu)) 2049 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 2050 2051 /* 2052 * The default is to expose CSV2 == 1 if the HW isn't affected. 2053 * Although this is a per-CPU feature, we make it global because 2054 * asymmetric systems are just a nuisance. 2055 * 2056 * Userspace can override this as long as it doesn't promise 2057 * the impossible. 2058 */ 2059 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 2060 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 2061 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 2062 } 2063 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 2064 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 2065 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 2066 } 2067 2068 if (vgic_host_has_gicv3()) { 2069 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 2070 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 2071 } 2072 2073 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 2074 2075 /* 2076 * MPAM is disabled by default as KVM also needs a set of PARTID to 2077 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some 2078 * older kernels let the guest see the ID bit. 2079 */ 2080 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 2081 2082 return val; 2083 } 2084 2085 static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val) 2086 { 2087 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 2088 2089 if (!kvm_has_mte(vcpu->kvm)) { 2090 val &= ~ID_AA64PFR1_EL1_MTE; 2091 val &= ~ID_AA64PFR1_EL1_MTE_frac; 2092 } 2093 2094 if (!(cpus_have_final_cap(ARM64_HAS_RASV1P1_EXTN) && 2095 SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, pfr0) == ID_AA64PFR0_EL1_RAS_IMP)) 2096 val &= ~ID_AA64PFR1_EL1_RAS_frac; 2097 2098 val &= ~ID_AA64PFR1_EL1_SME; 2099 val &= ~ID_AA64PFR1_EL1_RNDR_trap; 2100 val &= ~ID_AA64PFR1_EL1_NMI; 2101 val &= ~ID_AA64PFR1_EL1_GCS; 2102 val &= ~ID_AA64PFR1_EL1_THE; 2103 val &= ~ID_AA64PFR1_EL1_MTEX; 2104 val &= ~ID_AA64PFR1_EL1_PFAR; 2105 val &= ~ID_AA64PFR1_EL1_MPAM_frac; 2106 2107 return val; 2108 } 2109 2110 static u64 sanitise_id_aa64pfr2_el1(const struct kvm_vcpu *vcpu, u64 val) 2111 { 2112 val &= ID_AA64PFR2_EL1_FPMR | 2113 ID_AA64PFR2_EL1_MTEFAR | 2114 ID_AA64PFR2_EL1_MTESTOREONLY; 2115 2116 if (!kvm_has_mte(vcpu->kvm)) { 2117 val &= ~ID_AA64PFR2_EL1_MTEFAR; 2118 val &= ~ID_AA64PFR2_EL1_MTESTOREONLY; 2119 } 2120 2121 if (vgic_host_has_gicv5()) 2122 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR2_EL1, GCIE, IMP); 2123 2124 return val; 2125 } 2126 2127 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 2128 { 2129 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 2130 2131 /* 2132 * Only initialize the PMU version if the vCPU was configured with one. 2133 */ 2134 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 2135 if (kvm_vcpu_has_pmu(vcpu)) 2136 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 2137 kvm_arm_pmu_get_pmuver_limit()); 2138 2139 /* Hide SPE from guests */ 2140 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 2141 2142 /* Hide BRBE from guests */ 2143 val &= ~ID_AA64DFR0_EL1_BRBE_MASK; 2144 2145 return val; 2146 } 2147 2148 /* 2149 * Older versions of KVM erroneously claim support for FEAT_DoubleLock with 2150 * NV-enabled VMs on unsupporting hardware. Silently ignore the incorrect 2151 * value if it is consistent with the bug. 2152 */ 2153 static bool ignore_feat_doublelock(struct kvm_vcpu *vcpu, u64 val) 2154 { 2155 u8 host, user; 2156 2157 if (!vcpu_has_nv(vcpu)) 2158 return false; 2159 2160 host = SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock, 2161 read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1)); 2162 user = SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock, val); 2163 2164 return host == ID_AA64DFR0_EL1_DoubleLock_NI && 2165 user == ID_AA64DFR0_EL1_DoubleLock_IMP; 2166 } 2167 2168 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 2169 const struct sys_reg_desc *rd, 2170 u64 val) 2171 { 2172 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 2173 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 2174 2175 /* 2176 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 2177 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 2178 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 2179 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 2180 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 2181 * 2182 * At minimum, we're on the hook to allow values that were given to 2183 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 2184 * with a more sensible NI. The value of an ID register changing under 2185 * the nose of the guest is unfortunate, but is certainly no more 2186 * surprising than an ill-guided PMU driver poking at impdef system 2187 * registers that end in an UNDEF... 2188 */ 2189 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 2190 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 2191 2192 /* 2193 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 2194 * nonzero minimum safe value. 2195 */ 2196 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 2197 return -EINVAL; 2198 2199 if (ignore_feat_doublelock(vcpu, val)) { 2200 val &= ~ID_AA64DFR0_EL1_DoubleLock; 2201 val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DoubleLock, NI); 2202 } 2203 2204 return set_id_reg(vcpu, rd, val); 2205 } 2206 2207 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 2208 const struct sys_reg_desc *rd) 2209 { 2210 u8 perfmon; 2211 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 2212 2213 val &= ~ID_DFR0_EL1_PerfMon_MASK; 2214 if (kvm_vcpu_has_pmu(vcpu)) { 2215 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 2216 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 2217 } 2218 2219 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 2220 2221 return val; 2222 } 2223 2224 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 2225 const struct sys_reg_desc *rd, 2226 u64 val) 2227 { 2228 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 2229 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 2230 2231 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 2232 val &= ~ID_DFR0_EL1_PerfMon_MASK; 2233 perfmon = 0; 2234 } 2235 2236 /* 2237 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 2238 * it doesn't promise more than what the HW gives us on the 2239 * AArch64 side (as everything is emulated with that), and 2240 * that this is a PMUv3. 2241 */ 2242 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 2243 return -EINVAL; 2244 2245 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 2246 return -EINVAL; 2247 2248 return set_id_reg(vcpu, rd, val); 2249 } 2250 2251 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 2252 const struct sys_reg_desc *rd, u64 user_val) 2253 { 2254 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 2255 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK; 2256 2257 /* 2258 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits 2259 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to 2260 * guests, but didn't add trap handling. KVM doesn't support MPAM and 2261 * always returns an UNDEF for these registers. The guest must see 0 2262 * for this field. 2263 * 2264 * But KVM must also accept values from user-space that were provided 2265 * by KVM. On CPUs that support MPAM, permit user-space to write 2266 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field. 2267 */ 2268 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 2269 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 2270 2271 /* Fail the guest's request to disable the AA64 ISA at EL{0,1,2} */ 2272 if (!FIELD_GET(ID_AA64PFR0_EL1_EL0, user_val) || 2273 !FIELD_GET(ID_AA64PFR0_EL1_EL1, user_val) || 2274 (vcpu_has_nv(vcpu) && !FIELD_GET(ID_AA64PFR0_EL1_EL2, user_val))) 2275 return -EINVAL; 2276 2277 return set_id_reg(vcpu, rd, user_val); 2278 } 2279 2280 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, 2281 const struct sys_reg_desc *rd, u64 user_val) 2282 { 2283 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 2284 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK; 2285 u8 mte = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE, hw_val); 2286 u8 user_mte_frac = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE_frac, user_val); 2287 u8 hw_mte_frac = SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE_frac, hw_val); 2288 2289 /* See set_id_aa64pfr0_el1 for comment about MPAM */ 2290 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 2291 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 2292 2293 /* 2294 * Previously MTE_frac was hidden from guest. However, if the 2295 * hardware supports MTE2 but not MTE_ASYM_FAULT then a value 2296 * of 0 for this field indicates that the hardware supports 2297 * MTE_ASYNC. Whereas, 0xf indicates MTE_ASYNC is not supported. 2298 * 2299 * As KVM must accept values from KVM provided by user-space, 2300 * when ID_AA64PFR1_EL1.MTE is 2 allow user-space to set 2301 * ID_AA64PFR1_EL1.MTE_frac to 0. However, ignore it to avoid 2302 * incorrectly claiming hardware support for MTE_ASYNC in the 2303 * guest. 2304 */ 2305 2306 if (mte == ID_AA64PFR1_EL1_MTE_MTE2 && 2307 hw_mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI && 2308 user_mte_frac == ID_AA64PFR1_EL1_MTE_frac_ASYNC) { 2309 user_val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK; 2310 user_val |= hw_val & ID_AA64PFR1_EL1_MTE_frac_MASK; 2311 } 2312 2313 return set_id_reg(vcpu, rd, user_val); 2314 } 2315 2316 static int set_id_aa64pfr2_el1(struct kvm_vcpu *vcpu, 2317 const struct sys_reg_desc *rd, u64 user_val) 2318 { 2319 return set_id_reg(vcpu, rd, user_val); 2320 } 2321 2322 /* 2323 * Allow userspace to de-feature a stage-2 translation granule but prevent it 2324 * from claiming the impossible. 2325 */ 2326 #define tgran2_val_allowed(tg, safe, user) \ 2327 ({ \ 2328 u8 __s = SYS_FIELD_GET(ID_AA64MMFR0_EL1, tg, safe); \ 2329 u8 __u = SYS_FIELD_GET(ID_AA64MMFR0_EL1, tg, user); \ 2330 \ 2331 __s == __u || __u == ID_AA64MMFR0_EL1_##tg##_NI; \ 2332 }) 2333 2334 static int set_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu, 2335 const struct sys_reg_desc *rd, u64 user_val) 2336 { 2337 u64 sanitized_val = kvm_read_sanitised_id_reg(vcpu, rd); 2338 2339 if (!vcpu_has_nv(vcpu)) 2340 return set_id_reg(vcpu, rd, user_val); 2341 2342 if (!tgran2_val_allowed(TGRAN4_2, sanitized_val, user_val) || 2343 !tgran2_val_allowed(TGRAN16_2, sanitized_val, user_val) || 2344 !tgran2_val_allowed(TGRAN64_2, sanitized_val, user_val)) 2345 return -EINVAL; 2346 2347 return set_id_reg(vcpu, rd, user_val); 2348 } 2349 2350 static int set_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu, 2351 const struct sys_reg_desc *rd, u64 user_val) 2352 { 2353 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); 2354 u64 nv_mask = ID_AA64MMFR2_EL1_NV_MASK; 2355 2356 /* 2357 * We made the mistake to expose the now deprecated NV field, 2358 * so allow userspace to write it, but silently ignore it. 2359 */ 2360 if ((hw_val & nv_mask) == (user_val & nv_mask)) 2361 user_val &= ~nv_mask; 2362 2363 return set_id_reg(vcpu, rd, user_val); 2364 } 2365 2366 static int set_ctr_el0(struct kvm_vcpu *vcpu, 2367 const struct sys_reg_desc *rd, u64 user_val) 2368 { 2369 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val); 2370 2371 /* 2372 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved. 2373 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based 2374 * on what hardware reports. 2375 * 2376 * Using a VIPT software model on PIPT will lead to over invalidation, 2377 * but still correct. Hence, we can allow downgrading PIPT to VIPT, 2378 * but not the other way around. This is handled via arm64_ftr_safe_value() 2379 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value 2380 * set as VIPT. 2381 */ 2382 switch (user_L1Ip) { 2383 case CTR_EL0_L1Ip_RESERVED_VPIPT: 2384 case CTR_EL0_L1Ip_RESERVED_AIVIVT: 2385 return -EINVAL; 2386 case CTR_EL0_L1Ip_VIPT: 2387 case CTR_EL0_L1Ip_PIPT: 2388 return set_id_reg(vcpu, rd, user_val); 2389 default: 2390 return -ENOENT; 2391 } 2392 } 2393 2394 /* 2395 * cpufeature ID register user accessors 2396 * 2397 * For now, these registers are immutable for userspace, so no values 2398 * are stored, and for set_id_reg() we don't allow the effective value 2399 * to be changed. 2400 */ 2401 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2402 u64 *val) 2403 { 2404 /* 2405 * Avoid locking if the VM has already started, as the ID registers are 2406 * guaranteed to be invariant at that point. 2407 */ 2408 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2409 *val = read_id_reg(vcpu, rd); 2410 return 0; 2411 } 2412 2413 mutex_lock(&vcpu->kvm->arch.config_lock); 2414 *val = read_id_reg(vcpu, rd); 2415 mutex_unlock(&vcpu->kvm->arch.config_lock); 2416 2417 return 0; 2418 } 2419 2420 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2421 u64 val) 2422 { 2423 u32 id = reg_to_encoding(rd); 2424 int ret; 2425 2426 mutex_lock(&vcpu->kvm->arch.config_lock); 2427 2428 /* 2429 * Once the VM has started the ID registers are immutable. Reject any 2430 * write that does not match the final register value. 2431 */ 2432 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2433 if (val != read_id_reg(vcpu, rd)) 2434 ret = -EBUSY; 2435 else 2436 ret = 0; 2437 2438 mutex_unlock(&vcpu->kvm->arch.config_lock); 2439 return ret; 2440 } 2441 2442 ret = arm64_check_features(vcpu, rd, val); 2443 if (!ret) 2444 kvm_set_vm_id_reg(vcpu->kvm, id, val); 2445 2446 mutex_unlock(&vcpu->kvm->arch.config_lock); 2447 2448 /* 2449 * arm64_check_features() returns -E2BIG to indicate the register's 2450 * feature set is a superset of the maximally-allowed register value. 2451 * While it would be nice to precisely describe this to userspace, the 2452 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 2453 * writes return -EINVAL. 2454 */ 2455 if (ret == -E2BIG) 2456 ret = -EINVAL; 2457 return ret; 2458 } 2459 2460 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 2461 { 2462 u64 *p = __vm_id_reg(&kvm->arch, reg); 2463 2464 lockdep_assert_held(&kvm->arch.config_lock); 2465 2466 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 2467 return; 2468 2469 *p = val; 2470 } 2471 2472 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2473 u64 *val) 2474 { 2475 *val = 0; 2476 return 0; 2477 } 2478 2479 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2480 u64 val) 2481 { 2482 return 0; 2483 } 2484 2485 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2486 const struct sys_reg_desc *r) 2487 { 2488 if (p->is_write) 2489 return write_to_read_only(vcpu, p, r); 2490 2491 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 2492 return true; 2493 } 2494 2495 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2496 const struct sys_reg_desc *r) 2497 { 2498 if (p->is_write) 2499 return write_to_read_only(vcpu, p, r); 2500 2501 p->regval = __vcpu_sys_reg(vcpu, r->reg); 2502 return true; 2503 } 2504 2505 /* 2506 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 2507 * by the physical CPU which the vcpu currently resides in. 2508 */ 2509 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2510 { 2511 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2512 u64 clidr; 2513 u8 loc; 2514 2515 if ((ctr_el0 & CTR_EL0_IDC)) { 2516 /* 2517 * Data cache clean to the PoU is not required so LoUU and LoUIS 2518 * will not be set and a unified cache, which will be marked as 2519 * LoC, will be added. 2520 * 2521 * If not DIC, let the unified cache L2 so that an instruction 2522 * cache can be added as L1 later. 2523 */ 2524 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2525 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2526 } else { 2527 /* 2528 * Data cache clean to the PoU is required so let L1 have a data 2529 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2530 * it can be marked as LoC too. 2531 */ 2532 loc = 1; 2533 clidr = 1 << CLIDR_LOUU_SHIFT; 2534 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2535 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2536 } 2537 2538 /* 2539 * Instruction cache invalidation to the PoU is required so let L1 have 2540 * an instruction cache. If L1 already has a data cache, it will be 2541 * CACHE_TYPE_SEPARATE. 2542 */ 2543 if (!(ctr_el0 & CTR_EL0_DIC)) 2544 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2545 2546 clidr |= loc << CLIDR_LOC_SHIFT; 2547 2548 /* 2549 * Add tag cache unified to data cache. Allocation tags and data are 2550 * unified in a cache line so that it looks valid even if there is only 2551 * one cache line. 2552 */ 2553 if (kvm_has_mte(vcpu->kvm)) 2554 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2555 2556 __vcpu_assign_sys_reg(vcpu, r->reg, clidr); 2557 2558 return __vcpu_sys_reg(vcpu, r->reg); 2559 } 2560 2561 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2562 u64 val) 2563 { 2564 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2565 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2566 2567 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2568 return -EINVAL; 2569 2570 __vcpu_assign_sys_reg(vcpu, rd->reg, val); 2571 2572 return 0; 2573 } 2574 2575 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2576 const struct sys_reg_desc *r) 2577 { 2578 int reg = r->reg; 2579 2580 if (p->is_write) 2581 vcpu_write_sys_reg(vcpu, p->regval, reg); 2582 else 2583 p->regval = vcpu_read_sys_reg(vcpu, reg); 2584 return true; 2585 } 2586 2587 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2588 const struct sys_reg_desc *r) 2589 { 2590 u32 csselr; 2591 2592 if (p->is_write) 2593 return write_to_read_only(vcpu, p, r); 2594 2595 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2596 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2597 if (csselr < CSSELR_MAX) 2598 p->regval = get_ccsidr(vcpu, csselr); 2599 2600 return true; 2601 } 2602 2603 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2604 const struct sys_reg_desc *rd) 2605 { 2606 if (kvm_has_mte(vcpu->kvm)) 2607 return 0; 2608 2609 return REG_HIDDEN; 2610 } 2611 2612 #define MTE_REG(name) { \ 2613 SYS_DESC(SYS_##name), \ 2614 .access = undef_access, \ 2615 .reset = reset_unknown, \ 2616 .reg = name, \ 2617 .visibility = mte_visibility, \ 2618 } 2619 2620 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2621 const struct sys_reg_desc *rd) 2622 { 2623 if (vcpu_has_nv(vcpu)) 2624 return 0; 2625 2626 return REG_HIDDEN; 2627 } 2628 2629 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2630 struct sys_reg_params *p, 2631 const struct sys_reg_desc *r) 2632 { 2633 /* 2634 * We really shouldn't be here, and this is likely the result 2635 * of a misconfigured trap, as this register should target the 2636 * VNCR page, and nothing else. 2637 */ 2638 return bad_trap(vcpu, p, r, 2639 "trap of VNCR-backed register"); 2640 } 2641 2642 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2643 struct sys_reg_params *p, 2644 const struct sys_reg_desc *r) 2645 { 2646 /* 2647 * We really shouldn't be here, and this is likely the result 2648 * of a misconfigured trap, as this register should target the 2649 * corresponding EL1, and nothing else. 2650 */ 2651 return bad_trap(vcpu, p, r, 2652 "trap of EL2 register redirected to EL1"); 2653 } 2654 2655 #define SYS_REG_USER_FILTER(name, acc, rst, v, gu, su, filter) { \ 2656 SYS_DESC(SYS_##name), \ 2657 .access = acc, \ 2658 .reset = rst, \ 2659 .reg = name, \ 2660 .get_user = gu, \ 2661 .set_user = su, \ 2662 .visibility = filter, \ 2663 .val = v, \ 2664 } 2665 2666 #define EL2_REG_FILTERED(name, acc, rst, v, filter) \ 2667 SYS_REG_USER_FILTER(name, acc, rst, v, NULL, NULL, filter) 2668 2669 #define EL2_REG(name, acc, rst, v) \ 2670 EL2_REG_FILTERED(name, acc, rst, v, el2_visibility) 2671 2672 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2673 #define EL2_REG_VNCR_FILT(name, vis) \ 2674 EL2_REG_FILTERED(name, bad_vncr_trap, reset_val, 0, vis) 2675 #define EL2_REG_VNCR_GICv3(name) \ 2676 EL2_REG_VNCR_FILT(name, hidden_visibility) 2677 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2678 2679 #define TIMER_REG(name, vis) \ 2680 SYS_REG_USER_FILTER(name, access_arch_timer, reset_val, 0, \ 2681 arch_timer_get_user, arch_timer_set_user, vis) 2682 2683 /* 2684 * Since reset() callback and field val are not used for idregs, they will be 2685 * used for specific purposes for idregs. 2686 * The reset() would return KVM sanitised register value. The value would be the 2687 * same as the host kernel sanitised value if there is no KVM sanitisation. 2688 * The val would be used as a mask indicating writable fields for the idreg. 2689 * Only bits with 1 are writable from userspace. This mask might not be 2690 * necessary in the future whenever all ID registers are enabled as writable 2691 * from userspace. 2692 */ 2693 2694 #define ID_DESC_DEFAULT_CALLBACKS \ 2695 .access = access_id_reg, \ 2696 .get_user = get_id_reg, \ 2697 .set_user = set_id_reg, \ 2698 .visibility = id_visibility, \ 2699 .reset = kvm_read_sanitised_id_reg 2700 2701 #define ID_DESC(name) \ 2702 SYS_DESC(SYS_##name), \ 2703 ID_DESC_DEFAULT_CALLBACKS 2704 2705 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2706 #define ID_SANITISED(name) { \ 2707 ID_DESC(name), \ 2708 .val = 0, \ 2709 } 2710 2711 /* sys_reg_desc initialiser for writable ID registers */ 2712 #define ID_WRITABLE(name, mask) { \ 2713 ID_DESC(name), \ 2714 .val = mask, \ 2715 } 2716 2717 /* 2718 * 32bit ID regs are fully writable when the guest is 32bit 2719 * capable. Nothing in the KVM code should rely on 32bit features 2720 * anyway, only 64bit, so let the VMM do its worse. 2721 */ 2722 #define AA32_ID_WRITABLE(name) { \ 2723 ID_DESC(name), \ 2724 .visibility = aa32_id_visibility, \ 2725 .val = GENMASK(31, 0), \ 2726 } 2727 2728 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */ 2729 #define ID_FILTERED(sysreg, name, mask) { \ 2730 ID_DESC(sysreg), \ 2731 .set_user = set_##name, \ 2732 .val = (mask), \ 2733 } 2734 2735 /* 2736 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2737 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2738 * (1 <= crm < 8, 0 <= Op2 < 8). 2739 */ 2740 #define ID_UNALLOCATED(crm, op2) { \ 2741 .name = "S3_0_0_" #crm "_" #op2, \ 2742 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2743 ID_DESC_DEFAULT_CALLBACKS, \ 2744 .visibility = raz_visibility, \ 2745 .val = 0, \ 2746 } 2747 2748 /* 2749 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2750 * For now, these are exposed just like unallocated ID regs: they appear 2751 * RAZ for the guest. 2752 */ 2753 #define ID_HIDDEN(name) { \ 2754 ID_DESC(name), \ 2755 .visibility = raz_visibility, \ 2756 .val = 0, \ 2757 } 2758 2759 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2760 struct sys_reg_params *p, 2761 const struct sys_reg_desc *r) 2762 { 2763 if (p->is_write) 2764 __vcpu_assign_sys_reg(vcpu, SP_EL1, p->regval); 2765 else 2766 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2767 2768 return true; 2769 } 2770 2771 static bool access_elr(struct kvm_vcpu *vcpu, 2772 struct sys_reg_params *p, 2773 const struct sys_reg_desc *r) 2774 { 2775 if (p->is_write) 2776 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2777 else 2778 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2779 2780 return true; 2781 } 2782 2783 static bool access_spsr(struct kvm_vcpu *vcpu, 2784 struct sys_reg_params *p, 2785 const struct sys_reg_desc *r) 2786 { 2787 if (p->is_write) 2788 __vcpu_assign_sys_reg(vcpu, SPSR_EL1, p->regval); 2789 else 2790 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2791 2792 return true; 2793 } 2794 2795 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2796 struct sys_reg_params *p, 2797 const struct sys_reg_desc *r) 2798 { 2799 if (p->is_write) 2800 __vcpu_assign_sys_reg(vcpu, CNTKCTL_EL1, p->regval); 2801 else 2802 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2803 2804 return true; 2805 } 2806 2807 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2808 { 2809 u64 val = r->val; 2810 2811 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2812 val |= HCR_E2H; 2813 2814 __vcpu_assign_sys_reg(vcpu, r->reg, val); 2815 2816 return __vcpu_sys_reg(vcpu, r->reg); 2817 } 2818 2819 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu, 2820 const struct sys_reg_desc *rd, 2821 unsigned int (*fn)(const struct kvm_vcpu *, 2822 const struct sys_reg_desc *)) 2823 { 2824 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd); 2825 } 2826 2827 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2828 const struct sys_reg_desc *rd) 2829 { 2830 return __el2_visibility(vcpu, rd, sve_visibility); 2831 } 2832 2833 static unsigned int vncr_el2_visibility(const struct kvm_vcpu *vcpu, 2834 const struct sys_reg_desc *rd) 2835 { 2836 if (el2_visibility(vcpu, rd) == 0 && 2837 kvm_has_feat(vcpu->kvm, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY)) 2838 return 0; 2839 2840 return REG_HIDDEN; 2841 } 2842 2843 static unsigned int sctlr2_visibility(const struct kvm_vcpu *vcpu, 2844 const struct sys_reg_desc *rd) 2845 { 2846 if (kvm_has_sctlr2(vcpu->kvm)) 2847 return 0; 2848 2849 return REG_HIDDEN; 2850 } 2851 2852 static unsigned int sctlr2_el2_visibility(const struct kvm_vcpu *vcpu, 2853 const struct sys_reg_desc *rd) 2854 { 2855 return __el2_visibility(vcpu, rd, sctlr2_visibility); 2856 } 2857 2858 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2859 struct sys_reg_params *p, 2860 const struct sys_reg_desc *r) 2861 { 2862 if (guest_hyp_sve_traps_enabled(vcpu)) { 2863 kvm_inject_nested_sve_trap(vcpu); 2864 return false; 2865 } 2866 2867 if (!p->is_write) 2868 p->regval = __vcpu_sys_reg(vcpu, ZCR_EL2); 2869 else 2870 __vcpu_assign_sys_reg(vcpu, ZCR_EL2, p->regval); 2871 2872 return true; 2873 } 2874 2875 static bool access_gic_vtr(struct kvm_vcpu *vcpu, 2876 struct sys_reg_params *p, 2877 const struct sys_reg_desc *r) 2878 { 2879 if (p->is_write) 2880 return write_to_read_only(vcpu, p, r); 2881 2882 p->regval = kvm_get_guest_vtr_el2(); 2883 2884 return true; 2885 } 2886 2887 static bool access_gic_misr(struct kvm_vcpu *vcpu, 2888 struct sys_reg_params *p, 2889 const struct sys_reg_desc *r) 2890 { 2891 if (p->is_write) 2892 return write_to_read_only(vcpu, p, r); 2893 2894 p->regval = vgic_v3_get_misr(vcpu); 2895 2896 return true; 2897 } 2898 2899 static bool access_gic_eisr(struct kvm_vcpu *vcpu, 2900 struct sys_reg_params *p, 2901 const struct sys_reg_desc *r) 2902 { 2903 if (p->is_write) 2904 return write_to_read_only(vcpu, p, r); 2905 2906 p->regval = vgic_v3_get_eisr(vcpu); 2907 2908 return true; 2909 } 2910 2911 static bool access_gic_elrsr(struct kvm_vcpu *vcpu, 2912 struct sys_reg_params *p, 2913 const struct sys_reg_desc *r) 2914 { 2915 if (p->is_write) 2916 return write_to_read_only(vcpu, p, r); 2917 2918 p->regval = vgic_v3_get_elrsr(vcpu); 2919 2920 return true; 2921 } 2922 2923 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 2924 const struct sys_reg_desc *rd) 2925 { 2926 if (kvm_has_s1poe(vcpu->kvm)) 2927 return 0; 2928 2929 return REG_HIDDEN; 2930 } 2931 2932 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu, 2933 const struct sys_reg_desc *rd) 2934 { 2935 return __el2_visibility(vcpu, rd, s1poe_visibility); 2936 } 2937 2938 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu, 2939 const struct sys_reg_desc *rd) 2940 { 2941 if (kvm_has_tcr2(vcpu->kvm)) 2942 return 0; 2943 2944 return REG_HIDDEN; 2945 } 2946 2947 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu, 2948 const struct sys_reg_desc *rd) 2949 { 2950 return __el2_visibility(vcpu, rd, tcr2_visibility); 2951 } 2952 2953 static unsigned int fgt2_visibility(const struct kvm_vcpu *vcpu, 2954 const struct sys_reg_desc *rd) 2955 { 2956 if (el2_visibility(vcpu, rd) == 0 && 2957 kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, FGT, FGT2)) 2958 return 0; 2959 2960 return REG_HIDDEN; 2961 } 2962 2963 static unsigned int fgt_visibility(const struct kvm_vcpu *vcpu, 2964 const struct sys_reg_desc *rd) 2965 { 2966 if (el2_visibility(vcpu, rd) == 0 && 2967 kvm_has_feat(vcpu->kvm, ID_AA64MMFR0_EL1, FGT, IMP)) 2968 return 0; 2969 2970 return REG_HIDDEN; 2971 } 2972 2973 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu, 2974 const struct sys_reg_desc *rd) 2975 { 2976 if (kvm_has_s1pie(vcpu->kvm)) 2977 return 0; 2978 2979 return REG_HIDDEN; 2980 } 2981 2982 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, 2983 const struct sys_reg_desc *rd) 2984 { 2985 return __el2_visibility(vcpu, rd, s1pie_visibility); 2986 } 2987 2988 static unsigned int cnthv_visibility(const struct kvm_vcpu *vcpu, 2989 const struct sys_reg_desc *rd) 2990 { 2991 if (vcpu_has_nv(vcpu) && 2992 !vcpu_has_feature(vcpu, KVM_ARM_VCPU_HAS_EL2_E2H0)) 2993 return 0; 2994 2995 return REG_HIDDEN; 2996 } 2997 2998 static bool access_mdcr(struct kvm_vcpu *vcpu, 2999 struct sys_reg_params *p, 3000 const struct sys_reg_desc *r) 3001 { 3002 u64 hpmn, val, old = __vcpu_sys_reg(vcpu, MDCR_EL2); 3003 3004 if (!p->is_write) { 3005 p->regval = old; 3006 return true; 3007 } 3008 3009 val = p->regval; 3010 hpmn = FIELD_GET(MDCR_EL2_HPMN, val); 3011 3012 /* 3013 * If HPMN is out of bounds, limit it to what we actually 3014 * support. This matches the UNKNOWN definition of the field 3015 * in that case, and keeps the emulation simple. Sort of. 3016 */ 3017 if (hpmn > vcpu->kvm->arch.nr_pmu_counters) { 3018 hpmn = vcpu->kvm->arch.nr_pmu_counters; 3019 u64p_replace_bits(&val, hpmn, MDCR_EL2_HPMN); 3020 } 3021 3022 __vcpu_assign_sys_reg(vcpu, MDCR_EL2, val); 3023 3024 /* 3025 * Request a reload of the PMU to enable/disable the counters 3026 * affected by HPME. 3027 */ 3028 if ((old ^ val) & MDCR_EL2_HPME) 3029 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 3030 3031 return true; 3032 } 3033 3034 static bool access_ras(struct kvm_vcpu *vcpu, 3035 struct sys_reg_params *p, 3036 const struct sys_reg_desc *r) 3037 { 3038 struct kvm *kvm = vcpu->kvm; 3039 3040 switch(reg_to_encoding(r)) { 3041 case SYS_ERXPFGCDN_EL1: 3042 case SYS_ERXPFGCTL_EL1: 3043 case SYS_ERXPFGF_EL1: 3044 case SYS_ERXMISC2_EL1: 3045 case SYS_ERXMISC3_EL1: 3046 if (!(kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) || 3047 (kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, IMP) && 3048 kvm_has_feat(kvm, ID_AA64PFR1_EL1, RAS_frac, RASv1p1)))) { 3049 kvm_inject_undefined(vcpu); 3050 return false; 3051 } 3052 break; 3053 default: 3054 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) { 3055 kvm_inject_undefined(vcpu); 3056 return false; 3057 } 3058 } 3059 3060 return trap_raz_wi(vcpu, p, r); 3061 } 3062 3063 /* 3064 * For historical (ahem ABI) reasons, KVM treated MIDR_EL1, REVIDR_EL1, and 3065 * AIDR_EL1 as "invariant" registers, meaning userspace cannot change them. 3066 * The values made visible to userspace were the register values of the boot 3067 * CPU. 3068 * 3069 * At the same time, reads from these registers at EL1 previously were not 3070 * trapped, allowing the guest to read the actual hardware value. On big-little 3071 * machines, this means the VM can see different values depending on where a 3072 * given vCPU got scheduled. 3073 * 3074 * These registers are now trapped as collateral damage from SME, and what 3075 * follows attempts to give a user / guest view consistent with the existing 3076 * ABI. 3077 */ 3078 static bool access_imp_id_reg(struct kvm_vcpu *vcpu, 3079 struct sys_reg_params *p, 3080 const struct sys_reg_desc *r) 3081 { 3082 if (p->is_write) 3083 return write_to_read_only(vcpu, p, r); 3084 3085 /* 3086 * Return the VM-scoped implementation ID register values if userspace 3087 * has made them writable. 3088 */ 3089 if (test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &vcpu->kvm->arch.flags)) 3090 return access_id_reg(vcpu, p, r); 3091 3092 /* 3093 * Otherwise, fall back to the old behavior of returning the value of 3094 * the current CPU. 3095 */ 3096 switch (reg_to_encoding(r)) { 3097 case SYS_REVIDR_EL1: 3098 p->regval = read_sysreg(revidr_el1); 3099 break; 3100 case SYS_AIDR_EL1: 3101 p->regval = read_sysreg(aidr_el1); 3102 break; 3103 default: 3104 WARN_ON_ONCE(1); 3105 } 3106 3107 return true; 3108 } 3109 3110 static u64 __ro_after_init boot_cpu_midr_val; 3111 static u64 __ro_after_init boot_cpu_revidr_val; 3112 static u64 __ro_after_init boot_cpu_aidr_val; 3113 3114 static void init_imp_id_regs(void) 3115 { 3116 boot_cpu_midr_val = read_sysreg(midr_el1); 3117 boot_cpu_revidr_val = read_sysreg(revidr_el1); 3118 boot_cpu_aidr_val = read_sysreg(aidr_el1); 3119 } 3120 3121 static u64 reset_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 3122 { 3123 switch (reg_to_encoding(r)) { 3124 case SYS_MIDR_EL1: 3125 return boot_cpu_midr_val; 3126 case SYS_REVIDR_EL1: 3127 return boot_cpu_revidr_val; 3128 case SYS_AIDR_EL1: 3129 return boot_cpu_aidr_val; 3130 default: 3131 KVM_BUG_ON(1, vcpu->kvm); 3132 return 0; 3133 } 3134 } 3135 3136 static int set_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 3137 u64 val) 3138 { 3139 struct kvm *kvm = vcpu->kvm; 3140 u64 expected; 3141 3142 guard(mutex)(&kvm->arch.config_lock); 3143 3144 expected = read_id_reg(vcpu, r); 3145 if (expected == val) 3146 return 0; 3147 3148 if (!test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &kvm->arch.flags)) 3149 return -EINVAL; 3150 3151 /* 3152 * Once the VM has started the ID registers are immutable. Reject the 3153 * write if userspace tries to change it. 3154 */ 3155 if (kvm_vm_has_ran_once(kvm)) 3156 return -EBUSY; 3157 3158 /* 3159 * Any value is allowed for the implementation ID registers so long as 3160 * it is within the writable mask. 3161 */ 3162 if ((val & r->val) != val) 3163 return -EINVAL; 3164 3165 kvm_set_vm_id_reg(kvm, reg_to_encoding(r), val); 3166 return 0; 3167 } 3168 3169 #define IMPLEMENTATION_ID(reg, mask) { \ 3170 SYS_DESC(SYS_##reg), \ 3171 .access = access_imp_id_reg, \ 3172 .get_user = get_id_reg, \ 3173 .set_user = set_imp_id_reg, \ 3174 .reset = reset_imp_id_reg, \ 3175 .val = mask, \ 3176 } 3177 3178 static u64 reset_mdcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 3179 { 3180 __vcpu_assign_sys_reg(vcpu, r->reg, vcpu->kvm->arch.nr_pmu_counters); 3181 return vcpu->kvm->arch.nr_pmu_counters; 3182 } 3183 3184 /* 3185 * Architected system registers. 3186 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 3187 * 3188 * Debug handling: We do trap most, if not all debug related system 3189 * registers. The implementation is good enough to ensure that a guest 3190 * can use these with minimal performance degradation. The drawback is 3191 * that we don't implement any of the external debug architecture. 3192 * This should be revisited if we ever encounter a more demanding 3193 * guest... 3194 */ 3195 static const struct sys_reg_desc sys_reg_descs[] = { 3196 DBG_BCR_BVR_WCR_WVR_EL1(0), 3197 DBG_BCR_BVR_WCR_WVR_EL1(1), 3198 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 3199 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 3200 DBG_BCR_BVR_WCR_WVR_EL1(2), 3201 DBG_BCR_BVR_WCR_WVR_EL1(3), 3202 DBG_BCR_BVR_WCR_WVR_EL1(4), 3203 DBG_BCR_BVR_WCR_WVR_EL1(5), 3204 DBG_BCR_BVR_WCR_WVR_EL1(6), 3205 DBG_BCR_BVR_WCR_WVR_EL1(7), 3206 DBG_BCR_BVR_WCR_WVR_EL1(8), 3207 DBG_BCR_BVR_WCR_WVR_EL1(9), 3208 DBG_BCR_BVR_WCR_WVR_EL1(10), 3209 DBG_BCR_BVR_WCR_WVR_EL1(11), 3210 DBG_BCR_BVR_WCR_WVR_EL1(12), 3211 DBG_BCR_BVR_WCR_WVR_EL1(13), 3212 DBG_BCR_BVR_WCR_WVR_EL1(14), 3213 DBG_BCR_BVR_WCR_WVR_EL1(15), 3214 3215 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 3216 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 3217 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 3218 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 3219 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 3220 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 3221 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 3222 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 3223 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 3224 3225 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 3226 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 3227 // DBGDTR[TR]X_EL0 share the same encoding 3228 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 3229 3230 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 3231 3232 IMPLEMENTATION_ID(MIDR_EL1, GENMASK_ULL(31, 0)), 3233 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 3234 IMPLEMENTATION_ID(REVIDR_EL1, GENMASK_ULL(63, 0)), 3235 3236 /* 3237 * ID regs: all ID_SANITISED() entries here must have corresponding 3238 * entries in arm64_ftr_regs[]. 3239 */ 3240 3241 /* AArch64 mappings of the AArch32 ID registers */ 3242 /* CRm=1 */ 3243 AA32_ID_WRITABLE(ID_PFR0_EL1), 3244 AA32_ID_WRITABLE(ID_PFR1_EL1), 3245 { SYS_DESC(SYS_ID_DFR0_EL1), 3246 .access = access_id_reg, 3247 .get_user = get_id_reg, 3248 .set_user = set_id_dfr0_el1, 3249 .visibility = aa32_id_visibility, 3250 .reset = read_sanitised_id_dfr0_el1, 3251 .val = GENMASK(31, 0) }, 3252 ID_HIDDEN(ID_AFR0_EL1), 3253 AA32_ID_WRITABLE(ID_MMFR0_EL1), 3254 AA32_ID_WRITABLE(ID_MMFR1_EL1), 3255 AA32_ID_WRITABLE(ID_MMFR2_EL1), 3256 AA32_ID_WRITABLE(ID_MMFR3_EL1), 3257 3258 /* CRm=2 */ 3259 AA32_ID_WRITABLE(ID_ISAR0_EL1), 3260 AA32_ID_WRITABLE(ID_ISAR1_EL1), 3261 AA32_ID_WRITABLE(ID_ISAR2_EL1), 3262 AA32_ID_WRITABLE(ID_ISAR3_EL1), 3263 AA32_ID_WRITABLE(ID_ISAR4_EL1), 3264 AA32_ID_WRITABLE(ID_ISAR5_EL1), 3265 AA32_ID_WRITABLE(ID_MMFR4_EL1), 3266 AA32_ID_WRITABLE(ID_ISAR6_EL1), 3267 3268 /* CRm=3 */ 3269 AA32_ID_WRITABLE(MVFR0_EL1), 3270 AA32_ID_WRITABLE(MVFR1_EL1), 3271 AA32_ID_WRITABLE(MVFR2_EL1), 3272 ID_UNALLOCATED(3,3), 3273 AA32_ID_WRITABLE(ID_PFR2_EL1), 3274 ID_HIDDEN(ID_DFR1_EL1), 3275 AA32_ID_WRITABLE(ID_MMFR5_EL1), 3276 ID_UNALLOCATED(3,7), 3277 3278 /* AArch64 ID registers */ 3279 /* CRm=4 */ 3280 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1, 3281 ~(ID_AA64PFR0_EL1_AMU | 3282 ID_AA64PFR0_EL1_MPAM | 3283 ID_AA64PFR0_EL1_SVE | 3284 ID_AA64PFR0_EL1_AdvSIMD | 3285 ID_AA64PFR0_EL1_FP)), 3286 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, 3287 ~(ID_AA64PFR1_EL1_PFAR | 3288 ID_AA64PFR1_EL1_MTEX | 3289 ID_AA64PFR1_EL1_THE | 3290 ID_AA64PFR1_EL1_GCS | 3291 ID_AA64PFR1_EL1_MTE_frac | 3292 ID_AA64PFR1_EL1_NMI | 3293 ID_AA64PFR1_EL1_RNDR_trap | 3294 ID_AA64PFR1_EL1_SME | 3295 ID_AA64PFR1_EL1_RES0 | 3296 ID_AA64PFR1_EL1_MPAM_frac | 3297 ID_AA64PFR1_EL1_MTE)), 3298 ID_FILTERED(ID_AA64PFR2_EL1, id_aa64pfr2_el1, 3299 (ID_AA64PFR2_EL1_FPMR | 3300 ID_AA64PFR2_EL1_MTEFAR | 3301 ID_AA64PFR2_EL1_MTESTOREONLY | 3302 ID_AA64PFR2_EL1_GCIE)), 3303 ID_UNALLOCATED(4,3), 3304 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 3305 ID_HIDDEN(ID_AA64SMFR0_EL1), 3306 ID_UNALLOCATED(4,6), 3307 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 3308 3309 /* CRm=5 */ 3310 /* 3311 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 3312 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 3313 * KVM does not trap + emulate the breakpoint registers, and as such 3314 * cannot support a layout that misaligns with the underlying hardware. 3315 * While it may be possible to describe a subset that aligns with 3316 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 3317 * simplicity. 3318 * 3319 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 3320 * of breakpoints for more details. 3321 */ 3322 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, 3323 ID_AA64DFR0_EL1_DoubleLock_MASK | 3324 ID_AA64DFR0_EL1_WRPs_MASK | 3325 ID_AA64DFR0_EL1_PMUVer_MASK | 3326 ID_AA64DFR0_EL1_DebugVer_MASK), 3327 ID_SANITISED(ID_AA64DFR1_EL1), 3328 ID_UNALLOCATED(5,2), 3329 ID_UNALLOCATED(5,3), 3330 ID_HIDDEN(ID_AA64AFR0_EL1), 3331 ID_HIDDEN(ID_AA64AFR1_EL1), 3332 ID_UNALLOCATED(5,6), 3333 ID_UNALLOCATED(5,7), 3334 3335 /* CRm=6 */ 3336 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 3337 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 3338 ID_AA64ISAR1_EL1_GPA | 3339 ID_AA64ISAR1_EL1_API | 3340 ID_AA64ISAR1_EL1_APA)), 3341 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 3342 ID_AA64ISAR2_EL1_APA3 | 3343 ID_AA64ISAR2_EL1_GPA3)), 3344 ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT | 3345 ID_AA64ISAR3_EL1_LSFE | 3346 ID_AA64ISAR3_EL1_LSUI | 3347 ID_AA64ISAR3_EL1_FAMINMAX)), 3348 ID_UNALLOCATED(6,4), 3349 ID_UNALLOCATED(6,5), 3350 ID_UNALLOCATED(6,6), 3351 ID_UNALLOCATED(6,7), 3352 3353 /* CRm=7 */ 3354 ID_FILTERED(ID_AA64MMFR0_EL1, id_aa64mmfr0_el1, 3355 ~(ID_AA64MMFR0_EL1_RES0 | 3356 ID_AA64MMFR0_EL1_ASIDBITS)), 3357 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 3358 ID_AA64MMFR1_EL1_XNX | 3359 ID_AA64MMFR1_EL1_VH | 3360 ID_AA64MMFR1_EL1_VMIDBits)), 3361 ID_FILTERED(ID_AA64MMFR2_EL1, 3362 id_aa64mmfr2_el1, ~(ID_AA64MMFR2_EL1_RES0 | 3363 ID_AA64MMFR2_EL1_EVT | 3364 ID_AA64MMFR2_EL1_FWB | 3365 ID_AA64MMFR2_EL1_IDS | 3366 ID_AA64MMFR2_EL1_NV | 3367 ID_AA64MMFR2_EL1_CCIDX)), 3368 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 3369 ID_AA64MMFR3_EL1_SCTLRX | 3370 ID_AA64MMFR3_EL1_S1PIE | 3371 ID_AA64MMFR3_EL1_S1POE)), 3372 ID_WRITABLE(ID_AA64MMFR4_EL1, ID_AA64MMFR4_EL1_NV_frac), 3373 ID_UNALLOCATED(7,5), 3374 ID_UNALLOCATED(7,6), 3375 ID_UNALLOCATED(7,7), 3376 3377 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 3378 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 3379 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 3380 { SYS_DESC(SYS_SCTLR2_EL1), access_vm_reg, reset_val, SCTLR2_EL1, 0, 3381 .visibility = sctlr2_visibility }, 3382 3383 MTE_REG(RGSR_EL1), 3384 MTE_REG(GCR_EL1), 3385 3386 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 3387 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 3388 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 3389 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 3390 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 3391 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 3392 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 3393 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0, 3394 .visibility = tcr2_visibility }, 3395 3396 PTRAUTH_KEY(APIA), 3397 PTRAUTH_KEY(APIB), 3398 PTRAUTH_KEY(APDA), 3399 PTRAUTH_KEY(APDB), 3400 PTRAUTH_KEY(APGA), 3401 3402 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 3403 { SYS_DESC(SYS_ELR_EL1), access_elr}, 3404 3405 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 3406 3407 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 3408 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 3409 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 3410 3411 { SYS_DESC(SYS_ERRIDR_EL1), access_ras }, 3412 { SYS_DESC(SYS_ERRSELR_EL1), access_ras }, 3413 { SYS_DESC(SYS_ERXFR_EL1), access_ras }, 3414 { SYS_DESC(SYS_ERXCTLR_EL1), access_ras }, 3415 { SYS_DESC(SYS_ERXSTATUS_EL1), access_ras }, 3416 { SYS_DESC(SYS_ERXADDR_EL1), access_ras }, 3417 { SYS_DESC(SYS_ERXPFGF_EL1), access_ras }, 3418 { SYS_DESC(SYS_ERXPFGCTL_EL1), access_ras }, 3419 { SYS_DESC(SYS_ERXPFGCDN_EL1), access_ras }, 3420 { SYS_DESC(SYS_ERXMISC0_EL1), access_ras }, 3421 { SYS_DESC(SYS_ERXMISC1_EL1), access_ras }, 3422 { SYS_DESC(SYS_ERXMISC2_EL1), access_ras }, 3423 { SYS_DESC(SYS_ERXMISC3_EL1), access_ras }, 3424 3425 MTE_REG(TFSR_EL1), 3426 MTE_REG(TFSRE0_EL1), 3427 3428 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 3429 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 3430 3431 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 3432 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 3433 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 3434 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 3435 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 3436 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 3437 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 3438 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 3439 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 3440 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 3441 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 3442 { SYS_DESC(SYS_PMSDSFR_EL1), undef_access }, 3443 /* PMBIDR_EL1 is not trapped */ 3444 3445 { PMU_SYS_REG(PMINTENSET_EL1), 3446 .access = access_pminten, .reg = PMINTENSET_EL1, 3447 .get_user = get_pmreg, .set_user = set_pmreg }, 3448 { PMU_SYS_REG(PMINTENCLR_EL1), 3449 .access = access_pminten, .reg = PMINTENSET_EL1, 3450 .get_user = get_pmreg, .set_user = set_pmreg }, 3451 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 3452 3453 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 3454 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1, 3455 .visibility = s1pie_visibility }, 3456 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1, 3457 .visibility = s1pie_visibility }, 3458 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 3459 .visibility = s1poe_visibility }, 3460 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 3461 3462 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 3463 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 3464 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 3465 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 3466 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access }, 3467 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 3468 3469 { SYS_DESC(SYS_MPAM1_EL1), undef_access }, 3470 { SYS_DESC(SYS_MPAM0_EL1), undef_access }, 3471 { SYS_DESC(SYS_MPAMSM_EL1), undef_access }, 3472 3473 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 3474 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 3475 3476 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3477 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3478 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3479 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3480 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3481 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3482 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3483 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3484 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3485 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3486 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3487 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3488 { SYS_DESC(SYS_ICC_IDR0_EL1), access_gicv5_idr0 }, 3489 { SYS_DESC(SYS_ICC_IAFFIDR_EL1), access_gicv5_iaffid }, 3490 { SYS_DESC(SYS_ICC_PPI_ENABLER0_EL1), access_gicv5_ppi_enabler }, 3491 { SYS_DESC(SYS_ICC_PPI_ENABLER1_EL1), access_gicv5_ppi_enabler }, 3492 { SYS_DESC(SYS_ICC_DIR_EL1), access_gic_dir }, 3493 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3494 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 3495 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 3496 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 3497 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3498 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3499 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3500 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3501 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3502 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3503 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3504 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3505 3506 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 3507 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 3508 3509 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 3510 3511 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 3512 3513 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 3514 3515 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 3516 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 3517 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 3518 IMPLEMENTATION_ID(AIDR_EL1, GENMASK_ULL(63, 0)), 3519 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 3520 ID_FILTERED(CTR_EL0, ctr_el0, 3521 CTR_EL0_DIC_MASK | 3522 CTR_EL0_IDC_MASK | 3523 CTR_EL0_DminLine_MASK | 3524 CTR_EL0_L1Ip_MASK | 3525 CTR_EL0_IminLine_MASK), 3526 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 3527 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 3528 3529 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 3530 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 3531 { PMU_SYS_REG(PMCNTENSET_EL0), 3532 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 3533 .get_user = get_pmreg, .set_user = set_pmreg }, 3534 { PMU_SYS_REG(PMCNTENCLR_EL0), 3535 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 3536 .get_user = get_pmreg, .set_user = set_pmreg }, 3537 { PMU_SYS_REG(PMOVSCLR_EL0), 3538 .access = access_pmovs, .reg = PMOVSSET_EL0, 3539 .get_user = get_pmreg, .set_user = set_pmreg }, 3540 /* 3541 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 3542 * previously (and pointlessly) advertised in the past... 3543 */ 3544 { PMU_SYS_REG(PMSWINC_EL0), 3545 .get_user = get_raz_reg, .set_user = set_wi_reg, 3546 .access = access_pmswinc, .reset = NULL }, 3547 { PMU_SYS_REG(PMSELR_EL0), 3548 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 3549 { PMU_SYS_REG(PMCEID0_EL0), 3550 .access = access_pmceid, .reset = NULL }, 3551 { PMU_SYS_REG(PMCEID1_EL0), 3552 .access = access_pmceid, .reset = NULL }, 3553 { PMU_SYS_REG(PMCCNTR_EL0), 3554 .access = access_pmu_evcntr, .reset = reset_unknown, 3555 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr, 3556 .set_user = set_pmu_evcntr }, 3557 { PMU_SYS_REG(PMXEVTYPER_EL0), 3558 .access = access_pmu_evtyper, .reset = NULL }, 3559 { PMU_SYS_REG(PMXEVCNTR_EL0), 3560 .access = access_pmu_evcntr, .reset = NULL }, 3561 /* 3562 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 3563 * in 32bit mode. Here we choose to reset it as zero for consistency. 3564 */ 3565 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 3566 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 3567 { PMU_SYS_REG(PMOVSSET_EL0), 3568 .access = access_pmovs, .reg = PMOVSSET_EL0, 3569 .get_user = get_pmreg, .set_user = set_pmreg }, 3570 3571 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 3572 .visibility = s1poe_visibility }, 3573 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 3574 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 3575 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 3576 3577 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 3578 3579 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 3580 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 3581 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 3582 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 3583 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 3584 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 3585 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 3586 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 3587 AMU_AMEVCNTR0_EL0(0), 3588 AMU_AMEVCNTR0_EL0(1), 3589 AMU_AMEVCNTR0_EL0(2), 3590 AMU_AMEVCNTR0_EL0(3), 3591 AMU_AMEVCNTR0_EL0(4), 3592 AMU_AMEVCNTR0_EL0(5), 3593 AMU_AMEVCNTR0_EL0(6), 3594 AMU_AMEVCNTR0_EL0(7), 3595 AMU_AMEVCNTR0_EL0(8), 3596 AMU_AMEVCNTR0_EL0(9), 3597 AMU_AMEVCNTR0_EL0(10), 3598 AMU_AMEVCNTR0_EL0(11), 3599 AMU_AMEVCNTR0_EL0(12), 3600 AMU_AMEVCNTR0_EL0(13), 3601 AMU_AMEVCNTR0_EL0(14), 3602 AMU_AMEVCNTR0_EL0(15), 3603 AMU_AMEVTYPER0_EL0(0), 3604 AMU_AMEVTYPER0_EL0(1), 3605 AMU_AMEVTYPER0_EL0(2), 3606 AMU_AMEVTYPER0_EL0(3), 3607 AMU_AMEVTYPER0_EL0(4), 3608 AMU_AMEVTYPER0_EL0(5), 3609 AMU_AMEVTYPER0_EL0(6), 3610 AMU_AMEVTYPER0_EL0(7), 3611 AMU_AMEVTYPER0_EL0(8), 3612 AMU_AMEVTYPER0_EL0(9), 3613 AMU_AMEVTYPER0_EL0(10), 3614 AMU_AMEVTYPER0_EL0(11), 3615 AMU_AMEVTYPER0_EL0(12), 3616 AMU_AMEVTYPER0_EL0(13), 3617 AMU_AMEVTYPER0_EL0(14), 3618 AMU_AMEVTYPER0_EL0(15), 3619 AMU_AMEVCNTR1_EL0(0), 3620 AMU_AMEVCNTR1_EL0(1), 3621 AMU_AMEVCNTR1_EL0(2), 3622 AMU_AMEVCNTR1_EL0(3), 3623 AMU_AMEVCNTR1_EL0(4), 3624 AMU_AMEVCNTR1_EL0(5), 3625 AMU_AMEVCNTR1_EL0(6), 3626 AMU_AMEVCNTR1_EL0(7), 3627 AMU_AMEVCNTR1_EL0(8), 3628 AMU_AMEVCNTR1_EL0(9), 3629 AMU_AMEVCNTR1_EL0(10), 3630 AMU_AMEVCNTR1_EL0(11), 3631 AMU_AMEVCNTR1_EL0(12), 3632 AMU_AMEVCNTR1_EL0(13), 3633 AMU_AMEVCNTR1_EL0(14), 3634 AMU_AMEVCNTR1_EL0(15), 3635 AMU_AMEVTYPER1_EL0(0), 3636 AMU_AMEVTYPER1_EL0(1), 3637 AMU_AMEVTYPER1_EL0(2), 3638 AMU_AMEVTYPER1_EL0(3), 3639 AMU_AMEVTYPER1_EL0(4), 3640 AMU_AMEVTYPER1_EL0(5), 3641 AMU_AMEVTYPER1_EL0(6), 3642 AMU_AMEVTYPER1_EL0(7), 3643 AMU_AMEVTYPER1_EL0(8), 3644 AMU_AMEVTYPER1_EL0(9), 3645 AMU_AMEVTYPER1_EL0(10), 3646 AMU_AMEVTYPER1_EL0(11), 3647 AMU_AMEVTYPER1_EL0(12), 3648 AMU_AMEVTYPER1_EL0(13), 3649 AMU_AMEVTYPER1_EL0(14), 3650 AMU_AMEVTYPER1_EL0(15), 3651 3652 { SYS_DESC(SYS_CNTPCT_EL0), .access = access_arch_timer, 3653 .get_user = arch_timer_get_user, .set_user = arch_timer_set_user }, 3654 { SYS_DESC(SYS_CNTVCT_EL0), .access = access_arch_timer, 3655 .get_user = arch_timer_get_user, .set_user = arch_timer_set_user }, 3656 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 3657 { SYS_DESC(SYS_CNTVCTSS_EL0), access_arch_timer }, 3658 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 3659 TIMER_REG(CNTP_CTL_EL0, NULL), 3660 TIMER_REG(CNTP_CVAL_EL0, NULL), 3661 3662 { SYS_DESC(SYS_CNTV_TVAL_EL0), access_arch_timer }, 3663 TIMER_REG(CNTV_CTL_EL0, NULL), 3664 TIMER_REG(CNTV_CVAL_EL0, NULL), 3665 3666 /* PMEVCNTRn_EL0 */ 3667 PMU_PMEVCNTR_EL0(0), 3668 PMU_PMEVCNTR_EL0(1), 3669 PMU_PMEVCNTR_EL0(2), 3670 PMU_PMEVCNTR_EL0(3), 3671 PMU_PMEVCNTR_EL0(4), 3672 PMU_PMEVCNTR_EL0(5), 3673 PMU_PMEVCNTR_EL0(6), 3674 PMU_PMEVCNTR_EL0(7), 3675 PMU_PMEVCNTR_EL0(8), 3676 PMU_PMEVCNTR_EL0(9), 3677 PMU_PMEVCNTR_EL0(10), 3678 PMU_PMEVCNTR_EL0(11), 3679 PMU_PMEVCNTR_EL0(12), 3680 PMU_PMEVCNTR_EL0(13), 3681 PMU_PMEVCNTR_EL0(14), 3682 PMU_PMEVCNTR_EL0(15), 3683 PMU_PMEVCNTR_EL0(16), 3684 PMU_PMEVCNTR_EL0(17), 3685 PMU_PMEVCNTR_EL0(18), 3686 PMU_PMEVCNTR_EL0(19), 3687 PMU_PMEVCNTR_EL0(20), 3688 PMU_PMEVCNTR_EL0(21), 3689 PMU_PMEVCNTR_EL0(22), 3690 PMU_PMEVCNTR_EL0(23), 3691 PMU_PMEVCNTR_EL0(24), 3692 PMU_PMEVCNTR_EL0(25), 3693 PMU_PMEVCNTR_EL0(26), 3694 PMU_PMEVCNTR_EL0(27), 3695 PMU_PMEVCNTR_EL0(28), 3696 PMU_PMEVCNTR_EL0(29), 3697 PMU_PMEVCNTR_EL0(30), 3698 /* PMEVTYPERn_EL0 */ 3699 PMU_PMEVTYPER_EL0(0), 3700 PMU_PMEVTYPER_EL0(1), 3701 PMU_PMEVTYPER_EL0(2), 3702 PMU_PMEVTYPER_EL0(3), 3703 PMU_PMEVTYPER_EL0(4), 3704 PMU_PMEVTYPER_EL0(5), 3705 PMU_PMEVTYPER_EL0(6), 3706 PMU_PMEVTYPER_EL0(7), 3707 PMU_PMEVTYPER_EL0(8), 3708 PMU_PMEVTYPER_EL0(9), 3709 PMU_PMEVTYPER_EL0(10), 3710 PMU_PMEVTYPER_EL0(11), 3711 PMU_PMEVTYPER_EL0(12), 3712 PMU_PMEVTYPER_EL0(13), 3713 PMU_PMEVTYPER_EL0(14), 3714 PMU_PMEVTYPER_EL0(15), 3715 PMU_PMEVTYPER_EL0(16), 3716 PMU_PMEVTYPER_EL0(17), 3717 PMU_PMEVTYPER_EL0(18), 3718 PMU_PMEVTYPER_EL0(19), 3719 PMU_PMEVTYPER_EL0(20), 3720 PMU_PMEVTYPER_EL0(21), 3721 PMU_PMEVTYPER_EL0(22), 3722 PMU_PMEVTYPER_EL0(23), 3723 PMU_PMEVTYPER_EL0(24), 3724 PMU_PMEVTYPER_EL0(25), 3725 PMU_PMEVTYPER_EL0(26), 3726 PMU_PMEVTYPER_EL0(27), 3727 PMU_PMEVTYPER_EL0(28), 3728 PMU_PMEVTYPER_EL0(29), 3729 PMU_PMEVTYPER_EL0(30), 3730 /* 3731 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 3732 * in 32bit mode. Here we choose to reset it as zero for consistency. 3733 */ 3734 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 3735 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 3736 3737 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 3738 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 3739 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 3740 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 3741 EL2_REG_FILTERED(SCTLR2_EL2, access_vm_reg, reset_val, 0, 3742 sctlr2_el2_visibility), 3743 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 3744 EL2_REG(MDCR_EL2, access_mdcr, reset_mdcr, 0), 3745 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 3746 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 3747 EL2_REG_VNCR_FILT(HFGRTR_EL2, fgt_visibility), 3748 EL2_REG_VNCR_FILT(HFGWTR_EL2, fgt_visibility), 3749 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 3750 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 3751 3752 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0, 3753 sve_el2_visibility), 3754 3755 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 3756 3757 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 3758 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 3759 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 3760 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1, 3761 tcr2_el2_visibility), 3762 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 3763 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 3764 EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0, 3765 vncr_el2_visibility), 3766 3767 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 3768 EL2_REG_VNCR_FILT(HDFGRTR2_EL2, fgt2_visibility), 3769 EL2_REG_VNCR_FILT(HDFGWTR2_EL2, fgt2_visibility), 3770 EL2_REG_VNCR_FILT(HFGRTR2_EL2, fgt2_visibility), 3771 EL2_REG_VNCR_FILT(HFGWTR2_EL2, fgt2_visibility), 3772 EL2_REG_VNCR_FILT(HDFGRTR_EL2, fgt_visibility), 3773 EL2_REG_VNCR_FILT(HDFGWTR_EL2, fgt_visibility), 3774 EL2_REG_VNCR_FILT(HAFGRTR_EL2, fgt_visibility), 3775 EL2_REG_VNCR_FILT(HFGITR2_EL2, fgt2_visibility), 3776 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 3777 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 3778 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 3779 3780 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 3781 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 3782 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 3783 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 3784 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 3785 3786 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 3787 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 3788 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 3789 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 3790 EL2_REG_VNCR(VSESR_EL2, reset_unknown, 0), 3791 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 3792 3793 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 3794 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 3795 3796 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 3797 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0, 3798 s1pie_el2_visibility), 3799 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0, 3800 s1pie_el2_visibility), 3801 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0, 3802 s1poe_el2_visibility), 3803 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 3804 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access }, 3805 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access }, 3806 { SYS_DESC(SYS_MPAM2_EL2), undef_access }, 3807 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access }, 3808 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access }, 3809 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access }, 3810 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access }, 3811 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access }, 3812 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access }, 3813 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access }, 3814 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access }, 3815 3816 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 3817 { SYS_DESC(SYS_RVBAR_EL2), undef_access }, 3818 { SYS_DESC(SYS_RMR_EL2), undef_access }, 3819 EL2_REG_VNCR(VDISR_EL2, reset_unknown, 0), 3820 3821 EL2_REG_VNCR_GICv3(ICH_AP0R0_EL2), 3822 EL2_REG_VNCR_GICv3(ICH_AP0R1_EL2), 3823 EL2_REG_VNCR_GICv3(ICH_AP0R2_EL2), 3824 EL2_REG_VNCR_GICv3(ICH_AP0R3_EL2), 3825 EL2_REG_VNCR_GICv3(ICH_AP1R0_EL2), 3826 EL2_REG_VNCR_GICv3(ICH_AP1R1_EL2), 3827 EL2_REG_VNCR_GICv3(ICH_AP1R2_EL2), 3828 EL2_REG_VNCR_GICv3(ICH_AP1R3_EL2), 3829 3830 { SYS_DESC(SYS_ICC_SRE_EL2), access_gic_sre }, 3831 3832 EL2_REG_VNCR_GICv3(ICH_HCR_EL2), 3833 { SYS_DESC(SYS_ICH_VTR_EL2), access_gic_vtr }, 3834 { SYS_DESC(SYS_ICH_MISR_EL2), access_gic_misr }, 3835 { SYS_DESC(SYS_ICH_EISR_EL2), access_gic_eisr }, 3836 { SYS_DESC(SYS_ICH_ELRSR_EL2), access_gic_elrsr }, 3837 EL2_REG_VNCR_GICv3(ICH_VMCR_EL2), 3838 3839 EL2_REG_VNCR_GICv3(ICH_LR0_EL2), 3840 EL2_REG_VNCR_GICv3(ICH_LR1_EL2), 3841 EL2_REG_VNCR_GICv3(ICH_LR2_EL2), 3842 EL2_REG_VNCR_GICv3(ICH_LR3_EL2), 3843 EL2_REG_VNCR_GICv3(ICH_LR4_EL2), 3844 EL2_REG_VNCR_GICv3(ICH_LR5_EL2), 3845 EL2_REG_VNCR_GICv3(ICH_LR6_EL2), 3846 EL2_REG_VNCR_GICv3(ICH_LR7_EL2), 3847 EL2_REG_VNCR_GICv3(ICH_LR8_EL2), 3848 EL2_REG_VNCR_GICv3(ICH_LR9_EL2), 3849 EL2_REG_VNCR_GICv3(ICH_LR10_EL2), 3850 EL2_REG_VNCR_GICv3(ICH_LR11_EL2), 3851 EL2_REG_VNCR_GICv3(ICH_LR12_EL2), 3852 EL2_REG_VNCR_GICv3(ICH_LR13_EL2), 3853 EL2_REG_VNCR_GICv3(ICH_LR14_EL2), 3854 EL2_REG_VNCR_GICv3(ICH_LR15_EL2), 3855 3856 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 3857 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 3858 3859 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 3860 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 3861 { SYS_DESC(SYS_CNTHP_TVAL_EL2), access_arch_timer }, 3862 TIMER_REG(CNTHP_CTL_EL2, el2_visibility), 3863 TIMER_REG(CNTHP_CVAL_EL2, el2_visibility), 3864 3865 { SYS_DESC(SYS_CNTHV_TVAL_EL2), access_arch_timer, .visibility = cnthv_visibility }, 3866 TIMER_REG(CNTHV_CTL_EL2, cnthv_visibility), 3867 TIMER_REG(CNTHV_CVAL_EL2, cnthv_visibility), 3868 3869 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 3870 3871 { SYS_DESC(SYS_CNTP_TVAL_EL02), access_arch_timer }, 3872 { SYS_DESC(SYS_CNTP_CTL_EL02), access_arch_timer }, 3873 { SYS_DESC(SYS_CNTP_CVAL_EL02), access_arch_timer }, 3874 3875 { SYS_DESC(SYS_CNTV_TVAL_EL02), access_arch_timer }, 3876 { SYS_DESC(SYS_CNTV_CTL_EL02), access_arch_timer }, 3877 { SYS_DESC(SYS_CNTV_CVAL_EL02), access_arch_timer }, 3878 3879 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 3880 }; 3881 3882 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3883 const struct sys_reg_desc *r) 3884 { 3885 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3886 3887 if (__kvm_at_s1e01(vcpu, op, p->regval)) 3888 return false; 3889 3890 return true; 3891 } 3892 3893 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3894 const struct sys_reg_desc *r) 3895 { 3896 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3897 3898 /* There is no FGT associated with AT S1E2A :-( */ 3899 if (op == OP_AT_S1E2A && 3900 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 3901 kvm_inject_undefined(vcpu); 3902 return false; 3903 } 3904 3905 if (__kvm_at_s1e2(vcpu, op, p->regval)) 3906 return false; 3907 3908 return true; 3909 } 3910 3911 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3912 const struct sys_reg_desc *r) 3913 { 3914 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3915 3916 if (__kvm_at_s12(vcpu, op, p->regval)) 3917 return false; 3918 3919 return true; 3920 } 3921 3922 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 3923 { 3924 struct kvm *kvm = vpcu->kvm; 3925 u8 CRm = sys_reg_CRm(instr); 3926 3927 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3928 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3929 return false; 3930 3931 if (CRm == TLBI_CRm_nROS && 3932 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3933 return false; 3934 3935 return true; 3936 } 3937 3938 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3939 const struct sys_reg_desc *r) 3940 { 3941 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3942 3943 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3944 return undef_access(vcpu, p, r); 3945 3946 write_lock(&vcpu->kvm->mmu_lock); 3947 3948 /* 3949 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 3950 * corresponding VMIDs. 3951 */ 3952 kvm_nested_s2_unmap(vcpu->kvm, true); 3953 3954 write_unlock(&vcpu->kvm->mmu_lock); 3955 3956 return true; 3957 } 3958 3959 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 3960 { 3961 struct kvm *kvm = vpcu->kvm; 3962 u8 CRm = sys_reg_CRm(instr); 3963 u8 Op2 = sys_reg_Op2(instr); 3964 3965 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3966 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3967 return false; 3968 3969 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 3970 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3971 return false; 3972 3973 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 3974 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3975 return false; 3976 3977 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 3978 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3979 return false; 3980 3981 return true; 3982 } 3983 3984 /* Only defined here as this is an internal "abstraction" */ 3985 union tlbi_info { 3986 struct { 3987 u64 start; 3988 u64 size; 3989 } range; 3990 3991 struct { 3992 u64 addr; 3993 } ipa; 3994 3995 struct { 3996 u64 addr; 3997 u32 encoding; 3998 } va; 3999 }; 4000 4001 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 4002 const union tlbi_info *info) 4003 { 4004 /* 4005 * The unmap operation is allowed to drop the MMU lock and block, which 4006 * means that @mmu could be used for a different context than the one 4007 * currently being invalidated. 4008 * 4009 * This behavior is still safe, as: 4010 * 4011 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 4012 * the entire MMU before reusing it, which still honors the intent 4013 * of a TLBI. 4014 * 4015 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 4016 * and ERET to the guest), other vCPUs are allowed to use stale 4017 * translations. 4018 * 4019 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 4020 * at worst may cause more aborts for shadow stage-2 fills. 4021 * 4022 * Dropping the MMU lock also implies that shadow stage-2 fills could 4023 * happen behind the back of the TLBI. This is still safe, though, as 4024 * the L1 needs to put its stage-2 in a consistent state before doing 4025 * the TLBI. 4026 */ 4027 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 4028 } 4029 4030 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4031 const struct sys_reg_desc *r) 4032 { 4033 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4034 u64 limit, vttbr; 4035 4036 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 4037 return undef_access(vcpu, p, r); 4038 4039 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 4040 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 4041 4042 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 4043 &(union tlbi_info) { 4044 .range = { 4045 .start = 0, 4046 .size = limit, 4047 }, 4048 }, 4049 s2_mmu_unmap_range); 4050 4051 return true; 4052 } 4053 4054 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4055 const struct sys_reg_desc *r) 4056 { 4057 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4058 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 4059 u64 base, range; 4060 4061 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 4062 return undef_access(vcpu, p, r); 4063 4064 /* 4065 * Because the shadow S2 structure doesn't necessarily reflect that 4066 * of the guest's S2 (different base granule size, for example), we 4067 * decide to ignore TTL and only use the described range. 4068 */ 4069 base = decode_range_tlbi(p->regval, &range, NULL); 4070 4071 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 4072 &(union tlbi_info) { 4073 .range = { 4074 .start = base, 4075 .size = range, 4076 }, 4077 }, 4078 s2_mmu_unmap_range); 4079 4080 return true; 4081 } 4082 4083 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 4084 const union tlbi_info *info) 4085 { 4086 unsigned long max_size; 4087 u64 base_addr; 4088 4089 /* 4090 * We drop a number of things from the supplied value: 4091 * 4092 * - NS bit: we're non-secure only. 4093 * 4094 * - IPA[51:48]: We don't support 52bit IPA just yet... 4095 * 4096 * And of course, adjust the IPA to be on an actual address. 4097 */ 4098 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 4099 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 4100 base_addr &= ~(max_size - 1); 4101 4102 /* 4103 * See comment in s2_mmu_unmap_range() for why this is allowed to 4104 * reschedule. 4105 */ 4106 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 4107 } 4108 4109 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4110 const struct sys_reg_desc *r) 4111 { 4112 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4113 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 4114 4115 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 4116 return undef_access(vcpu, p, r); 4117 4118 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 4119 &(union tlbi_info) { 4120 .ipa = { 4121 .addr = p->regval, 4122 }, 4123 }, 4124 s2_mmu_unmap_ipa); 4125 4126 return true; 4127 } 4128 4129 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 4130 const union tlbi_info *info) 4131 { 4132 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 4133 } 4134 4135 static bool handle_tlbi_el2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4136 const struct sys_reg_desc *r) 4137 { 4138 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4139 4140 if (!kvm_supported_tlbi_s1e2_op(vcpu, sys_encoding)) 4141 return undef_access(vcpu, p, r); 4142 4143 kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval); 4144 return true; 4145 } 4146 4147 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 4148 const struct sys_reg_desc *r) 4149 { 4150 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 4151 4152 /* 4153 * If we're here, this is because we've trapped on a EL1 TLBI 4154 * instruction that affects the EL1 translation regime while 4155 * we're running in a context that doesn't allow us to let the 4156 * HW do its thing (aka vEL2): 4157 * 4158 * - HCR_EL2.E2H == 0 : a non-VHE guest 4159 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 4160 * 4161 * Another possibility is that we are invalidating the EL2 context 4162 * using EL1 instructions, but that we landed here because we need 4163 * additional invalidation for structures that are not held in the 4164 * CPU TLBs (such as the VNCR pseudo-TLB and its EL2 mapping). In 4165 * that case, we are guaranteed that HCR_EL2.{E2H,TGE} == { 1, 1 } 4166 * as we don't allow an NV-capable L1 in a nVHE configuration. 4167 * 4168 * We don't expect these helpers to ever be called when running 4169 * in a vEL1 context. 4170 */ 4171 4172 WARN_ON(!vcpu_is_el2(vcpu)); 4173 4174 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 4175 return undef_access(vcpu, p, r); 4176 4177 if (vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)) { 4178 kvm_handle_s1e2_tlbi(vcpu, sys_encoding, p->regval); 4179 return true; 4180 } 4181 4182 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, 4183 get_vmid(__vcpu_sys_reg(vcpu, VTTBR_EL2)), 4184 &(union tlbi_info) { 4185 .va = { 4186 .addr = p->regval, 4187 .encoding = sys_encoding, 4188 }, 4189 }, 4190 s2_mmu_tlbi_s1e1); 4191 4192 return true; 4193 } 4194 4195 #define SYS_INSN(insn, access_fn) \ 4196 { \ 4197 SYS_DESC(OP_##insn), \ 4198 .access = (access_fn), \ 4199 } 4200 4201 static struct sys_reg_desc sys_insn_descs[] = { 4202 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 4203 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 4204 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 4205 4206 SYS_INSN(AT_S1E1R, handle_at_s1e01), 4207 SYS_INSN(AT_S1E1W, handle_at_s1e01), 4208 SYS_INSN(AT_S1E0R, handle_at_s1e01), 4209 SYS_INSN(AT_S1E0W, handle_at_s1e01), 4210 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 4211 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 4212 SYS_INSN(AT_S1E1A, handle_at_s1e01), 4213 4214 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 4215 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 4216 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 4217 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 4218 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 4219 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 4220 4221 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 4222 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 4223 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 4224 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 4225 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 4226 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 4227 4228 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 4229 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 4230 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 4231 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 4232 4233 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 4234 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 4235 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 4236 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 4237 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 4238 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 4239 4240 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 4241 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 4242 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 4243 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 4244 4245 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 4246 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 4247 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 4248 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 4249 4250 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 4251 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 4252 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 4253 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 4254 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 4255 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 4256 4257 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 4258 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 4259 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 4260 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 4261 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 4262 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 4263 4264 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 4265 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 4266 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 4267 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 4268 4269 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 4270 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 4271 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 4272 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 4273 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 4274 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 4275 4276 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 4277 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 4278 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 4279 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 4280 4281 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 4282 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 4283 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 4284 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 4285 4286 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 4287 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 4288 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 4289 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 4290 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 4291 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 4292 4293 SYS_INSN(AT_S1E2R, handle_at_s1e2), 4294 SYS_INSN(AT_S1E2W, handle_at_s1e2), 4295 SYS_INSN(AT_S12E1R, handle_at_s12), 4296 SYS_INSN(AT_S12E1W, handle_at_s12), 4297 SYS_INSN(AT_S12E0R, handle_at_s12), 4298 SYS_INSN(AT_S12E0W, handle_at_s12), 4299 SYS_INSN(AT_S1E2A, handle_at_s1e2), 4300 4301 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 4302 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 4303 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 4304 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 4305 4306 SYS_INSN(TLBI_ALLE2OS, handle_tlbi_el2), 4307 SYS_INSN(TLBI_VAE2OS, handle_tlbi_el2), 4308 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 4309 SYS_INSN(TLBI_VALE2OS, handle_tlbi_el2), 4310 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 4311 4312 SYS_INSN(TLBI_RVAE2IS, handle_tlbi_el2), 4313 SYS_INSN(TLBI_RVALE2IS, handle_tlbi_el2), 4314 SYS_INSN(TLBI_ALLE2IS, handle_tlbi_el2), 4315 SYS_INSN(TLBI_VAE2IS, handle_tlbi_el2), 4316 4317 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 4318 4319 SYS_INSN(TLBI_VALE2IS, handle_tlbi_el2), 4320 4321 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 4322 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 4323 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 4324 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 4325 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 4326 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 4327 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 4328 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 4329 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 4330 SYS_INSN(TLBI_RVAE2OS, handle_tlbi_el2), 4331 SYS_INSN(TLBI_RVALE2OS, handle_tlbi_el2), 4332 SYS_INSN(TLBI_RVAE2, handle_tlbi_el2), 4333 SYS_INSN(TLBI_RVALE2, handle_tlbi_el2), 4334 SYS_INSN(TLBI_ALLE2, handle_tlbi_el2), 4335 SYS_INSN(TLBI_VAE2, handle_tlbi_el2), 4336 4337 SYS_INSN(TLBI_ALLE1, handle_alle1is), 4338 4339 SYS_INSN(TLBI_VALE2, handle_tlbi_el2), 4340 4341 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 4342 4343 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 4344 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 4345 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 4346 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 4347 4348 SYS_INSN(TLBI_ALLE2OSNXS, handle_tlbi_el2), 4349 SYS_INSN(TLBI_VAE2OSNXS, handle_tlbi_el2), 4350 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 4351 SYS_INSN(TLBI_VALE2OSNXS, handle_tlbi_el2), 4352 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 4353 4354 SYS_INSN(TLBI_RVAE2ISNXS, handle_tlbi_el2), 4355 SYS_INSN(TLBI_RVALE2ISNXS, handle_tlbi_el2), 4356 SYS_INSN(TLBI_ALLE2ISNXS, handle_tlbi_el2), 4357 SYS_INSN(TLBI_VAE2ISNXS, handle_tlbi_el2), 4358 4359 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 4360 SYS_INSN(TLBI_VALE2ISNXS, handle_tlbi_el2), 4361 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 4362 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 4363 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 4364 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 4365 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 4366 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 4367 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 4368 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 4369 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 4370 SYS_INSN(TLBI_RVAE2OSNXS, handle_tlbi_el2), 4371 SYS_INSN(TLBI_RVALE2OSNXS, handle_tlbi_el2), 4372 SYS_INSN(TLBI_RVAE2NXS, handle_tlbi_el2), 4373 SYS_INSN(TLBI_RVALE2NXS, handle_tlbi_el2), 4374 SYS_INSN(TLBI_ALLE2NXS, handle_tlbi_el2), 4375 SYS_INSN(TLBI_VAE2NXS, handle_tlbi_el2), 4376 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 4377 SYS_INSN(TLBI_VALE2NXS, handle_tlbi_el2), 4378 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 4379 }; 4380 4381 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 4382 struct sys_reg_params *p, 4383 const struct sys_reg_desc *r) 4384 { 4385 if (p->is_write) { 4386 return ignore_write(vcpu, p); 4387 } else { 4388 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 4389 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 4390 4391 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 4392 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 4393 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 4394 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 4395 (1 << 15) | (el3 << 14) | (el3 << 12)); 4396 return true; 4397 } 4398 } 4399 4400 /* 4401 * AArch32 debug register mappings 4402 * 4403 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 4404 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 4405 * 4406 * None of the other registers share their location, so treat them as 4407 * if they were 64bit. 4408 */ 4409 #define DBG_BCR_BVR_WCR_WVR(n) \ 4410 /* DBGBVRn */ \ 4411 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \ 4412 trap_dbg_wb_reg, NULL, n }, \ 4413 /* DBGBCRn */ \ 4414 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \ 4415 /* DBGWVRn */ \ 4416 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \ 4417 /* DBGWCRn */ \ 4418 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n } 4419 4420 #define DBGBXVR(n) \ 4421 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \ 4422 trap_dbg_wb_reg, NULL, n } 4423 4424 /* 4425 * Trapped cp14 registers. We generally ignore most of the external 4426 * debug, on the principle that they don't really make sense to a 4427 * guest. Revisit this one day, would this principle change. 4428 */ 4429 static const struct sys_reg_desc cp14_regs[] = { 4430 /* DBGDIDR */ 4431 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 4432 /* DBGDTRRXext */ 4433 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 4434 4435 DBG_BCR_BVR_WCR_WVR(0), 4436 /* DBGDSCRint */ 4437 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 4438 DBG_BCR_BVR_WCR_WVR(1), 4439 /* DBGDCCINT */ 4440 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 4441 /* DBGDSCRext */ 4442 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 4443 DBG_BCR_BVR_WCR_WVR(2), 4444 /* DBGDTR[RT]Xint */ 4445 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 4446 /* DBGDTR[RT]Xext */ 4447 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 4448 DBG_BCR_BVR_WCR_WVR(3), 4449 DBG_BCR_BVR_WCR_WVR(4), 4450 DBG_BCR_BVR_WCR_WVR(5), 4451 /* DBGWFAR */ 4452 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 4453 /* DBGOSECCR */ 4454 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 4455 DBG_BCR_BVR_WCR_WVR(6), 4456 /* DBGVCR */ 4457 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 4458 DBG_BCR_BVR_WCR_WVR(7), 4459 DBG_BCR_BVR_WCR_WVR(8), 4460 DBG_BCR_BVR_WCR_WVR(9), 4461 DBG_BCR_BVR_WCR_WVR(10), 4462 DBG_BCR_BVR_WCR_WVR(11), 4463 DBG_BCR_BVR_WCR_WVR(12), 4464 DBG_BCR_BVR_WCR_WVR(13), 4465 DBG_BCR_BVR_WCR_WVR(14), 4466 DBG_BCR_BVR_WCR_WVR(15), 4467 4468 /* DBGDRAR (32bit) */ 4469 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 4470 4471 DBGBXVR(0), 4472 /* DBGOSLAR */ 4473 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 4474 DBGBXVR(1), 4475 /* DBGOSLSR */ 4476 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 4477 DBGBXVR(2), 4478 DBGBXVR(3), 4479 /* DBGOSDLR */ 4480 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 4481 DBGBXVR(4), 4482 /* DBGPRCR */ 4483 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 4484 DBGBXVR(5), 4485 DBGBXVR(6), 4486 DBGBXVR(7), 4487 DBGBXVR(8), 4488 DBGBXVR(9), 4489 DBGBXVR(10), 4490 DBGBXVR(11), 4491 DBGBXVR(12), 4492 DBGBXVR(13), 4493 DBGBXVR(14), 4494 DBGBXVR(15), 4495 4496 /* DBGDSAR (32bit) */ 4497 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 4498 4499 /* DBGDEVID2 */ 4500 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 4501 /* DBGDEVID1 */ 4502 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 4503 /* DBGDEVID */ 4504 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 4505 /* DBGCLAIMSET */ 4506 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 4507 /* DBGCLAIMCLR */ 4508 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 4509 /* DBGAUTHSTATUS */ 4510 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 4511 }; 4512 4513 /* Trapped cp14 64bit registers */ 4514 static const struct sys_reg_desc cp14_64_regs[] = { 4515 /* DBGDRAR (64bit) */ 4516 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 4517 4518 /* DBGDSAR (64bit) */ 4519 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 4520 }; 4521 4522 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 4523 AA32(_map), \ 4524 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 4525 .visibility = pmu_visibility 4526 4527 /* Macro to expand the PMEVCNTRn register */ 4528 #define PMU_PMEVCNTR(n) \ 4529 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 4530 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 4531 .access = access_pmu_evcntr } 4532 4533 /* Macro to expand the PMEVTYPERn register */ 4534 #define PMU_PMEVTYPER(n) \ 4535 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 4536 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 4537 .access = access_pmu_evtyper } 4538 /* 4539 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 4540 * depending on the way they are accessed (as a 32bit or a 64bit 4541 * register). 4542 */ 4543 static const struct sys_reg_desc cp15_regs[] = { 4544 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 4545 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 4546 /* ACTLR */ 4547 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 4548 /* ACTLR2 */ 4549 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 4550 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 4551 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 4552 /* TTBCR */ 4553 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 4554 /* TTBCR2 */ 4555 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 4556 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 4557 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 4558 /* DFSR */ 4559 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 4560 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 4561 /* ADFSR */ 4562 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 4563 /* AIFSR */ 4564 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 4565 /* DFAR */ 4566 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 4567 /* IFAR */ 4568 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 4569 4570 /* 4571 * DC{C,I,CI}SW operations: 4572 */ 4573 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 4574 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 4575 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 4576 4577 /* PMU */ 4578 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 4579 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 4580 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 4581 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 4582 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 4583 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 4584 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 4585 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 4586 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 4587 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 4588 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 4589 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 4590 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 4591 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 4592 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 4593 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 4594 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 4595 /* PMMIR */ 4596 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 4597 4598 /* PRRR/MAIR0 */ 4599 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 4600 /* NMRR/MAIR1 */ 4601 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 4602 /* AMAIR0 */ 4603 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 4604 /* AMAIR1 */ 4605 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 4606 4607 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 4608 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 4609 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 4610 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 4611 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 4612 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 4613 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 4614 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 4615 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 4616 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 4617 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 4618 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 4619 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), access_gic_dir }, 4620 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 4621 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 4622 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 4623 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 4624 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 4625 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 4626 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 4627 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 4628 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 4629 4630 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 4631 4632 /* Arch Tmers */ 4633 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 4634 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 4635 4636 /* PMEVCNTRn */ 4637 PMU_PMEVCNTR(0), 4638 PMU_PMEVCNTR(1), 4639 PMU_PMEVCNTR(2), 4640 PMU_PMEVCNTR(3), 4641 PMU_PMEVCNTR(4), 4642 PMU_PMEVCNTR(5), 4643 PMU_PMEVCNTR(6), 4644 PMU_PMEVCNTR(7), 4645 PMU_PMEVCNTR(8), 4646 PMU_PMEVCNTR(9), 4647 PMU_PMEVCNTR(10), 4648 PMU_PMEVCNTR(11), 4649 PMU_PMEVCNTR(12), 4650 PMU_PMEVCNTR(13), 4651 PMU_PMEVCNTR(14), 4652 PMU_PMEVCNTR(15), 4653 PMU_PMEVCNTR(16), 4654 PMU_PMEVCNTR(17), 4655 PMU_PMEVCNTR(18), 4656 PMU_PMEVCNTR(19), 4657 PMU_PMEVCNTR(20), 4658 PMU_PMEVCNTR(21), 4659 PMU_PMEVCNTR(22), 4660 PMU_PMEVCNTR(23), 4661 PMU_PMEVCNTR(24), 4662 PMU_PMEVCNTR(25), 4663 PMU_PMEVCNTR(26), 4664 PMU_PMEVCNTR(27), 4665 PMU_PMEVCNTR(28), 4666 PMU_PMEVCNTR(29), 4667 PMU_PMEVCNTR(30), 4668 /* PMEVTYPERn */ 4669 PMU_PMEVTYPER(0), 4670 PMU_PMEVTYPER(1), 4671 PMU_PMEVTYPER(2), 4672 PMU_PMEVTYPER(3), 4673 PMU_PMEVTYPER(4), 4674 PMU_PMEVTYPER(5), 4675 PMU_PMEVTYPER(6), 4676 PMU_PMEVTYPER(7), 4677 PMU_PMEVTYPER(8), 4678 PMU_PMEVTYPER(9), 4679 PMU_PMEVTYPER(10), 4680 PMU_PMEVTYPER(11), 4681 PMU_PMEVTYPER(12), 4682 PMU_PMEVTYPER(13), 4683 PMU_PMEVTYPER(14), 4684 PMU_PMEVTYPER(15), 4685 PMU_PMEVTYPER(16), 4686 PMU_PMEVTYPER(17), 4687 PMU_PMEVTYPER(18), 4688 PMU_PMEVTYPER(19), 4689 PMU_PMEVTYPER(20), 4690 PMU_PMEVTYPER(21), 4691 PMU_PMEVTYPER(22), 4692 PMU_PMEVTYPER(23), 4693 PMU_PMEVTYPER(24), 4694 PMU_PMEVTYPER(25), 4695 PMU_PMEVTYPER(26), 4696 PMU_PMEVTYPER(27), 4697 PMU_PMEVTYPER(28), 4698 PMU_PMEVTYPER(29), 4699 PMU_PMEVTYPER(30), 4700 /* PMCCFILTR */ 4701 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 4702 4703 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 4704 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 4705 4706 /* CCSIDR2 */ 4707 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 4708 4709 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 4710 }; 4711 4712 static const struct sys_reg_desc cp15_64_regs[] = { 4713 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 4714 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 4715 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 4716 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 4717 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 4718 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 4719 { SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer }, 4720 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 4721 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 4722 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 4723 { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer }, 4724 }; 4725 4726 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 4727 bool reset_check) 4728 { 4729 unsigned int i; 4730 4731 for (i = 0; i < n; i++) { 4732 if (reset_check && table[i].reg && !table[i].reset) { 4733 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 4734 &table[i], i, table[i].name); 4735 return false; 4736 } 4737 4738 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 4739 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 4740 &table[i], i, table[i - 1].name, table[i].name); 4741 return false; 4742 } 4743 } 4744 4745 return true; 4746 } 4747 4748 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 4749 { 4750 kvm_inject_undefined(vcpu); 4751 return 1; 4752 } 4753 4754 static void perform_access(struct kvm_vcpu *vcpu, 4755 struct sys_reg_params *params, 4756 const struct sys_reg_desc *r) 4757 { 4758 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 4759 4760 /* Check for regs disabled by runtime config */ 4761 if (sysreg_hidden(vcpu, r)) { 4762 kvm_inject_undefined(vcpu); 4763 return; 4764 } 4765 4766 /* 4767 * Not having an accessor means that we have configured a trap 4768 * that we don't know how to handle. This certainly qualifies 4769 * as a gross bug that should be fixed right away. 4770 */ 4771 if (!r->access) { 4772 bad_trap(vcpu, params, r, "register access"); 4773 return; 4774 } 4775 4776 /* Skip instruction if instructed so */ 4777 if (likely(r->access(vcpu, params, r))) 4778 kvm_incr_pc(vcpu); 4779 } 4780 4781 /* 4782 * emulate_cp -- tries to match a sys_reg access in a handling table, and 4783 * call the corresponding trap handler. 4784 * 4785 * @params: pointer to the descriptor of the access 4786 * @table: array of trap descriptors 4787 * @num: size of the trap descriptor array 4788 * 4789 * Return true if the access has been handled, false if not. 4790 */ 4791 static bool emulate_cp(struct kvm_vcpu *vcpu, 4792 struct sys_reg_params *params, 4793 const struct sys_reg_desc *table, 4794 size_t num) 4795 { 4796 const struct sys_reg_desc *r; 4797 4798 if (!table) 4799 return false; /* Not handled */ 4800 4801 r = find_reg(params, table, num); 4802 4803 if (r) { 4804 perform_access(vcpu, params, r); 4805 return true; 4806 } 4807 4808 /* Not handled */ 4809 return false; 4810 } 4811 4812 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 4813 struct sys_reg_params *params) 4814 { 4815 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 4816 int cp = -1; 4817 4818 switch (esr_ec) { 4819 case ESR_ELx_EC_CP15_32: 4820 case ESR_ELx_EC_CP15_64: 4821 cp = 15; 4822 break; 4823 case ESR_ELx_EC_CP14_MR: 4824 case ESR_ELx_EC_CP14_64: 4825 cp = 14; 4826 break; 4827 default: 4828 WARN_ON(1); 4829 } 4830 4831 print_sys_reg_msg(params, 4832 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 4833 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4834 kvm_inject_undefined(vcpu); 4835 } 4836 4837 /** 4838 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 4839 * @vcpu: The VCPU pointer 4840 * @global: &struct sys_reg_desc 4841 * @nr_global: size of the @global array 4842 */ 4843 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 4844 const struct sys_reg_desc *global, 4845 size_t nr_global) 4846 { 4847 struct sys_reg_params params; 4848 u64 esr = kvm_vcpu_get_esr(vcpu); 4849 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4850 int Rt2 = (esr >> 10) & 0x1f; 4851 4852 params.CRm = (esr >> 1) & 0xf; 4853 params.is_write = ((esr & 1) == 0); 4854 4855 params.Op0 = 0; 4856 params.Op1 = (esr >> 16) & 0xf; 4857 params.Op2 = 0; 4858 params.CRn = 0; 4859 4860 /* 4861 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 4862 * backends between AArch32 and AArch64, we get away with it. 4863 */ 4864 if (params.is_write) { 4865 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 4866 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 4867 } 4868 4869 /* 4870 * If the table contains a handler, handle the 4871 * potential register operation in the case of a read and return 4872 * with success. 4873 */ 4874 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 4875 /* Split up the value between registers for the read side */ 4876 if (!params.is_write) { 4877 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 4878 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 4879 } 4880 4881 return 1; 4882 } 4883 4884 unhandled_cp_access(vcpu, ¶ms); 4885 return 1; 4886 } 4887 4888 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 4889 4890 /* 4891 * The CP10 ID registers are architecturally mapped to AArch64 feature 4892 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 4893 * from AArch32. 4894 */ 4895 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 4896 { 4897 u8 reg_id = (esr >> 10) & 0xf; 4898 bool valid; 4899 4900 params->is_write = ((esr & 1) == 0); 4901 params->Op0 = 3; 4902 params->Op1 = 0; 4903 params->CRn = 0; 4904 params->CRm = 3; 4905 4906 /* CP10 ID registers are read-only */ 4907 valid = !params->is_write; 4908 4909 switch (reg_id) { 4910 /* MVFR0 */ 4911 case 0b0111: 4912 params->Op2 = 0; 4913 break; 4914 /* MVFR1 */ 4915 case 0b0110: 4916 params->Op2 = 1; 4917 break; 4918 /* MVFR2 */ 4919 case 0b0101: 4920 params->Op2 = 2; 4921 break; 4922 default: 4923 valid = false; 4924 } 4925 4926 if (valid) 4927 return true; 4928 4929 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 4930 str_write_read(params->is_write), reg_id); 4931 return false; 4932 } 4933 4934 /** 4935 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 4936 * VFP Register' from AArch32. 4937 * @vcpu: The vCPU pointer 4938 * 4939 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 4940 * Work out the correct AArch64 system register encoding and reroute to the 4941 * AArch64 system register emulation. 4942 */ 4943 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 4944 { 4945 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4946 u64 esr = kvm_vcpu_get_esr(vcpu); 4947 struct sys_reg_params params; 4948 4949 /* UNDEF on any unhandled register access */ 4950 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 4951 kvm_inject_undefined(vcpu); 4952 return 1; 4953 } 4954 4955 if (emulate_sys_reg(vcpu, ¶ms)) 4956 vcpu_set_reg(vcpu, Rt, params.regval); 4957 4958 return 1; 4959 } 4960 4961 /** 4962 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 4963 * CRn=0, which corresponds to the AArch32 feature 4964 * registers. 4965 * @vcpu: the vCPU pointer 4966 * @params: the system register access parameters. 4967 * 4968 * Our cp15 system register tables do not enumerate the AArch32 feature 4969 * registers. Conveniently, our AArch64 table does, and the AArch32 system 4970 * register encoding can be trivially remapped into the AArch64 for the feature 4971 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 4972 * 4973 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 4974 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 4975 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 4976 * treat undefined registers in this range as RAZ. 4977 */ 4978 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 4979 struct sys_reg_params *params) 4980 { 4981 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4982 4983 /* Treat impossible writes to RO registers as UNDEFINED */ 4984 if (params->is_write) { 4985 unhandled_cp_access(vcpu, params); 4986 return 1; 4987 } 4988 4989 params->Op0 = 3; 4990 4991 /* 4992 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 4993 * Avoid conflicting with future expansion of AArch64 feature registers 4994 * and simply treat them as RAZ here. 4995 */ 4996 if (params->CRm > 3) 4997 params->regval = 0; 4998 else if (!emulate_sys_reg(vcpu, params)) 4999 return 1; 5000 5001 vcpu_set_reg(vcpu, Rt, params->regval); 5002 return 1; 5003 } 5004 5005 /** 5006 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 5007 * @vcpu: The VCPU pointer 5008 * @params: &struct sys_reg_params 5009 * @global: &struct sys_reg_desc 5010 * @nr_global: size of the @global array 5011 */ 5012 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 5013 struct sys_reg_params *params, 5014 const struct sys_reg_desc *global, 5015 size_t nr_global) 5016 { 5017 int Rt = kvm_vcpu_sys_get_rt(vcpu); 5018 5019 params->regval = vcpu_get_reg(vcpu, Rt); 5020 5021 if (emulate_cp(vcpu, params, global, nr_global)) { 5022 if (!params->is_write) 5023 vcpu_set_reg(vcpu, Rt, params->regval); 5024 return 1; 5025 } 5026 5027 unhandled_cp_access(vcpu, params); 5028 return 1; 5029 } 5030 5031 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 5032 { 5033 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 5034 } 5035 5036 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 5037 { 5038 struct sys_reg_params params; 5039 5040 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 5041 5042 /* 5043 * Certain AArch32 ID registers are handled by rerouting to the AArch64 5044 * system register table. Registers in the ID range where CRm=0 are 5045 * excluded from this scheme as they do not trivially map into AArch64 5046 * system register encodings, except for AIDR/REVIDR. 5047 */ 5048 if (params.Op1 == 0 && params.CRn == 0 && 5049 (params.CRm || params.Op2 == 6 /* REVIDR */)) 5050 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 5051 if (params.Op1 == 1 && params.CRn == 0 && 5052 params.CRm == 0 && params.Op2 == 7 /* AIDR */) 5053 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 5054 5055 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 5056 } 5057 5058 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 5059 { 5060 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 5061 } 5062 5063 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 5064 { 5065 struct sys_reg_params params; 5066 5067 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 5068 5069 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 5070 } 5071 5072 /** 5073 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 5074 * @vcpu: The VCPU pointer 5075 * @params: Decoded system register parameters 5076 * 5077 * Return: true if the system register access was successful, false otherwise. 5078 */ 5079 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 5080 struct sys_reg_params *params) 5081 { 5082 const struct sys_reg_desc *r; 5083 5084 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 5085 if (likely(r)) { 5086 perform_access(vcpu, params, r); 5087 return true; 5088 } 5089 5090 print_sys_reg_msg(params, 5091 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 5092 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 5093 kvm_inject_undefined(vcpu); 5094 5095 return false; 5096 } 5097 5098 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, loff_t pos) 5099 { 5100 unsigned long i, idreg_idx = 0; 5101 5102 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5103 const struct sys_reg_desc *r = &sys_reg_descs[i]; 5104 5105 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 5106 continue; 5107 5108 if (idreg_idx++ == pos) 5109 return r; 5110 } 5111 5112 return NULL; 5113 } 5114 5115 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 5116 { 5117 struct kvm *kvm = s->private; 5118 5119 if (!test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 5120 return NULL; 5121 5122 return (void *)idregs_debug_find(kvm, *pos); 5123 } 5124 5125 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 5126 { 5127 struct kvm *kvm = s->private; 5128 5129 (*pos)++; 5130 5131 return (void *)idregs_debug_find(kvm, *pos); 5132 } 5133 5134 static void idregs_debug_stop(struct seq_file *s, void *v) 5135 { 5136 } 5137 5138 static int idregs_debug_show(struct seq_file *s, void *v) 5139 { 5140 const struct sys_reg_desc *desc = v; 5141 struct kvm *kvm = s->private; 5142 5143 if (!desc) 5144 return 0; 5145 5146 seq_printf(s, "%20s:\t%016llx\n", 5147 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 5148 5149 return 0; 5150 } 5151 5152 static const struct seq_operations idregs_debug_sops = { 5153 .start = idregs_debug_start, 5154 .next = idregs_debug_next, 5155 .stop = idregs_debug_stop, 5156 .show = idregs_debug_show, 5157 }; 5158 5159 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 5160 5161 static const struct sys_reg_desc *sr_resx_find(struct kvm *kvm, loff_t pos) 5162 { 5163 unsigned long i, sr_idx = 0; 5164 5165 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5166 const struct sys_reg_desc *r = &sys_reg_descs[i]; 5167 5168 if (r->reg < __SANITISED_REG_START__) 5169 continue; 5170 5171 if (sr_idx++ == pos) 5172 return r; 5173 } 5174 5175 return NULL; 5176 } 5177 5178 static void *sr_resx_start(struct seq_file *s, loff_t *pos) 5179 { 5180 struct kvm *kvm = s->private; 5181 5182 if (!kvm->arch.sysreg_masks) 5183 return NULL; 5184 5185 return (void *)sr_resx_find(kvm, *pos); 5186 } 5187 5188 static void *sr_resx_next(struct seq_file *s, void *v, loff_t *pos) 5189 { 5190 struct kvm *kvm = s->private; 5191 5192 (*pos)++; 5193 5194 return (void *)sr_resx_find(kvm, *pos); 5195 } 5196 5197 static void sr_resx_stop(struct seq_file *s, void *v) 5198 { 5199 } 5200 5201 static int sr_resx_show(struct seq_file *s, void *v) 5202 { 5203 const struct sys_reg_desc *desc = v; 5204 struct kvm *kvm = s->private; 5205 struct resx resx; 5206 5207 if (!desc) 5208 return 0; 5209 5210 resx = kvm_get_sysreg_resx(kvm, desc->reg); 5211 5212 seq_printf(s, "%20s:\tRES0:%016llx\tRES1:%016llx\n", 5213 desc->name, resx.res0, resx.res1); 5214 5215 return 0; 5216 } 5217 5218 static const struct seq_operations sr_resx_sops = { 5219 .start = sr_resx_start, 5220 .next = sr_resx_next, 5221 .stop = sr_resx_stop, 5222 .show = sr_resx_show, 5223 }; 5224 5225 DEFINE_SEQ_ATTRIBUTE(sr_resx); 5226 5227 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 5228 { 5229 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 5230 &idregs_debug_fops); 5231 debugfs_create_file("resx", 0444, kvm->debugfs_dentry, kvm, 5232 &sr_resx_fops); 5233 } 5234 5235 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 5236 { 5237 u32 id = reg_to_encoding(reg); 5238 struct kvm *kvm = vcpu->kvm; 5239 5240 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 5241 return; 5242 5243 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 5244 } 5245 5246 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 5247 const struct sys_reg_desc *reg) 5248 { 5249 if (kvm_vcpu_initialized(vcpu)) 5250 return; 5251 5252 reg->reset(vcpu, reg); 5253 } 5254 5255 /** 5256 * kvm_reset_sys_regs - sets system registers to reset value 5257 * @vcpu: The VCPU pointer 5258 * 5259 * This function finds the right table above and sets the registers on the 5260 * virtual CPU struct to their architecturally defined reset values. 5261 */ 5262 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 5263 { 5264 struct kvm *kvm = vcpu->kvm; 5265 unsigned long i; 5266 5267 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5268 const struct sys_reg_desc *r = &sys_reg_descs[i]; 5269 5270 if (!r->reset) 5271 continue; 5272 5273 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 5274 reset_vm_ftr_id_reg(vcpu, r); 5275 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 5276 reset_vcpu_ftr_id_reg(vcpu, r); 5277 else 5278 r->reset(vcpu, r); 5279 5280 if (r->reg >= __SANITISED_REG_START__ && r->reg < NR_SYS_REGS) 5281 __vcpu_rmw_sys_reg(vcpu, r->reg, |=, 0); 5282 } 5283 5284 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 5285 5286 if (kvm_vcpu_has_pmu(vcpu)) 5287 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 5288 } 5289 5290 /** 5291 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 5292 * trap on a guest execution 5293 * @vcpu: The VCPU pointer 5294 */ 5295 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 5296 { 5297 const struct sys_reg_desc *desc = NULL; 5298 struct sys_reg_params params; 5299 unsigned long esr = kvm_vcpu_get_esr(vcpu); 5300 int Rt = kvm_vcpu_sys_get_rt(vcpu); 5301 int sr_idx; 5302 5303 trace_kvm_handle_sys_reg(esr); 5304 5305 if (triage_sysreg_trap(vcpu, &sr_idx)) 5306 return 1; 5307 5308 params = esr_sys64_to_params(esr); 5309 params.regval = vcpu_get_reg(vcpu, Rt); 5310 5311 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 5312 if (params.Op0 == 2 || params.Op0 == 3) 5313 desc = &sys_reg_descs[sr_idx]; 5314 else 5315 desc = &sys_insn_descs[sr_idx]; 5316 5317 perform_access(vcpu, ¶ms, desc); 5318 5319 /* Read from system register? */ 5320 if (!params.is_write && 5321 (params.Op0 == 2 || params.Op0 == 3)) 5322 vcpu_set_reg(vcpu, Rt, params.regval); 5323 5324 return 1; 5325 } 5326 5327 /****************************************************************************** 5328 * Userspace API 5329 *****************************************************************************/ 5330 5331 static bool index_to_params(u64 id, struct sys_reg_params *params) 5332 { 5333 switch (id & KVM_REG_SIZE_MASK) { 5334 case KVM_REG_SIZE_U64: 5335 /* Any unused index bits means it's not valid. */ 5336 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 5337 | KVM_REG_ARM_COPROC_MASK 5338 | KVM_REG_ARM64_SYSREG_OP0_MASK 5339 | KVM_REG_ARM64_SYSREG_OP1_MASK 5340 | KVM_REG_ARM64_SYSREG_CRN_MASK 5341 | KVM_REG_ARM64_SYSREG_CRM_MASK 5342 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 5343 return false; 5344 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 5345 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 5346 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 5347 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 5348 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 5349 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 5350 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 5351 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 5352 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 5353 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 5354 return true; 5355 default: 5356 return false; 5357 } 5358 } 5359 5360 const struct sys_reg_desc *get_reg_by_id(u64 id, 5361 const struct sys_reg_desc table[], 5362 unsigned int num) 5363 { 5364 struct sys_reg_params params; 5365 5366 if (!index_to_params(id, ¶ms)) 5367 return NULL; 5368 5369 return find_reg(¶ms, table, num); 5370 } 5371 5372 /* Decode an index value, and find the sys_reg_desc entry. */ 5373 static const struct sys_reg_desc * 5374 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 5375 const struct sys_reg_desc table[], unsigned int num) 5376 5377 { 5378 const struct sys_reg_desc *r; 5379 5380 /* We only do sys_reg for now. */ 5381 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 5382 return NULL; 5383 5384 r = get_reg_by_id(id, table, num); 5385 5386 /* Not saved in the sys_reg array and not otherwise accessible? */ 5387 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 5388 r = NULL; 5389 5390 return r; 5391 } 5392 5393 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 5394 { 5395 u32 val; 5396 u32 __user *uval = uaddr; 5397 5398 /* Fail if we have unknown bits set. */ 5399 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 5400 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 5401 return -ENOENT; 5402 5403 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 5404 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 5405 if (KVM_REG_SIZE(id) != 4) 5406 return -ENOENT; 5407 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 5408 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 5409 if (val >= CSSELR_MAX) 5410 return -ENOENT; 5411 5412 return put_user(get_ccsidr(vcpu, val), uval); 5413 default: 5414 return -ENOENT; 5415 } 5416 } 5417 5418 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 5419 { 5420 u32 val, newval; 5421 u32 __user *uval = uaddr; 5422 5423 /* Fail if we have unknown bits set. */ 5424 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 5425 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 5426 return -ENOENT; 5427 5428 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 5429 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 5430 if (KVM_REG_SIZE(id) != 4) 5431 return -ENOENT; 5432 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 5433 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 5434 if (val >= CSSELR_MAX) 5435 return -ENOENT; 5436 5437 if (get_user(newval, uval)) 5438 return -EFAULT; 5439 5440 return set_ccsidr(vcpu, val, newval); 5441 default: 5442 return -ENOENT; 5443 } 5444 } 5445 5446 static u64 kvm_one_reg_to_id(const struct kvm_one_reg *reg) 5447 { 5448 switch(reg->id) { 5449 case KVM_REG_ARM_TIMER_CVAL: 5450 return TO_ARM64_SYS_REG(CNTV_CVAL_EL0); 5451 case KVM_REG_ARM_TIMER_CNT: 5452 return TO_ARM64_SYS_REG(CNTVCT_EL0); 5453 default: 5454 return reg->id; 5455 } 5456 } 5457 5458 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 5459 const struct sys_reg_desc table[], unsigned int num) 5460 { 5461 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 5462 const struct sys_reg_desc *r; 5463 u64 id = kvm_one_reg_to_id(reg); 5464 u64 val; 5465 int ret; 5466 5467 r = id_to_sys_reg_desc(vcpu, id, table, num); 5468 if (!r || sysreg_hidden(vcpu, r)) 5469 return -ENOENT; 5470 5471 if (r->get_user) { 5472 ret = (r->get_user)(vcpu, r, &val); 5473 } else { 5474 val = __vcpu_sys_reg(vcpu, r->reg); 5475 ret = 0; 5476 } 5477 5478 if (!ret) 5479 ret = put_user(val, uaddr); 5480 5481 return ret; 5482 } 5483 5484 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 5485 { 5486 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 5487 5488 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 5489 return demux_c15_get(vcpu, reg->id, uaddr); 5490 5491 return kvm_sys_reg_get_user(vcpu, reg, 5492 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 5493 } 5494 5495 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 5496 const struct sys_reg_desc table[], unsigned int num) 5497 { 5498 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 5499 const struct sys_reg_desc *r; 5500 u64 id = kvm_one_reg_to_id(reg); 5501 u64 val; 5502 int ret; 5503 5504 if (get_user(val, uaddr)) 5505 return -EFAULT; 5506 5507 r = id_to_sys_reg_desc(vcpu, id, table, num); 5508 if (!r || sysreg_hidden(vcpu, r)) 5509 return -ENOENT; 5510 5511 if (sysreg_user_write_ignore(vcpu, r)) 5512 return 0; 5513 5514 if (r->set_user) { 5515 ret = (r->set_user)(vcpu, r, val); 5516 } else { 5517 __vcpu_assign_sys_reg(vcpu, r->reg, val); 5518 ret = 0; 5519 } 5520 5521 return ret; 5522 } 5523 5524 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 5525 { 5526 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 5527 5528 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 5529 return demux_c15_set(vcpu, reg->id, uaddr); 5530 5531 return kvm_sys_reg_set_user(vcpu, reg, 5532 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 5533 } 5534 5535 static unsigned int num_demux_regs(void) 5536 { 5537 return CSSELR_MAX; 5538 } 5539 5540 static int write_demux_regids(u64 __user *uindices) 5541 { 5542 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 5543 unsigned int i; 5544 5545 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 5546 for (i = 0; i < CSSELR_MAX; i++) { 5547 if (put_user(val | i, uindices)) 5548 return -EFAULT; 5549 uindices++; 5550 } 5551 return 0; 5552 } 5553 5554 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 5555 { 5556 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 5557 KVM_REG_ARM64_SYSREG | 5558 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 5559 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 5560 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 5561 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 5562 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 5563 } 5564 5565 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 5566 { 5567 u64 idx; 5568 5569 if (!*uind) 5570 return true; 5571 5572 switch (reg_to_encoding(reg)) { 5573 case SYS_CNTV_CVAL_EL0: 5574 idx = KVM_REG_ARM_TIMER_CVAL; 5575 break; 5576 case SYS_CNTVCT_EL0: 5577 idx = KVM_REG_ARM_TIMER_CNT; 5578 break; 5579 default: 5580 idx = sys_reg_to_index(reg); 5581 } 5582 5583 if (put_user(idx, *uind)) 5584 return false; 5585 5586 (*uind)++; 5587 return true; 5588 } 5589 5590 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 5591 const struct sys_reg_desc *rd, 5592 u64 __user **uind, 5593 unsigned int *total) 5594 { 5595 /* 5596 * Ignore registers we trap but don't save, 5597 * and for which no custom user accessor is provided. 5598 */ 5599 if (!(rd->reg || rd->get_user)) 5600 return 0; 5601 5602 if (sysreg_hidden(vcpu, rd)) 5603 return 0; 5604 5605 if (!copy_reg_to_user(rd, uind)) 5606 return -EFAULT; 5607 5608 (*total)++; 5609 return 0; 5610 } 5611 5612 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 5613 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 5614 { 5615 const struct sys_reg_desc *i2, *end2; 5616 unsigned int total = 0; 5617 int err; 5618 5619 i2 = sys_reg_descs; 5620 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 5621 5622 while (i2 != end2) { 5623 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 5624 if (err) 5625 return err; 5626 } 5627 return total; 5628 } 5629 5630 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 5631 { 5632 return num_demux_regs() 5633 + walk_sys_regs(vcpu, (u64 __user *)NULL); 5634 } 5635 5636 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 5637 { 5638 int err; 5639 5640 err = walk_sys_regs(vcpu, uindices); 5641 if (err < 0) 5642 return err; 5643 uindices += err; 5644 5645 return write_demux_regids(uindices); 5646 } 5647 5648 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 5649 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 5650 sys_reg_Op1(r), \ 5651 sys_reg_CRn(r), \ 5652 sys_reg_CRm(r), \ 5653 sys_reg_Op2(r)) 5654 5655 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 5656 { 5657 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 5658 u64 __user *masks = (u64 __user *)range->addr; 5659 5660 /* Only feature id range is supported, reserved[13] must be zero. */ 5661 if (range->range || 5662 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 5663 return -EINVAL; 5664 5665 /* Wipe the whole thing first */ 5666 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 5667 return -EFAULT; 5668 5669 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5670 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 5671 u32 encoding = reg_to_encoding(reg); 5672 u64 val; 5673 5674 if (!is_feature_id_reg(encoding) || !reg->set_user) 5675 continue; 5676 5677 if (!reg->val || 5678 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 5679 continue; 5680 } 5681 val = reg->val; 5682 5683 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 5684 return -EFAULT; 5685 } 5686 5687 return 0; 5688 } 5689 5690 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 5691 { 5692 struct kvm *kvm = vcpu->kvm; 5693 5694 if (has_vhe() || has_hvhe()) 5695 vcpu->arch.hcr_el2 |= HCR_E2H; 5696 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 5697 /* route synchronous external abort exceptions to EL2 */ 5698 vcpu->arch.hcr_el2 |= HCR_TEA; 5699 /* trap error record accesses */ 5700 vcpu->arch.hcr_el2 |= HCR_TERR; 5701 } 5702 5703 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 5704 vcpu->arch.hcr_el2 |= HCR_FWB; 5705 5706 if (cpus_have_final_cap(ARM64_HAS_EVT) && 5707 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 5708 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 5709 vcpu->arch.hcr_el2 |= HCR_TID4; 5710 else 5711 vcpu->arch.hcr_el2 |= HCR_TID2; 5712 5713 if (vcpu_el1_is_32bit(vcpu)) 5714 vcpu->arch.hcr_el2 &= ~HCR_RW; 5715 5716 if (kvm_has_mte(vcpu->kvm)) 5717 vcpu->arch.hcr_el2 |= HCR_ATA; 5718 else 5719 vcpu->arch.hcr_el2 |= HCR_TID5; 5720 5721 /* 5722 * In the absence of FGT, we cannot independently trap TLBI 5723 * Range instructions. This isn't great, but trapping all 5724 * TLBIs would be far worse. Live with it... 5725 */ 5726 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 5727 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 5728 } 5729 5730 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 5731 { 5732 struct kvm *kvm = vcpu->kvm; 5733 5734 mutex_lock(&kvm->arch.config_lock); 5735 vcpu_set_hcr(vcpu); 5736 vcpu_set_ich_hcr(vcpu); 5737 vcpu_set_hcrx(vcpu); 5738 5739 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 5740 goto out; 5741 5742 compute_fgu(kvm, HFGRTR_GROUP); 5743 compute_fgu(kvm, HFGITR_GROUP); 5744 compute_fgu(kvm, HDFGRTR_GROUP); 5745 compute_fgu(kvm, HAFGRTR_GROUP); 5746 compute_fgu(kvm, HFGRTR2_GROUP); 5747 compute_fgu(kvm, HFGITR2_GROUP); 5748 compute_fgu(kvm, HDFGRTR2_GROUP); 5749 compute_fgu(kvm, ICH_HFGRTR_GROUP); 5750 compute_fgu(kvm, ICH_HFGITR_GROUP); 5751 5752 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 5753 out: 5754 mutex_unlock(&kvm->arch.config_lock); 5755 } 5756 5757 /* 5758 * Perform last adjustments to the ID registers that are implied by the 5759 * configuration outside of the ID regs themselves, as well as any 5760 * initialisation that directly depend on these ID registers (such as 5761 * RES0/RES1 behaviours). This is not the place to configure traps though. 5762 * 5763 * Because this can be called once per CPU, changes must be idempotent. 5764 */ 5765 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 5766 { 5767 struct kvm *kvm = vcpu->kvm; 5768 5769 guard(mutex)(&kvm->arch.config_lock); 5770 5771 if (vcpu_has_nv(vcpu)) { 5772 int ret = kvm_init_nv_sysregs(vcpu); 5773 if (ret) 5774 return ret; 5775 } 5776 5777 if (kvm_vm_has_ran_once(kvm)) 5778 return 0; 5779 5780 /* 5781 * This hacks into the ID registers, so only perform it when the 5782 * first vcpu runs, or the kvm_set_vm_id_reg() helper will scream. 5783 */ 5784 if (!irqchip_in_kernel(kvm)) { 5785 u64 val; 5786 5787 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1) & ~ID_AA64PFR0_EL1_GIC; 5788 kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1, val); 5789 val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR2_EL1) & ~ID_AA64PFR2_EL1_GCIE; 5790 kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR2_EL1, val); 5791 val = kvm_read_vm_id_reg(kvm, SYS_ID_PFR1_EL1) & ~ID_PFR1_EL1_GIC; 5792 kvm_set_vm_id_reg(kvm, SYS_ID_PFR1_EL1, val); 5793 } else { 5794 /* 5795 * Certain userspace software - QEMU - samples the system 5796 * register state without creating an irqchip, then blindly 5797 * restores the state prior to running the final guest. This 5798 * means that it restores the virtualization & emulation 5799 * capabilities of the host system, rather than something that 5800 * reflects the final guest state. Moreover, it checks that the 5801 * state was "correctly" restored (i.e., verbatim), bailing if 5802 * it isn't, so masking off invalid state isn't an option. 5803 * 5804 * On GICv5 hardware that supports FEAT_GCIE_LEGACY we can run 5805 * both GICv3- and GICv5-based guests. Therefore, we initially 5806 * present both ID_AA64PFR0.GIC and ID_AA64PFR2.GCIE as IMP to 5807 * reflect that userspace can create EITHER a vGICv3 or a 5808 * vGICv5. This is an architecturally invalid combination, of 5809 * course. Once an in-kernel GIC is created, the sysreg state is 5810 * updated to reflect the actual, valid configuration. 5811 * 5812 * Setting both the GIC and GCIE features to IMP unsurprisingly 5813 * results in guests falling over, and hence we need to fix up 5814 * this mess in KVM. Before running for the first time we yet 5815 * again ensure that the GIC and GCIE fields accurately reflect 5816 * the actual hardware the guest should see. 5817 * 5818 * This hack allows legacy QEMU-based GICv3 guests to run 5819 * unmodified on compatible GICv5 hosts, and avoids the inverse 5820 * problem for GICv5-based guests in the future. 5821 */ 5822 kvm_vgic_finalize_idregs(kvm); 5823 } 5824 5825 return 0; 5826 } 5827 5828 int __init kvm_sys_reg_table_init(void) 5829 { 5830 const struct sys_reg_desc *gicv3_regs; 5831 bool valid = true; 5832 unsigned int i, sz; 5833 int ret = 0; 5834 5835 /* Make sure tables are unique and in order. */ 5836 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), true); 5837 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), false); 5838 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), false); 5839 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), false); 5840 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), false); 5841 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 5842 5843 gicv3_regs = vgic_v3_get_sysreg_table(&sz); 5844 valid &= check_sysreg_table(gicv3_regs, sz, false); 5845 5846 if (!valid) 5847 return -EINVAL; 5848 5849 init_imp_id_regs(); 5850 5851 ret = populate_nv_trap_config(); 5852 5853 check_feature_map(); 5854 5855 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 5856 ret = populate_sysreg_config(sys_reg_descs + i, i); 5857 5858 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 5859 ret = populate_sysreg_config(sys_insn_descs + i, i); 5860 5861 return ret; 5862 } 5863