1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25 #include <linux/bitops.h> 26 #include <linux/bpf.h> 27 #include <linux/bpf_trace.h> 28 #include <linux/cacheflush.h> 29 #include <linux/clk.h> 30 #include <linux/crc32.h> 31 #include <linux/delay.h> 32 #include <linux/errno.h> 33 #include <linux/etherdevice.h> 34 #include <linux/fec.h> 35 #include <linux/filter.h> 36 #include <linux/gpio/consumer.h> 37 #include <linux/icmp.h> 38 #include <linux/if_vlan.h> 39 #include <linux/in.h> 40 #include <linux/interrupt.h> 41 #include <linux/io.h> 42 #include <linux/ioport.h> 43 #include <linux/ip.h> 44 #include <linux/irq.h> 45 #include <linux/kernel.h> 46 #include <linux/mdio.h> 47 #include <linux/mfd/syscon.h> 48 #include <linux/module.h> 49 #include <linux/netdevice.h> 50 #include <linux/of.h> 51 #include <linux/of_mdio.h> 52 #include <linux/of_net.h> 53 #include <linux/phy.h> 54 #include <linux/pinctrl/consumer.h> 55 #include <linux/phy_fixed.h> 56 #include <linux/platform_device.h> 57 #include <linux/pm_runtime.h> 58 #include <linux/prefetch.h> 59 #include <linux/property.h> 60 #include <linux/ptrace.h> 61 #include <linux/regmap.h> 62 #include <linux/regulator/consumer.h> 63 #include <linux/skbuff.h> 64 #include <linux/slab.h> 65 #include <linux/spinlock.h> 66 #include <linux/string.h> 67 #include <linux/tcp.h> 68 #include <linux/udp.h> 69 #include <linux/workqueue.h> 70 #include <net/ip.h> 71 #include <net/page_pool/helpers.h> 72 #include <net/selftests.h> 73 #include <net/tso.h> 74 #include <soc/imx/cpuidle.h> 75 76 #include "fec.h" 77 78 static void set_multicast_list(struct net_device *ndev); 79 static void fec_enet_itr_coal_set(struct net_device *ndev); 80 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 81 int cpu, struct xdp_buff *xdp, 82 u32 dma_sync_len); 83 84 #define DRIVER_NAME "fec" 85 86 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 87 88 #define FEC_ENET_RSEM_V 0x84 89 #define FEC_ENET_RSFL_V 16 90 #define FEC_ENET_RAEM_V 0x8 91 #define FEC_ENET_RAFL_V 0x8 92 #define FEC_ENET_OPD_V 0xFFF0 93 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 94 95 #define FEC_ENET_XDP_PASS 0 96 #define FEC_ENET_XDP_CONSUMED BIT(0) 97 #define FEC_ENET_XDP_TX BIT(1) 98 #define FEC_ENET_XDP_REDIR BIT(2) 99 100 struct fec_devinfo { 101 u32 quirks; 102 }; 103 104 static const struct fec_devinfo fec_imx25_info = { 105 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 107 }; 108 109 static const struct fec_devinfo fec_imx27_info = { 110 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 111 FEC_QUIRK_HAS_MDIO_C45, 112 }; 113 114 static const struct fec_devinfo fec_imx28_info = { 115 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 116 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 117 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 118 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 119 }; 120 121 static const struct fec_devinfo fec_imx6q_info = { 122 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 125 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 126 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 127 }; 128 129 static const struct fec_devinfo fec_mvf600_info = { 130 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 131 FEC_QUIRK_HAS_MDIO_C45, 132 }; 133 134 static const struct fec_devinfo fec_imx6sx_info = { 135 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 136 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 137 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 138 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 139 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 140 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 141 FEC_QUIRK_HAS_MDIO_C45, 142 }; 143 144 static const struct fec_devinfo fec_imx6ul_info = { 145 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 146 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 147 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 148 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 149 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 150 FEC_QUIRK_HAS_MDIO_C45, 151 }; 152 153 static const struct fec_devinfo fec_imx8mq_info = { 154 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 155 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 156 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 157 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 158 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 159 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 160 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 161 FEC_QUIRK_HAS_MDIO_C45, 162 }; 163 164 static const struct fec_devinfo fec_imx8qm_info = { 165 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 166 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 167 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 168 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 169 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 170 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 171 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45 | 172 FEC_QUIRK_JUMBO_FRAME, 173 }; 174 175 static const struct fec_devinfo fec_s32v234_info = { 176 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 177 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 178 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 179 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 180 FEC_QUIRK_HAS_MDIO_C45, 181 }; 182 183 static struct platform_device_id fec_devtype[] = { 184 { 185 /* keep it for coldfire */ 186 .name = DRIVER_NAME, 187 .driver_data = 0, 188 }, { 189 /* sentinel */ 190 } 191 }; 192 MODULE_DEVICE_TABLE(platform, fec_devtype); 193 194 static const struct of_device_id fec_dt_ids[] = { 195 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, }, 196 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, }, 197 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, }, 198 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, }, 199 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, }, 200 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6sx_info, }, 201 { .compatible = "fsl,imx6ul-fec", .data = &fec_imx6ul_info, }, 202 { .compatible = "fsl,imx8mq-fec", .data = &fec_imx8mq_info, }, 203 { .compatible = "fsl,imx8qm-fec", .data = &fec_imx8qm_info, }, 204 { .compatible = "fsl,s32v234-fec", .data = &fec_s32v234_info, }, 205 { /* sentinel */ } 206 }; 207 MODULE_DEVICE_TABLE(of, fec_dt_ids); 208 209 static unsigned char macaddr[ETH_ALEN]; 210 module_param_array(macaddr, byte, NULL, 0); 211 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 212 213 #if defined(CONFIG_M5272) 214 /* 215 * Some hardware gets it MAC address out of local flash memory. 216 * if this is non-zero then assume it is the address to get MAC from. 217 */ 218 #if defined(CONFIG_NETtel) 219 #define FEC_FLASHMAC 0xf0006006 220 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 221 #define FEC_FLASHMAC 0xf0006000 222 #elif defined(CONFIG_CANCam) 223 #define FEC_FLASHMAC 0xf0020000 224 #elif defined (CONFIG_M5272C3) 225 #define FEC_FLASHMAC (0xffe04000 + 4) 226 #elif defined(CONFIG_MOD5272) 227 #define FEC_FLASHMAC 0xffc0406b 228 #else 229 #define FEC_FLASHMAC 0 230 #endif 231 #endif /* CONFIG_M5272 */ 232 233 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 234 * 235 * 2048 byte skbufs are allocated. However, alignment requirements 236 * varies between FEC variants. Worst case is 64, so round down by 64. 237 */ 238 #define MAX_JUMBO_BUF_SIZE (round_down(16384 - FEC_DRV_RESERVE_SPACE - 64, 64)) 239 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 240 #define PKT_MINBUF_SIZE 64 241 242 /* FEC receive acceleration */ 243 #define FEC_RACC_IPDIS BIT(1) 244 #define FEC_RACC_PRODIS BIT(2) 245 #define FEC_RACC_SHIFT16 BIT(7) 246 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 247 248 /* MIB Control Register */ 249 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 250 251 /* 252 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 253 * size bits. Other FEC hardware does not, so we need to take that into 254 * account when setting it. 255 */ 256 #ifndef CONFIG_M5272 257 #define OPT_ARCH_HAS_MAX_FL 1 258 #else 259 #define OPT_ARCH_HAS_MAX_FL 0 260 #endif 261 262 /* FEC MII MMFR bits definition */ 263 #define FEC_MMFR_ST (1 << 30) 264 #define FEC_MMFR_ST_C45 (0) 265 #define FEC_MMFR_OP_READ (2 << 28) 266 #define FEC_MMFR_OP_READ_C45 (3 << 28) 267 #define FEC_MMFR_OP_WRITE (1 << 28) 268 #define FEC_MMFR_OP_ADDR_WRITE (0) 269 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 270 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 271 #define FEC_MMFR_TA (2 << 16) 272 #define FEC_MMFR_DATA(v) (v & 0xffff) 273 /* FEC ECR bits definition */ 274 #define FEC_ECR_RESET BIT(0) 275 #define FEC_ECR_ETHEREN BIT(1) 276 #define FEC_ECR_MAGICEN BIT(2) 277 #define FEC_ECR_SLEEP BIT(3) 278 #define FEC_ECR_EN1588 BIT(4) 279 #define FEC_ECR_SPEED BIT(5) 280 #define FEC_ECR_BYTESWP BIT(8) 281 /* FEC RCR bits definition */ 282 #define FEC_RCR_LOOP BIT(0) 283 #define FEC_RCR_DRT BIT(1) 284 #define FEC_RCR_MII BIT(2) 285 #define FEC_RCR_PROMISC BIT(3) 286 #define FEC_RCR_BC_REJ BIT(4) 287 #define FEC_RCR_FLOWCTL BIT(5) 288 #define FEC_RCR_RGMII BIT(6) 289 #define FEC_RCR_RMII BIT(8) 290 #define FEC_RCR_10BASET BIT(9) 291 #define FEC_RCR_NLC BIT(30) 292 /* TX WMARK bits */ 293 #define FEC_TXWMRK_STRFWD BIT(8) 294 295 #define FEC_MII_TIMEOUT 30000 /* us */ 296 297 /* Transmitter timeout */ 298 #define TX_TIMEOUT (2 * HZ) 299 300 #define FEC_PAUSE_FLAG_AUTONEG 0x1 301 #define FEC_PAUSE_FLAG_ENABLE 0x2 302 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 303 #define FEC_WOL_FLAG_ENABLE (0x1 << 1) 304 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 305 306 /* Max number of allowed TCP segments for software TSO */ 307 #define FEC_MAX_TSO_SEGS 100 308 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 309 310 #define IS_TSO_HEADER(txq, addr) \ 311 ((addr >= txq->tso_hdrs_dma) && \ 312 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 313 314 static int mii_cnt; 315 316 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 317 struct bufdesc_prop *bd) 318 { 319 return (bdp >= bd->last) ? bd->base 320 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 321 } 322 323 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 324 struct bufdesc_prop *bd) 325 { 326 return (bdp <= bd->base) ? bd->last 327 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 328 } 329 330 static int fec_enet_get_bd_index(struct bufdesc *bdp, 331 struct bufdesc_prop *bd) 332 { 333 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 334 } 335 336 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 337 { 338 int entries; 339 340 entries = (((const char *)txq->dirty_tx - 341 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 342 343 return entries >= 0 ? entries : entries + txq->bd.ring_size; 344 } 345 346 static void swap_buffer(void *bufaddr, int len) 347 { 348 int i; 349 unsigned int *buf = bufaddr; 350 351 for (i = 0; i < len; i += 4, buf++) 352 swab32s(buf); 353 } 354 355 static void fec_dump(struct net_device *ndev) 356 { 357 struct fec_enet_private *fep = netdev_priv(ndev); 358 struct bufdesc *bdp; 359 struct fec_enet_priv_tx_q *txq; 360 int index = 0; 361 362 netdev_info(ndev, "TX ring dump\n"); 363 pr_info("Nr SC addr len SKB\n"); 364 365 txq = fep->tx_queue[0]; 366 bdp = txq->bd.base; 367 368 do { 369 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 370 index, 371 bdp == txq->bd.cur ? 'S' : ' ', 372 bdp == txq->dirty_tx ? 'H' : ' ', 373 fec16_to_cpu(bdp->cbd_sc), 374 fec32_to_cpu(bdp->cbd_bufaddr), 375 fec16_to_cpu(bdp->cbd_datlen), 376 txq->tx_buf[index].buf_p); 377 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 378 index++; 379 } while (bdp != txq->bd.base); 380 } 381 382 /* 383 * Coldfire does not support DMA coherent allocations, and has historically used 384 * a band-aid with a manual flush in fec_enet_rx_queue. 385 */ 386 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 387 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 388 gfp_t gfp) 389 { 390 return dma_alloc_noncoherent(dev, size, handle, DMA_BIDIRECTIONAL, gfp); 391 } 392 393 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 394 dma_addr_t handle) 395 { 396 dma_free_noncoherent(dev, size, cpu_addr, handle, DMA_BIDIRECTIONAL); 397 } 398 #else /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 399 static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 400 gfp_t gfp) 401 { 402 return dma_alloc_coherent(dev, size, handle, gfp); 403 } 404 405 static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 406 dma_addr_t handle) 407 { 408 dma_free_coherent(dev, size, cpu_addr, handle); 409 } 410 #endif /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 411 412 struct fec_dma_devres { 413 size_t size; 414 void *vaddr; 415 dma_addr_t dma_handle; 416 }; 417 418 static void fec_dmam_release(struct device *dev, void *res) 419 { 420 struct fec_dma_devres *this = res; 421 422 fec_dma_free(dev, this->size, this->vaddr, this->dma_handle); 423 } 424 425 static void *fec_dmam_alloc(struct device *dev, size_t size, dma_addr_t *handle, 426 gfp_t gfp) 427 { 428 struct fec_dma_devres *dr; 429 void *vaddr; 430 431 dr = devres_alloc(fec_dmam_release, sizeof(*dr), gfp); 432 if (!dr) 433 return NULL; 434 vaddr = fec_dma_alloc(dev, size, handle, gfp); 435 if (!vaddr) { 436 devres_free(dr); 437 return NULL; 438 } 439 dr->vaddr = vaddr; 440 dr->dma_handle = *handle; 441 dr->size = size; 442 devres_add(dev, dr); 443 return vaddr; 444 } 445 446 static inline bool is_ipv4_pkt(struct sk_buff *skb) 447 { 448 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 449 } 450 451 static int 452 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 453 { 454 /* Only run for packets requiring a checksum. */ 455 if (skb->ip_summed != CHECKSUM_PARTIAL) 456 return 0; 457 458 if (unlikely(skb_cow_head(skb, 0))) 459 return -1; 460 461 if (is_ipv4_pkt(skb)) 462 ip_hdr(skb)->check = 0; 463 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 464 465 return 0; 466 } 467 468 static int 469 fec_enet_create_page_pool(struct fec_enet_private *fep, 470 struct fec_enet_priv_rx_q *rxq, int size) 471 { 472 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 473 struct page_pool_params pp_params = { 474 .order = fep->pagepool_order, 475 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 476 .pool_size = size, 477 .nid = dev_to_node(&fep->pdev->dev), 478 .dev = &fep->pdev->dev, 479 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 480 .offset = FEC_ENET_XDP_HEADROOM, 481 .max_len = fep->rx_frame_size, 482 }; 483 int err; 484 485 rxq->page_pool = page_pool_create(&pp_params); 486 if (IS_ERR(rxq->page_pool)) { 487 err = PTR_ERR(rxq->page_pool); 488 rxq->page_pool = NULL; 489 return err; 490 } 491 492 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 493 if (err < 0) 494 goto err_free_pp; 495 496 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 497 rxq->page_pool); 498 if (err) 499 goto err_unregister_rxq; 500 501 return 0; 502 503 err_unregister_rxq: 504 xdp_rxq_info_unreg(&rxq->xdp_rxq); 505 err_free_pp: 506 page_pool_destroy(rxq->page_pool); 507 rxq->page_pool = NULL; 508 return err; 509 } 510 511 static struct bufdesc * 512 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 513 struct sk_buff *skb, 514 struct net_device *ndev) 515 { 516 struct fec_enet_private *fep = netdev_priv(ndev); 517 struct bufdesc *bdp = txq->bd.cur; 518 struct bufdesc_ex *ebdp; 519 int nr_frags = skb_shinfo(skb)->nr_frags; 520 int frag, frag_len; 521 unsigned short status; 522 unsigned int estatus = 0; 523 skb_frag_t *this_frag; 524 unsigned int index; 525 void *bufaddr; 526 dma_addr_t addr; 527 int i; 528 529 for (frag = 0; frag < nr_frags; frag++) { 530 this_frag = &skb_shinfo(skb)->frags[frag]; 531 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 532 ebdp = (struct bufdesc_ex *)bdp; 533 534 status = fec16_to_cpu(bdp->cbd_sc); 535 status &= ~BD_ENET_TX_STATS; 536 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 537 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 538 539 /* Handle the last BD specially */ 540 if (frag == nr_frags - 1) { 541 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 542 if (fep->bufdesc_ex) { 543 estatus |= BD_ENET_TX_INT; 544 if (unlikely(skb_shinfo(skb)->tx_flags & 545 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 546 estatus |= BD_ENET_TX_TS; 547 } 548 } 549 550 if (fep->bufdesc_ex) { 551 if (fep->quirks & FEC_QUIRK_HAS_AVB) 552 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 553 if (skb->ip_summed == CHECKSUM_PARTIAL) 554 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 555 556 ebdp->cbd_bdu = 0; 557 ebdp->cbd_esc = cpu_to_fec32(estatus); 558 } 559 560 bufaddr = skb_frag_address(this_frag); 561 562 index = fec_enet_get_bd_index(bdp, &txq->bd); 563 if (((unsigned long) bufaddr) & fep->tx_align || 564 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 565 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 566 bufaddr = txq->tx_bounce[index]; 567 568 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 569 swap_buffer(bufaddr, frag_len); 570 } 571 572 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 573 DMA_TO_DEVICE); 574 if (dma_mapping_error(&fep->pdev->dev, addr)) { 575 if (net_ratelimit()) 576 netdev_err(ndev, "Tx DMA memory map failed\n"); 577 goto dma_mapping_error; 578 } 579 580 bdp->cbd_bufaddr = cpu_to_fec32(addr); 581 bdp->cbd_datlen = cpu_to_fec16(frag_len); 582 /* Make sure the updates to rest of the descriptor are 583 * performed before transferring ownership. 584 */ 585 wmb(); 586 bdp->cbd_sc = cpu_to_fec16(status); 587 } 588 589 return bdp; 590 dma_mapping_error: 591 bdp = txq->bd.cur; 592 for (i = 0; i < frag; i++) { 593 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 594 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 595 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 596 } 597 return ERR_PTR(-ENOMEM); 598 } 599 600 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 601 struct sk_buff *skb, struct net_device *ndev) 602 { 603 struct fec_enet_private *fep = netdev_priv(ndev); 604 int nr_frags = skb_shinfo(skb)->nr_frags; 605 struct bufdesc *bdp, *last_bdp; 606 void *bufaddr; 607 dma_addr_t addr; 608 unsigned short status; 609 unsigned short buflen; 610 unsigned int estatus = 0; 611 unsigned int index; 612 int entries_free; 613 614 entries_free = fec_enet_get_free_txdesc_num(txq); 615 if (entries_free < MAX_SKB_FRAGS + 1) { 616 dev_kfree_skb_any(skb); 617 if (net_ratelimit()) 618 netdev_err(ndev, "NOT enough BD for SG!\n"); 619 return NETDEV_TX_OK; 620 } 621 622 /* Protocol checksum off-load for TCP and UDP. */ 623 if (fec_enet_clear_csum(skb, ndev)) { 624 dev_kfree_skb_any(skb); 625 return NETDEV_TX_OK; 626 } 627 628 /* Fill in a Tx ring entry */ 629 bdp = txq->bd.cur; 630 last_bdp = bdp; 631 status = fec16_to_cpu(bdp->cbd_sc); 632 status &= ~BD_ENET_TX_STATS; 633 634 /* Set buffer length and buffer pointer */ 635 bufaddr = skb->data; 636 buflen = skb_headlen(skb); 637 638 index = fec_enet_get_bd_index(bdp, &txq->bd); 639 if (((unsigned long) bufaddr) & fep->tx_align || 640 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 641 memcpy(txq->tx_bounce[index], skb->data, buflen); 642 bufaddr = txq->tx_bounce[index]; 643 644 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 645 swap_buffer(bufaddr, buflen); 646 } 647 648 /* Push the data cache so the CPM does not get stale memory data. */ 649 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 650 if (dma_mapping_error(&fep->pdev->dev, addr)) { 651 dev_kfree_skb_any(skb); 652 if (net_ratelimit()) 653 netdev_err(ndev, "Tx DMA memory map failed\n"); 654 return NETDEV_TX_OK; 655 } 656 657 if (nr_frags) { 658 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 659 if (IS_ERR(last_bdp)) { 660 dma_unmap_single(&fep->pdev->dev, addr, 661 buflen, DMA_TO_DEVICE); 662 dev_kfree_skb_any(skb); 663 return NETDEV_TX_OK; 664 } 665 } else { 666 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 667 if (fep->bufdesc_ex) { 668 estatus = BD_ENET_TX_INT; 669 if (unlikely(skb_shinfo(skb)->tx_flags & 670 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 671 estatus |= BD_ENET_TX_TS; 672 } 673 } 674 bdp->cbd_bufaddr = cpu_to_fec32(addr); 675 bdp->cbd_datlen = cpu_to_fec16(buflen); 676 677 if (fep->bufdesc_ex) { 678 679 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 680 681 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 682 fep->hwts_tx_en)) 683 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 684 685 if (fep->quirks & FEC_QUIRK_HAS_AVB) 686 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 687 688 if (skb->ip_summed == CHECKSUM_PARTIAL) 689 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 690 691 ebdp->cbd_bdu = 0; 692 ebdp->cbd_esc = cpu_to_fec32(estatus); 693 } 694 695 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 696 /* Save skb pointer */ 697 txq->tx_buf[index].buf_p = skb; 698 699 /* Make sure the updates to rest of the descriptor are performed before 700 * transferring ownership. 701 */ 702 wmb(); 703 704 /* Send it on its way. Tell FEC it's ready, interrupt when done, 705 * it's the last BD of the frame, and to put the CRC on the end. 706 */ 707 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 708 bdp->cbd_sc = cpu_to_fec16(status); 709 710 /* If this was the last BD in the ring, start at the beginning again. */ 711 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 712 713 skb_tx_timestamp(skb); 714 715 /* Make sure the update to bdp is performed before txq->bd.cur. */ 716 wmb(); 717 txq->bd.cur = bdp; 718 719 /* Trigger transmission start */ 720 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 721 !readl(txq->bd.reg_desc_active) || 722 !readl(txq->bd.reg_desc_active) || 723 !readl(txq->bd.reg_desc_active) || 724 !readl(txq->bd.reg_desc_active)) 725 writel(0, txq->bd.reg_desc_active); 726 727 return 0; 728 } 729 730 static int 731 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 732 struct net_device *ndev, 733 struct bufdesc *bdp, int index, char *data, 734 int size, bool last_tcp, bool is_last) 735 { 736 struct fec_enet_private *fep = netdev_priv(ndev); 737 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 738 unsigned short status; 739 unsigned int estatus = 0; 740 dma_addr_t addr; 741 742 status = fec16_to_cpu(bdp->cbd_sc); 743 status &= ~BD_ENET_TX_STATS; 744 745 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 746 747 if (((unsigned long) data) & fep->tx_align || 748 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 749 memcpy(txq->tx_bounce[index], data, size); 750 data = txq->tx_bounce[index]; 751 752 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 753 swap_buffer(data, size); 754 } 755 756 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 757 if (dma_mapping_error(&fep->pdev->dev, addr)) { 758 dev_kfree_skb_any(skb); 759 if (net_ratelimit()) 760 netdev_err(ndev, "Tx DMA memory map failed\n"); 761 return NETDEV_TX_OK; 762 } 763 764 bdp->cbd_datlen = cpu_to_fec16(size); 765 bdp->cbd_bufaddr = cpu_to_fec32(addr); 766 767 if (fep->bufdesc_ex) { 768 if (fep->quirks & FEC_QUIRK_HAS_AVB) 769 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 770 if (skb->ip_summed == CHECKSUM_PARTIAL) 771 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 772 ebdp->cbd_bdu = 0; 773 ebdp->cbd_esc = cpu_to_fec32(estatus); 774 } 775 776 /* Handle the last BD specially */ 777 if (last_tcp) 778 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 779 if (is_last) { 780 status |= BD_ENET_TX_INTR; 781 if (fep->bufdesc_ex) 782 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 783 } 784 785 bdp->cbd_sc = cpu_to_fec16(status); 786 787 return 0; 788 } 789 790 static int 791 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 792 struct sk_buff *skb, struct net_device *ndev, 793 struct bufdesc *bdp, int index) 794 { 795 struct fec_enet_private *fep = netdev_priv(ndev); 796 int hdr_len = skb_tcp_all_headers(skb); 797 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 798 void *bufaddr; 799 unsigned long dmabuf; 800 unsigned short status; 801 unsigned int estatus = 0; 802 803 status = fec16_to_cpu(bdp->cbd_sc); 804 status &= ~BD_ENET_TX_STATS; 805 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 806 807 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 808 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 809 if (((unsigned long)bufaddr) & fep->tx_align || 810 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 811 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 812 bufaddr = txq->tx_bounce[index]; 813 814 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 815 swap_buffer(bufaddr, hdr_len); 816 817 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 818 hdr_len, DMA_TO_DEVICE); 819 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 820 dev_kfree_skb_any(skb); 821 if (net_ratelimit()) 822 netdev_err(ndev, "Tx DMA memory map failed\n"); 823 return NETDEV_TX_OK; 824 } 825 } 826 827 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 828 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 829 830 if (fep->bufdesc_ex) { 831 if (fep->quirks & FEC_QUIRK_HAS_AVB) 832 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 833 if (skb->ip_summed == CHECKSUM_PARTIAL) 834 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 835 ebdp->cbd_bdu = 0; 836 ebdp->cbd_esc = cpu_to_fec32(estatus); 837 } 838 839 bdp->cbd_sc = cpu_to_fec16(status); 840 841 return 0; 842 } 843 844 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 845 struct sk_buff *skb, 846 struct net_device *ndev) 847 { 848 struct fec_enet_private *fep = netdev_priv(ndev); 849 int hdr_len, total_len, data_left; 850 struct bufdesc *bdp = txq->bd.cur; 851 struct bufdesc *tmp_bdp; 852 struct bufdesc_ex *ebdp; 853 struct tso_t tso; 854 unsigned int index = 0; 855 int ret; 856 857 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 858 dev_kfree_skb_any(skb); 859 if (net_ratelimit()) 860 netdev_err(ndev, "NOT enough BD for TSO!\n"); 861 return NETDEV_TX_OK; 862 } 863 864 /* Protocol checksum off-load for TCP and UDP. */ 865 if (fec_enet_clear_csum(skb, ndev)) { 866 dev_kfree_skb_any(skb); 867 return NETDEV_TX_OK; 868 } 869 870 /* Initialize the TSO handler, and prepare the first payload */ 871 hdr_len = tso_start(skb, &tso); 872 873 total_len = skb->len - hdr_len; 874 while (total_len > 0) { 875 char *hdr; 876 877 index = fec_enet_get_bd_index(bdp, &txq->bd); 878 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 879 total_len -= data_left; 880 881 /* prepare packet headers: MAC + IP + TCP */ 882 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 883 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 884 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 885 if (ret) 886 goto err_release; 887 888 while (data_left > 0) { 889 int size; 890 891 size = min_t(int, tso.size, data_left); 892 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 893 index = fec_enet_get_bd_index(bdp, &txq->bd); 894 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 895 bdp, index, 896 tso.data, size, 897 size == data_left, 898 total_len == 0); 899 if (ret) 900 goto err_release; 901 902 data_left -= size; 903 tso_build_data(skb, &tso, size); 904 } 905 906 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 907 } 908 909 /* Save skb pointer */ 910 txq->tx_buf[index].buf_p = skb; 911 912 skb_tx_timestamp(skb); 913 txq->bd.cur = bdp; 914 915 /* Trigger transmission start */ 916 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 917 !readl(txq->bd.reg_desc_active) || 918 !readl(txq->bd.reg_desc_active) || 919 !readl(txq->bd.reg_desc_active) || 920 !readl(txq->bd.reg_desc_active)) 921 writel(0, txq->bd.reg_desc_active); 922 923 return 0; 924 925 err_release: 926 /* Release all used data descriptors for TSO */ 927 tmp_bdp = txq->bd.cur; 928 929 while (tmp_bdp != bdp) { 930 /* Unmap data buffers */ 931 if (tmp_bdp->cbd_bufaddr && 932 !IS_TSO_HEADER(txq, fec32_to_cpu(tmp_bdp->cbd_bufaddr))) 933 dma_unmap_single(&fep->pdev->dev, 934 fec32_to_cpu(tmp_bdp->cbd_bufaddr), 935 fec16_to_cpu(tmp_bdp->cbd_datlen), 936 DMA_TO_DEVICE); 937 938 /* Clear standard buffer descriptor fields */ 939 tmp_bdp->cbd_sc = 0; 940 tmp_bdp->cbd_datlen = 0; 941 tmp_bdp->cbd_bufaddr = 0; 942 943 /* Handle extended descriptor if enabled */ 944 if (fep->bufdesc_ex) { 945 ebdp = (struct bufdesc_ex *)tmp_bdp; 946 ebdp->cbd_esc = 0; 947 } 948 949 tmp_bdp = fec_enet_get_nextdesc(tmp_bdp, &txq->bd); 950 } 951 952 dev_kfree_skb_any(skb); 953 954 return ret; 955 } 956 957 static netdev_tx_t 958 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 959 { 960 struct fec_enet_private *fep = netdev_priv(ndev); 961 int entries_free; 962 unsigned short queue; 963 struct fec_enet_priv_tx_q *txq; 964 struct netdev_queue *nq; 965 int ret; 966 967 queue = skb_get_queue_mapping(skb); 968 txq = fep->tx_queue[queue]; 969 nq = netdev_get_tx_queue(ndev, queue); 970 971 if (skb_is_gso(skb)) 972 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 973 else 974 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 975 if (ret) 976 return ret; 977 978 entries_free = fec_enet_get_free_txdesc_num(txq); 979 if (entries_free <= txq->tx_stop_threshold) 980 netif_tx_stop_queue(nq); 981 982 return NETDEV_TX_OK; 983 } 984 985 /* Init RX & TX buffer descriptors 986 */ 987 static void fec_enet_bd_init(struct net_device *dev) 988 { 989 struct fec_enet_private *fep = netdev_priv(dev); 990 struct fec_enet_priv_tx_q *txq; 991 struct fec_enet_priv_rx_q *rxq; 992 struct bufdesc *bdp; 993 unsigned int i; 994 unsigned int q; 995 996 for (q = 0; q < fep->num_rx_queues; q++) { 997 /* Initialize the receive buffer descriptors. */ 998 rxq = fep->rx_queue[q]; 999 bdp = rxq->bd.base; 1000 1001 for (i = 0; i < rxq->bd.ring_size; i++) { 1002 1003 /* Initialize the BD for every fragment in the page. */ 1004 if (bdp->cbd_bufaddr) 1005 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 1006 else 1007 bdp->cbd_sc = cpu_to_fec16(0); 1008 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1009 } 1010 1011 /* Set the last buffer to wrap */ 1012 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 1013 bdp->cbd_sc |= cpu_to_fec16(BD_ENET_RX_WRAP); 1014 1015 rxq->bd.cur = rxq->bd.base; 1016 } 1017 1018 for (q = 0; q < fep->num_tx_queues; q++) { 1019 /* ...and the same for transmit */ 1020 txq = fep->tx_queue[q]; 1021 bdp = txq->bd.base; 1022 txq->bd.cur = bdp; 1023 1024 for (i = 0; i < txq->bd.ring_size; i++) { 1025 /* Initialize the BD for every fragment in the page. */ 1026 bdp->cbd_sc = cpu_to_fec16(0); 1027 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 1028 if (bdp->cbd_bufaddr && 1029 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1030 dma_unmap_single(&fep->pdev->dev, 1031 fec32_to_cpu(bdp->cbd_bufaddr), 1032 fec16_to_cpu(bdp->cbd_datlen), 1033 DMA_TO_DEVICE); 1034 if (txq->tx_buf[i].buf_p) 1035 dev_kfree_skb_any(txq->tx_buf[i].buf_p); 1036 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 1037 if (bdp->cbd_bufaddr) 1038 dma_unmap_single(&fep->pdev->dev, 1039 fec32_to_cpu(bdp->cbd_bufaddr), 1040 fec16_to_cpu(bdp->cbd_datlen), 1041 DMA_TO_DEVICE); 1042 1043 if (txq->tx_buf[i].buf_p) 1044 xdp_return_frame(txq->tx_buf[i].buf_p); 1045 } else { 1046 struct page *page = txq->tx_buf[i].buf_p; 1047 1048 if (page) 1049 page_pool_put_page(pp_page_to_nmdesc(page)->pp, 1050 page, 0, 1051 false); 1052 } 1053 1054 txq->tx_buf[i].buf_p = NULL; 1055 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1056 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 1057 bdp->cbd_bufaddr = cpu_to_fec32(0); 1058 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1059 } 1060 1061 /* Set the last buffer to wrap */ 1062 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 1063 bdp->cbd_sc |= cpu_to_fec16(BD_ENET_TX_WRAP); 1064 txq->dirty_tx = bdp; 1065 } 1066 } 1067 1068 static void fec_enet_active_rxring(struct net_device *ndev) 1069 { 1070 struct fec_enet_private *fep = netdev_priv(ndev); 1071 int i; 1072 1073 for (i = 0; i < fep->num_rx_queues; i++) 1074 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 1075 } 1076 1077 static void fec_enet_enable_ring(struct net_device *ndev) 1078 { 1079 struct fec_enet_private *fep = netdev_priv(ndev); 1080 struct fec_enet_priv_tx_q *txq; 1081 struct fec_enet_priv_rx_q *rxq; 1082 int i; 1083 1084 for (i = 0; i < fep->num_rx_queues; i++) { 1085 rxq = fep->rx_queue[i]; 1086 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 1087 writel(fep->max_buf_size, fep->hwp + FEC_R_BUFF_SIZE(i)); 1088 1089 /* enable DMA1/2 */ 1090 if (i) 1091 writel(RCMR_MATCHEN | RCMR_CMP(i), 1092 fep->hwp + FEC_RCMR(i)); 1093 } 1094 1095 for (i = 0; i < fep->num_tx_queues; i++) { 1096 txq = fep->tx_queue[i]; 1097 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1098 1099 /* enable DMA1/2 */ 1100 if (i) 1101 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1102 fep->hwp + FEC_DMA_CFG(i)); 1103 } 1104 } 1105 1106 /* Whack a reset. We should wait for this. 1107 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1108 * instead of reset MAC itself. 1109 */ 1110 static void fec_ctrl_reset(struct fec_enet_private *fep, bool allow_wol) 1111 { 1112 u32 val; 1113 1114 if (!allow_wol || !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1115 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1116 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1117 writel(0, fep->hwp + FEC_ECNTRL); 1118 } else { 1119 writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL); 1120 udelay(10); 1121 } 1122 } else { 1123 val = readl(fep->hwp + FEC_ECNTRL); 1124 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1125 writel(val, fep->hwp + FEC_ECNTRL); 1126 } 1127 } 1128 1129 static void fec_set_hw_mac_addr(struct net_device *ndev) 1130 { 1131 struct fec_enet_private *fep = netdev_priv(ndev); 1132 1133 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1134 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1135 fep->hwp + FEC_ADDR_LOW); 1136 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1137 fep->hwp + FEC_ADDR_HIGH); 1138 } 1139 1140 /* 1141 * This function is called to start or restart the FEC during a link 1142 * change, transmit timeout, or to reconfigure the FEC. The network 1143 * packet processing for this device must be stopped before this call. 1144 */ 1145 static void 1146 fec_restart(struct net_device *ndev) 1147 { 1148 struct fec_enet_private *fep = netdev_priv(ndev); 1149 u32 ecntl = FEC_ECR_ETHEREN; 1150 u32 rcntl = FEC_RCR_MII; 1151 1152 if (OPT_ARCH_HAS_MAX_FL) 1153 rcntl |= (fep->netdev->mtu + ETH_HLEN + ETH_FCS_LEN) << 16; 1154 1155 if (fep->bufdesc_ex) 1156 fec_ptp_save_state(fep); 1157 1158 fec_ctrl_reset(fep, false); 1159 1160 /* 1161 * enet-mac reset will reset mac address registers too, 1162 * so need to reconfigure it. 1163 */ 1164 fec_set_hw_mac_addr(ndev); 1165 1166 /* Clear any outstanding interrupt, except MDIO. */ 1167 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1168 1169 fec_enet_bd_init(ndev); 1170 1171 fec_enet_enable_ring(ndev); 1172 1173 /* Enable MII mode */ 1174 if (fep->full_duplex == DUPLEX_FULL) { 1175 /* FD enable */ 1176 writel(0x04, fep->hwp + FEC_X_CNTRL); 1177 } else { 1178 /* No Rcv on Xmit */ 1179 rcntl |= FEC_RCR_DRT; 1180 writel(0x0, fep->hwp + FEC_X_CNTRL); 1181 } 1182 1183 /* Set MII speed */ 1184 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1185 1186 #if !defined(CONFIG_M5272) 1187 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1188 u32 val = readl(fep->hwp + FEC_RACC); 1189 1190 /* align IP header */ 1191 val |= FEC_RACC_SHIFT16; 1192 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1193 /* set RX checksum */ 1194 val |= FEC_RACC_OPTIONS; 1195 else 1196 val &= ~FEC_RACC_OPTIONS; 1197 writel(val, fep->hwp + FEC_RACC); 1198 writel(min(fep->rx_frame_size, fep->max_buf_size), fep->hwp + FEC_FTRL); 1199 } 1200 #endif 1201 1202 /* 1203 * The phy interface and speed need to get configured 1204 * differently on enet-mac. 1205 */ 1206 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1207 /* Enable flow control and length check */ 1208 rcntl |= FEC_RCR_NLC | FEC_RCR_FLOWCTL; 1209 1210 /* RGMII, RMII or MII */ 1211 if (phy_interface_mode_is_rgmii(fep->phy_interface)) 1212 rcntl |= FEC_RCR_RGMII; 1213 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1214 rcntl |= FEC_RCR_RMII; 1215 else 1216 rcntl &= ~FEC_RCR_RMII; 1217 1218 /* 1G, 100M or 10M */ 1219 if (ndev->phydev) { 1220 if (ndev->phydev->speed == SPEED_1000) 1221 ecntl |= FEC_ECR_SPEED; 1222 else if (ndev->phydev->speed == SPEED_100) 1223 rcntl &= ~FEC_RCR_10BASET; 1224 else 1225 rcntl |= FEC_RCR_10BASET; 1226 } 1227 } else { 1228 #ifdef FEC_MIIGSK_ENR 1229 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1230 u32 cfgr; 1231 /* disable the gasket and wait */ 1232 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1233 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1234 udelay(1); 1235 1236 /* 1237 * configure the gasket: 1238 * RMII, 50 MHz, no loopback, no echo 1239 * MII, 25 MHz, no loopback, no echo 1240 */ 1241 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1242 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1243 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1244 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1245 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1246 1247 /* re-enable the gasket */ 1248 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1249 } 1250 #endif 1251 } 1252 1253 #if !defined(CONFIG_M5272) 1254 /* enable pause frame*/ 1255 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1256 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1257 ndev->phydev && ndev->phydev->pause)) { 1258 rcntl |= FEC_RCR_FLOWCTL; 1259 1260 /* set FIFO threshold parameter to reduce overrun */ 1261 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1262 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1263 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1264 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1265 1266 /* OPD */ 1267 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1268 } else { 1269 rcntl &= ~FEC_RCR_FLOWCTL; 1270 } 1271 #endif /* !defined(CONFIG_M5272) */ 1272 1273 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1274 1275 /* Setup multicast filter. */ 1276 set_multicast_list(ndev); 1277 #ifndef CONFIG_M5272 1278 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1279 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1280 #endif 1281 1282 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1283 /* enable ENET endian swap */ 1284 ecntl |= FEC_ECR_BYTESWP; 1285 1286 /* When Jumbo Frame is enabled, the FIFO may not be large enough 1287 * to hold an entire frame. In such cases, if the MTU exceeds 1288 * (PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN), configure the interface 1289 * to operate in cut-through mode, triggered by the FIFO threshold. 1290 * Otherwise, enable the ENET store-and-forward mode. 1291 */ 1292 if ((fep->quirks & FEC_QUIRK_JUMBO_FRAME) && 1293 (ndev->mtu > (PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN))) 1294 writel(0xF, fep->hwp + FEC_X_WMRK); 1295 else 1296 writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK); 1297 } 1298 1299 if (fep->bufdesc_ex) 1300 ecntl |= FEC_ECR_EN1588; 1301 1302 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1303 fep->rgmii_txc_dly) 1304 ecntl |= FEC_ENET_TXC_DLY; 1305 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1306 fep->rgmii_rxc_dly) 1307 ecntl |= FEC_ENET_RXC_DLY; 1308 1309 #ifndef CONFIG_M5272 1310 /* Enable the MIB statistic event counters */ 1311 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1312 #endif 1313 1314 /* And last, enable the transmit and receive processing */ 1315 writel(ecntl, fep->hwp + FEC_ECNTRL); 1316 fec_enet_active_rxring(ndev); 1317 1318 if (fep->bufdesc_ex) { 1319 fec_ptp_start_cyclecounter(ndev); 1320 fec_ptp_restore_state(fep); 1321 } 1322 1323 /* Enable interrupts we wish to service */ 1324 if (fep->link) 1325 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1326 else 1327 writel(0, fep->hwp + FEC_IMASK); 1328 1329 /* Init the interrupt coalescing */ 1330 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1331 fec_enet_itr_coal_set(ndev); 1332 } 1333 1334 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1335 { 1336 if (!(of_machine_is_compatible("fsl,imx8qm") || 1337 of_machine_is_compatible("fsl,imx8qxp") || 1338 of_machine_is_compatible("fsl,imx8dxl"))) 1339 return 0; 1340 1341 return imx_scu_get_handle(&fep->ipc_handle); 1342 } 1343 1344 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1345 { 1346 struct device_node *np = fep->pdev->dev.of_node; 1347 u32 rsrc_id, val; 1348 int idx; 1349 1350 if (!np || !fep->ipc_handle) 1351 return; 1352 1353 idx = of_alias_get_id(np, "ethernet"); 1354 if (idx < 0) 1355 idx = 0; 1356 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1357 1358 val = enabled ? 1 : 0; 1359 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1360 } 1361 1362 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1363 { 1364 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1365 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1366 1367 if (stop_gpr->gpr) { 1368 if (enabled) 1369 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1370 BIT(stop_gpr->bit), 1371 BIT(stop_gpr->bit)); 1372 else 1373 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1374 BIT(stop_gpr->bit), 0); 1375 } else if (pdata && pdata->sleep_mode_enable) { 1376 pdata->sleep_mode_enable(enabled); 1377 } else { 1378 fec_enet_ipg_stop_set(fep, enabled); 1379 } 1380 } 1381 1382 static void fec_irqs_disable(struct net_device *ndev) 1383 { 1384 struct fec_enet_private *fep = netdev_priv(ndev); 1385 1386 writel(0, fep->hwp + FEC_IMASK); 1387 } 1388 1389 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1390 { 1391 struct fec_enet_private *fep = netdev_priv(ndev); 1392 1393 writel(0, fep->hwp + FEC_IMASK); 1394 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1395 } 1396 1397 static void 1398 fec_stop(struct net_device *ndev) 1399 { 1400 struct fec_enet_private *fep = netdev_priv(ndev); 1401 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII; 1402 u32 val; 1403 1404 /* We cannot expect a graceful transmit stop without link !!! */ 1405 if (fep->link) { 1406 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1407 udelay(10); 1408 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1409 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1410 } 1411 1412 if (fep->bufdesc_ex) 1413 fec_ptp_save_state(fep); 1414 1415 fec_ctrl_reset(fep, true); 1416 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1417 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1418 1419 /* We have to keep ENET enabled to have MII interrupt stay working */ 1420 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1421 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1422 writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL); 1423 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1424 } 1425 1426 if (fep->bufdesc_ex) { 1427 val = readl(fep->hwp + FEC_ECNTRL); 1428 val |= FEC_ECR_EN1588; 1429 writel(val, fep->hwp + FEC_ECNTRL); 1430 1431 fec_ptp_start_cyclecounter(ndev); 1432 fec_ptp_restore_state(fep); 1433 } 1434 } 1435 1436 static void 1437 fec_timeout(struct net_device *ndev, unsigned int txqueue) 1438 { 1439 struct fec_enet_private *fep = netdev_priv(ndev); 1440 1441 fec_dump(ndev); 1442 1443 ndev->stats.tx_errors++; 1444 1445 schedule_work(&fep->tx_timeout_work); 1446 } 1447 1448 static void fec_enet_timeout_work(struct work_struct *work) 1449 { 1450 struct fec_enet_private *fep = 1451 container_of(work, struct fec_enet_private, tx_timeout_work); 1452 struct net_device *ndev = fep->netdev; 1453 1454 rtnl_lock(); 1455 if (netif_device_present(ndev) || netif_running(ndev)) { 1456 napi_disable(&fep->napi); 1457 netif_tx_lock_bh(ndev); 1458 fec_restart(ndev); 1459 netif_tx_wake_all_queues(ndev); 1460 netif_tx_unlock_bh(ndev); 1461 napi_enable(&fep->napi); 1462 } 1463 rtnl_unlock(); 1464 } 1465 1466 static void 1467 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1468 struct skb_shared_hwtstamps *hwtstamps) 1469 { 1470 unsigned long flags; 1471 u64 ns; 1472 1473 spin_lock_irqsave(&fep->tmreg_lock, flags); 1474 ns = timecounter_cyc2time(&fep->tc, ts); 1475 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1476 1477 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1478 hwtstamps->hwtstamp = ns_to_ktime(ns); 1479 } 1480 1481 static void 1482 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1483 { 1484 struct fec_enet_private *fep; 1485 struct xdp_frame *xdpf; 1486 struct bufdesc *bdp; 1487 unsigned short status; 1488 struct sk_buff *skb; 1489 struct fec_enet_priv_tx_q *txq; 1490 struct netdev_queue *nq; 1491 int index = 0; 1492 int entries_free; 1493 struct page *page; 1494 int frame_len; 1495 1496 fep = netdev_priv(ndev); 1497 1498 txq = fep->tx_queue[queue_id]; 1499 /* get next bdp of dirty_tx */ 1500 nq = netdev_get_tx_queue(ndev, queue_id); 1501 bdp = txq->dirty_tx; 1502 1503 /* get next bdp of dirty_tx */ 1504 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1505 1506 while (bdp != READ_ONCE(txq->bd.cur)) { 1507 /* Order the load of bd.cur and cbd_sc */ 1508 rmb(); 1509 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1510 if (status & BD_ENET_TX_READY) 1511 break; 1512 1513 index = fec_enet_get_bd_index(bdp, &txq->bd); 1514 1515 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1516 skb = txq->tx_buf[index].buf_p; 1517 if (bdp->cbd_bufaddr && 1518 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1519 dma_unmap_single(&fep->pdev->dev, 1520 fec32_to_cpu(bdp->cbd_bufaddr), 1521 fec16_to_cpu(bdp->cbd_datlen), 1522 DMA_TO_DEVICE); 1523 bdp->cbd_bufaddr = cpu_to_fec32(0); 1524 if (!skb) 1525 goto tx_buf_done; 1526 } else { 1527 /* Tx processing cannot call any XDP (or page pool) APIs if 1528 * the "budget" is 0. Because NAPI is called with budget of 1529 * 0 (such as netpoll) indicates we may be in an IRQ context, 1530 * however, we can't use the page pool from IRQ context. 1531 */ 1532 if (unlikely(!budget)) 1533 break; 1534 1535 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1536 xdpf = txq->tx_buf[index].buf_p; 1537 if (bdp->cbd_bufaddr) 1538 dma_unmap_single(&fep->pdev->dev, 1539 fec32_to_cpu(bdp->cbd_bufaddr), 1540 fec16_to_cpu(bdp->cbd_datlen), 1541 DMA_TO_DEVICE); 1542 } else { 1543 page = txq->tx_buf[index].buf_p; 1544 } 1545 1546 bdp->cbd_bufaddr = cpu_to_fec32(0); 1547 if (unlikely(!txq->tx_buf[index].buf_p)) { 1548 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1549 goto tx_buf_done; 1550 } 1551 1552 frame_len = fec16_to_cpu(bdp->cbd_datlen); 1553 } 1554 1555 /* Check for errors. */ 1556 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1557 BD_ENET_TX_RL | BD_ENET_TX_UN | 1558 BD_ENET_TX_CSL)) { 1559 ndev->stats.tx_errors++; 1560 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1561 ndev->stats.tx_heartbeat_errors++; 1562 if (status & BD_ENET_TX_LC) /* Late collision */ 1563 ndev->stats.tx_window_errors++; 1564 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1565 ndev->stats.tx_aborted_errors++; 1566 if (status & BD_ENET_TX_UN) /* Underrun */ 1567 ndev->stats.tx_fifo_errors++; 1568 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1569 ndev->stats.tx_carrier_errors++; 1570 } else { 1571 ndev->stats.tx_packets++; 1572 1573 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1574 ndev->stats.tx_bytes += skb->len; 1575 else 1576 ndev->stats.tx_bytes += frame_len; 1577 } 1578 1579 /* Deferred means some collisions occurred during transmit, 1580 * but we eventually sent the packet OK. 1581 */ 1582 if (status & BD_ENET_TX_DEF) 1583 ndev->stats.collisions++; 1584 1585 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1586 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1587 * are to time stamp the packet, so we still need to check time 1588 * stamping enabled flag. 1589 */ 1590 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1591 fep->hwts_tx_en) && fep->bufdesc_ex) { 1592 struct skb_shared_hwtstamps shhwtstamps; 1593 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1594 1595 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1596 skb_tstamp_tx(skb, &shhwtstamps); 1597 } 1598 1599 /* Free the sk buffer associated with this last transmit */ 1600 napi_consume_skb(skb, budget); 1601 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1602 xdp_return_frame_rx_napi(xdpf); 1603 } else { /* recycle pages of XDP_TX frames */ 1604 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */ 1605 page_pool_put_page(pp_page_to_nmdesc(page)->pp, page, 1606 0, true); 1607 } 1608 1609 txq->tx_buf[index].buf_p = NULL; 1610 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1611 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1612 1613 tx_buf_done: 1614 /* Make sure the update to bdp and tx_buf are performed 1615 * before dirty_tx 1616 */ 1617 wmb(); 1618 txq->dirty_tx = bdp; 1619 1620 /* Update pointer to next buffer descriptor to be transmitted */ 1621 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1622 1623 /* Since we have freed up a buffer, the ring is no longer full 1624 */ 1625 if (netif_tx_queue_stopped(nq)) { 1626 entries_free = fec_enet_get_free_txdesc_num(txq); 1627 if (entries_free >= txq->tx_wake_threshold) 1628 netif_tx_wake_queue(nq); 1629 } 1630 } 1631 1632 /* ERR006358: Keep the transmitter going */ 1633 if (bdp != txq->bd.cur && 1634 readl(txq->bd.reg_desc_active) == 0) 1635 writel(0, txq->bd.reg_desc_active); 1636 } 1637 1638 static void fec_enet_tx(struct net_device *ndev, int budget) 1639 { 1640 struct fec_enet_private *fep = netdev_priv(ndev); 1641 int i; 1642 1643 /* Make sure that AVB queues are processed first. */ 1644 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1645 fec_enet_tx_queue(ndev, i, budget); 1646 } 1647 1648 static int fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1649 struct bufdesc *bdp, int index) 1650 { 1651 struct page *new_page; 1652 dma_addr_t phys_addr; 1653 1654 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1655 if (unlikely(!new_page)) 1656 return -ENOMEM; 1657 1658 rxq->rx_buf[index] = new_page; 1659 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1660 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1661 1662 return 0; 1663 } 1664 1665 static u32 1666 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1667 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu) 1668 { 1669 unsigned int sync, len = xdp->data_end - xdp->data; 1670 u32 ret = FEC_ENET_XDP_PASS; 1671 struct page *page; 1672 int err; 1673 u32 act; 1674 1675 act = bpf_prog_run_xdp(prog, xdp); 1676 1677 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover 1678 * max len CPU touch 1679 */ 1680 sync = xdp->data_end - xdp->data; 1681 sync = max(sync, len); 1682 1683 switch (act) { 1684 case XDP_PASS: 1685 rxq->stats[RX_XDP_PASS]++; 1686 ret = FEC_ENET_XDP_PASS; 1687 break; 1688 1689 case XDP_REDIRECT: 1690 rxq->stats[RX_XDP_REDIRECT]++; 1691 err = xdp_do_redirect(fep->netdev, xdp, prog); 1692 if (unlikely(err)) 1693 goto xdp_err; 1694 1695 ret = FEC_ENET_XDP_REDIR; 1696 break; 1697 1698 case XDP_TX: 1699 rxq->stats[RX_XDP_TX]++; 1700 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync); 1701 if (unlikely(err)) { 1702 rxq->stats[RX_XDP_TX_ERRORS]++; 1703 goto xdp_err; 1704 } 1705 1706 ret = FEC_ENET_XDP_TX; 1707 break; 1708 1709 default: 1710 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1711 fallthrough; 1712 1713 case XDP_ABORTED: 1714 fallthrough; /* handle aborts by dropping packet */ 1715 1716 case XDP_DROP: 1717 rxq->stats[RX_XDP_DROP]++; 1718 xdp_err: 1719 ret = FEC_ENET_XDP_CONSUMED; 1720 page = virt_to_head_page(xdp->data); 1721 page_pool_put_page(rxq->page_pool, page, sync, true); 1722 if (act != XDP_DROP) 1723 trace_xdp_exception(fep->netdev, prog, act); 1724 break; 1725 } 1726 1727 return ret; 1728 } 1729 1730 static void fec_enet_rx_vlan(const struct net_device *ndev, struct sk_buff *skb) 1731 { 1732 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { 1733 const struct vlan_ethhdr *vlan_header = skb_vlan_eth_hdr(skb); 1734 const u16 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1735 1736 /* Push and remove the vlan tag */ 1737 1738 memmove(skb->data + VLAN_HLEN, skb->data, ETH_ALEN * 2); 1739 skb_pull(skb, VLAN_HLEN); 1740 __vlan_hwaccel_put_tag(skb, 1741 htons(ETH_P_8021Q), 1742 vlan_tag); 1743 } 1744 } 1745 1746 /* During a receive, the bd_rx.cur points to the current incoming buffer. 1747 * When we update through the ring, if the next incoming buffer has 1748 * not been given to the system, we just set the empty indicator, 1749 * effectively tossing the packet. 1750 */ 1751 static int 1752 fec_enet_rx_queue(struct net_device *ndev, u16 queue_id, int budget) 1753 { 1754 struct fec_enet_private *fep = netdev_priv(ndev); 1755 struct fec_enet_priv_rx_q *rxq; 1756 struct bufdesc *bdp; 1757 unsigned short status; 1758 struct sk_buff *skb; 1759 ushort pkt_len; 1760 int pkt_received = 0; 1761 struct bufdesc_ex *ebdp = NULL; 1762 int index = 0; 1763 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1764 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1765 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1766 u32 data_start = FEC_ENET_XDP_HEADROOM; 1767 int cpu = smp_processor_id(); 1768 struct xdp_buff xdp; 1769 struct page *page; 1770 __fec32 cbd_bufaddr; 1771 u32 sub_len = 4; 1772 1773 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1774 * FEC_RACC_SHIFT16 is set by default in the probe function. 1775 */ 1776 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1777 data_start += 2; 1778 sub_len += 2; 1779 } 1780 1781 #if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 1782 /* 1783 * Hacky flush of all caches instead of using the DMA API for the TSO 1784 * headers. 1785 */ 1786 flush_cache_all(); 1787 #endif 1788 rxq = fep->rx_queue[queue_id]; 1789 1790 /* First, grab all of the stats for the incoming packet. 1791 * These get messed up if we get called due to a busy condition. 1792 */ 1793 bdp = rxq->bd.cur; 1794 xdp_init_buff(&xdp, PAGE_SIZE << fep->pagepool_order, &rxq->xdp_rxq); 1795 1796 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1797 1798 if (pkt_received >= budget) 1799 break; 1800 pkt_received++; 1801 1802 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1803 1804 /* Check for errors. */ 1805 status ^= BD_ENET_RX_LAST; 1806 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1807 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1808 BD_ENET_RX_CL)) { 1809 ndev->stats.rx_errors++; 1810 if (status & BD_ENET_RX_OV) { 1811 /* FIFO overrun */ 1812 ndev->stats.rx_fifo_errors++; 1813 goto rx_processing_done; 1814 } 1815 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1816 | BD_ENET_RX_LAST)) { 1817 /* Frame too long or too short. */ 1818 ndev->stats.rx_length_errors++; 1819 if (status & BD_ENET_RX_LAST) 1820 netdev_err(ndev, "rcv is not +last\n"); 1821 } 1822 if (status & BD_ENET_RX_CR) /* CRC Error */ 1823 ndev->stats.rx_crc_errors++; 1824 /* Report late collisions as a frame error. */ 1825 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1826 ndev->stats.rx_frame_errors++; 1827 goto rx_processing_done; 1828 } 1829 1830 /* Process the incoming frame. */ 1831 ndev->stats.rx_packets++; 1832 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1833 ndev->stats.rx_bytes += pkt_len; 1834 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1835 ndev->stats.rx_bytes -= 2; 1836 1837 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1838 page = rxq->rx_buf[index]; 1839 cbd_bufaddr = bdp->cbd_bufaddr; 1840 if (fec_enet_update_cbd(rxq, bdp, index)) { 1841 ndev->stats.rx_dropped++; 1842 goto rx_processing_done; 1843 } 1844 1845 dma_sync_single_for_cpu(&fep->pdev->dev, 1846 fec32_to_cpu(cbd_bufaddr), 1847 pkt_len, 1848 DMA_FROM_DEVICE); 1849 prefetch(page_address(page)); 1850 1851 if (xdp_prog) { 1852 xdp_buff_clear_frags_flag(&xdp); 1853 /* subtract 16bit shift and FCS */ 1854 xdp_prepare_buff(&xdp, page_address(page), 1855 data_start, pkt_len - sub_len, false); 1856 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu); 1857 xdp_result |= ret; 1858 if (ret != FEC_ENET_XDP_PASS) 1859 goto rx_processing_done; 1860 } 1861 1862 /* The packet length includes FCS, but we don't want to 1863 * include that when passing upstream as it messes up 1864 * bridging applications. 1865 */ 1866 skb = build_skb(page_address(page), 1867 PAGE_SIZE << fep->pagepool_order); 1868 if (unlikely(!skb)) { 1869 page_pool_recycle_direct(rxq->page_pool, page); 1870 ndev->stats.rx_dropped++; 1871 1872 netdev_err_once(ndev, "build_skb failed!\n"); 1873 goto rx_processing_done; 1874 } 1875 1876 skb_reserve(skb, data_start); 1877 skb_put(skb, pkt_len - sub_len); 1878 skb_mark_for_recycle(skb); 1879 1880 if (unlikely(need_swap)) { 1881 u8 *data; 1882 1883 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1884 swap_buffer(data, pkt_len); 1885 } 1886 1887 /* Extract the enhanced buffer descriptor */ 1888 ebdp = NULL; 1889 if (fep->bufdesc_ex) 1890 ebdp = (struct bufdesc_ex *)bdp; 1891 1892 /* If this is a VLAN packet remove the VLAN Tag */ 1893 if (fep->bufdesc_ex && 1894 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) 1895 fec_enet_rx_vlan(ndev, skb); 1896 1897 skb->protocol = eth_type_trans(skb, ndev); 1898 1899 /* Get receive timestamp from the skb */ 1900 if (fep->hwts_rx_en && fep->bufdesc_ex) 1901 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1902 skb_hwtstamps(skb)); 1903 1904 if (fep->bufdesc_ex && 1905 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1906 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1907 /* don't check it */ 1908 skb->ip_summed = CHECKSUM_UNNECESSARY; 1909 } else { 1910 skb_checksum_none_assert(skb); 1911 } 1912 } 1913 1914 skb_record_rx_queue(skb, queue_id); 1915 napi_gro_receive(&fep->napi, skb); 1916 1917 rx_processing_done: 1918 /* Clear the status flags for this buffer */ 1919 status &= ~BD_ENET_RX_STATS; 1920 1921 /* Mark the buffer empty */ 1922 status |= BD_ENET_RX_EMPTY; 1923 1924 if (fep->bufdesc_ex) { 1925 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1926 1927 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1928 ebdp->cbd_prot = 0; 1929 ebdp->cbd_bdu = 0; 1930 } 1931 /* Make sure the updates to rest of the descriptor are 1932 * performed before transferring ownership. 1933 */ 1934 wmb(); 1935 bdp->cbd_sc = cpu_to_fec16(status); 1936 1937 /* Update BD pointer to next entry */ 1938 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1939 1940 /* Doing this here will keep the FEC running while we process 1941 * incoming frames. On a heavily loaded network, we should be 1942 * able to keep up at the expense of system resources. 1943 */ 1944 writel(0, rxq->bd.reg_desc_active); 1945 } 1946 rxq->bd.cur = bdp; 1947 1948 if (xdp_result & FEC_ENET_XDP_REDIR) 1949 xdp_do_flush(); 1950 1951 return pkt_received; 1952 } 1953 1954 static int fec_enet_rx(struct net_device *ndev, int budget) 1955 { 1956 struct fec_enet_private *fep = netdev_priv(ndev); 1957 int i, done = 0; 1958 1959 /* Make sure that AVB queues are processed first. */ 1960 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1961 done += fec_enet_rx_queue(ndev, i, budget - done); 1962 1963 return done; 1964 } 1965 1966 static bool fec_enet_collect_events(struct fec_enet_private *fep) 1967 { 1968 uint int_events; 1969 1970 int_events = readl(fep->hwp + FEC_IEVENT); 1971 1972 /* Don't clear MDIO events, we poll for those */ 1973 int_events &= ~FEC_ENET_MII; 1974 1975 writel(int_events, fep->hwp + FEC_IEVENT); 1976 1977 return int_events != 0; 1978 } 1979 1980 static irqreturn_t 1981 fec_enet_interrupt(int irq, void *dev_id) 1982 { 1983 struct net_device *ndev = dev_id; 1984 struct fec_enet_private *fep = netdev_priv(ndev); 1985 irqreturn_t ret = IRQ_NONE; 1986 1987 if (fec_enet_collect_events(fep) && fep->link) { 1988 ret = IRQ_HANDLED; 1989 1990 if (napi_schedule_prep(&fep->napi)) { 1991 /* Disable interrupts */ 1992 writel(0, fep->hwp + FEC_IMASK); 1993 __napi_schedule(&fep->napi); 1994 } 1995 } 1996 1997 return ret; 1998 } 1999 2000 static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 2001 { 2002 struct net_device *ndev = napi->dev; 2003 struct fec_enet_private *fep = netdev_priv(ndev); 2004 int done = 0; 2005 2006 do { 2007 done += fec_enet_rx(ndev, budget - done); 2008 fec_enet_tx(ndev, budget); 2009 } while ((done < budget) && fec_enet_collect_events(fep)); 2010 2011 if (done < budget) { 2012 napi_complete_done(napi, done); 2013 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 2014 } 2015 2016 return done; 2017 } 2018 2019 /* ------------------------------------------------------------------------- */ 2020 static int fec_get_mac(struct net_device *ndev) 2021 { 2022 struct fec_enet_private *fep = netdev_priv(ndev); 2023 unsigned char *iap, tmpaddr[ETH_ALEN]; 2024 int ret; 2025 2026 /* 2027 * try to get mac address in following order: 2028 * 2029 * 1) module parameter via kernel command line in form 2030 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 2031 */ 2032 iap = macaddr; 2033 2034 /* 2035 * 2) from device tree data 2036 */ 2037 if (!is_valid_ether_addr(iap)) { 2038 struct device_node *np = fep->pdev->dev.of_node; 2039 if (np) { 2040 ret = of_get_mac_address(np, tmpaddr); 2041 if (!ret) 2042 iap = tmpaddr; 2043 else if (ret == -EPROBE_DEFER) 2044 return ret; 2045 } 2046 } 2047 2048 /* 2049 * 3) from flash or fuse (via platform data) 2050 */ 2051 if (!is_valid_ether_addr(iap)) { 2052 #ifdef CONFIG_M5272 2053 if (FEC_FLASHMAC) 2054 iap = (unsigned char *)FEC_FLASHMAC; 2055 #else 2056 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 2057 2058 if (pdata) 2059 iap = (unsigned char *)&pdata->mac; 2060 #endif 2061 } 2062 2063 /* 2064 * 4) FEC mac registers set by bootloader 2065 */ 2066 if (!is_valid_ether_addr(iap)) { 2067 *((__be32 *) &tmpaddr[0]) = 2068 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 2069 *((__be16 *) &tmpaddr[4]) = 2070 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 2071 iap = &tmpaddr[0]; 2072 } 2073 2074 /* 2075 * 5) random mac address 2076 */ 2077 if (!is_valid_ether_addr(iap)) { 2078 /* Report it and use a random ethernet address instead */ 2079 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 2080 eth_hw_addr_random(ndev); 2081 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 2082 ndev->dev_addr); 2083 return 0; 2084 } 2085 2086 /* Adjust MAC if using macaddr */ 2087 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 2088 2089 return 0; 2090 } 2091 2092 /* ------------------------------------------------------------------------- */ 2093 2094 /* 2095 * Phy section 2096 */ 2097 2098 /* LPI Sleep Ts count base on tx clk (clk_ref). 2099 * The lpi sleep cnt value = X us / (cycle_ns). 2100 */ 2101 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2102 { 2103 struct fec_enet_private *fep = netdev_priv(ndev); 2104 2105 return us * (fep->clk_ref_rate / 1000) / 1000; 2106 } 2107 2108 static int fec_enet_eee_mode_set(struct net_device *ndev, u32 lpi_timer, 2109 bool enable) 2110 { 2111 struct fec_enet_private *fep = netdev_priv(ndev); 2112 unsigned int sleep_cycle, wake_cycle; 2113 2114 if (enable) { 2115 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, lpi_timer); 2116 wake_cycle = sleep_cycle; 2117 } else { 2118 sleep_cycle = 0; 2119 wake_cycle = 0; 2120 } 2121 2122 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2123 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2124 2125 return 0; 2126 } 2127 2128 static void fec_enet_adjust_link(struct net_device *ndev) 2129 { 2130 struct fec_enet_private *fep = netdev_priv(ndev); 2131 struct phy_device *phy_dev = ndev->phydev; 2132 int status_change = 0; 2133 2134 /* 2135 * If the netdev is down, or is going down, we're not interested 2136 * in link state events, so just mark our idea of the link as down 2137 * and ignore the event. 2138 */ 2139 if (!netif_running(ndev) || !netif_device_present(ndev)) { 2140 fep->link = 0; 2141 } else if (phy_dev->link) { 2142 if (!fep->link) { 2143 fep->link = phy_dev->link; 2144 status_change = 1; 2145 } 2146 2147 if (fep->full_duplex != phy_dev->duplex) { 2148 fep->full_duplex = phy_dev->duplex; 2149 status_change = 1; 2150 } 2151 2152 if (phy_dev->speed != fep->speed) { 2153 fep->speed = phy_dev->speed; 2154 status_change = 1; 2155 } 2156 2157 /* if any of the above changed restart the FEC */ 2158 if (status_change) { 2159 netif_stop_queue(ndev); 2160 napi_disable(&fep->napi); 2161 netif_tx_lock_bh(ndev); 2162 fec_restart(ndev); 2163 netif_tx_wake_all_queues(ndev); 2164 netif_tx_unlock_bh(ndev); 2165 napi_enable(&fep->napi); 2166 } 2167 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2168 fec_enet_eee_mode_set(ndev, 2169 phy_dev->eee_cfg.tx_lpi_timer, 2170 phy_dev->enable_tx_lpi); 2171 } else { 2172 if (fep->link) { 2173 netif_stop_queue(ndev); 2174 napi_disable(&fep->napi); 2175 netif_tx_lock_bh(ndev); 2176 fec_stop(ndev); 2177 netif_tx_unlock_bh(ndev); 2178 napi_enable(&fep->napi); 2179 fep->link = phy_dev->link; 2180 status_change = 1; 2181 } 2182 } 2183 2184 if (status_change) 2185 phy_print_status(phy_dev); 2186 } 2187 2188 static int fec_enet_mdio_wait(struct fec_enet_private *fep) 2189 { 2190 uint ievent; 2191 int ret; 2192 2193 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2194 ievent & FEC_ENET_MII, 2, 30000); 2195 2196 if (!ret) 2197 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2198 2199 return ret; 2200 } 2201 2202 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2203 { 2204 struct fec_enet_private *fep = bus->priv; 2205 struct device *dev = &fep->pdev->dev; 2206 int ret = 0, frame_start, frame_addr, frame_op; 2207 2208 ret = pm_runtime_resume_and_get(dev); 2209 if (ret < 0) 2210 return ret; 2211 2212 /* C22 read */ 2213 frame_op = FEC_MMFR_OP_READ; 2214 frame_start = FEC_MMFR_ST; 2215 frame_addr = regnum; 2216 2217 /* start a read op */ 2218 writel(frame_start | frame_op | 2219 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2220 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2221 2222 /* wait for end of transfer */ 2223 ret = fec_enet_mdio_wait(fep); 2224 if (ret) { 2225 netdev_err(fep->netdev, "MDIO read timeout\n"); 2226 goto out; 2227 } 2228 2229 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2230 2231 out: 2232 pm_runtime_put_autosuspend(dev); 2233 2234 return ret; 2235 } 2236 2237 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2238 int devad, int regnum) 2239 { 2240 struct fec_enet_private *fep = bus->priv; 2241 struct device *dev = &fep->pdev->dev; 2242 int ret = 0, frame_start, frame_op; 2243 2244 ret = pm_runtime_resume_and_get(dev); 2245 if (ret < 0) 2246 return ret; 2247 2248 frame_start = FEC_MMFR_ST_C45; 2249 2250 /* write address */ 2251 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2252 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2253 FEC_MMFR_TA | (regnum & 0xFFFF), 2254 fep->hwp + FEC_MII_DATA); 2255 2256 /* wait for end of transfer */ 2257 ret = fec_enet_mdio_wait(fep); 2258 if (ret) { 2259 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2260 goto out; 2261 } 2262 2263 frame_op = FEC_MMFR_OP_READ_C45; 2264 2265 /* start a read op */ 2266 writel(frame_start | frame_op | 2267 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2268 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2269 2270 /* wait for end of transfer */ 2271 ret = fec_enet_mdio_wait(fep); 2272 if (ret) { 2273 netdev_err(fep->netdev, "MDIO read timeout\n"); 2274 goto out; 2275 } 2276 2277 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2278 2279 out: 2280 pm_runtime_put_autosuspend(dev); 2281 2282 return ret; 2283 } 2284 2285 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2286 u16 value) 2287 { 2288 struct fec_enet_private *fep = bus->priv; 2289 struct device *dev = &fep->pdev->dev; 2290 int ret, frame_start, frame_addr; 2291 2292 ret = pm_runtime_resume_and_get(dev); 2293 if (ret < 0) 2294 return ret; 2295 2296 /* C22 write */ 2297 frame_start = FEC_MMFR_ST; 2298 frame_addr = regnum; 2299 2300 /* start a write op */ 2301 writel(frame_start | FEC_MMFR_OP_WRITE | 2302 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2303 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2304 fep->hwp + FEC_MII_DATA); 2305 2306 /* wait for end of transfer */ 2307 ret = fec_enet_mdio_wait(fep); 2308 if (ret) 2309 netdev_err(fep->netdev, "MDIO write timeout\n"); 2310 2311 pm_runtime_put_autosuspend(dev); 2312 2313 return ret; 2314 } 2315 2316 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2317 int devad, int regnum, u16 value) 2318 { 2319 struct fec_enet_private *fep = bus->priv; 2320 struct device *dev = &fep->pdev->dev; 2321 int ret, frame_start; 2322 2323 ret = pm_runtime_resume_and_get(dev); 2324 if (ret < 0) 2325 return ret; 2326 2327 frame_start = FEC_MMFR_ST_C45; 2328 2329 /* write address */ 2330 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2331 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2332 FEC_MMFR_TA | (regnum & 0xFFFF), 2333 fep->hwp + FEC_MII_DATA); 2334 2335 /* wait for end of transfer */ 2336 ret = fec_enet_mdio_wait(fep); 2337 if (ret) { 2338 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2339 goto out; 2340 } 2341 2342 /* start a write op */ 2343 writel(frame_start | FEC_MMFR_OP_WRITE | 2344 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2345 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2346 fep->hwp + FEC_MII_DATA); 2347 2348 /* wait for end of transfer */ 2349 ret = fec_enet_mdio_wait(fep); 2350 if (ret) 2351 netdev_err(fep->netdev, "MDIO write timeout\n"); 2352 2353 out: 2354 pm_runtime_put_autosuspend(dev); 2355 2356 return ret; 2357 } 2358 2359 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2360 { 2361 struct fec_enet_private *fep = netdev_priv(ndev); 2362 struct phy_device *phy_dev = ndev->phydev; 2363 2364 if (phy_dev) { 2365 phy_reset_after_clk_enable(phy_dev); 2366 } else if (fep->phy_node) { 2367 /* 2368 * If the PHY still is not bound to the MAC, but there is 2369 * OF PHY node and a matching PHY device instance already, 2370 * use the OF PHY node to obtain the PHY device instance, 2371 * and then use that PHY device instance when triggering 2372 * the PHY reset. 2373 */ 2374 phy_dev = of_phy_find_device(fep->phy_node); 2375 phy_reset_after_clk_enable(phy_dev); 2376 if (phy_dev) 2377 put_device(&phy_dev->mdio.dev); 2378 } 2379 } 2380 2381 static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2382 { 2383 struct fec_enet_private *fep = netdev_priv(ndev); 2384 int ret; 2385 2386 if (enable) { 2387 ret = clk_prepare_enable(fep->clk_enet_out); 2388 if (ret) 2389 return ret; 2390 2391 if (fep->clk_ptp) { 2392 mutex_lock(&fep->ptp_clk_mutex); 2393 ret = clk_prepare_enable(fep->clk_ptp); 2394 if (ret) { 2395 mutex_unlock(&fep->ptp_clk_mutex); 2396 goto failed_clk_ptp; 2397 } else { 2398 fep->ptp_clk_on = true; 2399 } 2400 mutex_unlock(&fep->ptp_clk_mutex); 2401 } 2402 2403 ret = clk_prepare_enable(fep->clk_ref); 2404 if (ret) 2405 goto failed_clk_ref; 2406 2407 ret = clk_prepare_enable(fep->clk_2x_txclk); 2408 if (ret) 2409 goto failed_clk_2x_txclk; 2410 2411 fec_enet_phy_reset_after_clk_enable(ndev); 2412 } else { 2413 clk_disable_unprepare(fep->clk_enet_out); 2414 if (fep->clk_ptp) { 2415 mutex_lock(&fep->ptp_clk_mutex); 2416 clk_disable_unprepare(fep->clk_ptp); 2417 fep->ptp_clk_on = false; 2418 mutex_unlock(&fep->ptp_clk_mutex); 2419 } 2420 clk_disable_unprepare(fep->clk_ref); 2421 clk_disable_unprepare(fep->clk_2x_txclk); 2422 } 2423 2424 return 0; 2425 2426 failed_clk_2x_txclk: 2427 if (fep->clk_ref) 2428 clk_disable_unprepare(fep->clk_ref); 2429 failed_clk_ref: 2430 if (fep->clk_ptp) { 2431 mutex_lock(&fep->ptp_clk_mutex); 2432 clk_disable_unprepare(fep->clk_ptp); 2433 fep->ptp_clk_on = false; 2434 mutex_unlock(&fep->ptp_clk_mutex); 2435 } 2436 failed_clk_ptp: 2437 clk_disable_unprepare(fep->clk_enet_out); 2438 2439 return ret; 2440 } 2441 2442 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2443 struct device_node *np) 2444 { 2445 u32 rgmii_tx_delay, rgmii_rx_delay; 2446 2447 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2448 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2449 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2450 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2451 return -EINVAL; 2452 } else if (rgmii_tx_delay == 2000) { 2453 fep->rgmii_txc_dly = true; 2454 } 2455 } 2456 2457 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2458 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2459 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2460 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2461 return -EINVAL; 2462 } else if (rgmii_rx_delay == 2000) { 2463 fep->rgmii_rxc_dly = true; 2464 } 2465 } 2466 2467 return 0; 2468 } 2469 2470 static int fec_enet_mii_probe(struct net_device *ndev) 2471 { 2472 struct fec_enet_private *fep = netdev_priv(ndev); 2473 struct phy_device *phy_dev; 2474 int ret; 2475 2476 if (fep->phy_node) { 2477 phy_dev = of_phy_connect(ndev, fep->phy_node, 2478 &fec_enet_adjust_link, 0, 2479 fep->phy_interface); 2480 if (!phy_dev) { 2481 netdev_err(ndev, "Unable to connect to phy\n"); 2482 return -ENODEV; 2483 } 2484 } else { 2485 /* check for attached phy */ 2486 phy_dev = phy_find_first(fep->mii_bus); 2487 if (fep->dev_id && phy_dev) 2488 phy_dev = phy_find_next(fep->mii_bus, phy_dev); 2489 2490 if (!phy_dev) { 2491 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2492 phy_dev = fixed_phy_register_100fd(); 2493 if (IS_ERR(phy_dev)) { 2494 netdev_err(ndev, "could not register fixed PHY\n"); 2495 return PTR_ERR(phy_dev); 2496 } 2497 } 2498 2499 ret = phy_connect_direct(ndev, phy_dev, &fec_enet_adjust_link, 2500 fep->phy_interface); 2501 if (ret) { 2502 if (phy_is_pseudo_fixed_link(phy_dev)) 2503 fixed_phy_unregister(phy_dev); 2504 netdev_err(ndev, "could not attach to PHY\n"); 2505 return ret; 2506 } 2507 2508 } 2509 2510 /* mask with MAC supported features */ 2511 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2512 phy_set_max_speed(phy_dev, 1000); 2513 phy_remove_link_mode(phy_dev, 2514 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2515 phy_support_sym_pause(phy_dev); 2516 } 2517 else 2518 phy_set_max_speed(phy_dev, 100); 2519 2520 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2521 phy_support_eee(phy_dev); 2522 2523 fep->link = 0; 2524 fep->full_duplex = 0; 2525 2526 phy_attached_info(phy_dev); 2527 2528 return 0; 2529 } 2530 2531 static int fec_enet_mii_init(struct platform_device *pdev) 2532 { 2533 static struct mii_bus *fec0_mii_bus; 2534 struct net_device *ndev = platform_get_drvdata(pdev); 2535 struct fec_enet_private *fep = netdev_priv(ndev); 2536 bool suppress_preamble = false; 2537 struct phy_device *phydev; 2538 struct device_node *node; 2539 int err = -ENXIO; 2540 u32 mii_speed, holdtime; 2541 u32 bus_freq; 2542 2543 /* 2544 * The i.MX28 dual fec interfaces are not equal. 2545 * Here are the differences: 2546 * 2547 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2548 * - fec0 acts as the 1588 time master while fec1 is slave 2549 * - external phys can only be configured by fec0 2550 * 2551 * That is to say fec1 can not work independently. It only works 2552 * when fec0 is working. The reason behind this design is that the 2553 * second interface is added primarily for Switch mode. 2554 * 2555 * Because of the last point above, both phys are attached on fec0 2556 * mdio interface in board design, and need to be configured by 2557 * fec0 mii_bus. 2558 */ 2559 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2560 /* fec1 uses fec0 mii_bus */ 2561 if (mii_cnt && fec0_mii_bus) { 2562 fep->mii_bus = fec0_mii_bus; 2563 mii_cnt++; 2564 return 0; 2565 } 2566 return -ENOENT; 2567 } 2568 2569 bus_freq = 2500000; /* 2.5MHz by default */ 2570 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2571 if (node) { 2572 of_property_read_u32(node, "clock-frequency", &bus_freq); 2573 suppress_preamble = of_property_read_bool(node, 2574 "suppress-preamble"); 2575 } 2576 2577 /* 2578 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2579 * 2580 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2581 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2582 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2583 * document. 2584 */ 2585 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2586 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2587 mii_speed--; 2588 if (mii_speed > 63) { 2589 dev_err(&pdev->dev, 2590 "fec clock (%lu) too fast to get right mii speed\n", 2591 clk_get_rate(fep->clk_ipg)); 2592 err = -EINVAL; 2593 goto err_out; 2594 } 2595 2596 /* 2597 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2598 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2599 * versions are RAZ there, so just ignore the difference and write the 2600 * register always. 2601 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2602 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2603 * output. 2604 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2605 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2606 * holdtime cannot result in a value greater than 3. 2607 */ 2608 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2609 2610 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2611 2612 if (suppress_preamble) 2613 fep->phy_speed |= BIT(7); 2614 2615 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2616 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2617 * MII event generation condition: 2618 * - writing MSCR: 2619 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2620 * mscr_reg_data_in[7:0] != 0 2621 * - writing MMFR: 2622 * - mscr[7:0]_not_zero 2623 */ 2624 writel(0, fep->hwp + FEC_MII_DATA); 2625 } 2626 2627 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2628 2629 /* Clear any pending transaction complete indication */ 2630 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2631 2632 fep->mii_bus = mdiobus_alloc(); 2633 if (fep->mii_bus == NULL) { 2634 err = -ENOMEM; 2635 goto err_out; 2636 } 2637 2638 fep->mii_bus->name = "fec_enet_mii_bus"; 2639 fep->mii_bus->read = fec_enet_mdio_read_c22; 2640 fep->mii_bus->write = fec_enet_mdio_write_c22; 2641 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2642 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2643 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2644 } 2645 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2646 pdev->name, fep->dev_id + 1); 2647 fep->mii_bus->priv = fep; 2648 fep->mii_bus->parent = &pdev->dev; 2649 2650 err = of_mdiobus_register(fep->mii_bus, node); 2651 if (err) 2652 goto err_out_free_mdiobus; 2653 of_node_put(node); 2654 2655 /* find all the PHY devices on the bus and set mac_managed_pm to true */ 2656 mdiobus_for_each_phy(fep->mii_bus, phydev) 2657 phydev->mac_managed_pm = true; 2658 2659 mii_cnt++; 2660 2661 /* save fec0 mii_bus */ 2662 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2663 fec0_mii_bus = fep->mii_bus; 2664 2665 return 0; 2666 2667 err_out_free_mdiobus: 2668 mdiobus_free(fep->mii_bus); 2669 err_out: 2670 of_node_put(node); 2671 return err; 2672 } 2673 2674 static void fec_enet_mii_remove(struct fec_enet_private *fep) 2675 { 2676 if (--mii_cnt == 0) { 2677 mdiobus_unregister(fep->mii_bus); 2678 mdiobus_free(fep->mii_bus); 2679 } 2680 } 2681 2682 static void fec_enet_get_drvinfo(struct net_device *ndev, 2683 struct ethtool_drvinfo *info) 2684 { 2685 struct fec_enet_private *fep = netdev_priv(ndev); 2686 2687 strscpy(info->driver, fep->pdev->dev.driver->name, 2688 sizeof(info->driver)); 2689 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2690 } 2691 2692 static int fec_enet_get_regs_len(struct net_device *ndev) 2693 { 2694 struct fec_enet_private *fep = netdev_priv(ndev); 2695 struct resource *r; 2696 int s = 0; 2697 2698 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2699 if (r) 2700 s = resource_size(r); 2701 2702 return s; 2703 } 2704 2705 /* List of registers that can be safety be read to dump them with ethtool */ 2706 #if !defined(CONFIG_M5272) || defined(CONFIG_COMPILE_TEST) 2707 static __u32 fec_enet_register_version = 2; 2708 static u32 fec_enet_register_offset[] = { 2709 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2710 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2711 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2712 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2713 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2714 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2715 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2716 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2717 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2718 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2719 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2720 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2721 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2722 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2723 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2724 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2725 RMON_T_P_GTE2048, RMON_T_OCTETS, 2726 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2727 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2728 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2729 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2730 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2731 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2732 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2733 RMON_R_P_GTE2048, RMON_R_OCTETS, 2734 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2735 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2736 }; 2737 /* for i.MX6ul */ 2738 static u32 fec_enet_register_offset_6ul[] = { 2739 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2740 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2741 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2742 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2743 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2744 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2745 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2746 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2747 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2748 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2749 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2750 RMON_T_P_GTE2048, RMON_T_OCTETS, 2751 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2752 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2753 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2754 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2755 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2756 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2757 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2758 RMON_R_P_GTE2048, RMON_R_OCTETS, 2759 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2760 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2761 }; 2762 #else 2763 static __u32 fec_enet_register_version = 1; 2764 static u32 fec_enet_register_offset[] = { 2765 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2766 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2767 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2768 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2769 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2770 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2771 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2772 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2773 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2774 }; 2775 #endif 2776 2777 static void fec_enet_get_regs(struct net_device *ndev, 2778 struct ethtool_regs *regs, void *regbuf) 2779 { 2780 u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2781 struct fec_enet_private *fep = netdev_priv(ndev); 2782 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2783 u32 *reg_list = fec_enet_register_offset; 2784 struct device *dev = &fep->pdev->dev; 2785 u32 *buf = (u32 *)regbuf; 2786 u32 i, off; 2787 int ret; 2788 2789 #if !defined(CONFIG_M5272) || defined(CONFIG_COMPILE_TEST) 2790 if (of_machine_is_compatible("fsl,imx6ul")) { 2791 reg_list = fec_enet_register_offset_6ul; 2792 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2793 } 2794 #endif 2795 2796 ret = pm_runtime_resume_and_get(dev); 2797 if (ret < 0) 2798 return; 2799 2800 regs->version = fec_enet_register_version; 2801 2802 memset(buf, 0, regs->len); 2803 2804 for (i = 0; i < reg_cnt; i++) { 2805 off = reg_list[i]; 2806 2807 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2808 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2809 continue; 2810 2811 off >>= 2; 2812 buf[off] = readl(&theregs[off]); 2813 } 2814 2815 pm_runtime_put_autosuspend(dev); 2816 } 2817 2818 static int fec_enet_get_ts_info(struct net_device *ndev, 2819 struct kernel_ethtool_ts_info *info) 2820 { 2821 struct fec_enet_private *fep = netdev_priv(ndev); 2822 2823 if (fep->bufdesc_ex) { 2824 2825 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2826 SOF_TIMESTAMPING_TX_HARDWARE | 2827 SOF_TIMESTAMPING_RX_HARDWARE | 2828 SOF_TIMESTAMPING_RAW_HARDWARE; 2829 if (fep->ptp_clock) 2830 info->phc_index = ptp_clock_index(fep->ptp_clock); 2831 2832 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2833 (1 << HWTSTAMP_TX_ON); 2834 2835 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2836 (1 << HWTSTAMP_FILTER_ALL); 2837 return 0; 2838 } else { 2839 return ethtool_op_get_ts_info(ndev, info); 2840 } 2841 } 2842 2843 #if !defined(CONFIG_M5272) 2844 2845 static void fec_enet_get_pauseparam(struct net_device *ndev, 2846 struct ethtool_pauseparam *pause) 2847 { 2848 struct fec_enet_private *fep = netdev_priv(ndev); 2849 2850 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2851 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2852 pause->rx_pause = pause->tx_pause; 2853 } 2854 2855 static int fec_enet_set_pauseparam(struct net_device *ndev, 2856 struct ethtool_pauseparam *pause) 2857 { 2858 struct fec_enet_private *fep = netdev_priv(ndev); 2859 2860 if (!ndev->phydev) 2861 return -ENODEV; 2862 2863 if (pause->tx_pause != pause->rx_pause) { 2864 netdev_info(ndev, 2865 "hardware only support enable/disable both tx and rx"); 2866 return -EINVAL; 2867 } 2868 2869 fep->pause_flag = 0; 2870 2871 /* tx pause must be same as rx pause */ 2872 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2873 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2874 2875 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2876 pause->autoneg); 2877 2878 if (pause->autoneg) { 2879 if (netif_running(ndev)) 2880 fec_stop(ndev); 2881 phy_start_aneg(ndev->phydev); 2882 } 2883 if (netif_running(ndev)) { 2884 napi_disable(&fep->napi); 2885 netif_tx_lock_bh(ndev); 2886 fec_restart(ndev); 2887 netif_tx_wake_all_queues(ndev); 2888 netif_tx_unlock_bh(ndev); 2889 napi_enable(&fep->napi); 2890 } 2891 2892 return 0; 2893 } 2894 2895 static const struct fec_stat { 2896 char name[ETH_GSTRING_LEN]; 2897 u16 offset; 2898 } fec_stats[] = { 2899 /* RMON TX */ 2900 { "tx_dropped", RMON_T_DROP }, 2901 { "tx_packets", RMON_T_PACKETS }, 2902 { "tx_broadcast", RMON_T_BC_PKT }, 2903 { "tx_multicast", RMON_T_MC_PKT }, 2904 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2905 { "tx_undersize", RMON_T_UNDERSIZE }, 2906 { "tx_oversize", RMON_T_OVERSIZE }, 2907 { "tx_fragment", RMON_T_FRAG }, 2908 { "tx_jabber", RMON_T_JAB }, 2909 { "tx_collision", RMON_T_COL }, 2910 { "tx_64byte", RMON_T_P64 }, 2911 { "tx_65to127byte", RMON_T_P65TO127 }, 2912 { "tx_128to255byte", RMON_T_P128TO255 }, 2913 { "tx_256to511byte", RMON_T_P256TO511 }, 2914 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2915 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2916 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2917 { "tx_octets", RMON_T_OCTETS }, 2918 2919 /* IEEE TX */ 2920 { "IEEE_tx_drop", IEEE_T_DROP }, 2921 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2922 { "IEEE_tx_1col", IEEE_T_1COL }, 2923 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2924 { "IEEE_tx_def", IEEE_T_DEF }, 2925 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2926 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2927 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2928 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2929 { "IEEE_tx_sqe", IEEE_T_SQE }, 2930 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2931 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2932 2933 /* RMON RX */ 2934 { "rx_packets", RMON_R_PACKETS }, 2935 { "rx_broadcast", RMON_R_BC_PKT }, 2936 { "rx_multicast", RMON_R_MC_PKT }, 2937 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2938 { "rx_undersize", RMON_R_UNDERSIZE }, 2939 { "rx_oversize", RMON_R_OVERSIZE }, 2940 { "rx_fragment", RMON_R_FRAG }, 2941 { "rx_jabber", RMON_R_JAB }, 2942 { "rx_64byte", RMON_R_P64 }, 2943 { "rx_65to127byte", RMON_R_P65TO127 }, 2944 { "rx_128to255byte", RMON_R_P128TO255 }, 2945 { "rx_256to511byte", RMON_R_P256TO511 }, 2946 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2947 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2948 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2949 { "rx_octets", RMON_R_OCTETS }, 2950 2951 /* IEEE RX */ 2952 { "IEEE_rx_drop", IEEE_R_DROP }, 2953 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2954 { "IEEE_rx_crc", IEEE_R_CRC }, 2955 { "IEEE_rx_align", IEEE_R_ALIGN }, 2956 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2957 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2958 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2959 }; 2960 2961 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2962 2963 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2964 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2965 "rx_xdp_pass", /* RX_XDP_PASS, */ 2966 "rx_xdp_drop", /* RX_XDP_DROP, */ 2967 "rx_xdp_tx", /* RX_XDP_TX, */ 2968 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2969 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2970 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2971 }; 2972 2973 static void fec_enet_update_ethtool_stats(struct net_device *dev) 2974 { 2975 struct fec_enet_private *fep = netdev_priv(dev); 2976 int i; 2977 2978 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2979 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2980 } 2981 2982 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 2983 { 2984 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 2985 struct fec_enet_priv_rx_q *rxq; 2986 int i, j; 2987 2988 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2989 rxq = fep->rx_queue[i]; 2990 2991 for (j = 0; j < XDP_STATS_TOTAL; j++) 2992 xdp_stats[j] += rxq->stats[j]; 2993 } 2994 2995 memcpy(data, xdp_stats, sizeof(xdp_stats)); 2996 } 2997 2998 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 2999 { 3000 #ifdef CONFIG_PAGE_POOL_STATS 3001 struct page_pool_stats stats = {}; 3002 struct fec_enet_priv_rx_q *rxq; 3003 int i; 3004 3005 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3006 rxq = fep->rx_queue[i]; 3007 3008 if (!rxq->page_pool) 3009 continue; 3010 3011 page_pool_get_stats(rxq->page_pool, &stats); 3012 } 3013 3014 page_pool_ethtool_stats_get(data, &stats); 3015 #endif 3016 } 3017 3018 static void fec_enet_get_ethtool_stats(struct net_device *dev, 3019 struct ethtool_stats *stats, u64 *data) 3020 { 3021 struct fec_enet_private *fep = netdev_priv(dev); 3022 3023 if (netif_running(dev)) 3024 fec_enet_update_ethtool_stats(dev); 3025 3026 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 3027 data += FEC_STATS_SIZE / sizeof(u64); 3028 3029 fec_enet_get_xdp_stats(fep, data); 3030 data += XDP_STATS_TOTAL; 3031 3032 fec_enet_page_pool_stats(fep, data); 3033 } 3034 3035 static void fec_enet_get_strings(struct net_device *netdev, 3036 u32 stringset, u8 *data) 3037 { 3038 int i; 3039 switch (stringset) { 3040 case ETH_SS_STATS: 3041 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 3042 ethtool_puts(&data, fec_stats[i].name); 3043 } 3044 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 3045 ethtool_puts(&data, fec_xdp_stat_strs[i]); 3046 } 3047 page_pool_ethtool_stats_get_strings(data); 3048 3049 break; 3050 case ETH_SS_TEST: 3051 net_selftest_get_strings(data); 3052 break; 3053 } 3054 } 3055 3056 static int fec_enet_get_sset_count(struct net_device *dev, int sset) 3057 { 3058 int count; 3059 3060 switch (sset) { 3061 case ETH_SS_STATS: 3062 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 3063 count += page_pool_ethtool_stats_get_count(); 3064 return count; 3065 3066 case ETH_SS_TEST: 3067 return net_selftest_get_count(); 3068 default: 3069 return -EOPNOTSUPP; 3070 } 3071 } 3072 3073 static void fec_enet_clear_ethtool_stats(struct net_device *dev) 3074 { 3075 struct fec_enet_private *fep = netdev_priv(dev); 3076 struct fec_enet_priv_rx_q *rxq; 3077 int i, j; 3078 3079 /* Disable MIB statistics counters */ 3080 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 3081 3082 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 3083 writel(0, fep->hwp + fec_stats[i].offset); 3084 3085 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3086 rxq = fep->rx_queue[i]; 3087 for (j = 0; j < XDP_STATS_TOTAL; j++) 3088 rxq->stats[j] = 0; 3089 } 3090 3091 /* Don't disable MIB statistics counters */ 3092 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 3093 } 3094 3095 #else /* !defined(CONFIG_M5272) */ 3096 #define FEC_STATS_SIZE 0 3097 static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 3098 { 3099 } 3100 3101 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 3102 { 3103 } 3104 #endif /* !defined(CONFIG_M5272) */ 3105 3106 /* ITR clock source is enet system clock (clk_ahb). 3107 * TCTT unit is cycle_ns * 64 cycle 3108 * So, the ICTT value = X us / (cycle_ns * 64) 3109 */ 3110 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 3111 { 3112 struct fec_enet_private *fep = netdev_priv(ndev); 3113 3114 return us * (fep->itr_clk_rate / 64000) / 1000; 3115 } 3116 3117 /* Set threshold for interrupt coalescing */ 3118 static void fec_enet_itr_coal_set(struct net_device *ndev) 3119 { 3120 struct fec_enet_private *fep = netdev_priv(ndev); 3121 u32 rx_itr = 0, tx_itr = 0; 3122 int rx_ictt, tx_ictt; 3123 3124 rx_ictt = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 3125 tx_ictt = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 3126 3127 if (rx_ictt > 0 && fep->rx_pkts_itr > 1) { 3128 /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ 3129 rx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; 3130 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 3131 rx_itr |= FEC_ITR_ICTT(rx_ictt); 3132 } 3133 3134 if (tx_ictt > 0 && fep->tx_pkts_itr > 1) { 3135 /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ 3136 tx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; 3137 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 3138 tx_itr |= FEC_ITR_ICTT(tx_ictt); 3139 } 3140 3141 writel(tx_itr, fep->hwp + FEC_TXIC0); 3142 writel(rx_itr, fep->hwp + FEC_RXIC0); 3143 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3144 writel(tx_itr, fep->hwp + FEC_TXIC1); 3145 writel(rx_itr, fep->hwp + FEC_RXIC1); 3146 writel(tx_itr, fep->hwp + FEC_TXIC2); 3147 writel(rx_itr, fep->hwp + FEC_RXIC2); 3148 } 3149 } 3150 3151 static int fec_enet_get_coalesce(struct net_device *ndev, 3152 struct ethtool_coalesce *ec, 3153 struct kernel_ethtool_coalesce *kernel_coal, 3154 struct netlink_ext_ack *extack) 3155 { 3156 struct fec_enet_private *fep = netdev_priv(ndev); 3157 3158 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3159 return -EOPNOTSUPP; 3160 3161 ec->rx_coalesce_usecs = fep->rx_time_itr; 3162 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 3163 3164 ec->tx_coalesce_usecs = fep->tx_time_itr; 3165 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 3166 3167 return 0; 3168 } 3169 3170 static int fec_enet_set_coalesce(struct net_device *ndev, 3171 struct ethtool_coalesce *ec, 3172 struct kernel_ethtool_coalesce *kernel_coal, 3173 struct netlink_ext_ack *extack) 3174 { 3175 struct fec_enet_private *fep = netdev_priv(ndev); 3176 struct device *dev = &fep->pdev->dev; 3177 unsigned int cycle; 3178 3179 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3180 return -EOPNOTSUPP; 3181 3182 if (ec->rx_max_coalesced_frames > 255) { 3183 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3184 return -EINVAL; 3185 } 3186 3187 if (ec->tx_max_coalesced_frames > 255) { 3188 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3189 return -EINVAL; 3190 } 3191 3192 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3193 if (cycle > 0xFFFF) { 3194 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3195 return -EINVAL; 3196 } 3197 3198 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3199 if (cycle > 0xFFFF) { 3200 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3201 return -EINVAL; 3202 } 3203 3204 fep->rx_time_itr = ec->rx_coalesce_usecs; 3205 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3206 3207 fep->tx_time_itr = ec->tx_coalesce_usecs; 3208 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3209 3210 fec_enet_itr_coal_set(ndev); 3211 3212 return 0; 3213 } 3214 3215 static int 3216 fec_enet_get_eee(struct net_device *ndev, struct ethtool_keee *edata) 3217 { 3218 struct fec_enet_private *fep = netdev_priv(ndev); 3219 3220 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3221 return -EOPNOTSUPP; 3222 3223 if (!netif_running(ndev)) 3224 return -ENETDOWN; 3225 3226 return phy_ethtool_get_eee(ndev->phydev, edata); 3227 } 3228 3229 static int 3230 fec_enet_set_eee(struct net_device *ndev, struct ethtool_keee *edata) 3231 { 3232 struct fec_enet_private *fep = netdev_priv(ndev); 3233 3234 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3235 return -EOPNOTSUPP; 3236 3237 if (!netif_running(ndev)) 3238 return -ENETDOWN; 3239 3240 return phy_ethtool_set_eee(ndev->phydev, edata); 3241 } 3242 3243 static void 3244 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3245 { 3246 struct fec_enet_private *fep = netdev_priv(ndev); 3247 3248 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3249 wol->supported = WAKE_MAGIC; 3250 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3251 } else { 3252 wol->supported = wol->wolopts = 0; 3253 } 3254 } 3255 3256 static int 3257 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3258 { 3259 struct fec_enet_private *fep = netdev_priv(ndev); 3260 3261 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3262 return -EINVAL; 3263 3264 if (wol->wolopts & ~WAKE_MAGIC) 3265 return -EINVAL; 3266 3267 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3268 if (device_may_wakeup(&ndev->dev)) 3269 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3270 else 3271 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3272 3273 return 0; 3274 } 3275 3276 static const struct ethtool_ops fec_enet_ethtool_ops = { 3277 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3278 ETHTOOL_COALESCE_MAX_FRAMES, 3279 .get_drvinfo = fec_enet_get_drvinfo, 3280 .get_regs_len = fec_enet_get_regs_len, 3281 .get_regs = fec_enet_get_regs, 3282 .nway_reset = phy_ethtool_nway_reset, 3283 .get_link = ethtool_op_get_link, 3284 .get_coalesce = fec_enet_get_coalesce, 3285 .set_coalesce = fec_enet_set_coalesce, 3286 #ifndef CONFIG_M5272 3287 .get_pauseparam = fec_enet_get_pauseparam, 3288 .set_pauseparam = fec_enet_set_pauseparam, 3289 .get_strings = fec_enet_get_strings, 3290 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3291 .get_sset_count = fec_enet_get_sset_count, 3292 #endif 3293 .get_ts_info = fec_enet_get_ts_info, 3294 .get_wol = fec_enet_get_wol, 3295 .set_wol = fec_enet_set_wol, 3296 .get_eee = fec_enet_get_eee, 3297 .set_eee = fec_enet_set_eee, 3298 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3299 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3300 .self_test = net_selftest, 3301 }; 3302 3303 static void fec_enet_free_buffers(struct net_device *ndev) 3304 { 3305 struct fec_enet_private *fep = netdev_priv(ndev); 3306 unsigned int i; 3307 struct fec_enet_priv_tx_q *txq; 3308 struct fec_enet_priv_rx_q *rxq; 3309 unsigned int q; 3310 3311 for (q = 0; q < fep->num_rx_queues; q++) { 3312 rxq = fep->rx_queue[q]; 3313 for (i = 0; i < rxq->bd.ring_size; i++) 3314 page_pool_put_full_page(rxq->page_pool, rxq->rx_buf[i], 3315 false); 3316 3317 for (i = 0; i < XDP_STATS_TOTAL; i++) 3318 rxq->stats[i] = 0; 3319 3320 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3321 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3322 page_pool_destroy(rxq->page_pool); 3323 rxq->page_pool = NULL; 3324 } 3325 3326 for (q = 0; q < fep->num_tx_queues; q++) { 3327 txq = fep->tx_queue[q]; 3328 for (i = 0; i < txq->bd.ring_size; i++) { 3329 kfree(txq->tx_bounce[i]); 3330 txq->tx_bounce[i] = NULL; 3331 3332 if (!txq->tx_buf[i].buf_p) { 3333 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3334 continue; 3335 } 3336 3337 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3338 dev_kfree_skb(txq->tx_buf[i].buf_p); 3339 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 3340 xdp_return_frame(txq->tx_buf[i].buf_p); 3341 } else { 3342 struct page *page = txq->tx_buf[i].buf_p; 3343 3344 page_pool_put_page(pp_page_to_nmdesc(page)->pp, 3345 page, 0, false); 3346 } 3347 3348 txq->tx_buf[i].buf_p = NULL; 3349 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3350 } 3351 } 3352 } 3353 3354 static void fec_enet_free_queue(struct net_device *ndev) 3355 { 3356 struct fec_enet_private *fep = netdev_priv(ndev); 3357 int i; 3358 struct fec_enet_priv_tx_q *txq; 3359 3360 for (i = 0; i < fep->num_tx_queues; i++) 3361 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3362 txq = fep->tx_queue[i]; 3363 fec_dma_free(&fep->pdev->dev, 3364 txq->bd.ring_size * TSO_HEADER_SIZE, 3365 txq->tso_hdrs, txq->tso_hdrs_dma); 3366 } 3367 3368 for (i = 0; i < fep->num_rx_queues; i++) 3369 kfree(fep->rx_queue[i]); 3370 for (i = 0; i < fep->num_tx_queues; i++) 3371 kfree(fep->tx_queue[i]); 3372 } 3373 3374 static int fec_enet_alloc_queue(struct net_device *ndev) 3375 { 3376 struct fec_enet_private *fep = netdev_priv(ndev); 3377 int i; 3378 int ret = 0; 3379 struct fec_enet_priv_tx_q *txq; 3380 3381 for (i = 0; i < fep->num_tx_queues; i++) { 3382 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3383 if (!txq) { 3384 ret = -ENOMEM; 3385 goto alloc_failed; 3386 } 3387 3388 fep->tx_queue[i] = txq; 3389 txq->bd.ring_size = TX_RING_SIZE; 3390 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3391 3392 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3393 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3394 3395 txq->tso_hdrs = fec_dma_alloc(&fep->pdev->dev, 3396 txq->bd.ring_size * TSO_HEADER_SIZE, 3397 &txq->tso_hdrs_dma, GFP_KERNEL); 3398 if (!txq->tso_hdrs) { 3399 ret = -ENOMEM; 3400 goto alloc_failed; 3401 } 3402 } 3403 3404 for (i = 0; i < fep->num_rx_queues; i++) { 3405 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3406 GFP_KERNEL); 3407 if (!fep->rx_queue[i]) { 3408 ret = -ENOMEM; 3409 goto alloc_failed; 3410 } 3411 3412 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3413 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3414 } 3415 return ret; 3416 3417 alloc_failed: 3418 fec_enet_free_queue(ndev); 3419 return ret; 3420 } 3421 3422 static int 3423 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3424 { 3425 struct fec_enet_private *fep = netdev_priv(ndev); 3426 struct fec_enet_priv_rx_q *rxq; 3427 dma_addr_t phys_addr; 3428 struct bufdesc *bdp; 3429 struct page *page; 3430 int i, err; 3431 3432 rxq = fep->rx_queue[queue]; 3433 bdp = rxq->bd.base; 3434 3435 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3436 if (err < 0) { 3437 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3438 return err; 3439 } 3440 3441 /* Some platforms require the RX buffer must be 64 bytes alignment. 3442 * Some platforms require 16 bytes alignment. And some platforms 3443 * require 4 bytes alignment. But since the page pool have been 3444 * introduced into the driver, the address of RX buffer is always 3445 * the page address plus FEC_ENET_XDP_HEADROOM, and 3446 * FEC_ENET_XDP_HEADROOM is 256 bytes. Therefore, this address can 3447 * satisfy all platforms. To prevent future modifications to 3448 * FEC_ENET_XDP_HEADROOM from ignoring this hardware limitation, a 3449 * BUILD_BUG_ON() test has been added, which ensures that 3450 * FEC_ENET_XDP_HEADROOM provides the required alignment. 3451 */ 3452 BUILD_BUG_ON(FEC_ENET_XDP_HEADROOM & 0x3f); 3453 3454 for (i = 0; i < rxq->bd.ring_size; i++) { 3455 page = page_pool_dev_alloc_pages(rxq->page_pool); 3456 if (!page) 3457 goto err_alloc; 3458 3459 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3460 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3461 3462 rxq->rx_buf[i] = page; 3463 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3464 3465 if (fep->bufdesc_ex) { 3466 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3467 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3468 } 3469 3470 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3471 } 3472 3473 /* Set the last buffer to wrap. */ 3474 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3475 bdp->cbd_sc |= cpu_to_fec16(BD_ENET_RX_WRAP); 3476 return 0; 3477 3478 err_alloc: 3479 fec_enet_free_buffers(ndev); 3480 return -ENOMEM; 3481 } 3482 3483 static int 3484 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3485 { 3486 struct fec_enet_private *fep = netdev_priv(ndev); 3487 unsigned int i; 3488 struct bufdesc *bdp; 3489 struct fec_enet_priv_tx_q *txq; 3490 3491 txq = fep->tx_queue[queue]; 3492 bdp = txq->bd.base; 3493 for (i = 0; i < txq->bd.ring_size; i++) { 3494 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3495 if (!txq->tx_bounce[i]) 3496 goto err_alloc; 3497 3498 bdp->cbd_sc = cpu_to_fec16(0); 3499 bdp->cbd_bufaddr = cpu_to_fec32(0); 3500 3501 if (fep->bufdesc_ex) { 3502 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3503 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3504 } 3505 3506 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3507 } 3508 3509 /* Set the last buffer to wrap. */ 3510 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3511 bdp->cbd_sc |= cpu_to_fec16(BD_ENET_TX_WRAP); 3512 3513 return 0; 3514 3515 err_alloc: 3516 fec_enet_free_buffers(ndev); 3517 return -ENOMEM; 3518 } 3519 3520 static int fec_enet_alloc_buffers(struct net_device *ndev) 3521 { 3522 struct fec_enet_private *fep = netdev_priv(ndev); 3523 unsigned int i; 3524 3525 for (i = 0; i < fep->num_rx_queues; i++) 3526 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3527 return -ENOMEM; 3528 3529 for (i = 0; i < fep->num_tx_queues; i++) 3530 if (fec_enet_alloc_txq_buffers(ndev, i)) 3531 return -ENOMEM; 3532 return 0; 3533 } 3534 3535 static int 3536 fec_enet_open(struct net_device *ndev) 3537 { 3538 struct fec_enet_private *fep = netdev_priv(ndev); 3539 int ret; 3540 bool reset_again; 3541 3542 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3543 if (ret < 0) 3544 return ret; 3545 3546 pinctrl_pm_select_default_state(&fep->pdev->dev); 3547 ret = fec_enet_clk_enable(ndev, true); 3548 if (ret) 3549 goto clk_enable; 3550 3551 /* During the first fec_enet_open call the PHY isn't probed at this 3552 * point. Therefore the phy_reset_after_clk_enable() call within 3553 * fec_enet_clk_enable() fails. As we need this reset in order to be 3554 * sure the PHY is working correctly we check if we need to reset again 3555 * later when the PHY is probed 3556 */ 3557 if (ndev->phydev && ndev->phydev->drv) 3558 reset_again = false; 3559 else 3560 reset_again = true; 3561 3562 /* I should reset the ring buffers here, but I don't yet know 3563 * a simple way to do that. 3564 */ 3565 3566 ret = fec_enet_alloc_buffers(ndev); 3567 if (ret) 3568 goto err_enet_alloc; 3569 3570 /* Init MAC prior to mii bus probe */ 3571 fec_restart(ndev); 3572 3573 /* Call phy_reset_after_clk_enable() again if it failed during 3574 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3575 */ 3576 if (reset_again) 3577 fec_enet_phy_reset_after_clk_enable(ndev); 3578 3579 /* Probe and connect to PHY when open the interface */ 3580 ret = fec_enet_mii_probe(ndev); 3581 if (ret) 3582 goto err_enet_mii_probe; 3583 3584 if (fep->quirks & FEC_QUIRK_ERR006687) 3585 imx6q_cpuidle_fec_irqs_used(); 3586 3587 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3588 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3589 3590 napi_enable(&fep->napi); 3591 phy_start(ndev->phydev); 3592 netif_tx_start_all_queues(ndev); 3593 3594 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3595 FEC_WOL_FLAG_ENABLE); 3596 3597 return 0; 3598 3599 err_enet_mii_probe: 3600 fec_enet_free_buffers(ndev); 3601 err_enet_alloc: 3602 fec_enet_clk_enable(ndev, false); 3603 clk_enable: 3604 pm_runtime_put_autosuspend(&fep->pdev->dev); 3605 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3606 return ret; 3607 } 3608 3609 static int 3610 fec_enet_close(struct net_device *ndev) 3611 { 3612 struct fec_enet_private *fep = netdev_priv(ndev); 3613 struct phy_device *phy_dev = ndev->phydev; 3614 3615 phy_stop(phy_dev); 3616 3617 if (netif_device_present(ndev)) { 3618 napi_disable(&fep->napi); 3619 netif_tx_disable(ndev); 3620 fec_stop(ndev); 3621 } 3622 3623 phy_disconnect(phy_dev); 3624 3625 if (!fep->phy_node && phy_is_pseudo_fixed_link(phy_dev)) 3626 fixed_phy_unregister(phy_dev); 3627 3628 if (fep->quirks & FEC_QUIRK_ERR006687) 3629 imx6q_cpuidle_fec_irqs_unused(); 3630 3631 fec_enet_update_ethtool_stats(ndev); 3632 3633 fec_enet_clk_enable(ndev, false); 3634 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3635 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3636 3637 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3638 pm_runtime_put_autosuspend(&fep->pdev->dev); 3639 3640 fec_enet_free_buffers(ndev); 3641 3642 return 0; 3643 } 3644 3645 /* Set or clear the multicast filter for this adaptor. 3646 * Skeleton taken from sunlance driver. 3647 * The CPM Ethernet implementation allows Multicast as well as individual 3648 * MAC address filtering. Some of the drivers check to make sure it is 3649 * a group multicast address, and discard those that are not. I guess I 3650 * will do the same for now, but just remove the test if you want 3651 * individual filtering as well (do the upper net layers want or support 3652 * this kind of feature?). 3653 */ 3654 3655 #define FEC_HASH_BITS 6 /* #bits in hash */ 3656 3657 static void set_multicast_list(struct net_device *ndev) 3658 { 3659 struct fec_enet_private *fep = netdev_priv(ndev); 3660 struct netdev_hw_addr *ha; 3661 unsigned int crc, tmp; 3662 unsigned char hash; 3663 unsigned int hash_high = 0, hash_low = 0; 3664 3665 if (ndev->flags & IFF_PROMISC) { 3666 tmp = readl(fep->hwp + FEC_R_CNTRL); 3667 tmp |= 0x8; 3668 writel(tmp, fep->hwp + FEC_R_CNTRL); 3669 return; 3670 } 3671 3672 tmp = readl(fep->hwp + FEC_R_CNTRL); 3673 tmp &= ~0x8; 3674 writel(tmp, fep->hwp + FEC_R_CNTRL); 3675 3676 if (ndev->flags & IFF_ALLMULTI) { 3677 /* Catch all multicast addresses, so set the 3678 * filter to all 1's 3679 */ 3680 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3681 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3682 3683 return; 3684 } 3685 3686 /* Add the addresses in hash register */ 3687 netdev_for_each_mc_addr(ha, ndev) { 3688 /* calculate crc32 value of mac address */ 3689 crc = ether_crc_le(ndev->addr_len, ha->addr); 3690 3691 /* only upper 6 bits (FEC_HASH_BITS) are used 3692 * which point to specific bit in the hash registers 3693 */ 3694 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3695 3696 if (hash > 31) 3697 hash_high |= 1 << (hash - 32); 3698 else 3699 hash_low |= 1 << hash; 3700 } 3701 3702 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3703 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3704 } 3705 3706 /* Set a MAC change in hardware. */ 3707 static int 3708 fec_set_mac_address(struct net_device *ndev, void *p) 3709 { 3710 struct sockaddr *addr = p; 3711 3712 if (addr) { 3713 if (!is_valid_ether_addr(addr->sa_data)) 3714 return -EADDRNOTAVAIL; 3715 eth_hw_addr_set(ndev, addr->sa_data); 3716 } 3717 3718 /* Add netif status check here to avoid system hang in below case: 3719 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3720 * After ethx down, fec all clocks are gated off and then register 3721 * access causes system hang. 3722 */ 3723 if (!netif_running(ndev)) 3724 return 0; 3725 3726 fec_set_hw_mac_addr(ndev); 3727 3728 return 0; 3729 } 3730 3731 static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3732 netdev_features_t features) 3733 { 3734 struct fec_enet_private *fep = netdev_priv(netdev); 3735 netdev_features_t changed = features ^ netdev->features; 3736 3737 netdev->features = features; 3738 3739 /* Receive checksum has been changed */ 3740 if (changed & NETIF_F_RXCSUM) { 3741 if (features & NETIF_F_RXCSUM) 3742 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3743 else 3744 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3745 } 3746 } 3747 3748 static int fec_set_features(struct net_device *netdev, 3749 netdev_features_t features) 3750 { 3751 struct fec_enet_private *fep = netdev_priv(netdev); 3752 netdev_features_t changed = features ^ netdev->features; 3753 3754 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3755 napi_disable(&fep->napi); 3756 netif_tx_lock_bh(netdev); 3757 fec_stop(netdev); 3758 fec_enet_set_netdev_features(netdev, features); 3759 fec_restart(netdev); 3760 netif_tx_wake_all_queues(netdev); 3761 netif_tx_unlock_bh(netdev); 3762 napi_enable(&fep->napi); 3763 } else { 3764 fec_enet_set_netdev_features(netdev, features); 3765 } 3766 3767 return 0; 3768 } 3769 3770 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3771 struct net_device *sb_dev) 3772 { 3773 struct fec_enet_private *fep = netdev_priv(ndev); 3774 u16 vlan_tag = 0; 3775 3776 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3777 return netdev_pick_tx(ndev, skb, NULL); 3778 3779 /* VLAN is present in the payload.*/ 3780 if (eth_type_vlan(skb->protocol)) { 3781 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb); 3782 3783 vlan_tag = ntohs(vhdr->h_vlan_TCI); 3784 /* VLAN is present in the skb but not yet pushed in the payload.*/ 3785 } else if (skb_vlan_tag_present(skb)) { 3786 vlan_tag = skb->vlan_tci; 3787 } else { 3788 return vlan_tag; 3789 } 3790 3791 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3792 } 3793 3794 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3795 { 3796 struct fec_enet_private *fep = netdev_priv(dev); 3797 bool is_run = netif_running(dev); 3798 struct bpf_prog *old_prog; 3799 3800 switch (bpf->command) { 3801 case XDP_SETUP_PROG: 3802 /* No need to support the SoCs that require to 3803 * do the frame swap because the performance wouldn't be 3804 * better than the skb mode. 3805 */ 3806 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3807 return -EOPNOTSUPP; 3808 3809 if (!bpf->prog) 3810 xdp_features_clear_redirect_target(dev); 3811 3812 if (is_run) { 3813 napi_disable(&fep->napi); 3814 netif_tx_disable(dev); 3815 } 3816 3817 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3818 if (old_prog) 3819 bpf_prog_put(old_prog); 3820 3821 fec_restart(dev); 3822 3823 if (is_run) { 3824 napi_enable(&fep->napi); 3825 netif_tx_start_all_queues(dev); 3826 } 3827 3828 if (bpf->prog) 3829 xdp_features_set_redirect_target(dev, false); 3830 3831 return 0; 3832 3833 case XDP_SETUP_XSK_POOL: 3834 return -EOPNOTSUPP; 3835 3836 default: 3837 return -EOPNOTSUPP; 3838 } 3839 } 3840 3841 static int 3842 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3843 { 3844 if (unlikely(index < 0)) 3845 return 0; 3846 3847 return (index % fep->num_tx_queues); 3848 } 3849 3850 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3851 struct fec_enet_priv_tx_q *txq, 3852 void *frame, u32 dma_sync_len, 3853 bool ndo_xmit) 3854 { 3855 unsigned int index, status, estatus; 3856 struct bufdesc *bdp; 3857 dma_addr_t dma_addr; 3858 int entries_free; 3859 u16 frame_len; 3860 3861 entries_free = fec_enet_get_free_txdesc_num(txq); 3862 if (entries_free < MAX_SKB_FRAGS + 1) { 3863 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3864 return -EBUSY; 3865 } 3866 3867 /* Fill in a Tx ring entry */ 3868 bdp = txq->bd.cur; 3869 status = fec16_to_cpu(bdp->cbd_sc); 3870 status &= ~BD_ENET_TX_STATS; 3871 3872 index = fec_enet_get_bd_index(bdp, &txq->bd); 3873 3874 if (ndo_xmit) { 3875 struct xdp_frame *xdpf = frame; 3876 3877 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data, 3878 xdpf->len, DMA_TO_DEVICE); 3879 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3880 return -ENOMEM; 3881 3882 frame_len = xdpf->len; 3883 txq->tx_buf[index].buf_p = xdpf; 3884 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3885 } else { 3886 struct xdp_buff *xdpb = frame; 3887 struct page *page; 3888 3889 page = virt_to_page(xdpb->data); 3890 dma_addr = page_pool_get_dma_addr(page) + 3891 (xdpb->data - xdpb->data_hard_start); 3892 dma_sync_single_for_device(&fep->pdev->dev, dma_addr, 3893 dma_sync_len, DMA_BIDIRECTIONAL); 3894 frame_len = xdpb->data_end - xdpb->data; 3895 txq->tx_buf[index].buf_p = page; 3896 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX; 3897 } 3898 3899 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3900 if (fep->bufdesc_ex) 3901 estatus = BD_ENET_TX_INT; 3902 3903 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3904 bdp->cbd_datlen = cpu_to_fec16(frame_len); 3905 3906 if (fep->bufdesc_ex) { 3907 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3908 3909 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3910 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3911 3912 ebdp->cbd_bdu = 0; 3913 ebdp->cbd_esc = cpu_to_fec32(estatus); 3914 } 3915 3916 /* Make sure the updates to rest of the descriptor are performed before 3917 * transferring ownership. 3918 */ 3919 dma_wmb(); 3920 3921 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3922 * it's the last BD of the frame, and to put the CRC on the end. 3923 */ 3924 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3925 bdp->cbd_sc = cpu_to_fec16(status); 3926 3927 /* If this was the last BD in the ring, start at the beginning again. */ 3928 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3929 3930 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3931 dma_wmb(); 3932 3933 txq->bd.cur = bdp; 3934 3935 /* Trigger transmission start */ 3936 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 3937 !readl(txq->bd.reg_desc_active) || 3938 !readl(txq->bd.reg_desc_active) || 3939 !readl(txq->bd.reg_desc_active) || 3940 !readl(txq->bd.reg_desc_active)) 3941 writel(0, txq->bd.reg_desc_active); 3942 3943 return 0; 3944 } 3945 3946 static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 3947 int cpu, struct xdp_buff *xdp, 3948 u32 dma_sync_len) 3949 { 3950 struct fec_enet_priv_tx_q *txq; 3951 struct netdev_queue *nq; 3952 int queue, ret; 3953 3954 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3955 txq = fep->tx_queue[queue]; 3956 nq = netdev_get_tx_queue(fep->netdev, queue); 3957 3958 __netif_tx_lock(nq, cpu); 3959 3960 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3961 txq_trans_cond_update(nq); 3962 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false); 3963 3964 __netif_tx_unlock(nq); 3965 3966 return ret; 3967 } 3968 3969 static int fec_enet_xdp_xmit(struct net_device *dev, 3970 int num_frames, 3971 struct xdp_frame **frames, 3972 u32 flags) 3973 { 3974 struct fec_enet_private *fep = netdev_priv(dev); 3975 struct fec_enet_priv_tx_q *txq; 3976 int cpu = smp_processor_id(); 3977 unsigned int sent_frames = 0; 3978 struct netdev_queue *nq; 3979 unsigned int queue; 3980 int i; 3981 3982 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3983 txq = fep->tx_queue[queue]; 3984 nq = netdev_get_tx_queue(fep->netdev, queue); 3985 3986 __netif_tx_lock(nq, cpu); 3987 3988 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3989 txq_trans_cond_update(nq); 3990 for (i = 0; i < num_frames; i++) { 3991 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0) 3992 break; 3993 sent_frames++; 3994 } 3995 3996 __netif_tx_unlock(nq); 3997 3998 return sent_frames; 3999 } 4000 4001 static int fec_hwtstamp_get(struct net_device *ndev, 4002 struct kernel_hwtstamp_config *config) 4003 { 4004 struct fec_enet_private *fep = netdev_priv(ndev); 4005 4006 if (!netif_running(ndev)) 4007 return -EINVAL; 4008 4009 if (!fep->bufdesc_ex) 4010 return -EOPNOTSUPP; 4011 4012 fec_ptp_get(ndev, config); 4013 4014 return 0; 4015 } 4016 4017 static int fec_hwtstamp_set(struct net_device *ndev, 4018 struct kernel_hwtstamp_config *config, 4019 struct netlink_ext_ack *extack) 4020 { 4021 struct fec_enet_private *fep = netdev_priv(ndev); 4022 4023 if (!netif_running(ndev)) 4024 return -EINVAL; 4025 4026 if (!fep->bufdesc_ex) 4027 return -EOPNOTSUPP; 4028 4029 return fec_ptp_set(ndev, config, extack); 4030 } 4031 4032 static int fec_change_mtu(struct net_device *ndev, int new_mtu) 4033 { 4034 struct fec_enet_private *fep = netdev_priv(ndev); 4035 int order; 4036 4037 if (netif_running(ndev)) 4038 return -EBUSY; 4039 4040 order = get_order(new_mtu + ETH_HLEN + ETH_FCS_LEN 4041 + FEC_DRV_RESERVE_SPACE); 4042 fep->rx_frame_size = (PAGE_SIZE << order) - FEC_DRV_RESERVE_SPACE; 4043 fep->pagepool_order = order; 4044 WRITE_ONCE(ndev->mtu, new_mtu); 4045 4046 return 0; 4047 } 4048 4049 static const struct net_device_ops fec_netdev_ops = { 4050 .ndo_open = fec_enet_open, 4051 .ndo_stop = fec_enet_close, 4052 .ndo_start_xmit = fec_enet_start_xmit, 4053 .ndo_select_queue = fec_enet_select_queue, 4054 .ndo_set_rx_mode = set_multicast_list, 4055 .ndo_validate_addr = eth_validate_addr, 4056 .ndo_tx_timeout = fec_timeout, 4057 .ndo_set_mac_address = fec_set_mac_address, 4058 .ndo_change_mtu = fec_change_mtu, 4059 .ndo_eth_ioctl = phy_do_ioctl_running, 4060 .ndo_set_features = fec_set_features, 4061 .ndo_bpf = fec_enet_bpf, 4062 .ndo_xdp_xmit = fec_enet_xdp_xmit, 4063 .ndo_hwtstamp_get = fec_hwtstamp_get, 4064 .ndo_hwtstamp_set = fec_hwtstamp_set, 4065 }; 4066 4067 static const unsigned short offset_des_active_rxq[] = { 4068 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 4069 }; 4070 4071 static const unsigned short offset_des_active_txq[] = { 4072 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 4073 }; 4074 4075 /* 4076 * XXX: We need to clean up on failure exits here. 4077 * 4078 */ 4079 static int fec_enet_init(struct net_device *ndev) 4080 { 4081 struct fec_enet_private *fep = netdev_priv(ndev); 4082 struct bufdesc *cbd_base; 4083 dma_addr_t bd_dma; 4084 int bd_size; 4085 unsigned int i; 4086 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 4087 sizeof(struct bufdesc); 4088 unsigned dsize_log2 = __fls(dsize); 4089 int ret; 4090 4091 WARN_ON(dsize != (1 << dsize_log2)); 4092 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 4093 fep->tx_align = 0xf; 4094 #else 4095 fep->tx_align = 0x3; 4096 #endif 4097 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4098 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4099 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 4100 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 4101 4102 /* Check mask of the streaming and coherent API */ 4103 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 4104 if (ret < 0) { 4105 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 4106 return ret; 4107 } 4108 4109 ret = fec_enet_alloc_queue(ndev); 4110 if (ret) 4111 return ret; 4112 4113 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 4114 4115 /* Allocate memory for buffer descriptors. */ 4116 cbd_base = fec_dmam_alloc(&fep->pdev->dev, bd_size, &bd_dma, 4117 GFP_KERNEL); 4118 if (!cbd_base) { 4119 ret = -ENOMEM; 4120 goto free_queue_mem; 4121 } 4122 4123 /* Get the Ethernet address */ 4124 ret = fec_get_mac(ndev); 4125 if (ret) 4126 goto free_queue_mem; 4127 4128 /* Set receive and transmit descriptor base. */ 4129 for (i = 0; i < fep->num_rx_queues; i++) { 4130 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 4131 unsigned size = dsize * rxq->bd.ring_size; 4132 4133 rxq->bd.qid = i; 4134 rxq->bd.base = cbd_base; 4135 rxq->bd.cur = cbd_base; 4136 rxq->bd.dma = bd_dma; 4137 rxq->bd.dsize = dsize; 4138 rxq->bd.dsize_log2 = dsize_log2; 4139 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 4140 bd_dma += size; 4141 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4142 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4143 } 4144 4145 for (i = 0; i < fep->num_tx_queues; i++) { 4146 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4147 unsigned size = dsize * txq->bd.ring_size; 4148 4149 txq->bd.qid = i; 4150 txq->bd.base = cbd_base; 4151 txq->bd.cur = cbd_base; 4152 txq->bd.dma = bd_dma; 4153 txq->bd.dsize = dsize; 4154 txq->bd.dsize_log2 = dsize_log2; 4155 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4156 bd_dma += size; 4157 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4158 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4159 } 4160 4161 4162 /* The FEC Ethernet specific entries in the device structure */ 4163 ndev->watchdog_timeo = TX_TIMEOUT; 4164 ndev->netdev_ops = &fec_netdev_ops; 4165 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4166 4167 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4168 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4169 4170 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4171 /* enable hw VLAN support */ 4172 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4173 4174 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4175 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4176 4177 /* enable hw accelerator */ 4178 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4179 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4180 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4181 } 4182 4183 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) 4184 fep->tx_align = 0; 4185 4186 ndev->hw_features = ndev->features; 4187 4188 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4189 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4190 NETDEV_XDP_ACT_REDIRECT; 4191 4192 fec_restart(ndev); 4193 4194 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4195 fec_enet_clear_ethtool_stats(ndev); 4196 else 4197 fec_enet_update_ethtool_stats(ndev); 4198 4199 return 0; 4200 4201 free_queue_mem: 4202 fec_enet_free_queue(ndev); 4203 return ret; 4204 } 4205 4206 static void fec_enet_deinit(struct net_device *ndev) 4207 { 4208 struct fec_enet_private *fep = netdev_priv(ndev); 4209 4210 netif_napi_del(&fep->napi); 4211 fec_enet_free_queue(ndev); 4212 } 4213 4214 #ifdef CONFIG_OF 4215 static int fec_reset_phy(struct platform_device *pdev) 4216 { 4217 struct gpio_desc *phy_reset; 4218 int msec = 1, phy_post_delay = 0; 4219 struct device_node *np = pdev->dev.of_node; 4220 int err; 4221 4222 if (!np) 4223 return 0; 4224 4225 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4226 /* A sane reset duration should not be longer than 1s */ 4227 if (!err && msec > 1000) 4228 msec = 1; 4229 4230 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4231 /* valid reset duration should be less than 1s */ 4232 if (!err && phy_post_delay > 1000) 4233 return -EINVAL; 4234 4235 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4236 GPIOD_OUT_HIGH); 4237 if (IS_ERR(phy_reset)) 4238 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4239 "failed to get phy-reset-gpios\n"); 4240 4241 if (!phy_reset) 4242 return 0; 4243 4244 if (msec > 20) 4245 msleep(msec); 4246 else 4247 usleep_range(msec * 1000, msec * 1000 + 1000); 4248 4249 gpiod_set_value_cansleep(phy_reset, 0); 4250 4251 if (!phy_post_delay) 4252 return 0; 4253 4254 if (phy_post_delay > 20) 4255 msleep(phy_post_delay); 4256 else 4257 usleep_range(phy_post_delay * 1000, 4258 phy_post_delay * 1000 + 1000); 4259 4260 return 0; 4261 } 4262 #else /* CONFIG_OF */ 4263 static int fec_reset_phy(struct platform_device *pdev) 4264 { 4265 /* 4266 * In case of platform probe, the reset has been done 4267 * by machine code. 4268 */ 4269 return 0; 4270 } 4271 #endif /* CONFIG_OF */ 4272 4273 static void 4274 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4275 { 4276 struct device_node *np = pdev->dev.of_node; 4277 4278 *num_tx = *num_rx = 1; 4279 4280 if (!np || !of_device_is_available(np)) 4281 return; 4282 4283 /* parse the num of tx and rx queues */ 4284 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4285 4286 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4287 4288 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4289 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4290 *num_tx); 4291 *num_tx = 1; 4292 return; 4293 } 4294 4295 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4296 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4297 *num_rx); 4298 *num_rx = 1; 4299 return; 4300 } 4301 4302 } 4303 4304 static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4305 { 4306 int irq_cnt = platform_irq_count(pdev); 4307 4308 if (irq_cnt > FEC_IRQ_NUM) 4309 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4310 else if (irq_cnt == 2) 4311 irq_cnt = 1; /* last for pps */ 4312 else if (irq_cnt <= 0) 4313 irq_cnt = 1; /* At least 1 irq is needed */ 4314 return irq_cnt; 4315 } 4316 4317 static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4318 { 4319 struct net_device *ndev = platform_get_drvdata(pdev); 4320 struct fec_enet_private *fep = netdev_priv(ndev); 4321 4322 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4323 fep->wake_irq = fep->irq[2]; 4324 else 4325 fep->wake_irq = fep->irq[0]; 4326 } 4327 4328 static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4329 struct device_node *np) 4330 { 4331 struct device_node *gpr_np; 4332 u32 out_val[3]; 4333 int ret = 0; 4334 4335 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4336 if (!gpr_np) 4337 return 0; 4338 4339 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4340 ARRAY_SIZE(out_val)); 4341 if (ret) { 4342 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4343 goto out; 4344 } 4345 4346 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4347 if (IS_ERR(fep->stop_gpr.gpr)) { 4348 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4349 ret = PTR_ERR(fep->stop_gpr.gpr); 4350 fep->stop_gpr.gpr = NULL; 4351 goto out; 4352 } 4353 4354 fep->stop_gpr.reg = out_val[1]; 4355 fep->stop_gpr.bit = out_val[2]; 4356 4357 out: 4358 of_node_put(gpr_np); 4359 4360 return ret; 4361 } 4362 4363 static int 4364 fec_probe(struct platform_device *pdev) 4365 { 4366 struct fec_enet_private *fep; 4367 struct fec_platform_data *pdata; 4368 phy_interface_t interface; 4369 struct net_device *ndev; 4370 int i, irq, ret = 0; 4371 static int dev_id; 4372 struct device_node *np = pdev->dev.of_node, *phy_node; 4373 int num_tx_qs; 4374 int num_rx_qs; 4375 char irq_name[8]; 4376 int irq_cnt; 4377 const struct fec_devinfo *dev_info; 4378 4379 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4380 4381 /* Init network device */ 4382 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4383 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4384 if (!ndev) 4385 return -ENOMEM; 4386 4387 SET_NETDEV_DEV(ndev, &pdev->dev); 4388 4389 /* setup board info structure */ 4390 fep = netdev_priv(ndev); 4391 4392 dev_info = device_get_match_data(&pdev->dev); 4393 if (!dev_info) 4394 dev_info = (const struct fec_devinfo *)pdev->id_entry->driver_data; 4395 if (dev_info) 4396 fep->quirks = dev_info->quirks; 4397 4398 fep->netdev = ndev; 4399 fep->num_rx_queues = num_rx_qs; 4400 fep->num_tx_queues = num_tx_qs; 4401 4402 /* default enable pause frame auto negotiation */ 4403 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4404 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4405 4406 /* Select default pin state */ 4407 pinctrl_pm_select_default_state(&pdev->dev); 4408 4409 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4410 if (IS_ERR(fep->hwp)) { 4411 ret = PTR_ERR(fep->hwp); 4412 goto failed_ioremap; 4413 } 4414 4415 fep->pdev = pdev; 4416 fep->dev_id = dev_id++; 4417 4418 platform_set_drvdata(pdev, ndev); 4419 4420 if ((of_machine_is_compatible("fsl,imx6q") || 4421 of_machine_is_compatible("fsl,imx6dl")) && 4422 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4423 fep->quirks |= FEC_QUIRK_ERR006687; 4424 4425 ret = fec_enet_ipc_handle_init(fep); 4426 if (ret) 4427 goto failed_ipc_init; 4428 4429 if (of_property_read_bool(np, "fsl,magic-packet")) 4430 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4431 4432 ret = fec_enet_init_stop_mode(fep, np); 4433 if (ret) 4434 goto failed_stop_mode; 4435 4436 phy_node = of_parse_phandle(np, "phy-handle", 0); 4437 if (!phy_node && of_phy_is_fixed_link(np)) { 4438 ret = of_phy_register_fixed_link(np); 4439 if (ret < 0) { 4440 dev_err(&pdev->dev, 4441 "broken fixed-link specification\n"); 4442 goto failed_phy; 4443 } 4444 phy_node = of_node_get(np); 4445 } 4446 fep->phy_node = phy_node; 4447 4448 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4449 if (ret) { 4450 pdata = dev_get_platdata(&pdev->dev); 4451 if (pdata) 4452 fep->phy_interface = pdata->phy; 4453 else 4454 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4455 } else { 4456 fep->phy_interface = interface; 4457 } 4458 4459 ret = fec_enet_parse_rgmii_delay(fep, np); 4460 if (ret) 4461 goto failed_rgmii_delay; 4462 4463 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4464 if (IS_ERR(fep->clk_ipg)) { 4465 ret = PTR_ERR(fep->clk_ipg); 4466 goto failed_clk; 4467 } 4468 4469 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4470 if (IS_ERR(fep->clk_ahb)) { 4471 ret = PTR_ERR(fep->clk_ahb); 4472 goto failed_clk; 4473 } 4474 4475 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4476 4477 /* enet_out is optional, depends on board */ 4478 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4479 if (IS_ERR(fep->clk_enet_out)) { 4480 ret = PTR_ERR(fep->clk_enet_out); 4481 goto failed_clk; 4482 } 4483 4484 fep->ptp_clk_on = false; 4485 mutex_init(&fep->ptp_clk_mutex); 4486 4487 /* clk_ref is optional, depends on board */ 4488 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4489 if (IS_ERR(fep->clk_ref)) { 4490 ret = PTR_ERR(fep->clk_ref); 4491 goto failed_clk; 4492 } 4493 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4494 4495 /* clk_2x_txclk is optional, depends on board */ 4496 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4497 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4498 if (IS_ERR(fep->clk_2x_txclk)) 4499 fep->clk_2x_txclk = NULL; 4500 } 4501 4502 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4503 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4504 if (IS_ERR(fep->clk_ptp)) { 4505 fep->clk_ptp = NULL; 4506 fep->bufdesc_ex = false; 4507 } 4508 4509 ret = fec_enet_clk_enable(ndev, true); 4510 if (ret) 4511 goto failed_clk; 4512 4513 ret = clk_prepare_enable(fep->clk_ipg); 4514 if (ret) 4515 goto failed_clk_ipg; 4516 ret = clk_prepare_enable(fep->clk_ahb); 4517 if (ret) 4518 goto failed_clk_ahb; 4519 4520 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4521 if (!IS_ERR(fep->reg_phy)) { 4522 ret = regulator_enable(fep->reg_phy); 4523 if (ret) { 4524 dev_err(&pdev->dev, 4525 "Failed to enable phy regulator: %d\n", ret); 4526 goto failed_regulator; 4527 } 4528 } else { 4529 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4530 ret = -EPROBE_DEFER; 4531 goto failed_regulator; 4532 } 4533 fep->reg_phy = NULL; 4534 } 4535 4536 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4537 pm_runtime_use_autosuspend(&pdev->dev); 4538 pm_runtime_get_noresume(&pdev->dev); 4539 pm_runtime_set_active(&pdev->dev); 4540 pm_runtime_enable(&pdev->dev); 4541 4542 ret = fec_reset_phy(pdev); 4543 if (ret) 4544 goto failed_reset; 4545 4546 irq_cnt = fec_enet_get_irq_cnt(pdev); 4547 if (fep->bufdesc_ex) 4548 fec_ptp_init(pdev, irq_cnt); 4549 4550 ret = fec_enet_init(ndev); 4551 if (ret) 4552 goto failed_init; 4553 4554 for (i = 0; i < irq_cnt; i++) { 4555 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4556 irq = platform_get_irq_byname_optional(pdev, irq_name); 4557 if (irq < 0) 4558 irq = platform_get_irq(pdev, i); 4559 if (irq < 0) { 4560 ret = irq; 4561 goto failed_irq; 4562 } 4563 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4564 0, pdev->name, ndev); 4565 if (ret) 4566 goto failed_irq; 4567 4568 fep->irq[i] = irq; 4569 } 4570 4571 /* Decide which interrupt line is wakeup capable */ 4572 fec_enet_get_wakeup_irq(pdev); 4573 4574 ret = fec_enet_mii_init(pdev); 4575 if (ret) 4576 goto failed_mii_init; 4577 4578 /* Carrier starts down, phylib will bring it up */ 4579 netif_carrier_off(ndev); 4580 fec_enet_clk_enable(ndev, false); 4581 pinctrl_pm_select_sleep_state(&pdev->dev); 4582 4583 fep->pagepool_order = 0; 4584 fep->rx_frame_size = FEC_ENET_RX_FRSIZE; 4585 4586 if (fep->quirks & FEC_QUIRK_JUMBO_FRAME) 4587 fep->max_buf_size = MAX_JUMBO_BUF_SIZE; 4588 else 4589 fep->max_buf_size = PKT_MAXBUF_SIZE; 4590 4591 ndev->max_mtu = fep->max_buf_size - ETH_HLEN - ETH_FCS_LEN; 4592 4593 ret = register_netdev(ndev); 4594 if (ret) 4595 goto failed_register; 4596 4597 device_init_wakeup(&ndev->dev, fep->wol_flag & 4598 FEC_WOL_HAS_MAGIC_PACKET); 4599 4600 if (fep->bufdesc_ex && fep->ptp_clock) 4601 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4602 4603 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4604 4605 pm_runtime_put_autosuspend(&pdev->dev); 4606 4607 return 0; 4608 4609 failed_register: 4610 fec_enet_mii_remove(fep); 4611 failed_mii_init: 4612 failed_irq: 4613 fec_enet_deinit(ndev); 4614 failed_init: 4615 fec_ptp_stop(pdev); 4616 failed_reset: 4617 pm_runtime_put_noidle(&pdev->dev); 4618 pm_runtime_disable(&pdev->dev); 4619 if (fep->reg_phy) 4620 regulator_disable(fep->reg_phy); 4621 failed_regulator: 4622 clk_disable_unprepare(fep->clk_ahb); 4623 failed_clk_ahb: 4624 clk_disable_unprepare(fep->clk_ipg); 4625 failed_clk_ipg: 4626 fec_enet_clk_enable(ndev, false); 4627 failed_clk: 4628 failed_rgmii_delay: 4629 if (of_phy_is_fixed_link(np)) 4630 of_phy_deregister_fixed_link(np); 4631 of_node_put(phy_node); 4632 failed_stop_mode: 4633 failed_ipc_init: 4634 failed_phy: 4635 dev_id--; 4636 failed_ioremap: 4637 free_netdev(ndev); 4638 4639 return ret; 4640 } 4641 4642 static void 4643 fec_drv_remove(struct platform_device *pdev) 4644 { 4645 struct net_device *ndev = platform_get_drvdata(pdev); 4646 struct fec_enet_private *fep = netdev_priv(ndev); 4647 struct device_node *np = pdev->dev.of_node; 4648 int ret; 4649 4650 ret = pm_runtime_get_sync(&pdev->dev); 4651 if (ret < 0) 4652 dev_err(&pdev->dev, 4653 "Failed to resume device in remove callback (%pe)\n", 4654 ERR_PTR(ret)); 4655 4656 cancel_work_sync(&fep->tx_timeout_work); 4657 fec_ptp_stop(pdev); 4658 unregister_netdev(ndev); 4659 fec_enet_mii_remove(fep); 4660 if (fep->reg_phy) 4661 regulator_disable(fep->reg_phy); 4662 4663 if (of_phy_is_fixed_link(np)) 4664 of_phy_deregister_fixed_link(np); 4665 of_node_put(fep->phy_node); 4666 4667 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4668 * disabling them again. 4669 */ 4670 if (ret >= 0) { 4671 clk_disable_unprepare(fep->clk_ahb); 4672 clk_disable_unprepare(fep->clk_ipg); 4673 } 4674 pm_runtime_put_noidle(&pdev->dev); 4675 pm_runtime_disable(&pdev->dev); 4676 4677 fec_enet_deinit(ndev); 4678 free_netdev(ndev); 4679 } 4680 4681 static int fec_suspend(struct device *dev) 4682 { 4683 struct net_device *ndev = dev_get_drvdata(dev); 4684 struct fec_enet_private *fep = netdev_priv(ndev); 4685 int ret; 4686 4687 rtnl_lock(); 4688 if (netif_running(ndev)) { 4689 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4690 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4691 phy_stop(ndev->phydev); 4692 napi_disable(&fep->napi); 4693 netif_tx_lock_bh(ndev); 4694 netif_device_detach(ndev); 4695 netif_tx_unlock_bh(ndev); 4696 fec_stop(ndev); 4697 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4698 fec_irqs_disable(ndev); 4699 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4700 } else { 4701 fec_irqs_disable_except_wakeup(ndev); 4702 if (fep->wake_irq > 0) { 4703 disable_irq(fep->wake_irq); 4704 enable_irq_wake(fep->wake_irq); 4705 } 4706 fec_enet_stop_mode(fep, true); 4707 } 4708 /* It's safe to disable clocks since interrupts are masked */ 4709 fec_enet_clk_enable(ndev, false); 4710 4711 fep->rpm_active = !pm_runtime_status_suspended(dev); 4712 if (fep->rpm_active) { 4713 ret = pm_runtime_force_suspend(dev); 4714 if (ret < 0) { 4715 rtnl_unlock(); 4716 return ret; 4717 } 4718 } 4719 } 4720 rtnl_unlock(); 4721 4722 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4723 regulator_disable(fep->reg_phy); 4724 4725 /* SOC supply clock to phy, when clock is disabled, phy link down 4726 * SOC control phy regulator, when regulator is disabled, phy link down 4727 */ 4728 if (fep->clk_enet_out || fep->reg_phy) 4729 fep->link = 0; 4730 4731 return 0; 4732 } 4733 4734 static int fec_resume(struct device *dev) 4735 { 4736 struct net_device *ndev = dev_get_drvdata(dev); 4737 struct fec_enet_private *fep = netdev_priv(ndev); 4738 int ret; 4739 int val; 4740 4741 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4742 ret = regulator_enable(fep->reg_phy); 4743 if (ret) 4744 return ret; 4745 } 4746 4747 rtnl_lock(); 4748 if (netif_running(ndev)) { 4749 if (fep->rpm_active) 4750 pm_runtime_force_resume(dev); 4751 4752 ret = fec_enet_clk_enable(ndev, true); 4753 if (ret) { 4754 rtnl_unlock(); 4755 goto failed_clk; 4756 } 4757 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4758 fec_enet_stop_mode(fep, false); 4759 if (fep->wake_irq) { 4760 disable_irq_wake(fep->wake_irq); 4761 enable_irq(fep->wake_irq); 4762 } 4763 4764 val = readl(fep->hwp + FEC_ECNTRL); 4765 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4766 writel(val, fep->hwp + FEC_ECNTRL); 4767 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4768 } else { 4769 pinctrl_pm_select_default_state(&fep->pdev->dev); 4770 } 4771 fec_restart(ndev); 4772 netif_tx_lock_bh(ndev); 4773 netif_device_attach(ndev); 4774 netif_tx_unlock_bh(ndev); 4775 napi_enable(&fep->napi); 4776 phy_init_hw(ndev->phydev); 4777 phy_start(ndev->phydev); 4778 } 4779 rtnl_unlock(); 4780 4781 return 0; 4782 4783 failed_clk: 4784 if (fep->reg_phy) 4785 regulator_disable(fep->reg_phy); 4786 return ret; 4787 } 4788 4789 static int fec_runtime_suspend(struct device *dev) 4790 { 4791 struct net_device *ndev = dev_get_drvdata(dev); 4792 struct fec_enet_private *fep = netdev_priv(ndev); 4793 4794 clk_disable_unprepare(fep->clk_ahb); 4795 clk_disable_unprepare(fep->clk_ipg); 4796 4797 return 0; 4798 } 4799 4800 static int fec_runtime_resume(struct device *dev) 4801 { 4802 struct net_device *ndev = dev_get_drvdata(dev); 4803 struct fec_enet_private *fep = netdev_priv(ndev); 4804 int ret; 4805 4806 ret = clk_prepare_enable(fep->clk_ahb); 4807 if (ret) 4808 return ret; 4809 ret = clk_prepare_enable(fep->clk_ipg); 4810 if (ret) 4811 goto failed_clk_ipg; 4812 4813 return 0; 4814 4815 failed_clk_ipg: 4816 clk_disable_unprepare(fep->clk_ahb); 4817 return ret; 4818 } 4819 4820 static const struct dev_pm_ops fec_pm_ops = { 4821 SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4822 RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4823 }; 4824 4825 static struct platform_driver fec_driver = { 4826 .driver = { 4827 .name = DRIVER_NAME, 4828 .pm = pm_ptr(&fec_pm_ops), 4829 .of_match_table = fec_dt_ids, 4830 .suppress_bind_attrs = true, 4831 }, 4832 .id_table = fec_devtype, 4833 .probe = fec_probe, 4834 .remove = fec_drv_remove, 4835 }; 4836 4837 module_platform_driver(fec_driver); 4838 4839 MODULE_DESCRIPTION("NXP Fast Ethernet Controller (FEC) driver"); 4840 MODULE_LICENSE("GPL"); 4841