xref: /linux/drivers/net/ethernet/mellanox/mlx5/core/en/port.c (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /*
2  * Copyright (c) 2018, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include "port.h"
34 
mlx5_port_query_eth_autoneg(struct mlx5_core_dev * dev,u8 * an_status,u8 * an_disable_cap,u8 * an_disable_admin)35 void mlx5_port_query_eth_autoneg(struct mlx5_core_dev *dev, u8 *an_status,
36 				 u8 *an_disable_cap, u8 *an_disable_admin)
37 {
38 	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
39 
40 	*an_status = 0;
41 	*an_disable_cap = 0;
42 	*an_disable_admin = 0;
43 
44 	if (mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_EN, 1, 0))
45 		return;
46 
47 	*an_status = MLX5_GET(ptys_reg, out, an_status);
48 	*an_disable_cap = MLX5_GET(ptys_reg, out, an_disable_cap);
49 	*an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
50 }
51 
mlx5_port_set_eth_ptys(struct mlx5_core_dev * dev,bool an_disable,u32 proto_admin,bool ext)52 int mlx5_port_set_eth_ptys(struct mlx5_core_dev *dev, bool an_disable,
53 			   u32 proto_admin, bool ext)
54 {
55 	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
56 	u32 in[MLX5_ST_SZ_DW(ptys_reg)];
57 	u8 an_disable_admin;
58 	u8 an_disable_cap;
59 	u8 an_status;
60 
61 	mlx5_port_query_eth_autoneg(dev, &an_status, &an_disable_cap,
62 				    &an_disable_admin);
63 	if (!an_disable_cap && an_disable)
64 		return -EPERM;
65 
66 	memset(in, 0, sizeof(in));
67 
68 	MLX5_SET(ptys_reg, in, local_port, 1);
69 	MLX5_SET(ptys_reg, in, an_disable_admin, an_disable);
70 	MLX5_SET(ptys_reg, in, proto_mask, MLX5_PTYS_EN);
71 	if (ext)
72 		MLX5_SET(ptys_reg, in, ext_eth_proto_admin, proto_admin);
73 	else
74 		MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
75 
76 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
77 			    sizeof(out), MLX5_REG_PTYS, 0, 1);
78 }
79 
mlx5e_port_linkspeed(struct mlx5_core_dev * mdev,u32 * speed)80 int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
81 {
82 	struct mlx5_port_eth_proto eproto;
83 	bool force_legacy = false;
84 	bool ext;
85 	int err;
86 
87 	ext = mlx5_ptys_ext_supported(mdev);
88 	err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
89 	if (err)
90 		goto out;
91 	if (ext && !eproto.admin) {
92 		force_legacy = true;
93 		err = mlx5_port_query_eth_proto(mdev, 1, false, &eproto);
94 		if (err)
95 			goto out;
96 	}
97 	*speed = mlx5_port_ptys2speed(mdev, eproto.oper, force_legacy);
98 	if (!(*speed))
99 		err = -EINVAL;
100 
101 out:
102 	return err;
103 }
104 
mlx5e_port_query_pbmc(struct mlx5_core_dev * mdev,void * out)105 int mlx5e_port_query_pbmc(struct mlx5_core_dev *mdev, void *out)
106 {
107 	int sz = MLX5_ST_SZ_BYTES(pbmc_reg);
108 	void *in;
109 	int err;
110 
111 	in = kzalloc(sz, GFP_KERNEL);
112 	if (!in)
113 		return -ENOMEM;
114 
115 	MLX5_SET(pbmc_reg, in, local_port, 1);
116 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PBMC, 0, 0);
117 
118 	kfree(in);
119 	return err;
120 }
121 
mlx5e_port_set_pbmc(struct mlx5_core_dev * mdev,void * in)122 int mlx5e_port_set_pbmc(struct mlx5_core_dev *mdev, void *in)
123 {
124 	int sz = MLX5_ST_SZ_BYTES(pbmc_reg);
125 	void *out;
126 	int err;
127 
128 	out = kzalloc(sz, GFP_KERNEL);
129 	if (!out)
130 		return -ENOMEM;
131 
132 	MLX5_SET(pbmc_reg, in, local_port, 1);
133 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PBMC, 0, 1);
134 
135 	kfree(out);
136 	return err;
137 }
138 
mlx5e_port_query_sbpr(struct mlx5_core_dev * mdev,u32 desc,u8 dir,u8 pool_idx,void * out,int size_out)139 int mlx5e_port_query_sbpr(struct mlx5_core_dev *mdev, u32 desc, u8 dir,
140 			  u8 pool_idx, void *out, int size_out)
141 {
142 	u32 in[MLX5_ST_SZ_DW(sbpr_reg)] = {};
143 
144 	MLX5_SET(sbpr_reg, in, desc, desc);
145 	MLX5_SET(sbpr_reg, in, dir, dir);
146 	MLX5_SET(sbpr_reg, in, pool, pool_idx);
147 
148 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, size_out, MLX5_REG_SBPR, 0, 0);
149 }
150 
mlx5e_port_set_sbpr(struct mlx5_core_dev * mdev,u32 desc,u8 dir,u8 pool_idx,u32 infi_size,u32 size)151 int mlx5e_port_set_sbpr(struct mlx5_core_dev *mdev, u32 desc, u8 dir,
152 			u8 pool_idx, u32 infi_size, u32 size)
153 {
154 	u32 out[MLX5_ST_SZ_DW(sbpr_reg)] = {};
155 	u32 in[MLX5_ST_SZ_DW(sbpr_reg)] = {};
156 
157 	MLX5_SET(sbpr_reg, in, desc, desc);
158 	MLX5_SET(sbpr_reg, in, dir, dir);
159 	MLX5_SET(sbpr_reg, in, pool, pool_idx);
160 	MLX5_SET(sbpr_reg, in, infi_size, infi_size);
161 	MLX5_SET(sbpr_reg, in, size, size);
162 	MLX5_SET(sbpr_reg, in, mode, 1);
163 
164 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), MLX5_REG_SBPR, 0, 1);
165 }
166 
mlx5e_port_query_sbcm(struct mlx5_core_dev * mdev,u32 desc,u8 pg_buff_idx,u8 dir,void * out,int size_out)167 static int mlx5e_port_query_sbcm(struct mlx5_core_dev *mdev, u32 desc,
168 				 u8 pg_buff_idx, u8 dir, void *out,
169 				 int size_out)
170 {
171 	u32 in[MLX5_ST_SZ_DW(sbcm_reg)] = {};
172 
173 	MLX5_SET(sbcm_reg, in, desc, desc);
174 	MLX5_SET(sbcm_reg, in, local_port, 1);
175 	MLX5_SET(sbcm_reg, in, pg_buff, pg_buff_idx);
176 	MLX5_SET(sbcm_reg, in, dir, dir);
177 
178 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, size_out, MLX5_REG_SBCM, 0, 0);
179 }
180 
mlx5e_port_set_sbcm(struct mlx5_core_dev * mdev,u32 desc,u8 pg_buff_idx,u8 dir,u8 infi_size,u32 max_buff,u8 pool_idx)181 int mlx5e_port_set_sbcm(struct mlx5_core_dev *mdev, u32 desc, u8 pg_buff_idx,
182 			u8 dir, u8 infi_size, u32 max_buff, u8 pool_idx)
183 {
184 	u32 out[MLX5_ST_SZ_DW(sbcm_reg)] = {};
185 	u32 in[MLX5_ST_SZ_DW(sbcm_reg)] = {};
186 	u32 min_buff;
187 	int err;
188 	u8 exc;
189 
190 	err = mlx5e_port_query_sbcm(mdev, desc, pg_buff_idx, dir, out,
191 				    sizeof(out));
192 	if (err)
193 		return err;
194 
195 	exc = MLX5_GET(sbcm_reg, out, exc);
196 	min_buff = MLX5_GET(sbcm_reg, out, min_buff);
197 
198 	MLX5_SET(sbcm_reg, in, desc, desc);
199 	MLX5_SET(sbcm_reg, in, local_port, 1);
200 	MLX5_SET(sbcm_reg, in, pg_buff, pg_buff_idx);
201 	MLX5_SET(sbcm_reg, in, dir, dir);
202 	MLX5_SET(sbcm_reg, in, exc, exc);
203 	MLX5_SET(sbcm_reg, in, min_buff, min_buff);
204 	MLX5_SET(sbcm_reg, in, infi_max, infi_size);
205 	MLX5_SET(sbcm_reg, in, max_buff, max_buff);
206 	MLX5_SET(sbcm_reg, in, pool, pool_idx);
207 
208 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), MLX5_REG_SBCM, 0, 1);
209 }
210 
211 /* buffer[i]: buffer that priority i mapped to */
mlx5e_port_query_priority2buffer(struct mlx5_core_dev * mdev,u8 * buffer)212 int mlx5e_port_query_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
213 {
214 	int sz = MLX5_ST_SZ_BYTES(pptb_reg);
215 	u32 prio_x_buff;
216 	void *out;
217 	void *in;
218 	int prio;
219 	int err;
220 
221 	in = kzalloc(sz, GFP_KERNEL);
222 	out = kzalloc(sz, GFP_KERNEL);
223 	if (!in || !out) {
224 		err = -ENOMEM;
225 		goto out;
226 	}
227 
228 	MLX5_SET(pptb_reg, in, local_port, 1);
229 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0);
230 	if (err)
231 		goto out;
232 
233 	prio_x_buff = MLX5_GET(pptb_reg, out, prio_x_buff);
234 	for (prio = 0; prio < 8; prio++) {
235 		buffer[prio] = (u8)(prio_x_buff >> (4 * prio)) & 0xF;
236 		mlx5_core_dbg(mdev, "prio %d, buffer %d\n", prio, buffer[prio]);
237 	}
238 out:
239 	kfree(in);
240 	kfree(out);
241 	return err;
242 }
243 
mlx5e_port_set_priority2buffer(struct mlx5_core_dev * mdev,u8 * buffer)244 int mlx5e_port_set_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
245 {
246 	int sz = MLX5_ST_SZ_BYTES(pptb_reg);
247 	u32 prio_x_buff;
248 	void *out;
249 	void *in;
250 	int prio;
251 	int err;
252 
253 	in = kzalloc(sz, GFP_KERNEL);
254 	out = kzalloc(sz, GFP_KERNEL);
255 	if (!in || !out) {
256 		err = -ENOMEM;
257 		goto out;
258 	}
259 
260 	/* First query the pptb register */
261 	MLX5_SET(pptb_reg, in, local_port, 1);
262 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0);
263 	if (err)
264 		goto out;
265 
266 	memcpy(in, out, sz);
267 	MLX5_SET(pptb_reg, in, local_port, 1);
268 
269 	/* Update the pm and prio_x_buff */
270 	MLX5_SET(pptb_reg, in, pm, 0xFF);
271 
272 	prio_x_buff = 0;
273 	for (prio = 0; prio < 8; prio++)
274 		prio_x_buff |= (buffer[prio] << (4 * prio));
275 	MLX5_SET(pptb_reg, in, prio_x_buff, prio_x_buff);
276 
277 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 1);
278 
279 out:
280 	kfree(in);
281 	kfree(out);
282 	return err;
283 }
284 
285 enum mlx5e_fec_supported_link_mode {
286 	MLX5E_FEC_SUPPORTED_LINK_MODES_10G_40G,
287 	MLX5E_FEC_SUPPORTED_LINK_MODES_25G,
288 	MLX5E_FEC_SUPPORTED_LINK_MODES_50G,
289 	MLX5E_FEC_SUPPORTED_LINK_MODES_56G,
290 	MLX5E_FEC_SUPPORTED_LINK_MODES_100G,
291 	MLX5E_FEC_SUPPORTED_LINK_MODE_50G_1X,
292 	MLX5E_FEC_SUPPORTED_LINK_MODE_100G_2X,
293 	MLX5E_FEC_SUPPORTED_LINK_MODE_200G_4X,
294 	MLX5E_FEC_SUPPORTED_LINK_MODE_400G_8X,
295 	MLX5E_FEC_SUPPORTED_LINK_MODE_100G_1X,
296 	MLX5E_FEC_SUPPORTED_LINK_MODE_200G_2X,
297 	MLX5E_FEC_SUPPORTED_LINK_MODE_400G_4X,
298 	MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X,
299 	MLX5E_MAX_FEC_SUPPORTED_LINK_MODE,
300 };
301 
302 #define MLX5E_FEC_FIRST_50G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_50G_1X
303 #define MLX5E_FEC_FIRST_100G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_100G_1X
304 
305 #define MLX5E_FEC_OVERRIDE_ADMIN_POLICY(buf, policy, write, link)			\
306 	do {										\
307 		u16 *_policy = &(policy);						\
308 		u32 *_buf = buf;							\
309 											\
310 		if (write)								\
311 			MLX5_SET(pplm_reg, _buf, fec_override_admin_##link, *_policy);	\
312 		else									\
313 			*_policy = MLX5_GET(pplm_reg, _buf, fec_override_admin_##link);	\
314 	} while (0)
315 
316 /* Returns true if FEC can be set for a given link mode. */
mlx5e_is_fec_supported_link_mode(struct mlx5_core_dev * dev,enum mlx5e_fec_supported_link_mode link_mode)317 static bool mlx5e_is_fec_supported_link_mode(struct mlx5_core_dev *dev,
318 					     enum mlx5e_fec_supported_link_mode link_mode)
319 {
320 	return link_mode < MLX5E_FEC_FIRST_50G_PER_LANE_MODE ||
321 	       (link_mode < MLX5E_FEC_FIRST_100G_PER_LANE_MODE &&
322 		MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm)) ||
323 	       (link_mode >= MLX5E_FEC_FIRST_100G_PER_LANE_MODE &&
324 		MLX5_CAP_PCAM_FEATURE(dev, fec_100G_per_lane_in_pplm));
325 }
326 
327 /* get/set FEC admin field for a given speed */
mlx5e_fec_admin_field(u32 * pplm,u16 * fec_policy,bool write,enum mlx5e_fec_supported_link_mode link_mode)328 static int mlx5e_fec_admin_field(u32 *pplm, u16 *fec_policy, bool write,
329 				 enum mlx5e_fec_supported_link_mode link_mode)
330 {
331 	switch (link_mode) {
332 	case MLX5E_FEC_SUPPORTED_LINK_MODES_10G_40G:
333 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 10g_40g);
334 		break;
335 	case MLX5E_FEC_SUPPORTED_LINK_MODES_25G:
336 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 25g);
337 		break;
338 	case MLX5E_FEC_SUPPORTED_LINK_MODES_50G:
339 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 50g);
340 		break;
341 	case MLX5E_FEC_SUPPORTED_LINK_MODES_56G:
342 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 56g);
343 		break;
344 	case MLX5E_FEC_SUPPORTED_LINK_MODES_100G:
345 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 100g);
346 		break;
347 	case MLX5E_FEC_SUPPORTED_LINK_MODE_50G_1X:
348 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 50g_1x);
349 		break;
350 	case MLX5E_FEC_SUPPORTED_LINK_MODE_100G_2X:
351 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 100g_2x);
352 		break;
353 	case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_4X:
354 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 200g_4x);
355 		break;
356 	case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_8X:
357 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 400g_8x);
358 		break;
359 	case MLX5E_FEC_SUPPORTED_LINK_MODE_100G_1X:
360 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 100g_1x);
361 		break;
362 	case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_2X:
363 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 200g_2x);
364 		break;
365 	case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_4X:
366 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 400g_4x);
367 		break;
368 	case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X:
369 		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 800g_8x);
370 		break;
371 	default:
372 		return -EINVAL;
373 	}
374 	return 0;
375 }
376 
377 #define MLX5E_GET_FEC_OVERRIDE_CAP(buf, link)  \
378 	MLX5_GET(pplm_reg, buf, fec_override_cap_##link)
379 
380 /* returns FEC capabilities for a given speed */
mlx5e_get_fec_cap_field(u32 * pplm,u16 * fec_cap,enum mlx5e_fec_supported_link_mode link_mode)381 static int mlx5e_get_fec_cap_field(u32 *pplm, u16 *fec_cap,
382 				   enum mlx5e_fec_supported_link_mode link_mode)
383 {
384 	switch (link_mode) {
385 	case MLX5E_FEC_SUPPORTED_LINK_MODES_10G_40G:
386 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 10g_40g);
387 		break;
388 	case MLX5E_FEC_SUPPORTED_LINK_MODES_25G:
389 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 25g);
390 		break;
391 	case MLX5E_FEC_SUPPORTED_LINK_MODES_50G:
392 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 50g);
393 		break;
394 	case MLX5E_FEC_SUPPORTED_LINK_MODES_56G:
395 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 56g);
396 		break;
397 	case MLX5E_FEC_SUPPORTED_LINK_MODES_100G:
398 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 100g);
399 		break;
400 	case MLX5E_FEC_SUPPORTED_LINK_MODE_50G_1X:
401 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 50g_1x);
402 		break;
403 	case MLX5E_FEC_SUPPORTED_LINK_MODE_100G_2X:
404 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 100g_2x);
405 		break;
406 	case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_4X:
407 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 200g_4x);
408 		break;
409 	case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_8X:
410 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 400g_8x);
411 		break;
412 	case MLX5E_FEC_SUPPORTED_LINK_MODE_100G_1X:
413 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 100g_1x);
414 		break;
415 	case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_2X:
416 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 200g_2x);
417 		break;
418 	case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_4X:
419 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 400g_4x);
420 		break;
421 	case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X:
422 		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 800g_8x);
423 		break;
424 	default:
425 		return -EINVAL;
426 	}
427 	return 0;
428 }
429 
mlx5e_fec_in_caps(struct mlx5_core_dev * dev,int fec_policy)430 bool mlx5e_fec_in_caps(struct mlx5_core_dev *dev, int fec_policy)
431 {
432 	u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
433 	u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
434 	int sz = MLX5_ST_SZ_BYTES(pplm_reg);
435 	int err;
436 	int i;
437 
438 	if (!MLX5_CAP_GEN(dev, pcam_reg) || !MLX5_CAP_PCAM_REG(dev, pplm))
439 		return false;
440 
441 	MLX5_SET(pplm_reg, in, local_port, 1);
442 	err =  mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
443 	if (err)
444 		return false;
445 
446 	for (i = 0; i < MLX5E_MAX_FEC_SUPPORTED_LINK_MODE; i++) {
447 		u16 fec_caps;
448 
449 		if (!mlx5e_is_fec_supported_link_mode(dev, i))
450 			break;
451 
452 		mlx5e_get_fec_cap_field(out, &fec_caps, i);
453 		if (fec_caps & fec_policy)
454 			return true;
455 	}
456 	return false;
457 }
458 
mlx5e_get_fec_mode(struct mlx5_core_dev * dev,u32 * fec_mode_active,u16 * fec_configured_mode)459 int mlx5e_get_fec_mode(struct mlx5_core_dev *dev, u32 *fec_mode_active,
460 		       u16 *fec_configured_mode)
461 {
462 	u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
463 	u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
464 	int sz = MLX5_ST_SZ_BYTES(pplm_reg);
465 	int err;
466 	int i;
467 
468 	if (!MLX5_CAP_GEN(dev, pcam_reg))
469 		return -EOPNOTSUPP;
470 
471 	if (!MLX5_CAP_PCAM_REG(dev, pplm))
472 		return -EOPNOTSUPP;
473 
474 	MLX5_SET(pplm_reg, in, local_port, 1);
475 	err =  mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
476 	if (err)
477 		return err;
478 
479 	*fec_mode_active = MLX5_GET(pplm_reg, out, fec_mode_active);
480 
481 	if (!fec_configured_mode)
482 		goto out;
483 
484 	*fec_configured_mode = 0;
485 	for (i = 0; i < MLX5E_MAX_FEC_SUPPORTED_LINK_MODE; i++) {
486 		if (!mlx5e_is_fec_supported_link_mode(dev, i))
487 			break;
488 
489 		mlx5e_fec_admin_field(out, fec_configured_mode, 0, i);
490 		if (*fec_configured_mode != 0)
491 			goto out;
492 	}
493 out:
494 	return 0;
495 }
496 
mlx5e_set_fec_mode(struct mlx5_core_dev * dev,u16 fec_policy)497 int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy)
498 {
499 	bool fec_50g_per_lane = MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm);
500 	u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
501 	u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
502 	int sz = MLX5_ST_SZ_BYTES(pplm_reg);
503 	u16 fec_policy_auto = 0;
504 	int err;
505 	int i;
506 
507 	if (!MLX5_CAP_GEN(dev, pcam_reg))
508 		return -EOPNOTSUPP;
509 
510 	if (!MLX5_CAP_PCAM_REG(dev, pplm))
511 		return -EOPNOTSUPP;
512 
513 	if (fec_policy >= (1 << MLX5E_FEC_LLRS_272_257_1) && !fec_50g_per_lane)
514 		return -EOPNOTSUPP;
515 
516 	if (fec_policy && !mlx5e_fec_in_caps(dev, fec_policy))
517 		return -EOPNOTSUPP;
518 
519 	MLX5_SET(pplm_reg, in, local_port, 1);
520 	err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
521 	if (err)
522 		return err;
523 
524 	MLX5_SET(pplm_reg, out, local_port, 1);
525 
526 	for (i = 0; i < MLX5E_MAX_FEC_SUPPORTED_LINK_MODE; i++) {
527 		u16 conf_fec = fec_policy;
528 		u16 fec_caps = 0;
529 
530 		if (!mlx5e_is_fec_supported_link_mode(dev, i))
531 			break;
532 
533 		/* RS fec in ethtool is mapped to MLX5E_FEC_RS_528_514
534 		 * to link modes up to 25G per lane and to
535 		 * MLX5E_FEC_RS_544_514 in the new link modes based on
536 		 * 50G or 100G per lane
537 		 */
538 		if (conf_fec == (1 << MLX5E_FEC_RS_528_514) &&
539 		    i >= MLX5E_FEC_FIRST_50G_PER_LANE_MODE)
540 			conf_fec = (1 << MLX5E_FEC_RS_544_514);
541 
542 		mlx5e_get_fec_cap_field(out, &fec_caps, i);
543 
544 		/* policy supported for link speed */
545 		if (fec_caps & conf_fec)
546 			mlx5e_fec_admin_field(out, &conf_fec, 1, i);
547 		else
548 			/* set FEC to auto*/
549 			mlx5e_fec_admin_field(out, &fec_policy_auto, 1, i);
550 	}
551 
552 	return mlx5_core_access_reg(dev, out, sz, out, sz, MLX5_REG_PPLM, 0, 1);
553 }
554