xref: /linux/drivers/net/ethernet/airoha/airoha_eth.h (revision 7e170da2edec9fb0717543571cc14b0aabee2b46) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2024 AIROHA Inc
4  * Author: Lorenzo Bianconi <lorenzo@kernel.org>
5  */
6 
7 #ifndef AIROHA_ETH_H
8 #define AIROHA_ETH_H
9 
10 #include <linux/debugfs.h>
11 #include <linux/etherdevice.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/netdevice.h>
15 #include <linux/reset.h>
16 #include <linux/soc/airoha/airoha_offload.h>
17 #include <net/dsa.h>
18 
19 #define AIROHA_MAX_NUM_GDM_PORTS	4
20 #define AIROHA_MAX_NUM_GDM_DEVS		2
21 #define AIROHA_MAX_NUM_QDMA		2
22 #define AIROHA_MAX_NUM_IRQ_BANKS	4
23 #define AIROHA_MAX_DSA_PORTS		7
24 #define AIROHA_MAX_NUM_RSTS		3
25 #define AIROHA_MAX_MTU			9220
26 #define AIROHA_MAX_RX_SIZE		16128
27 #define AIROHA_MAX_PACKET_SIZE		2048
28 #define AIROHA_NUM_QOS_CHANNELS		4
29 #define AIROHA_NUM_QOS_QUEUES		8
30 #define AIROHA_NUM_TX_RING		32
31 #define AIROHA_NUM_RX_RING		32
32 #define AIROHA_NUM_NETDEV_TX_RINGS	(AIROHA_NUM_TX_RING + \
33 					 AIROHA_NUM_QOS_CHANNELS)
34 #define AIROHA_FE_MC_MAX_VLAN_TABLE	64
35 #define AIROHA_FE_MC_MAX_VLAN_PORT	16
36 #define AIROHA_NUM_TX_IRQ		2
37 #define AIROHA_RX_HEADROOM		(NET_SKB_PAD + NET_IP_ALIGN)
38 #define AIROHA_RX_LEN(_n)		((_n) - AIROHA_RX_HEADROOM)
39 #define HW_DSCP_NUM			2048
40 #define IRQ_QUEUE_LEN(_n)		((_n) ? 1024 : 2048)
41 #define TX_DSCP_NUM			1024
42 #define RX_DSCP_NUM(_n)			\
43 	((_n) ==  2 ? 128 :		\
44 	 (_n) == 11 ? 128 :		\
45 	 (_n) == 15 ? 128 :		\
46 	 (_n) ==  0 ? 1024 : 16)
47 
48 #define PSE_RSV_PAGES			128
49 #define PSE_QUEUE_RSV_PAGES		64
50 
51 #define QDMA_METER_IDX(_n)		((_n) & 0xff)
52 #define QDMA_METER_GROUP(_n)		(((_n) >> 8) & 0x3)
53 
54 #define PPE_SRAM_NUM_ENTRIES		(8 * 1024)
55 #define PPE_STATS_NUM_ENTRIES		(4 * 1024)
56 #define PPE_DRAM_NUM_ENTRIES		(16 * 1024)
57 #define PPE_ENTRY_SIZE			80
58 #define PPE_RAM_NUM_ENTRIES_SHIFT(_n)	(__ffs((_n) >> 10))
59 
60 #define MTK_HDR_LEN			4
61 #define MTK_HDR_XMIT_TAGGED_TPID_8100	1
62 #define MTK_HDR_XMIT_TAGGED_TPID_88A8	2
63 
64 enum {
65 	QDMA_INT_REG_IDX0,
66 	QDMA_INT_REG_IDX1,
67 	QDMA_INT_REG_IDX2,
68 	QDMA_INT_REG_IDX3,
69 	QDMA_INT_REG_IDX4,
70 	QDMA_INT_REG_MAX
71 };
72 
73 enum {
74 	HSGMII_LAN_7581_PCIE0_SRCPORT	= 0x16,
75 	HSGMII_LAN_7581_PCIE1_SRCPORT,
76 	HSGMII_LAN_7581_ETH_SRCPORT,
77 	HSGMII_LAN_7581_USB_SRCPORT,
78 };
79 
80 enum {
81 	HSGMII_LAN_7583_ETH_SRCPORT	= 0x16,
82 	HSGMII_LAN_7583_PCIE_SRCPORT	= 0x18,
83 	HSGMII_LAN_7583_USB_SRCPORT,
84 };
85 
86 enum {
87 	XSI_PCIE0_VIP_PORT_MASK	= BIT(22),
88 	XSI_PCIE1_VIP_PORT_MASK	= BIT(23),
89 	XSI_USB_VIP_PORT_MASK	= BIT(25),
90 	XSI_ETH_VIP_PORT_MASK	= BIT(24),
91 };
92 
93 enum {
94 	DEV_STATE_INITIALIZED,
95 	DEV_STATE_REGISTERED,
96 };
97 
98 enum {
99 	CDM_CRSN_QSEL_Q1 = 1,
100 	CDM_CRSN_QSEL_Q5 = 5,
101 	CDM_CRSN_QSEL_Q6 = 6,
102 	CDM_CRSN_QSEL_Q15 = 15,
103 };
104 
105 enum {
106 	CRSN_08 = 0x8,
107 	CRSN_21 = 0x15, /* KA */
108 	CRSN_22 = 0x16, /* hit bind and force route to CPU */
109 	CRSN_24 = 0x18,
110 	CRSN_25 = 0x19,
111 };
112 
113 enum airoha_gdm_index {
114 	AIROHA_GDM1_IDX = 1,
115 	AIROHA_GDM2_IDX = 2,
116 	AIROHA_GDM3_IDX = 3,
117 	AIROHA_GDM4_IDX = 4,
118 };
119 
120 enum {
121 	FE_PSE_PORT_CDM1,
122 	FE_PSE_PORT_GDM1,
123 	FE_PSE_PORT_GDM2,
124 	FE_PSE_PORT_GDM3,
125 	FE_PSE_PORT_PPE1,
126 	FE_PSE_PORT_CDM2,
127 	FE_PSE_PORT_CDM3,
128 	FE_PSE_PORT_CDM4,
129 	FE_PSE_PORT_PPE2,
130 	FE_PSE_PORT_GDM4,
131 	FE_PSE_PORT_CDM5,
132 	FE_PSE_PORT_DROP = 0xf,
133 };
134 
135 enum tx_sched_mode {
136 	TC_SCH_WRR8,
137 	TC_SCH_SP,
138 	TC_SCH_WRR7,
139 	TC_SCH_WRR6,
140 	TC_SCH_WRR5,
141 	TC_SCH_WRR4,
142 	TC_SCH_WRR3,
143 	TC_SCH_WRR2,
144 };
145 
146 enum trtcm_unit_type {
147 	TRTCM_BYTE_UNIT,
148 	TRTCM_PACKET_UNIT,
149 };
150 
151 enum trtcm_param_type {
152 	TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */
153 	TRTCM_TOKEN_RATE_MODE,
154 	TRTCM_BUCKETSIZE_SHIFT_MODE,
155 	TRTCM_BUCKET_COUNTER_MODE,
156 };
157 
158 enum trtcm_mode_type {
159 	TRTCM_COMMIT_MODE,
160 	TRTCM_PEAK_MODE,
161 };
162 
163 enum trtcm_param {
164 	TRTCM_TICK_SEL = BIT(0),
165 	TRTCM_PKT_MODE = BIT(1),
166 	TRTCM_METER_MODE = BIT(2),
167 };
168 
169 #define MIN_TOKEN_SIZE				4096
170 #define MAX_TOKEN_SIZE_OFFSET			17
171 #define TRTCM_TOKEN_RATE_MASK			GENMASK(23, 6)
172 #define TRTCM_TOKEN_RATE_FRACTION_MASK		GENMASK(5, 0)
173 
174 #define TRTCM_CONFIG_RETRY_MAX			2
175 
176 enum airoha_dma_map_type {
177 	AIROHA_DMA_UNMAPPED,
178 	AIROHA_DMA_MAP_SINGLE,
179 	AIROHA_DMA_MAP_PAGE,
180 };
181 
182 struct airoha_queue_entry {
183 	union {
184 		void *buf;
185 		struct {
186 			struct list_head list;
187 			struct sk_buff *skb;
188 			enum airoha_dma_map_type dma_type;
189 		};
190 	};
191 	dma_addr_t dma_addr;
192 	u16 dma_len;
193 };
194 
195 struct airoha_queue {
196 	struct airoha_qdma *qdma;
197 
198 	/* protect concurrent queue accesses */
199 	spinlock_t lock;
200 	struct airoha_queue_entry *entry;
201 	struct airoha_qdma_desc *desc;
202 	u16 head;
203 	u16 tail;
204 
205 	int queued;
206 	int ndesc;
207 	int free_thr;
208 	int buf_size;
209 	bool txq_stopped;
210 	bool flushing;
211 
212 	struct napi_struct napi;
213 	struct page_pool *page_pool;
214 	struct sk_buff *skb;
215 
216 	struct list_head tx_list;
217 };
218 
219 struct airoha_tx_irq_queue {
220 	struct airoha_qdma *qdma;
221 
222 	struct napi_struct napi;
223 
224 	int size;
225 	u32 *q;
226 };
227 
228 struct airoha_hw_stats {
229 	struct u64_stats_sync syncp;
230 
231 	/* get_stats64 */
232 	u64 rx_ok_pkts;
233 	u64 tx_ok_pkts;
234 	u64 rx_ok_bytes;
235 	u64 tx_ok_bytes;
236 	u64 rx_multicast;
237 	u64 rx_errors;
238 	u64 rx_drops;
239 	u64 tx_drops;
240 	u64 rx_crc_error;
241 	u64 rx_over_errors;
242 	/* ethtool stats */
243 	u64 tx_broadcast;
244 	u64 tx_multicast;
245 	u64 tx_len[7];
246 	u64 rx_broadcast;
247 	u64 rx_fragment;
248 	u64 rx_jabber;
249 	u64 rx_len[7];
250 
251 	struct {
252 		/* Previous HW register values for 32-bit counter delta
253 		 * tracking. Storing the last seen value and accumulating
254 		 * (u32)(curr - prev) into the 64-bit software counter
255 		 * handles wrap-around transparently via unsigned arithmetic.
256 		 * tx_runt64/rx_runt64 hold the running sum of runt deltas.
257 		 * These fields are never reported to userspace.
258 		 */
259 		u32 tx_drops;
260 		u32 tx_broadcast;
261 		u32 tx_multicast;
262 		u32 tx_runt;
263 		u32 tx_long;
264 		u64 tx_runt64;
265 		u32 rx_drops;
266 		u32 rx_broadcast;
267 		u32 rx_multicast;
268 		u32 rx_errors;
269 		u32 rx_crc_error;
270 		u32 rx_over_errors;
271 		u32 rx_fragment;
272 		u32 rx_jabber;
273 		u32 rx_runt;
274 		u32 rx_long;
275 		u64 rx_runt64;
276 	} mib_prev;
277 };
278 
279 enum {
280 	AIROHA_FOE_STATE_INVALID,
281 	AIROHA_FOE_STATE_UNBIND,
282 	AIROHA_FOE_STATE_BIND,
283 	AIROHA_FOE_STATE_FIN
284 };
285 
286 enum {
287 	PPE_PKT_TYPE_IPV4_HNAPT = 0,
288 	PPE_PKT_TYPE_IPV4_ROUTE = 1,
289 	PPE_PKT_TYPE_BRIDGE = 2,
290 	PPE_PKT_TYPE_IPV4_DSLITE = 3,
291 	PPE_PKT_TYPE_IPV6_ROUTE_3T = 4,
292 	PPE_PKT_TYPE_IPV6_ROUTE_5T = 5,
293 	PPE_PKT_TYPE_IPV6_6RD = 7,
294 };
295 
296 #define AIROHA_FOE_MAC_SMAC_ID		GENMASK(20, 16)
297 #define AIROHA_FOE_MAC_PPPOE_ID		GENMASK(15, 0)
298 
299 #define AIROHA_FOE_MAC_WDMA_QOS		GENMASK(15, 12)
300 #define AIROHA_FOE_MAC_WDMA_BAND	BIT(11)
301 #define AIROHA_FOE_MAC_WDMA_WCID	GENMASK(10, 0)
302 
303 struct airoha_foe_mac_info_common {
304 	u16 vlan1;
305 	u16 etype;
306 
307 	u32 dest_mac_hi;
308 
309 	u16 vlan2;
310 	u16 dest_mac_lo;
311 
312 	u32 src_mac_hi;
313 };
314 
315 struct airoha_foe_mac_info {
316 	struct airoha_foe_mac_info_common common;
317 
318 	u16 pppoe_id;
319 	u16 src_mac_lo;
320 
321 	u32 meter;
322 };
323 
324 #define AIROHA_FOE_IB1_UNBIND_PREBIND		BIT(24)
325 #define AIROHA_FOE_IB1_UNBIND_PACKETS		GENMASK(23, 8)
326 #define AIROHA_FOE_IB1_UNBIND_TIMESTAMP		GENMASK(7, 0)
327 
328 #define AIROHA_FOE_IB1_BIND_STATIC		BIT(31)
329 #define AIROHA_FOE_IB1_BIND_UDP			BIT(30)
330 #define AIROHA_FOE_IB1_BIND_STATE		GENMASK(29, 28)
331 #define AIROHA_FOE_IB1_BIND_PACKET_TYPE		GENMASK(27, 25)
332 #define AIROHA_FOE_IB1_BIND_TTL			BIT(24)
333 #define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP	BIT(23)
334 #define AIROHA_FOE_IB1_BIND_PPPOE		BIT(22)
335 #define AIROHA_FOE_IB1_BIND_VPM			GENMASK(21, 20)
336 #define AIROHA_FOE_IB1_BIND_VLAN_LAYER		GENMASK(19, 16)
337 #define AIROHA_FOE_IB1_BIND_KEEPALIVE		BIT(15)
338 #define AIROHA_FOE_IB1_BIND_TIMESTAMP		GENMASK(14, 0)
339 
340 #define AIROHA_FOE_IB2_DSCP			GENMASK(31, 24)
341 #define AIROHA_FOE_IB2_PORT_AG			GENMASK(23, 13)
342 #define AIROHA_FOE_IB2_PCP			BIT(12)
343 #define AIROHA_FOE_IB2_MULTICAST		BIT(11)
344 #define AIROHA_FOE_IB2_FAST_PATH		BIT(10)
345 #define AIROHA_FOE_IB2_PSE_QOS			BIT(9)
346 #define AIROHA_FOE_IB2_PSE_PORT			GENMASK(8, 5)
347 #define AIROHA_FOE_IB2_NBQ			GENMASK(4, 0)
348 
349 #define AIROHA_FOE_ACTDP			GENMASK(31, 24)
350 #define AIROHA_FOE_SHAPER_ID			GENMASK(23, 16)
351 #define AIROHA_FOE_CHANNEL			GENMASK(15, 11)
352 #define AIROHA_FOE_QID				GENMASK(10, 8)
353 #define AIROHA_FOE_DPI				BIT(7)
354 #define AIROHA_FOE_TUNNEL			BIT(6)
355 #define AIROHA_FOE_TUNNEL_ID			GENMASK(5, 0)
356 
357 #define AIROHA_FOE_TUNNEL_MTU			GENMASK(31, 16)
358 #define AIROHA_FOE_ACNT_GRP3			GENMASK(15, 9)
359 #define AIROHA_FOE_METER_GRP3			GENMASK(8, 5)
360 #define AIROHA_FOE_METER_GRP2			GENMASK(4, 0)
361 
362 struct airoha_foe_bridge {
363 	u32 dest_mac_hi;
364 
365 	u16 src_mac_hi;
366 	u16 dest_mac_lo;
367 
368 	u32 src_mac_lo;
369 
370 	u32 ib2;
371 
372 	u32 rsv[5];
373 
374 	u32 data;
375 
376 	struct airoha_foe_mac_info l2;
377 };
378 
379 struct airoha_foe_ipv4_tuple {
380 	u32 src_ip;
381 	u32 dest_ip;
382 	union {
383 		struct {
384 			u16 dest_port;
385 			u16 src_port;
386 		};
387 		struct {
388 			u8 protocol;
389 			u8 _pad[3]; /* fill with 0xa5a5a5 */
390 		};
391 		u32 ports;
392 	};
393 };
394 
395 struct airoha_foe_ipv4 {
396 	struct airoha_foe_ipv4_tuple orig_tuple;
397 
398 	u32 ib2;
399 
400 	struct airoha_foe_ipv4_tuple new_tuple;
401 
402 	u32 rsv[2];
403 
404 	u32 data;
405 
406 	struct airoha_foe_mac_info l2;
407 };
408 
409 struct airoha_foe_ipv4_dslite {
410 	struct airoha_foe_ipv4_tuple ip4;
411 
412 	u32 ib2;
413 
414 	u8 flow_label[3];
415 	u8 priority;
416 
417 	u32 rsv[4];
418 
419 	u32 data;
420 
421 	struct airoha_foe_mac_info l2;
422 };
423 
424 struct airoha_foe_ipv6 {
425 	u32 src_ip[4];
426 	u32 dest_ip[4];
427 
428 	union {
429 		struct {
430 			u16 dest_port;
431 			u16 src_port;
432 		};
433 		struct {
434 			u8 protocol;
435 			u8 pad[3];
436 		};
437 		u32 ports;
438 	};
439 
440 	u32 data;
441 
442 	u32 ib2;
443 
444 	struct airoha_foe_mac_info_common l2;
445 
446 	u32 meter;
447 };
448 
449 struct airoha_foe_entry {
450 	union {
451 		struct {
452 			u32 ib1;
453 			union {
454 				struct airoha_foe_bridge bridge;
455 				struct airoha_foe_ipv4 ipv4;
456 				struct airoha_foe_ipv4_dslite dslite;
457 				struct airoha_foe_ipv6 ipv6;
458 				DECLARE_FLEX_ARRAY(u32, d);
459 			};
460 		};
461 		u8 data[PPE_ENTRY_SIZE];
462 	};
463 };
464 
465 struct airoha_foe_stats {
466 	u32 bytes;
467 	u32 packets;
468 };
469 
470 struct airoha_foe_stats64 {
471 	u64 bytes;
472 	u64 packets;
473 };
474 
475 struct airoha_flow_data {
476 	struct ethhdr eth;
477 
478 	union {
479 		struct {
480 			__be32 src_addr;
481 			__be32 dst_addr;
482 		} v4;
483 
484 		struct {
485 			struct in6_addr src_addr;
486 			struct in6_addr dst_addr;
487 		} v6;
488 	};
489 
490 	__be16 src_port;
491 	__be16 dst_port;
492 
493 	struct {
494 		struct {
495 			u16 id;
496 			__be16 proto;
497 		} hdr[2];
498 		u8 num;
499 	} vlan;
500 	struct {
501 		u16 sid;
502 		u8 num;
503 	} pppoe;
504 };
505 
506 enum airoha_flow_entry_type {
507 	FLOW_TYPE_L4,
508 	FLOW_TYPE_L2,
509 	FLOW_TYPE_L2_SUBFLOW,
510 };
511 
512 struct airoha_flow_table_entry {
513 	union {
514 		struct hlist_node list; /* PPE L3 flow entry */
515 		struct {
516 			struct rhash_head l2_node;  /* L2 flow entry */
517 			struct hlist_head l2_flows; /* PPE L2 subflows list */
518 		};
519 	};
520 
521 	struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */
522 	u32 hash;
523 
524 	struct airoha_foe_stats64 stats;
525 	enum airoha_flow_entry_type type;
526 
527 	struct rhash_head node;
528 	unsigned long cookie;
529 
530 	/* Must be last --ends in a flexible-array member. */
531 	struct airoha_foe_entry data;
532 };
533 
534 struct airoha_wdma_info {
535 	u8 idx;
536 	u8 queue;
537 	u16 wcid;
538 	u8 bss;
539 };
540 
541 /* RX queue to IRQ mapping: BIT(q) in IRQ(n) */
542 #define RX_IRQ0_BANK_PIN_MASK			0x839f
543 #define RX_IRQ1_BANK_PIN_MASK			0xffe00000
544 #define RX_IRQ2_BANK_PIN_MASK			0x20
545 #define RX_IRQ3_BANK_PIN_MASK			0x40
546 #define RX_IRQ_BANK_PIN_MASK(_n)		\
547 	(((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK :	\
548 	 ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK :	\
549 	 ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK :	\
550 	 RX_IRQ0_BANK_PIN_MASK)
551 
552 struct airoha_irq_bank {
553 	struct airoha_qdma *qdma;
554 
555 	/* protect concurrent irqmask accesses */
556 	spinlock_t irq_lock;
557 	u32 irqmask[QDMA_INT_REG_MAX];
558 	int irq;
559 };
560 
561 struct airoha_qdma {
562 	struct airoha_eth *eth;
563 	void __iomem *regs;
564 
565 	struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS];
566 
567 	struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ];
568 
569 	struct airoha_queue q_tx[AIROHA_NUM_TX_RING];
570 	struct airoha_queue q_rx[AIROHA_NUM_RX_RING];
571 
572 	DECLARE_BITMAP(qos_channel_map, AIROHA_NUM_QOS_CHANNELS);
573 };
574 
575 enum airoha_dev_flags {
576 	AIROHA_DEV_F_WAN,
577 	AIROHA_DEV_F_TX_QOS,
578 };
579 
580 struct airoha_gdm_dev {
581 	struct airoha_qdma __rcu *qdma;
582 	struct airoha_gdm_port *port;
583 	struct airoha_eth *eth;
584 
585 	DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
586 	struct {
587 		u32 cpu_tx_packets;
588 		u32 fwd_tx_packets;
589 	} qos_stats[AIROHA_NUM_QOS_CHANNELS];
590 
591 	unsigned long flags;
592 	int nbq;
593 
594 	struct airoha_hw_stats stats;
595 
596 	/* Serialize netdev_tx_completed_queue() calls per TX queue during
597 	 * QDMA migration.
598 	 */
599 	spinlock_t txq_lock[AIROHA_NUM_NETDEV_TX_RINGS];
600 };
601 
602 struct airoha_gdm_port {
603 	struct airoha_gdm_dev *devs[AIROHA_MAX_NUM_GDM_DEVS];
604 	int id;
605 	int users;
606 
607 	/* protect concurrent hw_stats accesses */
608 	spinlock_t stats_lock;
609 
610 	struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];
611 };
612 
613 #define AIROHA_RXD4_PPE_CPU_REASON	GENMASK(20, 16)
614 #define AIROHA_RXD4_FOE_ENTRY		GENMASK(15, 0)
615 
616 struct airoha_ppe {
617 	struct airoha_ppe_dev dev;
618 	struct airoha_eth *eth;
619 
620 	void *foe;
621 	dma_addr_t foe_dma;
622 
623 	struct rhashtable l2_flows;
624 
625 	struct hlist_head *foe_flow;
626 	u16 *foe_check_time;
627 
628 	struct airoha_foe_stats *foe_stats;
629 	dma_addr_t foe_stats_dma;
630 
631 	struct dentry *debugfs_dir;
632 };
633 
634 struct airoha_eth_soc_data {
635 	u16 version;
636 	const char * const *xsi_rsts_names;
637 	int num_xsi_rsts;
638 	int num_ppe;
639 	struct {
640 		int (*get_sport)(struct airoha_gdm_port *port, int nbq);
641 		u32 (*get_vip_port)(struct airoha_gdm_port *port, int nbq);
642 		int (*get_dev_from_sport)(struct airoha_qdma_desc *desc,
643 					  u16 *port, u16 *dev);
644 	} ops;
645 };
646 
647 struct airoha_eth {
648 	struct device *dev;
649 
650 	const struct airoha_eth_soc_data *soc;
651 
652 	unsigned long state;
653 	void __iomem *fe_regs;
654 
655 	struct airoha_npu __rcu *npu;
656 
657 	struct airoha_ppe *ppe;
658 	struct rhashtable flow_table;
659 
660 	struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS];
661 	struct reset_control_bulk_data *xsi_rsts;
662 
663 	struct net_device *napi_dev;
664 
665 	struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA];
666 	struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS];
667 };
668 
669 u32 airoha_rr(void __iomem *base, u32 offset);
670 void airoha_wr(void __iomem *base, u32 offset, u32 val);
671 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
672 
673 #define airoha_fe_rr(eth, offset)				\
674 	airoha_rr((eth)->fe_regs, (offset))
675 #define airoha_fe_wr(eth, offset, val)				\
676 	airoha_wr((eth)->fe_regs, (offset), (val))
677 #define airoha_fe_rmw(eth, offset, mask, val)			\
678 	airoha_rmw((eth)->fe_regs, (offset), (mask), (val))
679 #define airoha_fe_set(eth, offset, val)				\
680 	airoha_rmw((eth)->fe_regs, (offset), 0, (val))
681 #define airoha_fe_clear(eth, offset, val)			\
682 	airoha_rmw((eth)->fe_regs, (offset), (val), 0)
683 #define airoha_fe_get(eth, offset, mask)			\
684 	FIELD_GET((mask), airoha_fe_rr((eth), (offset)))
685 
686 #define airoha_qdma_rr(qdma, offset)				\
687 	airoha_rr((qdma)->regs, (offset))
688 #define airoha_qdma_wr(qdma, offset, val)			\
689 	airoha_wr((qdma)->regs, (offset), (val))
690 #define airoha_qdma_rmw(qdma, offset, mask, val)		\
691 	airoha_rmw((qdma)->regs, (offset), (mask), (val))
692 #define airoha_qdma_set(qdma, offset, val)			\
693 	airoha_rmw((qdma)->regs, (offset), 0, (val))
694 #define airoha_qdma_clear(qdma, offset, val)			\
695 	airoha_rmw((qdma)->regs, (offset), (val), 0)
696 #define airoha_qdma_get(qdma, offset, mask)			\
697 	FIELD_GET((mask), airoha_qdma_rr((qdma), (offset)))
698 
699 static inline u16 airoha_qdma_get_txq(struct airoha_qdma *qdma, u16 qid)
700 {
701 	return qid % ARRAY_SIZE(qdma->q_tx);
702 }
703 
704 static inline bool airoha_is_lan_gdm_dev(struct airoha_gdm_dev *dev)
705 {
706 	return !test_bit(AIROHA_DEV_F_WAN, &dev->flags);
707 }
708 
709 static inline bool airoha_is_7581(struct airoha_eth *eth)
710 {
711 	return eth->soc->version == 0x7581;
712 }
713 
714 static inline bool airoha_is_7583(struct airoha_eth *eth)
715 {
716 	return eth->soc->version == 0x7583;
717 }
718 
719 int airoha_get_fe_port(struct airoha_gdm_dev *dev);
720 bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,
721 			     struct airoha_gdm_dev *dev);
722 
723 extern struct mutex flow_offload_mutex;
724 
725 static inline struct airoha_qdma *
726 airoha_qdma_deref(struct airoha_gdm_dev *dev)
727 {
728 	return rcu_dereference_protected(dev->qdma,
729 					 lockdep_rtnl_is_held() ||
730 					 lockdep_is_held(&flow_offload_mutex));
731 }
732 
733 void airoha_ppe_set_xmit_frame_size(struct airoha_gdm_dev *dev);
734 void airoha_ppe_set_cpu_port(struct airoha_gdm_dev *dev, u8 ppe_id, u8 fport);
735 bool airoha_ppe_is_enabled(struct airoha_eth *eth, int index);
736 void airoha_ppe_check_skb(struct airoha_ppe_dev *dev, struct sk_buff *skb,
737 			  u16 hash, bool rx_wlan);
738 int airoha_ppe_setup_tc_block_cb(struct airoha_ppe_dev *dev, void *type_data);
739 int airoha_ppe_init(struct airoha_eth *eth);
740 void airoha_ppe_deinit(struct airoha_eth *eth);
741 void airoha_ppe_init_upd_mem(struct airoha_gdm_dev *dev, const u8 *addr);
742 u32 airoha_ppe_get_total_num_entries(struct airoha_ppe *ppe);
743 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe,
744 						  u32 hash);
745 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,
746 				    struct airoha_foe_stats64 *stats);
747 
748 #ifdef CONFIG_DEBUG_FS
749 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe);
750 #else
751 static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe)
752 {
753 	return 0;
754 }
755 #endif
756 
757 #endif /* AIROHA_ETH_H */
758