1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7 #ifndef __SPARX5_MAIN_H__ 8 #define __SPARX5_MAIN_H__ 9 10 #include <linux/types.h> 11 #include <linux/phy/phy.h> 12 #include <linux/netdevice.h> 13 #include <linux/phy.h> 14 #include <linux/if_vlan.h> 15 #include <linux/bitmap.h> 16 #include <linux/phylink.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 #include <linux/hrtimer.h> 20 #include <linux/debugfs.h> 21 #include <net/flow_offload.h> 22 23 #include <fdma_api.h> 24 25 #include "sparx5_main_regs.h" 26 27 /* Target chip type */ 28 enum spx5_target_chiptype { 29 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ 30 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ 31 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ 32 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ 33 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ 34 SPX5_TARGET_CT_7546TSN = 0x0546, /* SparX-5-64i Industrial */ 35 SPX5_TARGET_CT_7549TSN = 0x0549, /* SparX-5-90i Industrial */ 36 SPX5_TARGET_CT_7552TSN = 0x0552, /* SparX-5-128i Industrial */ 37 SPX5_TARGET_CT_7556TSN = 0x0556, /* SparX-5-160i Industrial */ 38 SPX5_TARGET_CT_7558TSN = 0x0558, /* SparX-5-200i Industrial */ 39 SPX5_TARGET_CT_LAN9694 = 0x9694, /* lan969x-40 */ 40 SPX5_TARGET_CT_LAN9691VAO = 0x9691, /* lan969x-40-VAO */ 41 SPX5_TARGET_CT_LAN9694TSN = 0x9695, /* lan969x-40-TSN */ 42 SPX5_TARGET_CT_LAN9694RED = 0x969A, /* lan969x-40-RED */ 43 SPX5_TARGET_CT_LAN9696 = 0x9696, /* lan969x-60 */ 44 SPX5_TARGET_CT_LAN9692VAO = 0x9692, /* lan969x-65-VAO */ 45 SPX5_TARGET_CT_LAN9696TSN = 0x9697, /* lan969x-60-TSN */ 46 SPX5_TARGET_CT_LAN9696RED = 0x969B, /* lan969x-60-RED */ 47 SPX5_TARGET_CT_LAN9698 = 0x9698, /* lan969x-100 */ 48 SPX5_TARGET_CT_LAN9693VAO = 0x9693, /* lan969x-100-VAO */ 49 SPX5_TARGET_CT_LAN9698TSN = 0x9699, /* lan969x-100-TSN */ 50 SPX5_TARGET_CT_LAN9698RED = 0x969C, /* lan969x-100-RED */ 51 }; 52 53 enum sparx5_port_max_tags { 54 SPX5_PORT_MAX_TAGS_NONE, /* No extra tags allowed */ 55 SPX5_PORT_MAX_TAGS_ONE, /* Single tag allowed */ 56 SPX5_PORT_MAX_TAGS_TWO /* Single and double tag allowed */ 57 }; 58 59 enum sparx5_vlan_port_type { 60 SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */ 61 SPX5_VLAN_PORT_TYPE_C, /* C-port */ 62 SPX5_VLAN_PORT_TYPE_S, /* S-port */ 63 SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ 64 }; 65 66 /* This is used in calendar configuration */ 67 enum sparx5_cal_bw { 68 SPX5_CAL_SPEED_NONE = 0, 69 SPX5_CAL_SPEED_1G = 1, 70 SPX5_CAL_SPEED_2G5 = 2, 71 SPX5_CAL_SPEED_5G = 3, 72 SPX5_CAL_SPEED_10G = 4, 73 SPX5_CAL_SPEED_25G = 5, 74 SPX5_CAL_SPEED_0G5 = 6, 75 SPX5_CAL_SPEED_12G5 = 7 76 }; 77 78 enum sparx5_feature { 79 SPX5_FEATURE_PSFP = BIT(0), 80 SPX5_FEATURE_PTP = BIT(1), 81 }; 82 83 #define SPX5_PORTS 65 84 #define SPX5_PORTS_ALL 70 /* Total number of ports */ 85 86 #define SPX5_PORT_CPU_0 0 /* CPU Port 0 */ 87 #define SPX5_PORT_CPU_1 1 /* CPU Port 1 */ 88 #define SPX5_PORT_VD0 2 /* VD0/Port used for IPMC */ 89 #define SPX5_PORT_VD1 3 /* VD1/Port used for AFI/OAM */ 90 #define SPX5_PORT_VD2 4 /* VD2/Port used for IPinIP*/ 91 92 #define PGID_UC_FLOOD 0 93 #define PGID_MC_FLOOD 1 94 #define PGID_IPV4_MC_DATA 2 95 #define PGID_IPV4_MC_CTRL 3 96 #define PGID_IPV6_MC_DATA 4 97 #define PGID_IPV6_MC_CTRL 5 98 #define PGID_BCAST 6 99 #define PGID_CPU 7 100 #define PGID_MCAST_START 8 101 102 #define PGID_TABLE_SIZE 3290 103 104 #define IFH_LEN 9 /* 36 bytes */ 105 #define NULL_VID 0 106 #define SPX5_MACT_PULL_DELAY (2 * HZ) 107 #define SPX5_STATS_CHECK_DELAY (1 * HZ) 108 #define SPX5_PRIOS 8 /* Number of priority queues */ 109 #define SPX5_BUFFER_CELL_SZ 184 /* Cell size */ 110 #define SPX5_BUFFER_MEMORY 4194280 /* 22795 words * 184 bytes */ 111 112 #define XTR_QUEUE 0 113 #define INJ_QUEUE 0 114 115 #define FDMA_XTR_CHANNEL 6 116 #define FDMA_INJ_CHANNEL 0 117 #define FDMA_DCB_MAX 64 118 #define FDMA_RX_DCB_MAX_DBS 15 119 #define FDMA_TX_DCB_MAX_DBS 1 120 121 #define SPARX5_PHC_COUNT 3 122 #define SPARX5_PHC_PORT 0 123 124 #define IFH_REW_OP_NOOP 0x0 125 #define IFH_REW_OP_ONE_STEP_PTP 0x3 126 #define IFH_REW_OP_TWO_STEP_PTP 0x4 127 128 #define IFH_PDU_TYPE_NONE 0x0 129 #define IFH_PDU_TYPE_PTP 0x5 130 #define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6 131 #define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7 132 133 #define SPX5_DSM_CAL_LEN 64 134 #define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 135 #define SPX5_DSM_CAL_EMPTY 0xFFFF 136 137 #define SPARX5_MAX_PTP_ID 512 138 139 struct sparx5; 140 141 struct sparx5_calendar_data { 142 u32 schedule[SPX5_DSM_CAL_LEN]; 143 u32 avg_dist[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; 144 u32 taxi_ports[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; 145 u32 taxi_speeds[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; 146 u32 dev_slots[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; 147 u32 new_slots[SPX5_DSM_CAL_LEN]; 148 u32 temp_sched[SPX5_DSM_CAL_LEN]; 149 u32 indices[SPX5_DSM_CAL_LEN]; 150 u32 short_list[SPX5_DSM_CAL_LEN]; 151 u32 long_list[SPX5_DSM_CAL_LEN]; 152 }; 153 154 /* Frame DMA receive state: 155 * For each DB, there is a SKB, and the skb data pointer is mapped in 156 * the DB. Once a frame is received the skb is given to the upper layers 157 * and a new skb is added to the dcb. 158 * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused. 159 */ 160 struct sparx5_rx { 161 struct fdma fdma; 162 struct page_pool *page_pool; 163 union { 164 struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; 165 struct page *page[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; 166 }; 167 dma_addr_t dma; 168 struct napi_struct napi; 169 struct net_device *ndev; 170 u64 packets; 171 u8 page_order; 172 }; 173 174 /* Used to store information about TX buffers. */ 175 struct sparx5_tx_buf { 176 struct net_device *dev; 177 struct sk_buff *skb; 178 dma_addr_t dma_addr; 179 bool used; 180 bool ptp; 181 }; 182 183 /* Frame DMA transmit state: 184 * DCBs are chained using the DCBs nextptr field. 185 */ 186 struct sparx5_tx { 187 struct fdma fdma; 188 struct sparx5_tx_buf *dbs; 189 u64 packets; 190 u64 dropped; 191 }; 192 193 struct sparx5_port_config { 194 phy_interface_t portmode; 195 u32 bandwidth; 196 int speed; 197 int duplex; 198 enum phy_media media; 199 bool inband; 200 bool power_down; 201 bool autoneg; 202 bool serdes_reset; 203 u32 pause; 204 u32 pause_adv; 205 phy_interface_t phy_mode; 206 u32 sd_sgpio; 207 }; 208 209 struct sparx5_port { 210 struct net_device *ndev; 211 struct sparx5 *sparx5; 212 struct device_node *of_node; 213 struct phy *serdes; 214 struct sparx5_port_config conf; 215 struct phylink_config phylink_config; 216 struct phylink *phylink; 217 struct phylink_pcs phylink_pcs; 218 struct flow_stats mirror_stats; 219 u16 portno; 220 /* Ingress default VLAN (pvid) */ 221 u16 pvid; 222 /* Egress default VLAN (vid) */ 223 u16 vid; 224 bool signd_internal; 225 bool signd_active_high; 226 bool signd_enable; 227 bool flow_control; 228 enum sparx5_port_max_tags max_vlan_tags; 229 enum sparx5_vlan_port_type vlan_type; 230 u32 custom_etype; 231 bool vlan_aware; 232 struct hrtimer inj_timer; 233 /* ptp */ 234 u8 ptp_cmd; 235 u16 ts_id; 236 struct sk_buff_head tx_skbs; 237 bool is_mrouter; 238 struct list_head tc_templates; /* list of TC templates on this port */ 239 }; 240 241 enum sparx5_core_clockfreq { 242 SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */ 243 SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */ 244 SPX5_CORE_CLOCK_328MHZ, /* 328MHZ core clock frequency */ 245 SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */ 246 SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */ 247 }; 248 249 struct sparx5_phc { 250 struct ptp_clock *clock; 251 struct ptp_clock_info info; 252 struct kernel_hwtstamp_config hwtstamp_config; 253 struct sparx5 *sparx5; 254 u8 index; 255 }; 256 257 struct sparx5_skb_cb { 258 u8 rew_op; 259 u8 pdu_type; 260 u8 pdu_w16_offset; 261 u16 ts_id; 262 unsigned long jiffies; 263 }; 264 265 struct sparx5_mdb_entry { 266 struct list_head list; 267 DECLARE_BITMAP(port_mask, SPX5_PORTS); 268 unsigned char addr[ETH_ALEN]; 269 bool cpu_copy; 270 u16 vid; 271 u16 pgid_idx; 272 }; 273 274 struct sparx5_mall_mirror_entry { 275 u32 idx; 276 struct sparx5_port *port; 277 }; 278 279 struct sparx5_mall_entry { 280 struct list_head list; 281 struct sparx5_port *port; 282 unsigned long cookie; 283 enum flow_action_id type; 284 bool ingress; 285 union { 286 struct sparx5_mall_mirror_entry mirror; 287 }; 288 }; 289 290 #define SPARX5_PTP_TIMEOUT msecs_to_jiffies(10) 291 #define SPARX5_SKB_CB(skb) \ 292 ((struct sparx5_skb_cb *)((skb)->cb)) 293 294 struct sparx5_regs { 295 const unsigned int *tsize; 296 const unsigned int *gaddr; 297 const unsigned int *gcnt; 298 const unsigned int *gsize; 299 const unsigned int *raddr; 300 const unsigned int *rcnt; 301 const unsigned int *fpos; 302 const unsigned int *fsize; 303 }; 304 305 struct sparx5_consts { 306 u32 n_ports; /* Number of front ports */ 307 u32 n_ports_all; /* Number of front ports + internal ports */ 308 u32 n_hsch_l1_elems; /* Number of HSCH layer 1 elements */ 309 u32 n_hsch_queues; /* Number of HSCH queues */ 310 u32 n_lb_groups; /* Number of leacky bucket groupd */ 311 u32 n_pgids; /* Number of PGID's */ 312 u32 n_sio_clks; /* Number of serial IO clocks */ 313 u32 n_own_upsids; /* Number of own UPSID's */ 314 u32 n_auto_cals; /* Number of auto calendars */ 315 u32 n_filters; /* Number of PSFP filters */ 316 u32 n_gates; /* Number of PSFP gates */ 317 u32 n_sdlbs; /* Number of service dual leaky buckets */ 318 u32 n_dsm_cal_taxis; /* Number of DSM calendar taxis */ 319 u32 buf_size; /* Amount of QLIM watermark memory */ 320 u32 qres_max_prio_idx; /* Maximum QRES prio index */ 321 u32 qres_max_colour_idx; /* Maximum QRES colour index */ 322 u32 tod_pin; /* PTP TOD pin */ 323 const struct sparx5_vcap_inst *vcaps_cfg; 324 const struct vcap_info *vcaps; 325 const struct vcap_statistics *vcap_stats; 326 }; 327 328 struct sparx5_ops { 329 bool (*is_port_2g5)(int portno); 330 bool (*is_port_5g)(int portno); 331 bool (*is_port_10g)(int portno); 332 bool (*is_port_25g)(int portno); 333 bool (*is_port_rgmii)(int portno); 334 u32 (*get_port_dev_index)(struct sparx5 *sparx5, int port); 335 u32 (*get_port_dev_bit)(struct sparx5 *sparx5, int port); 336 u32 (*get_hsch_max_group_rate)(int grp); 337 struct sparx5_sdlb_group *(*get_sdlb_group)(int idx); 338 int (*set_port_mux)(struct sparx5 *sparx5, struct sparx5_port *port, 339 struct sparx5_port_config *conf); 340 341 irqreturn_t (*ptp_irq_handler)(int irq, void *args); 342 int (*dsm_calendar_calc)(struct sparx5 *sparx5, u32 taxi, 343 struct sparx5_calendar_data *data); 344 int (*port_config_rgmii)(struct sparx5_port *port, 345 struct sparx5_port_config *conf); 346 int (*fdma_init)(struct sparx5 *sparx5); 347 int (*fdma_deinit)(struct sparx5 *sparx5); 348 int (*fdma_poll)(struct napi_struct *napi, int weight); 349 int (*fdma_xmit)(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, 350 struct net_device *dev); 351 }; 352 353 struct sparx5_main_io_resource { 354 enum sparx5_target id; 355 phys_addr_t offset; 356 int range; 357 }; 358 359 struct sparx5_match_data { 360 const struct sparx5_regs *regs; 361 const struct sparx5_consts *consts; 362 const struct sparx5_ops *ops; 363 const struct sparx5_main_io_resource *iomap; 364 int ioranges; 365 int iomap_size; 366 }; 367 368 struct sparx5 { 369 struct platform_device *pdev; 370 struct device *dev; 371 u32 chip_id; 372 enum spx5_target_chiptype target_ct; 373 u32 features; 374 void __iomem *regs[NUM_TARGETS]; 375 int port_count; 376 struct mutex lock; /* MAC reg lock */ 377 /* port structures are in net device */ 378 struct sparx5_port *ports[SPX5_PORTS]; 379 enum sparx5_core_clockfreq coreclock; 380 /* Statistics */ 381 u32 num_stats; 382 u32 num_ethtool_stats; 383 const char * const *stats_layout; 384 u64 *stats; 385 /* Workqueue for reading stats */ 386 struct mutex queue_stats_lock; 387 struct delayed_work stats_work; 388 struct workqueue_struct *stats_queue; 389 /* Notifiers */ 390 struct notifier_block netdevice_nb; 391 struct notifier_block switchdev_nb; 392 struct notifier_block switchdev_blocking_nb; 393 /* Switch state */ 394 u8 base_mac[ETH_ALEN]; 395 u8 base_mac_assign_type; 396 /* Associated bridge device (when bridged) */ 397 struct net_device *hw_bridge_dev; 398 /* Bridged interfaces */ 399 DECLARE_BITMAP(bridge_mask, SPX5_PORTS); 400 DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS); 401 DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS); 402 DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS); 403 /* SW MAC table */ 404 struct list_head mact_entries; 405 /* mac table list (mact_entries) mutex */ 406 struct mutex mact_lock; 407 /* SW MDB table */ 408 struct list_head mdb_entries; 409 /* mdb list mutex */ 410 struct mutex mdb_lock; 411 struct delayed_work mact_work; 412 struct workqueue_struct *mact_queue; 413 /* Board specifics */ 414 bool sd_sgpio_remapping; 415 /* Register based inj/xtr */ 416 int xtr_irq; 417 /* Frame DMA */ 418 int fdma_irq; 419 spinlock_t tx_lock; /* lock for frame transmission */ 420 struct sparx5_rx rx; 421 struct sparx5_tx tx; 422 /* PTP */ 423 bool ptp; 424 struct sparx5_phc phc[SPARX5_PHC_COUNT]; 425 spinlock_t ptp_clock_lock; /* lock for phc */ 426 spinlock_t ptp_ts_id_lock; /* lock for ts_id */ 427 struct mutex ptp_lock; /* lock for ptp interface state */ 428 u16 ptp_skbs; 429 int ptp_irq; 430 /* VCAP */ 431 struct vcap_control *vcap_ctrl; 432 /* PGID allocation map */ 433 u8 pgid_map[PGID_TABLE_SIZE]; 434 struct list_head mall_entries; 435 /* Common root for debugfs */ 436 struct dentry *debugfs_root; 437 const struct sparx5_match_data *data; 438 }; 439 440 /* sparx5_main.c */ 441 bool is_sparx5(struct sparx5 *sparx5); 442 bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature); 443 444 /* sparx5_switchdev.c */ 445 int sparx5_register_notifier_blocks(struct sparx5 *sparx5); 446 void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5); 447 448 /* sparx5_packet.c */ 449 struct frame_info { 450 int src_port; 451 u32 timestamp; 452 }; 453 454 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); 455 void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info); 456 irqreturn_t sparx5_xtr_handler(int irq, void *_priv); 457 netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev); 458 int sparx5_manual_injection_mode(struct sparx5 *sparx5); 459 void sparx5_port_inj_timer_setup(struct sparx5_port *port); 460 461 /* sparx5_fdma.c */ 462 int sparx5_fdma_init(struct sparx5 *sparx5); 463 int sparx5_fdma_deinit(struct sparx5 *sparx5); 464 int sparx5_fdma_start(struct sparx5 *sparx5); 465 int sparx5_fdma_stop(struct sparx5 *sparx5); 466 int sparx5_fdma_napi_callback(struct napi_struct *napi, int weight); 467 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, 468 struct net_device *dev); 469 irqreturn_t sparx5_fdma_handler(int irq, void *args); 470 void sparx5_fdma_reload(struct sparx5 *sparx5, struct fdma *fdma); 471 void sparx5_fdma_injection_mode(struct sparx5 *sparx5); 472 473 /* sparx5_mactable.c */ 474 int sparx5_mact_learn(struct sparx5 *sparx5, int port, 475 const unsigned char mac[ETH_ALEN], u16 vid); 476 bool sparx5_mact_getnext(struct sparx5 *sparx5, 477 unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2); 478 int sparx5_mact_find(struct sparx5 *sparx5, 479 const unsigned char mac[ETH_ALEN], u16 vid, u32 *pcfg2); 480 int sparx5_mact_forget(struct sparx5 *sparx5, 481 const unsigned char mac[ETH_ALEN], u16 vid); 482 int sparx5_add_mact_entry(struct sparx5 *sparx5, 483 struct net_device *dev, 484 u16 portno, 485 const unsigned char *addr, u16 vid); 486 int sparx5_del_mact_entry(struct sparx5 *sparx5, 487 const unsigned char *addr, 488 u16 vid); 489 int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr); 490 int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr); 491 void sparx5_set_ageing(struct sparx5 *sparx5, int msecs); 492 int sparx5_mact_init(struct sparx5 *sparx5); 493 void sparx5_mact_deinit(struct sparx5 *sparx5); 494 495 /* sparx5_vlan.c */ 496 void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable); 497 void sparx5_pgid_clear(struct sparx5 *spx5, int pgid); 498 void sparx5_pgid_read_mask(struct sparx5 *sparx5, int pgid, u32 portmask[3]); 499 void sparx5_update_fwd(struct sparx5 *sparx5); 500 void sparx5_vlan_init(struct sparx5 *sparx5); 501 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno); 502 int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid, 503 bool untagged); 504 int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid); 505 void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port); 506 507 /* sparx5_calendar.c */ 508 int sparx5_calendar_init(struct sparx5 *sparx5); 509 int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, 510 struct sparx5_calendar_data *data); 511 u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed); 512 enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno); 513 514 515 /* sparx5_ethtool.c */ 516 void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats); 517 int sparx5_stats_init(struct sparx5 *sparx5); 518 void sparx5_stats_deinit(struct sparx5 *sparx5); 519 520 /* sparx5_dcb.c */ 521 #ifdef CONFIG_SPARX5_DCB 522 int sparx5_dcb_init(struct sparx5 *sparx5); 523 #else 524 static inline int sparx5_dcb_init(struct sparx5 *sparx5) 525 { 526 return 0; 527 } 528 #endif 529 530 /* sparx5_netdev.c */ 531 void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, 532 u64 timestamp); 533 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); 534 void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, 535 u32 pdu_type); 536 void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr, 537 u32 pdu_w16_offset); 538 void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno); 539 bool sparx5_netdevice_check(const struct net_device *dev); 540 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); 541 int sparx5_register_netdevs(struct sparx5 *sparx5); 542 void sparx5_destroy_netdevs(struct sparx5 *sparx5); 543 void sparx5_unregister_netdevs(struct sparx5 *sparx5); 544 545 /* sparx5_ptp.c */ 546 int sparx5_ptp_init(struct sparx5 *sparx5); 547 void sparx5_ptp_deinit(struct sparx5 *sparx5); 548 int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, 549 struct kernel_hwtstamp_config *cfg, 550 struct netlink_ext_ack *extack); 551 void sparx5_ptp_hwtstamp_get(struct sparx5_port *port, 552 struct kernel_hwtstamp_config *cfg); 553 void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb, 554 u64 timestamp); 555 int sparx5_ptp_txtstamp_request(struct sparx5_port *port, 556 struct sk_buff *skb); 557 void sparx5_ptp_txtstamp_release(struct sparx5_port *port, 558 struct sk_buff *skb); 559 irqreturn_t sparx5_ptp_irq_handler(int irq, void *args); 560 int sparx5_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts); 561 void sparx5_get_hwtimestamp(struct sparx5 *sparx5, 562 struct timespec64 *ts, 563 u32 nsec); 564 565 /* sparx5_vcap_impl.c */ 566 int sparx5_vcap_init(struct sparx5 *sparx5); 567 void sparx5_vcap_deinit(struct sparx5 *sparx5); 568 569 /* sparx5_pgid.c */ 570 enum sparx5_pgid_type { 571 SPX5_PGID_FREE, 572 SPX5_PGID_RESERVED, 573 SPX5_PGID_MULTICAST, 574 }; 575 576 void sparx5_pgid_init(struct sparx5 *spx5); 577 int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx); 578 int sparx5_pgid_free(struct sparx5 *spx5, u16 idx); 579 int sparx5_get_pgid(struct sparx5 *sparx5, int pgid); 580 581 /* sparx5_pool.c */ 582 struct sparx5_pool_entry { 583 u16 ref_cnt; 584 u32 idx; /* tc index */ 585 }; 586 587 u32 sparx5_pool_idx_to_id(u32 idx); 588 int sparx5_pool_put(struct sparx5_pool_entry *pool, int size, u32 id); 589 int sparx5_pool_get(struct sparx5_pool_entry *pool, int size, u32 *id); 590 int sparx5_pool_get_with_idx(struct sparx5_pool_entry *pool, int size, u32 idx, 591 u32 *id); 592 593 /* sparx5_port.c */ 594 int sparx5_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, 595 struct sparx5_port_config *conf); 596 int sparx5_get_internal_port(struct sparx5 *sparx5, int port); 597 598 /* sparx5_sdlb.c */ 599 #define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF 600 #define SPX5_SDLB_PUP_TOKEN_MAX (SPX5_SDLB_PUP_TOKEN_DISABLE - 1) 601 #define SPX5_SDLB_GROUP_RATE_MAX 25000000000ULL 602 #define SPX5_SDLB_2CYCLES_TYPE2_THRES_OFFSET 13 603 #define SPX5_SDLB_CNT 4096 604 #define SPX5_SDLB_GROUP_CNT 10 605 #define SPX5_CLK_PER_100PS_DEFAULT 16 606 607 struct sparx5_sdlb_group { 608 u64 max_rate; 609 u32 min_burst; 610 u32 frame_size; 611 u32 pup_interval; 612 u32 nsets; 613 }; 614 615 extern struct sparx5_sdlb_group sdlb_groups[SPX5_SDLB_GROUP_CNT]; 616 struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx); 617 int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, 618 u64 rate); 619 620 u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); 621 int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst); 622 int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group); 623 624 int sparx5_sdlb_group_add(struct sparx5 *sparx5, u32 group, u32 idx); 625 int sparx5_sdlb_group_del(struct sparx5 *sparx5, u32 group, u32 idx); 626 627 void sparx5_sdlb_group_init(struct sparx5 *sparx5, u64 max_rate, u32 min_burst, 628 u32 frame_size, u32 idx); 629 630 /* sparx5_police.c */ 631 enum { 632 /* More policer types will be added later */ 633 SPX5_POL_SERVICE 634 }; 635 636 struct sparx5_policer { 637 u32 type; 638 u32 idx; 639 u64 rate; 640 u32 burst; 641 u32 group; 642 u8 event_mask; 643 }; 644 645 int sparx5_policer_conf_set(struct sparx5 *sparx5, struct sparx5_policer *pol); 646 647 /* sparx5_psfp.c */ 648 #define SPX5_PSFP_GCE_CNT 4 649 #define SPX5_PSFP_SG_CNT 1024 650 #define SPX5_PSFP_SG_MIN_CYCLE_TIME_NS (1 * NSEC_PER_USEC) 651 #define SPX5_PSFP_SG_MAX_CYCLE_TIME_NS ((1 * NSEC_PER_SEC) - 1) 652 #define SPX5_PSFP_SG_MAX_IPV (SPX5_PRIOS - 1) 653 #define SPX5_PSFP_SG_OPEN (SPX5_PSFP_SG_CNT - 1) 654 #define SPX5_PSFP_SG_CYCLE_TIME_DEFAULT 1000000 655 #define SPX5_PSFP_SF_MAX_SDU 16383 656 657 struct sparx5_psfp_fm { 658 struct sparx5_policer pol; 659 }; 660 661 struct sparx5_psfp_gce { 662 bool gate_state; /* StreamGateState */ 663 u32 interval; /* TimeInterval */ 664 u32 ipv; /* InternalPriorityValue */ 665 u32 maxoctets; /* IntervalOctetMax */ 666 }; 667 668 struct sparx5_psfp_sg { 669 bool gate_state; /* PSFPAdminGateStates */ 670 bool gate_enabled; /* PSFPGateEnabled */ 671 u32 ipv; /* PSFPAdminIPV */ 672 struct timespec64 basetime; /* PSFPAdminBaseTime */ 673 u32 cycletime; /* PSFPAdminCycleTime */ 674 u32 cycletimeext; /* PSFPAdminCycleTimeExtension */ 675 u32 num_entries; /* PSFPAdminControlListLength */ 676 struct sparx5_psfp_gce gce[SPX5_PSFP_GCE_CNT]; 677 }; 678 679 struct sparx5_psfp_sf { 680 bool sblock_osize_ena; 681 bool sblock_osize; 682 u32 max_sdu; 683 u32 sgid; /* Gate id */ 684 u32 fmid; /* Flow meter id */ 685 }; 686 687 int sparx5_psfp_fm_add(struct sparx5 *sparx5, u32 uidx, 688 struct sparx5_psfp_fm *fm, u32 *id); 689 int sparx5_psfp_fm_del(struct sparx5 *sparx5, u32 id); 690 691 int sparx5_psfp_sg_add(struct sparx5 *sparx5, u32 uidx, 692 struct sparx5_psfp_sg *sg, u32 *id); 693 int sparx5_psfp_sg_del(struct sparx5 *sparx5, u32 id); 694 695 int sparx5_psfp_sf_add(struct sparx5 *sparx5, const struct sparx5_psfp_sf *sf, 696 u32 *id); 697 int sparx5_psfp_sf_del(struct sparx5 *sparx5, u32 id); 698 699 u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx); 700 u32 sparx5_psfp_isdx_get_fm(struct sparx5 *sparx5, u32 isdx); 701 u32 sparx5_psfp_sf_get_sg(struct sparx5 *sparx5, u32 sfid); 702 void sparx5_isdx_conf_set(struct sparx5 *sparx5, u32 isdx, u32 sfid, u32 fmid); 703 704 void sparx5_psfp_init(struct sparx5 *sparx5); 705 706 /* sparx5_qos.c */ 707 void sparx5_new_base_time(struct sparx5 *sparx5, const u32 cycle_time, 708 const ktime_t org_base_time, ktime_t *new_base_time); 709 710 /* sparx5_mirror.c */ 711 int sparx5_mirror_add(struct sparx5_mall_entry *entry); 712 void sparx5_mirror_del(struct sparx5_mall_entry *entry); 713 void sparx5_mirror_stats(struct sparx5_mall_entry *entry, 714 struct flow_stats *fstats); 715 716 /* Clock period in picoseconds */ 717 static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock) 718 { 719 switch (cclock) { 720 case SPX5_CORE_CLOCK_250MHZ: 721 return 4000; 722 case SPX5_CORE_CLOCK_328MHZ: 723 return 3048; 724 case SPX5_CORE_CLOCK_500MHZ: 725 return 2000; 726 case SPX5_CORE_CLOCK_625MHZ: 727 default: 728 return 1600; 729 } 730 } 731 732 static inline bool sparx5_is_baser(phy_interface_t interface) 733 { 734 return interface == PHY_INTERFACE_MODE_5GBASER || 735 interface == PHY_INTERFACE_MODE_10GBASER || 736 interface == PHY_INTERFACE_MODE_25GBASER; 737 } 738 739 extern const struct phylink_mac_ops sparx5_phylink_mac_ops; 740 extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops; 741 extern const struct ethtool_ops sparx5_ethtool_ops; 742 extern const struct dcbnl_rtnl_ops sparx5_dcbnl_ops; 743 744 /* Calculate raw offset */ 745 static inline __pure int spx5_offset(int id, int tinst, int tcnt, 746 int gbase, int ginst, 747 int gcnt, int gwidth, 748 int raddr, int rinst, 749 int rcnt, int rwidth) 750 { 751 WARN_ON((tinst) >= tcnt); 752 WARN_ON((ginst) >= gcnt); 753 WARN_ON((rinst) >= rcnt); 754 return gbase + ((ginst) * gwidth) + 755 raddr + ((rinst) * rwidth); 756 } 757 758 /* Read, Write and modify registers content. 759 * The register definition macros start at the id 760 */ 761 static inline void __iomem *spx5_addr(void __iomem *base[], 762 int id, int tinst, int tcnt, 763 int gbase, int ginst, 764 int gcnt, int gwidth, 765 int raddr, int rinst, 766 int rcnt, int rwidth) 767 { 768 WARN_ON((tinst) >= tcnt); 769 WARN_ON((ginst) >= gcnt); 770 WARN_ON((rinst) >= rcnt); 771 return base[id + (tinst)] + 772 gbase + ((ginst) * gwidth) + 773 raddr + ((rinst) * rwidth); 774 } 775 776 static inline void __iomem *spx5_inst_addr(void __iomem *base, 777 int gbase, int ginst, 778 int gcnt, int gwidth, 779 int raddr, int rinst, 780 int rcnt, int rwidth) 781 { 782 WARN_ON((ginst) >= gcnt); 783 WARN_ON((rinst) >= rcnt); 784 return base + 785 gbase + ((ginst) * gwidth) + 786 raddr + ((rinst) * rwidth); 787 } 788 789 static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt, 790 int gbase, int ginst, int gcnt, int gwidth, 791 int raddr, int rinst, int rcnt, int rwidth) 792 { 793 return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 794 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 795 } 796 797 static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt, 798 int gbase, int ginst, int gcnt, int gwidth, 799 int raddr, int rinst, int rcnt, int rwidth) 800 { 801 return readl(spx5_inst_addr(iomem, gbase, ginst, 802 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 803 } 804 805 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, 806 int id, int tinst, int tcnt, 807 int gbase, int ginst, int gcnt, int gwidth, 808 int raddr, int rinst, int rcnt, int rwidth) 809 { 810 writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt, 811 gbase, ginst, gcnt, gwidth, 812 raddr, rinst, rcnt, rwidth)); 813 } 814 815 static inline void spx5_inst_wr(u32 val, void __iomem *iomem, 816 int id, int tinst, int tcnt, 817 int gbase, int ginst, int gcnt, int gwidth, 818 int raddr, int rinst, int rcnt, int rwidth) 819 { 820 writel(val, spx5_inst_addr(iomem, 821 gbase, ginst, gcnt, gwidth, 822 raddr, rinst, rcnt, rwidth)); 823 } 824 825 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, 826 int id, int tinst, int tcnt, 827 int gbase, int ginst, int gcnt, int gwidth, 828 int raddr, int rinst, int rcnt, int rwidth) 829 { 830 u32 nval; 831 832 nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 833 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 834 nval = (nval & ~mask) | (val & mask); 835 writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 836 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 837 } 838 839 static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem, 840 int id, int tinst, int tcnt, 841 int gbase, int ginst, int gcnt, int gwidth, 842 int raddr, int rinst, int rcnt, int rwidth) 843 { 844 u32 nval; 845 846 nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 847 rinst, rcnt, rwidth)); 848 nval = (nval & ~mask) | (val & mask); 849 writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 850 rinst, rcnt, rwidth)); 851 } 852 853 static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst) 854 { 855 return sparx5->regs[id + tinst]; 856 } 857 858 static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5, 859 int id, int tinst, int tcnt, 860 int gbase, int ginst, int gcnt, int gwidth, 861 int raddr, int rinst, int rcnt, int rwidth) 862 { 863 return spx5_addr(sparx5->regs, id, tinst, tcnt, 864 gbase, ginst, gcnt, gwidth, 865 raddr, rinst, rcnt, rwidth); 866 } 867 868 #endif /* __SPARX5_MAIN_H__ */ 869