1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "core_status.h"
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn10/dcn10_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn10/dcn10_resource.h"
35 #include "dcn10/dcn10_ipp.h"
36 #include "dcn10/dcn10_mpc.h"
37
38 #include "dcn10/dcn10_dwb.h"
39
40 #include "irq/dcn10/irq_service_dcn10.h"
41 #include "dcn10/dcn10_dpp.h"
42 #include "dcn10/dcn10_optc.h"
43 #include "dcn10/dcn10_hwseq.h"
44 #include "dce110/dce110_hwseq.h"
45 #include "dcn10/dcn10_opp.h"
46 #include "dcn10/dcn10_link_encoder.h"
47 #include "dcn10/dcn10_stream_encoder.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
50 #include "dce/dce_hwseq.h"
51 #include "dio/virtual/virtual_stream_encoder.h"
52 #include "dce110/dce110_resource.h"
53 #include "dce112/dce112_resource.h"
54 #include "dcn10/dcn10_hubp.h"
55 #include "dcn10/dcn10_hubbub.h"
56 #include "dce/dce_panel_cntl.h"
57
58 #include "soc15_hw_ip.h"
59 #include "vega10_ip_offset.h"
60
61 #include "dcn/dcn_1_0_offset.h"
62 #include "dcn/dcn_1_0_sh_mask.h"
63
64 #include "nbio/nbio_7_0_offset.h"
65
66 #include "mmhub/mmhub_9_1_offset.h"
67 #include "mmhub/mmhub_9_1_sh_mask.h"
68
69 #include "reg_helper.h"
70 #include "dce/dce_abm.h"
71 #include "dce/dce_dmcu.h"
72 #include "dce/dce_aux.h"
73 #include "dce/dce_i2c.h"
74 #include "dio/dcn10/dcn10_dio.h"
75
76 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
77 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
78 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
79 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
80 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
81 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
82 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
83 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
84 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
85 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
86 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
87 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
88 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
89 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
90 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
91 #endif
92
93
94 enum dcn10_clk_src_array_id {
95 DCN10_CLK_SRC_PLL0,
96 DCN10_CLK_SRC_PLL1,
97 DCN10_CLK_SRC_PLL2,
98 DCN10_CLK_SRC_PLL3,
99 DCN10_CLK_SRC_TOTAL,
100 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
101 };
102
103 /* begin *********************
104 * macros to expend register list macro defined in HW object header file */
105
106 /* DCN */
107 #define BASE_INNER(seg) \
108 DCE_BASE__INST0_SEG ## seg
109
110 #define BASE(seg) \
111 BASE_INNER(seg)
112
113 #define SR(reg_name)\
114 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
115 mm ## reg_name
116
117 #define SRI(reg_name, block, id)\
118 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
119 mm ## block ## id ## _ ## reg_name
120
121
122 #define SRII(reg_name, block, id)\
123 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
124 mm ## block ## id ## _ ## reg_name
125
126 #define VUPDATE_SRII(reg_name, block, id)\
127 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
128 mm ## reg_name ## 0 ## _ ## block ## id
129
130 /* set field/register/bitfield name */
131 #define SFRB(field_name, reg_name, bitfield, post_fix)\
132 .field_name = reg_name ## __ ## bitfield ## post_fix
133
134 /* NBIO */
135 #define NBIO_BASE_INNER(seg) \
136 NBIF_BASE__INST0_SEG ## seg
137
138 #define NBIO_BASE(seg) \
139 NBIO_BASE_INNER(seg)
140
141 #define NBIO_SR(reg_name)\
142 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
143 mm ## reg_name
144
145 /* MMHUB */
146 #define MMHUB_BASE_INNER(seg) \
147 MMHUB_BASE__INST0_SEG ## seg
148
149 #define MMHUB_BASE(seg) \
150 MMHUB_BASE_INNER(seg)
151
152 #define MMHUB_SR(reg_name)\
153 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
154 mm ## reg_name
155
156 /* macros to expend register list macro defined in HW object header file
157 * end *********************/
158
159
160 static const struct dce_dmcu_registers dmcu_regs = {
161 DMCU_DCN10_REG_LIST()
162 };
163
164 static const struct dce_dmcu_shift dmcu_shift = {
165 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
166 };
167
168 static const struct dce_dmcu_mask dmcu_mask = {
169 DMCU_MASK_SH_LIST_DCN10(_MASK)
170 };
171
172 static const struct dce_abm_registers abm_regs = {
173 ABM_DCN10_REG_LIST(0)
174 };
175
176 static const struct dce_abm_shift abm_shift = {
177 ABM_MASK_SH_LIST_DCN10(__SHIFT)
178 };
179
180 static const struct dce_abm_mask abm_mask = {
181 ABM_MASK_SH_LIST_DCN10(_MASK)
182 };
183
184 #define stream_enc_regs(id)\
185 [id] = {\
186 SE_DCN_REG_LIST(id)\
187 }
188
189 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
190 stream_enc_regs(0),
191 stream_enc_regs(1),
192 stream_enc_regs(2),
193 stream_enc_regs(3),
194 };
195
196 static const struct dcn10_stream_encoder_shift se_shift = {
197 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
198 };
199
200 static const struct dcn10_stream_encoder_mask se_mask = {
201 SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
202 };
203
204 #define audio_regs(id)\
205 [id] = {\
206 AUD_COMMON_REG_LIST(id)\
207 }
208
209 static const struct dce_audio_registers audio_regs[] = {
210 audio_regs(0),
211 audio_regs(1),
212 audio_regs(2),
213 audio_regs(3),
214 };
215
216 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
217 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
218 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
219 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
220
221 static const struct dce_audio_shift audio_shift = {
222 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
223 };
224
225 static const struct dce_audio_mask audio_mask = {
226 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
227 };
228
229 #define aux_regs(id)\
230 [id] = {\
231 AUX_REG_LIST(id)\
232 }
233
234 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
235 aux_regs(0),
236 aux_regs(1),
237 aux_regs(2),
238 aux_regs(3)
239 };
240
241 #define hpd_regs(id)\
242 [id] = {\
243 HPD_REG_LIST(id)\
244 }
245
246 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
247 hpd_regs(0),
248 hpd_regs(1),
249 hpd_regs(2),
250 hpd_regs(3)
251 };
252
253 #define link_regs(id)\
254 [id] = {\
255 LE_DCN10_REG_LIST(id), \
256 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
257 }
258
259 static const struct dcn10_link_enc_registers link_enc_regs[] = {
260 link_regs(0),
261 link_regs(1),
262 link_regs(2),
263 link_regs(3)
264 };
265
266 static const struct dcn10_link_enc_shift le_shift = {
267 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
268 };
269
270 static const struct dcn10_link_enc_mask le_mask = {
271 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
272 };
273
274 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
275 { DCN_PANEL_CNTL_REG_LIST() }
276 };
277
278 static const struct dce_panel_cntl_shift panel_cntl_shift = {
279 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
280 };
281
282 static const struct dce_panel_cntl_mask panel_cntl_mask = {
283 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
284 };
285
286 static const struct dce110_aux_registers_shift aux_shift = {
287 DCN10_AUX_MASK_SH_LIST(__SHIFT)
288 };
289
290 static const struct dce110_aux_registers_mask aux_mask = {
291 DCN10_AUX_MASK_SH_LIST(_MASK)
292 };
293
294 #define ipp_regs(id)\
295 [id] = {\
296 IPP_REG_LIST_DCN10(id),\
297 }
298
299 static const struct dcn10_ipp_registers ipp_regs[] = {
300 ipp_regs(0),
301 ipp_regs(1),
302 ipp_regs(2),
303 ipp_regs(3),
304 };
305
306 static const struct dcn10_ipp_shift ipp_shift = {
307 IPP_MASK_SH_LIST_DCN10(__SHIFT)
308 };
309
310 static const struct dcn10_ipp_mask ipp_mask = {
311 IPP_MASK_SH_LIST_DCN10(_MASK),
312 };
313
314 #define opp_regs(id)\
315 [id] = {\
316 OPP_REG_LIST_DCN10(id),\
317 }
318
319 static const struct dcn10_opp_registers opp_regs[] = {
320 opp_regs(0),
321 opp_regs(1),
322 opp_regs(2),
323 opp_regs(3),
324 };
325
326 static const struct dcn10_opp_shift opp_shift = {
327 OPP_MASK_SH_LIST_DCN10(__SHIFT)
328 };
329
330 static const struct dcn10_opp_mask opp_mask = {
331 OPP_MASK_SH_LIST_DCN10(_MASK),
332 };
333
334 #define aux_engine_regs(id)\
335 [id] = {\
336 AUX_COMMON_REG_LIST(id), \
337 .AUX_RESET_MASK = 0 \
338 }
339
340 static const struct dce110_aux_registers aux_engine_regs[] = {
341 aux_engine_regs(0),
342 aux_engine_regs(1),
343 aux_engine_regs(2),
344 aux_engine_regs(3),
345 aux_engine_regs(4),
346 aux_engine_regs(5)
347 };
348
349 #define tf_regs(id)\
350 [id] = {\
351 TF_REG_LIST_DCN10(id),\
352 }
353
354 static const struct dcn_dpp_registers tf_regs[] = {
355 tf_regs(0),
356 tf_regs(1),
357 tf_regs(2),
358 tf_regs(3),
359 };
360
361 static const struct dcn_dpp_shift tf_shift = {
362 TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
363 TF_DEBUG_REG_LIST_SH_DCN10
364
365 };
366
367 static const struct dcn_dpp_mask tf_mask = {
368 TF_REG_LIST_SH_MASK_DCN10(_MASK),
369 TF_DEBUG_REG_LIST_MASK_DCN10
370 };
371
372 static const struct dcn_mpc_registers mpc_regs = {
373 MPC_COMMON_REG_LIST_DCN1_0(0),
374 MPC_COMMON_REG_LIST_DCN1_0(1),
375 MPC_COMMON_REG_LIST_DCN1_0(2),
376 MPC_COMMON_REG_LIST_DCN1_0(3),
377 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
378 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
379 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
380 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
381 };
382
383 static const struct dcn_mpc_shift mpc_shift = {
384 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\
385 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT)
386 };
387
388 static const struct dcn_mpc_mask mpc_mask = {
389 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\
390 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK)
391 };
392
393 #define tg_regs(id)\
394 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
395
396 static const struct dcn_optc_registers tg_regs[] = {
397 tg_regs(0),
398 tg_regs(1),
399 tg_regs(2),
400 tg_regs(3),
401 };
402
403 static const struct dcn_optc_shift tg_shift = {
404 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
405 };
406
407 static const struct dcn_optc_mask tg_mask = {
408 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
409 };
410
411 static const struct bios_registers bios_regs = {
412 NBIO_SR(BIOS_SCRATCH_3),
413 NBIO_SR(BIOS_SCRATCH_6)
414 };
415
416 #define hubp_regs(id)\
417 [id] = {\
418 HUBP_REG_LIST_DCN10(id)\
419 }
420
421 static const struct dcn_mi_registers hubp_regs[] = {
422 hubp_regs(0),
423 hubp_regs(1),
424 hubp_regs(2),
425 hubp_regs(3),
426 };
427
428 static const struct dcn_mi_shift hubp_shift = {
429 HUBP_MASK_SH_LIST_DCN10(__SHIFT)
430 };
431
432 static const struct dcn_mi_mask hubp_mask = {
433 HUBP_MASK_SH_LIST_DCN10(_MASK)
434 };
435
436 static const struct dcn_hubbub_registers hubbub_reg = {
437 HUBBUB_REG_LIST_DCN10(0)
438 };
439
440 static const struct dcn_hubbub_shift hubbub_shift = {
441 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
442 };
443
444 static const struct dcn_hubbub_mask hubbub_mask = {
445 HUBBUB_MASK_SH_LIST_DCN10(_MASK)
446 };
447
448 static const struct dcn_dio_registers dio_regs = {
449 DIO_REG_LIST_DCN10()
450 };
451
452 #define DIO_MASK_SH_LIST(mask_sh)\
453 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
454
455 static const struct dcn_dio_shift dio_shift = {
456 DIO_MASK_SH_LIST(__SHIFT)
457 };
458
459 static const struct dcn_dio_mask dio_mask = {
460 DIO_MASK_SH_LIST(_MASK)
461 };
462
dcn10_dio_create(struct dc_context * ctx)463 static struct dio *dcn10_dio_create(struct dc_context *ctx)
464 {
465 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
466
467 if (!dio10)
468 return NULL;
469
470 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
471
472 return &dio10->base;
473 }
474
map_transmitter_id_to_phy_instance(enum transmitter transmitter)475 static int map_transmitter_id_to_phy_instance(
476 enum transmitter transmitter)
477 {
478 switch (transmitter) {
479 case TRANSMITTER_UNIPHY_A:
480 return 0;
481 break;
482 case TRANSMITTER_UNIPHY_B:
483 return 1;
484 break;
485 case TRANSMITTER_UNIPHY_C:
486 return 2;
487 break;
488 case TRANSMITTER_UNIPHY_D:
489 return 3;
490 break;
491 default:
492 ASSERT(0);
493 return 0;
494 }
495 }
496
497 #define clk_src_regs(index, pllid)\
498 [index] = {\
499 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
500 }
501
502 static const struct dce110_clk_src_regs clk_src_regs[] = {
503 clk_src_regs(0, A),
504 clk_src_regs(1, B),
505 clk_src_regs(2, C),
506 clk_src_regs(3, D)
507 };
508
509 static const struct dce110_clk_src_shift cs_shift = {
510 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
511 };
512
513 static const struct dce110_clk_src_mask cs_mask = {
514 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
515 };
516
517 static const struct resource_caps res_cap = {
518 .num_timing_generator = 4,
519 .num_opp = 4,
520 .num_video_plane = 4,
521 .num_audio = 4,
522 .num_stream_encoder = 4,
523 .num_pll = 4,
524 .num_ddc = 4,
525 };
526
527 static const struct resource_caps rv2_res_cap = {
528 .num_timing_generator = 3,
529 .num_opp = 3,
530 .num_video_plane = 3,
531 .num_audio = 3,
532 .num_stream_encoder = 3,
533 .num_pll = 3,
534 .num_ddc = 4,
535 };
536
537 static const struct dc_plane_cap plane_cap = {
538 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
539 .per_pixel_alpha = true,
540
541 .pixel_format_support = {
542 .argb8888 = true,
543 .nv12 = true,
544 .fp16 = true,
545 .p010 = false
546 },
547
548 .max_upscale_factor = {
549 .argb8888 = 16000,
550 .nv12 = 16000,
551 .fp16 = 1
552 },
553
554 .max_downscale_factor = {
555 .argb8888 = 250,
556 .nv12 = 250,
557 .fp16 = 1
558 }
559 };
560
561 static const struct dc_debug_options debug_defaults_drv = {
562 .sanity_checks = true,
563 .disable_dmcu = false,
564 .force_abm_enable = false,
565 .clock_trace = true,
566
567 /* raven smu dones't allow 0 disp clk,
568 * smu min disp clk limit is 50Mhz
569 * keep min disp clk 100Mhz avoid smu hang
570 */
571 .min_disp_clk_khz = 100000,
572
573 .disable_pplib_clock_request = false,
574 .disable_pplib_wm_range = false,
575 .pplib_wm_report_mode = WM_REPORT_DEFAULT,
576 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
577 .force_single_disp_pipe_split = true,
578 .disable_dcc = DCC_ENABLE,
579 .voltage_align_fclk = true,
580 .disable_stereo_support = true,
581 .vsr_support = true,
582 .performance_trace = false,
583 .az_endpoint_mute_only = true,
584 .recovery_enabled = false, /*enable this by default after testing.*/
585 .max_downscale_src_width = 3840,
586 .underflow_assert_delay_us = 0xFFFFFFFF,
587 .using_dml2 = false,
588 };
589
590 static const struct dc_check_config config_defaults = {
591 .enable_legacy_fast_update = true,
592 };
593
dcn10_dpp_destroy(struct dpp ** dpp)594 static void dcn10_dpp_destroy(struct dpp **dpp)
595 {
596 kfree(TO_DCN10_DPP(*dpp));
597 *dpp = NULL;
598 }
599
dcn10_dpp_create(struct dc_context * ctx,uint32_t inst)600 static struct dpp *dcn10_dpp_create(
601 struct dc_context *ctx,
602 uint32_t inst)
603 {
604 struct dcn10_dpp *dpp =
605 kzalloc_obj(struct dcn10_dpp);
606
607 if (!dpp)
608 return NULL;
609
610 dpp1_construct(dpp, ctx, inst,
611 &tf_regs[inst], &tf_shift, &tf_mask);
612 return &dpp->base;
613 }
614
dcn10_ipp_create(struct dc_context * ctx,uint32_t inst)615 static struct input_pixel_processor *dcn10_ipp_create(
616 struct dc_context *ctx, uint32_t inst)
617 {
618 struct dcn10_ipp *ipp =
619 kzalloc_obj(struct dcn10_ipp);
620
621 if (!ipp) {
622 BREAK_TO_DEBUGGER();
623 return NULL;
624 }
625
626 dcn10_ipp_construct(ipp, ctx, inst,
627 &ipp_regs[inst], &ipp_shift, &ipp_mask);
628 return &ipp->base;
629 }
630
631
dcn10_opp_create(struct dc_context * ctx,uint32_t inst)632 static struct output_pixel_processor *dcn10_opp_create(
633 struct dc_context *ctx, uint32_t inst)
634 {
635 struct dcn10_opp *opp =
636 kzalloc_obj(struct dcn10_opp);
637
638 if (!opp) {
639 BREAK_TO_DEBUGGER();
640 return NULL;
641 }
642
643 dcn10_opp_construct(opp, ctx, inst,
644 &opp_regs[inst], &opp_shift, &opp_mask);
645 return &opp->base;
646 }
647
dcn10_aux_engine_create(struct dc_context * ctx,uint32_t inst)648 static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx,
649 uint32_t inst)
650 {
651 struct aux_engine_dce110 *aux_engine =
652 kzalloc_obj(struct aux_engine_dce110);
653
654 if (!aux_engine)
655 return NULL;
656
657 dce110_aux_engine_construct(aux_engine, ctx, inst,
658 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
659 &aux_engine_regs[inst],
660 &aux_mask,
661 &aux_shift,
662 ctx->dc->caps.extended_aux_timeout_support);
663
664 return &aux_engine->base;
665 }
666 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
667
668 static const struct dce_i2c_registers i2c_hw_regs[] = {
669 i2c_inst_regs(1),
670 i2c_inst_regs(2),
671 i2c_inst_regs(3),
672 i2c_inst_regs(4),
673 i2c_inst_regs(5),
674 i2c_inst_regs(6),
675 };
676
677 static const struct dce_i2c_shift i2c_shifts = {
678 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
679 };
680
681 static const struct dce_i2c_mask i2c_masks = {
682 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
683 };
684
dcn10_i2c_hw_create(struct dc_context * ctx,uint32_t inst)685 static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx,
686 uint32_t inst)
687 {
688 struct dce_i2c_hw *dce_i2c_hw =
689 kzalloc_obj(struct dce_i2c_hw);
690
691 if (!dce_i2c_hw)
692 return NULL;
693
694 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,
695 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
696
697 return dce_i2c_hw;
698 }
dcn10_mpc_create(struct dc_context * ctx)699 static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
700 {
701 struct dcn10_mpc *mpc10 = kzalloc_obj(struct dcn10_mpc);
702
703 if (!mpc10)
704 return NULL;
705
706 dcn10_mpc_construct(mpc10, ctx,
707 &mpc_regs,
708 &mpc_shift,
709 &mpc_mask,
710 4);
711
712 return &mpc10->base;
713 }
714
dcn10_hubbub_create(struct dc_context * ctx)715 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
716 {
717 struct dcn10_hubbub *dcn10_hubbub = kzalloc_obj(struct dcn10_hubbub);
718
719 if (!dcn10_hubbub)
720 return NULL;
721
722 hubbub1_construct(&dcn10_hubbub->base, ctx,
723 &hubbub_reg,
724 &hubbub_shift,
725 &hubbub_mask);
726
727 return &dcn10_hubbub->base;
728 }
729
dcn10_timing_generator_create(struct dc_context * ctx,uint32_t instance)730 static struct timing_generator *dcn10_timing_generator_create(
731 struct dc_context *ctx,
732 uint32_t instance)
733 {
734 struct optc *tgn10 =
735 kzalloc_obj(struct optc);
736
737 if (!tgn10)
738 return NULL;
739
740 tgn10->base.inst = instance;
741 tgn10->base.ctx = ctx;
742
743 tgn10->tg_regs = &tg_regs[instance];
744 tgn10->tg_shift = &tg_shift;
745 tgn10->tg_mask = &tg_mask;
746
747 dcn10_timing_generator_init(tgn10);
748
749 return &tgn10->base;
750 }
751
752 static const struct encoder_feature_support link_enc_feature = {
753 .max_hdmi_deep_color = COLOR_DEPTH_121212,
754 .max_hdmi_pixel_clock = 600000,
755 .hdmi_ycbcr420_supported = true,
756 .dp_ycbcr420_supported = true,
757 .flags.bits.IS_HBR2_CAPABLE = true,
758 .flags.bits.IS_HBR3_CAPABLE = true,
759 .flags.bits.IS_TPS3_CAPABLE = true,
760 .flags.bits.IS_TPS4_CAPABLE = true
761 };
762
dcn10_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)763 static struct link_encoder *dcn10_link_encoder_create(
764 struct dc_context *ctx,
765 const struct encoder_init_data *enc_init_data)
766 {
767 (void)ctx;
768 struct dcn10_link_encoder *enc10 =
769 kzalloc_obj(struct dcn10_link_encoder);
770 int link_regs_id;
771
772 if (!enc10 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
773 return NULL;
774
775 link_regs_id =
776 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
777
778 dcn10_link_encoder_construct(enc10,
779 enc_init_data,
780 &link_enc_feature,
781 &link_enc_regs[link_regs_id],
782 &link_enc_aux_regs[enc_init_data->channel - 1],
783 &link_enc_hpd_regs[enc_init_data->hpd_source],
784 &le_shift,
785 &le_mask);
786
787 return &enc10->base;
788 }
789
dcn10_panel_cntl_create(const struct panel_cntl_init_data * init_data)790 static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data)
791 {
792 struct dce_panel_cntl *panel_cntl =
793 kzalloc_obj(struct dce_panel_cntl);
794
795 if (!panel_cntl)
796 return NULL;
797
798 dce_panel_cntl_construct(panel_cntl,
799 init_data,
800 &panel_cntl_regs[init_data->inst],
801 &panel_cntl_shift,
802 &panel_cntl_mask);
803
804 return &panel_cntl->base;
805 }
806
dcn10_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)807 static struct clock_source *dcn10_clock_source_create(
808 struct dc_context *ctx,
809 struct dc_bios *bios,
810 enum clock_source_id id,
811 const struct dce110_clk_src_regs *regs,
812 bool dp_clk_src)
813 {
814 struct dce110_clk_src *clk_src =
815 kzalloc_obj(struct dce110_clk_src);
816
817 if (!clk_src)
818 return NULL;
819
820 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
821 regs, &cs_shift, &cs_mask)) {
822 clk_src->base.dp_clk_src = dp_clk_src;
823 return &clk_src->base;
824 }
825
826 kfree(clk_src);
827 BREAK_TO_DEBUGGER();
828 return NULL;
829 }
830
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)831 static void read_dce_straps(
832 struct dc_context *ctx,
833 struct resource_straps *straps)
834 {
835 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
836 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
837 }
838
create_audio(struct dc_context * ctx,unsigned int inst)839 static struct audio *create_audio(
840 struct dc_context *ctx, unsigned int inst)
841 {
842 return dce_audio_create(ctx, inst,
843 &audio_regs[inst], &audio_shift, &audio_mask);
844 }
845
dcn10_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)846 static struct stream_encoder *dcn10_stream_encoder_create(
847 enum engine_id eng_id,
848 struct dc_context *ctx)
849 {
850 struct dcn10_stream_encoder *enc1 =
851 kzalloc_obj(struct dcn10_stream_encoder);
852
853 if (!enc1)
854 return NULL;
855
856 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
857 &stream_enc_regs[eng_id],
858 &se_shift, &se_mask);
859 return &enc1->base;
860 }
861
862 static const struct dce_hwseq_registers hwseq_reg = {
863 HWSEQ_DCN1_REG_LIST()
864 };
865
866 static const struct dce_hwseq_shift hwseq_shift = {
867 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
868 };
869
870 static const struct dce_hwseq_mask hwseq_mask = {
871 HWSEQ_DCN1_MASK_SH_LIST(_MASK)
872 };
873
dcn10_hwseq_create(struct dc_context * ctx)874 static struct dce_hwseq *dcn10_hwseq_create(
875 struct dc_context *ctx)
876 {
877 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
878
879 if (hws) {
880 hws->ctx = ctx;
881 hws->regs = &hwseq_reg;
882 hws->shifts = &hwseq_shift;
883 hws->masks = &hwseq_mask;
884 hws->wa.DEGVIDCN10_253 = true;
885 hws->wa.false_optc_underflow = true;
886 hws->wa.DEGVIDCN10_254 = true;
887
888 if ((ctx->asic_id.chip_family == FAMILY_RV) &&
889 ASICREV_IS_RAVEN2(ctx->asic_id.hw_internal_rev))
890 switch (ctx->asic_id.pci_revision_id) {
891 case PRID_POLLOCK_94:
892 case PRID_POLLOCK_95:
893 case PRID_POLLOCK_E9:
894 case PRID_POLLOCK_EA:
895 case PRID_POLLOCK_EB:
896 hws->wa.wait_hubpret_read_start_during_mpo_transition = true;
897 break;
898 default:
899 hws->wa.wait_hubpret_read_start_during_mpo_transition = false;
900 break;
901 }
902 }
903 return hws;
904 }
905
906 static const struct resource_create_funcs res_create_funcs = {
907 .read_dce_straps = read_dce_straps,
908 .create_audio = create_audio,
909 .create_stream_encoder = dcn10_stream_encoder_create,
910 .create_hwseq = dcn10_hwseq_create,
911 };
912
dcn10_clock_source_destroy(struct clock_source ** clk_src)913 static void dcn10_clock_source_destroy(struct clock_source **clk_src)
914 {
915 kfree(TO_DCE110_CLK_SRC(*clk_src));
916 *clk_src = NULL;
917 }
918
dcn10_pp_smu_create(struct dc_context * ctx)919 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx)
920 {
921 struct pp_smu_funcs *pp_smu = kzalloc_obj(*pp_smu);
922
923 if (!pp_smu)
924 return pp_smu;
925
926 dm_pp_get_funcs(ctx, pp_smu);
927 return pp_smu;
928 }
929
dcn10_resource_destruct(struct dcn10_resource_pool * pool)930 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
931 {
932 unsigned int i;
933
934 for (i = 0; i < pool->base.stream_enc_count; i++) {
935 if (pool->base.stream_enc[i] != NULL) {
936 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
937 pool->base.stream_enc[i] = NULL;
938 }
939 }
940
941 if (pool->base.mpc != NULL) {
942 kfree(TO_DCN10_MPC(pool->base.mpc));
943 pool->base.mpc = NULL;
944 }
945
946 kfree(pool->base.hubbub);
947 pool->base.hubbub = NULL;
948
949 if (pool->base.dio != NULL) {
950 kfree(TO_DCN10_DIO(pool->base.dio));
951 pool->base.dio = NULL;
952 }
953
954 for (i = 0; i < pool->base.pipe_count; i++) {
955 if (pool->base.opps[i] != NULL)
956 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
957
958 if (pool->base.dpps[i] != NULL)
959 dcn10_dpp_destroy(&pool->base.dpps[i]);
960
961 if (pool->base.ipps[i] != NULL)
962 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
963
964 if (pool->base.hubps[i] != NULL) {
965 kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
966 pool->base.hubps[i] = NULL;
967 }
968
969 if (pool->base.irqs != NULL) {
970 dal_irq_service_destroy(&pool->base.irqs);
971 }
972
973 if (pool->base.timing_generators[i] != NULL) {
974 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
975 pool->base.timing_generators[i] = NULL;
976 }
977 }
978
979 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
980 if (pool->base.engines[i] != NULL)
981 dce110_engine_destroy(&pool->base.engines[i]);
982 kfree(pool->base.hw_i2cs[i]);
983 pool->base.hw_i2cs[i] = NULL;
984 kfree(pool->base.sw_i2cs[i]);
985 pool->base.sw_i2cs[i] = NULL;
986 }
987
988 for (i = 0; i < pool->base.audio_count; i++) {
989 if (pool->base.audios[i])
990 dce_aud_destroy(&pool->base.audios[i]);
991 }
992
993 for (i = 0; i < pool->base.clk_src_count; i++) {
994 if (pool->base.clock_sources[i] != NULL) {
995 dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
996 pool->base.clock_sources[i] = NULL;
997 }
998 }
999
1000 if (pool->base.dp_clock_source != NULL) {
1001 dcn10_clock_source_destroy(&pool->base.dp_clock_source);
1002 pool->base.dp_clock_source = NULL;
1003 }
1004
1005 if (pool->base.abm != NULL)
1006 dce_abm_destroy(&pool->base.abm);
1007
1008 if (pool->base.dmcu != NULL)
1009 dce_dmcu_destroy(&pool->base.dmcu);
1010
1011 kfree(pool->base.pp_smu);
1012 }
1013
dcn10_hubp_create(struct dc_context * ctx,uint32_t inst)1014 static struct hubp *dcn10_hubp_create(
1015 struct dc_context *ctx,
1016 uint32_t inst)
1017 {
1018 struct dcn10_hubp *hubp1 =
1019 kzalloc_obj(struct dcn10_hubp);
1020
1021 if (!hubp1)
1022 return NULL;
1023
1024 dcn10_hubp_construct(hubp1, ctx, inst,
1025 &hubp_regs[inst], &hubp_shift, &hubp_mask);
1026 return &hubp1->base;
1027 }
1028
get_pixel_clock_parameters(const struct pipe_ctx * pipe_ctx,struct pixel_clk_params * pixel_clk_params)1029 static void get_pixel_clock_parameters(
1030 const struct pipe_ctx *pipe_ctx,
1031 struct pixel_clk_params *pixel_clk_params)
1032 {
1033 const struct dc_stream_state *stream = pipe_ctx->stream;
1034 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1035 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1036 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1037 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1038 /* TODO: un-hardcode*/
1039 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1040 LINK_RATE_REF_FREQ_IN_KHZ;
1041 pixel_clk_params->flags.ENABLE_SS = 0;
1042 pixel_clk_params->color_depth =
1043 stream->timing.display_color_depth;
1044 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1045 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1046
1047 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1048 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1049
1050 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1051 pixel_clk_params->requested_pix_clk_100hz /= 2;
1052 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1053 pixel_clk_params->requested_pix_clk_100hz *= 2;
1054
1055 }
1056
build_clamping_params(struct dc_stream_state * stream)1057 static void build_clamping_params(struct dc_stream_state *stream)
1058 {
1059 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1060 stream->clamping.c_depth = stream->timing.display_color_depth;
1061 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1062 }
1063
build_pipe_hw_param(struct pipe_ctx * pipe_ctx)1064 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1065 {
1066
1067 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1068
1069 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1070 pipe_ctx->clock_source,
1071 &pipe_ctx->stream_res.pix_clk_params,
1072 &pipe_ctx->pll_settings);
1073
1074 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1075
1076 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1077 &pipe_ctx->stream->bit_depth_params);
1078 build_clamping_params(pipe_ctx->stream);
1079 }
1080
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)1081 static enum dc_status build_mapped_resource(
1082 const struct dc *dc,
1083 struct dc_state *context,
1084 struct dc_stream_state *stream)
1085 {
1086 (void)dc;
1087 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
1088
1089 if (!pipe_ctx)
1090 return DC_ERROR_UNEXPECTED;
1091
1092 build_pipe_hw_param(pipe_ctx);
1093 return DC_OK;
1094 }
1095
dcn10_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1096 static enum dc_status dcn10_add_stream_to_ctx(
1097 struct dc *dc,
1098 struct dc_state *new_ctx,
1099 struct dc_stream_state *dc_stream)
1100 {
1101 enum dc_status result = DC_ERROR_UNEXPECTED;
1102
1103 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1104
1105 if (result == DC_OK)
1106 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1107
1108
1109 if (result == DC_OK)
1110 result = build_mapped_resource(dc, new_ctx, dc_stream);
1111
1112 return result;
1113 }
1114
dcn10_acquire_free_pipe_for_layer(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * opp_head_pipe)1115 static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer(
1116 const struct dc_state *cur_ctx,
1117 struct dc_state *new_ctx,
1118 const struct resource_pool *pool,
1119 const struct pipe_ctx *opp_head_pipe)
1120 {
1121 (void)cur_ctx;
1122 struct resource_context *res_ctx = &new_ctx->res_ctx;
1123 struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);
1124 struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);
1125
1126 if (!head_pipe) {
1127 ASSERT(0);
1128 return NULL;
1129 }
1130
1131 if (!idle_pipe)
1132 return NULL;
1133
1134 idle_pipe->stream = head_pipe->stream;
1135 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1136 idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
1137 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1138
1139 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1140 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1141 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1142 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1143
1144 return idle_pipe;
1145 }
1146
dcn10_get_dcc_compression_cap(const struct dc * dc,const struct dc_dcc_surface_param * input,struct dc_surface_dcc_cap * output)1147 static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
1148 const struct dc_dcc_surface_param *input,
1149 struct dc_surface_dcc_cap *output)
1150 {
1151 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1152 dc->res_pool->hubbub,
1153 input,
1154 output);
1155 }
1156
dcn10_destroy_resource_pool(struct resource_pool ** pool)1157 static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1158 {
1159 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1160
1161 dcn10_resource_destruct(dcn10_pool);
1162 kfree(dcn10_pool);
1163 *pool = NULL;
1164 }
1165
dcn10_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1166 static enum dc_status dcn10_validate_bandwidth(
1167 struct dc *dc,
1168 struct dc_state *context,
1169 enum dc_validate_mode validate_mode)
1170 {
1171 bool voltage_supported;
1172
1173 DC_FP_START();
1174 voltage_supported = dcn_validate_bandwidth(dc, context, validate_mode);
1175 DC_FP_END();
1176
1177 return voltage_supported ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1178 }
1179
dcn10_validate_plane(const struct dc_plane_state * plane_state,struct dc_caps * caps)1180 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1181 {
1182 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1183 && caps->max_video_width != 0
1184 && plane_state->src_rect.width > caps->max_video_width)
1185 return DC_FAIL_SURFACE_VALIDATE;
1186
1187 return DC_OK;
1188 }
1189
dcn10_validate_global(struct dc * dc,struct dc_state * context)1190 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)
1191 {
1192 int i, j;
1193 bool video_down_scaled = false;
1194 bool video_large = false;
1195 bool desktop_large = false;
1196 bool dcc_disabled = false;
1197 bool mpo_enabled = false;
1198
1199 for (i = 0; i < context->stream_count; i++) {
1200 if (context->stream_status[i].plane_count == 0)
1201 continue;
1202
1203 if (context->stream_status[i].plane_count > 2)
1204 return DC_FAIL_UNSUPPORTED_1;
1205
1206 if (context->stream_status[i].plane_count > 1)
1207 mpo_enabled = true;
1208
1209 for (j = 0; j < context->stream_status[i].plane_count; j++) {
1210 struct dc_plane_state *plane =
1211 context->stream_status[i].plane_states[j];
1212
1213
1214 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1215
1216 if (plane->src_rect.width > plane->dst_rect.width ||
1217 plane->src_rect.height > plane->dst_rect.height)
1218 video_down_scaled = true;
1219
1220 if (plane->src_rect.width >= 3840)
1221 video_large = true;
1222
1223 } else {
1224 if (plane->src_rect.width >= 3840)
1225 desktop_large = true;
1226 if (!plane->dcc.enable)
1227 dcc_disabled = true;
1228 }
1229 }
1230 }
1231
1232 /* Disable MPO in multi-display configurations. */
1233 if (context->stream_count > 1 && mpo_enabled)
1234 return DC_FAIL_UNSUPPORTED_1;
1235
1236 /*
1237 * Workaround: On DCN10 there is UMC issue that causes underflow when
1238 * playing 4k video on 4k desktop with video downscaled and single channel
1239 * memory
1240 */
1241 if (video_large && desktop_large && video_down_scaled && dcc_disabled &&
1242 dc->dcn_soc->number_of_channels == 1)
1243 return DC_FAIL_SURFACE_VALIDATE;
1244
1245 return DC_OK;
1246 }
1247
dcn10_patch_unknown_plane_state(struct dc_plane_state * plane_state)1248 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1249 {
1250 enum surface_pixel_format surf_pix_format = plane_state->format;
1251 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
1252
1253 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
1254
1255 if (bpp == 64)
1256 swizzle = DC_SW_64KB_D;
1257 else
1258 swizzle = DC_SW_64KB_S;
1259
1260 plane_state->tiling_info.gfx9.swizzle = swizzle;
1261 return DC_OK;
1262 }
1263
dcn10_find_first_free_match_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)1264 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
1265 struct resource_context *res_ctx,
1266 const struct resource_pool *pool,
1267 struct dc_stream_state *stream)
1268 {
1269 int i;
1270 int j = -1;
1271 struct dc_link *link = stream->link;
1272
1273 for (i = 0; i < pool->stream_enc_count; i++) {
1274 if (!res_ctx->is_stream_enc_acquired[i] &&
1275 pool->stream_enc[i]) {
1276 /* Store first available for MST second display
1277 * in daisy chain use case
1278 */
1279
1280 if (pool->stream_enc[i]->id != ENGINE_ID_VIRTUAL)
1281 j = i;
1282
1283 if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id ==
1284 link->link_enc->preferred_engine)
1285 return pool->stream_enc[i];
1286
1287 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && pool->stream_enc[i]->id ==
1288 link->dpia_preferred_eng_id)
1289 return pool->stream_enc[i];
1290 }
1291 }
1292
1293 /*
1294 * For CZ and later, we can allow DIG FE and BE to differ for all display types
1295 */
1296
1297 if (j >= 0)
1298 return pool->stream_enc[j];
1299
1300 return NULL;
1301 }
1302
dcn10_get_vstartup_for_pipe(struct pipe_ctx * pipe_ctx)1303 unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)
1304 {
1305 return pipe_ctx->pipe_dlg_param.vstartup_start;
1306 }
1307
1308 static const struct dc_cap_funcs cap_funcs = {
1309 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1310 };
1311
dcn10_get_default_tiling_info(struct dc_tiling_info * tiling_info)1312 void dcn10_get_default_tiling_info(struct dc_tiling_info *tiling_info)
1313 {
1314 tiling_info->gfxversion = DcGfxVersion9;
1315 tiling_info->gfx9.swizzle = DC_SW_LINEAR;
1316 }
1317
1318 static const struct resource_funcs dcn10_res_pool_funcs = {
1319 .destroy = dcn10_destroy_resource_pool,
1320 .link_enc_create = dcn10_link_encoder_create,
1321 .panel_cntl_create = dcn10_panel_cntl_create,
1322 .validate_bandwidth = dcn10_validate_bandwidth,
1323 .acquire_free_pipe_as_secondary_dpp_pipe = dcn10_acquire_free_pipe_for_layer,
1324 .validate_plane = dcn10_validate_plane,
1325 .validate_global = dcn10_validate_global,
1326 .add_stream_to_ctx = dcn10_add_stream_to_ctx,
1327 .patch_unknown_plane_state = dcn10_patch_unknown_plane_state,
1328 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1329 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1330 .get_default_tiling_info = dcn10_get_default_tiling_info
1331 };
1332
read_pipe_fuses(struct dc_context * ctx)1333 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1334 {
1335 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1336 /* RV1 support max 4 pipes */
1337 value = value & 0xf;
1338 return value;
1339 }
1340
verify_clock_values(struct dm_pp_clock_levels_with_voltage * clks)1341 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1342 {
1343 int i;
1344
1345 if (clks->num_levels == 0)
1346 return false;
1347
1348 for (i = 0; i < clks->num_levels; i++)
1349 /* Ensure that the result is sane */
1350 if (clks->data[i].clocks_in_khz == 0)
1351 return false;
1352
1353 return true;
1354 }
1355
dcn10_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn10_resource_pool * pool)1356 static bool dcn10_resource_construct(
1357 uint8_t num_virtual_links,
1358 struct dc *dc,
1359 struct dcn10_resource_pool *pool)
1360 {
1361 int i;
1362 int j;
1363 struct dc_context *ctx = dc->ctx;
1364 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1365 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1366 int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1367 bool res;
1368
1369 ctx->dc_bios->regs = &bios_regs;
1370
1371 if (ctx->dce_version == DCN_VERSION_1_01)
1372 pool->base.res_cap = &rv2_res_cap;
1373 else
1374 pool->base.res_cap = &res_cap;
1375 pool->base.funcs = &dcn10_res_pool_funcs;
1376
1377 /*
1378 * TODO fill in from actual raven resource when we create
1379 * more than virtual encoder
1380 */
1381
1382 /*************************************************
1383 * Resource + asic cap harcoding *
1384 *************************************************/
1385 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1386
1387 /* max pipe num for ASIC before check pipe fuses */
1388 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1389
1390 if (dc->ctx->dce_version == DCN_VERSION_1_01)
1391 pool->base.pipe_count = 3;
1392 dc->caps.max_video_width = 3840;
1393 dc->caps.max_downscale_ratio = 200;
1394 dc->caps.i2c_speed_in_khz = 100;
1395 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1396 dc->caps.max_cursor_size = 256;
1397 dc->caps.min_horizontal_blanking_period = 80;
1398 dc->caps.max_slave_planes = 1;
1399 dc->caps.max_slave_yuv_planes = 1;
1400 dc->caps.max_slave_rgb_planes = 0;
1401 dc->caps.is_apu = true;
1402 dc->caps.post_blend_color_processing = false;
1403 dc->caps.extended_aux_timeout_support = false;
1404
1405 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
1406 dc->caps.force_dp_tps4_for_cp2520 = true;
1407
1408 /* Color pipeline capabilities */
1409 dc->caps.color.dpp.dcn_arch = 1;
1410 dc->caps.color.dpp.input_lut_shared = 1;
1411 dc->caps.color.dpp.icsc = 1;
1412 dc->caps.color.dpp.dgam_ram = 1;
1413 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1414 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1415 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1416 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1417 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1418 dc->caps.color.dpp.post_csc = 0;
1419 dc->caps.color.dpp.gamma_corr = 0;
1420 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1421
1422 dc->caps.color.dpp.hw_3d_lut = 0;
1423 dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1
1424 dc->caps.color.dpp.ogam_rom_caps.srgb = 1;
1425 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;
1426 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1427 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1428 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1429 dc->caps.color.dpp.ocsc = 1;
1430
1431 /* no post-blend color operations */
1432 dc->caps.color.mpc.gamut_remap = 0;
1433 dc->caps.color.mpc.num_3dluts = 0;
1434 dc->caps.color.mpc.shared_3d_lut = 0;
1435 dc->caps.color.mpc.ogam_ram = 0;
1436 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1437 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1438 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1439 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1440 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1441 dc->caps.color.mpc.ocsc = 0;
1442 dc->debug = debug_defaults_drv;
1443 dc->check_config = config_defaults;
1444
1445 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1446 dc->debug = debug_defaults_drv;
1447
1448 /*************************************************
1449 * Create resources *
1450 *************************************************/
1451
1452 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1453 dcn10_clock_source_create(ctx, ctx->dc_bios,
1454 CLOCK_SOURCE_COMBO_PHY_PLL0,
1455 &clk_src_regs[0], false);
1456 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1457 dcn10_clock_source_create(ctx, ctx->dc_bios,
1458 CLOCK_SOURCE_COMBO_PHY_PLL1,
1459 &clk_src_regs[1], false);
1460 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1461 dcn10_clock_source_create(ctx, ctx->dc_bios,
1462 CLOCK_SOURCE_COMBO_PHY_PLL2,
1463 &clk_src_regs[2], false);
1464
1465 if (dc->ctx->dce_version == DCN_VERSION_1_0) {
1466 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1467 dcn10_clock_source_create(ctx, ctx->dc_bios,
1468 CLOCK_SOURCE_COMBO_PHY_PLL3,
1469 &clk_src_regs[3], false);
1470 }
1471
1472 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1473
1474 if (dc->ctx->dce_version == DCN_VERSION_1_01)
1475 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
1476
1477 pool->base.dp_clock_source =
1478 dcn10_clock_source_create(ctx, ctx->dc_bios,
1479 CLOCK_SOURCE_ID_DP_DTO,
1480 /* todo: not reuse phy_pll registers */
1481 &clk_src_regs[0], true);
1482
1483 for (i = 0; i < pool->base.clk_src_count; i++) {
1484 if (pool->base.clock_sources[i] == NULL) {
1485 dm_error("DC: failed to create clock sources!\n");
1486 BREAK_TO_DEBUGGER();
1487 goto fail;
1488 }
1489 }
1490
1491 pool->base.dmcu = dcn10_dmcu_create(ctx,
1492 &dmcu_regs,
1493 &dmcu_shift,
1494 &dmcu_mask);
1495 if (pool->base.dmcu == NULL) {
1496 dm_error("DC: failed to create dmcu!\n");
1497 BREAK_TO_DEBUGGER();
1498 goto fail;
1499 }
1500
1501 pool->base.abm = dce_abm_create(ctx,
1502 &abm_regs,
1503 &abm_shift,
1504 &abm_mask);
1505 if (pool->base.abm == NULL) {
1506 dm_error("DC: failed to create abm!\n");
1507 BREAK_TO_DEBUGGER();
1508 goto fail;
1509 }
1510
1511 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
1512 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1513 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1514
1515 DC_FP_START();
1516 dcn10_resource_construct_fp(dc);
1517 DC_FP_END();
1518
1519 if (!dc->config.is_vmin_only_asic)
1520 if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev))
1521 switch (dc->ctx->asic_id.pci_revision_id) {
1522 case PRID_DALI_DE:
1523 case PRID_DALI_DF:
1524 case PRID_DALI_E3:
1525 case PRID_DALI_E4:
1526 case PRID_POLLOCK_94:
1527 case PRID_POLLOCK_95:
1528 case PRID_POLLOCK_E9:
1529 case PRID_POLLOCK_EA:
1530 case PRID_POLLOCK_EB:
1531 dc->config.is_vmin_only_asic = true;
1532 break;
1533 default:
1534 break;
1535 }
1536
1537 pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1538
1539 /*
1540 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification *
1541 * implemented. So AZ D3 should work.For issue 197007. *
1542 */
1543 if (pool->base.pp_smu != NULL
1544 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
1545 dc->debug.az_endpoint_mute_only = false;
1546
1547
1548 if (!dc->debug.disable_pplib_clock_request) {
1549 /*
1550 * TODO: This is not the proper way to obtain
1551 * fabric_and_dram_bandwidth, should be min(fclk, memclk).
1552 */
1553 res = dm_pp_get_clock_levels_by_type_with_voltage(
1554 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1555
1556 DC_FP_START();
1557
1558 if (res)
1559 res = verify_clock_values(&fclks);
1560
1561 if (res)
1562 dcn_bw_update_from_pplib_fclks(dc, &fclks);
1563 else
1564 BREAK_TO_DEBUGGER();
1565
1566 DC_FP_END();
1567
1568 res = dm_pp_get_clock_levels_by_type_with_voltage(
1569 ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1570
1571 DC_FP_START();
1572
1573 if (res)
1574 res = verify_clock_values(&dcfclks);
1575
1576 if (res)
1577 dcn_bw_update_from_pplib_dcfclks(dc, &dcfclks);
1578 else
1579 BREAK_TO_DEBUGGER();
1580
1581 DC_FP_END();
1582 }
1583
1584 dcn_bw_sync_calcs_and_dml(dc);
1585 if (!dc->debug.disable_pplib_wm_range) {
1586 dc->res_pool = &pool->base;
1587 DC_FP_START();
1588 dcn_get_soc_clks(
1589 dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);
1590 DC_FP_END();
1591 dcn_bw_notify_pplib_of_wm_ranges(
1592 dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);
1593 }
1594
1595 {
1596 struct irq_service_init_data init_data;
1597 init_data.ctx = dc->ctx;
1598 pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1599 if (!pool->base.irqs)
1600 goto fail;
1601 }
1602
1603 /* index to valid pipe resource */
1604 j = 0;
1605 /* mem input -> ipp -> dpp -> opp -> TG */
1606 for (i = 0; i < pool->base.pipe_count; i++) {
1607 /* if pipe is disabled, skip instance of HW pipe,
1608 * i.e, skip ASIC register instance
1609 */
1610 if ((pipe_fuses & (1 << i)) != 0)
1611 continue;
1612
1613 pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1614 if (pool->base.hubps[j] == NULL) {
1615 BREAK_TO_DEBUGGER();
1616 dm_error(
1617 "DC: failed to create memory input!\n");
1618 goto fail;
1619 }
1620
1621 pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1622 if (pool->base.ipps[j] == NULL) {
1623 BREAK_TO_DEBUGGER();
1624 dm_error(
1625 "DC: failed to create input pixel processor!\n");
1626 goto fail;
1627 }
1628
1629 pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1630 if (pool->base.dpps[j] == NULL) {
1631 BREAK_TO_DEBUGGER();
1632 dm_error(
1633 "DC: failed to create dpp!\n");
1634 goto fail;
1635 }
1636
1637 pool->base.opps[j] = dcn10_opp_create(ctx, i);
1638 if (pool->base.opps[j] == NULL) {
1639 BREAK_TO_DEBUGGER();
1640 dm_error(
1641 "DC: failed to create output pixel processor!\n");
1642 goto fail;
1643 }
1644
1645 pool->base.timing_generators[j] = dcn10_timing_generator_create(
1646 ctx, i);
1647 if (pool->base.timing_generators[j] == NULL) {
1648 BREAK_TO_DEBUGGER();
1649 dm_error("DC: failed to create tg!\n");
1650 goto fail;
1651 }
1652 /* check next valid pipe */
1653 j++;
1654 }
1655
1656 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1657 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1658 if (pool->base.engines[i] == NULL) {
1659 BREAK_TO_DEBUGGER();
1660 dm_error(
1661 "DC:failed to create aux engine!!\n");
1662 goto fail;
1663 }
1664 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i);
1665 if (pool->base.hw_i2cs[i] == NULL) {
1666 BREAK_TO_DEBUGGER();
1667 dm_error(
1668 "DC:failed to create hw i2c!!\n");
1669 goto fail;
1670 }
1671 pool->base.sw_i2cs[i] = NULL;
1672 }
1673
1674 /* valid pipe num */
1675 pool->base.pipe_count = j;
1676 pool->base.timing_generator_count = j;
1677 pool->base.mpcc_count = j;
1678
1679 /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1680 * the value may be changed
1681 */
1682 dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1683 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1684
1685 pool->base.mpc = dcn10_mpc_create(ctx);
1686 if (pool->base.mpc == NULL) {
1687 BREAK_TO_DEBUGGER();
1688 dm_error("DC: failed to create mpc!\n");
1689 goto fail;
1690 }
1691
1692 pool->base.hubbub = dcn10_hubbub_create(ctx);
1693 if (pool->base.hubbub == NULL) {
1694 BREAK_TO_DEBUGGER();
1695 dm_error("DC: failed to create hubbub!\n");
1696 goto fail;
1697 }
1698
1699 /* DIO */
1700 pool->base.dio = dcn10_dio_create(ctx);
1701 if (pool->base.dio == NULL) {
1702 BREAK_TO_DEBUGGER();
1703 dm_error("DC: failed to create dio!\n");
1704 goto fail;
1705 }
1706
1707 if (!resource_construct(num_virtual_links, dc, &pool->base,
1708 &res_create_funcs))
1709 goto fail;
1710
1711 dcn10_hw_sequencer_construct(dc);
1712 dc->caps.max_planes = pool->base.pipe_count;
1713
1714 for (i = 0; i < dc->caps.max_planes; ++i)
1715 dc->caps.planes[i] = plane_cap;
1716
1717 dc->cap_funcs = cap_funcs;
1718
1719 return true;
1720
1721 fail:
1722
1723 dcn10_resource_destruct(pool);
1724
1725 return false;
1726 }
1727
dcn10_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1728 struct resource_pool *dcn10_create_resource_pool(
1729 const struct dc_init_data *init_data,
1730 struct dc *dc)
1731 {
1732 struct dcn10_resource_pool *pool =
1733 kzalloc_obj(struct dcn10_resource_pool);
1734
1735 if (!pool)
1736 return NULL;
1737
1738 if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
1739 return &pool->base;
1740
1741 kfree(pool);
1742 BREAK_TO_DEBUGGER();
1743 return NULL;
1744 }
1745