1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/pci-tph.h>
40 #include <linux/irq.h>
41 #include <linux/spinlock_types.h>
42 #include <linux/semaphore.h>
43 #include <linux/slab.h>
44 #include <linux/vmalloc.h>
45 #include <linux/xarray.h>
46 #include <linux/workqueue.h>
47 #include <linux/mempool.h>
48 #include <linux/interrupt.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 #include <linux/mutex.h>
53
54 #include <linux/mlx5/device.h>
55 #include <linux/mlx5/doorbell.h>
56 #include <linux/mlx5/eq.h>
57 #include <linux/timecounter.h>
58 #include <net/devlink.h>
59
60 #define MLX5_ADEV_NAME "mlx5_core"
61
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
63
64 enum {
65 MLX5_BOARD_ID_LEN = 64,
66 };
67
68 enum {
69 MLX5_CMD_WQ_MAX_NAME = 32,
70 };
71
72 enum {
73 CMD_OWNER_SW = 0x0,
74 CMD_OWNER_HW = 0x1,
75 CMD_STATUS_SUCCESS = 0,
76 };
77
78 enum mlx5_sqp_t {
79 MLX5_SQP_SMI = 0,
80 MLX5_SQP_GSI = 1,
81 MLX5_SQP_IEEE_1588 = 2,
82 MLX5_SQP_SNIFFER = 3,
83 MLX5_SQP_SYNC_UMR = 4,
84 };
85
86 enum {
87 MLX5_MAX_PORTS = 8,
88 };
89
90 enum {
91 MLX5_ATOMIC_MODE_OFFSET = 16,
92 MLX5_ATOMIC_MODE_IB_COMP = 1,
93 MLX5_ATOMIC_MODE_CX = 2,
94 MLX5_ATOMIC_MODE_8B = 3,
95 MLX5_ATOMIC_MODE_16B = 4,
96 MLX5_ATOMIC_MODE_32B = 5,
97 MLX5_ATOMIC_MODE_64B = 6,
98 MLX5_ATOMIC_MODE_128B = 7,
99 MLX5_ATOMIC_MODE_256B = 8,
100 };
101
102 enum {
103 MLX5_REG_SBPR = 0xb001,
104 MLX5_REG_SBCM = 0xb002,
105 MLX5_REG_QPTS = 0x4002,
106 MLX5_REG_QETCR = 0x4005,
107 MLX5_REG_QTCT = 0x400a,
108 MLX5_REG_QPDPM = 0x4013,
109 MLX5_REG_QCAM = 0x4019,
110 MLX5_REG_DCBX_PARAM = 0x4020,
111 MLX5_REG_DCBX_APP = 0x4021,
112 MLX5_REG_FPGA_CAP = 0x4022,
113 MLX5_REG_FPGA_CTRL = 0x4023,
114 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 MLX5_REG_CORE_DUMP = 0x402e,
116 MLX5_REG_PCAP = 0x5001,
117 MLX5_REG_PMTU = 0x5003,
118 MLX5_REG_PTYS = 0x5004,
119 MLX5_REG_PAOS = 0x5006,
120 MLX5_REG_PFCC = 0x5007,
121 MLX5_REG_PPCNT = 0x5008,
122 MLX5_REG_PPTB = 0x500b,
123 MLX5_REG_PBMC = 0x500c,
124 MLX5_REG_PMAOS = 0x5012,
125 MLX5_REG_PUDE = 0x5009,
126 MLX5_REG_PMPE = 0x5010,
127 MLX5_REG_PELC = 0x500e,
128 MLX5_REG_PVLC = 0x500f,
129 MLX5_REG_PCMR = 0x5041,
130 MLX5_REG_PDDR = 0x5031,
131 MLX5_REG_PMLP = 0x5002,
132 MLX5_REG_PPLM = 0x5023,
133 MLX5_REG_PCAM = 0x507f,
134 MLX5_REG_NODE_DESC = 0x6001,
135 MLX5_REG_HOST_ENDIANNESS = 0x7004,
136 MLX5_REG_MTCAP = 0x9009,
137 MLX5_REG_MTMP = 0x900A,
138 MLX5_REG_MCIA = 0x9014,
139 MLX5_REG_MFRL = 0x9028,
140 MLX5_REG_MLCR = 0x902b,
141 MLX5_REG_MRTC = 0x902d,
142 MLX5_REG_MTRC_CAP = 0x9040,
143 MLX5_REG_MTRC_CONF = 0x9041,
144 MLX5_REG_MTRC_STDB = 0x9042,
145 MLX5_REG_MTRC_CTRL = 0x9043,
146 MLX5_REG_MPEIN = 0x9050,
147 MLX5_REG_MPCNT = 0x9051,
148 MLX5_REG_MTPPS = 0x9053,
149 MLX5_REG_MTPPSE = 0x9054,
150 MLX5_REG_MTUTC = 0x9055,
151 MLX5_REG_MPEGC = 0x9056,
152 MLX5_REG_MPIR = 0x9059,
153 MLX5_REG_MCQS = 0x9060,
154 MLX5_REG_MCQI = 0x9061,
155 MLX5_REG_MCC = 0x9062,
156 MLX5_REG_MCDA = 0x9063,
157 MLX5_REG_MCAM = 0x907f,
158 MLX5_REG_MSECQ = 0x9155,
159 MLX5_REG_MSEES = 0x9156,
160 MLX5_REG_MIRC = 0x9162,
161 MLX5_REG_MTPTM = 0x9180,
162 MLX5_REG_MTCTR = 0x9181,
163 MLX5_REG_MRTCQ = 0x9182,
164 MLX5_REG_SBCAM = 0xB01F,
165 MLX5_REG_RESOURCE_DUMP = 0xC000,
166 MLX5_REG_NIC_CAP = 0xC00D,
167 MLX5_REG_DTOR = 0xC00E,
168 MLX5_REG_VHCA_ICM_CTRL = 0xC010,
169 };
170
171 enum mlx5_qpts_trust_state {
172 MLX5_QPTS_TRUST_PCP = 1,
173 MLX5_QPTS_TRUST_DSCP = 2,
174 };
175
176 enum mlx5_dcbx_oper_mode {
177 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
178 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
179 };
180
181 enum {
182 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
183 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
184 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
185 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
186 };
187
188 enum mlx5_page_fault_resume_flags {
189 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
190 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
191 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
192 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
193 };
194
195 enum dbg_rsc_type {
196 MLX5_DBG_RSC_QP,
197 MLX5_DBG_RSC_EQ,
198 MLX5_DBG_RSC_CQ,
199 };
200
201 enum port_state_policy {
202 MLX5_POLICY_DOWN = 0,
203 MLX5_POLICY_UP = 1,
204 MLX5_POLICY_FOLLOW = 2,
205 MLX5_POLICY_INVALID = 0xffffffff
206 };
207
208 enum mlx5_coredev_type {
209 MLX5_COREDEV_PF,
210 MLX5_COREDEV_VF,
211 MLX5_COREDEV_SF,
212 };
213
214 struct mlx5_field_desc {
215 int i;
216 };
217
218 struct mlx5_rsc_debug {
219 struct mlx5_core_dev *dev;
220 void *object;
221 enum dbg_rsc_type type;
222 struct dentry *root;
223 struct mlx5_field_desc fields[];
224 };
225
226 enum mlx5_dev_event {
227 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
228 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
229 MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
230 };
231
232 enum mlx5_port_status {
233 MLX5_PORT_UP = 1,
234 MLX5_PORT_DOWN = 2,
235 };
236
237 enum mlx5_cmdif_state {
238 MLX5_CMDIF_STATE_UNINITIALIZED,
239 MLX5_CMDIF_STATE_UP,
240 MLX5_CMDIF_STATE_DOWN,
241 };
242
243 struct mlx5_cmd_first {
244 __be32 data[4];
245 };
246
247 struct mlx5_cmd_msg {
248 struct list_head list;
249 struct cmd_msg_cache *parent;
250 u32 len;
251 struct mlx5_cmd_first first;
252 struct mlx5_cmd_mailbox *next;
253 };
254
255 struct mlx5_cmd_debug {
256 struct dentry *dbg_root;
257 void *in_msg;
258 void *out_msg;
259 u8 status;
260 u16 inlen;
261 u16 outlen;
262 };
263
264 struct cmd_msg_cache {
265 /* protect block chain allocations
266 */
267 spinlock_t lock;
268 struct list_head head;
269 unsigned int max_inbox_size;
270 unsigned int num_ent;
271 };
272
273 enum {
274 MLX5_NUM_COMMAND_CACHES = 5,
275 };
276
277 struct mlx5_cmd_stats {
278 u64 sum;
279 u64 n;
280 /* number of times command failed */
281 u64 failed;
282 /* number of times command failed on bad status returned by FW */
283 u64 failed_mbox_status;
284 /* last command failed returned errno */
285 u32 last_failed_errno;
286 /* last bad status returned by FW */
287 u8 last_failed_mbox_status;
288 /* last command failed syndrome returned by FW */
289 u32 last_failed_syndrome;
290 struct dentry *root;
291 /* protect command average calculations */
292 spinlock_t lock;
293 };
294
295 struct mlx5_cmd {
296 struct mlx5_nb nb;
297
298 /* members which needs to be queried or reinitialized each reload */
299 struct {
300 u16 cmdif_rev;
301 u8 log_sz;
302 u8 log_stride;
303 int max_reg_cmds;
304 unsigned long bitmask;
305 struct semaphore sem;
306 struct semaphore pages_sem;
307 struct semaphore throttle_sem;
308 struct semaphore unprivileged_sem;
309 struct xarray privileged_uids;
310 } vars;
311 enum mlx5_cmdif_state state;
312 void *cmd_alloc_buf;
313 dma_addr_t alloc_dma;
314 int alloc_size;
315 void *cmd_buf;
316 dma_addr_t dma;
317
318 /* protect command queue allocations
319 */
320 spinlock_t alloc_lock;
321
322 /* protect token allocations
323 */
324 spinlock_t token_lock;
325 u8 token;
326 char wq_name[MLX5_CMD_WQ_MAX_NAME];
327 struct workqueue_struct *wq;
328 int mode;
329 u16 allowed_opcode;
330 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
331 struct dma_pool *pool;
332 struct mlx5_cmd_debug dbg;
333 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
334 int checksum_disabled;
335 struct xarray stats;
336 };
337
338 struct mlx5_cmd_mailbox {
339 void *buf;
340 dma_addr_t dma;
341 struct mlx5_cmd_mailbox *next;
342 };
343
344 struct mlx5_buf_list {
345 void *buf;
346 dma_addr_t map;
347 };
348
349 struct mlx5_frag_buf {
350 struct mlx5_buf_list *frags;
351 int npages;
352 int size;
353 u8 page_shift;
354 };
355
356 struct mlx5_frag_buf_ctrl {
357 struct mlx5_buf_list *frags;
358 u32 sz_m1;
359 u16 frag_sz_m1;
360 u16 strides_offset;
361 u8 log_sz;
362 u8 log_stride;
363 u8 log_frag_strides;
364 };
365
366 struct mlx5_core_psv {
367 u32 psv_idx;
368 struct psv_layout {
369 u32 pd;
370 u16 syndrome;
371 u16 reserved;
372 u16 bg;
373 u16 app_tag;
374 u32 ref_tag;
375 } psv;
376 };
377
378 struct mlx5_core_sig_ctx {
379 struct mlx5_core_psv psv_memory;
380 struct mlx5_core_psv psv_wire;
381 struct ib_sig_err err_item;
382 bool sig_status_checked;
383 bool sig_err_exists;
384 u32 sigerr_count;
385 };
386
387 #define MLX5_24BIT_MASK ((1 << 24) - 1)
388
389 enum mlx5_res_type {
390 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
391 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
392 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
393 MLX5_RES_SRQ = 3,
394 MLX5_RES_XSRQ = 4,
395 MLX5_RES_XRQ = 5,
396 };
397
398 struct mlx5_core_rsc_common {
399 enum mlx5_res_type res;
400 refcount_t refcount;
401 struct completion free;
402 bool invalid;
403 };
404
405 struct mlx5_uars_page {
406 void __iomem *map;
407 bool wc;
408 u32 index;
409 struct list_head list;
410 unsigned int bfregs;
411 unsigned long *reg_bitmap; /* for non fast path bf regs */
412 unsigned long *fp_bitmap;
413 unsigned int reg_avail;
414 unsigned int fp_avail;
415 struct kref ref_count;
416 struct mlx5_core_dev *mdev;
417 };
418
419 struct mlx5_bfreg_head {
420 /* protect blue flame registers allocations */
421 struct mutex lock;
422 struct list_head list;
423 };
424
425 struct mlx5_bfreg_data {
426 struct mlx5_bfreg_head reg_head;
427 struct mlx5_bfreg_head wc_head;
428 };
429
430 struct mlx5_sq_bfreg {
431 void __iomem *map;
432 struct mlx5_uars_page *up;
433 bool wc;
434 u32 index;
435 unsigned int offset;
436 };
437
438 struct mlx5_core_health {
439 struct health_buffer __iomem *health;
440 __be32 __iomem *health_counter;
441 struct timer_list timer;
442 u32 prev;
443 int miss_counter;
444 u8 synd;
445 u32 fatal_error;
446 u32 crdump_size;
447 struct workqueue_struct *wq;
448 unsigned long flags;
449 struct work_struct fatal_report_work;
450 struct work_struct report_work;
451 struct devlink_health_reporter *fw_reporter;
452 struct devlink_health_reporter *fw_fatal_reporter;
453 struct devlink_health_reporter *vnic_reporter;
454 struct delayed_work update_fw_log_ts_work;
455 };
456
457 enum {
458 MLX5_PF_NOTIFY_DISABLE_VF,
459 MLX5_PF_NOTIFY_ENABLE_VF,
460 };
461
462 struct mlx5_vf_context {
463 int enabled;
464 u64 port_guid;
465 u64 node_guid;
466 /* Valid bits are used to validate administrative guid only.
467 * Enabled after ndo_set_vf_guid
468 */
469 u8 port_guid_valid:1;
470 u8 node_guid_valid:1;
471 enum port_state_policy policy;
472 struct blocking_notifier_head notifier;
473 };
474
475 struct mlx5_core_sriov {
476 struct mlx5_vf_context *vfs_ctx;
477 int num_vfs;
478 u16 max_vfs;
479 u16 max_ec_vfs;
480 };
481
482 struct mlx5_events;
483 struct mlx5_mpfs;
484 struct mlx5_eswitch;
485 struct mlx5_lag;
486 struct mlx5_devcom_dev;
487 struct mlx5_fw_reset;
488 struct mlx5_eq_table;
489 struct mlx5_irq_table;
490 struct mlx5_vhca_state_notifier;
491 struct mlx5_sf_dev_table;
492 struct mlx5_sf_hw_table;
493 struct mlx5_sf_table;
494 struct mlx5_crypto_dek_priv;
495
496 struct mlx5_rate_limit {
497 u32 rate;
498 u32 max_burst_sz;
499 u16 typical_pkt_sz;
500 };
501
502 struct mlx5_rl_entry {
503 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
504 u64 refcount;
505 u16 index;
506 u16 uid;
507 u8 dedicated : 1;
508 };
509
510 struct mlx5_rl_table {
511 /* protect rate limit table */
512 struct mutex rl_lock;
513 u16 max_size;
514 u32 max_rate;
515 u32 min_rate;
516 struct mlx5_rl_entry *rl_entry;
517 u64 refcount;
518 };
519
520 struct mlx5_core_roce {
521 struct mlx5_flow_table *ft;
522 struct mlx5_flow_group *fg;
523 struct mlx5_flow_handle *allow_rule;
524 };
525
526 enum {
527 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
528 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
529 /* Set during device detach to block any further devices
530 * creation/deletion on drivers rescan. Unset during device attach.
531 */
532 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
533 MLX5_PRIV_FLAGS_SWITCH_LEGACY = 1 << 3,
534 };
535
536 struct mlx5_adev {
537 struct auxiliary_device adev;
538 struct mlx5_core_dev *mdev;
539 int idx;
540 };
541
542 struct mlx5_debugfs_entries {
543 struct dentry *dbg_root;
544 struct dentry *qp_debugfs;
545 struct dentry *eq_debugfs;
546 struct dentry *cq_debugfs;
547 struct dentry *cmdif_debugfs;
548 struct dentry *pages_debugfs;
549 struct dentry *lag_debugfs;
550 };
551
552 enum mlx5_func_type {
553 MLX5_PF,
554 MLX5_VF,
555 MLX5_SF,
556 MLX5_HOST_PF,
557 MLX5_EC_VF,
558 MLX5_FUNC_TYPE_NUM,
559 };
560
561 struct mlx5_ft_pool;
562 struct mlx5_priv {
563 /* IRQ table valid only for real pci devices PF or VF */
564 struct mlx5_irq_table *irq_table;
565 struct mlx5_eq_table *eq_table;
566
567 /* pages stuff */
568 struct mlx5_nb pg_nb;
569 struct workqueue_struct *pg_wq;
570 struct xarray page_root_xa;
571 atomic_t reg_pages;
572 struct list_head free_list;
573 u32 fw_pages;
574 u32 page_counters[MLX5_FUNC_TYPE_NUM];
575 u32 fw_pages_alloc_failed;
576 u32 give_pages_dropped;
577 u32 reclaim_pages_discard;
578
579 struct mlx5_core_health health;
580 struct list_head traps;
581
582 struct mlx5_debugfs_entries dbg;
583
584 /* start: alloc staff */
585 /* protect buffer allocation according to numa node */
586 struct mutex alloc_mutex;
587 int numa_node;
588
589 struct mutex pgdir_mutex;
590 struct list_head pgdir_list;
591 /* end: alloc staff */
592
593 struct mlx5_adev **adev;
594 int adev_idx;
595 int sw_vhca_id;
596 struct mlx5_events *events;
597 struct mlx5_vhca_events *vhca_events;
598
599 struct mlx5_flow_steering *steering;
600 struct mlx5_mpfs *mpfs;
601 struct mlx5_eswitch *eswitch;
602 struct mlx5_core_sriov sriov;
603 struct mlx5_lag *lag;
604 u32 flags;
605 struct mlx5_devcom_dev *devc;
606 struct mlx5_devcom_comp_dev *hca_devcom_comp;
607 struct mlx5_fw_reset *fw_reset;
608 struct mlx5_core_roce roce;
609 struct mlx5_fc_stats *fc_stats;
610 struct mlx5_rl_table rl_table;
611 struct mlx5_ft_pool *ft_pool;
612
613 struct mlx5_bfreg_data bfregs;
614 struct mlx5_uars_page *uar;
615 #ifdef CONFIG_MLX5_SF
616 struct mlx5_vhca_state_notifier *vhca_state_notifier;
617 struct mlx5_sf_dev_table *sf_dev_table;
618 struct mlx5_core_dev *parent_mdev;
619 #endif
620 #ifdef CONFIG_MLX5_SF_MANAGER
621 struct mlx5_sf_hw_table *sf_hw_table;
622 struct mlx5_sf_table *sf_table;
623 #endif
624 struct blocking_notifier_head lag_nh;
625 };
626
627 enum mlx5_device_state {
628 MLX5_DEVICE_STATE_UP = 1,
629 MLX5_DEVICE_STATE_INTERNAL_ERROR,
630 };
631
632 enum mlx5_interface_state {
633 MLX5_INTERFACE_STATE_UP = BIT(0),
634 MLX5_BREAK_FW_WAIT = BIT(1),
635 };
636
637 enum mlx5_pci_status {
638 MLX5_PCI_STATUS_DISABLED,
639 MLX5_PCI_STATUS_ENABLED,
640 };
641
642 enum mlx5_pagefault_type_flags {
643 MLX5_PFAULT_REQUESTOR = 1 << 0,
644 MLX5_PFAULT_WRITE = 1 << 1,
645 MLX5_PFAULT_RDMA = 1 << 2,
646 };
647
648 struct mlx5_td {
649 /* protects tirs list changes while tirs refresh */
650 struct mutex list_lock;
651 struct list_head tirs_list;
652 u32 tdn;
653 };
654
655 struct mlx5e_resources {
656 struct mlx5e_hw_objs {
657 u32 pdn;
658 struct mlx5_td td;
659 u32 mkey;
660 struct mlx5_sq_bfreg bfreg;
661 #define MLX5_MAX_NUM_TC 8
662 u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC];
663 bool tisn_valid;
664 } hw_objs;
665 struct net_device *uplink_netdev;
666 netdevice_tracker tracker;
667 struct mutex uplink_netdev_lock;
668 struct mlx5_crypto_dek_priv *dek_priv;
669 };
670
671 enum mlx5_sw_icm_type {
672 MLX5_SW_ICM_TYPE_STEERING,
673 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
674 MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
675 MLX5_SW_ICM_TYPE_SW_ENCAP,
676 };
677
678 #define MLX5_MAX_RESERVED_GIDS 8
679
680 struct mlx5_rsvd_gids {
681 unsigned int start;
682 unsigned int count;
683 struct ida ida;
684 };
685
686 struct mlx5_clock;
687 struct mlx5_clock_dev_state;
688 struct mlx5_dm;
689 struct mlx5_fw_tracer;
690 struct mlx5_vxlan;
691 struct mlx5_geneve;
692 struct mlx5_hv_vhca;
693 struct mlx5_st;
694
695 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
696 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
697
698 enum {
699 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
700 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
701 };
702
703 enum {
704 MKEY_CACHE_LAST_STD_ENTRY = 20,
705 MLX5_IMR_KSM_CACHE_ENTRY,
706 MAX_MKEY_CACHE_ENTRIES
707 };
708
709 struct mlx5_profile {
710 u64 mask;
711 u8 log_max_qp;
712 u8 num_cmd_caches;
713 struct {
714 int size;
715 int limit;
716 } mr_cache[MAX_MKEY_CACHE_ENTRIES];
717 };
718
719 struct mlx5_hca_cap {
720 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
721 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
722 };
723
724 enum mlx5_wc_state {
725 MLX5_WC_STATE_UNINITIALIZED,
726 MLX5_WC_STATE_UNSUPPORTED,
727 MLX5_WC_STATE_SUPPORTED,
728 };
729
730 struct mlx5_core_dev {
731 struct device *device;
732 enum mlx5_coredev_type coredev_type;
733 struct pci_dev *pdev;
734 /* sync pci state */
735 struct mutex pci_status_mutex;
736 enum mlx5_pci_status pci_status;
737 u8 rev_id;
738 char board_id[MLX5_BOARD_ID_LEN];
739 struct mlx5_cmd cmd;
740 struct {
741 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
742 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
743 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
744 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
745 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
746 u8 embedded_cpu;
747 } caps;
748 struct mlx5_timeouts *timeouts;
749 u64 sys_image_guid;
750 phys_addr_t iseg_base;
751 struct mlx5_init_seg __iomem *iseg;
752 phys_addr_t bar_addr;
753 enum mlx5_device_state state;
754 /* sync interface state */
755 struct mutex intf_state_mutex;
756 struct lock_class_key lock_key;
757 unsigned long intf_state;
758 struct mlx5_priv priv;
759 struct mlx5_profile profile;
760 u32 issi;
761 struct mlx5e_resources mlx5e_res;
762 struct mlx5_dm *dm;
763 struct mlx5_st *st;
764 struct mlx5_vxlan *vxlan;
765 struct mlx5_geneve *geneve;
766 struct {
767 struct mlx5_rsvd_gids reserved_gids;
768 u32 roce_en;
769 } roce;
770 #ifdef CONFIG_MLX5_FPGA
771 struct mlx5_fpga_device *fpga;
772 #endif
773 struct mlx5_clock *clock;
774 struct mlx5_clock_dev_state *clock_state;
775 struct mlx5_ib_clock_info *clock_info;
776 struct mlx5_fw_tracer *tracer;
777 struct mlx5_rsc_dump *rsc_dump;
778 u32 vsc_addr;
779 struct mlx5_hv_vhca *hv_vhca;
780 struct mlx5_hwmon *hwmon;
781 u64 num_block_tc;
782 u64 num_block_ipsec;
783 #ifdef CONFIG_MLX5_MACSEC
784 struct mlx5_macsec_fs *macsec_fs;
785 /* MACsec notifier chain to sync MACsec core and IB database */
786 struct blocking_notifier_head macsec_nh;
787 #endif
788 u64 num_ipsec_offloads;
789 struct mlx5_sd *sd;
790 enum mlx5_wc_state wc_state;
791 /* sync write combining state */
792 struct mutex wc_state_lock;
793 };
794
795 struct mlx5_db {
796 __be32 *db;
797 union {
798 struct mlx5_db_pgdir *pgdir;
799 struct mlx5_ib_user_db_page *user_page;
800 } u;
801 dma_addr_t dma;
802 int index;
803 };
804
805 enum {
806 MLX5_COMP_EQ_SIZE = 1024,
807 };
808
809 enum {
810 MLX5_PTYS_IB = 1 << 0,
811 MLX5_PTYS_EN = 1 << 2,
812 };
813
814 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
815
816 enum {
817 MLX5_CMD_ENT_STATE_PENDING_COMP,
818 };
819
820 struct mlx5_cmd_work_ent {
821 unsigned long state;
822 struct mlx5_cmd_msg *in;
823 struct mlx5_cmd_msg *out;
824 void *uout;
825 int uout_size;
826 mlx5_cmd_cbk_t callback;
827 struct delayed_work cb_timeout_work;
828 void *context;
829 int idx;
830 struct completion handling;
831 struct completion slotted;
832 struct completion done;
833 struct mlx5_cmd *cmd;
834 struct work_struct work;
835 struct mlx5_cmd_layout *lay;
836 int ret;
837 int page_queue;
838 u8 status;
839 u8 token;
840 u64 ts1;
841 u64 ts2;
842 u16 op;
843 bool polling;
844 /* Track the max comp handlers */
845 refcount_t refcnt;
846 };
847
848 enum phy_port_state {
849 MLX5_AAA_111
850 };
851
852 struct mlx5_hca_vport_context {
853 u32 field_select;
854 bool sm_virt_aware;
855 bool has_smi;
856 bool has_raw;
857 enum port_state_policy policy;
858 enum phy_port_state phys_state;
859 enum ib_port_state vport_state;
860 u8 port_physical_state;
861 u64 sys_image_guid;
862 u64 port_guid;
863 u64 node_guid;
864 u32 cap_mask1;
865 u32 cap_mask1_perm;
866 u16 cap_mask2;
867 u16 cap_mask2_perm;
868 u16 lid;
869 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
870 u8 lmc;
871 u8 subnet_timeout;
872 u16 sm_lid;
873 u8 sm_sl;
874 u16 qkey_violation_counter;
875 u16 pkey_violation_counter;
876 bool grh_required;
877 u8 num_plane;
878 };
879
880 #define STRUCT_FIELD(header, field) \
881 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
882 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
883
884 extern struct dentry *mlx5_debugfs_root;
885
fw_rev_maj(struct mlx5_core_dev * dev)886 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
887 {
888 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
889 }
890
fw_rev_min(struct mlx5_core_dev * dev)891 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
892 {
893 return ioread32be(&dev->iseg->fw_rev) >> 16;
894 }
895
fw_rev_sub(struct mlx5_core_dev * dev)896 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
897 {
898 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
899 }
900
mlx5_base_mkey(const u32 key)901 static inline u32 mlx5_base_mkey(const u32 key)
902 {
903 return key & 0xffffff00u;
904 }
905
wq_get_byte_sz(u8 log_sz,u8 log_stride)906 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
907 {
908 return ((u32)1 << log_sz) << log_stride;
909 }
910
mlx5_init_fbc_offset(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)911 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
912 u8 log_stride, u8 log_sz,
913 u16 strides_offset,
914 struct mlx5_frag_buf_ctrl *fbc)
915 {
916 fbc->frags = frags;
917 fbc->log_stride = log_stride;
918 fbc->log_sz = log_sz;
919 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
920 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
921 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
922 fbc->strides_offset = strides_offset;
923 }
924
mlx5_init_fbc(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)925 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
926 u8 log_stride, u8 log_sz,
927 struct mlx5_frag_buf_ctrl *fbc)
928 {
929 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
930 }
931
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)932 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
933 u32 ix)
934 {
935 unsigned int frag;
936
937 ix += fbc->strides_offset;
938 frag = ix >> fbc->log_frag_strides;
939
940 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
941 }
942
943 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)944 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
945 {
946 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
947
948 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
949 }
950
951 enum {
952 CMD_ALLOWED_OPCODE_ALL,
953 };
954
955 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
956 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
957 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
958
959 struct mlx5_async_ctx {
960 struct mlx5_core_dev *dev;
961 atomic_t num_inflight;
962 struct completion inflight_done;
963 };
964
965 struct mlx5_async_work;
966
967 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
968
969 struct mlx5_async_work {
970 struct mlx5_async_ctx *ctx;
971 mlx5_async_cbk_t user_callback;
972 u16 opcode; /* cmd opcode */
973 u16 op_mod; /* cmd op_mod */
974 u8 throttle_locked:1;
975 u8 unpriv_locked:1;
976 void *out; /* pointer to the cmd output buffer */
977 };
978
979 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
980 struct mlx5_async_ctx *ctx);
981 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
982 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
983 void *out, int out_size, mlx5_async_cbk_t callback,
984 struct mlx5_async_work *work);
985 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
986 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
987 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
988 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
989 int out_size);
990
991 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
992 ({ \
993 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
994 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
995 })
996
997 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
998 ({ \
999 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
1000 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
1001 })
1002
1003 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1004 void *out, int out_size);
1005 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1006 int mlx5_cmd_add_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1007 void mlx5_cmd_remove_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1008
1009 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1010 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1011
1012 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data);
1013
1014 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1015 int mlx5_health_init(struct mlx5_core_dev *dev);
1016 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1017 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1018 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1019 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1020 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1021 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1022 struct mlx5_frag_buf *buf, int node);
1023 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1024 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1025 int inlen);
1026 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1027 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1028 int outlen);
1029 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1030 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1031 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1032 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1033 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1034 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1035 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1036 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1037 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1038 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1039 void mlx5_register_debugfs(void);
1040 void mlx5_unregister_debugfs(void);
1041
1042 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1043 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1044 int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1045 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1046 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1047
1048 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1049 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1050 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1051 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1052 void *data_out, int size_out, u16 reg_id, int arg,
1053 int write, bool verbose);
1054 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1055 int size_in, void *data_out, int size_out,
1056 u16 reg_num, int arg, int write);
1057
1058 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1059 int node);
1060
mlx5_db_alloc(struct mlx5_core_dev * dev,struct mlx5_db * db)1061 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1062 {
1063 return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1064 }
1065
1066 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1067
1068 const char *mlx5_command_str(int command);
1069 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1070 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1071 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1072 int npsvs, u32 *sig_index);
1073 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1074 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1075 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1076
1077 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1078 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1079 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1080 struct mlx5_rate_limit *rl);
1081 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1082 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1083 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1084 bool dedicated_entry, u16 *index);
1085 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1086 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1087 struct mlx5_rate_limit *rl_1);
1088 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1089 bool map_wc, bool fast_path);
1090 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1091
1092 unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1093 int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1094 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1095 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1096 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1097 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1098
mlx5_mkey_to_idx(u32 mkey)1099 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1100 {
1101 return mkey >> 8;
1102 }
1103
mlx5_idx_to_mkey(u32 mkey_idx)1104 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1105 {
1106 return mkey_idx << 8;
1107 }
1108
mlx5_mkey_variant(u32 mkey)1109 static inline u8 mlx5_mkey_variant(u32 mkey)
1110 {
1111 return mkey & 0xff;
1112 }
1113
1114 /* Async-atomic event notifier used by mlx5 core to forward FW
1115 * evetns received from event queue to mlx5 consumers.
1116 * Optimise event queue dipatching.
1117 */
1118 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1119 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1120
1121 /* Async-atomic event notifier used for forwarding
1122 * evetns from the event queue into the to mlx5 events dispatcher,
1123 * eswitch, clock and others.
1124 */
1125 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1126 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1127
1128 /* Blocking event notifier used to forward SW events, used for slow path */
1129 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1130 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1131 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1132 void *data);
1133
1134 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1135
1136 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1137 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1138 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1139 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1140 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1141 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1142 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1143 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1144 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1145 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1146 struct net_device *slave);
1147 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1148 u64 *values,
1149 int num_counters,
1150 size_t *offsets);
1151 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1152
1153 #define mlx5_lag_for_each_peer_mdev(dev, peer, i) \
1154 for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i); \
1155 peer; \
1156 peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1157
1158 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1159 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1160 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1161 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1162 u64 length, u32 log_alignment, u16 uid,
1163 phys_addr_t *addr, u32 *obj_id);
1164 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1165 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1166
1167 #ifdef CONFIG_PCIE_TPH
1168 int mlx5_st_alloc_index(struct mlx5_core_dev *dev, enum tph_mem_type mem_type,
1169 unsigned int cpu_uid, u16 *st_index);
1170 int mlx5_st_dealloc_index(struct mlx5_core_dev *dev, u16 st_index);
1171 #else
mlx5_st_alloc_index(struct mlx5_core_dev * dev,enum tph_mem_type mem_type,unsigned int cpu_uid,u16 * st_index)1172 static inline int mlx5_st_alloc_index(struct mlx5_core_dev *dev,
1173 enum tph_mem_type mem_type,
1174 unsigned int cpu_uid, u16 *st_index)
1175 {
1176 return -EOPNOTSUPP;
1177 }
mlx5_st_dealloc_index(struct mlx5_core_dev * dev,u16 st_index)1178 static inline int mlx5_st_dealloc_index(struct mlx5_core_dev *dev, u16 st_index)
1179 {
1180 return -EOPNOTSUPP;
1181 }
1182 #endif
1183
1184 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1185 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1186
1187 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1188 int vf_id,
1189 struct notifier_block *nb);
1190 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1191 int vf_id,
1192 struct notifier_block *nb);
1193 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1194 struct ib_device *device,
1195 struct rdma_netdev_alloc_params *params);
1196
1197 enum {
1198 MLX5_PCI_DEV_IS_VF = 1 << 0,
1199 };
1200
mlx5_core_is_pf(const struct mlx5_core_dev * dev)1201 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1202 {
1203 return dev->coredev_type == MLX5_COREDEV_PF;
1204 }
1205
mlx5_core_is_vf(const struct mlx5_core_dev * dev)1206 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1207 {
1208 return dev->coredev_type == MLX5_COREDEV_VF;
1209 }
1210
mlx5_core_same_coredev_type(const struct mlx5_core_dev * dev1,const struct mlx5_core_dev * dev2)1211 static inline bool mlx5_core_same_coredev_type(const struct mlx5_core_dev *dev1,
1212 const struct mlx5_core_dev *dev2)
1213 {
1214 return dev1->coredev_type == dev2->coredev_type;
1215 }
1216
mlx5_core_is_ecpf(const struct mlx5_core_dev * dev)1217 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1218 {
1219 return dev->caps.embedded_cpu;
1220 }
1221
1222 static inline bool
mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev * dev)1223 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1224 {
1225 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1226 }
1227
mlx5_ecpf_vport_exists(const struct mlx5_core_dev * dev)1228 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1229 {
1230 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1231 }
1232
mlx5_core_max_vfs(const struct mlx5_core_dev * dev)1233 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1234 {
1235 return dev->priv.sriov.max_vfs;
1236 }
1237
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)1238 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1239 {
1240 /* LACP owner conditions:
1241 * 1) Function is physical.
1242 * 2) LAG is supported by FW.
1243 * 3) LAG is managed by driver (currently the only option).
1244 */
1245 return MLX5_CAP_GEN(dev, vport_group_manager) &&
1246 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1247 MLX5_CAP_GEN(dev, lag_master);
1248 }
1249
mlx5_core_max_ec_vfs(const struct mlx5_core_dev * dev)1250 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1251 {
1252 return dev->priv.sriov.max_ec_vfs;
1253 }
1254
mlx5_get_gid_table_len(u16 param)1255 static inline int mlx5_get_gid_table_len(u16 param)
1256 {
1257 if (param > 4) {
1258 pr_warn("gid table length is zero\n");
1259 return 0;
1260 }
1261
1262 return 8 * (1 << param);
1263 }
1264
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1265 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1266 {
1267 return !!(dev->priv.rl_table.max_size);
1268 }
1269
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1270 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1271 {
1272 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1273 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1274 }
1275
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1276 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1277 {
1278 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1279 }
1280
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1281 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1282 {
1283 return mlx5_core_is_mp_slave(dev) ||
1284 mlx5_core_is_mp_master(dev);
1285 }
1286
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1287 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1288 {
1289 if (!mlx5_core_mp_enabled(dev))
1290 return 1;
1291
1292 return MLX5_CAP_GEN(dev, native_port_num);
1293 }
1294
mlx5_get_dev_index(struct mlx5_core_dev * dev)1295 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1296 {
1297 int idx = MLX5_CAP_GEN(dev, native_port_num);
1298
1299 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1300 return idx - 1;
1301 else
1302 return PCI_FUNC(dev->pdev->devfn);
1303 }
1304
1305 enum {
1306 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1307 };
1308
1309 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1310
mlx5_get_roce_state(struct mlx5_core_dev * dev)1311 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1312 {
1313 if (MLX5_CAP_GEN(dev, roce_rw_supported))
1314 return MLX5_CAP_GEN(dev, roce);
1315
1316 /* If RoCE cap is read-only in FW, get RoCE state from devlink
1317 * in order to support RoCE enable/disable feature
1318 */
1319 return mlx5_is_roce_on(dev);
1320 }
1321
1322 #ifdef CONFIG_MLX5_MACSEC
mlx5e_is_macsec_device(const struct mlx5_core_dev * mdev)1323 static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1324 {
1325 if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1326 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1327 return false;
1328
1329 if (!MLX5_CAP_GEN(mdev, log_max_dek))
1330 return false;
1331
1332 if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1333 return false;
1334
1335 if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1336 !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1337 return false;
1338
1339 if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1340 !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1341 return false;
1342
1343 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1344 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1345 return false;
1346
1347 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1348 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1349 return false;
1350
1351 return true;
1352 }
1353
1354 #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1355
mlx5_is_macsec_roce_supported(struct mlx5_core_dev * mdev)1356 static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1357 {
1358 if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1359 NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1360 !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1361 !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1362 return false;
1363
1364 return true;
1365 }
1366 #endif
1367
1368 enum {
1369 MLX5_OCTWORD = 16,
1370 };
1371
1372 bool mlx5_wc_support_get(struct mlx5_core_dev *mdev);
1373
mlx5_core_net(struct mlx5_core_dev * dev)1374 static inline struct net *mlx5_core_net(struct mlx5_core_dev *dev)
1375 {
1376 return devlink_net(priv_to_devlink(dev));
1377 }
1378 #endif /* MLX5_DRIVER_H */
1379