1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // regmap KUnit tests 4 // 5 // Copyright 2023 Arm Ltd 6 7 #include <kunit/device.h> 8 #include <kunit/resource.h> 9 #include <kunit/test.h> 10 #include "internal.h" 11 12 #define BLOCK_TEST_SIZE 12 13 14 #define HIGH_BIT_REG ((UINT_MAX / 2) - 3) 15 16 KUNIT_DEFINE_ACTION_WRAPPER(regmap_exit_action, regmap_exit, struct regmap *); 17 18 struct regmap_test_priv { 19 struct device *dev; 20 bool *reg_default_called; 21 unsigned int reg_default_max; 22 }; 23 24 struct regmap_test_param { 25 enum regcache_type cache; 26 enum regmap_endian val_endian; 27 28 unsigned int base_reg; 29 unsigned int from_reg; 30 bool fast_io; 31 }; 32 33 static void get_changed_bytes(void *orig, void *new, size_t size) 34 { 35 char *o = orig; 36 char *n = new; 37 int i; 38 39 get_random_bytes(new, size); 40 41 /* 42 * This could be nicer and more efficient but we shouldn't 43 * super care. 44 */ 45 for (i = 0; i < size; i++) 46 while (n[i] == o[i]) 47 get_random_bytes(&n[i], 1); 48 } 49 50 static const struct regmap_config test_regmap_config = { 51 .reg_stride = 1, 52 .val_bits = sizeof(unsigned int) * 8, 53 }; 54 55 static const char *regcache_type_name(enum regcache_type type) 56 { 57 switch (type) { 58 case REGCACHE_NONE: 59 return "none"; 60 case REGCACHE_FLAT: 61 return "flat"; 62 case REGCACHE_FLAT_S: 63 return "flat-sparse"; 64 case REGCACHE_RBTREE: 65 return "rbtree"; 66 case REGCACHE_MAPLE: 67 return "maple"; 68 default: 69 return NULL; 70 } 71 } 72 73 static const char *regmap_endian_name(enum regmap_endian endian) 74 { 75 switch (endian) { 76 case REGMAP_ENDIAN_BIG: 77 return "big"; 78 case REGMAP_ENDIAN_LITTLE: 79 return "little"; 80 case REGMAP_ENDIAN_DEFAULT: 81 return "default"; 82 case REGMAP_ENDIAN_NATIVE: 83 return "native"; 84 default: 85 return NULL; 86 } 87 } 88 89 static void param_to_desc(const struct regmap_test_param *param, char *desc) 90 { 91 snprintf(desc, KUNIT_PARAM_DESC_SIZE, "%s-%s%s @%#x", 92 regcache_type_name(param->cache), 93 regmap_endian_name(param->val_endian), 94 param->fast_io ? " fast I/O" : "", 95 param->from_reg); 96 } 97 98 static const struct regmap_test_param regcache_types_list[] = { 99 { .cache = REGCACHE_NONE }, 100 { .cache = REGCACHE_NONE, .fast_io = true }, 101 { .cache = REGCACHE_FLAT }, 102 { .cache = REGCACHE_FLAT, .fast_io = true }, 103 { .cache = REGCACHE_FLAT_S }, 104 { .cache = REGCACHE_FLAT_S, .fast_io = true }, 105 { .cache = REGCACHE_RBTREE }, 106 { .cache = REGCACHE_RBTREE, .fast_io = true }, 107 { .cache = REGCACHE_MAPLE }, 108 { .cache = REGCACHE_MAPLE, .fast_io = true }, 109 }; 110 111 KUNIT_ARRAY_PARAM(regcache_types, regcache_types_list, param_to_desc); 112 113 static const struct regmap_test_param real_cache_types_only_list[] = { 114 { .cache = REGCACHE_FLAT }, 115 { .cache = REGCACHE_FLAT, .fast_io = true }, 116 { .cache = REGCACHE_FLAT_S }, 117 { .cache = REGCACHE_FLAT_S, .fast_io = true }, 118 { .cache = REGCACHE_RBTREE }, 119 { .cache = REGCACHE_RBTREE, .fast_io = true }, 120 { .cache = REGCACHE_MAPLE }, 121 { .cache = REGCACHE_MAPLE, .fast_io = true }, 122 }; 123 124 KUNIT_ARRAY_PARAM(real_cache_types_only, real_cache_types_only_list, param_to_desc); 125 126 static const struct regmap_test_param flat_cache_types_list[] = { 127 { .cache = REGCACHE_FLAT, .from_reg = 0 }, 128 { .cache = REGCACHE_FLAT, .from_reg = 0, .fast_io = true }, 129 { .cache = REGCACHE_FLAT, .from_reg = 0x2001 }, 130 }; 131 132 KUNIT_ARRAY_PARAM(flat_cache_types, flat_cache_types_list, param_to_desc); 133 134 static const struct regmap_test_param real_cache_types_list[] = { 135 { .cache = REGCACHE_FLAT, .from_reg = 0 }, 136 { .cache = REGCACHE_FLAT, .from_reg = 0, .fast_io = true }, 137 { .cache = REGCACHE_FLAT, .from_reg = 0x2001 }, 138 { .cache = REGCACHE_FLAT, .from_reg = 0x2002 }, 139 { .cache = REGCACHE_FLAT, .from_reg = 0x2003 }, 140 { .cache = REGCACHE_FLAT, .from_reg = 0x2004 }, 141 { .cache = REGCACHE_FLAT_S, .from_reg = 0 }, 142 { .cache = REGCACHE_FLAT_S, .from_reg = 0, .fast_io = true }, 143 { .cache = REGCACHE_FLAT_S, .from_reg = 0x2001 }, 144 { .cache = REGCACHE_FLAT_S, .from_reg = 0x2002 }, 145 { .cache = REGCACHE_FLAT_S, .from_reg = 0x2003 }, 146 { .cache = REGCACHE_FLAT_S, .from_reg = 0x2004 }, 147 { .cache = REGCACHE_RBTREE, .from_reg = 0 }, 148 { .cache = REGCACHE_RBTREE, .from_reg = 0, .fast_io = true }, 149 { .cache = REGCACHE_RBTREE, .from_reg = 0x2001 }, 150 { .cache = REGCACHE_RBTREE, .from_reg = 0x2002 }, 151 { .cache = REGCACHE_RBTREE, .from_reg = 0x2003 }, 152 { .cache = REGCACHE_RBTREE, .from_reg = 0x2004 }, 153 { .cache = REGCACHE_MAPLE, .from_reg = 0 }, 154 { .cache = REGCACHE_MAPLE, .from_reg = 0, .fast_io = true }, 155 { .cache = REGCACHE_MAPLE, .from_reg = 0x2001 }, 156 { .cache = REGCACHE_MAPLE, .from_reg = 0x2002 }, 157 { .cache = REGCACHE_MAPLE, .from_reg = 0x2003 }, 158 { .cache = REGCACHE_MAPLE, .from_reg = 0x2004 }, 159 }; 160 161 KUNIT_ARRAY_PARAM(real_cache_types, real_cache_types_list, param_to_desc); 162 163 static const struct regmap_test_param sparse_cache_types_list[] = { 164 { .cache = REGCACHE_FLAT_S, .from_reg = 0 }, 165 { .cache = REGCACHE_FLAT_S, .from_reg = 0, .fast_io = true }, 166 { .cache = REGCACHE_FLAT_S, .from_reg = 0x2001 }, 167 { .cache = REGCACHE_FLAT_S, .from_reg = 0x2002 }, 168 { .cache = REGCACHE_FLAT_S, .from_reg = 0x2003 }, 169 { .cache = REGCACHE_FLAT_S, .from_reg = 0x2004 }, 170 { .cache = REGCACHE_RBTREE, .from_reg = 0 }, 171 { .cache = REGCACHE_RBTREE, .from_reg = 0, .fast_io = true }, 172 { .cache = REGCACHE_RBTREE, .from_reg = 0x2001 }, 173 { .cache = REGCACHE_RBTREE, .from_reg = 0x2002 }, 174 { .cache = REGCACHE_RBTREE, .from_reg = 0x2003 }, 175 { .cache = REGCACHE_RBTREE, .from_reg = 0x2004 }, 176 { .cache = REGCACHE_MAPLE, .from_reg = 0 }, 177 { .cache = REGCACHE_MAPLE, .from_reg = 0, .fast_io = true }, 178 { .cache = REGCACHE_MAPLE, .from_reg = 0x2001 }, 179 { .cache = REGCACHE_MAPLE, .from_reg = 0x2002 }, 180 { .cache = REGCACHE_MAPLE, .from_reg = 0x2003 }, 181 { .cache = REGCACHE_MAPLE, .from_reg = 0x2004 }, 182 }; 183 184 KUNIT_ARRAY_PARAM(sparse_cache_types, sparse_cache_types_list, param_to_desc); 185 186 static struct regmap *gen_regmap(struct kunit *test, 187 struct regmap_config *config, 188 struct regmap_ram_data **data) 189 { 190 const struct regmap_test_param *param = test->param_value; 191 struct regmap_test_priv *priv = test->priv; 192 unsigned int *buf; 193 struct regmap *ret = ERR_PTR(-ENOMEM); 194 size_t size; 195 int i, error; 196 struct reg_default *defaults; 197 198 config->cache_type = param->cache; 199 config->fast_io = param->fast_io; 200 201 if (config->max_register == 0) { 202 config->max_register = param->from_reg; 203 if (config->num_reg_defaults) 204 config->max_register += (config->num_reg_defaults - 1) * 205 config->reg_stride; 206 else 207 config->max_register += (BLOCK_TEST_SIZE * config->reg_stride); 208 } 209 210 size = array_size(config->max_register - param->base_reg + 1, 211 sizeof(*buf)); 212 buf = kmalloc(size, GFP_KERNEL); 213 if (!buf) 214 return ERR_PTR(-ENOMEM); 215 216 get_random_bytes(buf, size); 217 218 *data = kzalloc_obj(**data); 219 if (!(*data)) 220 goto out_free; 221 (*data)->vals = buf; 222 (*data)->base_reg = param->base_reg; 223 224 if (config->num_reg_defaults) { 225 defaults = kunit_kcalloc(test, 226 config->num_reg_defaults, 227 sizeof(struct reg_default), 228 GFP_KERNEL); 229 if (!defaults) 230 goto out_free; 231 232 config->reg_defaults = defaults; 233 234 for (i = 0; i < config->num_reg_defaults; i++) { 235 defaults[i].reg = param->from_reg - param->base_reg + (i * config->reg_stride); 236 defaults[i].def = buf[param->from_reg - param->base_reg + (i * config->reg_stride)]; 237 } 238 } 239 240 ret = regmap_init_ram(priv->dev, config, *data); 241 if (IS_ERR(ret)) 242 goto out_free; 243 244 /* This calls regmap_exit() on failure, which frees buf and *data */ 245 error = kunit_add_action_or_reset(test, regmap_exit_action, ret); 246 if (error) 247 ret = ERR_PTR(error); 248 249 return ret; 250 251 out_free: 252 kfree(buf); 253 kfree(*data); 254 255 return ret; 256 } 257 258 static bool reg_5_false(struct device *dev, unsigned int reg) 259 { 260 struct kunit *test = dev_get_drvdata(dev); 261 const struct regmap_test_param *param = test->param_value; 262 263 return reg != (param->from_reg + 5); 264 } 265 266 static unsigned int reg_default_expected(unsigned int reg) 267 { 268 return 0x5a5a0000 | (reg & 0xffff); 269 } 270 271 static int reg_default_test_cb(struct device *dev, unsigned int reg, 272 unsigned int *def) 273 { 274 struct kunit *test = dev_get_drvdata(dev); 275 struct regmap_test_priv *priv = test->priv; 276 277 if (priv && priv->reg_default_called && reg <= priv->reg_default_max) 278 priv->reg_default_called[reg] = true; 279 280 *def = reg_default_expected(reg); 281 return 0; 282 } 283 284 static void expect_reg_default_value(struct kunit *test, struct regmap *map, 285 struct regmap_ram_data *data, 286 struct regmap_test_priv *priv, 287 unsigned int reg) 288 { 289 unsigned int val; 290 291 KUNIT_EXPECT_TRUE(test, priv->reg_default_called[reg]); 292 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, reg, &val)); 293 KUNIT_EXPECT_EQ(test, reg_default_expected(reg), val); 294 KUNIT_EXPECT_FALSE(test, data->read[reg]); 295 } 296 297 static void basic_read_write(struct kunit *test) 298 { 299 struct regmap *map; 300 struct regmap_config config; 301 struct regmap_ram_data *data; 302 unsigned int val, rval; 303 304 config = test_regmap_config; 305 306 map = gen_regmap(test, &config, &data); 307 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 308 if (IS_ERR(map)) 309 return; 310 311 get_random_bytes(&val, sizeof(val)); 312 313 /* If we write a value to a register we can read it back */ 314 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 0, val)); 315 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 0, &rval)); 316 KUNIT_EXPECT_EQ(test, val, rval); 317 318 /* If using a cache the cache satisfied the read */ 319 KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[0]); 320 } 321 322 static void bulk_write(struct kunit *test) 323 { 324 struct regmap *map; 325 struct regmap_config config; 326 struct regmap_ram_data *data; 327 unsigned int val[BLOCK_TEST_SIZE], rval[BLOCK_TEST_SIZE]; 328 int i; 329 330 config = test_regmap_config; 331 332 map = gen_regmap(test, &config, &data); 333 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 334 if (IS_ERR(map)) 335 return; 336 337 get_random_bytes(&val, sizeof(val)); 338 339 /* 340 * Data written via the bulk API can be read back with single 341 * reads. 342 */ 343 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, 0, val, 344 BLOCK_TEST_SIZE)); 345 for (i = 0; i < BLOCK_TEST_SIZE; i++) 346 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval[i])); 347 348 KUNIT_EXPECT_MEMEQ(test, val, rval, sizeof(val)); 349 350 /* If using a cache the cache satisfied the read */ 351 for (i = 0; i < BLOCK_TEST_SIZE; i++) 352 KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]); 353 } 354 355 static void bulk_read(struct kunit *test) 356 { 357 struct regmap *map; 358 struct regmap_config config; 359 struct regmap_ram_data *data; 360 unsigned int val[BLOCK_TEST_SIZE], rval[BLOCK_TEST_SIZE]; 361 int i; 362 363 config = test_regmap_config; 364 365 map = gen_regmap(test, &config, &data); 366 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 367 if (IS_ERR(map)) 368 return; 369 370 get_random_bytes(&val, sizeof(val)); 371 372 /* Data written as single writes can be read via the bulk API */ 373 for (i = 0; i < BLOCK_TEST_SIZE; i++) 374 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, val[i])); 375 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, 0, rval, 376 BLOCK_TEST_SIZE)); 377 KUNIT_EXPECT_MEMEQ(test, val, rval, sizeof(val)); 378 379 /* If using a cache the cache satisfied the read */ 380 for (i = 0; i < BLOCK_TEST_SIZE; i++) 381 KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]); 382 } 383 384 static void multi_write(struct kunit *test) 385 { 386 struct regmap *map; 387 struct regmap_config config; 388 struct regmap_ram_data *data; 389 struct reg_sequence sequence[BLOCK_TEST_SIZE]; 390 unsigned int val[BLOCK_TEST_SIZE], rval[BLOCK_TEST_SIZE]; 391 int i; 392 393 config = test_regmap_config; 394 395 map = gen_regmap(test, &config, &data); 396 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 397 if (IS_ERR(map)) 398 return; 399 400 get_random_bytes(&val, sizeof(val)); 401 402 /* 403 * Data written via the multi API can be read back with single 404 * reads. 405 */ 406 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 407 sequence[i].reg = i; 408 sequence[i].def = val[i]; 409 sequence[i].delay_us = 0; 410 } 411 KUNIT_EXPECT_EQ(test, 0, 412 regmap_multi_reg_write(map, sequence, BLOCK_TEST_SIZE)); 413 for (i = 0; i < BLOCK_TEST_SIZE; i++) 414 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval[i])); 415 416 KUNIT_EXPECT_MEMEQ(test, val, rval, sizeof(val)); 417 418 /* If using a cache the cache satisfied the read */ 419 for (i = 0; i < BLOCK_TEST_SIZE; i++) 420 KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]); 421 } 422 423 static void multi_read(struct kunit *test) 424 { 425 struct regmap *map; 426 struct regmap_config config; 427 struct regmap_ram_data *data; 428 unsigned int regs[BLOCK_TEST_SIZE]; 429 unsigned int val[BLOCK_TEST_SIZE], rval[BLOCK_TEST_SIZE]; 430 int i; 431 432 config = test_regmap_config; 433 434 map = gen_regmap(test, &config, &data); 435 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 436 if (IS_ERR(map)) 437 return; 438 439 get_random_bytes(&val, sizeof(val)); 440 441 /* Data written as single writes can be read via the multi API */ 442 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 443 regs[i] = i; 444 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, val[i])); 445 } 446 KUNIT_EXPECT_EQ(test, 0, 447 regmap_multi_reg_read(map, regs, rval, BLOCK_TEST_SIZE)); 448 KUNIT_EXPECT_MEMEQ(test, val, rval, sizeof(val)); 449 450 /* If using a cache the cache satisfied the read */ 451 for (i = 0; i < BLOCK_TEST_SIZE; i++) 452 KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]); 453 } 454 455 static void read_bypassed(struct kunit *test) 456 { 457 const struct regmap_test_param *param = test->param_value; 458 struct regmap *map; 459 struct regmap_config config; 460 struct regmap_ram_data *data; 461 unsigned int val[BLOCK_TEST_SIZE], rval; 462 int i; 463 464 config = test_regmap_config; 465 466 map = gen_regmap(test, &config, &data); 467 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 468 if (IS_ERR(map)) 469 return; 470 471 KUNIT_EXPECT_FALSE(test, map->cache_bypass); 472 473 get_random_bytes(&val, sizeof(val)); 474 475 /* Write some test values */ 476 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, param->from_reg, val, ARRAY_SIZE(val))); 477 478 regcache_cache_only(map, true); 479 480 /* 481 * While in cache-only regmap_read_bypassed() should return the register 482 * value and leave the map in cache-only. 483 */ 484 for (i = 0; i < ARRAY_SIZE(val); i++) { 485 /* Put inverted bits in rval to prove we really read the value */ 486 rval = ~val[i]; 487 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, &rval)); 488 KUNIT_EXPECT_EQ(test, val[i], rval); 489 490 rval = ~val[i]; 491 KUNIT_EXPECT_EQ(test, 0, regmap_read_bypassed(map, param->from_reg + i, &rval)); 492 KUNIT_EXPECT_EQ(test, val[i], rval); 493 KUNIT_EXPECT_TRUE(test, map->cache_only); 494 KUNIT_EXPECT_FALSE(test, map->cache_bypass); 495 } 496 497 /* 498 * Change the underlying register values to prove it is returning 499 * real values not cached values. 500 */ 501 for (i = 0; i < ARRAY_SIZE(val); i++) { 502 val[i] = ~val[i]; 503 data->vals[param->from_reg + i] = val[i]; 504 } 505 506 for (i = 0; i < ARRAY_SIZE(val); i++) { 507 rval = ~val[i]; 508 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, &rval)); 509 KUNIT_EXPECT_NE(test, val[i], rval); 510 511 rval = ~val[i]; 512 KUNIT_EXPECT_EQ(test, 0, regmap_read_bypassed(map, param->from_reg + i, &rval)); 513 KUNIT_EXPECT_EQ(test, val[i], rval); 514 KUNIT_EXPECT_TRUE(test, map->cache_only); 515 KUNIT_EXPECT_FALSE(test, map->cache_bypass); 516 } 517 } 518 519 static void read_bypassed_volatile(struct kunit *test) 520 { 521 const struct regmap_test_param *param = test->param_value; 522 struct regmap *map; 523 struct regmap_config config; 524 struct regmap_ram_data *data; 525 unsigned int val[BLOCK_TEST_SIZE], rval; 526 int i; 527 528 config = test_regmap_config; 529 /* All registers except #5 volatile */ 530 config.volatile_reg = reg_5_false; 531 532 map = gen_regmap(test, &config, &data); 533 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 534 if (IS_ERR(map)) 535 return; 536 537 KUNIT_EXPECT_FALSE(test, map->cache_bypass); 538 539 get_random_bytes(&val, sizeof(val)); 540 541 /* Write some test values */ 542 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, param->from_reg, val, ARRAY_SIZE(val))); 543 544 regcache_cache_only(map, true); 545 546 /* 547 * While in cache-only regmap_read_bypassed() should return the register 548 * value and leave the map in cache-only. 549 */ 550 for (i = 0; i < ARRAY_SIZE(val); i++) { 551 /* Register #5 is non-volatile so should read from cache */ 552 KUNIT_EXPECT_EQ(test, (i == 5) ? 0 : -EBUSY, 553 regmap_read(map, param->from_reg + i, &rval)); 554 555 /* Put inverted bits in rval to prove we really read the value */ 556 rval = ~val[i]; 557 KUNIT_EXPECT_EQ(test, 0, regmap_read_bypassed(map, param->from_reg + i, &rval)); 558 KUNIT_EXPECT_EQ(test, val[i], rval); 559 KUNIT_EXPECT_TRUE(test, map->cache_only); 560 KUNIT_EXPECT_FALSE(test, map->cache_bypass); 561 } 562 563 /* 564 * Change the underlying register values to prove it is returning 565 * real values not cached values. 566 */ 567 for (i = 0; i < ARRAY_SIZE(val); i++) { 568 val[i] = ~val[i]; 569 data->vals[param->from_reg + i] = val[i]; 570 } 571 572 for (i = 0; i < ARRAY_SIZE(val); i++) { 573 if (i == 5) 574 continue; 575 576 rval = ~val[i]; 577 KUNIT_EXPECT_EQ(test, 0, regmap_read_bypassed(map, param->from_reg + i, &rval)); 578 KUNIT_EXPECT_EQ(test, val[i], rval); 579 KUNIT_EXPECT_TRUE(test, map->cache_only); 580 KUNIT_EXPECT_FALSE(test, map->cache_bypass); 581 } 582 } 583 584 static void write_readonly(struct kunit *test) 585 { 586 struct regmap *map; 587 struct regmap_config config; 588 struct regmap_ram_data *data; 589 unsigned int val; 590 int i; 591 592 config = test_regmap_config; 593 config.num_reg_defaults = BLOCK_TEST_SIZE; 594 config.writeable_reg = reg_5_false; 595 596 map = gen_regmap(test, &config, &data); 597 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 598 if (IS_ERR(map)) 599 return; 600 601 get_random_bytes(&val, sizeof(val)); 602 603 for (i = 0; i < BLOCK_TEST_SIZE; i++) 604 data->written[i] = false; 605 606 /* Change the value of all registers, readonly should fail */ 607 for (i = 0; i < BLOCK_TEST_SIZE; i++) 608 KUNIT_EXPECT_EQ(test, i != 5, regmap_write(map, i, val) == 0); 609 610 /* Did that match what we see on the device? */ 611 for (i = 0; i < BLOCK_TEST_SIZE; i++) 612 KUNIT_EXPECT_EQ(test, i != 5, data->written[i]); 613 } 614 615 static void read_writeonly(struct kunit *test) 616 { 617 struct regmap *map; 618 struct regmap_config config; 619 struct regmap_ram_data *data; 620 unsigned int val; 621 int i; 622 623 config = test_regmap_config; 624 config.readable_reg = reg_5_false; 625 626 map = gen_regmap(test, &config, &data); 627 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 628 if (IS_ERR(map)) 629 return; 630 631 for (i = 0; i < BLOCK_TEST_SIZE; i++) 632 data->read[i] = false; 633 634 /* 635 * Try to read all the registers, the writeonly one should 636 * fail if we aren't using the flat cache. 637 */ 638 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 639 if (config.cache_type != REGCACHE_FLAT) { 640 KUNIT_EXPECT_EQ(test, i != 5, 641 regmap_read(map, i, &val) == 0); 642 } else { 643 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &val)); 644 } 645 } 646 647 /* Did we trigger a hardware access? */ 648 KUNIT_EXPECT_FALSE(test, data->read[5]); 649 } 650 651 static void reg_defaults(struct kunit *test) 652 { 653 struct regmap *map; 654 struct regmap_config config; 655 struct regmap_ram_data *data; 656 unsigned int rval[BLOCK_TEST_SIZE]; 657 int i; 658 659 config = test_regmap_config; 660 config.num_reg_defaults = BLOCK_TEST_SIZE; 661 662 map = gen_regmap(test, &config, &data); 663 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 664 if (IS_ERR(map)) 665 return; 666 667 /* Read back the expected default data */ 668 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, 0, rval, 669 BLOCK_TEST_SIZE)); 670 KUNIT_EXPECT_MEMEQ(test, data->vals, rval, sizeof(rval)); 671 672 /* The data should have been read from cache if there was one */ 673 for (i = 0; i < BLOCK_TEST_SIZE; i++) 674 KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]); 675 } 676 677 static void reg_default_callback_populates_flat_cache(struct kunit *test) 678 { 679 const struct regmap_test_param *param = test->param_value; 680 struct regmap_test_priv *priv = test->priv; 681 struct regmap *map; 682 struct regmap_config config; 683 struct regmap_ram_data *data; 684 unsigned int reg, val; 685 unsigned int defaults_end; 686 687 config = test_regmap_config; 688 config.num_reg_defaults = 3; 689 config.max_register = param->from_reg + BLOCK_TEST_SIZE - 1; 690 config.reg_default_cb = reg_default_test_cb; 691 692 priv->reg_default_max = config.max_register; 693 priv->reg_default_called = kunit_kcalloc(test, config.max_register + 1, 694 sizeof(*priv->reg_default_called), 695 GFP_KERNEL); 696 KUNIT_ASSERT_NOT_NULL(test, priv->reg_default_called); 697 698 map = gen_regmap(test, &config, &data); 699 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 700 if (IS_ERR(map)) 701 return; 702 703 for (reg = 0; reg <= config.max_register; reg++) 704 data->read[reg] = false; 705 706 defaults_end = param->from_reg + config.num_reg_defaults - 1; 707 708 for (reg = param->from_reg; reg <= defaults_end; reg++) { 709 KUNIT_EXPECT_FALSE(test, priv->reg_default_called[reg]); 710 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, reg, &val)); 711 KUNIT_EXPECT_EQ(test, data->vals[reg], val); 712 KUNIT_EXPECT_FALSE(test, data->read[reg]); 713 } 714 715 if (param->from_reg > 0) 716 expect_reg_default_value(test, map, data, priv, 0); 717 718 if (defaults_end + 1 <= config.max_register) 719 expect_reg_default_value(test, map, data, priv, defaults_end + 1); 720 721 if (config.max_register > defaults_end + 1) 722 expect_reg_default_value(test, map, data, priv, config.max_register); 723 } 724 725 static void reg_defaults_read_dev(struct kunit *test) 726 { 727 struct regmap *map; 728 struct regmap_config config; 729 struct regmap_ram_data *data; 730 unsigned int rval[BLOCK_TEST_SIZE]; 731 int i; 732 733 config = test_regmap_config; 734 config.num_reg_defaults_raw = BLOCK_TEST_SIZE; 735 736 map = gen_regmap(test, &config, &data); 737 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 738 if (IS_ERR(map)) 739 return; 740 741 /* We should have read the cache defaults back from the map */ 742 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 743 KUNIT_EXPECT_EQ(test, config.cache_type != REGCACHE_NONE, data->read[i]); 744 data->read[i] = false; 745 } 746 747 /* Read back the expected default data */ 748 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, 0, rval, 749 BLOCK_TEST_SIZE)); 750 KUNIT_EXPECT_MEMEQ(test, data->vals, rval, sizeof(rval)); 751 752 /* The data should have been read from cache if there was one */ 753 for (i = 0; i < BLOCK_TEST_SIZE; i++) 754 KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]); 755 } 756 757 static void register_patch(struct kunit *test) 758 { 759 struct regmap *map; 760 struct regmap_config config; 761 struct regmap_ram_data *data; 762 struct reg_sequence patch[2]; 763 unsigned int rval[BLOCK_TEST_SIZE]; 764 int i; 765 766 /* We need defaults so readback works */ 767 config = test_regmap_config; 768 config.num_reg_defaults = BLOCK_TEST_SIZE; 769 770 map = gen_regmap(test, &config, &data); 771 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 772 if (IS_ERR(map)) 773 return; 774 775 /* Stash the original values */ 776 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, 0, rval, 777 BLOCK_TEST_SIZE)); 778 779 /* Patch a couple of values */ 780 patch[0].reg = 2; 781 patch[0].def = rval[2] + 1; 782 patch[0].delay_us = 0; 783 patch[1].reg = 5; 784 patch[1].def = rval[5] + 1; 785 patch[1].delay_us = 0; 786 KUNIT_EXPECT_EQ(test, 0, regmap_register_patch(map, patch, 787 ARRAY_SIZE(patch))); 788 789 /* Only the patched registers are written */ 790 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 791 switch (i) { 792 case 2: 793 case 5: 794 KUNIT_EXPECT_TRUE(test, data->written[i]); 795 KUNIT_EXPECT_EQ(test, data->vals[i], rval[i] + 1); 796 break; 797 default: 798 KUNIT_EXPECT_FALSE(test, data->written[i]); 799 KUNIT_EXPECT_EQ(test, data->vals[i], rval[i]); 800 break; 801 } 802 } 803 } 804 805 static void stride(struct kunit *test) 806 { 807 struct regmap *map; 808 struct regmap_config config; 809 struct regmap_ram_data *data; 810 unsigned int rval; 811 int i; 812 813 config = test_regmap_config; 814 config.reg_stride = 2; 815 config.num_reg_defaults = BLOCK_TEST_SIZE / 2; 816 817 /* 818 * Allow one extra register so that the read/written arrays 819 * are sized big enough to include an entry for the odd 820 * address past the final reg_default register. 821 */ 822 config.max_register = BLOCK_TEST_SIZE; 823 824 map = gen_regmap(test, &config, &data); 825 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 826 if (IS_ERR(map)) 827 return; 828 829 /* Only even addresses can be accessed, try both read and write */ 830 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 831 data->read[i] = false; 832 data->written[i] = false; 833 834 if (i % 2) { 835 KUNIT_EXPECT_NE(test, 0, regmap_read(map, i, &rval)); 836 KUNIT_EXPECT_NE(test, 0, regmap_write(map, i, rval)); 837 KUNIT_EXPECT_FALSE(test, data->read[i]); 838 KUNIT_EXPECT_FALSE(test, data->written[i]); 839 } else { 840 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval)); 841 KUNIT_EXPECT_EQ(test, data->vals[i], rval); 842 KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, 843 data->read[i]); 844 845 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, rval)); 846 KUNIT_EXPECT_TRUE(test, data->written[i]); 847 } 848 } 849 } 850 851 static const struct regmap_range_cfg test_range = { 852 .selector_reg = 1, 853 .selector_mask = 0xff, 854 855 .window_start = 4, 856 .window_len = 10, 857 858 .range_min = 20, 859 .range_max = 40, 860 }; 861 862 static bool test_range_window_volatile(struct device *dev, unsigned int reg) 863 { 864 if (reg >= test_range.window_start && 865 reg <= test_range.window_start + test_range.window_len) 866 return true; 867 868 return false; 869 } 870 871 static bool test_range_all_volatile(struct device *dev, unsigned int reg) 872 { 873 if (test_range_window_volatile(dev, reg)) 874 return true; 875 876 if (reg >= test_range.range_min && reg <= test_range.range_max) 877 return true; 878 879 return false; 880 } 881 882 static void basic_ranges(struct kunit *test) 883 { 884 struct regmap *map; 885 struct regmap_config config; 886 struct regmap_ram_data *data; 887 unsigned int val; 888 int i; 889 890 config = test_regmap_config; 891 config.volatile_reg = test_range_all_volatile; 892 config.ranges = &test_range; 893 config.num_ranges = 1; 894 config.max_register = test_range.range_max; 895 896 map = gen_regmap(test, &config, &data); 897 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 898 if (IS_ERR(map)) 899 return; 900 901 for (i = test_range.range_min; i < test_range.range_max; i++) { 902 data->read[i] = false; 903 data->written[i] = false; 904 } 905 906 /* Reset the page to a non-zero value to trigger a change */ 907 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, test_range.selector_reg, 908 test_range.range_max)); 909 910 /* Check we set the page and use the window for writes */ 911 data->written[test_range.selector_reg] = false; 912 data->written[test_range.window_start] = false; 913 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, test_range.range_min, 0)); 914 KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]); 915 KUNIT_EXPECT_TRUE(test, data->written[test_range.window_start]); 916 917 data->written[test_range.selector_reg] = false; 918 data->written[test_range.window_start] = false; 919 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 920 test_range.range_min + 921 test_range.window_len, 922 0)); 923 KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]); 924 KUNIT_EXPECT_TRUE(test, data->written[test_range.window_start]); 925 926 /* Same for reads */ 927 data->written[test_range.selector_reg] = false; 928 data->read[test_range.window_start] = false; 929 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, test_range.range_min, &val)); 930 KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]); 931 KUNIT_EXPECT_TRUE(test, data->read[test_range.window_start]); 932 933 data->written[test_range.selector_reg] = false; 934 data->read[test_range.window_start] = false; 935 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 936 test_range.range_min + 937 test_range.window_len, 938 &val)); 939 KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]); 940 KUNIT_EXPECT_TRUE(test, data->read[test_range.window_start]); 941 942 /* No physical access triggered in the virtual range */ 943 for (i = test_range.range_min; i < test_range.range_max; i++) { 944 KUNIT_EXPECT_FALSE(test, data->read[i]); 945 KUNIT_EXPECT_FALSE(test, data->written[i]); 946 } 947 } 948 949 /* Try to stress dynamic creation of cache data structures */ 950 static void stress_insert(struct kunit *test) 951 { 952 struct regmap *map; 953 struct regmap_config config; 954 struct regmap_ram_data *data; 955 unsigned int rval, *vals; 956 size_t buf_sz; 957 int i; 958 959 config = test_regmap_config; 960 config.max_register = 300; 961 962 map = gen_regmap(test, &config, &data); 963 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 964 if (IS_ERR(map)) 965 return; 966 967 buf_sz = array_size(sizeof(*vals), config.max_register); 968 vals = kunit_kmalloc(test, buf_sz, GFP_KERNEL); 969 KUNIT_ASSERT_FALSE(test, vals == NULL); 970 971 get_random_bytes(vals, buf_sz); 972 973 /* Write data into the map/cache in ever decreasing strides */ 974 for (i = 0; i < config.max_register; i += 100) 975 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i])); 976 for (i = 0; i < config.max_register; i += 50) 977 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i])); 978 for (i = 0; i < config.max_register; i += 25) 979 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i])); 980 for (i = 0; i < config.max_register; i += 10) 981 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i])); 982 for (i = 0; i < config.max_register; i += 5) 983 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i])); 984 for (i = 0; i < config.max_register; i += 3) 985 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i])); 986 for (i = 0; i < config.max_register; i += 2) 987 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i])); 988 for (i = 0; i < config.max_register; i++) 989 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i])); 990 991 /* Do reads from the cache (if there is one) match? */ 992 for (i = 0; i < config.max_register; i ++) { 993 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval)); 994 KUNIT_EXPECT_EQ(test, rval, vals[i]); 995 KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]); 996 } 997 } 998 999 static void cache_bypass(struct kunit *test) 1000 { 1001 const struct regmap_test_param *param = test->param_value; 1002 struct regmap *map; 1003 struct regmap_config config; 1004 struct regmap_ram_data *data; 1005 unsigned int val, rval; 1006 1007 config = test_regmap_config; 1008 1009 map = gen_regmap(test, &config, &data); 1010 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1011 if (IS_ERR(map)) 1012 return; 1013 1014 get_random_bytes(&val, sizeof(val)); 1015 1016 /* Ensure the cache has a value in it */ 1017 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg, val)); 1018 1019 /* Bypass then write a different value */ 1020 regcache_cache_bypass(map, true); 1021 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg, val + 1)); 1022 1023 /* Read the bypassed value */ 1024 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg, &rval)); 1025 KUNIT_EXPECT_EQ(test, val + 1, rval); 1026 KUNIT_EXPECT_EQ(test, data->vals[param->from_reg], rval); 1027 1028 /* Disable bypass, the cache should still return the original value */ 1029 regcache_cache_bypass(map, false); 1030 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg, &rval)); 1031 KUNIT_EXPECT_EQ(test, val, rval); 1032 } 1033 1034 static void cache_sync_marked_dirty(struct kunit *test) 1035 { 1036 const struct regmap_test_param *param = test->param_value; 1037 struct regmap *map; 1038 struct regmap_config config; 1039 struct regmap_ram_data *data; 1040 unsigned int val[BLOCK_TEST_SIZE]; 1041 int i; 1042 1043 config = test_regmap_config; 1044 1045 map = gen_regmap(test, &config, &data); 1046 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1047 if (IS_ERR(map)) 1048 return; 1049 1050 get_random_bytes(&val, sizeof(val)); 1051 1052 /* Put some data into the cache */ 1053 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, param->from_reg, val, 1054 BLOCK_TEST_SIZE)); 1055 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1056 data->written[param->from_reg + i] = false; 1057 1058 /* Trash the data on the device itself then resync */ 1059 regcache_mark_dirty(map); 1060 memset(data->vals, 0, sizeof(val)); 1061 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1062 1063 /* Did we just write the correct data out? */ 1064 KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], val, sizeof(val)); 1065 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1066 KUNIT_EXPECT_EQ(test, true, data->written[param->from_reg + i]); 1067 } 1068 1069 static void cache_sync_after_cache_only(struct kunit *test) 1070 { 1071 const struct regmap_test_param *param = test->param_value; 1072 struct regmap *map; 1073 struct regmap_config config; 1074 struct regmap_ram_data *data; 1075 unsigned int val[BLOCK_TEST_SIZE]; 1076 unsigned int val_mask; 1077 int i; 1078 1079 config = test_regmap_config; 1080 1081 map = gen_regmap(test, &config, &data); 1082 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1083 if (IS_ERR(map)) 1084 return; 1085 1086 val_mask = GENMASK(config.val_bits - 1, 0); 1087 get_random_bytes(&val, sizeof(val)); 1088 1089 /* Put some data into the cache */ 1090 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, param->from_reg, val, 1091 BLOCK_TEST_SIZE)); 1092 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1093 data->written[param->from_reg + i] = false; 1094 1095 /* Set cache-only and change the values */ 1096 regcache_cache_only(map, true); 1097 for (i = 0; i < ARRAY_SIZE(val); ++i) 1098 val[i] = ~val[i] & val_mask; 1099 1100 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, param->from_reg, val, 1101 BLOCK_TEST_SIZE)); 1102 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1103 KUNIT_EXPECT_FALSE(test, data->written[param->from_reg + i]); 1104 1105 KUNIT_EXPECT_MEMNEQ(test, &data->vals[param->from_reg], val, sizeof(val)); 1106 1107 /* Exit cache-only and sync the cache without marking hardware registers dirty */ 1108 regcache_cache_only(map, false); 1109 1110 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1111 1112 /* Did we just write the correct data out? */ 1113 KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], val, sizeof(val)); 1114 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1115 KUNIT_EXPECT_TRUE(test, data->written[param->from_reg + i]); 1116 } 1117 1118 static void cache_sync_defaults_marked_dirty(struct kunit *test) 1119 { 1120 const struct regmap_test_param *param = test->param_value; 1121 struct regmap *map; 1122 struct regmap_config config; 1123 struct regmap_ram_data *data; 1124 unsigned int val; 1125 int i; 1126 1127 config = test_regmap_config; 1128 config.num_reg_defaults = BLOCK_TEST_SIZE; 1129 1130 map = gen_regmap(test, &config, &data); 1131 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1132 if (IS_ERR(map)) 1133 return; 1134 1135 get_random_bytes(&val, sizeof(val)); 1136 1137 /* Change the value of one register */ 1138 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + 2, val)); 1139 1140 /* Resync */ 1141 regcache_mark_dirty(map); 1142 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1143 data->written[param->from_reg + i] = false; 1144 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1145 1146 /* Did we just sync the one register we touched? */ 1147 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1148 KUNIT_EXPECT_EQ(test, i == 2, data->written[param->from_reg + i]); 1149 1150 /* Rewrite registers back to their defaults */ 1151 for (i = 0; i < config.num_reg_defaults; ++i) 1152 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, config.reg_defaults[i].reg, 1153 config.reg_defaults[i].def)); 1154 1155 /* 1156 * Resync after regcache_mark_dirty() should not write out registers 1157 * that are at default value 1158 */ 1159 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1160 data->written[param->from_reg + i] = false; 1161 regcache_mark_dirty(map); 1162 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1163 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1164 KUNIT_EXPECT_FALSE(test, data->written[param->from_reg + i]); 1165 } 1166 1167 static void cache_sync_default_after_cache_only(struct kunit *test) 1168 { 1169 const struct regmap_test_param *param = test->param_value; 1170 struct regmap *map; 1171 struct regmap_config config; 1172 struct regmap_ram_data *data; 1173 unsigned int orig_val; 1174 int i; 1175 1176 config = test_regmap_config; 1177 config.num_reg_defaults = BLOCK_TEST_SIZE; 1178 1179 map = gen_regmap(test, &config, &data); 1180 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1181 if (IS_ERR(map)) 1182 return; 1183 1184 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + 2, &orig_val)); 1185 1186 /* Enter cache-only and change the value of one register */ 1187 regcache_cache_only(map, true); 1188 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + 2, orig_val + 1)); 1189 1190 /* Exit cache-only and resync, should write out the changed register */ 1191 regcache_cache_only(map, false); 1192 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1193 data->written[param->from_reg + i] = false; 1194 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1195 1196 /* Was the register written out? */ 1197 KUNIT_EXPECT_TRUE(test, data->written[param->from_reg + 2]); 1198 KUNIT_EXPECT_EQ(test, data->vals[param->from_reg + 2], orig_val + 1); 1199 1200 /* Enter cache-only and write register back to its default value */ 1201 regcache_cache_only(map, true); 1202 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + 2, orig_val)); 1203 1204 /* Resync should write out the new value */ 1205 regcache_cache_only(map, false); 1206 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1207 data->written[param->from_reg + i] = false; 1208 1209 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1210 KUNIT_EXPECT_TRUE(test, data->written[param->from_reg + 2]); 1211 KUNIT_EXPECT_EQ(test, data->vals[param->from_reg + 2], orig_val); 1212 } 1213 1214 static void cache_sync_readonly(struct kunit *test) 1215 { 1216 const struct regmap_test_param *param = test->param_value; 1217 struct regmap *map; 1218 struct regmap_config config; 1219 struct regmap_ram_data *data; 1220 unsigned int val; 1221 int i; 1222 1223 config = test_regmap_config; 1224 config.writeable_reg = reg_5_false; 1225 1226 map = gen_regmap(test, &config, &data); 1227 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1228 if (IS_ERR(map)) 1229 return; 1230 1231 /* Read all registers to fill the cache */ 1232 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1233 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, &val)); 1234 1235 /* Change the value of all registers, readonly should fail */ 1236 get_random_bytes(&val, sizeof(val)); 1237 regcache_cache_only(map, true); 1238 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1239 KUNIT_EXPECT_EQ(test, i != 5, regmap_write(map, param->from_reg + i, val) == 0); 1240 regcache_cache_only(map, false); 1241 1242 /* Resync */ 1243 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1244 data->written[param->from_reg + i] = false; 1245 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1246 1247 /* Did that match what we see on the device? */ 1248 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1249 KUNIT_EXPECT_EQ(test, i != 5, data->written[param->from_reg + i]); 1250 } 1251 1252 static void cache_sync_patch(struct kunit *test) 1253 { 1254 const struct regmap_test_param *param = test->param_value; 1255 struct regmap *map; 1256 struct regmap_config config; 1257 struct regmap_ram_data *data; 1258 struct reg_sequence patch[2]; 1259 unsigned int rval[BLOCK_TEST_SIZE], val; 1260 int i; 1261 1262 /* We need defaults so readback works */ 1263 config = test_regmap_config; 1264 config.num_reg_defaults = BLOCK_TEST_SIZE; 1265 1266 map = gen_regmap(test, &config, &data); 1267 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1268 if (IS_ERR(map)) 1269 return; 1270 1271 /* Stash the original values */ 1272 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, param->from_reg, rval, 1273 BLOCK_TEST_SIZE)); 1274 1275 /* Patch a couple of values */ 1276 patch[0].reg = param->from_reg + 2; 1277 patch[0].def = rval[2] + 1; 1278 patch[0].delay_us = 0; 1279 patch[1].reg = param->from_reg + 5; 1280 patch[1].def = rval[5] + 1; 1281 patch[1].delay_us = 0; 1282 KUNIT_EXPECT_EQ(test, 0, regmap_register_patch(map, patch, 1283 ARRAY_SIZE(patch))); 1284 1285 /* Sync the cache */ 1286 regcache_mark_dirty(map); 1287 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1288 data->written[param->from_reg + i] = false; 1289 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1290 1291 /* The patch should be on the device but not in the cache */ 1292 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 1293 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, &val)); 1294 KUNIT_EXPECT_EQ(test, val, rval[i]); 1295 1296 switch (i) { 1297 case 2: 1298 case 5: 1299 KUNIT_EXPECT_EQ(test, true, data->written[param->from_reg + i]); 1300 KUNIT_EXPECT_EQ(test, data->vals[param->from_reg + i], rval[i] + 1); 1301 break; 1302 default: 1303 KUNIT_EXPECT_EQ(test, false, data->written[param->from_reg + i]); 1304 KUNIT_EXPECT_EQ(test, data->vals[param->from_reg + i], rval[i]); 1305 break; 1306 } 1307 } 1308 } 1309 1310 static void cache_drop(struct kunit *test) 1311 { 1312 const struct regmap_test_param *param = test->param_value; 1313 struct regmap *map; 1314 struct regmap_config config; 1315 struct regmap_ram_data *data; 1316 unsigned int rval[BLOCK_TEST_SIZE]; 1317 int i; 1318 1319 config = test_regmap_config; 1320 config.num_reg_defaults = BLOCK_TEST_SIZE; 1321 1322 map = gen_regmap(test, &config, &data); 1323 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1324 if (IS_ERR(map)) 1325 return; 1326 1327 /* Ensure the data is read from the cache */ 1328 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1329 data->read[param->from_reg + i] = false; 1330 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, param->from_reg, rval, 1331 BLOCK_TEST_SIZE)); 1332 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 1333 KUNIT_EXPECT_FALSE(test, data->read[param->from_reg + i]); 1334 data->read[param->from_reg + i] = false; 1335 } 1336 KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], rval, sizeof(rval)); 1337 1338 /* Drop some registers */ 1339 KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, param->from_reg + 3, 1340 param->from_reg + 5)); 1341 1342 /* Reread and check only the dropped registers hit the device. */ 1343 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, param->from_reg, rval, 1344 BLOCK_TEST_SIZE)); 1345 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1346 KUNIT_EXPECT_EQ(test, data->read[param->from_reg + i], i >= 3 && i <= 5); 1347 KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], rval, sizeof(rval)); 1348 } 1349 1350 static void cache_drop_with_non_contiguous_ranges(struct kunit *test) 1351 { 1352 const struct regmap_test_param *param = test->param_value; 1353 struct regmap *map; 1354 struct regmap_config config; 1355 struct regmap_ram_data *data; 1356 unsigned int val[4][BLOCK_TEST_SIZE]; 1357 unsigned int reg; 1358 const int num_ranges = ARRAY_SIZE(val) * 2; 1359 int rangeidx, i; 1360 1361 static_assert(ARRAY_SIZE(val) == 4); 1362 1363 config = test_regmap_config; 1364 config.max_register = param->from_reg + (num_ranges * BLOCK_TEST_SIZE); 1365 1366 map = gen_regmap(test, &config, &data); 1367 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1368 if (IS_ERR(map)) 1369 return; 1370 1371 for (i = 0; i < config.max_register + 1; i++) 1372 data->written[i] = false; 1373 1374 /* Create non-contiguous cache blocks by writing every other range */ 1375 get_random_bytes(&val, sizeof(val)); 1376 for (rangeidx = 0; rangeidx < num_ranges; rangeidx += 2) { 1377 reg = param->from_reg + (rangeidx * BLOCK_TEST_SIZE); 1378 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, reg, 1379 &val[rangeidx / 2], 1380 BLOCK_TEST_SIZE)); 1381 KUNIT_EXPECT_MEMEQ(test, &data->vals[reg], 1382 &val[rangeidx / 2], sizeof(val[rangeidx / 2])); 1383 } 1384 1385 /* Check that odd ranges weren't written */ 1386 for (rangeidx = 1; rangeidx < num_ranges; rangeidx += 2) { 1387 reg = param->from_reg + (rangeidx * BLOCK_TEST_SIZE); 1388 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1389 KUNIT_EXPECT_FALSE(test, data->written[reg + i]); 1390 } 1391 1392 /* Drop range 2 */ 1393 reg = param->from_reg + (2 * BLOCK_TEST_SIZE); 1394 KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, reg, reg + BLOCK_TEST_SIZE - 1)); 1395 1396 /* Drop part of range 4 */ 1397 reg = param->from_reg + (4 * BLOCK_TEST_SIZE); 1398 KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, reg + 3, reg + 5)); 1399 1400 /* Mark dirty and reset mock registers to 0 */ 1401 regcache_mark_dirty(map); 1402 for (i = 0; i < config.max_register + 1; i++) { 1403 data->vals[i] = 0; 1404 data->written[i] = false; 1405 } 1406 1407 /* The registers that were dropped from range 4 should now remain at 0 */ 1408 val[4 / 2][3] = 0; 1409 val[4 / 2][4] = 0; 1410 val[4 / 2][5] = 0; 1411 1412 /* Sync and check that the expected register ranges were written */ 1413 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1414 1415 /* Check that odd ranges weren't written */ 1416 for (rangeidx = 1; rangeidx < num_ranges; rangeidx += 2) { 1417 reg = param->from_reg + (rangeidx * BLOCK_TEST_SIZE); 1418 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1419 KUNIT_EXPECT_FALSE(test, data->written[reg + i]); 1420 } 1421 1422 /* Check that even ranges (except 2 and 4) were written */ 1423 for (rangeidx = 0; rangeidx < num_ranges; rangeidx += 2) { 1424 if ((rangeidx == 2) || (rangeidx == 4)) 1425 continue; 1426 1427 reg = param->from_reg + (rangeidx * BLOCK_TEST_SIZE); 1428 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1429 KUNIT_EXPECT_TRUE(test, data->written[reg + i]); 1430 1431 KUNIT_EXPECT_MEMEQ(test, &data->vals[reg], 1432 &val[rangeidx / 2], sizeof(val[rangeidx / 2])); 1433 } 1434 1435 /* Check that range 2 wasn't written */ 1436 reg = param->from_reg + (2 * BLOCK_TEST_SIZE); 1437 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1438 KUNIT_EXPECT_FALSE(test, data->written[reg + i]); 1439 1440 /* Check that range 4 was partially written */ 1441 reg = param->from_reg + (4 * BLOCK_TEST_SIZE); 1442 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1443 KUNIT_EXPECT_EQ(test, data->written[reg + i], i < 3 || i > 5); 1444 1445 KUNIT_EXPECT_MEMEQ(test, &data->vals[reg], &val[4 / 2], sizeof(val[4 / 2])); 1446 1447 /* Nothing before param->from_reg should have been written */ 1448 for (i = 0; i < param->from_reg; i++) 1449 KUNIT_EXPECT_FALSE(test, data->written[i]); 1450 } 1451 1452 static void cache_drop_all_and_sync_marked_dirty(struct kunit *test) 1453 { 1454 const struct regmap_test_param *param = test->param_value; 1455 struct regmap *map; 1456 struct regmap_config config; 1457 struct regmap_ram_data *data; 1458 unsigned int rval[BLOCK_TEST_SIZE]; 1459 int i; 1460 1461 config = test_regmap_config; 1462 config.num_reg_defaults = BLOCK_TEST_SIZE; 1463 1464 map = gen_regmap(test, &config, &data); 1465 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1466 if (IS_ERR(map)) 1467 return; 1468 1469 /* Ensure the data is read from the cache */ 1470 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1471 data->read[param->from_reg + i] = false; 1472 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, param->from_reg, rval, 1473 BLOCK_TEST_SIZE)); 1474 KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], rval, sizeof(rval)); 1475 1476 /* Change all values in cache from defaults */ 1477 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1478 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + i, rval[i] + 1)); 1479 1480 /* Drop all registers */ 1481 KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, 0, config.max_register)); 1482 1483 /* Mark dirty and cache sync should not write anything. */ 1484 regcache_mark_dirty(map); 1485 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1486 data->written[param->from_reg + i] = false; 1487 1488 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1489 for (i = 0; i <= config.max_register; i++) 1490 KUNIT_EXPECT_FALSE(test, data->written[i]); 1491 } 1492 1493 static void cache_drop_all_and_sync_no_defaults(struct kunit *test) 1494 { 1495 const struct regmap_test_param *param = test->param_value; 1496 struct regmap *map; 1497 struct regmap_config config; 1498 struct regmap_ram_data *data; 1499 unsigned int rval[BLOCK_TEST_SIZE]; 1500 int i; 1501 1502 config = test_regmap_config; 1503 1504 map = gen_regmap(test, &config, &data); 1505 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1506 if (IS_ERR(map)) 1507 return; 1508 1509 /* Ensure the data is read from the cache */ 1510 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1511 data->read[param->from_reg + i] = false; 1512 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, param->from_reg, rval, 1513 BLOCK_TEST_SIZE)); 1514 KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], rval, sizeof(rval)); 1515 1516 /* Change all values in cache */ 1517 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1518 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + i, rval[i] + 1)); 1519 1520 /* Drop all registers */ 1521 KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, 0, config.max_register)); 1522 1523 /* 1524 * Sync cache without marking it dirty. All registers were dropped 1525 * so the cache should not have any entries to write out. 1526 */ 1527 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1528 data->written[param->from_reg + i] = false; 1529 1530 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1531 for (i = 0; i <= config.max_register; i++) 1532 KUNIT_EXPECT_FALSE(test, data->written[i]); 1533 } 1534 1535 static void cache_drop_all_and_sync_has_defaults(struct kunit *test) 1536 { 1537 const struct regmap_test_param *param = test->param_value; 1538 struct regmap *map; 1539 struct regmap_config config; 1540 struct regmap_ram_data *data; 1541 unsigned int rval[BLOCK_TEST_SIZE]; 1542 int i; 1543 1544 config = test_regmap_config; 1545 config.num_reg_defaults = BLOCK_TEST_SIZE; 1546 1547 map = gen_regmap(test, &config, &data); 1548 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1549 if (IS_ERR(map)) 1550 return; 1551 1552 /* Ensure the data is read from the cache */ 1553 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1554 data->read[param->from_reg + i] = false; 1555 KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, param->from_reg, rval, 1556 BLOCK_TEST_SIZE)); 1557 KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], rval, sizeof(rval)); 1558 1559 /* Change all values in cache from defaults */ 1560 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1561 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + i, rval[i] + 1)); 1562 1563 /* Drop all registers */ 1564 KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, 0, config.max_register)); 1565 1566 /* 1567 * Sync cache without marking it dirty. All registers were dropped 1568 * so the cache should not have any entries to write out. 1569 */ 1570 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1571 data->written[param->from_reg + i] = false; 1572 1573 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1574 for (i = 0; i <= config.max_register; i++) 1575 KUNIT_EXPECT_FALSE(test, data->written[i]); 1576 } 1577 1578 static void cache_present(struct kunit *test) 1579 { 1580 const struct regmap_test_param *param = test->param_value; 1581 struct regmap *map; 1582 struct regmap_config config; 1583 struct regmap_ram_data *data; 1584 unsigned int val; 1585 int i; 1586 1587 config = test_regmap_config; 1588 1589 map = gen_regmap(test, &config, &data); 1590 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1591 if (IS_ERR(map)) 1592 return; 1593 1594 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1595 data->read[param->from_reg + i] = false; 1596 1597 /* No defaults so no registers cached. */ 1598 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1599 KUNIT_ASSERT_FALSE(test, regcache_reg_cached(map, param->from_reg + i)); 1600 1601 /* We didn't trigger any reads */ 1602 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1603 KUNIT_ASSERT_FALSE(test, data->read[param->from_reg + i]); 1604 1605 /* Fill the cache */ 1606 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1607 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, &val)); 1608 1609 /* Now everything should be cached */ 1610 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1611 KUNIT_ASSERT_TRUE(test, regcache_reg_cached(map, param->from_reg + i)); 1612 } 1613 1614 static void cache_write_zero(struct kunit *test) 1615 { 1616 const struct regmap_test_param *param = test->param_value; 1617 struct regmap *map; 1618 struct regmap_config config; 1619 struct regmap_ram_data *data; 1620 unsigned int val; 1621 int i; 1622 1623 config = test_regmap_config; 1624 1625 map = gen_regmap(test, &config, &data); 1626 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1627 if (IS_ERR(map)) 1628 return; 1629 1630 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1631 data->read[param->from_reg + i] = false; 1632 1633 /* No defaults so no registers cached. */ 1634 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1635 KUNIT_ASSERT_FALSE(test, regcache_reg_cached(map, param->from_reg + i)); 1636 1637 /* We didn't trigger any reads */ 1638 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1639 KUNIT_ASSERT_FALSE(test, data->read[param->from_reg + i]); 1640 1641 /* Write a zero value */ 1642 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 1, 0)); 1643 1644 /* Read that zero value back */ 1645 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 1, &val)); 1646 KUNIT_EXPECT_EQ(test, 0, val); 1647 1648 /* From the cache? */ 1649 KUNIT_ASSERT_TRUE(test, regcache_reg_cached(map, 1)); 1650 1651 /* Try to throw it away */ 1652 KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, 1, 1)); 1653 KUNIT_ASSERT_FALSE(test, regcache_reg_cached(map, 1)); 1654 } 1655 1656 static const struct regmap_test_param high_bit_cache_types_list[] = { 1657 { .cache = REGCACHE_RBTREE, .from_reg = HIGH_BIT_REG, 1658 .base_reg = HIGH_BIT_REG }, 1659 { .cache = REGCACHE_MAPLE, .from_reg = HIGH_BIT_REG, 1660 .base_reg = HIGH_BIT_REG }, 1661 }; 1662 1663 KUNIT_ARRAY_PARAM(high_bit_cache_types, high_bit_cache_types_list, param_to_desc); 1664 1665 /* 1666 * Dynamically allocated cache types should support registers with the 1667 * high bit set, the backend will return an error for any operation on 1668 * a register below the expected window. 1669 */ 1670 static void cache_high_bit_reg(struct kunit *test) 1671 { 1672 const struct regmap_test_param *param = test->param_value; 1673 struct regmap_ram_data *data; 1674 struct regmap_config config; 1675 struct regmap *map; 1676 unsigned int val[BLOCK_TEST_SIZE], rval; 1677 int i; 1678 1679 config = test_regmap_config; 1680 1681 map = gen_regmap(test, &config, &data); 1682 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1683 if (IS_ERR(map)) 1684 return; 1685 1686 get_random_bytes(&val, sizeof(val)); 1687 1688 /* No defaults so no registers cached */ 1689 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1690 KUNIT_EXPECT_FALSE(test, regcache_reg_cached(map, param->from_reg + i)); 1691 1692 /* Writes should reach the device */ 1693 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1694 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + i, 1695 val[i])); 1696 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 1697 KUNIT_EXPECT_TRUE(test, data->written[i]); 1698 KUNIT_EXPECT_EQ(test, val[i], data->vals[i]); 1699 } 1700 1701 /* Reads should be satisfied from the cache */ 1702 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 1703 KUNIT_EXPECT_TRUE(test, regcache_reg_cached(map, param->from_reg + i)); 1704 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, 1705 &rval)); 1706 KUNIT_EXPECT_EQ(test, val[i], rval); 1707 KUNIT_EXPECT_FALSE(test, data->read[i]); 1708 } 1709 1710 /* Trash the data on the device then resync */ 1711 regcache_mark_dirty(map); 1712 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 1713 data->vals[i] = 0; 1714 data->written[i] = false; 1715 } 1716 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 1717 1718 /* Did we just write the correct data out? */ 1719 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 1720 KUNIT_EXPECT_TRUE(test, data->written[i]); 1721 KUNIT_EXPECT_EQ(test, val[i], data->vals[i]); 1722 } 1723 1724 /* Drop some registers */ 1725 KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, param->from_reg + 3, 1726 param->from_reg + 5)); 1727 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1728 KUNIT_EXPECT_EQ(test, i < 3 || i > 5, 1729 regcache_reg_cached(map, param->from_reg + i)); 1730 1731 /* Reread and check only the dropped registers hit the device */ 1732 for (i = 0; i < BLOCK_TEST_SIZE; i++) 1733 data->read[i] = false; 1734 for (i = 0; i < BLOCK_TEST_SIZE; i++) { 1735 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, 1736 &rval)); 1737 KUNIT_EXPECT_EQ(test, val[i], rval); 1738 KUNIT_EXPECT_EQ(test, i >= 3 && i <= 5, data->read[i]); 1739 } 1740 } 1741 1742 /* Check that caching the window register works with sync */ 1743 static void cache_range_window_reg(struct kunit *test) 1744 { 1745 struct regmap *map; 1746 struct regmap_config config; 1747 struct regmap_ram_data *data; 1748 unsigned int val; 1749 int i; 1750 1751 config = test_regmap_config; 1752 config.volatile_reg = test_range_window_volatile; 1753 config.ranges = &test_range; 1754 config.num_ranges = 1; 1755 config.max_register = test_range.range_max; 1756 1757 map = gen_regmap(test, &config, &data); 1758 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1759 if (IS_ERR(map)) 1760 return; 1761 1762 /* Write new values to the entire range */ 1763 for (i = test_range.range_min; i <= test_range.range_max; i++) 1764 KUNIT_ASSERT_EQ(test, 0, regmap_write(map, i, 0)); 1765 1766 val = data->vals[test_range.selector_reg] & test_range.selector_mask; 1767 KUNIT_ASSERT_EQ(test, val, 2); 1768 1769 /* Write to the first register in the range to reset the page */ 1770 KUNIT_ASSERT_EQ(test, 0, regmap_write(map, test_range.range_min, 0)); 1771 val = data->vals[test_range.selector_reg] & test_range.selector_mask; 1772 KUNIT_ASSERT_EQ(test, val, 0); 1773 1774 /* Trigger a cache sync */ 1775 regcache_mark_dirty(map); 1776 KUNIT_ASSERT_EQ(test, 0, regcache_sync(map)); 1777 1778 /* Write to the first register again, the page should be reset */ 1779 KUNIT_ASSERT_EQ(test, 0, regmap_write(map, test_range.range_min, 0)); 1780 val = data->vals[test_range.selector_reg] & test_range.selector_mask; 1781 KUNIT_ASSERT_EQ(test, val, 0); 1782 1783 /* Trigger another cache sync */ 1784 regcache_mark_dirty(map); 1785 KUNIT_ASSERT_EQ(test, 0, regcache_sync(map)); 1786 1787 /* Write to the last register again, the page should be reset */ 1788 KUNIT_ASSERT_EQ(test, 0, regmap_write(map, test_range.range_max, 0)); 1789 val = data->vals[test_range.selector_reg] & test_range.selector_mask; 1790 KUNIT_ASSERT_EQ(test, val, 2); 1791 } 1792 1793 static const struct regmap_test_param raw_types_list[] = { 1794 { .cache = REGCACHE_NONE, .val_endian = REGMAP_ENDIAN_LITTLE }, 1795 { .cache = REGCACHE_NONE, .val_endian = REGMAP_ENDIAN_BIG }, 1796 { .cache = REGCACHE_FLAT, .val_endian = REGMAP_ENDIAN_LITTLE }, 1797 { .cache = REGCACHE_FLAT, .val_endian = REGMAP_ENDIAN_BIG }, 1798 { .cache = REGCACHE_FLAT_S, .val_endian = REGMAP_ENDIAN_LITTLE }, 1799 { .cache = REGCACHE_FLAT_S, .val_endian = REGMAP_ENDIAN_BIG }, 1800 { .cache = REGCACHE_RBTREE, .val_endian = REGMAP_ENDIAN_LITTLE }, 1801 { .cache = REGCACHE_RBTREE, .val_endian = REGMAP_ENDIAN_BIG }, 1802 { .cache = REGCACHE_MAPLE, .val_endian = REGMAP_ENDIAN_LITTLE }, 1803 { .cache = REGCACHE_MAPLE, .val_endian = REGMAP_ENDIAN_BIG }, 1804 }; 1805 1806 KUNIT_ARRAY_PARAM(raw_test_types, raw_types_list, param_to_desc); 1807 1808 static const struct regmap_test_param raw_cache_types_list[] = { 1809 { .cache = REGCACHE_FLAT, .val_endian = REGMAP_ENDIAN_LITTLE }, 1810 { .cache = REGCACHE_FLAT, .val_endian = REGMAP_ENDIAN_BIG }, 1811 { .cache = REGCACHE_FLAT_S, .val_endian = REGMAP_ENDIAN_LITTLE }, 1812 { .cache = REGCACHE_FLAT_S, .val_endian = REGMAP_ENDIAN_BIG }, 1813 { .cache = REGCACHE_RBTREE, .val_endian = REGMAP_ENDIAN_LITTLE }, 1814 { .cache = REGCACHE_RBTREE, .val_endian = REGMAP_ENDIAN_BIG }, 1815 { .cache = REGCACHE_MAPLE, .val_endian = REGMAP_ENDIAN_LITTLE }, 1816 { .cache = REGCACHE_MAPLE, .val_endian = REGMAP_ENDIAN_BIG }, 1817 }; 1818 1819 KUNIT_ARRAY_PARAM(raw_test_cache_types, raw_cache_types_list, param_to_desc); 1820 1821 static const struct regmap_config raw_regmap_config = { 1822 .max_register = BLOCK_TEST_SIZE, 1823 1824 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1825 .reg_bits = 16, 1826 .val_bits = 16, 1827 }; 1828 1829 static struct regmap *gen_raw_regmap(struct kunit *test, 1830 struct regmap_config *config, 1831 struct regmap_ram_data **data) 1832 { 1833 struct regmap_test_priv *priv = test->priv; 1834 const struct regmap_test_param *param = test->param_value; 1835 u16 *buf; 1836 struct regmap *ret = ERR_PTR(-ENOMEM); 1837 int i, error; 1838 struct reg_default *defaults; 1839 size_t size; 1840 1841 config->cache_type = param->cache; 1842 config->val_format_endian = param->val_endian; 1843 config->disable_locking = config->cache_type == REGCACHE_RBTREE || 1844 config->cache_type == REGCACHE_MAPLE; 1845 1846 size = array_size(config->max_register + 1, BITS_TO_BYTES(config->reg_bits)); 1847 buf = kmalloc(size, GFP_KERNEL); 1848 if (!buf) 1849 return ERR_PTR(-ENOMEM); 1850 1851 get_random_bytes(buf, size); 1852 1853 *data = kzalloc_obj(**data); 1854 if (!(*data)) 1855 goto out_free; 1856 (*data)->vals = (void *)buf; 1857 1858 config->num_reg_defaults = config->max_register + 1; 1859 defaults = kunit_kcalloc(test, 1860 config->num_reg_defaults, 1861 sizeof(struct reg_default), 1862 GFP_KERNEL); 1863 if (!defaults) 1864 goto out_free; 1865 config->reg_defaults = defaults; 1866 1867 for (i = 0; i < config->num_reg_defaults; i++) { 1868 defaults[i].reg = i; 1869 switch (param->val_endian) { 1870 case REGMAP_ENDIAN_LITTLE: 1871 defaults[i].def = le16_to_cpu(buf[i]); 1872 break; 1873 case REGMAP_ENDIAN_BIG: 1874 defaults[i].def = be16_to_cpu(buf[i]); 1875 break; 1876 default: 1877 ret = ERR_PTR(-EINVAL); 1878 goto out_free; 1879 } 1880 } 1881 1882 /* 1883 * We use the defaults in the tests but they don't make sense 1884 * to the core if there's no cache. 1885 */ 1886 if (config->cache_type == REGCACHE_NONE) 1887 config->num_reg_defaults = 0; 1888 1889 ret = regmap_init_raw_ram(priv->dev, config, *data); 1890 if (IS_ERR(ret)) 1891 goto out_free; 1892 1893 /* This calls regmap_exit() on failure, which frees buf and *data */ 1894 error = kunit_add_action_or_reset(test, regmap_exit_action, ret); 1895 if (error) 1896 ret = ERR_PTR(error); 1897 1898 return ret; 1899 1900 out_free: 1901 kfree(buf); 1902 kfree(*data); 1903 1904 return ret; 1905 } 1906 1907 static void raw_read_defaults_single(struct kunit *test) 1908 { 1909 struct regmap *map; 1910 struct regmap_config config; 1911 struct regmap_ram_data *data; 1912 unsigned int rval; 1913 int i; 1914 1915 config = raw_regmap_config; 1916 1917 map = gen_raw_regmap(test, &config, &data); 1918 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1919 if (IS_ERR(map)) 1920 return; 1921 1922 /* Check that we can read the defaults via the API */ 1923 for (i = 0; i < config.max_register + 1; i++) { 1924 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval)); 1925 KUNIT_EXPECT_EQ(test, config.reg_defaults[i].def, rval); 1926 } 1927 } 1928 1929 static void raw_read_defaults(struct kunit *test) 1930 { 1931 struct regmap *map; 1932 struct regmap_config config; 1933 struct regmap_ram_data *data; 1934 u16 *rval; 1935 u16 def; 1936 size_t val_len; 1937 int i; 1938 1939 config = raw_regmap_config; 1940 1941 map = gen_raw_regmap(test, &config, &data); 1942 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1943 if (IS_ERR(map)) 1944 return; 1945 1946 val_len = array_size(sizeof(*rval), config.max_register + 1); 1947 rval = kunit_kmalloc(test, val_len, GFP_KERNEL); 1948 KUNIT_ASSERT_TRUE(test, rval != NULL); 1949 if (!rval) 1950 return; 1951 1952 /* Check that we can read the defaults via the API */ 1953 KUNIT_EXPECT_EQ(test, 0, regmap_raw_read(map, 0, rval, val_len)); 1954 for (i = 0; i < config.max_register + 1; i++) { 1955 def = config.reg_defaults[i].def; 1956 if (config.val_format_endian == REGMAP_ENDIAN_BIG) { 1957 KUNIT_EXPECT_EQ(test, def, be16_to_cpu((__force __be16)rval[i])); 1958 } else { 1959 KUNIT_EXPECT_EQ(test, def, le16_to_cpu((__force __le16)rval[i])); 1960 } 1961 } 1962 } 1963 1964 static void raw_write_read_single(struct kunit *test) 1965 { 1966 struct regmap *map; 1967 struct regmap_config config; 1968 struct regmap_ram_data *data; 1969 u16 val; 1970 unsigned int rval; 1971 1972 config = raw_regmap_config; 1973 1974 map = gen_raw_regmap(test, &config, &data); 1975 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 1976 if (IS_ERR(map)) 1977 return; 1978 1979 get_random_bytes(&val, sizeof(val)); 1980 1981 /* If we write a value to a register we can read it back */ 1982 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 0, val)); 1983 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 0, &rval)); 1984 KUNIT_EXPECT_EQ(test, val, rval); 1985 } 1986 1987 static void raw_write(struct kunit *test) 1988 { 1989 struct regmap *map; 1990 struct regmap_config config; 1991 struct regmap_ram_data *data; 1992 u16 *hw_buf; 1993 u16 val[2]; 1994 unsigned int rval; 1995 int i; 1996 1997 config = raw_regmap_config; 1998 1999 map = gen_raw_regmap(test, &config, &data); 2000 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 2001 if (IS_ERR(map)) 2002 return; 2003 2004 hw_buf = (u16 *)data->vals; 2005 2006 get_random_bytes(&val, sizeof(val)); 2007 2008 /* Do a raw write */ 2009 KUNIT_EXPECT_EQ(test, 0, regmap_raw_write(map, 2, val, sizeof(val))); 2010 2011 /* We should read back the new values, and defaults for the rest */ 2012 for (i = 0; i < config.max_register + 1; i++) { 2013 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval)); 2014 2015 switch (i) { 2016 case 2: 2017 case 3: 2018 if (config.val_format_endian == REGMAP_ENDIAN_BIG) { 2019 KUNIT_EXPECT_EQ(test, rval, 2020 be16_to_cpu((__force __be16)val[i % 2])); 2021 } else { 2022 KUNIT_EXPECT_EQ(test, rval, 2023 le16_to_cpu((__force __le16)val[i % 2])); 2024 } 2025 break; 2026 default: 2027 KUNIT_EXPECT_EQ(test, config.reg_defaults[i].def, rval); 2028 break; 2029 } 2030 } 2031 2032 /* The values should appear in the "hardware" */ 2033 KUNIT_EXPECT_MEMEQ(test, &hw_buf[2], val, sizeof(val)); 2034 } 2035 2036 static bool reg_zero(struct device *dev, unsigned int reg) 2037 { 2038 return reg == 0; 2039 } 2040 2041 static bool ram_reg_zero(struct regmap_ram_data *data, unsigned int reg) 2042 { 2043 return reg == 0; 2044 } 2045 2046 static void raw_noinc_write(struct kunit *test) 2047 { 2048 struct regmap *map; 2049 struct regmap_config config; 2050 struct regmap_ram_data *data; 2051 unsigned int val; 2052 u16 val_test, val_last; 2053 u16 val_array[BLOCK_TEST_SIZE]; 2054 2055 config = raw_regmap_config; 2056 config.volatile_reg = reg_zero; 2057 config.writeable_noinc_reg = reg_zero; 2058 config.readable_noinc_reg = reg_zero; 2059 2060 map = gen_raw_regmap(test, &config, &data); 2061 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 2062 if (IS_ERR(map)) 2063 return; 2064 2065 data->noinc_reg = ram_reg_zero; 2066 2067 get_random_bytes(&val_array, sizeof(val_array)); 2068 2069 if (config.val_format_endian == REGMAP_ENDIAN_BIG) { 2070 val_test = be16_to_cpu(val_array[1]) + 100; 2071 val_last = be16_to_cpu(val_array[BLOCK_TEST_SIZE - 1]); 2072 } else { 2073 val_test = le16_to_cpu(val_array[1]) + 100; 2074 val_last = le16_to_cpu(val_array[BLOCK_TEST_SIZE - 1]); 2075 } 2076 2077 /* Put some data into the register following the noinc register */ 2078 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 1, val_test)); 2079 2080 /* Write some data to the noinc register */ 2081 KUNIT_EXPECT_EQ(test, 0, regmap_noinc_write(map, 0, val_array, 2082 sizeof(val_array))); 2083 2084 /* We should read back the last value written */ 2085 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 0, &val)); 2086 KUNIT_ASSERT_EQ(test, val_last, val); 2087 2088 /* Make sure we didn't touch the register after the noinc register */ 2089 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 1, &val)); 2090 KUNIT_ASSERT_EQ(test, val_test, val); 2091 } 2092 2093 static void raw_sync(struct kunit *test) 2094 { 2095 struct regmap *map; 2096 struct regmap_config config; 2097 struct regmap_ram_data *data; 2098 u16 val[3]; 2099 u16 *hw_buf; 2100 unsigned int rval; 2101 int i; 2102 2103 config = raw_regmap_config; 2104 2105 map = gen_raw_regmap(test, &config, &data); 2106 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 2107 if (IS_ERR(map)) 2108 return; 2109 2110 hw_buf = (u16 *)data->vals; 2111 2112 get_changed_bytes(&hw_buf[2], &val[0], sizeof(val)); 2113 2114 /* Do a regular write and a raw write in cache only mode */ 2115 regcache_cache_only(map, true); 2116 KUNIT_EXPECT_EQ(test, 0, regmap_raw_write(map, 2, val, 2117 sizeof(u16) * 2)); 2118 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 4, val[2])); 2119 2120 /* We should read back the new values, and defaults for the rest */ 2121 for (i = 0; i < config.max_register + 1; i++) { 2122 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval)); 2123 2124 switch (i) { 2125 case 2: 2126 case 3: 2127 if (config.val_format_endian == REGMAP_ENDIAN_BIG) { 2128 KUNIT_EXPECT_EQ(test, rval, 2129 be16_to_cpu((__force __be16)val[i - 2])); 2130 } else { 2131 KUNIT_EXPECT_EQ(test, rval, 2132 le16_to_cpu((__force __le16)val[i - 2])); 2133 } 2134 break; 2135 case 4: 2136 KUNIT_EXPECT_EQ(test, rval, val[i - 2]); 2137 break; 2138 default: 2139 KUNIT_EXPECT_EQ(test, config.reg_defaults[i].def, rval); 2140 break; 2141 } 2142 } 2143 2144 /* 2145 * The value written via _write() was translated by the core, 2146 * translate the original copy for comparison purposes. 2147 */ 2148 if (config.val_format_endian == REGMAP_ENDIAN_BIG) 2149 val[2] = cpu_to_be16(val[2]); 2150 else 2151 val[2] = cpu_to_le16(val[2]); 2152 2153 /* The values should not appear in the "hardware" */ 2154 KUNIT_EXPECT_MEMNEQ(test, &hw_buf[2], &val[0], sizeof(val)); 2155 2156 for (i = 0; i < config.max_register + 1; i++) 2157 data->written[i] = false; 2158 2159 /* Do the sync */ 2160 regcache_cache_only(map, false); 2161 regcache_mark_dirty(map); 2162 KUNIT_EXPECT_EQ(test, 0, regcache_sync(map)); 2163 2164 /* The values should now appear in the "hardware" */ 2165 KUNIT_EXPECT_MEMEQ(test, &hw_buf[2], &val[0], sizeof(val)); 2166 } 2167 2168 static void raw_ranges(struct kunit *test) 2169 { 2170 struct regmap *map; 2171 struct regmap_config config; 2172 struct regmap_ram_data *data; 2173 unsigned int val; 2174 int i; 2175 2176 config = raw_regmap_config; 2177 config.volatile_reg = test_range_all_volatile; 2178 config.ranges = &test_range; 2179 config.num_ranges = 1; 2180 config.max_register = test_range.range_max; 2181 2182 map = gen_raw_regmap(test, &config, &data); 2183 KUNIT_ASSERT_FALSE(test, IS_ERR(map)); 2184 if (IS_ERR(map)) 2185 return; 2186 2187 /* Reset the page to a non-zero value to trigger a change */ 2188 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, test_range.selector_reg, 2189 test_range.range_max)); 2190 2191 /* Check we set the page and use the window for writes */ 2192 data->written[test_range.selector_reg] = false; 2193 data->written[test_range.window_start] = false; 2194 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, test_range.range_min, 0)); 2195 KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]); 2196 KUNIT_EXPECT_TRUE(test, data->written[test_range.window_start]); 2197 2198 data->written[test_range.selector_reg] = false; 2199 data->written[test_range.window_start] = false; 2200 KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 2201 test_range.range_min + 2202 test_range.window_len, 2203 0)); 2204 KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]); 2205 KUNIT_EXPECT_TRUE(test, data->written[test_range.window_start]); 2206 2207 /* Same for reads */ 2208 data->written[test_range.selector_reg] = false; 2209 data->read[test_range.window_start] = false; 2210 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, test_range.range_min, &val)); 2211 KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]); 2212 KUNIT_EXPECT_TRUE(test, data->read[test_range.window_start]); 2213 2214 data->written[test_range.selector_reg] = false; 2215 data->read[test_range.window_start] = false; 2216 KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 2217 test_range.range_min + 2218 test_range.window_len, 2219 &val)); 2220 KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]); 2221 KUNIT_EXPECT_TRUE(test, data->read[test_range.window_start]); 2222 2223 /* No physical access triggered in the virtual range */ 2224 for (i = test_range.range_min; i < test_range.range_max; i++) { 2225 KUNIT_EXPECT_FALSE(test, data->read[i]); 2226 KUNIT_EXPECT_FALSE(test, data->written[i]); 2227 } 2228 } 2229 2230 static struct kunit_case regmap_test_cases[] = { 2231 KUNIT_CASE_PARAM(basic_read_write, regcache_types_gen_params), 2232 KUNIT_CASE_PARAM(read_bypassed, real_cache_types_gen_params), 2233 KUNIT_CASE_PARAM(read_bypassed_volatile, real_cache_types_gen_params), 2234 KUNIT_CASE_PARAM(bulk_write, regcache_types_gen_params), 2235 KUNIT_CASE_PARAM(bulk_read, regcache_types_gen_params), 2236 KUNIT_CASE_PARAM(multi_write, regcache_types_gen_params), 2237 KUNIT_CASE_PARAM(multi_read, regcache_types_gen_params), 2238 KUNIT_CASE_PARAM(write_readonly, regcache_types_gen_params), 2239 KUNIT_CASE_PARAM(read_writeonly, regcache_types_gen_params), 2240 KUNIT_CASE_PARAM(reg_defaults, regcache_types_gen_params), 2241 KUNIT_CASE_PARAM(reg_default_callback_populates_flat_cache, 2242 flat_cache_types_gen_params), 2243 KUNIT_CASE_PARAM(reg_defaults_read_dev, regcache_types_gen_params), 2244 KUNIT_CASE_PARAM(register_patch, regcache_types_gen_params), 2245 KUNIT_CASE_PARAM(stride, regcache_types_gen_params), 2246 KUNIT_CASE_PARAM(basic_ranges, regcache_types_gen_params), 2247 KUNIT_CASE_PARAM(stress_insert, regcache_types_gen_params), 2248 KUNIT_CASE_PARAM(cache_bypass, real_cache_types_gen_params), 2249 KUNIT_CASE_PARAM(cache_sync_marked_dirty, real_cache_types_gen_params), 2250 KUNIT_CASE_PARAM(cache_sync_after_cache_only, real_cache_types_gen_params), 2251 KUNIT_CASE_PARAM(cache_sync_defaults_marked_dirty, real_cache_types_gen_params), 2252 KUNIT_CASE_PARAM(cache_sync_default_after_cache_only, real_cache_types_gen_params), 2253 KUNIT_CASE_PARAM(cache_sync_readonly, real_cache_types_gen_params), 2254 KUNIT_CASE_PARAM(cache_sync_patch, real_cache_types_gen_params), 2255 KUNIT_CASE_PARAM(cache_drop, sparse_cache_types_gen_params), 2256 KUNIT_CASE_PARAM(cache_drop_with_non_contiguous_ranges, sparse_cache_types_gen_params), 2257 KUNIT_CASE_PARAM(cache_drop_all_and_sync_marked_dirty, sparse_cache_types_gen_params), 2258 KUNIT_CASE_PARAM(cache_drop_all_and_sync_no_defaults, sparse_cache_types_gen_params), 2259 KUNIT_CASE_PARAM(cache_drop_all_and_sync_has_defaults, sparse_cache_types_gen_params), 2260 KUNIT_CASE_PARAM(cache_present, sparse_cache_types_gen_params), 2261 KUNIT_CASE_PARAM(cache_write_zero, sparse_cache_types_gen_params), 2262 KUNIT_CASE_PARAM(cache_high_bit_reg, high_bit_cache_types_gen_params), 2263 KUNIT_CASE_PARAM(cache_range_window_reg, real_cache_types_only_gen_params), 2264 2265 KUNIT_CASE_PARAM(raw_read_defaults_single, raw_test_types_gen_params), 2266 KUNIT_CASE_PARAM(raw_read_defaults, raw_test_types_gen_params), 2267 KUNIT_CASE_PARAM(raw_write_read_single, raw_test_types_gen_params), 2268 KUNIT_CASE_PARAM(raw_write, raw_test_types_gen_params), 2269 KUNIT_CASE_PARAM(raw_noinc_write, raw_test_types_gen_params), 2270 KUNIT_CASE_PARAM(raw_sync, raw_test_cache_types_gen_params), 2271 KUNIT_CASE_PARAM(raw_ranges, raw_test_cache_types_gen_params), 2272 {} 2273 }; 2274 2275 static int regmap_test_init(struct kunit *test) 2276 { 2277 struct regmap_test_priv *priv; 2278 struct device *dev; 2279 2280 priv = kunit_kzalloc(test, sizeof(*priv), GFP_KERNEL); 2281 if (!priv) 2282 return -ENOMEM; 2283 2284 test->priv = priv; 2285 2286 dev = kunit_device_register(test, "regmap_test"); 2287 if (IS_ERR(dev)) 2288 return PTR_ERR(dev); 2289 2290 priv->dev = get_device(dev); 2291 dev_set_drvdata(dev, test); 2292 2293 return 0; 2294 } 2295 2296 static void regmap_test_exit(struct kunit *test) 2297 { 2298 struct regmap_test_priv *priv = test->priv; 2299 2300 /* Destroy the dummy struct device */ 2301 if (priv && priv->dev) 2302 put_device(priv->dev); 2303 } 2304 2305 static struct kunit_suite regmap_test_suite = { 2306 .name = "regmap", 2307 .init = regmap_test_init, 2308 .exit = regmap_test_exit, 2309 .test_cases = regmap_test_cases, 2310 }; 2311 kunit_test_suite(regmap_test_suite); 2312 2313 MODULE_DESCRIPTION("Regmap KUnit tests"); 2314 MODULE_LICENSE("GPL v2"); 2315