1 /*
2 * Copyright 2012-2026 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
28
29 #include "dc_types.h"
30 #include "dc_state.h"
31 #include "dc_plane.h"
32 #include "dc_probe.h"
33 #include "grph_object_defs.h"
34 #include "logger_types.h"
35 #include "hdcp_msg_types.h"
36 #include "gpio_types.h"
37 #include "link_service_types.h"
38 #include "grph_object_ctrl_defs.h"
39 #include <inc/hw/opp.h>
40
41 #include "hwss/hw_sequencer.h"
42 #include "inc/compressor.h"
43 #include "inc/hw/dmcu.h"
44 #include "dml/display_mode_lib.h"
45
46 #include "dml2_0/dml2_wrapper.h"
47
48 #include "dmub/inc/dmub_cmd.h"
49
50 #include "dml/dml1_frl_cap_chk.h"
51
52 #include "sspl/dc_spl_types.h"
53
54 struct abm_save_restore;
55
56 /* forward declaration */
57 struct aux_payload;
58 struct set_config_cmd_payload;
59 struct dmub_notification;
60 struct dcn_hubbub_reg_state;
61 struct dcn_hubp_reg_state;
62 struct dcn_dpp_reg_state;
63 struct dcn_mpc_reg_state;
64 struct dcn_opp_reg_state;
65 struct dcn_dsc_reg_state;
66 struct dcn_optc_reg_state;
67 struct dcn_dccg_reg_state;
68
69 #define DC_VER "3.2.392"
70
71 /**
72 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
73 */
74 #define MAX_SURFACES 4
75 /**
76 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW
77 */
78 #define MAX_PLANES 6
79 #define MAX_STREAMS 6
80 #define MIN_VIEWPORT_SIZE 12
81 #define MAX_NUM_EDP 2
82 #define MAX_SUPPORTED_FORMATS 7
83
84 #define MAX_HOST_ROUTERS_NUM 3
85 #define MAX_DPIA_PER_HOST_ROUTER 3
86 #define MAX_DPIA_NUM (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER)
87
88 #define NUM_FAST_FLIPS_TO_STEADY_STATE 20
89
90 struct frl_cap_chk_intermediates_fixed31_32 {
91 int c_frl_sb;
92 struct fixed31_32 overhead_sb;
93 struct fixed31_32 overhead_rs;
94 struct fixed31_32 overhead_map;
95 struct fixed31_32 overhead_min;
96 struct fixed31_32 overhead_max;
97 struct fixed31_32 f_pixel_clock_max;
98 struct fixed31_32 t_line;
99 struct fixed31_32 r_bit_min;
100 struct fixed31_32 r_frl_char_min;
101 struct fixed31_32 c_frl_line;
102 struct fixed31_32 ap;
103 struct fixed31_32 r_ap;
104 struct fixed31_32 avg_audio_packets_line;
105 struct fixed31_32 margin;
106 int audio_packets_line;
107 int blank_audio_min;
108 };
109
110 struct frl_cap_chk_params_fixed31_32 {
111 int lanes;
112 struct fixed31_32 f_pixel_clock_nominal; /* Pixel Clock rate (Hz) */
113 struct fixed31_32 r_bit_nominal; /* FRL bitrate (bps) */
114 int audio_packet_type;
115 struct fixed31_32 f_audio; /* Audio rate (Hz) */
116 int h_active; /* Active pixels per line */
117 int h_blank; /* Blanking pixels per line */
118 int bpc; /* Bits per component */
119 int vic; /* Video Identification Code */
120
121 enum hdmi_frl_pixel_encoding pixel_encoding;
122
123 bool compressed; /* set to true if DSC is enabled */
124 bool bypass_hc_target_calc; /* debug only */
125 bool allow_all_bpp; /* dsc_all_bpp */
126
127 /* DSC parameters */
128 int slices;
129 int slice_width;
130 struct fixed31_32 bpp_target;
131 int layout;
132 int acat; /* not supported */
133
134 /* outputs */
135 struct frl_dml_borrow_params borrow_params;
136 int average_tribyte_rate;
137 };
138
139 /* Display Core Interfaces */
140 struct dc_versions {
141 const char *dc_ver;
142 struct dmcu_version dmcu_version;
143 };
144
145 enum dp_protocol_version {
146 DP_VERSION_1_4 = 0,
147 DP_VERSION_2_1,
148 DP_VERSION_UNKNOWN,
149 };
150
151 enum dc_plane_type {
152 DC_PLANE_TYPE_INVALID,
153 DC_PLANE_TYPE_DCE_RGB,
154 DC_PLANE_TYPE_DCE_UNDERLAY,
155 DC_PLANE_TYPE_DCN_UNIVERSAL,
156 };
157
158 // Sizes defined as multiples of 64KB
159 enum det_size {
160 DET_SIZE_DEFAULT = 0,
161 DET_SIZE_192KB = 3,
162 DET_SIZE_256KB = 4,
163 DET_SIZE_320KB = 5,
164 DET_SIZE_384KB = 6
165 };
166
167
168 struct dc_plane_cap {
169 enum dc_plane_type type;
170 uint32_t per_pixel_alpha : 1;
171 struct {
172 uint32_t argb8888 : 1;
173 uint32_t nv12 : 1;
174 uint32_t fp16 : 1;
175 uint32_t p010 : 1;
176 uint32_t ayuv : 1;
177 uint32_t yuy2 : 1; // Packed 422 8bpc
178 uint32_t y210 : 1; // Packed 422 10bpc
179 uint32_t y212 : 1; // Packed 422 12bpc
180 uint32_t p208 : 1; // Planar 422 8bpc
181 uint32_t p210 : 1; // Planar 422 10bpc
182 uint32_t p212 : 1; // Planar 422 12bpc
183 /* Not all caps will be used/supported */
184 } pixel_format_support;
185 // max upscaling factor x1000
186 // upscaling factors are always >= 1
187 // for example, 1080p -> 8K is 4.0, or 4000 raw value
188 struct {
189 uint32_t argb8888;
190 uint32_t nv12;
191 uint32_t fp16;
192 } max_upscale_factor;
193 // max downscale factor x1000
194 // downscale factors are always <= 1
195 // for example, 8K -> 1080p is 0.25, or 250 raw value
196 struct {
197 uint32_t argb8888;
198 uint32_t nv12;
199 uint32_t fp16;
200 } max_downscale_factor;
201 // minimal width/height
202 uint32_t min_width;
203 uint32_t min_height;
204 };
205
206 /**
207 * DOC: color-management-caps
208 *
209 * **Color management caps (DPP and MPC)**
210 *
211 * Modules/color calculates various color operations which are translated to
212 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
213 * DCN1, every new generation comes with fairly major differences in color
214 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
215 * decide mapping to HW block based on logical capabilities.
216 */
217
218 /**
219 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
220 * @srgb: RGB color space transfer func
221 * @bt2020: BT.2020 transfer func
222 * @gamma2_2: standard gamma
223 * @pq: perceptual quantizer transfer function
224 * @hlg: hybrid log–gamma transfer function
225 */
226 struct rom_curve_caps {
227 uint16_t srgb : 1;
228 uint16_t bt2020 : 1;
229 uint16_t gamma2_2 : 1;
230 uint16_t pq : 1;
231 uint16_t hlg : 1;
232 };
233
234 /**
235 * struct dpp_color_caps - color pipeline capabilities for display pipe and
236 * plane blocks
237 *
238 * @dcn_arch: all DCE generations treated the same
239 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
240 * just plain 256-entry lookup
241 * @icsc: input color space conversion
242 * @dgam_ram: programmable degamma LUT
243 * @post_csc: post color space conversion, before gamut remap
244 * @gamma_corr: degamma correction
245 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
246 * with MPC by setting mpc:shared_3d_lut flag
247 * @ogam_ram: programmable out/blend gamma LUT
248 * @ocsc: output color space conversion
249 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
250 * @upsp_pre_scaler: Ability to upsample 420/422 before scaling
251 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
252 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
253 *
254 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
255 */
256 struct dpp_color_caps {
257 uint16_t dcn_arch : 1;
258 uint16_t input_lut_shared : 1;
259 uint16_t icsc : 1;
260 uint16_t dgam_ram : 1;
261 uint16_t post_csc : 1;
262 uint16_t gamma_corr : 1;
263 uint16_t hw_3d_lut : 1;
264 uint16_t ogam_ram : 1;
265 uint16_t ocsc : 1;
266 uint16_t dgam_rom_for_yuv : 1;
267 uint16_t upsp_pre_scaler : 1;
268 struct rom_curve_caps dgam_rom_caps;
269 struct rom_curve_caps ogam_rom_caps;
270 };
271
272 /* Below structure is to describe the HW support for mem layout, extend support
273 range to match what OS could handle in the roadmap */
274 struct lut3d_caps {
275 uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */
276 struct {
277 uint32_t swizzle_3d_rgb : 1;
278 uint32_t swizzle_3d_bgr : 1;
279 uint32_t linear_1d : 1;
280 } mem_layout_support;
281 struct {
282 uint32_t unorm_12msb : 1;
283 uint32_t unorm_12lsb : 1;
284 uint32_t float_fp1_5_10 : 1;
285 } mem_format_support;
286 struct {
287 uint32_t order_rgba : 1;
288 uint32_t order_bgra : 1;
289 } mem_pixel_order_support;
290 /*< size options are 9, 17, 33, 45, 65 */
291 struct {
292 uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */
293 uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */
294 uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */
295 uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */
296 uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */
297 } lut_dim_caps;
298 };
299
300 /**
301 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
302 * plane combined blocks
303 *
304 * @gamut_remap: color transformation matrix
305 * @ogam_ram: programmable out gamma LUT
306 * @ocsc: output color space conversion matrix
307 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT
308 * @num_rmcm_3dluts: number of RMCM 3D LUTS; always assumes a preceding shaper LUT
309 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single
310 * instance
311 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
312 * @mcm_3d_lut_caps: HW support cap for MCM LUT memory
313 * @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory
314 * @preblend: whether color manager supports preblend with MPC
315 */
316 struct mpc_color_caps {
317 uint16_t gamut_remap : 1;
318 uint16_t ogam_ram : 1;
319 uint16_t ocsc : 1;
320 uint16_t num_3dluts : 3;
321 uint16_t num_rmcm_3dluts : 3;
322 uint16_t shared_3d_lut:1;
323 struct rom_curve_caps ogam_rom_caps;
324 struct lut3d_caps mcm_3d_lut_caps;
325 struct lut3d_caps rmcm_3d_lut_caps;
326 bool preblend;
327 struct fixed31_32 max_gamut_remap_coeff;
328 };
329
330 /**
331 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
332 * @dpp: color pipes caps for DPP
333 * @mpc: color pipes caps for MPC
334 */
335 struct dc_color_caps {
336 struct dpp_color_caps dpp;
337 struct mpc_color_caps mpc;
338 };
339
340 struct dc_dmub_caps {
341 bool psr;
342 bool mclk_sw;
343 bool subvp_psr;
344 bool gecc_enable;
345 uint8_t fams_ver;
346 bool aux_backlight_support;
347 };
348
349 struct dc_scl_caps {
350 bool sharpener_support;
351 };
352
353 struct dc_check_config {
354 /**
355 * max video plane width that can be safely assumed to be always
356 * supported by single DPP pipe.
357 */
358 unsigned int max_optimizable_video_width;
359 bool enable_legacy_fast_update;
360
361 bool deferred_transition_state;
362 unsigned int transition_countdown_to_steady_state;
363 };
364
365 struct dc_caps {
366 uint32_t max_streams;
367 uint32_t max_links;
368 uint32_t max_audios;
369 uint32_t max_slave_planes;
370 uint32_t max_slave_yuv_planes;
371 uint32_t max_slave_rgb_planes;
372 uint32_t max_planes;
373 uint32_t max_downscale_ratio;
374 uint32_t i2c_speed_in_khz;
375 uint32_t i2c_speed_in_khz_hdcp;
376 uint32_t dmdata_alloc_size;
377 unsigned int max_cursor_size;
378 unsigned int max_buffered_cursor_size;
379 unsigned int max_video_width;
380 unsigned int min_horizontal_blanking_period;
381 int linear_pitch_alignment;
382 bool dcc_const_color;
383 bool dynamic_audio;
384 bool is_apu;
385 bool dual_link_dvi;
386 bool post_blend_color_processing;
387 bool force_dp_tps4_for_cp2520;
388 bool disable_dp_clk_share;
389 bool psp_setup_panel_mode;
390 bool extended_aux_timeout_support;
391 bool dmcub_support;
392 bool zstate_support;
393 bool ips_support;
394 bool ips_v2_support;
395 uint32_t num_of_internal_disp;
396 enum dp_protocol_version max_dp_protocol_version;
397 bool hdmi_hpo;
398 unsigned int mall_size_per_mem_channel;
399 unsigned int mall_size_total;
400 unsigned int cursor_cache_size;
401 struct dc_plane_cap planes[MAX_PLANES];
402 struct dc_color_caps color;
403 struct dc_dmub_caps dmub_caps;
404 bool dp_hpo;
405 bool dp_hdmi21_pcon_support;
406 bool edp_dsc_support;
407 bool vbios_lttpr_aware;
408 bool vbios_lttpr_enable;
409 bool fused_io_supported;
410 uint32_t max_otg_num;
411 uint32_t max_cab_allocation_bytes;
412 uint32_t cache_line_size;
413 uint32_t cache_num_ways;
414 uint16_t subvp_fw_processing_delay_us;
415 uint8_t subvp_drr_max_vblank_margin_us;
416 uint16_t subvp_prefetch_end_to_mall_start_us;
417 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
418 uint16_t subvp_pstate_allow_width_us;
419 uint16_t subvp_vertical_int_margin_us;
420 bool seamless_odm;
421 uint32_t max_v_total;
422 bool vtotal_limited_by_fp2;
423 uint32_t max_disp_clock_khz_at_vmin;
424 uint8_t subvp_drr_vblank_start_margin_us;
425 bool cursor_not_scaled;
426 bool dcmode_power_limits_present;
427 bool sequential_ono;
428 /* Conservative limit for DCC cases which require ODM4:1 to support*/
429 uint32_t dcc_plane_width_limit;
430 struct dc_scl_caps scl_caps;
431 uint8_t num_of_host_routers;
432 uint8_t num_of_dpias_per_host_router;
433 /* limit of the ODM only, could be limited by other factors (like pipe count)*/
434 uint8_t max_odm_combine_factor;
435 };
436
437 struct dc_bug_wa {
438 bool no_connect_phy_config;
439 bool dedcn20_305_wa;
440 bool skip_clock_update;
441 bool lt_early_cr_pattern;
442 struct {
443 uint8_t uclk : 1;
444 uint8_t fclk : 1;
445 uint8_t dcfclk : 1;
446 uint8_t dcfclk_ds: 1;
447 } clock_update_disable_mask;
448 bool skip_psr_ips_crtc_disable;
449 };
450 struct dc_dcc_surface_param {
451 struct dc_size surface_size;
452 enum surface_pixel_format format;
453 unsigned int plane0_pitch;
454 struct dc_size plane1_size;
455 unsigned int plane1_pitch;
456 union {
457 enum swizzle_mode_values swizzle_mode;
458 enum swizzle_mode_addr3_values swizzle_mode_addr3;
459 };
460 enum dc_scan_direction scan;
461 };
462
463 struct dc_dcc_setting {
464 unsigned int max_compressed_blk_size;
465 unsigned int max_uncompressed_blk_size;
466 bool independent_64b_blks;
467 //These bitfields to be used starting with DCN 3.0
468 struct {
469 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)
470 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0
471 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0
472 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case)
473 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case)
474 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x
475 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case)
476 } dcc_controls;
477 };
478
479 struct dc_surface_dcc_cap {
480 union {
481 struct {
482 struct dc_dcc_setting rgb;
483 } grph;
484
485 struct {
486 struct dc_dcc_setting luma;
487 struct dc_dcc_setting chroma;
488 } video;
489 };
490
491 bool capable;
492 bool const_color_support;
493 };
494
495 struct dc_static_screen_params {
496 struct {
497 bool force_trigger;
498 bool cursor_update;
499 bool surface_update;
500 bool overlay_update;
501 } triggers;
502 unsigned int num_frames;
503 };
504
505
506 /* Surface update type is used by dc_update_surfaces_and_stream
507 * The update type is determined at the very beginning of the function based
508 * on parameters passed in and decides how much programming (or updating) is
509 * going to be done during the call.
510 *
511 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
512 * logical calculations or hardware register programming. This update MUST be
513 * ISR safe on windows. Currently fast update will only be used to flip surface
514 * address.
515 *
516 * UPDATE_TYPE_MED is used for slower updates which require significant hw
517 * re-programming however do not affect bandwidth consumption or clock
518 * requirements. At present, this is the level at which front end updates
519 * that do not require us to run bw_calcs happen. These are in/out transfer func
520 * updates, viewport offset changes, recout size changes and pixel depth changes.
521 * This update can be done at ISR, but we want to minimize how often this happens.
522 *
523 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
524 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
525 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
526 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
527 * a full update. This cannot be done at ISR level and should be a rare event.
528 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
529 * underscan we don't expect to see this call at all.
530 */
531
532 enum dc_update_type {
533 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
534 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
535 UPDATE_TYPE_FULL, /* may need to shuffle resources */
536 };
537
538 enum dc_lock_descriptor {
539 LOCK_DESCRIPTOR_NONE = 0x0,
540 LOCK_DESCRIPTOR_STREAM = 0x1,
541 LOCK_DESCRIPTOR_LINK = 0x2,
542 LOCK_DESCRIPTOR_GLOBAL = 0x4,
543 LOCK_DESCRIPTOR_PROBE = 0x8,
544 };
545
546 struct dc_update_descriptor {
547 enum dc_update_type update_type;
548 enum dc_lock_descriptor lock_descriptor;
549 };
550
551 /* Forward declaration*/
552 struct dc;
553 struct dc_plane_state;
554 struct dc_state;
555
556 struct dc_cap_funcs {
557 bool (*get_dcc_compression_cap)(const struct dc *dc,
558 const struct dc_dcc_surface_param *input,
559 struct dc_surface_dcc_cap *output);
560 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
561 };
562
563 struct link_training_settings;
564
565 union allow_lttpr_non_transparent_mode {
566 struct {
567 bool DP1_4A : 1;
568 bool DP2_0 : 1;
569 } bits;
570 unsigned char raw;
571 };
572 /* Structure to hold configuration flags set by dm at dc creation. */
573 struct dc_config {
574 bool gpu_vm_support;
575 bool disable_disp_pll_sharing;
576 bool fbc_support;
577 bool disable_fractional_pwm;
578 bool allow_seamless_boot_optimization;
579 bool seamless_boot_edp_requested;
580 bool edp_not_connected;
581 bool edp_no_power_sequencing;
582 bool force_enum_edp;
583 bool forced_clocks;
584 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
585 bool multi_mon_pp_mclk_switch;
586 bool disable_dmcu;
587 bool allow_4to1MPC;
588 bool enable_windowed_mpo_odm;
589 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
590 uint32_t allow_edp_hotplug_detection;
591 bool skip_riommu_prefetch_wa;
592 bool clamp_min_dcfclk;
593 uint64_t vblank_alignment_dto_params;
594 uint8_t vblank_alignment_max_frame_time_diff;
595 bool is_asymmetric_memory;
596 bool is_single_rank_dimm;
597 bool is_vmin_only_asic;
598 bool use_spl;
599 bool prefer_easf;
600 bool use_pipe_ctx_sync_logic;
601 int smart_mux_version;
602 bool ignore_dpref_ss;
603 bool enable_mipi_converter_optimization;
604 bool enable_frl;
605 bool force_hdmi21_frl_enc_enable;
606 bool use_default_clock_table;
607 bool force_bios_enable_lttpr;
608 uint8_t force_bios_fixed_vs;
609 unsigned int sdpif_request_limit_words_per_umc;
610 bool dc_mode_clk_limit_support;
611 bool EnableMinDispClkODM;
612 bool enable_auto_dpm_test_logs;
613 unsigned int disable_ips;
614 unsigned int disable_ips_rcg;
615 unsigned int disable_ips_in_vpb;
616 bool disable_ips_in_dpms_off;
617 bool usb4_bw_alloc_support;
618 bool allow_0_dtb_clk;
619 bool use_assr_psp_message;
620 bool support_edp0_on_dp1;
621 unsigned int enable_fpo_flicker_detection;
622 bool disable_hbr_audio_dp2;
623 bool consolidated_dpia_dp_lt;
624 bool set_pipe_unlock_order;
625 bool enable_dpia_pre_training;
626 bool unify_link_enc_assignment;
627 bool enable_cursor_offload;
628 bool dp_connector_no_native_i2c;
629 unsigned int link_index_with_no_ddc;
630 bool frame_update_cmd_version2;
631 struct spl_sharpness_range dcn_sharpness_range;
632 struct spl_sharpness_range dcn_override_sharpness_range;
633 bool no_native422_support;
634 };
635
636 enum visual_confirm {
637 VISUAL_CONFIRM_DISABLE = 0,
638 VISUAL_CONFIRM_SURFACE = 1,
639 VISUAL_CONFIRM_HDR = 2,
640 VISUAL_CONFIRM_MPCTREE = 4,
641 VISUAL_CONFIRM_PSR = 5,
642 VISUAL_CONFIRM_SWAPCHAIN = 6,
643 VISUAL_CONFIRM_FAMS = 7,
644 VISUAL_CONFIRM_SWIZZLE = 9,
645 VISUAL_CONFIRM_SMARTMUX_DGPU = 10,
646 VISUAL_CONFIRM_REPLAY = 12,
647 VISUAL_CONFIRM_SUBVP = 14,
648 VISUAL_CONFIRM_ABM = 15,
649 VISUAL_CONFIRM_MCLK_SWITCH = 16,
650 VISUAL_CONFIRM_FAMS2 = 19,
651 VISUAL_CONFIRM_HW_CURSOR = 20,
652 VISUAL_CONFIRM_VABC = 21,
653 VISUAL_CONFIRM_DCC = 22,
654 VISUAL_CONFIRM_BOOSTED_REFRESH_RATE = 23,
655 VISUAL_CONFIRM_EXPLICIT = 0x80000000,
656 };
657
658 enum dc_psr_power_opts {
659 psr_power_opt_invalid = 0x0,
660 psr_power_opt_smu_opt_static_screen = 0x1,
661 psr_power_opt_z10_static_screen = 0x10,
662 psr_power_opt_ds_disable_allow = 0x100,
663 };
664
665 enum dml_hostvm_override_opts {
666 DML_HOSTVM_NO_OVERRIDE = 0x0,
667 DML_HOSTVM_OVERRIDE_FALSE = 0x1,
668 DML_HOSTVM_OVERRIDE_TRUE = 0x2,
669 };
670
671 enum dc_replay_power_opts {
672 replay_power_opt_invalid = 0x0,
673 replay_power_opt_smu_opt_static_screen = 0x1,
674 replay_power_opt_z10_static_screen = 0x10,
675 };
676
677 enum dcc_option {
678 DCC_ENABLE = 0,
679 DCC_DISABLE = 1,
680 DCC_HALF_REQ_DISALBE = 2,
681 };
682
683 enum in_game_fams_config {
684 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams
685 INGAME_FAMS_DISABLE, // disable in-game fams
686 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display
687 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies
688 };
689
690 /**
691 * enum pipe_split_policy - Pipe split strategy supported by DCN
692 *
693 * This enum is used to define the pipe split policy supported by DCN. By
694 * default, DC favors MPC_SPLIT_DYNAMIC.
695 */
696 enum pipe_split_policy {
697 /**
698 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
699 * pipe in order to bring the best trade-off between performance and
700 * power consumption. This is the recommended option.
701 */
702 MPC_SPLIT_DYNAMIC = 0,
703
704 /**
705 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
706 * try any sort of split optimization.
707 */
708 MPC_SPLIT_AVOID = 1,
709
710 /**
711 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
712 * optimize the pipe utilization when using a single display; if the
713 * user connects to a second display, DC will avoid pipe split.
714 */
715 MPC_SPLIT_AVOID_MULT_DISP = 2,
716 };
717
718 enum wm_report_mode {
719 WM_REPORT_DEFAULT = 0,
720 WM_REPORT_OVERRIDE = 1,
721 };
722 enum dtm_pstate{
723 dtm_level_p0 = 0,/*highest voltage*/
724 dtm_level_p1,
725 dtm_level_p2,
726 dtm_level_p3,
727 dtm_level_p4,/*when active_display_count = 0*/
728 };
729
730 enum dcn_pwr_state {
731 DCN_PWR_STATE_UNKNOWN = -1,
732 DCN_PWR_STATE_MISSION_MODE = 0,
733 DCN_PWR_STATE_LOW_POWER = 3,
734 };
735
736 enum dcn_zstate_support_state {
737 DCN_ZSTATE_SUPPORT_UNKNOWN,
738 DCN_ZSTATE_SUPPORT_ALLOW,
739 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,
740 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,
741 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
742 DCN_ZSTATE_SUPPORT_DISALLOW,
743 };
744
745 /*
746 * struct dc_clocks - DC pipe clocks
747 *
748 * For any clocks that may differ per pipe only the max is stored in this
749 * structure
750 */
751 struct dc_clocks {
752 int dispclk_khz;
753 int actual_dispclk_khz;
754 int dppclk_khz;
755 int actual_dppclk_khz;
756 int disp_dpp_voltage_level_khz;
757 int dcfclk_khz;
758 int socclk_khz;
759 int dcfclk_deep_sleep_khz;
760 int fclk_khz;
761 int phyclk_khz;
762 int dramclk_khz;
763 bool p_state_change_support;
764 enum dcn_zstate_support_state zstate_support;
765 bool dtbclk_en;
766 int ref_dtbclk_khz;
767 bool fclk_p_state_change_support;
768 enum dcn_pwr_state pwr_state;
769 /*
770 * Elements below are not compared for the purposes of
771 * optimization required
772 */
773
774 /*
775 * @cstate_allow
776 *
777 * DCN's DF C-state vote as last successfully acknowledged by PMFW.
778 * false = DCN does NOT permit DF C-state;
779 * true = DCN permits DF C-state;
780 */
781 bool cstate_allow;
782 bool prev_p_state_change_support;
783 bool fclk_prev_p_state_change_support;
784 int num_ways;
785 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM];
786
787 /*
788 * @fw_based_mclk_switching
789 *
790 * DC has a mechanism that leverage the variable refresh rate to switch
791 * memory clock in cases that we have a large latency to achieve the
792 * memory clock change and a short vblank window. DC has some
793 * requirements to enable this feature, and this field describes if the
794 * system support or not such a feature.
795 */
796 bool fw_based_mclk_switching;
797 bool fw_based_mclk_switching_shut_down;
798 bool alt_ch_pstate_switch;
799 int prev_num_ways;
800 enum dtm_pstate dtm_level;
801 int max_supported_dppclk_khz;
802 int max_supported_dispclk_khz;
803 int bw_dppclk_khz; /*a copy of dppclk_khz*/
804 int bw_dispclk_khz;
805 int idle_dramclk_khz;
806 int idle_fclk_khz;
807 int subvp_prefetch_dramclk_khz;
808 int subvp_prefetch_fclk_khz;
809 /* deprecated: use _KBps variants — will be removed after DML update */
810 unsigned int utm_urgent_bandwidth_lb_Kbps;
811 unsigned int utm_nominal_bandwidth_lb_Kbps;
812 unsigned int utm_urgent_bandwidth_lb_KBps;
813 unsigned int utm_nominal_bandwidth_lb_KBps;
814 unsigned int utm_latency_ub_index;
815 unsigned int utm_lsdma_bandwidth_lb_KBps;
816 unsigned int utm_nominal_max_latency_ub_ns;
817 unsigned int utm_nominal_avg_latency_ub_ns;
818 /* deprecated: use _KBps variant — will be removed after DML update */
819 unsigned int required_avg_active_bandwidth_Kbps;
820 unsigned int required_avg_active_bandwidth_KBps;
821
822 /* Stutter efficiency is technically not clock values
823 * but stored here so the values are part of the update_clocks call similar to num_ways
824 * Efficiencies are stored as percentage (0-100)
825 */
826 struct {
827 uint8_t base_efficiency; //LP1
828 uint8_t low_power_efficiency; //LP2
829 uint8_t z8_stutter_efficiency;
830 int z8_stutter_period;
831 } stutter_efficiency;
832 };
833
834 struct dc_bw_validation_profile {
835 bool enable;
836
837 unsigned long long total_ticks;
838 unsigned long long voltage_level_ticks;
839 unsigned long long watermark_ticks;
840 unsigned long long rq_dlg_ticks;
841
842 unsigned long long total_count;
843 unsigned long long skip_fast_count;
844 unsigned long long skip_pass_count;
845 unsigned long long skip_fail_count;
846 };
847
848 #define BW_VAL_TRACE_SETUP() \
849 unsigned long long end_tick = 0; \
850 unsigned long long voltage_level_tick = 0; \
851 unsigned long long watermark_tick = 0; \
852 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
853 dm_get_timestamp(dc->ctx) : 0
854
855 #define BW_VAL_TRACE_COUNT() \
856 if (dc->debug.bw_val_profile.enable) \
857 dc->debug.bw_val_profile.total_count++
858
859 #define BW_VAL_TRACE_SKIP(status) \
860 if (dc->debug.bw_val_profile.enable) { \
861 if (!voltage_level_tick) \
862 voltage_level_tick = dm_get_timestamp(dc->ctx); \
863 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
864 }
865
866 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
867 if (dc->debug.bw_val_profile.enable) \
868 voltage_level_tick = dm_get_timestamp(dc->ctx)
869
870 #define BW_VAL_TRACE_END_WATERMARKS() \
871 if (dc->debug.bw_val_profile.enable) \
872 watermark_tick = dm_get_timestamp(dc->ctx)
873
874 #define BW_VAL_TRACE_FINISH() \
875 if (dc->debug.bw_val_profile.enable) { \
876 end_tick = dm_get_timestamp(dc->ctx); \
877 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
878 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
879 if (watermark_tick) { \
880 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
881 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
882 } \
883 }
884
885 union mem_low_power_enable_options {
886 struct {
887 bool vga: 1;
888 bool i2c: 1;
889 bool dmcu: 1;
890 bool dscl: 1;
891 bool cm: 1;
892 bool mpc: 1;
893 bool optc: 1;
894 bool vpg: 1;
895 bool afmt: 1;
896 } bits;
897 uint32_t u32All;
898 };
899
900 union root_clock_optimization_options {
901 struct {
902 bool dpp: 1;
903 bool dsc: 1;
904 bool hdmistream: 1;
905 bool hdmichar: 1;
906 bool dpstream: 1;
907 bool symclk32_se: 1;
908 bool symclk32_le: 1;
909 bool symclk_fe: 1;
910 bool physymclk: 1;
911 bool dpiasymclk: 1;
912 uint32_t reserved: 22;
913 } bits;
914 uint32_t u32All;
915 };
916
917 union fine_grain_clock_gating_enable_options {
918 struct {
919 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */
920 bool dchub : 1; /* Display controller hub */
921 bool dchubbub : 1;
922 bool dpp : 1; /* Display pipes and planes */
923 bool opp : 1; /* Output pixel processing */
924 bool optc : 1; /* Output pipe timing combiner */
925 bool dio : 1; /* Display output */
926 bool dwb : 1; /* Display writeback */
927 bool mmhubbub : 1; /* Multimedia hub */
928 bool dmu : 1; /* Display core management unit */
929 bool az : 1; /* Azalia */
930 bool dchvm : 1;
931 bool dsc : 1; /* Display stream compression */
932
933 uint32_t reserved : 19;
934 } bits;
935 uint32_t u32All;
936 };
937
938 enum pg_hw_pipe_resources {
939 PG_HUBP = 0,
940 PG_DPP,
941 PG_DSC,
942 PG_MPCC,
943 PG_OPP,
944 PG_OPTC,
945 PG_DPSTREAM,
946 PG_HDMISTREAM,
947 PG_PHYSYMCLK,
948 PG_HW_PIPE_RESOURCES_NUM_ELEMENT
949 };
950
951 enum pg_hw_resources {
952 PG_DCCG = 0,
953 PG_DCIO,
954 PG_DIO,
955 PG_DCHUBBUB,
956 PG_DCHVM,
957 PG_DWB,
958 PG_HPO,
959 PG_DCOH,
960 PG_HW_RESOURCES_NUM_ELEMENT
961 };
962
963 struct pg_block_update {
964 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
965 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT];
966 };
967
968 union dpia_debug_options {
969 struct {
970 uint32_t disable_dpia:1; /* bit 0 */
971 uint32_t force_non_lttpr:1; /* bit 1 */
972 uint32_t extend_aux_rd_interval:1; /* bit 2 */
973 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
974 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
975 uint32_t disable_usb4_pm_support:1; /* bit 5 */
976 uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */
977 uint32_t reserved:25;
978 } bits;
979 uint32_t raw;
980 };
981
982 /* AUX wake work around options
983 * 0: enable/disable work around
984 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
985 * 15-2: reserved
986 * 31-16: timeout in ms
987 */
988 union aux_wake_wa_options {
989 struct {
990 uint32_t enable_wa : 1;
991 uint32_t use_default_timeout : 1;
992 uint32_t rsvd: 14;
993 uint32_t timeout_ms : 16;
994 } bits;
995 uint32_t raw;
996 };
997
998 struct dc_debug_data {
999 uint32_t ltFailCount;
1000 uint32_t i2cErrorCount;
1001 uint32_t auxErrorCount;
1002 struct pipe_topology_history topology_history;
1003 };
1004
1005 struct dc_phy_addr_space_config {
1006 struct {
1007 uint64_t start_addr;
1008 uint64_t end_addr;
1009 uint64_t fb_top;
1010 uint64_t fb_offset;
1011 uint64_t fb_base;
1012 uint64_t agp_top;
1013 uint64_t agp_bot;
1014 uint64_t agp_base;
1015 } system_aperture;
1016
1017 struct {
1018 uint64_t page_table_start_addr;
1019 uint64_t page_table_end_addr;
1020 uint64_t page_table_base_addr;
1021 bool base_addr_is_mc_addr;
1022 } gart_config;
1023
1024 bool valid;
1025 bool is_hvm_enabled;
1026 uint64_t page_table_default_page_addr;
1027 };
1028
1029 struct dc_virtual_addr_space_config {
1030 uint64_t page_table_base_addr;
1031 uint64_t page_table_start_addr;
1032 uint64_t page_table_end_addr;
1033 uint32_t page_table_block_size_in_bytes;
1034 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
1035 };
1036
1037 struct dc_bounding_box_overrides {
1038 unsigned int sr_exit_time_ns;
1039 unsigned int sr_enter_plus_exit_time_ns;
1040 unsigned int sr_exit_z8_time_ns;
1041 unsigned int sr_enter_plus_exit_z8_time_ns;
1042 unsigned int urgent_latency_ns;
1043 unsigned int percent_of_ideal_drambw;
1044 unsigned int dram_clock_change_latency_ns;
1045 unsigned int dummy_clock_change_latency_ns;
1046 unsigned int fclk_clock_change_latency_ns;
1047 /* This forces a hard min on the DCFCLK we use
1048 * for DML. Unlike the debug option for forcing
1049 * DCFCLK, this override affects watermark calculations
1050 */
1051 unsigned int min_dcfclk_mhz;
1052 };
1053
1054 struct dc_qos_info {
1055 uint32_t qos_bandwidth_lb_in_mbps;
1056 uint32_t calculated_avg_bw_in_mbps;
1057 uint32_t qos_max_latency_ub_in_ns;
1058 uint32_t qos_avg_latency_ub_in_ns;
1059 uint32_t dcn_bandwidth_ub_in_mbps;
1060 uint32_t qos_max_bw_budget_in_mbps;
1061 };
1062
1063 struct dc_state;
1064 struct resource_pool;
1065 struct dce_hwseq;
1066 struct link_service;
1067
1068 /*
1069 * struct dc_debug_options - DC debug struct
1070 *
1071 * This struct provides a simple mechanism for developers to change some
1072 * configurations, enable/disable features, and activate extra debug options.
1073 * This can be very handy to narrow down whether some specific feature is
1074 * causing an issue or not.
1075 */
1076 struct dc_debug_options {
1077 bool disable_dsc;
1078 enum visual_confirm visual_confirm;
1079 unsigned int visual_confirm_rect_height;
1080
1081 bool sanity_checks;
1082 bool max_disp_clk;
1083 bool surface_trace;
1084 bool clock_trace;
1085 bool validation_trace;
1086 bool bandwidth_calcs_trace;
1087 int max_downscale_src_width;
1088
1089 /* stutter efficiency related */
1090 bool disable_stutter;
1091 bool use_max_lb;
1092 enum dcc_option disable_dcc;
1093
1094 /*
1095 * @pipe_split_policy: Define which pipe split policy is used by the
1096 * display core.
1097 */
1098 enum pipe_split_policy pipe_split_policy;
1099 bool force_single_disp_pipe_split;
1100 bool voltage_align_fclk;
1101 bool disable_min_fclk;
1102
1103 bool hdcp_lc_force_fw_enable;
1104 bool hdcp_lc_enable_sw_fallback;
1105
1106 bool disable_dfs_bypass;
1107 bool disable_dpp_power_gate;
1108 bool disable_hubp_power_gate;
1109 bool disable_dsc_power_gate;
1110 bool disable_optc_power_gate;
1111 bool disable_hpo_power_gate;
1112 bool disable_io_clk_power_gate;
1113 bool disable_mem_power_gate;
1114 bool disable_dio_power_gate;
1115 unsigned int dsc_min_slice_height_override;
1116 unsigned int dsc_bpp_increment_div;
1117 bool disable_pplib_wm_range;
1118 enum wm_report_mode pplib_wm_report_mode;
1119 unsigned int min_disp_clk_khz;
1120 unsigned int min_dpp_clk_khz;
1121 unsigned int min_dram_clk_khz;
1122 unsigned int sr_exit_time_dpm0_ns;
1123 unsigned int sr_enter_plus_exit_time_dpm0_ns;
1124 unsigned int sr_exit_time_ns;
1125 unsigned int sr_enter_plus_exit_time_ns;
1126 unsigned int sr_exit_z8_time_ns;
1127 unsigned int sr_enter_plus_exit_z8_time_ns;
1128 unsigned int urgent_latency_ns;
1129 uint32_t underflow_assert_delay_us;
1130 unsigned int percent_of_ideal_drambw;
1131 unsigned int dram_clock_change_latency_ns;
1132 bool optimized_watermark;
1133 int always_scale;
1134 bool disable_pplib_clock_request;
1135 bool disable_clock_gate;
1136 bool disable_mem_low_power;
1137 bool pstate_enabled;
1138 bool disable_dmcu;
1139 bool force_abm_enable;
1140 bool disable_stereo_support;
1141 bool vsr_support;
1142 bool performance_trace;
1143 bool az_endpoint_mute_only;
1144 bool always_use_regamma;
1145 bool recovery_enabled;
1146 bool avoid_vbios_exec_table;
1147 bool scl_reset_length10;
1148 bool hdmi20_disable;
1149 bool skip_detection_link_training;
1150 uint32_t edid_read_retry_times;
1151
1152 uint8_t force_odm_combine; //bit vector based on otg inst
1153 uint8_t seamless_boot_odm_combine;
1154 uint8_t force_odm_combine_4to1; //bit vector based on otg inst
1155
1156 unsigned int minimum_z8_residency_time;
1157 unsigned int minimum_z10_residency_time;
1158 bool disable_z9_mpc;
1159 unsigned int force_fclk_khz;
1160 bool enable_tri_buf;
1161 bool ips_disallow_entry;
1162 bool disable_idle_power_optimizations;
1163 unsigned int mall_size_override;
1164 unsigned int mall_additional_timer_percent;
1165 bool mall_error_as_fatal;
1166 bool dmub_command_table; /* for testing only */
1167 struct dc_bw_validation_profile bw_val_profile;
1168 bool disable_fec;
1169 bool disable_48mhz_pwrdwn;
1170 /* This forces a hard min on the DCFCLK requested to SMU/PP
1171 * watermarks are not affected.
1172 */
1173 unsigned int force_min_dcfclk_mhz;
1174 int dwb_fi_phase;
1175 bool disable_timing_sync;
1176 bool cm_in_bypass;
1177 int force_clock_mode;/*every mode change.*/
1178
1179 bool disable_dram_clock_change_vactive_support;
1180 bool validate_dml_output;
1181 bool enable_dmcub_surface_flip;
1182 bool usbc_combo_phy_reset_wa;
1183 bool force_fva;
1184 int max_frl_rate;
1185 unsigned int force_frl_rate;
1186 bool ignore_ffe;
1187 unsigned int select_ffe;
1188 unsigned int limit_ffe;
1189 bool force_frl_always;
1190 bool force_frl_dsc;
1191 bool force_frl_max;
1192 bool apply_vsdb_rcc_wa;
1193 bool enable_hdmi_idcc;
1194
1195 bool enable_dram_clock_change_one_display_vactive;
1196 /* TODO - remove once tested */
1197 bool legacy_dp2_lt;
1198 bool set_mst_en_for_sst;
1199 bool disable_uhbr;
1200 bool force_dp2_lt_fallback_method;
1201 bool ignore_cable_id;
1202 union mem_low_power_enable_options enable_mem_low_power;
1203 union root_clock_optimization_options root_clock_optimization;
1204 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating;
1205 bool hpo_optimization;
1206 bool force_vblank_alignment;
1207
1208 /* Enable dmub aux for legacy ddc */
1209 bool enable_dmub_aux_for_legacy_ddc;
1210 bool disable_fams;
1211 enum in_game_fams_config disable_fams_gaming;
1212 /* FEC/PSR1 sequence enable delay in 100us */
1213 uint8_t fec_enable_delay_in100us;
1214 bool enable_driver_sequence_debug;
1215 enum det_size crb_alloc_policy;
1216 unsigned int crb_alloc_policy_min_disp_count;
1217 bool disable_z10;
1218 bool enable_z9_disable_interface;
1219 bool psr_skip_crtc_disable;
1220 uint32_t ips_skip_crtc_disable_mask;
1221 union dpia_debug_options dpia_debug;
1222 bool disable_fixed_vs_aux_timeout_wa;
1223 uint32_t fixed_vs_aux_delay_config_wa;
1224 bool force_disable_subvp;
1225 bool force_subvp_mclk_switch;
1226 bool allow_sw_cursor_fallback;
1227 unsigned int force_subvp_num_ways;
1228 unsigned int force_mall_ss_num_ways;
1229 bool alloc_extra_way_for_cursor;
1230 uint32_t subvp_extra_lines;
1231 bool disable_force_pstate_allow_on_hw_release;
1232 bool force_usr_allow;
1233 /* uses value at boot and disables switch */
1234 bool disable_dtb_ref_clk_switch;
1235 bool extended_blank_optimization;
1236 union aux_wake_wa_options aux_wake_wa;
1237 uint32_t mst_start_top_delay;
1238 uint8_t psr_power_use_phy_fsm;
1239 enum dml_hostvm_override_opts dml_hostvm_override;
1240 bool dml_disallow_alternate_prefetch_modes;
1241 bool use_legacy_soc_bb_mechanism;
1242 bool exit_idle_opt_for_cursor_updates;
1243 bool using_dml2;
1244 bool enable_single_display_2to1_odm_policy;
1245 bool enable_double_buffered_dsc_pg_support;
1246 bool enable_dp_dig_pixel_rate_div_policy;
1247 bool using_dml21;
1248 enum lttpr_mode lttpr_mode_override;
1249 unsigned int dsc_delay_factor_wa_x1000;
1250 unsigned int min_prefetch_in_strobe_ns;
1251 bool disable_unbounded_requesting;
1252 bool dig_fifo_off_in_blank;
1253 bool override_dispclk_programming;
1254 bool otg_crc_db;
1255 bool disallow_dispclk_dppclk_ds;
1256 bool disable_fpo_optimizations;
1257 bool support_eDP1_5;
1258 uint32_t fpo_vactive_margin_us;
1259 bool disable_fpo_vactive;
1260 bool disable_boot_optimizations;
1261 bool override_odm_optimization;
1262 bool minimize_dispclk_using_odm;
1263 bool disable_subvp_high_refresh;
1264 bool disable_dp_plus_plus_wa;
1265 uint32_t fpo_vactive_min_active_margin_us;
1266 uint32_t fpo_vactive_max_blank_us;
1267 bool enable_hpo_pg_support;
1268 bool disable_dc_mode_overwrite;
1269 bool replay_skip_crtc_disabled;
1270 bool ignore_pg;/*do nothing, let pmfw control it*/
1271 bool psp_disabled_wa;
1272 unsigned int ips2_eval_delay_us;
1273 unsigned int ips2_entry_delay_us;
1274 bool optimize_ips_handshake;
1275 bool disable_dmub_reallow_idle;
1276 bool disable_timeout;
1277 bool disable_extblankadj;
1278 bool enable_idle_reg_checks;
1279 unsigned int static_screen_wait_frames;
1280 uint32_t pwm_freq;
1281 bool force_chroma_subsampling_1tap;
1282 unsigned int dcc_meta_propagation_delay_us;
1283 bool disable_422_left_edge_pixel;
1284 bool dml21_force_pstate_method;
1285 uint32_t dml21_force_pstate_method_values[MAX_PIPES];
1286 uint32_t dml21_disable_pstate_method_mask;
1287 union fw_assisted_mclk_switch_version fams_version;
1288 union dmub_fams2_global_feature_config fams2_config;
1289 unsigned int force_cositing;
1290 unsigned int disable_spl;
1291 unsigned int force_easf;
1292 unsigned int force_sharpness;
1293 unsigned int force_sharpness_level;
1294 unsigned int force_lls;
1295 bool notify_dpia_hr_bw;
1296 bool enable_ips_visual_confirm;
1297 unsigned int sharpen_policy;
1298 unsigned int scale_to_sharpness_policy;
1299 unsigned int enable_oled_edp_power_up_opt;
1300 bool enable_hblank_borrow;
1301 bool force_subvp_df_throttle;
1302 uint32_t acpi_transition_bitmasks[MAX_PIPES];
1303 bool enable_pg_cntl_debug_logs;
1304 unsigned int auxless_alpm_lfps_setup_ns;
1305 unsigned int auxless_alpm_lfps_period_ns;
1306 unsigned int auxless_alpm_lfps_silence_ns;
1307 unsigned int auxless_alpm_lfps_t1t2_us;
1308 short auxless_alpm_lfps_t1t2_offset_us;
1309 bool disable_stutter_for_wm_program;
1310 bool enable_block_sequence_programming;
1311 uint32_t custom_psp_footer_size;
1312 bool disable_deferred_minimal_transitions;
1313 unsigned int num_fast_flips_to_steady_state_override;
1314 bool enable_dmu_recovery;
1315 unsigned int force_vmin_threshold;
1316 bool enable_otg_frame_sync_pwa;
1317 unsigned int min_deep_sleep_dcfclk_khz;
1318 unsigned int force_odm2to1_for_edp_pixclk_mhz;
1319 bool enable_replay_esd_recovery;
1320 uint8_t iommu_mismatch_temp_wka;
1321 bool disable_dynamic_expansion_for_test_pattern;
1322 uint32_t dml21_custom_derate_num_dpms;
1323 uint32_t dml21_custom_derate_at_dpm[DML2_MAX_NUM_DPM_LVL];
1324 };
1325
1326
1327 /* Generic structure that can be used to query properties of DC. More fields
1328 * can be added as required.
1329 */
1330 struct dc_current_properties {
1331 unsigned int cursor_size_limit;
1332 };
1333
1334 enum frame_buffer_mode {
1335 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
1336 FRAME_BUFFER_MODE_ZFB_ONLY,
1337 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
1338 } ;
1339
1340 struct dchub_init_data {
1341 int64_t zfb_phys_addr_base;
1342 int64_t zfb_mc_base_addr;
1343 uint64_t zfb_size_in_byte;
1344 enum frame_buffer_mode fb_mode;
1345 bool dchub_initialzied;
1346 bool dchub_info_valid;
1347 };
1348
1349 struct dml2_soc_bb;
1350
1351 struct dc_init_data {
1352 struct hw_asic_id asic_id;
1353 void *driver; /* ctx */
1354 struct cgs_device *cgs_device;
1355 struct dc_bounding_box_overrides bb_overrides;
1356
1357 int num_virtual_links;
1358 /*
1359 * If 'vbios_override' not NULL, it will be called instead
1360 * of the real VBIOS. Intended use is Diagnostics on FPGA.
1361 */
1362 struct dc_bios *vbios_override;
1363 enum dce_environment dce_environment;
1364
1365 struct dmub_offload_funcs *dmub_if;
1366
1367 struct dc_config flags;
1368 uint64_t log_mask;
1369
1370 struct dpcd_vendor_signature vendor_signature;
1371 bool force_smu_not_present;
1372 /*
1373 * IP offset for run time initializaion of register addresses
1374 *
1375 * DCN3.5+ will fail dc_create() if these fields are null for them. They are
1376 * applicable starting with DCN32/321 and are not used for ASICs upstreamed
1377 * before them.
1378 */
1379 uint32_t *dcn_reg_offsets;
1380 uint32_t *nbio_reg_offsets;
1381 uint32_t *clk_reg_offsets;
1382 void *bb_from_dmub;
1383 };
1384
1385 struct dc_callback_init {
1386 struct cp_psp cp_psp;
1387 };
1388
1389 struct dc *dc_create(const struct dc_init_data *init_params);
1390 void dc_hardware_init(struct dc *dc);
1391
1392 int dc_get_vmid_use_vector(struct dc *dc);
1393 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1394 /* Returns the number of vmids supported */
1395 unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1396 void dc_init_callbacks(struct dc *dc,
1397 const struct dc_callback_init *init_params);
1398 void dc_deinit_callbacks(struct dc *dc);
1399 void dc_destroy(struct dc **dc);
1400
1401 /* Surface Interfaces */
1402
1403 enum {
1404 TRANSFER_FUNC_POINTS = 1025
1405 };
1406
1407 struct dc_hdr_static_metadata {
1408 /* display chromaticities and white point in units of 0.00001 */
1409 unsigned int chromaticity_green_x;
1410 unsigned int chromaticity_green_y;
1411 unsigned int chromaticity_blue_x;
1412 unsigned int chromaticity_blue_y;
1413 unsigned int chromaticity_red_x;
1414 unsigned int chromaticity_red_y;
1415 unsigned int chromaticity_white_point_x;
1416 unsigned int chromaticity_white_point_y;
1417
1418 uint32_t min_luminance;
1419 uint32_t max_luminance;
1420 uint32_t maximum_content_light_level;
1421 uint32_t maximum_frame_average_light_level;
1422 };
1423
1424 enum dc_transfer_func_type {
1425 TF_TYPE_PREDEFINED,
1426 TF_TYPE_DISTRIBUTED_POINTS,
1427 TF_TYPE_BYPASS,
1428 TF_TYPE_HWPWL
1429 };
1430
1431 struct dc_transfer_func_distributed_points {
1432 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
1433 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
1434 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
1435
1436 uint16_t end_exponent;
1437 uint16_t x_point_at_y1_red;
1438 uint16_t x_point_at_y1_green;
1439 uint16_t x_point_at_y1_blue;
1440 };
1441
1442 enum dc_transfer_func_predefined {
1443 TRANSFER_FUNCTION_SRGB,
1444 TRANSFER_FUNCTION_BT709,
1445 TRANSFER_FUNCTION_PQ,
1446 TRANSFER_FUNCTION_LINEAR,
1447 TRANSFER_FUNCTION_UNITY,
1448 TRANSFER_FUNCTION_HLG,
1449 TRANSFER_FUNCTION_HLG12,
1450 TRANSFER_FUNCTION_GAMMA22,
1451 TRANSFER_FUNCTION_GAMMA24,
1452 TRANSFER_FUNCTION_GAMMA26
1453 };
1454
1455
1456 struct dc_transfer_func {
1457 struct kref refcount;
1458 enum dc_transfer_func_type type;
1459 enum dc_transfer_func_predefined tf;
1460 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
1461 uint32_t sdr_ref_white_level;
1462 struct fixed31_32 hdr_multiplier;
1463 union {
1464 struct pwl_params pwl;
1465 struct dc_transfer_func_distributed_points tf_pts;
1466 };
1467 };
1468
1469
1470 union dc_3dlut_state {
1471 struct {
1472 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
1473 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
1474 uint32_t rmu_mux_num:3; /*index of mux to use*/
1475 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1476 uint32_t mpc_rmu1_mux:4;
1477 uint32_t mpc_rmu2_mux:4;
1478 uint32_t reserved:15;
1479 } bits;
1480 uint32_t raw;
1481 };
1482
1483
1484 #define MATRIX_9C__DIM_128_ALIGNED_LEN 16 // 9+8 : 9 * 8 + 7 * 8 = 72 + 56 = 128 % 128 = 0
1485 #define MATRIX_17C__DIM_128_ALIGNED_LEN 32 //17+15: 17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0
1486 #define MATRIX_33C__DIM_128_ALIGNED_LEN 64 //17+47: 17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0
1487
1488 struct lut_rgb {
1489 uint16_t b;
1490 uint16_t g;
1491 uint16_t r;
1492 uint16_t padding;
1493 };
1494
1495 //this structure maps directly to how the lut will read it from memory
1496 struct lut_mem_mapping {
1497 union {
1498 //NATIVE MODE 1, 2
1499 //RGB layout [b][g][r] //red is 128 byte aligned
1500 //BGR layout [r][g][b] //blue is 128 byte aligned
1501 struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN];
1502 struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN];
1503
1504 //TRANSFORMED
1505 uint16_t linear_rgb[(33*33*33*4/128+1)*128];
1506 };
1507 uint16_t size;
1508 };
1509
1510 struct dc_rmcm_3dlut {
1511 bool isInUse;
1512 const struct dc_stream_state *stream;
1513 };
1514
1515 struct dc_3dlut {
1516 struct kref refcount;
1517 struct tetrahedral_params lut_3d;
1518 union dc_3dlut_state state;
1519 };
1520
1521 /* 3DLUT DMA (Fast Load) params */
1522 struct dc_3dlut_dma {
1523 struct dc_plane_address addr;
1524 enum dc_cm_lut_swizzle swizzle;
1525 enum dc_cm_lut_pixel_format format;
1526 uint16_t bias; /* FP1.5.10 */
1527 uint16_t scale; /* FP1.5.10 */
1528 enum dc_cm_lut_size size;
1529 };
1530
1531 /* color manager */
1532 union dc_plane_cm_flags {
1533 unsigned int all;
1534 struct {
1535 unsigned int shaper_enable : 1;
1536 unsigned int lut3d_enable : 1;
1537 unsigned int blend_enable : 1;
1538 /* whether legacy (lut3d_func) or DMA is valid */
1539 unsigned int lut3d_dma_enable : 1;
1540 /* RMCM lut to be used instead of MCM */
1541 unsigned int rmcm_enable : 1;
1542 unsigned int reserved: 27;
1543 } bits;
1544 };
1545
1546 struct dc_plane_cm {
1547 struct kref refcount;
1548 struct dc_transfer_func shaper_func;
1549 union {
1550 struct dc_3dlut lut3d_func;
1551 struct dc_3dlut_dma lut3d_dma;
1552 };
1553 struct dc_transfer_func blend_func;
1554 union dc_plane_cm_flags flags;
1555 };
1556
1557 /*
1558 * This structure is filled in by dc_surface_get_status and contains
1559 * the last requested address and the currently active address so the called
1560 * can determine if there are any outstanding flips
1561 */
1562 struct dc_plane_status {
1563 struct dc_plane_address requested_address;
1564 struct dc_plane_address current_address;
1565 bool is_flip_pending;
1566 bool is_right_eye;
1567 struct cm_hist cm_hist;
1568 };
1569
1570 struct pipe_update_bits {
1571 uint32_t addr_update:1;
1572 uint32_t dcc_change:1;
1573 uint32_t color_space_change:1;
1574 uint32_t horizontal_mirror_change:1;
1575 uint32_t per_pixel_alpha_change:1;
1576 uint32_t global_alpha_change:1;
1577 uint32_t hdr_mult:1;
1578 uint32_t rotation_change:1;
1579 uint32_t swizzle_change:1;
1580 uint32_t scaling_change:1;
1581 uint32_t position_change:1;
1582 uint32_t in_transfer_func_change:1;
1583 uint32_t input_csc_change:1;
1584 uint32_t coeff_reduction_change:1;
1585 uint32_t pixel_format_change:1;
1586 uint32_t plane_size_change:1;
1587 uint32_t gamut_remap_change:1;
1588 uint32_t cursor_csc_color_matrix_change:1;
1589 uint32_t new_plane:1;
1590 uint32_t bpp_change:1;
1591 uint32_t gamma_change:1;
1592 uint32_t bandwidth_change:1;
1593 uint32_t clock_change:1;
1594 uint32_t stereo_format_change:1;
1595 uint32_t lut_3d:1;
1596 uint32_t tmz_changed:1;
1597 uint32_t full_update:1;
1598 uint32_t sdr_white_level_nits:1;
1599 uint32_t cm_hist_change:1;
1600 /* NOTE: When adding a new field, also update:
1601 * - dc_pipe_update_bits_set_full()
1602 * - dc_pipe_update_bits_is_any_set()
1603 */
1604 };
1605
dc_pipe_update_bits_clear(struct pipe_update_bits * flags)1606 static inline void dc_pipe_update_bits_clear(struct pipe_update_bits *flags)
1607 {
1608 /* memset ensures padding bits are zeroed */
1609 memset(flags, 0, sizeof(*flags));
1610 }
1611
dc_pipe_update_bits_set_full(struct pipe_update_bits * flags)1612 static inline void dc_pipe_update_bits_set_full(struct pipe_update_bits *flags)
1613 {
1614 dc_pipe_update_bits_clear(flags);
1615 flags->addr_update = 1;
1616 flags->dcc_change = 1;
1617 flags->color_space_change = 1;
1618 flags->horizontal_mirror_change = 1;
1619 flags->per_pixel_alpha_change = 1;
1620 flags->global_alpha_change = 1;
1621 flags->hdr_mult = 1;
1622 flags->rotation_change = 1;
1623 flags->swizzle_change = 1;
1624 flags->scaling_change = 1;
1625 flags->position_change = 1;
1626 flags->in_transfer_func_change = 1;
1627 flags->input_csc_change = 1;
1628 flags->coeff_reduction_change = 1;
1629 flags->pixel_format_change = 1;
1630 flags->plane_size_change = 1;
1631 flags->gamut_remap_change = 1;
1632 flags->cursor_csc_color_matrix_change = 1;
1633 flags->new_plane = 1;
1634 flags->bpp_change = 1;
1635 flags->gamma_change = 1;
1636 flags->bandwidth_change = 1;
1637 flags->clock_change = 1;
1638 flags->stereo_format_change = 1;
1639 flags->lut_3d = 1;
1640 flags->tmz_changed = 1;
1641 flags->full_update = 1;
1642 flags->sdr_white_level_nits = 1;
1643 flags->cm_hist_change = 1;
1644 }
1645
dc_pipe_update_bits_is_any_set(const struct pipe_update_bits * flags)1646 static inline bool dc_pipe_update_bits_is_any_set(const struct pipe_update_bits *flags)
1647 {
1648 return flags->addr_update ||
1649 flags->dcc_change ||
1650 flags->color_space_change ||
1651 flags->horizontal_mirror_change ||
1652 flags->per_pixel_alpha_change ||
1653 flags->global_alpha_change ||
1654 flags->hdr_mult ||
1655 flags->rotation_change ||
1656 flags->swizzle_change ||
1657 flags->scaling_change ||
1658 flags->position_change ||
1659 flags->in_transfer_func_change ||
1660 flags->input_csc_change ||
1661 flags->coeff_reduction_change ||
1662 flags->pixel_format_change ||
1663 flags->plane_size_change ||
1664 flags->gamut_remap_change ||
1665 flags->cursor_csc_color_matrix_change ||
1666 flags->new_plane ||
1667 flags->bpp_change ||
1668 flags->gamma_change ||
1669 flags->bandwidth_change ||
1670 flags->clock_change ||
1671 flags->stereo_format_change ||
1672 flags->lut_3d ||
1673 flags->tmz_changed ||
1674 flags->full_update ||
1675 flags->sdr_white_level_nits ||
1676 flags->cm_hist_change;
1677 }
1678
1679 bool dc_check_address_only_update(struct pipe_update_bits update_bits);
1680
1681 #define DC_REMOVE_PLANE_POINTERS 1
1682
1683 struct dc_plane_state {
1684 struct dc_plane_address address;
1685 struct dc_plane_flip_time time;
1686 bool triplebuffer_flips;
1687 struct scaling_taps scaling_quality;
1688 struct rect src_rect;
1689 struct rect dst_rect;
1690 struct rect clip_rect;
1691
1692 struct plane_size plane_size;
1693 struct dc_tiling_info tiling_info;
1694
1695 struct dc_plane_dcc_param dcc;
1696
1697 struct dc_gamma gamma_correction;
1698 struct dc_transfer_func in_transfer_func;
1699 struct dc_bias_and_scale bias_and_scale;
1700 struct dc_csc_transform input_csc_color_matrix;
1701 struct fixed31_32 coeff_reduction_factor;
1702 struct fixed31_32 hdr_mult;
1703 struct colorspace_transform gamut_remap_matrix;
1704
1705 enum dc_color_space color_space;
1706
1707 #ifndef TRIM_CM2
1708 bool lut_bank_a;
1709 struct dc_hdr_static_metadata hdr_static_ctx;
1710 struct dc_3dlut lut3d_func;
1711 struct dc_transfer_func in_shaper_func;
1712 struct dc_transfer_func blend_tf;
1713 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting;
1714 bool mcm_lut1d_enable;
1715 struct dc_cm2_func_luts mcm_luts;
1716 enum mpcc_movable_cm_location mcm_location;
1717 #endif /* TRIM_CM2 */
1718 struct dc_plane_cm cm;
1719
1720 struct dc_transfer_func *gamcor_tf;
1721 enum surface_pixel_format format;
1722 enum dc_rotation_angle rotation;
1723 enum plane_stereo_format stereo_format;
1724
1725 bool is_tiling_rotated;
1726 bool per_pixel_alpha;
1727 bool pre_multiplied_alpha;
1728 bool global_alpha;
1729 int global_alpha_value;
1730 bool visible;
1731 bool flip_immediate;
1732 bool horizontal_mirror;
1733 unsigned int layer_index;
1734
1735 struct pipe_update_bits update_bits;
1736 bool flip_int_enabled;
1737 bool skip_manual_trigger;
1738
1739 /* private to DC core */
1740 struct dc_plane_status status;
1741 struct dc_context *ctx;
1742
1743 /* HACK: Workaround for forcing full reprogramming under some conditions */
1744 bool force_full_update;
1745
1746 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1747
1748 /* private to dc_surface.c */
1749 enum dc_irq_source irq_source;
1750 struct kref refcount;
1751 struct tg_color visual_confirm_color;
1752
1753 bool is_statically_allocated;
1754 enum chroma_cositing cositing;
1755 struct dc_csc_transform cursor_csc_color_matrix;
1756 bool adaptive_sharpness_en;
1757 int adaptive_sharpness_policy;
1758 unsigned int sharpness_level;
1759 enum dc_scaling_linearity scaling_linearity;
1760 unsigned int sdr_white_level_nits;
1761 struct cm_hist_control cm_hist_control;
1762 struct spl_sharpness_range sharpness_range;
1763 enum sharpness_range_source sharpness_source;
1764 };
1765
1766 struct dc_plane_info {
1767 struct plane_size plane_size;
1768 struct dc_tiling_info tiling_info;
1769 struct dc_plane_dcc_param dcc;
1770 enum surface_pixel_format format;
1771 enum dc_rotation_angle rotation;
1772 enum plane_stereo_format stereo_format;
1773 enum dc_color_space color_space;
1774 bool horizontal_mirror;
1775 bool visible;
1776 bool per_pixel_alpha;
1777 bool pre_multiplied_alpha;
1778 bool global_alpha;
1779 int global_alpha_value;
1780 bool input_csc_enabled;
1781 unsigned int layer_index;
1782 enum chroma_cositing cositing;
1783 enum dc_scaling_linearity scaling_linearity;
1784 };
1785
1786 #include "dc_stream.h"
1787
1788 struct dc_scratch_space {
1789 /* used to temporarily backup plane states of a stream during
1790 * dc update. The reason is that plane states are overwritten
1791 * with surface updates in dc update. Once they are overwritten
1792 * current state is no longer valid. We want to temporarily
1793 * store current value in plane states so we can still recover
1794 * a valid current state during dc update.
1795 */
1796 struct dc_plane_state plane_states[MAX_SURFACES];
1797
1798 struct dc_stream_state stream_state;
1799 };
1800
1801 /*
1802 * A link contains one or more sinks and their connected status.
1803 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1804 */
1805 struct dc_link {
1806 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
1807 unsigned int sink_count;
1808 struct dc_sink *local_sink;
1809 unsigned int link_index;
1810 enum dc_connection_type type;
1811 enum signal_type connector_signal;
1812 enum dc_irq_source irq_source_hpd;
1813 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */
1814 enum dc_irq_source irq_source_read_request;/* Read Request */
1815
1816 bool is_hpd_filter_disabled;
1817 bool dp_ss_off;
1818
1819 /**
1820 * @link_state_valid:
1821 *
1822 * If there is no link and local sink, this variable should be set to
1823 * false. Otherwise, it should be set to true; usually, the function
1824 * core_link_enable_stream sets this field to true.
1825 */
1826 bool link_state_valid;
1827 bool aux_access_disabled;
1828 bool sync_lt_in_progress;
1829 bool skip_stream_reenable;
1830 bool is_internal_display;
1831 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */
1832 bool is_dig_mapping_flexible;
1833 bool hpd_status; /* HPD status of link without physical HPD pin. */
1834 bool is_hpd_pending; /* Indicates a new received hpd */
1835
1836 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method
1837 * for every link training. This is incompatible with DP LL compliance automation,
1838 * which expects the same link settings to be used every retry on a link loss.
1839 * This flag is used to skip the fallback when link loss occurs during automation.
1840 */
1841 bool skip_fallback_on_link_loss;
1842
1843 bool edp_sink_present;
1844
1845 struct dp_trace dp_trace;
1846 volatile bool is_link_locked;
1847
1848 /* caps is the same as reported_link_cap. link_traing use
1849 * reported_link_cap. Will clean up. TODO
1850 */
1851 struct dc_link_settings reported_link_cap;
1852 struct dc_link_settings verified_link_cap;
1853 struct dc_link_settings cur_link_settings;
1854 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
1855 struct dc_link_settings preferred_link_setting;
1856 /* preferred_training_settings are override values that
1857 * come from DM. DM is responsible for the memory
1858 * management of the override pointers.
1859 */
1860 struct dc_link_training_overrides preferred_training_settings;
1861 struct dc_hdmi_frl_link_training_overrides preferred_hdmi_frl_settings;
1862 struct dp_audio_test_data audio_test_data;
1863
1864 /* On ASICs with dp_connector_no_native_i2c cap set and no_ddc_pin cap
1865 * set by IFWI, link aux_hw_inst is used in aux layer functions instead
1866 * of ddc_pin to know which aux instance is associated with link.
1867 */
1868 bool no_ddc_pin;
1869 /** When set, forces all native I2C communication on this DP connector
1870 * to use the I2C-over-AUX protocol instead of native I2C signaling.
1871 */
1872 bool force_to_use_aux;
1873 enum gpio_ddc_line aux_hw_inst;
1874
1875 enum gpio_ddc_line ddc_hw_inst;
1876
1877 uint8_t hpd_src;
1878
1879 uint8_t link_enc_hw_inst;
1880 /* DIG link encoder ID. Used as index in link encoder resource pool.
1881 * For links with fixed mapping to DIG, this is not changed after dc_link
1882 * object creation.
1883 */
1884 enum engine_id eng_id;
1885 enum engine_id dpia_preferred_eng_id;
1886
1887 bool test_pattern_enabled;
1888 /* Pending/Current test pattern are only used to perform and track
1889 * FIXED_VS retimer test pattern/lane adjustment override state.
1890 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern,
1891 * to perform specific lane adjust overrides before setting certain
1892 * PHY test patterns. In cases when lane adjust and set test pattern
1893 * calls are not performed atomically (i.e. performing link training),
1894 * pending_test_pattern will be invalid or contain a non-PHY test pattern
1895 * and current_test_pattern will contain required context for any future
1896 * set pattern/set lane adjust to transition between override state(s).
1897 * */
1898 enum dp_test_pattern current_test_pattern;
1899 enum dp_test_pattern pending_test_pattern;
1900
1901 union compliance_test_state compliance_test_state;
1902
1903 void *priv;
1904
1905 struct ddc_service *ddc;
1906
1907 enum dp_panel_mode panel_mode;
1908 bool panel_mode_initialized;
1909 bool aux_mode;
1910
1911 /* Private to DC core */
1912
1913 const struct dc *dc;
1914
1915 struct dc_context *ctx;
1916
1917 struct panel_cntl *panel_cntl;
1918 struct link_encoder *link_enc;
1919 struct hpo_frl_link_encoder *hpo_frl_link_enc;
1920 struct dc_hdmi_frl_link_settings frl_reported_link_cap;
1921 struct dc_hdmi_frl_link_settings frl_verified_link_cap;
1922 struct dc_hdmi_frl_link_settings frl_link_settings;
1923 struct dc_hdmi_frl_flags frl_flags;
1924 union hdmi_idcc_cable_id hdmi_cable_id;
1925 struct graphics_object_id link_id;
1926
1927 /* External encoder eg. NUTMEG or TRAVIS used on CIK APUs. */
1928 struct graphics_object_id ext_enc_id;
1929
1930 /* Endpoint type distinguishes display endpoints which do not have entries
1931 * in the BIOS connector table from those that do. Helps when tracking link
1932 * encoder to display endpoint assignments.
1933 */
1934 enum display_endpoint_type ep_type;
1935 union ddi_channel_mapping ddi_channel_mapping;
1936 struct connector_device_tag_info device_tag;
1937 struct dpcd_caps dpcd_caps;
1938 uint32_t dongle_max_pix_clk;
1939 unsigned short chip_caps;
1940 unsigned int dpcd_sink_count;
1941 struct hdcp_caps hdcp_caps;
1942 enum edp_revision edp_revision;
1943 union dpcd_sink_ext_caps dpcd_sink_ext_caps;
1944
1945 struct psr_settings psr_settings;
1946 struct replay_settings replay_settings;
1947
1948 /* Drive settings read from integrated info table */
1949 struct dc_lane_settings bios_forced_drive_settings;
1950
1951 /* Vendor specific LTTPR workaround variables */
1952 uint8_t vendor_specific_lttpr_link_rate_wa;
1953 bool apply_vendor_specific_lttpr_link_rate_wa;
1954
1955 /* MST record stream using this link */
1956 struct link_flags {
1957 bool dp_keep_receiver_powered;
1958 bool dp_skip_DID2;
1959 bool dp_skip_reset_segment;
1960 bool dp_skip_fs_144hz;
1961 /* Some DP bridges don't work with RBR and must use HBR. */
1962 bool dp_skip_rbr;
1963 bool dp_mot_reset_segment;
1964 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */
1965 bool dpia_mst_dsc_always_on;
1966 /* Forced DPIA into TBT3 compatibility mode. */
1967 bool dpia_forced_tbt3_mode;
1968 bool dongle_mode_timing_override;
1969 bool blank_stream_on_ocs_change;
1970 bool read_dpcd204h_on_irq_hpd;
1971 bool force_dp_ffe_preset;
1972 bool skip_phy_ssc_reduction;
1973 } wa_flags;
1974 union dc_dp_ffe_preset forced_dp_ffe_preset;
1975 struct link_mst_stream_allocation_table mst_stream_alloc_table;
1976
1977 struct dc_link_status link_status;
1978 struct dprx_states dprx_states;
1979
1980 enum dc_link_fec_state fec_state;
1981 bool is_dds;
1982 bool is_display_mux_present;
1983 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly
1984
1985 struct dc_panel_config panel_config;
1986 enum dc_panel_type panel_type;
1987 struct phy_state phy_state;
1988 uint32_t phy_transition_bitmask;
1989 // BW ALLOCATON USB4 ONLY
1990 struct dc_dpia_bw_alloc dpia_bw_alloc_config;
1991 bool skip_implict_edp_power_control;
1992 bool forced_psr_active;
1993 enum backlight_control_type backlight_control_type;
1994 };
1995
1996 struct dc {
1997 struct dc_debug_options debug;
1998 struct dc_versions versions;
1999 struct dc_caps caps;
2000 struct dc_check_config check_config;
2001 struct dc_cap_funcs cap_funcs;
2002 struct dc_config config;
2003 struct dc_bounding_box_overrides bb_overrides;
2004 struct dc_bug_wa work_arounds;
2005 struct dc_context *ctx;
2006 struct dc_phy_addr_space_config vm_pa_config;
2007
2008 uint8_t link_count;
2009 struct dc_link *links[MAX_LINKS];
2010 uint8_t lowest_dpia_link_index;
2011 struct link_service *link_srv;
2012
2013 struct dc_state *current_state;
2014 struct resource_pool *res_pool;
2015
2016 /**
2017 * @update_scratch_pool: Per-commit scratch buffers for dc_update_state.
2018 */
2019 struct dc_update_scratch_space *update_scratch_pool[MAX_STREAMS + 1];
2020 bool update_scratch_in_use[MAX_STREAMS + 1];
2021
2022 struct clk_mgr *clk_mgr;
2023
2024 /* Display Engine Clock levels */
2025 struct dm_pp_clock_levels sclk_lvls;
2026
2027 /* Inputs into BW and WM calculations. */
2028 struct bw_calcs_dceip *bw_dceip;
2029 struct bw_calcs_vbios *bw_vbios;
2030 struct dcn_soc_bounding_box *dcn_soc;
2031 struct dcn_ip_params *dcn_ip;
2032 struct display_mode_lib dml;
2033
2034 /* HW functions */
2035 struct hw_sequencer_funcs hwss;
2036 struct dce_hwseq *hwseq;
2037
2038 /* Require to optimize clocks and bandwidth for added/removed planes */
2039 bool optimized_required;
2040 bool idle_optimizations_allowed;
2041 bool enable_c20_dtm_b0;
2042
2043 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
2044
2045 /* For eDP to know the switching state of SmartMux */
2046 bool is_switch_in_progress_orig;
2047 bool is_switch_in_progress_dest;
2048
2049 /* FBC compressor */
2050 struct compressor *fbc_compressor;
2051
2052 struct dc_debug_data debug_data;
2053 struct dpcd_vendor_signature vendor_signature;
2054
2055 const char *build_id;
2056 struct vm_helper *vm_helper;
2057
2058 uint32_t *dcn_reg_offsets;
2059 uint32_t *nbio_reg_offsets;
2060 uint32_t *clk_reg_offsets;
2061
2062 /* Scratch memory */
2063 struct {
2064 struct {
2065 /*
2066 * For matching clock_limits table in driver with table
2067 * from PMFW.
2068 */
2069 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
2070 } update_bw_bounding_box;
2071 struct dc_scratch_space current_state;
2072 struct dc_scratch_space new_state;
2073 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack
2074 struct dc_link temp_link;
2075 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */
2076 } scratch;
2077
2078 struct dml2_configuration_options dml2_options;
2079 struct dml2_configuration_options dml2_dc_power_options;
2080 enum dc_acpi_cm_power_state power_state;
2081 struct soc_and_ip_translator *soc_and_ip_translator;
2082 };
2083
2084 struct dc_scaling_info {
2085 struct rect src_rect;
2086 struct rect dst_rect;
2087 struct rect clip_rect;
2088 struct scaling_taps scaling_quality;
2089 };
2090
2091 struct dc_fast_update {
2092 const struct dc_flip_addrs *flip_addr;
2093 const struct dc_gamma *gamma;
2094 const struct colorspace_transform *gamut_remap_matrix;
2095 const struct dc_csc_transform *input_csc_color_matrix;
2096 const struct fixed31_32 *coeff_reduction_factor;
2097 struct dc_transfer_func *out_transfer_func;
2098 struct dc_csc_transform *output_csc_transform;
2099 const struct dc_csc_transform *cursor_csc_color_matrix;
2100 struct cm_hist_control *cm_hist_control;
2101 /* stream-level fast updates */
2102 const struct colorspace_transform *gamut_remap;
2103 const struct dc_cursor_attributes *cursor_attributes;
2104 const struct dc_cursor_position *cursor_position;
2105 const struct periodic_interrupt_config *periodic_interrupt;
2106 const enum dc_dither_option *dither_option;
2107 struct dc_info_packet *vrr_infopacket;
2108 struct dc_info_packet *vsc_infopacket;
2109 struct dc_info_packet *vsp_infopacket;
2110 struct dc_info_packet *hfvsif_infopacket;
2111 struct dc_info_packet *vtem_infopacket;
2112 struct dc_info_packet *adaptive_sync_infopacket;
2113 struct dc_info_packet *avi_infopacket;
2114 struct dc_info_packet *hdr_static_metadata;
2115 };
2116
2117 struct dc_surface_update {
2118 struct dc_plane_state *surface;
2119
2120 /* isr safe update parameters. null means no updates */
2121 const struct dc_flip_addrs *flip_addr;
2122 const struct dc_plane_info *plane_info;
2123 const struct dc_scaling_info *scaling_info;
2124 struct fixed31_32 hdr_mult;
2125 /* following updates require alloc/sleep/spin that is not isr safe,
2126 * null means no updates
2127 */
2128 const struct dc_gamma *gamma;
2129 const struct dc_transfer_func *in_transfer_func;
2130
2131 const struct dc_csc_transform *input_csc_color_matrix;
2132 const struct fixed31_32 *coeff_reduction_factor;
2133 const struct colorspace_transform *gamut_remap_matrix;
2134 const struct dc_plane_cm *cm;
2135 const struct dc_csc_transform *cursor_csc_color_matrix;
2136 unsigned int sdr_white_level_nits;
2137 struct dc_bias_and_scale bias_and_scale;
2138 struct cm_hist_control *cm_hist_control;
2139 };
2140
2141 struct dc_state_update {
2142 struct dc_stream_state *stream;
2143 struct dc_stream_update *stream_update;
2144 struct dc_surface_update *surface_updates;
2145 int surface_count;
2146 const struct dc_probe_updates *probe_updates;
2147 };
2148
2149 /**
2150 * dc_check_state_update() - Classify an update without committing it.
2151 * @check_config: DC check configuration
2152 * @updates: root update object to classify
2153 *
2154 * Return: descriptor indicating update type and required lock scope.
2155 */
2156 struct dc_update_descriptor dc_check_state_update(
2157 const struct dc_check_config *check_config,
2158 const struct dc_state_update *updates);
2159
2160 /**
2161 * dc_update_state - Commit an absolute dc_state_update.
2162 * @dc: DC structure
2163 * @updates: root update object carrying stream, plane, and probe updates
2164 *
2165 * Return: true on success, false on failure.
2166 */
2167 bool dc_update_state(struct dc *dc, const struct dc_state_update *updates);
2168
2169 struct dc_update_scratch_space;
2170
2171 /**
2172 * dc_update_state_init - Acquire and initialise a commit scratch buffer.
2173 * @dc: DC structure
2174 * @updates: update descriptor; validated before the slot is acquired
2175 *
2176 * Return: a scratch slot on success, NULL if validation fails or the pool
2177 * is exhausted. The slot must be released via dc_update_state_cleanup() on
2178 * success, or automatically by dc_update_state_prepare() on failure.
2179 */
2180 struct dc_update_scratch_space *dc_update_state_init(
2181 struct dc *dc,
2182 const struct dc_state_update *updates
2183 );
2184
2185 /**
2186 * dc_update_state_prepare - Prepare the commit under the global lock.
2187 * @scratch: commit scratch from dc_update_state_init()
2188 *
2189 * On failure the scratch slot is released and false is returned; the caller
2190 * must not call execute or cleanup.
2191 */
2192 bool dc_update_state_prepare(struct dc_update_scratch_space *scratch);
2193
2194 /**
2195 * dc_update_state_execute - Program hardware; called without the global lock.
2196 * @scratch: commit scratch from dc_update_state_init()
2197 */
2198 void dc_update_state_execute(const struct dc_update_scratch_space *scratch);
2199
2200 /**
2201 * dc_update_state_cleanup - Finalise the commit and release the scratch slot.
2202 * @scratch: commit scratch from dc_update_state_init()
2203 *
2204 * Must be called with the global lock held. Returns true if the caller must
2205 * loop back to prepare (SEAMLESS continuation).
2206 */
2207 bool dc_update_state_cleanup(struct dc_update_scratch_space *scratch);
2208
2209 /**
2210 * struct dc_probe_latencies - min/max/avg memory latency in ns.
2211 * @max_latency_ns: maximum latency in nanoseconds
2212 * @avg_latency_ns: average latency in nanoseconds
2213 * @min_latency_ns: minimum latency in nanoseconds
2214 */
2215 struct dc_probe_latencies {
2216 uint32_t max_latency_ns;
2217 uint32_t avg_latency_ns;
2218 uint32_t min_latency_ns;
2219 };
2220
2221 /**
2222 * struct dc_probe_status - results for a probe.
2223 * @valid: true if a measurement was latched.
2224 * @type: type of the probe that produced this result.
2225 * @u.bandwidth_mbps: peak BW in Mbps (DC_PROBE_PEAK_MEM_BW).
2226 * @u.latency: min/max/avg memory latency in ns (DC_PROBE_MEM_LATENCY),
2227 * stored as struct dc_probe_latencies.
2228 * @u.urgent_assertion_count: number of urgent assertion events (DC_PROBE_URGENT_ASSERTION_COUNT).
2229 * @u.prefetch_data_size: total prefetch data in bytes (DC_PROBE_PREFETCH_DATA_SIZE).
2230 */
2231 struct dc_probe_status {
2232 bool valid;
2233 enum dc_probe_type type;
2234 union {
2235 uint32_t bandwidth_mbps;
2236 struct dc_probe_latencies latency;
2237 uint32_t urgent_assertion_count;
2238 uint32_t prefetch_data_size;
2239 } u;
2240 };
2241
2242 /**
2243 * enum dc_get_status_type - Bitmask selecting which status classes to populate.
2244 * @DC_GET_STATUS_STREAM: populate stream_status fields in dc_state_status
2245 * @DC_GET_STATUS_PROBE: populate probe_status fields in dc_state_status
2246 */
2247 enum dc_get_status_type {
2248 DC_GET_STATUS_STREAM = (1u << 0),
2249 DC_GET_STATUS_PROBE = (1u << 1),
2250 };
2251
2252 /**
2253 * struct dc_get_status_options - Input selector for dc_state_get_status.
2254 * @state: source state to read status from
2255 * @types: OR of dc_get_status_type values selecting classes to populate
2256 * @stream: optional stream filter for DC_GET_STATUS_STREAM. NULL means
2257 * populate status for all streams in the state
2258 * @probe: optional probe filter for DC_GET_STATUS_PROBE. NULL means
2259 * populate status for all probes in the state
2260 */
2261 struct dc_get_status_options {
2262 struct dc_state *state;
2263 uint32_t types;
2264 const struct dc_stream_state *stream;
2265 const struct dc_probe_state *probe;
2266 };
2267
2268 /**
2269 * struct dc_state_status - Output-only status object from dc_state_get_status.
2270 * @stream_count: number of valid entries in stream_status (DC_GET_STATUS_STREAM)
2271 * @stream_status: pointers to live per-stream status entries
2272 * @probe_count: number of valid entries in probe_status (DC_GET_STATUS_PROBE)
2273 * @probe_status: pointers to live per-probe status entries
2274 */
2275 struct dc_state_status {
2276 int stream_count;
2277 struct dc_stream_status *stream_status[MAX_STREAMS];
2278 int probe_count;
2279 struct dc_probe_status *probe_status[MAX_PROBES];
2280 };
2281
2282 /**
2283 * dc_state_get_status - Unified status readback for dc_state.
2284 * @status: output object populated according to options->types
2285 * @options: selects the source state, status classes to fill, and filters
2286 *
2287 * Return: DC_OK on success, DC_ERROR_UNEXPECTED if state is NULL.
2288 */
2289 enum dc_status dc_state_get_status(struct dc_state_status *status,
2290 const struct dc_get_status_options *options);
2291
2292 struct dc_underflow_debug_data {
2293 struct dcn_hubbub_reg_state *hubbub_reg_state;
2294 struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES];
2295 struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES];
2296 struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES];
2297 struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES];
2298 struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES];
2299 struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES];
2300 struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES];
2301 };
2302
2303 struct power_features {
2304 bool ips;
2305 bool rcg;
2306 bool replay;
2307 bool dds;
2308 bool sprs;
2309 bool psr;
2310 bool fams;
2311 bool mpo;
2312 bool uclk_p_state;
2313 };
2314
2315 /*
2316 * Create a new surface with default parameters;
2317 */
2318 void dc_gamma_retain(struct dc_gamma *dc_gamma);
2319 void dc_gamma_release(struct dc_gamma **dc_gamma);
2320 struct dc_gamma *dc_create_gamma(void);
2321
2322 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
2323 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
2324 struct dc_transfer_func *dc_create_transfer_func(void);
2325
2326 struct dc_3dlut *dc_create_3dlut_func(void);
2327 void dc_3dlut_func_release(struct dc_3dlut *lut);
2328 void dc_3dlut_func_retain(struct dc_3dlut *lut);
2329
2330 struct dc_plane_cm *dc_plane_cm_create(void);
2331 void dc_plane_cm_release(struct dc_plane_cm *cm);
2332 void dc_plane_cm_retain(struct dc_plane_cm *cm);
2333
2334 void dc_post_update_surfaces_to_stream(
2335 struct dc *dc);
2336
2337 /*
2338 * dc_get_default_tiling_info() - Retrieve an ASIC-appropriate default tiling
2339 * description for (typically) linear surfaces.
2340 *
2341 * This is used by OS/DM paths that need a valid, fully-initialized tiling
2342 * description without hardcoding gfx-version specifics in the caller.
2343 */
2344 void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info);
2345
2346 /**
2347 * struct dc_validation_stream - Per-stream surface/stream association for validation
2348 */
2349 struct dc_validation_stream {
2350 /**
2351 * @stream: Stream state properties
2352 */
2353 struct dc_stream_state *stream;
2354
2355 /**
2356 * @plane_states: Surface state
2357 */
2358 struct dc_plane_state *plane_states[MAX_SURFACES];
2359
2360 /**
2361 * @plane_count: Total of active planes
2362 */
2363 uint8_t plane_count;
2364 };
2365
2366 /**
2367 * struct dc_validation_set - Root validation input grouping all streams for a commit
2368 */
2369 struct dc_validation_set {
2370 /**
2371 * @streams: Per-stream entries (stream + its planes)
2372 */
2373 struct dc_validation_stream streams[MAX_STREAMS];
2374
2375 /**
2376 * @stream_count: Number of active entries in @streams
2377 */
2378 uint8_t stream_count;
2379
2380 /**
2381 * @probes: Global probe descriptors to validate alongside the streams
2382 */
2383 struct dc_probe_state probes[MAX_PROBES];
2384
2385 /**
2386 * @probe_count: Number of active entries in @probes
2387 */
2388 uint8_t probe_count;
2389 };
2390
2391 bool dc_validate_boot_timing(const struct dc *dc,
2392 const struct dc_sink *sink,
2393 struct dc_crtc_timing *crtc_timing);
2394
2395 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
2396
2397 enum dc_status dc_validate_with_context(struct dc *dc,
2398 const struct dc_validation_set *set,
2399 struct dc_state *context,
2400 enum dc_validate_mode validate_mode);
2401
2402 bool dc_set_generic_gpio_for_stereo(bool enable,
2403 struct gpio_service *gpio_service);
2404
2405 enum dc_status dc_validate_global_state(
2406 struct dc *dc,
2407 struct dc_state *new_ctx,
2408 enum dc_validate_mode validate_mode);
2409
2410 bool dc_acquire_release_mpc_3dlut(
2411 struct dc *dc, bool acquire,
2412 struct dc_stream_state *stream,
2413 struct dc_3dlut **lut,
2414 struct dc_transfer_func **shaper);
2415
2416 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
2417 void get_audio_check(struct audio_info *aud_modes,
2418 struct audio_check *aud_chk);
2419
2420 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count);
2421 void populate_fast_updates(struct dc_fast_update *fast_update,
2422 struct dc_surface_update *srf_updates,
2423 int surface_count,
2424 struct dc_stream_update *stream_update);
2425 /*
2426 * Set up streams and links associated to drive sinks
2427 * The streams parameter is an absolute set of all active streams.
2428 *
2429 * After this call:
2430 * Phy, Encoder, Timing Generator are programmed and enabled.
2431 * New streams are enabled with blank stream; no memory read.
2432 */
2433 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);
2434
2435
2436 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
2437 struct dc_stream_state *stream,
2438 int mpcc_inst);
2439
2440
2441 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
2442 bool dc_set_fva_vrr_adjust(struct dc *dc,
2443 struct dc_stream_state *stream,
2444 struct fva_adj *fva_adj,
2445 struct dc_crtc_timing_adjust *vrr_adj);
2446
2447 int dc_get_hw_max_fva_factor(struct dc *dc,
2448 struct dc_stream_state *stream,
2449 unsigned int max_pixel_clock);
2450
2451 void dc_set_vstartup_start(struct dc *dc,
2452 struct dc_stream_state *stream);
2453
2454 void dc_set_disable_128b_132b_stream_overhead(bool disable);
2455
2456 /* The function returns minimum bandwidth required to drive a given timing
2457 * return - minimum required timing bandwidth in kbps.
2458 */
2459 uint32_t dc_bandwidth_in_kbps_from_timing(
2460 const struct dc_crtc_timing *timing,
2461 const enum dc_link_encoding_format link_encoding);
2462
2463 /* Link Interfaces */
2464 /* Return an enumerated dc_link.
2465 * dc_link order is constant and determined at
2466 * boot time. They cannot be created or destroyed.
2467 * Use dc_get_caps() to get number of links.
2468 */
2469 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
2470
2471 /* Return instance id of the edp link. Inst 0 is primary edp link. */
2472 bool dc_get_edp_link_panel_inst(const struct dc *dc,
2473 const struct dc_link *link,
2474 unsigned int *inst_out);
2475
2476 /* Return an array of link pointers to edp links. */
2477 void dc_get_edp_links(const struct dc *dc,
2478 struct dc_link **edp_links,
2479 unsigned int *edp_num);
2480
2481 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
2482 bool powerOn);
2483
2484 /* The function initiates detection handshake over the given link. It first
2485 * determines if there are display connections over the link. If so it initiates
2486 * detection protocols supported by the connected receiver device. The function
2487 * contains protocol specific handshake sequences which are sometimes mandatory
2488 * to establish a proper connection between TX and RX. So it is always
2489 * recommended to call this function as the first link operation upon HPD event
2490 * or power up event. Upon completion, the function will update link structure
2491 * in place based on latest RX capabilities. The function may also cause dpms
2492 * to be reset to off for all currently enabled streams to the link. It is DM's
2493 * responsibility to serialize detection and DPMS updates.
2494 *
2495 * @reason - Indicate which event triggers this detection. dc may customize
2496 * detection flow depending on the triggering events.
2497 * return false - if detection is not fully completed. This could happen when
2498 * there is an unrecoverable error during detection or detection is partially
2499 * completed (detection has been delegated to dm mst manager ie.
2500 * link->connection_type == dc_connection_mst_branch when returning false).
2501 * return true - detection is completed, link has been fully updated with latest
2502 * detection result.
2503 */
2504 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);
2505
2506 struct dc_sink_init_data;
2507
2508 /* When link connection type is dc_connection_mst_branch, remote sink can be
2509 * added to the link. The interface creates a remote sink and associates it with
2510 * current link. The sink will be retained by link until remove remote sink is
2511 * called.
2512 *
2513 * @dc_link - link the remote sink will be added to.
2514 * @edid - byte array of EDID raw data.
2515 * @len - size of the edid in byte
2516 * @init_data -
2517 */
2518 struct dc_sink *dc_link_add_remote_sink(
2519 struct dc_link *dc_link,
2520 const uint8_t *edid,
2521 unsigned int len,
2522 struct dc_sink_init_data *init_data);
2523
2524 /* Remove remote sink from a link with dc_connection_mst_branch connection type.
2525 * @link - link the sink should be removed from
2526 * @sink - sink to be removed.
2527 */
2528 void dc_link_remove_remote_sink(
2529 struct dc_link *link,
2530 struct dc_sink *sink);
2531
2532 /* Enable HPD interrupt handler for a given link */
2533 void dc_link_enable_hpd(const struct dc_link *link);
2534
2535 /* Disable HPD interrupt handler for a given link */
2536 void dc_link_disable_hpd(const struct dc_link *link);
2537
2538 /* determine if there is a sink connected to the link
2539 *
2540 * @type - dc_connection_single if connected, dc_connection_none otherwise.
2541 * return - false if an unexpected error occurs, true otherwise.
2542 *
2543 * NOTE: This function doesn't detect downstream sink connections i.e
2544 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will
2545 * return dc_connection_single if the branch device is connected despite of
2546 * downstream sink's connection status.
2547 */
2548 bool dc_link_detect_connection_type(struct dc_link *link,
2549 enum dc_connection_type *type);
2550
2551 /* query current hpd pin value
2552 * return - true HPD is asserted (HPD high), false otherwise (HPD low)
2553 *
2554 */
2555 bool dc_link_get_hpd_state(struct dc_link *link);
2556
2557 /* Getter for cached link status from given link */
2558 const struct dc_link_status *dc_link_get_status(const struct dc_link *link);
2559
2560 /* enable/disable hardware HPD filter.
2561 *
2562 * @link - The link the HPD pin is associated with.
2563 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
2564 * handler once after no HPD change has been detected within dc default HPD
2565 * filtering interval since last HPD event. i.e if display keeps toggling hpd
2566 * pulses within default HPD interval, no HPD event will be received until HPD
2567 * toggles have stopped. Then HPD event will be queued to irq handler once after
2568 * dc default HPD filtering interval since last HPD event.
2569 *
2570 * @enable = false - disable hardware HPD filter. HPD event will be queued
2571 * immediately to irq handler after no HPD change has been detected within
2572 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms).
2573 */
2574 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
2575
2576 /* submit i2c read/write payloads through ddc channel
2577 * @link_index - index to a link with ddc in i2c mode
2578 * @cmd - i2c command structure
2579 * return - true if success, false otherwise.
2580 */
2581 bool dc_submit_i2c(
2582 struct dc *dc,
2583 uint32_t link_index,
2584 struct i2c_command *cmd);
2585
2586 /* submit i2c read/write payloads through oem channel
2587 * @link_index - index to a link with ddc in i2c mode
2588 * @cmd - i2c command structure
2589 * return - true if success, false otherwise.
2590 */
2591 bool dc_submit_i2c_oem(
2592 struct dc *dc,
2593 struct i2c_command *cmd);
2594
2595 enum aux_return_code_type;
2596 /* Attempt to transfer the given aux payload. This function does not perform
2597 * retries or handle error states. The reply is returned in the payload->reply
2598 * and the result through operation_result. Returns the number of bytes
2599 * transferred,or -1 on a failure.
2600 */
2601 int dc_link_aux_transfer_raw(struct ddc_service *ddc,
2602 struct aux_payload *payload,
2603 enum aux_return_code_type *operation_result);
2604
2605 struct ddc_service *
2606 dc_get_oem_i2c_device(struct dc *dc);
2607
2608 bool dc_is_oem_i2c_device_present(
2609 struct dc *dc,
2610 size_t slave_address
2611 );
2612
2613 /* return true if the connected receiver supports the hdcp version */
2614 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
2615 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
2616
2617 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
2618 *
2619 * TODO - When defer_handling is true the function will have a different purpose.
2620 * It no longer does complete hpd rx irq handling. We should create a separate
2621 * interface specifically for this case.
2622 *
2623 * Return:
2624 * true - Downstream port status changed. DM should call DC to do the
2625 * detection.
2626 * false - no change in Downstream port status. No further action required
2627 * from DM.
2628 */
2629 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
2630 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,
2631 bool defer_handling, bool *has_left_work);
2632 /* handle DP specs define test automation sequence*/
2633 void dc_link_dp_handle_automated_test(struct dc_link *link);
2634
2635 /* handle DP Link loss sequence and try to recover RX link loss with best
2636 * effort
2637 */
2638 void dc_link_dp_handle_link_loss(struct dc_link *link);
2639
2640 /* Determine if hpd rx irq should be handled or ignored
2641 * return true - hpd rx irq should be handled.
2642 * return false - it is safe to ignore hpd rx irq event
2643 */
2644 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);
2645
2646 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data.
2647 * @link - link the hpd irq data associated with
2648 * @hpd_irq_dpcd_data - input hpd irq data
2649 * return - true if hpd irq data indicates a link lost
2650 */
2651 bool dc_link_check_link_loss_status(struct dc_link *link,
2652 union hpd_irq_data *hpd_irq_dpcd_data);
2653
2654 /* Read hpd rx irq data from a given link
2655 * @link - link where the hpd irq data should be read from
2656 * @irq_data - output hpd irq data
2657 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
2658 * read has failed.
2659 */
2660 enum dc_status dc_link_dp_read_hpd_rx_irq_data(
2661 struct dc_link *link,
2662 union hpd_irq_data *irq_data);
2663
2664 bool dc_link_frl_poll_status_flag(struct dc_link *link);
2665 bool dc_link_frl_margin_check_uncompressed_video(
2666 const struct dc_link *link,
2667 struct frl_cap_chk_params_fixed31_32 *params,
2668 struct frl_cap_chk_intermediates_fixed31_32 *inter);
2669
2670 /* The function clears recorded DP RX states in the link. DM should call this
2671 * function when it is resuming from S3 power state to previously connected links.
2672 *
2673 * TODO - in the future we should consider to expand link resume interface to
2674 * support clearing previous rx states. So we don't have to rely on dm to call
2675 * this interface explicitly.
2676 */
2677 void dc_link_clear_dprx_states(struct dc_link *link);
2678
2679 /* Destruct the mst topology of the link and reset the allocated payload table
2680 *
2681 * NOTE: this should only be called if DM chooses not to call dc_link_detect but
2682 * still wants to reset MST topology on an unplug event */
2683 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);
2684
2685 /* The function calculates effective DP link bandwidth when a given link is
2686 * using the given link settings.
2687 *
2688 * return - total effective link bandwidth in kbps.
2689 */
2690 uint32_t dc_link_bandwidth_kbps(
2691 const struct dc_link *link,
2692 const struct dc_link_settings *link_setting);
2693
2694 /* The function returns effective HDMI FRL bandwidth given link rate.
2695 * return - total effective link bandwidth in kbps.
2696 */
2697 uint32_t dc_link_frl_bandwidth_kbps(const struct dc_link *link,
2698 enum hdmi_frl_link_rate link_rate);
2699
2700 struct dp_audio_bandwidth_params {
2701 const struct dc_crtc_timing *crtc_timing;
2702 enum dp_link_encoding link_encoding;
2703 uint32_t channel_count;
2704 uint32_t sample_rate_hz;
2705 };
2706
2707 /* The function calculates the minimum size of hblank (in bytes) needed to
2708 * support the specified channel count and sample rate combination, given the
2709 * link encoding and timing to be used. This calculation is not supported
2710 * for 8b/10b SST.
2711 *
2712 * return - min hblank size in bytes, 0 if 8b/10b SST.
2713 */
2714 uint32_t dc_link_required_hblank_size_bytes(
2715 const struct dc_link *link,
2716 struct dp_audio_bandwidth_params *audio_params);
2717
2718 /* The function takes a snapshot of current link resource allocation state
2719 * @dc: pointer to dc of the dm calling this
2720 * @map: a dc link resource snapshot defined internally to dc.
2721 *
2722 * DM needs to capture a snapshot of current link resource allocation mapping
2723 * and store it in its persistent storage.
2724 *
2725 * Some of the link resource is using first come first serve policy.
2726 * The allocation mapping depends on original hotplug order. This information
2727 * is lost after driver is loaded next time. The snapshot is used in order to
2728 * restore link resource to its previous state so user will get consistent
2729 * link capability allocation across reboot.
2730 *
2731 */
2732 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
2733
2734 /* This function restores link resource allocation state from a snapshot
2735 * @dc: pointer to dc of the dm calling this
2736 * @map: a dc link resource snapshot defined internally to dc.
2737 *
2738 * DM needs to call this function after initial link detection on boot and
2739 * before first commit streams to restore link resource allocation state
2740 * from previous boot session.
2741 *
2742 * Some of the link resource is using first come first serve policy.
2743 * The allocation mapping depends on original hotplug order. This information
2744 * is lost after driver is loaded next time. The snapshot is used in order to
2745 * restore link resource to its previous state so user will get consistent
2746 * link capability allocation across reboot.
2747 *
2748 */
2749 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
2750
2751 void dc_link_wait_for_unlocked(struct dc_link *link);
2752
2753 /* TODO: this is not meant to be exposed to DM. Should switch to stream update
2754 * interface i.e stream_update->dsc_config
2755 */
2756 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);
2757
2758 /* translate a raw link rate data to bandwidth in kbps */
2759 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);
2760
2761 /* determine the optimal bandwidth given link and required bw.
2762 * @link - current detected link
2763 * @req_bw - requested bandwidth in kbps
2764 * @link_settings - returned most optimal link settings that can fit the
2765 * requested bandwidth
2766 * return - false if link can't support requested bandwidth, true if link
2767 * settings is found.
2768 */
2769 bool dc_link_decide_edp_link_settings(struct dc_link *link,
2770 struct dc_link_settings *link_settings,
2771 uint32_t req_bw);
2772
2773 /* return the max dp link settings can be driven by the link without considering
2774 * connected RX device and its capability
2775 */
2776 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,
2777 struct dc_link_settings *max_link_enc_cap);
2778
2779 /* determine when the link is driving MST mode, what DP link channel coding
2780 * format will be used. The decision will remain unchanged until next HPD event.
2781 *
2782 * @link - a link with DP RX connection
2783 * return - if stream is committed to this link with MST signal type, type of
2784 * channel coding format dc will choose.
2785 */
2786 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(
2787 const struct dc_link *link);
2788
2789 /* get max dp link settings the link can enable with all things considered. (i.e
2790 * TX/RX/Cable capabilities and dp override policies.
2791 *
2792 * @link - a link with DP RX connection
2793 * return - max dp link settings the link can enable.
2794 *
2795 */
2796 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link);
2797
2798 /* Get the highest encoding format that the link supports; highest meaning the
2799 * encoding format which supports the maximum bandwidth.
2800 *
2801 * @link - a link with DP RX connection
2802 * return - highest encoding format link supports.
2803 */
2804 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link);
2805
2806 /* get max frl link settings the link can enable with all things considered.
2807 * (i.e TX/RX capabilities and link verification result.
2808 *
2809 * @link - a link with FRL RX connection
2810 * return - max frl link settings the link can enable.
2811 *
2812 */
2813 struct dc_hdmi_frl_link_settings *dc_link_get_frl_link_cap(
2814 struct dc_link *link);
2815
2816 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected
2817 * to a link with dp connector signal type.
2818 * @link - a link with dp connector signal type
2819 * return - true if connected, false otherwise
2820 */
2821 bool dc_link_is_dp_sink_present(struct dc_link *link);
2822
2823 /* Force DP lane settings update to main-link video signal and notify the change
2824 * to DP RX via DPCD. This is a debug interface used for video signal integrity
2825 * tuning purpose. The interface assumes link has already been enabled with DP
2826 * signal.
2827 *
2828 * @lt_settings - a container structure with desired hw_lane_settings
2829 */
2830 void dc_link_set_drive_settings(struct dc *dc,
2831 struct link_training_settings *lt_settings,
2832 struct dc_link *link);
2833
2834 /* Enable a test pattern in Link or PHY layer in an active link for compliance
2835 * test or debugging purpose. The test pattern will remain until next un-plug.
2836 *
2837 * @link - active link with DP signal output enabled.
2838 * @test_pattern - desired test pattern to output.
2839 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern.
2840 * @test_pattern_color_space - for video test pattern choose a desired color
2841 * space.
2842 * @p_link_settings - For PHY pattern choose a desired link settings
2843 * @p_custom_pattern - some test pattern will require a custom input to
2844 * customize some pattern details. Otherwise keep it to NULL.
2845 * @cust_pattern_size - size of the custom pattern input.
2846 *
2847 */
2848 bool dc_link_dp_set_test_pattern(
2849 struct dc_link *link,
2850 enum dp_test_pattern test_pattern,
2851 enum dp_test_pattern_color_space test_pattern_color_space,
2852 const struct link_training_settings *p_link_settings,
2853 const unsigned char *p_custom_pattern,
2854 unsigned int cust_pattern_size);
2855
2856 /* Force DP link settings to always use a specific value until reboot to a
2857 * specific link. If link has already been enabled, the interface will also
2858 * switch to desired link settings immediately. This is a debug interface to
2859 * generic dp issue trouble shooting.
2860 */
2861 void dc_link_set_preferred_link_settings(struct dc *dc,
2862 struct dc_link_settings *link_setting,
2863 struct dc_link *link);
2864
2865 /* Force FRL link settings to always use a specific value until reboot to a
2866 * specific link. If link has already been enabled, the interface will also
2867 * switch to desired link settings immediately. This is a debug interface to
2868 * generic FRL issue trouble shooting.
2869 */
2870 void dc_link_set_preferred_frl_link_settings(struct dc *dc,
2871 struct dc_hdmi_frl_link_settings *link_setting,
2872 struct dc_hdmi_frl_link_training_overrides *lt_overrides,
2873 struct dc_link *link);
2874
2875 /* Force DP link to customize a specific link training behavior by overriding to
2876 * standard DP specs defined protocol. This is a debug interface to trouble shoot
2877 * display specific link training issues or apply some display specific
2878 * workaround in link training.
2879 *
2880 * @link_settings - if not NULL, force preferred link settings to the link.
2881 * @lt_override - a set of override pointers. If any pointer is none NULL, dc
2882 * will apply this particular override in future link training. If NULL is
2883 * passed in, dc resets previous overrides.
2884 * NOTE: DM must keep the memory from override pointers until DM resets preferred
2885 * training settings.
2886 */
2887 void dc_link_set_preferred_training_settings(struct dc *dc,
2888 struct dc_link_settings *link_setting,
2889 struct dc_link_training_overrides *lt_overrides,
2890 struct dc_link *link,
2891 bool skip_immediate_retrain);
2892
2893 /* return - true if FEC is supported with connected DP RX, false otherwise */
2894 bool dc_link_is_fec_supported(const struct dc_link *link);
2895
2896 /* query FEC enablement policy to determine if FEC will be enabled by dc during
2897 * link enablement.
2898 * return - true if FEC should be enabled, false otherwise.
2899 */
2900 bool dc_link_should_enable_fec(const struct dc_link *link);
2901
2902 /* determine lttpr mode the current link should be enabled with a specific link
2903 * settings.
2904 */
2905 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link,
2906 struct dc_link_settings *link_setting);
2907
2908 /* Force DP RX to update its power state.
2909 * NOTE: this interface doesn't update dp main-link. Calling this function will
2910 * cause DP TX main-link and DP RX power states out of sync. DM has to restore
2911 * RX power state back upon finish DM specific execution requiring DP RX in a
2912 * specific power state.
2913 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
2914 * state.
2915 */
2916 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on);
2917
2918 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
2919 * current value read from extended receiver cap from 02200h - 0220Fh.
2920 * Some DP RX has problems of providing accurate DP receiver caps from extended
2921 * field, this interface is a workaround to revert link back to use base caps.
2922 */
2923 void dc_link_overwrite_extended_receiver_cap(
2924 struct dc_link *link);
2925
2926 void dc_link_edp_panel_backlight_power_on(struct dc_link *link,
2927 bool wait_for_hpd);
2928
2929 /* Set backlight level of an embedded panel (eDP, LVDS).
2930 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer
2931 * and 16 bit fractional, where 1.0 is max backlight value.
2932 */
2933 bool dc_link_set_backlight_level(const struct dc_link *dc_link,
2934 struct set_backlight_level_params *backlight_level_params);
2935
2936 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
2937 bool dc_link_set_backlight_level_nits(struct dc_link *link,
2938 bool isHDR,
2939 uint32_t backlight_millinits,
2940 uint32_t transition_time_in_ms);
2941
2942 bool dc_link_get_backlight_level_nits(struct dc_link *link,
2943 uint32_t *backlight_millinits,
2944 uint32_t *backlight_millinits_peak);
2945
2946 int dc_link_get_backlight_level(const struct dc_link *dc_link);
2947
2948 int dc_link_get_target_backlight_pwm(const struct dc_link *link);
2949
2950 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable,
2951 bool wait, bool force_static, const unsigned int *power_opts);
2952
2953 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state);
2954
2955 bool dc_link_setup_psr(struct dc_link *dc_link,
2956 const struct dc_stream_state *stream, struct psr_config *psr_config,
2957 struct psr_context *psr_context);
2958
2959 /*
2960 * Communicate with DMUB to allow or disallow Panel Replay on the specified link:
2961 *
2962 * @link: pointer to the dc_link struct instance
2963 * @enable: enable(active) or disable(inactive) replay
2964 * @wait: state transition need to wait the active set completed.
2965 * @force_static: force disable(inactive) the replay
2966 * @power_opts: set power optimazation parameters to DMUB.
2967 *
2968 * return: allow Replay active will return true, else will return false.
2969 */
2970 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,
2971 bool wait, bool force_static, const unsigned int *power_opts);
2972
2973 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state);
2974
2975 /*
2976 * Enable or disable Panel Replay on the specified link:
2977 *
2978 * @link: pointer to the dc_link struct instance
2979 * @enable: enable or disable Panel Replay
2980 *
2981 * return: true if successful, false otherwise
2982 */
2983 bool dc_link_set_pr_enable(struct dc_link *link, bool enable);
2984
2985 /*
2986 * Update Panel Replay state parameters:
2987 *
2988 * @link: pointer to the dc_link struct instance
2989 * @update_state_data: pointer to state update data structure
2990 *
2991 * return: true if successful, false otherwise
2992 */
2993 bool dc_link_update_pr_state(struct dc_link *link,
2994 struct dmub_cmd_pr_update_state_data *update_state_data);
2995
2996 /*
2997 * Send general command to Panel Replay firmware:
2998 *
2999 * @link: pointer to the dc_link struct instance
3000 * @general_cmd_data: pointer to general command data structure
3001 *
3002 * return: true if successful, false otherwise
3003 */
3004 bool dc_link_set_pr_general_cmd(struct dc_link *link,
3005 struct dmub_cmd_pr_general_cmd_data *general_cmd_data);
3006
3007 /*
3008 * Measure Panel Replay residency for the given link.
3009 * mode: PR_RESIDENCY_MODE_PHY, PR_RESIDENCY_MODE_ALPM, or
3010 * PR_RESIDENCY_MODE_ENABLEMENT_PERIOD
3011 */
3012 void dc_link_edp_replay_residency(const struct dc_link *link,
3013 unsigned int *residency, bool is_start, enum pr_residency_mode mode);
3014
3015 /*
3016 * Get Panel Replay state:
3017 *
3018 * @link: pointer to the dc_link struct instance
3019 * @state: pointer to store the Panel Replay state
3020 *
3021 * return: true if successful, false otherwise
3022 */
3023 bool dc_link_get_pr_state(const struct dc_link *link, uint64_t *state);
3024
3025 /* On eDP links this function call will stall until T12 has elapsed.
3026 * If the panel is not in power off state, this function will return
3027 * immediately.
3028 */
3029 bool dc_link_wait_for_t12(struct dc_link *link);
3030
3031 /* Determine if dp trace has been initialized to reflect upto date result *
3032 * return - true if trace is initialized and has valid data. False dp trace
3033 * doesn't have valid result.
3034 */
3035 bool dc_dp_trace_is_initialized(struct dc_link *link);
3036
3037 /* Query a dp trace flag to indicate if the current dp trace data has been
3038 * logged before
3039 */
3040 bool dc_dp_trace_is_logged(struct dc_link *link,
3041 bool in_detection);
3042
3043 /* Set dp trace flag to indicate whether DM has already logged the current dp
3044 * trace data. DM can set is_logged to true upon logging and check
3045 * dc_dp_trace_is_logged before logging to avoid logging the same result twice.
3046 */
3047 void dc_dp_trace_set_is_logged_flag(struct dc_link *link,
3048 bool in_detection,
3049 bool is_logged);
3050
3051 /* Obtain driver time stamp for last dp link training end. The time stamp is
3052 * formatted based on dm_get_timestamp DM function.
3053 * @in_detection - true to get link training end time stamp of last link
3054 * training in detection sequence. false to get link training end time stamp
3055 * of last link training in commit (dpms) sequence
3056 */
3057 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link,
3058 bool in_detection);
3059
3060 /* Get how many link training attempts dc has done with latest sequence.
3061 * @in_detection - true to get link training count of last link
3062 * training in detection sequence. false to get link training count of last link
3063 * training in commit (dpms) sequence
3064 */
3065 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link,
3066 bool in_detection);
3067
3068 /* Get how many link loss has happened since last link training attempts */
3069 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link);
3070
3071 /*
3072 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS
3073 */
3074 /*
3075 * Send a request from DP-Tx requesting to allocate BW remotely after
3076 * allocating it locally. This will get processed by CM and a CB function
3077 * will be called.
3078 *
3079 * @link: pointer to the dc_link struct instance
3080 * @req_bw: The requested bw in Kbyte to allocated
3081 *
3082 * return: none
3083 */
3084 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw);
3085
3086 /*
3087 * Handle the USB4 BW Allocation related functionality here:
3088 * Plug => Try to allocate max bw from timing parameters supported by the sink
3089 * Unplug => de-allocate bw
3090 *
3091 * @link: pointer to the dc_link struct instance
3092 * @peak_bw: Peak bw used by the link/sink
3093 *
3094 */
3095 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(
3096 struct dc_link *link, int peak_bw);
3097
3098 /*
3099 * Calculates the DP tunneling bandwidth required for the stream timing
3100 * and aggregates the stream bandwidth for the respective DP tunneling link
3101 *
3102 * return: dc_status
3103 */
3104 enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx);
3105
3106 /*
3107 * Get if ALPM is supported by the link
3108 */
3109 void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support,
3110 bool *auxwake_support);
3111
3112 /* Sink Interfaces - A sink corresponds to a display output device */
3113
3114 struct dc_container_id {
3115 // 128bit GUID in binary form
3116 unsigned char guid[16];
3117 // 8 byte port ID -> ELD.PortID
3118 unsigned int portId[2];
3119 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
3120 unsigned short manufacturerName;
3121 // 2 byte product code -> ELD.ProductCode
3122 unsigned short productCode;
3123 };
3124
3125
3126 struct dc_sink_dsc_caps {
3127 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
3128 // 'false' if they are sink's DSC caps
3129 bool is_virtual_dpcd_dsc;
3130 // 'true' if MST topology supports DSC passthrough for sink
3131 // 'false' if MST topology does not support DSC passthrough
3132 bool is_dsc_passthrough_supported;
3133 struct dsc_dec_dpcd_caps dsc_dec_caps;
3134 };
3135
3136 struct dc_sink_hblank_expansion_caps {
3137 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology),
3138 // 'false' if they are sink's HBlank expansion caps
3139 bool is_virtual_dpcd_hblank_expansion;
3140 struct hblank_expansion_dpcd_caps dpcd_caps;
3141 };
3142
3143 struct dc_sink_fec_caps {
3144 bool is_rx_fec_supported;
3145 bool is_topology_fec_supported;
3146 };
3147
3148 struct scdc_caps {
3149 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI;
3150 union hdmi_scdc_device_id_data device_id;
3151 };
3152
3153 /*
3154 * The sink structure contains EDID and other display device properties
3155 */
3156 struct dc_sink {
3157 enum signal_type sink_signal;
3158 struct dc_edid dc_edid; /* raw edid */
3159 struct dc_edid_caps edid_caps; /* parse display caps */
3160 struct dc_container_id *dc_container_id;
3161 uint32_t dongle_max_pix_clk;
3162 void *priv;
3163 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
3164 bool converter_disable_audio;
3165
3166 struct mccs_caps mccs_caps;
3167 struct scdc_caps scdc_caps;
3168 struct dc_sink_dsc_caps dsc_caps;
3169 struct dc_sink_fec_caps fec_caps;
3170 struct dc_sink_hblank_expansion_caps hblank_expansion_caps;
3171
3172 bool is_vsc_sdp_colorimetry_supported;
3173
3174 /* private to DC core */
3175 struct dc_link *link;
3176 struct dc_context *ctx;
3177
3178 uint32_t sink_id;
3179
3180 /* private to dc_sink.c */
3181 // refcount must be the last member in dc_sink, since we want the
3182 // sink structure to be logically cloneable up to (but not including)
3183 // refcount
3184 struct kref refcount;
3185 };
3186
3187 void dc_sink_retain(struct dc_sink *sink);
3188 void dc_sink_release(struct dc_sink *sink);
3189
3190 struct dc_sink_init_data {
3191 enum signal_type sink_signal;
3192 struct dc_link *link;
3193 uint32_t dongle_max_pix_clk;
3194 bool converter_disable_audio;
3195 };
3196
3197 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
3198
3199 /* Newer interfaces */
3200 struct dc_cursor {
3201 struct dc_plane_address address;
3202 struct dc_cursor_attributes attributes;
3203 };
3204
3205
3206 /* Interrupt interfaces */
3207 enum dc_irq_source dc_interrupt_to_irq_source(
3208 struct dc *dc,
3209 uint32_t src_id,
3210 uint32_t ext_id);
3211 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
3212 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
3213 bool dc_get_flip_pending_on_otg(struct dc *dc, int otg_inst);
3214 enum dc_irq_source dc_get_hpd_irq_source_at_index(
3215 struct dc *dc, uint32_t link_index);
3216
3217 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
3218
3219 /* Power Interfaces */
3220
3221 void dc_set_power_state(
3222 struct dc *dc,
3223 enum dc_acpi_cm_power_state power_state);
3224 void dc_resume(struct dc *dc);
3225
3226 void dc_power_down_on_boot(struct dc *dc);
3227
3228 void dc_disable_dangling_timing_generators(struct dc *dc);
3229
3230 /*
3231 * HDCP Interfaces
3232 */
3233 enum hdcp_message_status dc_process_hdcp_msg(
3234 enum signal_type signal,
3235 struct dc_link *link,
3236 struct hdcp_protection_message *message_info);
3237 bool dc_is_dmcu_initialized(struct dc *dc);
3238
3239 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
3240 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
3241
3242 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
3243 unsigned int pitch,
3244 unsigned int height,
3245 enum surface_pixel_format format,
3246 struct dc_cursor_attributes *cursor_attr);
3247
3248 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__)
3249 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__)
3250
3251 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name);
3252 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name);
3253 bool dc_dmub_is_ips_idle_state(struct dc *dc);
3254
3255 /* set min and max memory clock to lowest and highest DPM level, respectively */
3256 void dc_unlock_memory_clock_frequency(struct dc *dc);
3257
3258 /* set min memory clock to the min required for current mode, max to maxDPM */
3259 void dc_lock_memory_clock_frequency(struct dc *dc);
3260
3261 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
3262 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
3263
3264 /* cleanup on driver unload */
3265 void dc_hardware_release(struct dc *dc);
3266
3267 /* disables fw based mclk switch */
3268 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
3269
3270 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
3271
3272 bool dc_set_replay_allow_active(struct dc *dc, bool active);
3273
3274 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips);
3275
3276 void dc_z10_restore(const struct dc *dc);
3277 void dc_z10_save_init(struct dc *dc);
3278
3279 bool dc_is_dmub_outbox_supported(struct dc *dc);
3280 bool dc_enable_dmub_notifications(struct dc *dc);
3281
3282 bool dc_abm_save_restore(
3283 struct dc *dc,
3284 struct dc_stream_state *stream,
3285 struct abm_save_restore *pData);
3286
3287 void dc_enable_dmub_outbox(struct dc *dc);
3288
3289 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
3290 uint32_t link_index,
3291 struct aux_payload *payload);
3292
3293 /*
3294 * smart power OLED Interfaces
3295 */
3296 bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits,
3297 uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline);
3298 bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL);
3299
3300 /* Get dc link index from dpia port index */
3301 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
3302 uint8_t dpia_port_index);
3303
3304 bool dc_process_dmub_set_config_async(struct dc *dc,
3305 uint32_t link_index,
3306 struct set_config_cmd_payload *payload,
3307 struct dmub_notification *notify);
3308
3309 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
3310 uint32_t link_index,
3311 uint8_t mst_alloc_slots,
3312 uint8_t *mst_slots_in_use);
3313
3314 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps);
3315
3316 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
3317 uint32_t hpd_int_enable);
3318
3319 void dc_print_dmub_diagnostic_data(const struct dc *dc);
3320
3321 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);
3322
3323 struct dc_power_profile {
3324 int power_level; /* Lower is better */
3325 };
3326
3327 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context);
3328
3329 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context);
3330
3331 bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index);
3332
3333 void dc_log_preos_dmcub_info(const struct dc *dc);
3334
3335 /* DSC Interfaces */
3336 #include "dc_dsc.h"
3337
3338 void dc_get_visual_confirm_for_stream(
3339 struct dc *dc,
3340 struct dc_stream_state *stream_state,
3341 struct tg_color *color);
3342
3343 /* Disable acc mode Interfaces */
3344 void dc_disable_accelerated_mode(struct dc *dc);
3345
3346 bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
3347 struct dc_stream_state *new_stream);
3348
3349 bool dc_is_cursor_limit_pending(struct dc *dc);
3350 bool dc_can_clear_cursor_limit(const struct dc *dc);
3351
3352 /**
3353 * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data.
3354 *
3355 * @dc: Pointer to the display core context.
3356 * @primary_otg_inst: Instance index of the primary OTG that underflowed.
3357 * @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information.
3358 *
3359 * This function collects and logs underflow-related HW states when underflow happens,
3360 * including OTG underflow status, current read positions, frame count, and per-HUBP debug data.
3361 * The results are stored in the provided out_data structure for further analysis or logging.
3362 */
3363 void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data);
3364
3365 void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data);
3366
3367 /*
3368 * Software state variables used to program register fields across the display pipeline
3369 */
3370 struct dc_register_software_state {
3371 /* HUBP register programming variables for each pipe */
3372 struct {
3373 bool valid_plane_state;
3374 bool valid_stream;
3375 bool min_dc_gfx_version9;
3376 uint32_t vtg_sel; /* DCHUBP_CNTL->HUBP_VTG_SEL from pipe_ctx->stream_res.tg->inst */
3377 uint32_t hubp_clock_enable; /* HUBP_CLK_CNTL->HUBP_CLOCK_ENABLE from power management */
3378 uint32_t surface_pixel_format; /* DCSURF_SURFACE_CONFIG->SURFACE_PIXEL_FORMAT from plane_state->format */
3379 uint32_t rotation_angle; /* DCSURF_SURFACE_CONFIG->ROTATION_ANGLE from plane_state->rotation */
3380 uint32_t h_mirror_en; /* DCSURF_SURFACE_CONFIG->H_MIRROR_EN from plane_state->horizontal_mirror */
3381 uint32_t surface_dcc_en; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_EN from dcc->enable */
3382 uint32_t surface_size_width; /* HUBP_SIZE->SURFACE_SIZE_WIDTH from plane_size.surface_size.width */
3383 uint32_t surface_size_height; /* HUBP_SIZE->SURFACE_SIZE_HEIGHT from plane_size.surface_size.height */
3384 uint32_t pri_viewport_width; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_WIDTH from scaler_data.viewport.width */
3385 uint32_t pri_viewport_height; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_HEIGHT from scaler_data.viewport.height */
3386 uint32_t pri_viewport_x_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_X_START from scaler_data.viewport.x */
3387 uint32_t pri_viewport_y_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_Y_START from scaler_data.viewport.y */
3388 uint32_t cursor_enable; /* CURSOR_CONTROL->CURSOR_ENABLE from cursor_attributes.enable */
3389 uint32_t cursor_width; /* CURSOR_SETTINGS->CURSOR_WIDTH from cursor_position.width */
3390 uint32_t cursor_height; /* CURSOR_SETTINGS->CURSOR_HEIGHT from cursor_position.height */
3391
3392 /* Additional DCC configuration */
3393 uint32_t surface_dcc_ind_64b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_64B_BLK from dcc.independent_64b_blks */
3394 uint32_t surface_dcc_ind_128b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_128B_BLK from dcc.independent_128b_blks */
3395
3396 /* Surface pitch configuration */
3397 uint32_t surface_pitch; /* DCSURF_SURFACE_PITCH->PITCH from plane_size.surface_pitch */
3398 uint32_t meta_pitch; /* DCSURF_SURFACE_PITCH->META_PITCH from dcc.meta_pitch */
3399 uint32_t chroma_pitch; /* DCSURF_SURFACE_PITCH_C->PITCH_C from plane_size.chroma_pitch */
3400 uint32_t meta_pitch_c; /* DCSURF_SURFACE_PITCH_C->META_PITCH_C from dcc.meta_pitch_c */
3401
3402 /* Surface addresses */
3403 uint32_t primary_surface_address_low; /* DCSURF_PRIMARY_SURFACE_ADDRESS->PRIMARY_SURFACE_ADDRESS from address.grph.addr.low_part */
3404 uint32_t primary_surface_address_high; /* DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH->PRIMARY_SURFACE_ADDRESS_HIGH from address.grph.addr.high_part */
3405 uint32_t primary_meta_surface_address_low; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS->PRIMARY_META_SURFACE_ADDRESS from address.grph.meta_addr.low_part */
3406 uint32_t primary_meta_surface_address_high; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH->PRIMARY_META_SURFACE_ADDRESS_HIGH from address.grph.meta_addr.high_part */
3407
3408 /* TMZ configuration */
3409 uint32_t primary_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_TMZ from address.tmz_surface */
3410 uint32_t primary_meta_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_META_SURFACE_TMZ from address.tmz_surface */
3411
3412 /* Tiling configuration */
3413 uint32_t sw_mode; /* DCSURF_TILING_CONFIG->SW_MODE from tiling_info.gfx9.swizzle */
3414 uint32_t num_pipes; /* DCSURF_ADDR_CONFIG->NUM_PIPES from tiling_info.gfx9.num_pipes */
3415 uint32_t num_banks; /* DCSURF_ADDR_CONFIG->NUM_BANKS from tiling_info.gfx9.num_banks */
3416 uint32_t pipe_interleave; /* DCSURF_ADDR_CONFIG->PIPE_INTERLEAVE from tiling_info.gfx9.pipe_interleave */
3417 uint32_t num_shader_engines; /* DCSURF_ADDR_CONFIG->NUM_SE from tiling_info.gfx9.num_shader_engines */
3418 uint32_t num_rb_per_se; /* DCSURF_ADDR_CONFIG->NUM_RB_PER_SE from tiling_info.gfx9.num_rb_per_se */
3419 uint32_t num_pkrs; /* DCSURF_ADDR_CONFIG->NUM_PKRS from tiling_info.gfx9.num_pkrs */
3420
3421 /* DML Request Size Configuration - Luma */
3422 uint32_t rq_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->CHUNK_SIZE from rq_regs.rq_regs_l.chunk_size */
3423 uint32_t rq_min_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_CHUNK_SIZE from rq_regs.rq_regs_l.min_chunk_size */
3424 uint32_t rq_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->META_CHUNK_SIZE from rq_regs.rq_regs_l.meta_chunk_size */
3425 uint32_t rq_min_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_META_CHUNK_SIZE from rq_regs.rq_regs_l.min_meta_chunk_size */
3426 uint32_t rq_dpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->DPTE_GROUP_SIZE from rq_regs.rq_regs_l.dpte_group_size */
3427 uint32_t rq_mpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->MPTE_GROUP_SIZE from rq_regs.rq_regs_l.mpte_group_size */
3428 uint32_t rq_swath_height_l; /* DCHUBP_REQ_SIZE_CONFIG->SWATH_HEIGHT_L from rq_regs.rq_regs_l.swath_height */
3429 uint32_t rq_pte_row_height_l; /* DCHUBP_REQ_SIZE_CONFIG->PTE_ROW_HEIGHT_L from rq_regs.rq_regs_l.pte_row_height */
3430
3431 /* DML Request Size Configuration - Chroma */
3432 uint32_t rq_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->CHUNK_SIZE_C from rq_regs.rq_regs_c.chunk_size */
3433 uint32_t rq_min_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_chunk_size */
3434 uint32_t rq_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->META_CHUNK_SIZE_C from rq_regs.rq_regs_c.meta_chunk_size */
3435 uint32_t rq_min_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_META_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_meta_chunk_size */
3436 uint32_t rq_dpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->DPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.dpte_group_size */
3437 uint32_t rq_mpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.mpte_group_size */
3438 uint32_t rq_swath_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->SWATH_HEIGHT_C from rq_regs.rq_regs_c.swath_height */
3439 uint32_t rq_pte_row_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->PTE_ROW_HEIGHT_C from rq_regs.rq_regs_c.pte_row_height */
3440
3441 /* DML Expansion Modes */
3442 uint32_t drq_expansion_mode; /* DCN_EXPANSION_MODE->DRQ_EXPANSION_MODE from rq_regs.drq_expansion_mode */
3443 uint32_t prq_expansion_mode; /* DCN_EXPANSION_MODE->PRQ_EXPANSION_MODE from rq_regs.prq_expansion_mode */
3444 uint32_t mrq_expansion_mode; /* DCN_EXPANSION_MODE->MRQ_EXPANSION_MODE from rq_regs.mrq_expansion_mode */
3445 uint32_t crq_expansion_mode; /* DCN_EXPANSION_MODE->CRQ_EXPANSION_MODE from rq_regs.crq_expansion_mode */
3446
3447 /* DML DLG parameters - nominal */
3448 uint32_t dst_y_per_vm_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_VM_VBLANK from dlg_regs.dst_y_per_vm_vblank */
3449 uint32_t dst_y_per_row_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_ROW_VBLANK from dlg_regs.dst_y_per_row_vblank */
3450 uint32_t dst_y_per_vm_flip; /* NOM_PARAMETERS_1->DST_Y_PER_VM_FLIP from dlg_regs.dst_y_per_vm_flip */
3451 uint32_t dst_y_per_row_flip; /* NOM_PARAMETERS_1->DST_Y_PER_ROW_FLIP from dlg_regs.dst_y_per_row_flip */
3452
3453 /* DML prefetch settings */
3454 uint32_t dst_y_prefetch; /* PREFETCH_SETTINS->DST_Y_PREFETCH from dlg_regs.dst_y_prefetch */
3455 uint32_t vratio_prefetch; /* PREFETCH_SETTINS->VRATIO_PREFETCH from dlg_regs.vratio_prefetch */
3456 uint32_t vratio_prefetch_c; /* PREFETCH_SETTINS_C->VRATIO_PREFETCH_C from dlg_regs.vratio_prefetch_c */
3457
3458 /* TTU parameters */
3459 uint32_t qos_level_low_wm; /* TTU_CNTL1->QoSLevelLowWaterMark from ttu_regs.qos_level_low_wm */
3460 uint32_t qos_level_high_wm; /* TTU_CNTL1->QoSLevelHighWaterMark from ttu_regs.qos_level_high_wm */
3461 uint32_t qos_level_flip; /* TTU_CNTL2->QoS_LEVEL_FLIP_L from ttu_regs.qos_level_flip */
3462 uint32_t min_ttu_vblank; /* DCN_GLOBAL_TTU_CNTL->MIN_TTU_VBLANK from ttu_regs.min_ttu_vblank */
3463 } hubp[MAX_PIPES];
3464
3465 /* HUBBUB register programming variables */
3466 struct {
3467 /* Individual DET buffer control per pipe - software state that programs DET registers */
3468 uint32_t det0_size; /* DCHUBBUB_DET0_CTRL->DET0_SIZE from hubbub->funcs->program_det_size(hubbub, 0, det_buffer_size_kb) */
3469 uint32_t det1_size; /* DCHUBBUB_DET1_CTRL->DET1_SIZE from hubbub->funcs->program_det_size(hubbub, 1, det_buffer_size_kb) */
3470 uint32_t det2_size; /* DCHUBBUB_DET2_CTRL->DET2_SIZE from hubbub->funcs->program_det_size(hubbub, 2, det_buffer_size_kb) */
3471 uint32_t det3_size; /* DCHUBBUB_DET3_CTRL->DET3_SIZE from hubbub->funcs->program_det_size(hubbub, 3, det_buffer_size_kb) */
3472
3473 /* Compression buffer control - software state that programs COMPBUF registers */
3474 uint32_t compbuf_size; /* DCHUBBUB_COMPBUF_CTRL->COMPBUF_SIZE from hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, safe_to_increase) */
3475 uint32_t compbuf_reserved_space_64b; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_64B from hubbub2->pixel_chunk_size / 32 */
3476 uint32_t compbuf_reserved_space_zs; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_ZS from hubbub2->pixel_chunk_size / 128 */
3477 } hubbub;
3478
3479 /* DPP register programming variables for each pipe (simplified for available fields) */
3480 struct {
3481 uint32_t dpp_clock_enable; /* DPP_CONTROL->DPP_CLOCK_ENABLE from dppclk_enable */
3482
3483 /* Recout (Rectangle of Interest) configuration */
3484 uint32_t recout_start_x; /* RECOUT_START->RECOUT_START_X from pipe_ctx->plane_res.scl_data.recout.x */
3485 uint32_t recout_start_y; /* RECOUT_START->RECOUT_START_Y from pipe_ctx->plane_res.scl_data.recout.y */
3486 uint32_t recout_width; /* RECOUT_SIZE->RECOUT_WIDTH from pipe_ctx->plane_res.scl_data.recout.width */
3487 uint32_t recout_height; /* RECOUT_SIZE->RECOUT_HEIGHT from pipe_ctx->plane_res.scl_data.recout.height */
3488
3489 /* MPC (Multiple Pipe/Plane Combiner) size configuration */
3490 uint32_t mpc_width; /* MPC_SIZE->MPC_WIDTH from pipe_ctx->plane_res.scl_data.h_active */
3491 uint32_t mpc_height; /* MPC_SIZE->MPC_HEIGHT from pipe_ctx->plane_res.scl_data.v_active */
3492
3493 /* DSCL mode configuration */
3494 uint32_t dscl_mode; /* SCL_MODE->DSCL_MODE from pipe_ctx->plane_res.scl_data.dscl_prog_data.dscl_mode */
3495
3496 /* Scaler ratios (simplified to integer parts) */
3497 uint32_t horz_ratio_int; /* SCL_HORZ_FILTER_SCALE_RATIO->SCL_H_SCALE_RATIO integer part from ratios.horz */
3498 uint32_t vert_ratio_int; /* SCL_VERT_FILTER_SCALE_RATIO->SCL_V_SCALE_RATIO integer part from ratios.vert */
3499
3500 /* Basic scaler taps */
3501 uint32_t h_taps; /* SCL_TAP_CONTROL->SCL_H_NUM_TAPS from taps.h_taps */
3502 uint32_t v_taps; /* SCL_TAP_CONTROL->SCL_V_NUM_TAPS from taps.v_taps */
3503 } dpp[MAX_PIPES];
3504
3505 /* DCCG register programming variables */
3506 struct {
3507 /* Core Display Clock Control */
3508 uint32_t dispclk_khz; /* DENTIST_DISPCLK_CNTL->DENTIST_DISPCLK_WDIVIDER from clk_mgr.dispclk_khz */
3509 uint32_t dc_mem_global_pwr_req_dis; /* DC_MEM_GLOBAL_PWR_REQ_CNTL->DC_MEM_GLOBAL_PWR_REQ_DIS from memory power management settings */
3510
3511 /* DPP Clock Control - 4 fields per pipe */
3512 uint32_t dppclk_khz[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK_R_GATE_DISABLE from dpp_clocks[pipe] */
3513 uint32_t dppclk_enable[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK0_EN,DPPCLK1_EN,DPPCLK2_EN,DPPCLK3_EN from dccg31_update_dpp_dto() */
3514 uint32_t dppclk_dto_enable[MAX_PIPES]; /* DPPCLK_DTO_CTRL->DPPCLK_DTO_ENABLE from dccg->dpp_clock_gated[dpp_inst] state */
3515 uint32_t dppclk_dto_phase[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_PHASE from phase calculation req_dppclk/ref_dppclk */
3516 uint32_t dppclk_dto_modulo[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_MODULO from modulo = 0xff */
3517
3518 /* DSC Clock Control - 4 fields per DSC resource */
3519 uint32_t dscclk_khz[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK_DTO_ENABLE from dsc_clocks */
3520 uint32_t dscclk_dto_enable[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK0_DTO_ENABLE,DSCCLK1_DTO_ENABLE,DSCCLK2_DTO_ENABLE,DSCCLK3_DTO_ENABLE */
3521 uint32_t dscclk_dto_phase[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_PHASE from dccg31_enable_dscclk() */
3522 uint32_t dscclk_dto_modulo[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_MODULO from dccg31_enable_dscclk() */
3523
3524 /* Pixel Clock Control - per pipe */
3525 uint32_t pixclk_khz[MAX_PIPES]; /* PIXCLK_RESYNC_CNTL->PIXCLK_RESYNC_ENABLE from stream.timing.pix_clk_100hz */
3526 uint32_t otg_pixel_rate_div[MAX_PIPES]; /* OTG_PIXEL_RATE_DIV->OTG_PIXEL_RATE_DIV from OTG pixel rate divider control */
3527 uint32_t dtbclk_dto_enable[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_ENABLE from dccg31_set_dtbclk_dto() */
3528 uint32_t pipe_dto_src_sel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->PIPE_DTO_SRC_SEL from dccg31_set_dtbclk_dto() source selection */
3529 uint32_t dtbclk_dto_div[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_DIV from dtbdto_div calculation */
3530 uint32_t otg_add_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_ADD_PIXEL from dccg31_otg_add_pixel() */
3531 uint32_t otg_drop_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_DROP_PIXEL from dccg31_otg_drop_pixel() */
3532
3533 /* DTBCLK DTO Control - 4 DTOs */
3534 uint32_t dtbclk_dto_modulo[4]; /* DTBCLK_DTO0_MODULO->DTBCLK_DTO0_MODULO from dccg31_set_dtbclk_dto() modulo calculation */
3535 uint32_t dtbclk_dto_phase[4]; /* DTBCLK_DTO0_PHASE->DTBCLK_DTO0_PHASE from phase calculation pixclk_khz/ref_dtbclk_khz */
3536 uint32_t dtbclk_dto_dbuf_en; /* DTBCLK_DTO_DBUF_EN->DTBCLK DTO data buffer enable */
3537
3538 /* DP Stream Clock Control - 4 pipes */
3539 uint32_t dpstreamclk_enable[MAX_PIPES]; /* DPSTREAMCLK_CNTL->DPSTREAMCLK_PIPE0_EN,DPSTREAMCLK_PIPE1_EN,DPSTREAMCLK_PIPE2_EN,DPSTREAMCLK_PIPE3_EN */
3540 uint32_t dp_dto_modulo[4]; /* DP_DTO0_MODULO->DP_DTO0_MODULO from DP stream DTO programming */
3541 uint32_t dp_dto_phase[4]; /* DP_DTO0_PHASE->DP_DTO0_PHASE from DP stream DTO programming */
3542 uint32_t dp_dto_dbuf_en; /* DP_DTO_DBUF_EN->DP DTO data buffer enable */
3543
3544 /* PHY Symbol Clock Control - 5 PHYs (A,B,C,D,E) */
3545 uint32_t phy_symclk_force_en[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_EN from dccg31_set_physymclk() force_enable */
3546 uint32_t phy_symclk_force_src_sel[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_SRC_SEL from dccg31_set_physymclk() clk_src */
3547 uint32_t phy_symclk_gate_disable[5]; /* DCCG_GATE_DISABLE_CNTL2->PHYASYMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.physymclk */
3548
3549 /* SYMCLK32 SE Control - 4 instances */
3550 uint32_t symclk32_se_src_sel[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_SRC_SEL from dccg31_enable_symclk32_se() with get_phy_mux_symclk() mapping */
3551 uint32_t symclk32_se_enable[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_EN from dccg31_enable_symclk32_se() enable */
3552 uint32_t symclk32_se_gate_disable[4]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_SE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_se */
3553
3554 /* SYMCLK32 LE Control - 2 instances */
3555 uint32_t symclk32_le_src_sel[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_SRC_SEL from dccg31_enable_symclk32_le() phyd32clk source */
3556 uint32_t symclk32_le_enable[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_EN from dccg31_enable_symclk32_le() enable */
3557 uint32_t symclk32_le_gate_disable[2]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_LE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_le */
3558
3559 /* HDMI Clock Control */
3560 uint32_t hdmicharclk_enable; /* HDMICHARCLK0_CLOCK_CNTL->HDMICHARCLK0_EN from dccg31_enable_hdmicharclk() */
3561 uint32_t hdmicharclk_src_sel; /* HDMICHARCLK0_CLOCK_CNTL->HDMICHARCLK0_SRC_SEL from dccg31_enable_hdmicharclk() phypll_inst source */
3562 uint32_t hdmistreamclk_src_sel; /* HDMISTREAMCLK_CNTL->HDMISTREAMCLK0_SRC_SEL from dccg31_set_hdmistreamclk() src selection */
3563 uint32_t hdmistreamclk_dto_force_dis; /* HDMISTREAMCLK_CNTL->HDMISTREAMCLK0_DTO_FORCE_DIS from dccg31_set_hdmistreamclk() DTO force bypass */
3564 uint32_t hdmistreamclk_dto_phase; /* HDMISTREAMCLK0_DTO_PARAM->HDMISTREAMCLK0_DTO_PHASE from dccg31_disable_hdmistreamclk() */
3565 uint32_t hdmistreamclk_dto_modulo; /* HDMISTREAMCLK0_DTO_PARAM->HDMISTREAMCLK0_DTO_MODULO from dccg31_disable_hdmistreamclk() */
3566
3567 /* DPIA Clock Control */
3568 uint32_t dpiaclk_540m_dto_modulo; /* DPIACLK_540M_DTO_MODULO->DPIA 540MHz DTO modulo */
3569 uint32_t dpiaclk_540m_dto_phase; /* DPIACLK_540M_DTO_PHASE->DPIA 540MHz DTO phase */
3570 uint32_t dpiaclk_810m_dto_modulo; /* DPIACLK_810M_DTO_MODULO->DPIA 810MHz DTO modulo */
3571 uint32_t dpiaclk_810m_dto_phase; /* DPIACLK_810M_DTO_PHASE->DPIA 810MHz DTO phase */
3572 uint32_t dpiaclk_dto_cntl; /* DPIACLK_DTO_CNTL->DPIA clock DTO control */
3573 uint32_t dpiasymclk_cntl; /* DPIASYMCLK_CNTL->DPIA symbol clock control */
3574
3575 /* Clock Gating Control */
3576 uint32_t dccg_gate_disable_cntl; /* DCCG_GATE_DISABLE_CNTL->Clock gate disable control from dccg31_init() */
3577 uint32_t dpstreamclk_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */
3578 uint32_t dpstreamclk_root_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_ROOT_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */
3579
3580 /* VSync Control */
3581 uint32_t vsync_cnt_ctrl; /* DCCG_VSYNC_CNT_CTRL->VSync counter control */
3582 uint32_t vsync_cnt_int_ctrl; /* DCCG_VSYNC_CNT_INT_CTRL->VSync counter interrupt control */
3583 uint32_t vsync_otg_latch_value[6]; /* DCCG_VSYNC_OTG0_LATCH_VALUE->OTG0 VSync latch value (for OTG0-5) */
3584
3585 /* Time Base Control */
3586 uint32_t microsecond_time_base_div; /* MICROSECOND_TIME_BASE_DIV->Microsecond time base divider */
3587 uint32_t millisecond_time_base_div; /* MILLISECOND_TIME_BASE_DIV->Millisecond time base divider */
3588 } dccg;
3589
3590 /* DSC essential configuration for underflow analysis */
3591 struct {
3592 /* DSC active state - critical for bandwidth analysis */
3593 uint32_t dsc_clock_enable; /* DSC enabled - affects bandwidth requirements */
3594
3595 /* DSC configuration affecting bandwidth and timing */
3596 uint32_t dsc_num_slices_h; /* Horizontal slice count - affects throughput */
3597 uint32_t dsc_num_slices_v; /* Vertical slice count - affects throughput */
3598 uint32_t dsc_bits_per_pixel; /* Compression ratio - affects bandwidth */
3599
3600 /* OPP integration - affects pipeline flow */
3601 uint32_t dscrm_dsc_forward_enable; /* DSC forwarding to OPP enabled */
3602 uint32_t dscrm_dsc_opp_pipe_source; /* Which OPP receives DSC output */
3603 } dsc[MAX_PIPES];
3604
3605 /* MPC register programming variables */
3606 struct {
3607 /* MPCC blending tree and mode control */
3608 uint32_t mpcc_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_MODE from blend_cfg.blend_mode */
3609 uint32_t mpcc_alpha_blend_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_BLND_MODE from blend_cfg.alpha_mode */
3610 uint32_t mpcc_alpha_multiplied_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_MULTIPLIED_MODE from blend_cfg.pre_multiplied_alpha */
3611 uint32_t mpcc_blnd_active_overlap_only[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BLND_ACTIVE_OVERLAP_ONLY from blend_cfg.overlap_only */
3612 uint32_t mpcc_global_alpha[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_ALPHA from blend_cfg.global_alpha */
3613 uint32_t mpcc_global_gain[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_GAIN from blend_cfg.global_gain */
3614 uint32_t mpcc_bg_bpc[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BG_BPC from background color depth */
3615 uint32_t mpcc_bot_gain_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BOT_GAIN_MODE from bottom layer gain control */
3616
3617 /* MPCC blending tree connections */
3618 uint32_t mpcc_bot_sel[MAX_PIPES]; /* MPCC_BOT_SEL->MPCC_BOT_SEL from mpcc_state->bot_sel */
3619 uint32_t mpcc_top_sel[MAX_PIPES]; /* MPCC_TOP_SEL->MPCC_TOP_SEL from mpcc_state->dpp_id */
3620
3621 /* MPCC output gamma control */
3622 uint32_t mpcc_ogam_mode[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_MODE from output gamma mode */
3623 uint32_t mpcc_ogam_select[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_SELECT from gamma LUT bank selection */
3624 uint32_t mpcc_ogam_pwl_disable[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_PWL_DISABLE from PWL control */
3625
3626 /* MPCC pipe assignment and status */
3627 uint32_t mpcc_opp_id[MAX_PIPES]; /* MPCC_OPP_ID->MPCC_OPP_ID from mpcc_state->opp_id */
3628 uint32_t mpcc_idle[MAX_PIPES]; /* MPCC_STATUS->MPCC_IDLE from mpcc idle status */
3629 uint32_t mpcc_busy[MAX_PIPES]; /* MPCC_STATUS->MPCC_BUSY from mpcc busy status */
3630
3631 /* MPC output processing */
3632 uint32_t mpc_out_csc_mode; /* MPC_OUT_CSC_COEF->MPC_OUT_CSC_MODE from output_csc */
3633 uint32_t mpc_out_gamma_mode; /* MPC_OUT_GAMMA_LUT->MPC_OUT_GAMMA_MODE from output_gamma */
3634 } mpc;
3635
3636 /* OPP register programming variables for each pipe */
3637 struct {
3638 /* Display Pattern Generator (DPG) Control - 19 fields from DPG_CONTROL register */
3639 uint32_t dpg_enable; /* DPG_CONTROL->DPG_EN from test_pattern parameter (enable/disable) */
3640
3641 /* Format Control (FMT) - 18 fields from FMT_CONTROL register */
3642 uint32_t fmt_pixel_encoding; /* FMT_CONTROL->FMT_PIXEL_ENCODING from clamping->pixel_encoding */
3643 uint32_t fmt_subsampling_mode; /* FMT_CONTROL->FMT_SUBSAMPLING_MODE from force_chroma_subsampling_1tap */
3644 uint32_t fmt_cbcr_bit_reduction_bypass; /* FMT_CONTROL->FMT_CBCR_BIT_REDUCTION_BYPASS from pixel_encoding bypass control */
3645 uint32_t fmt_stereosync_override; /* FMT_CONTROL->FMT_STEREOSYNC_OVERRIDE from stereo timing override */
3646 uint32_t fmt_spatial_dither_frame_counter_max; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX from fmt_bit_depth->flags */
3647 uint32_t fmt_spatial_dither_frame_counter_bit_swap; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP from dither control */
3648 uint32_t fmt_truncate_enable; /* FMT_CONTROL->FMT_TRUNCATE_EN from fmt_bit_depth->flags.TRUNCATE_ENABLED */
3649 uint32_t fmt_truncate_depth; /* FMT_CONTROL->FMT_TRUNCATE_DEPTH from fmt_bit_depth->flags.TRUNCATE_DEPTH */
3650 uint32_t fmt_truncate_mode; /* FMT_CONTROL->FMT_TRUNCATE_MODE from fmt_bit_depth->flags.TRUNCATE_MODE */
3651 uint32_t fmt_spatial_dither_enable; /* FMT_CONTROL->FMT_SPATIAL_DITHER_EN from fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED */
3652 uint32_t fmt_spatial_dither_mode; /* FMT_CONTROL->FMT_SPATIAL_DITHER_MODE from fmt_bit_depth->flags.SPATIAL_DITHER_MODE */
3653 uint32_t fmt_spatial_dither_depth; /* FMT_CONTROL->FMT_SPATIAL_DITHER_DEPTH from fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH */
3654 uint32_t fmt_temporal_dither_enable; /* FMT_CONTROL->FMT_TEMPORAL_DITHER_EN from fmt_bit_depth->flags.TEMPORAL_DITHER_ENABLED */
3655 uint32_t fmt_clamp_data_enable; /* FMT_CONTROL->FMT_CLAMP_DATA_EN from clamping->clamping_range enable */
3656 uint32_t fmt_clamp_color_format; /* FMT_CONTROL->FMT_CLAMP_COLOR_FORMAT from clamping->color_format */
3657 uint32_t fmt_dynamic_exp_enable; /* FMT_CONTROL->FMT_DYNAMIC_EXP_EN from color_sp/color_dpth/signal */
3658 uint32_t fmt_dynamic_exp_mode; /* FMT_CONTROL->FMT_DYNAMIC_EXP_MODE from color space mode mapping */
3659 uint32_t fmt_bit_depth_control; /* Legacy field - kept for compatibility */
3660
3661 /* OPP Pipe Control - 1 field from OPP_PIPE_CONTROL register */
3662 uint32_t opp_pipe_clock_enable; /* OPP_PIPE_CONTROL->OPP_PIPE_CLOCK_EN from enable parameter (bool) */
3663
3664 /* OPP CRC Control - 3 fields from OPP_PIPE_CRC_CONTROL register */
3665 uint32_t opp_crc_enable; /* OPP_PIPE_CRC_CONTROL->CRC_EN from CRC enable control */
3666 uint32_t opp_crc_select_source; /* OPP_PIPE_CRC_CONTROL->CRC_SELECT_SOURCE from CRC source selection */
3667 uint32_t opp_crc_stereo_cont; /* OPP_PIPE_CRC_CONTROL->CRC_STEREO_CONT from stereo continuous CRC */
3668
3669 /* Output Buffer (OPPBUF) Control - 6 fields from OPPBUF_CONTROL register */
3670 uint32_t oppbuf_active_width; /* OPPBUF_CONTROL->OPPBUF_ACTIVE_WIDTH from oppbuf_params->active_width */
3671 uint32_t oppbuf_pixel_repetition; /* OPPBUF_CONTROL->OPPBUF_PIXEL_REPETITION from oppbuf_params->pixel_repetition */
3672 uint32_t oppbuf_display_segmentation; /* OPPBUF_CONTROL->OPPBUF_DISPLAY_SEGMENTATION from oppbuf_params->mso_segmentation */
3673 uint32_t oppbuf_overlap_pixel_num; /* OPPBUF_CONTROL->OPPBUF_OVERLAP_PIXEL_NUM from oppbuf_params->mso_overlap_pixel_num */
3674 uint32_t oppbuf_3d_vact_space1_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE1_SIZE from 3D timing space1_size */
3675 uint32_t oppbuf_3d_vact_space2_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE2_SIZE from 3D timing space2_size */
3676
3677 /* DSC Forward Config - 3 fields from DSCRM_DSC_FORWARD_CONFIG register */
3678 uint32_t dscrm_dsc_forward_enable; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN from DSC forward enable control */
3679 uint32_t dscrm_dsc_opp_pipe_source; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_OPP_PIPE_SOURCE from opp_pipe parameter */
3680 uint32_t dscrm_dsc_forward_enable_status; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN_STATUS from DSC forward status (read-only) */
3681 } opp[MAX_PIPES];
3682
3683 /* OPTC register programming variables for each pipe */
3684 struct {
3685 uint32_t otg_master_inst;
3686
3687 /* OTG_CONTROL register - 5 fields for OTG control */
3688 uint32_t otg_master_enable; /* OTG_CONTROL->OTG_MASTER_EN from timing enable/disable control */
3689 uint32_t otg_disable_point_cntl; /* OTG_CONTROL->OTG_DISABLE_POINT_CNTL from disable timing control */
3690 uint32_t otg_start_point_cntl; /* OTG_CONTROL->OTG_START_POINT_CNTL from start timing control */
3691 uint32_t otg_field_number_cntl; /* OTG_CONTROL->OTG_FIELD_NUMBER_CNTL from interlace field control */
3692 uint32_t otg_out_mux; /* OTG_CONTROL->OTG_OUT_MUX from output mux selection */
3693
3694 /* OTG Horizontal Timing - 7 fields */
3695 uint32_t otg_h_total; /* OTG_H_TOTAL->OTG_H_TOTAL from dc_crtc_timing->h_total */
3696 uint32_t otg_h_blank_start; /* OTG_H_BLANK_START_END->OTG_H_BLANK_START from dc_crtc_timing->h_front_porch */
3697 uint32_t otg_h_blank_end; /* OTG_H_BLANK_START_END->OTG_H_BLANK_END from dc_crtc_timing->h_addressable_video_pixel_width */
3698 uint32_t otg_h_sync_start; /* OTG_H_SYNC_A->OTG_H_SYNC_A_START from dc_crtc_timing->h_sync_width */
3699 uint32_t otg_h_sync_end; /* OTG_H_SYNC_A->OTG_H_SYNC_A_END from calculated sync end position */
3700 uint32_t otg_h_sync_polarity; /* OTG_H_SYNC_A_CNTL->OTG_H_SYNC_A_POL from dc_crtc_timing->flags.HSYNC_POSITIVE_POLARITY */
3701 uint32_t otg_h_timing_div_mode; /* OTG_H_TIMING_CNTL->OTG_H_TIMING_DIV_MODE from horizontal timing division mode */
3702
3703 /* OTG Vertical Timing - 7 fields */
3704 uint32_t otg_v_total; /* OTG_V_TOTAL->OTG_V_TOTAL from dc_crtc_timing->v_total */
3705 uint32_t otg_v_blank_start; /* OTG_V_BLANK_START_END->OTG_V_BLANK_START from dc_crtc_timing->v_front_porch */
3706 uint32_t otg_v_blank_end; /* OTG_V_BLANK_START_END->OTG_V_BLANK_END from dc_crtc_timing->v_addressable_video_line_width */
3707 uint32_t otg_v_sync_start; /* OTG_V_SYNC_A->OTG_V_SYNC_A_START from dc_crtc_timing->v_sync_width */
3708 uint32_t otg_v_sync_end; /* OTG_V_SYNC_A->OTG_V_SYNC_A_END from calculated sync end position */
3709 uint32_t otg_v_sync_polarity; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_A_POL from dc_crtc_timing->flags.VSYNC_POSITIVE_POLARITY */
3710 uint32_t otg_v_sync_mode; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_MODE from sync mode selection */
3711
3712 /* OTG DRR (Dynamic Refresh Rate) Control - 8 fields */
3713 uint32_t otg_v_total_max; /* OTG_V_TOTAL_MAX->OTG_V_TOTAL_MAX from drr_params->vertical_total_max */
3714 uint32_t otg_v_total_min; /* OTG_V_TOTAL_MIN->OTG_V_TOTAL_MIN from drr_params->vertical_total_min */
3715 uint32_t otg_v_total_mid; /* OTG_V_TOTAL_MID->OTG_V_TOTAL_MID from drr_params->vertical_total_mid */
3716 uint32_t otg_v_total_max_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MAX_SEL from DRR max selection enable */
3717 uint32_t otg_v_total_min_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MIN_SEL from DRR min selection enable */
3718 uint32_t otg_vtotal_mid_replacing_max_en; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_REPLACING_MAX_EN from DRR mid-frame enable */
3719 uint32_t otg_vtotal_mid_frame_num; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_FRAME_NUM from drr_params->vertical_total_mid_frame_num */
3720 uint32_t otg_set_v_total_min_mask; /* OTG_V_TOTAL_CONTROL->OTG_SET_V_TOTAL_MIN_MASK from DRR trigger mask */
3721 uint32_t otg_force_lock_on_event; /* OTG_V_TOTAL_CONTROL->OTG_FORCE_LOCK_ON_EVENT from DRR force lock control */
3722
3723 /* OPTC Data Source and ODM - 6 fields */
3724 uint32_t optc_seg0_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG0_SRC_SEL from opp_id[0] ODM segment 0 source */
3725 uint32_t optc_seg1_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG1_SRC_SEL from opp_id[1] ODM segment 1 source */
3726 uint32_t optc_seg2_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG2_SRC_SEL from opp_id[2] ODM segment 2 source */
3727 uint32_t optc_seg3_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG3_SRC_SEL from opp_id[3] ODM segment 3 source */
3728 uint32_t optc_num_of_input_segment; /* OPTC_DATA_SOURCE_SELECT->OPTC_NUM_OF_INPUT_SEGMENT from opp_cnt-1 number of input segments */
3729 uint32_t optc_mem_sel; /* OPTC_MEMORY_CONFIG->OPTC_MEM_SEL from memory_mask ODM memory selection */
3730
3731 /* OPTC Data Format and DSC - 4 fields */
3732 uint32_t optc_data_format; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DATA_FORMAT from data format selection */
3733 uint32_t optc_dsc_mode; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DSC_MODE from dsc_mode parameter */
3734 uint32_t optc_dsc_bytes_per_pixel; /* OPTC_BYTES_PER_PIXEL->OPTC_DSC_BYTES_PER_PIXEL from dsc_bytes_per_pixel parameter */
3735 uint32_t optc_segment_width; /* OPTC_WIDTH_CONTROL->OPTC_SEGMENT_WIDTH from segment_width parameter */
3736 uint32_t optc_dsc_slice_width; /* OPTC_WIDTH_CONTROL->OPTC_DSC_SLICE_WIDTH from dsc_slice_width parameter */
3737
3738 /* OPTC Clock and Underflow Control - 4 fields */
3739 uint32_t optc_input_pix_clk_en; /* OPTC_INPUT_CLOCK_CONTROL->OPTC_INPUT_PIX_CLK_EN from pixel clock enable */
3740 uint32_t optc_underflow_occurred_status; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_OCCURRED_STATUS from underflow status (read-only) */
3741 uint32_t optc_underflow_clear; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_CLEAR from underflow clear control */
3742 uint32_t otg_clock_enable; /* OTG_CLOCK_CONTROL->OTG_CLOCK_EN from OTG clock enable */
3743 uint32_t otg_clock_gate_dis; /* OTG_CLOCK_CONTROL->OTG_CLOCK_GATE_DIS from clock gate disable */
3744
3745 /* OTG Stereo and 3D Control - 6 fields */
3746 uint32_t otg_stereo_enable; /* OTG_STEREO_CONTROL->OTG_STEREO_EN from stereo enable control */
3747 uint32_t otg_stereo_sync_output_line_num; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_LINE_NUM from timing->stereo_3d_format line num */
3748 uint32_t otg_stereo_sync_output_polarity; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_POLARITY from stereo polarity control */
3749 uint32_t otg_3d_structure_en; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_EN from 3D structure enable */
3750 uint32_t otg_3d_structure_v_update_mode; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_V_UPDATE_MODE from 3D vertical update mode */
3751 uint32_t otg_3d_structure_stereo_sel_ovr; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_STEREO_SEL_OVR from 3D stereo selection override */
3752 uint32_t otg_interlace_enable; /* OTG_INTERLACE_CONTROL->OTG_INTERLACE_ENABLE from dc_crtc_timing->flags.INTERLACE */
3753
3754 /* OTG GSL (Global Sync Lock) Control - 5 fields */
3755 uint32_t otg_gsl0_en; /* OTG_GSL_CONTROL->OTG_GSL0_EN from GSL group 0 enable */
3756 uint32_t otg_gsl1_en; /* OTG_GSL_CONTROL->OTG_GSL1_EN from GSL group 1 enable */
3757 uint32_t otg_gsl2_en; /* OTG_GSL_CONTROL->OTG_GSL2_EN from GSL group 2 enable */
3758 uint32_t otg_gsl_master_en; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_EN from GSL master enable */
3759 uint32_t otg_gsl_master_mode; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_MODE from gsl_params->gsl_master mode */
3760
3761 /* OTG DRR Advanced Control - 4 fields */
3762 uint32_t otg_v_total_last_used_by_drr; /* OTG_DRR_CONTROL->OTG_V_TOTAL_LAST_USED_BY_DRR from last used DRR V_TOTAL (read-only) */
3763 uint32_t otg_drr_trigger_window_start_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_START_X from window_start parameter */
3764 uint32_t otg_drr_trigger_window_end_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_END_X from window_end parameter */
3765 uint32_t otg_drr_v_total_change_limit; /* OTG_DRR_V_TOTAL_CHANGE->OTG_DRR_V_TOTAL_CHANGE_LIMIT from limit parameter */
3766
3767 /* OTG DSC Position Control - 2 fields */
3768 uint32_t otg_dsc_start_position_x; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_X from DSC start X position */
3769 uint32_t otg_dsc_start_position_line_num; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_LINE_NUM from DSC start line number */
3770
3771 /* OTG Double Buffer Control - 2 fields */
3772 uint32_t otg_drr_timing_dbuf_update_mode; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_DRR_TIMING_DBUF_UPDATE_MODE from DRR double buffer mode */
3773 uint32_t otg_blank_data_double_buffer_en; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_BLANK_DATA_DOUBLE_BUFFER_EN from blank data double buffer enable */
3774
3775 /* OTG Vertical Interrupts - 6 fields */
3776 uint32_t otg_vertical_interrupt0_int_enable; /* OTG_VERTICAL_INTERRUPT0_CONTROL->OTG_VERTICAL_INTERRUPT0_INT_ENABLE from interrupt 0 enable */
3777 uint32_t otg_vertical_interrupt0_line_start; /* OTG_VERTICAL_INTERRUPT0_POSITION->OTG_VERTICAL_INTERRUPT0_LINE_START from start_line parameter */
3778 uint32_t otg_vertical_interrupt1_int_enable; /* OTG_VERTICAL_INTERRUPT1_CONTROL->OTG_VERTICAL_INTERRUPT1_INT_ENABLE from interrupt 1 enable */
3779 uint32_t otg_vertical_interrupt1_line_start; /* OTG_VERTICAL_INTERRUPT1_POSITION->OTG_VERTICAL_INTERRUPT1_LINE_START from start_line parameter */
3780 uint32_t otg_vertical_interrupt2_int_enable; /* OTG_VERTICAL_INTERRUPT2_CONTROL->OTG_VERTICAL_INTERRUPT2_INT_ENABLE from interrupt 2 enable */
3781 uint32_t otg_vertical_interrupt2_line_start; /* OTG_VERTICAL_INTERRUPT2_POSITION->OTG_VERTICAL_INTERRUPT2_LINE_START from start_line parameter */
3782
3783 /* OTG Global Sync Parameters - 6 fields */
3784 uint32_t otg_vready_offset; /* OTG_VREADY_PARAM->OTG_VREADY_OFFSET from vready_offset parameter */
3785 uint32_t otg_vstartup_start; /* OTG_VSTARTUP_PARAM->OTG_VSTARTUP_START from vstartup_start parameter */
3786 uint32_t otg_vupdate_offset; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_OFFSET from vupdate_offset parameter */
3787 uint32_t otg_vupdate_width; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_WIDTH from vupdate_width parameter */
3788 uint32_t master_update_lock_vupdate_keepout_start_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET from pstate_keepout start */
3789 uint32_t master_update_lock_vupdate_keepout_end_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET from pstate_keepout end */
3790
3791 /* OTG Manual Trigger Control - 11 fields */
3792 uint32_t otg_triga_source_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_SELECT from trigger A source selection */
3793 uint32_t otg_triga_source_pipe_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_PIPE_SELECT from trigger A pipe selection */
3794 uint32_t otg_triga_rising_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_RISING_EDGE_DETECT_CNTL from trigger A rising edge detect */
3795 uint32_t otg_triga_falling_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_FALLING_EDGE_DETECT_CNTL from trigger A falling edge detect */
3796 uint32_t otg_triga_polarity_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_POLARITY_SELECT from trigger A polarity selection */
3797 uint32_t otg_triga_frequency_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_FREQUENCY_SELECT from trigger A frequency selection */
3798 uint32_t otg_triga_delay; /* OTG_TRIGA_CNTL->OTG_TRIGA_DELAY from trigger A delay */
3799 uint32_t otg_triga_clear; /* OTG_TRIGA_CNTL->OTG_TRIGA_CLEAR from trigger A clear */
3800 uint32_t otg_triga_manual_trig; /* OTG_TRIGA_MANUAL_TRIG->OTG_TRIGA_MANUAL_TRIG from manual trigger A */
3801 uint32_t otg_trigb_source_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_SOURCE_SELECT from trigger B source selection */
3802 uint32_t otg_trigb_polarity_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_POLARITY_SELECT from trigger B polarity selection */
3803 uint32_t otg_trigb_manual_trig; /* OTG_TRIGB_MANUAL_TRIG->OTG_TRIGB_MANUAL_TRIG from manual trigger B */
3804
3805 /* OTG Static Screen and Update Control - 6 fields */
3806 uint32_t otg_static_screen_event_mask; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_EVENT_MASK from event_triggers parameter */
3807 uint32_t otg_static_screen_frame_count; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_FRAME_COUNT from num_frames parameter */
3808 uint32_t master_update_lock; /* OTG_MASTER_UPDATE_LOCK->MASTER_UPDATE_LOCK from update lock control */
3809 uint32_t master_update_mode; /* OTG_MASTER_UPDATE_MODE->MASTER_UPDATE_MODE from update mode selection */
3810 uint32_t otg_force_count_now_mode; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_MODE from force count mode */
3811 uint32_t otg_force_count_now_clear; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_CLEAR from force count clear */
3812
3813 /* VTG Control - 3 fields */
3814 uint32_t vtg0_enable; /* CONTROL->VTG0_ENABLE from VTG enable control */
3815 uint32_t vtg0_fp2; /* CONTROL->VTG0_FP2 from VTG front porch 2 */
3816 uint32_t vtg0_vcount_init; /* CONTROL->VTG0_VCOUNT_INIT from VTG vertical count init */
3817
3818 /* OTG Status (Read-Only) - 12 fields */
3819 uint32_t otg_v_blank; /* OTG_STATUS->OTG_V_BLANK from vertical blank status (read-only) */
3820 uint32_t otg_v_active_disp; /* OTG_STATUS->OTG_V_ACTIVE_DISP from vertical active display (read-only) */
3821 uint32_t otg_frame_count; /* OTG_STATUS_FRAME_COUNT->OTG_FRAME_COUNT from frame count (read-only) */
3822 uint32_t otg_horz_count; /* OTG_STATUS_POSITION->OTG_HORZ_COUNT from horizontal position (read-only) */
3823 uint32_t otg_vert_count; /* OTG_STATUS_POSITION->OTG_VERT_COUNT from vertical position (read-only) */
3824 uint32_t otg_horz_count_hv; /* OTG_STATUS_HV_COUNT->OTG_HORZ_COUNT from horizontal count (read-only) */
3825 uint32_t otg_vert_count_nom; /* OTG_STATUS_HV_COUNT->OTG_VERT_COUNT_NOM from vertical count nominal (read-only) */
3826 uint32_t otg_flip_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_FLIP_PENDING from flip pending status (read-only) */
3827 uint32_t otg_dc_reg_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_DC_REG_UPDATE_PENDING from DC register update pending (read-only) */
3828 uint32_t otg_cursor_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_CURSOR_UPDATE_PENDING from cursor update pending (read-only) */
3829 uint32_t otg_vupdate_keepout_status; /* OTG_PIPE_UPDATE_STATUS->OTG_VUPDATE_KEEPOUT_STATUS from VUPDATE keepout status (read-only) */
3830 } optc[MAX_PIPES];
3831
3832 /* Metadata */
3833 uint32_t active_pipe_count;
3834 uint32_t active_stream_count;
3835 bool state_valid;
3836 };
3837
3838 /**
3839 * dc_capture_register_software_state() - Capture software state for register programming
3840 * @dc: DC context containing current display configuration
3841 * @state: Pointer to dc_register_software_state structure to populate
3842 *
3843 * Extracts all software state variables that are used to program hardware register
3844 * fields across the display driver pipeline. This provides a complete snapshot
3845 * of the software configuration that drives hardware register programming.
3846 *
3847 * The function traverses the DC context and extracts values from:
3848 * - Stream configurations (timing, format, DSC settings)
3849 * - Plane states (surface format, rotation, scaling, cursor)
3850 * - Pipe contexts (resource allocation, blending, viewport)
3851 * - Clock manager (display clocks, DPP clocks, pixel clocks)
3852 * - Resource context (DET buffer allocation, ODM configuration)
3853 *
3854 * This is essential for underflow debugging as it captures the exact software
3855 * state that determines how registers are programmed, allowing analysis of
3856 * whether underflow is caused by incorrect register programming or timing issues.
3857 *
3858 * Return: true if state was successfully captured, false on error
3859 */
3860 bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state);
3861
3862 /**
3863 * dc_get_qos_info() - Retrieve Quality of Service (QoS) information from display core
3864 * @dc: DC context containing current display configuration
3865 * @info: Pointer to dc_qos_info structure to populate with QoS metrics
3866 *
3867 * This function retrieves QoS metrics from the display core that can be used by
3868 * benchmark tools to analyze display system performance. The function may take
3869 * several milliseconds to execute due to hardware measurement requirements.
3870 *
3871 * QoS information includes:
3872 * - Bandwidth bounds (lower limits in Mbps)
3873 * - Latency bounds (upper limits in nanoseconds)
3874 * - Hardware-measured bandwidth metrics (peak/average in Mbps)
3875 * - Hardware-measured latency metrics (maximum/average in nanoseconds)
3876 *
3877 * The function will populate the provided dc_qos_info structure with current
3878 * QoS measurements. If hardware measurement functions are not available for
3879 * the current DCN version, the function returns false with zero'd info structure.
3880 *
3881 * Return: true if QoS information was successfully retrieved, false if measurement
3882 * functions are unavailable or hardware measurements cannot be performed
3883 */
3884 bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info);
3885
3886 /**
3887 * dc_override_memory_bandwidth_request - Override the DCN nominal memory
3888 * bandwidth request sent to PMFW, independent of the current display mode.
3889 * For debug use only.
3890 * @dc: DC instance
3891 * @bw_mbps: requested bandwidth in MB/s; 0 clears the override
3892 *
3893 * Return: capped bandwidth value actually applied (MB/s)
3894 */
3895 unsigned int dc_override_memory_bandwidth_request(
3896 struct dc *dc,
3897 unsigned int bw_mbps);
3898
3899 #endif /* DC_INTERFACE_H_ */
3900