1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 #include "sspl/dc_spl_types.h" 50 51 struct abm_save_restore; 52 53 /* forward declaration */ 54 struct aux_payload; 55 struct set_config_cmd_payload; 56 struct dmub_notification; 57 58 #define DC_VER "3.2.340" 59 60 /** 61 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC 62 */ 63 #define MAX_SURFACES 4 64 /** 65 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW 66 */ 67 #define MAX_PLANES 6 68 #define MAX_STREAMS 6 69 #define MIN_VIEWPORT_SIZE 12 70 #define MAX_NUM_EDP 2 71 #define MAX_SUPPORTED_FORMATS 7 72 73 #define MAX_HOST_ROUTERS_NUM 3 74 #define MAX_DPIA_PER_HOST_ROUTER 3 75 #define MAX_DPIA_NUM (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER) 76 77 /* Display Core Interfaces */ 78 struct dc_versions { 79 const char *dc_ver; 80 struct dmcu_version dmcu_version; 81 }; 82 83 enum dp_protocol_version { 84 DP_VERSION_1_4 = 0, 85 DP_VERSION_2_1, 86 DP_VERSION_UNKNOWN, 87 }; 88 89 enum dc_plane_type { 90 DC_PLANE_TYPE_INVALID, 91 DC_PLANE_TYPE_DCE_RGB, 92 DC_PLANE_TYPE_DCE_UNDERLAY, 93 DC_PLANE_TYPE_DCN_UNIVERSAL, 94 }; 95 96 // Sizes defined as multiples of 64KB 97 enum det_size { 98 DET_SIZE_DEFAULT = 0, 99 DET_SIZE_192KB = 3, 100 DET_SIZE_256KB = 4, 101 DET_SIZE_320KB = 5, 102 DET_SIZE_384KB = 6 103 }; 104 105 106 struct dc_plane_cap { 107 enum dc_plane_type type; 108 uint32_t per_pixel_alpha : 1; 109 struct { 110 uint32_t argb8888 : 1; 111 uint32_t nv12 : 1; 112 uint32_t fp16 : 1; 113 uint32_t p010 : 1; 114 uint32_t ayuv : 1; 115 } pixel_format_support; 116 // max upscaling factor x1000 117 // upscaling factors are always >= 1 118 // for example, 1080p -> 8K is 4.0, or 4000 raw value 119 struct { 120 uint32_t argb8888; 121 uint32_t nv12; 122 uint32_t fp16; 123 } max_upscale_factor; 124 // max downscale factor x1000 125 // downscale factors are always <= 1 126 // for example, 8K -> 1080p is 0.25, or 250 raw value 127 struct { 128 uint32_t argb8888; 129 uint32_t nv12; 130 uint32_t fp16; 131 } max_downscale_factor; 132 // minimal width/height 133 uint32_t min_width; 134 uint32_t min_height; 135 }; 136 137 /** 138 * DOC: color-management-caps 139 * 140 * **Color management caps (DPP and MPC)** 141 * 142 * Modules/color calculates various color operations which are translated to 143 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 144 * DCN1, every new generation comes with fairly major differences in color 145 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 146 * decide mapping to HW block based on logical capabilities. 147 */ 148 149 /** 150 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 151 * @srgb: RGB color space transfer func 152 * @bt2020: BT.2020 transfer func 153 * @gamma2_2: standard gamma 154 * @pq: perceptual quantizer transfer function 155 * @hlg: hybrid log–gamma transfer function 156 */ 157 struct rom_curve_caps { 158 uint16_t srgb : 1; 159 uint16_t bt2020 : 1; 160 uint16_t gamma2_2 : 1; 161 uint16_t pq : 1; 162 uint16_t hlg : 1; 163 }; 164 165 /** 166 * struct dpp_color_caps - color pipeline capabilities for display pipe and 167 * plane blocks 168 * 169 * @dcn_arch: all DCE generations treated the same 170 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 171 * just plain 256-entry lookup 172 * @icsc: input color space conversion 173 * @dgam_ram: programmable degamma LUT 174 * @post_csc: post color space conversion, before gamut remap 175 * @gamma_corr: degamma correction 176 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 177 * with MPC by setting mpc:shared_3d_lut flag 178 * @ogam_ram: programmable out/blend gamma LUT 179 * @ocsc: output color space conversion 180 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 181 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 182 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 183 * 184 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 185 */ 186 struct dpp_color_caps { 187 uint16_t dcn_arch : 1; 188 uint16_t input_lut_shared : 1; 189 uint16_t icsc : 1; 190 uint16_t dgam_ram : 1; 191 uint16_t post_csc : 1; 192 uint16_t gamma_corr : 1; 193 uint16_t hw_3d_lut : 1; 194 uint16_t ogam_ram : 1; 195 uint16_t ocsc : 1; 196 uint16_t dgam_rom_for_yuv : 1; 197 struct rom_curve_caps dgam_rom_caps; 198 struct rom_curve_caps ogam_rom_caps; 199 }; 200 201 /* Below structure is to describe the HW support for mem layout, extend support 202 range to match what OS could handle in the roadmap */ 203 struct lut3d_caps { 204 uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */ 205 struct { 206 uint32_t swizzle_3d_rgb : 1; 207 uint32_t swizzle_3d_bgr : 1; 208 uint32_t linear_1d : 1; 209 } mem_layout_support; 210 struct { 211 uint32_t unorm_12msb : 1; 212 uint32_t unorm_12lsb : 1; 213 uint32_t float_fp1_5_10 : 1; 214 } mem_format_support; 215 struct { 216 uint32_t order_rgba : 1; 217 uint32_t order_bgra : 1; 218 } mem_pixel_order_support; 219 /*< size options are 9, 17, 33, 45, 65 */ 220 struct { 221 uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */ 222 uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */ 223 uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */ 224 uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */ 225 uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */ 226 } lut_dim_caps; 227 }; 228 229 /** 230 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 231 * plane combined blocks 232 * 233 * @gamut_remap: color transformation matrix 234 * @ogam_ram: programmable out gamma LUT 235 * @ocsc: output color space conversion matrix 236 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 237 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 238 * instance 239 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 240 * @mcm_3d_lut_caps: HW support cap for MCM LUT memory 241 * @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory 242 * @preblend: whether color manager supports preblend with MPC 243 */ 244 struct mpc_color_caps { 245 uint16_t gamut_remap : 1; 246 uint16_t ogam_ram : 1; 247 uint16_t ocsc : 1; 248 uint16_t num_3dluts : 3; 249 uint16_t num_rmcm_3dluts : 3; 250 uint16_t shared_3d_lut:1; 251 struct rom_curve_caps ogam_rom_caps; 252 struct lut3d_caps mcm_3d_lut_caps; 253 struct lut3d_caps rmcm_3d_lut_caps; 254 bool preblend; 255 }; 256 257 /** 258 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 259 * @dpp: color pipes caps for DPP 260 * @mpc: color pipes caps for MPC 261 */ 262 struct dc_color_caps { 263 struct dpp_color_caps dpp; 264 struct mpc_color_caps mpc; 265 }; 266 267 struct dc_dmub_caps { 268 bool psr; 269 bool mclk_sw; 270 bool subvp_psr; 271 bool gecc_enable; 272 uint8_t fams_ver; 273 bool aux_backlight_support; 274 }; 275 276 struct dc_scl_caps { 277 bool sharpener_support; 278 }; 279 280 struct dc_caps { 281 uint32_t max_streams; 282 uint32_t max_links; 283 uint32_t max_audios; 284 uint32_t max_slave_planes; 285 uint32_t max_slave_yuv_planes; 286 uint32_t max_slave_rgb_planes; 287 uint32_t max_planes; 288 uint32_t max_downscale_ratio; 289 uint32_t i2c_speed_in_khz; 290 uint32_t i2c_speed_in_khz_hdcp; 291 uint32_t dmdata_alloc_size; 292 unsigned int max_cursor_size; 293 unsigned int max_buffered_cursor_size; 294 unsigned int max_video_width; 295 /* 296 * max video plane width that can be safely assumed to be always 297 * supported by single DPP pipe. 298 */ 299 unsigned int max_optimizable_video_width; 300 unsigned int min_horizontal_blanking_period; 301 int linear_pitch_alignment; 302 bool dcc_const_color; 303 bool dynamic_audio; 304 bool is_apu; 305 bool dual_link_dvi; 306 bool post_blend_color_processing; 307 bool force_dp_tps4_for_cp2520; 308 bool disable_dp_clk_share; 309 bool psp_setup_panel_mode; 310 bool extended_aux_timeout_support; 311 bool dmcub_support; 312 bool zstate_support; 313 bool ips_support; 314 bool ips_v2_support; 315 uint32_t num_of_internal_disp; 316 enum dp_protocol_version max_dp_protocol_version; 317 unsigned int mall_size_per_mem_channel; 318 unsigned int mall_size_total; 319 unsigned int cursor_cache_size; 320 struct dc_plane_cap planes[MAX_PLANES]; 321 struct dc_color_caps color; 322 struct dc_dmub_caps dmub_caps; 323 bool dp_hpo; 324 bool dp_hdmi21_pcon_support; 325 bool edp_dsc_support; 326 bool vbios_lttpr_aware; 327 bool vbios_lttpr_enable; 328 bool fused_io_supported; 329 uint32_t max_otg_num; 330 uint32_t max_cab_allocation_bytes; 331 uint32_t cache_line_size; 332 uint32_t cache_num_ways; 333 uint16_t subvp_fw_processing_delay_us; 334 uint8_t subvp_drr_max_vblank_margin_us; 335 uint16_t subvp_prefetch_end_to_mall_start_us; 336 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 337 uint16_t subvp_pstate_allow_width_us; 338 uint16_t subvp_vertical_int_margin_us; 339 bool seamless_odm; 340 uint32_t max_v_total; 341 bool vtotal_limited_by_fp2; 342 uint32_t max_disp_clock_khz_at_vmin; 343 uint8_t subvp_drr_vblank_start_margin_us; 344 bool cursor_not_scaled; 345 bool dcmode_power_limits_present; 346 bool sequential_ono; 347 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 348 uint32_t dcc_plane_width_limit; 349 struct dc_scl_caps scl_caps; 350 uint8_t num_of_host_routers; 351 uint8_t num_of_dpias_per_host_router; 352 /* limit of the ODM only, could be limited by other factors (like pipe count)*/ 353 uint8_t max_odm_combine_factor; 354 }; 355 356 struct dc_bug_wa { 357 bool no_connect_phy_config; 358 bool dedcn20_305_wa; 359 bool skip_clock_update; 360 bool lt_early_cr_pattern; 361 struct { 362 uint8_t uclk : 1; 363 uint8_t fclk : 1; 364 uint8_t dcfclk : 1; 365 uint8_t dcfclk_ds: 1; 366 } clock_update_disable_mask; 367 bool skip_psr_ips_crtc_disable; 368 }; 369 struct dc_dcc_surface_param { 370 struct dc_size surface_size; 371 enum surface_pixel_format format; 372 unsigned int plane0_pitch; 373 struct dc_size plane1_size; 374 unsigned int plane1_pitch; 375 union { 376 enum swizzle_mode_values swizzle_mode; 377 enum swizzle_mode_addr3_values swizzle_mode_addr3; 378 }; 379 enum dc_scan_direction scan; 380 }; 381 382 struct dc_dcc_setting { 383 unsigned int max_compressed_blk_size; 384 unsigned int max_uncompressed_blk_size; 385 bool independent_64b_blks; 386 //These bitfields to be used starting with DCN 3.0 387 struct { 388 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 389 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 390 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 391 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 392 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 393 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 394 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 395 } dcc_controls; 396 }; 397 398 struct dc_surface_dcc_cap { 399 union { 400 struct { 401 struct dc_dcc_setting rgb; 402 } grph; 403 404 struct { 405 struct dc_dcc_setting luma; 406 struct dc_dcc_setting chroma; 407 } video; 408 }; 409 410 bool capable; 411 bool const_color_support; 412 }; 413 414 struct dc_static_screen_params { 415 struct { 416 bool force_trigger; 417 bool cursor_update; 418 bool surface_update; 419 bool overlay_update; 420 } triggers; 421 unsigned int num_frames; 422 }; 423 424 425 /* Surface update type is used by dc_update_surfaces_and_stream 426 * The update type is determined at the very beginning of the function based 427 * on parameters passed in and decides how much programming (or updating) is 428 * going to be done during the call. 429 * 430 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 431 * logical calculations or hardware register programming. This update MUST be 432 * ISR safe on windows. Currently fast update will only be used to flip surface 433 * address. 434 * 435 * UPDATE_TYPE_MED is used for slower updates which require significant hw 436 * re-programming however do not affect bandwidth consumption or clock 437 * requirements. At present, this is the level at which front end updates 438 * that do not require us to run bw_calcs happen. These are in/out transfer func 439 * updates, viewport offset changes, recout size changes and pixel depth changes. 440 * This update can be done at ISR, but we want to minimize how often this happens. 441 * 442 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 443 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 444 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 445 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 446 * a full update. This cannot be done at ISR level and should be a rare event. 447 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 448 * underscan we don't expect to see this call at all. 449 */ 450 451 enum surface_update_type { 452 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 453 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 454 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 455 }; 456 457 /* Forward declaration*/ 458 struct dc; 459 struct dc_plane_state; 460 struct dc_state; 461 462 struct dc_cap_funcs { 463 bool (*get_dcc_compression_cap)(const struct dc *dc, 464 const struct dc_dcc_surface_param *input, 465 struct dc_surface_dcc_cap *output); 466 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 467 }; 468 469 struct link_training_settings; 470 471 union allow_lttpr_non_transparent_mode { 472 struct { 473 bool DP1_4A : 1; 474 bool DP2_0 : 1; 475 } bits; 476 unsigned char raw; 477 }; 478 479 /* Structure to hold configuration flags set by dm at dc creation. */ 480 struct dc_config { 481 bool gpu_vm_support; 482 bool disable_disp_pll_sharing; 483 bool fbc_support; 484 bool disable_fractional_pwm; 485 bool allow_seamless_boot_optimization; 486 bool seamless_boot_edp_requested; 487 bool edp_not_connected; 488 bool edp_no_power_sequencing; 489 bool force_enum_edp; 490 bool forced_clocks; 491 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 492 bool multi_mon_pp_mclk_switch; 493 bool disable_dmcu; 494 bool enable_4to1MPC; 495 bool enable_windowed_mpo_odm; 496 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 497 uint32_t allow_edp_hotplug_detection; 498 bool skip_riommu_prefetch_wa; 499 bool clamp_min_dcfclk; 500 uint64_t vblank_alignment_dto_params; 501 uint8_t vblank_alignment_max_frame_time_diff; 502 bool is_asymmetric_memory; 503 bool is_single_rank_dimm; 504 bool is_vmin_only_asic; 505 bool use_spl; 506 bool prefer_easf; 507 bool use_pipe_ctx_sync_logic; 508 int smart_mux_version; 509 bool ignore_dpref_ss; 510 bool enable_mipi_converter_optimization; 511 bool use_default_clock_table; 512 bool force_bios_enable_lttpr; 513 uint8_t force_bios_fixed_vs; 514 int sdpif_request_limit_words_per_umc; 515 bool dc_mode_clk_limit_support; 516 bool EnableMinDispClkODM; 517 bool enable_auto_dpm_test_logs; 518 unsigned int disable_ips; 519 unsigned int disable_ips_rcg; 520 unsigned int disable_ips_in_vpb; 521 bool disable_ips_in_dpms_off; 522 bool usb4_bw_alloc_support; 523 bool allow_0_dtb_clk; 524 bool use_assr_psp_message; 525 bool support_edp0_on_dp1; 526 unsigned int enable_fpo_flicker_detection; 527 bool disable_hbr_audio_dp2; 528 bool consolidated_dpia_dp_lt; 529 bool set_pipe_unlock_order; 530 bool enable_dpia_pre_training; 531 bool unify_link_enc_assignment; 532 struct spl_sharpness_range dcn_sharpness_range; 533 struct spl_sharpness_range dcn_override_sharpness_range; 534 }; 535 536 enum visual_confirm { 537 VISUAL_CONFIRM_DISABLE = 0, 538 VISUAL_CONFIRM_SURFACE = 1, 539 VISUAL_CONFIRM_HDR = 2, 540 VISUAL_CONFIRM_MPCTREE = 4, 541 VISUAL_CONFIRM_PSR = 5, 542 VISUAL_CONFIRM_SWAPCHAIN = 6, 543 VISUAL_CONFIRM_FAMS = 7, 544 VISUAL_CONFIRM_SWIZZLE = 9, 545 VISUAL_CONFIRM_SMARTMUX_DGPU = 10, 546 VISUAL_CONFIRM_REPLAY = 12, 547 VISUAL_CONFIRM_SUBVP = 14, 548 VISUAL_CONFIRM_MCLK_SWITCH = 16, 549 VISUAL_CONFIRM_FAMS2 = 19, 550 VISUAL_CONFIRM_HW_CURSOR = 20, 551 VISUAL_CONFIRM_VABC = 21, 552 VISUAL_CONFIRM_DCC = 22, 553 VISUAL_CONFIRM_EXPLICIT = 0x80000000, 554 }; 555 556 enum dc_psr_power_opts { 557 psr_power_opt_invalid = 0x0, 558 psr_power_opt_smu_opt_static_screen = 0x1, 559 psr_power_opt_z10_static_screen = 0x10, 560 psr_power_opt_ds_disable_allow = 0x100, 561 }; 562 563 enum dml_hostvm_override_opts { 564 DML_HOSTVM_NO_OVERRIDE = 0x0, 565 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 566 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 567 }; 568 569 enum dc_replay_power_opts { 570 replay_power_opt_invalid = 0x0, 571 replay_power_opt_smu_opt_static_screen = 0x1, 572 replay_power_opt_z10_static_screen = 0x10, 573 }; 574 575 enum dcc_option { 576 DCC_ENABLE = 0, 577 DCC_DISABLE = 1, 578 DCC_HALF_REQ_DISALBE = 2, 579 }; 580 581 enum in_game_fams_config { 582 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 583 INGAME_FAMS_DISABLE, // disable in-game fams 584 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 585 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 586 }; 587 588 /** 589 * enum pipe_split_policy - Pipe split strategy supported by DCN 590 * 591 * This enum is used to define the pipe split policy supported by DCN. By 592 * default, DC favors MPC_SPLIT_DYNAMIC. 593 */ 594 enum pipe_split_policy { 595 /** 596 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 597 * pipe in order to bring the best trade-off between performance and 598 * power consumption. This is the recommended option. 599 */ 600 MPC_SPLIT_DYNAMIC = 0, 601 602 /** 603 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 604 * try any sort of split optimization. 605 */ 606 MPC_SPLIT_AVOID = 1, 607 608 /** 609 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 610 * optimize the pipe utilization when using a single display; if the 611 * user connects to a second display, DC will avoid pipe split. 612 */ 613 MPC_SPLIT_AVOID_MULT_DISP = 2, 614 }; 615 616 enum wm_report_mode { 617 WM_REPORT_DEFAULT = 0, 618 WM_REPORT_OVERRIDE = 1, 619 }; 620 enum dtm_pstate{ 621 dtm_level_p0 = 0,/*highest voltage*/ 622 dtm_level_p1, 623 dtm_level_p2, 624 dtm_level_p3, 625 dtm_level_p4,/*when active_display_count = 0*/ 626 }; 627 628 enum dcn_pwr_state { 629 DCN_PWR_STATE_UNKNOWN = -1, 630 DCN_PWR_STATE_MISSION_MODE = 0, 631 DCN_PWR_STATE_LOW_POWER = 3, 632 }; 633 634 enum dcn_zstate_support_state { 635 DCN_ZSTATE_SUPPORT_UNKNOWN, 636 DCN_ZSTATE_SUPPORT_ALLOW, 637 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 638 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 639 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 640 DCN_ZSTATE_SUPPORT_DISALLOW, 641 }; 642 643 /* 644 * struct dc_clocks - DC pipe clocks 645 * 646 * For any clocks that may differ per pipe only the max is stored in this 647 * structure 648 */ 649 struct dc_clocks { 650 int dispclk_khz; 651 int actual_dispclk_khz; 652 int dppclk_khz; 653 int actual_dppclk_khz; 654 int disp_dpp_voltage_level_khz; 655 int dcfclk_khz; 656 int socclk_khz; 657 int dcfclk_deep_sleep_khz; 658 int fclk_khz; 659 int phyclk_khz; 660 int dramclk_khz; 661 bool p_state_change_support; 662 enum dcn_zstate_support_state zstate_support; 663 bool dtbclk_en; 664 int ref_dtbclk_khz; 665 bool fclk_p_state_change_support; 666 enum dcn_pwr_state pwr_state; 667 /* 668 * Elements below are not compared for the purposes of 669 * optimization required 670 */ 671 bool prev_p_state_change_support; 672 bool fclk_prev_p_state_change_support; 673 int num_ways; 674 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 675 676 /* 677 * @fw_based_mclk_switching 678 * 679 * DC has a mechanism that leverage the variable refresh rate to switch 680 * memory clock in cases that we have a large latency to achieve the 681 * memory clock change and a short vblank window. DC has some 682 * requirements to enable this feature, and this field describes if the 683 * system support or not such a feature. 684 */ 685 bool fw_based_mclk_switching; 686 bool fw_based_mclk_switching_shut_down; 687 int prev_num_ways; 688 enum dtm_pstate dtm_level; 689 int max_supported_dppclk_khz; 690 int max_supported_dispclk_khz; 691 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 692 int bw_dispclk_khz; 693 int idle_dramclk_khz; 694 int idle_fclk_khz; 695 int subvp_prefetch_dramclk_khz; 696 int subvp_prefetch_fclk_khz; 697 }; 698 699 struct dc_bw_validation_profile { 700 bool enable; 701 702 unsigned long long total_ticks; 703 unsigned long long voltage_level_ticks; 704 unsigned long long watermark_ticks; 705 unsigned long long rq_dlg_ticks; 706 707 unsigned long long total_count; 708 unsigned long long skip_fast_count; 709 unsigned long long skip_pass_count; 710 unsigned long long skip_fail_count; 711 }; 712 713 #define BW_VAL_TRACE_SETUP() \ 714 unsigned long long end_tick = 0; \ 715 unsigned long long voltage_level_tick = 0; \ 716 unsigned long long watermark_tick = 0; \ 717 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 718 dm_get_timestamp(dc->ctx) : 0 719 720 #define BW_VAL_TRACE_COUNT() \ 721 if (dc->debug.bw_val_profile.enable) \ 722 dc->debug.bw_val_profile.total_count++ 723 724 #define BW_VAL_TRACE_SKIP(status) \ 725 if (dc->debug.bw_val_profile.enable) { \ 726 if (!voltage_level_tick) \ 727 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 728 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 729 } 730 731 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 732 if (dc->debug.bw_val_profile.enable) \ 733 voltage_level_tick = dm_get_timestamp(dc->ctx) 734 735 #define BW_VAL_TRACE_END_WATERMARKS() \ 736 if (dc->debug.bw_val_profile.enable) \ 737 watermark_tick = dm_get_timestamp(dc->ctx) 738 739 #define BW_VAL_TRACE_FINISH() \ 740 if (dc->debug.bw_val_profile.enable) { \ 741 end_tick = dm_get_timestamp(dc->ctx); \ 742 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 743 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 744 if (watermark_tick) { \ 745 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 746 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 747 } \ 748 } 749 750 union mem_low_power_enable_options { 751 struct { 752 bool vga: 1; 753 bool i2c: 1; 754 bool dmcu: 1; 755 bool dscl: 1; 756 bool cm: 1; 757 bool mpc: 1; 758 bool optc: 1; 759 bool vpg: 1; 760 bool afmt: 1; 761 } bits; 762 uint32_t u32All; 763 }; 764 765 union root_clock_optimization_options { 766 struct { 767 bool dpp: 1; 768 bool dsc: 1; 769 bool hdmistream: 1; 770 bool hdmichar: 1; 771 bool dpstream: 1; 772 bool symclk32_se: 1; 773 bool symclk32_le: 1; 774 bool symclk_fe: 1; 775 bool physymclk: 1; 776 bool dpiasymclk: 1; 777 uint32_t reserved: 22; 778 } bits; 779 uint32_t u32All; 780 }; 781 782 union fine_grain_clock_gating_enable_options { 783 struct { 784 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 785 bool dchub : 1; /* Display controller hub */ 786 bool dchubbub : 1; 787 bool dpp : 1; /* Display pipes and planes */ 788 bool opp : 1; /* Output pixel processing */ 789 bool optc : 1; /* Output pipe timing combiner */ 790 bool dio : 1; /* Display output */ 791 bool dwb : 1; /* Display writeback */ 792 bool mmhubbub : 1; /* Multimedia hub */ 793 bool dmu : 1; /* Display core management unit */ 794 bool az : 1; /* Azalia */ 795 bool dchvm : 1; 796 bool dsc : 1; /* Display stream compression */ 797 798 uint32_t reserved : 19; 799 } bits; 800 uint32_t u32All; 801 }; 802 803 enum pg_hw_pipe_resources { 804 PG_HUBP = 0, 805 PG_DPP, 806 PG_DSC, 807 PG_MPCC, 808 PG_OPP, 809 PG_OPTC, 810 PG_DPSTREAM, 811 PG_HDMISTREAM, 812 PG_PHYSYMCLK, 813 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 814 }; 815 816 enum pg_hw_resources { 817 PG_DCCG = 0, 818 PG_DCIO, 819 PG_DIO, 820 PG_DCHUBBUB, 821 PG_DCHVM, 822 PG_DWB, 823 PG_HPO, 824 PG_DCOH, 825 PG_HW_RESOURCES_NUM_ELEMENT 826 }; 827 828 struct pg_block_update { 829 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 830 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 831 }; 832 833 union dpia_debug_options { 834 struct { 835 uint32_t disable_dpia:1; /* bit 0 */ 836 uint32_t force_non_lttpr:1; /* bit 1 */ 837 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 838 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 839 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 840 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 841 uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */ 842 uint32_t reserved:25; 843 } bits; 844 uint32_t raw; 845 }; 846 847 /* AUX wake work around options 848 * 0: enable/disable work around 849 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 850 * 15-2: reserved 851 * 31-16: timeout in ms 852 */ 853 union aux_wake_wa_options { 854 struct { 855 uint32_t enable_wa : 1; 856 uint32_t use_default_timeout : 1; 857 uint32_t rsvd: 14; 858 uint32_t timeout_ms : 16; 859 } bits; 860 uint32_t raw; 861 }; 862 863 struct dc_debug_data { 864 uint32_t ltFailCount; 865 uint32_t i2cErrorCount; 866 uint32_t auxErrorCount; 867 }; 868 869 struct dc_phy_addr_space_config { 870 struct { 871 uint64_t start_addr; 872 uint64_t end_addr; 873 uint64_t fb_top; 874 uint64_t fb_offset; 875 uint64_t fb_base; 876 uint64_t agp_top; 877 uint64_t agp_bot; 878 uint64_t agp_base; 879 } system_aperture; 880 881 struct { 882 uint64_t page_table_start_addr; 883 uint64_t page_table_end_addr; 884 uint64_t page_table_base_addr; 885 bool base_addr_is_mc_addr; 886 } gart_config; 887 888 bool valid; 889 bool is_hvm_enabled; 890 uint64_t page_table_default_page_addr; 891 }; 892 893 struct dc_virtual_addr_space_config { 894 uint64_t page_table_base_addr; 895 uint64_t page_table_start_addr; 896 uint64_t page_table_end_addr; 897 uint32_t page_table_block_size_in_bytes; 898 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 899 }; 900 901 struct dc_bounding_box_overrides { 902 int sr_exit_time_ns; 903 int sr_enter_plus_exit_time_ns; 904 int sr_exit_z8_time_ns; 905 int sr_enter_plus_exit_z8_time_ns; 906 int urgent_latency_ns; 907 int percent_of_ideal_drambw; 908 int dram_clock_change_latency_ns; 909 int dummy_clock_change_latency_ns; 910 int fclk_clock_change_latency_ns; 911 /* This forces a hard min on the DCFCLK we use 912 * for DML. Unlike the debug option for forcing 913 * DCFCLK, this override affects watermark calculations 914 */ 915 int min_dcfclk_mhz; 916 }; 917 918 struct dc_state; 919 struct resource_pool; 920 struct dce_hwseq; 921 struct link_service; 922 923 /* 924 * struct dc_debug_options - DC debug struct 925 * 926 * This struct provides a simple mechanism for developers to change some 927 * configurations, enable/disable features, and activate extra debug options. 928 * This can be very handy to narrow down whether some specific feature is 929 * causing an issue or not. 930 */ 931 struct dc_debug_options { 932 bool native422_support; 933 bool disable_dsc; 934 enum visual_confirm visual_confirm; 935 int visual_confirm_rect_height; 936 937 bool sanity_checks; 938 bool max_disp_clk; 939 bool surface_trace; 940 bool clock_trace; 941 bool validation_trace; 942 bool bandwidth_calcs_trace; 943 int max_downscale_src_width; 944 945 /* stutter efficiency related */ 946 bool disable_stutter; 947 bool use_max_lb; 948 enum dcc_option disable_dcc; 949 950 /* 951 * @pipe_split_policy: Define which pipe split policy is used by the 952 * display core. 953 */ 954 enum pipe_split_policy pipe_split_policy; 955 bool force_single_disp_pipe_split; 956 bool voltage_align_fclk; 957 bool disable_min_fclk; 958 959 bool hdcp_lc_force_fw_enable; 960 bool hdcp_lc_enable_sw_fallback; 961 962 bool disable_dfs_bypass; 963 bool disable_dpp_power_gate; 964 bool disable_hubp_power_gate; 965 bool disable_dsc_power_gate; 966 bool disable_optc_power_gate; 967 bool disable_hpo_power_gate; 968 bool disable_io_clk_power_gate; 969 bool disable_mem_power_gate; 970 bool disable_dio_power_gate; 971 int dsc_min_slice_height_override; 972 int dsc_bpp_increment_div; 973 bool disable_pplib_wm_range; 974 enum wm_report_mode pplib_wm_report_mode; 975 unsigned int min_disp_clk_khz; 976 unsigned int min_dpp_clk_khz; 977 unsigned int min_dram_clk_khz; 978 int sr_exit_time_dpm0_ns; 979 int sr_enter_plus_exit_time_dpm0_ns; 980 int sr_exit_time_ns; 981 int sr_enter_plus_exit_time_ns; 982 int sr_exit_z8_time_ns; 983 int sr_enter_plus_exit_z8_time_ns; 984 int urgent_latency_ns; 985 uint32_t underflow_assert_delay_us; 986 int percent_of_ideal_drambw; 987 int dram_clock_change_latency_ns; 988 bool optimized_watermark; 989 int always_scale; 990 bool disable_pplib_clock_request; 991 bool disable_clock_gate; 992 bool disable_mem_low_power; 993 bool pstate_enabled; 994 bool disable_dmcu; 995 bool force_abm_enable; 996 bool disable_stereo_support; 997 bool vsr_support; 998 bool performance_trace; 999 bool az_endpoint_mute_only; 1000 bool always_use_regamma; 1001 bool recovery_enabled; 1002 bool avoid_vbios_exec_table; 1003 bool scl_reset_length10; 1004 bool hdmi20_disable; 1005 bool skip_detection_link_training; 1006 uint32_t edid_read_retry_times; 1007 unsigned int force_odm_combine; //bit vector based on otg inst 1008 unsigned int seamless_boot_odm_combine; 1009 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 1010 int minimum_z8_residency_time; 1011 int minimum_z10_residency_time; 1012 bool disable_z9_mpc; 1013 unsigned int force_fclk_khz; 1014 bool enable_tri_buf; 1015 bool ips_disallow_entry; 1016 bool dmub_offload_enabled; 1017 bool dmcub_emulation; 1018 bool disable_idle_power_optimizations; 1019 unsigned int mall_size_override; 1020 unsigned int mall_additional_timer_percent; 1021 bool mall_error_as_fatal; 1022 bool dmub_command_table; /* for testing only */ 1023 struct dc_bw_validation_profile bw_val_profile; 1024 bool disable_fec; 1025 bool disable_48mhz_pwrdwn; 1026 /* This forces a hard min on the DCFCLK requested to SMU/PP 1027 * watermarks are not affected. 1028 */ 1029 unsigned int force_min_dcfclk_mhz; 1030 int dwb_fi_phase; 1031 bool disable_timing_sync; 1032 bool cm_in_bypass; 1033 int force_clock_mode;/*every mode change.*/ 1034 1035 bool disable_dram_clock_change_vactive_support; 1036 bool validate_dml_output; 1037 bool enable_dmcub_surface_flip; 1038 bool usbc_combo_phy_reset_wa; 1039 bool enable_dram_clock_change_one_display_vactive; 1040 /* TODO - remove once tested */ 1041 bool legacy_dp2_lt; 1042 bool set_mst_en_for_sst; 1043 bool disable_uhbr; 1044 bool force_dp2_lt_fallback_method; 1045 bool ignore_cable_id; 1046 union mem_low_power_enable_options enable_mem_low_power; 1047 union root_clock_optimization_options root_clock_optimization; 1048 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 1049 bool hpo_optimization; 1050 bool force_vblank_alignment; 1051 1052 /* Enable dmub aux for legacy ddc */ 1053 bool enable_dmub_aux_for_legacy_ddc; 1054 bool disable_fams; 1055 enum in_game_fams_config disable_fams_gaming; 1056 /* FEC/PSR1 sequence enable delay in 100us */ 1057 uint8_t fec_enable_delay_in100us; 1058 bool enable_driver_sequence_debug; 1059 enum det_size crb_alloc_policy; 1060 int crb_alloc_policy_min_disp_count; 1061 bool disable_z10; 1062 bool enable_z9_disable_interface; 1063 bool psr_skip_crtc_disable; 1064 uint32_t ips_skip_crtc_disable_mask; 1065 union dpia_debug_options dpia_debug; 1066 bool disable_fixed_vs_aux_timeout_wa; 1067 uint32_t fixed_vs_aux_delay_config_wa; 1068 bool force_disable_subvp; 1069 bool force_subvp_mclk_switch; 1070 bool allow_sw_cursor_fallback; 1071 unsigned int force_subvp_num_ways; 1072 unsigned int force_mall_ss_num_ways; 1073 bool alloc_extra_way_for_cursor; 1074 uint32_t subvp_extra_lines; 1075 bool force_usr_allow; 1076 /* uses value at boot and disables switch */ 1077 bool disable_dtb_ref_clk_switch; 1078 bool extended_blank_optimization; 1079 union aux_wake_wa_options aux_wake_wa; 1080 uint32_t mst_start_top_delay; 1081 uint8_t psr_power_use_phy_fsm; 1082 enum dml_hostvm_override_opts dml_hostvm_override; 1083 bool dml_disallow_alternate_prefetch_modes; 1084 bool use_legacy_soc_bb_mechanism; 1085 bool exit_idle_opt_for_cursor_updates; 1086 bool using_dml2; 1087 bool enable_single_display_2to1_odm_policy; 1088 bool enable_double_buffered_dsc_pg_support; 1089 bool enable_dp_dig_pixel_rate_div_policy; 1090 bool using_dml21; 1091 enum lttpr_mode lttpr_mode_override; 1092 unsigned int dsc_delay_factor_wa_x1000; 1093 unsigned int min_prefetch_in_strobe_ns; 1094 bool disable_unbounded_requesting; 1095 bool dig_fifo_off_in_blank; 1096 bool override_dispclk_programming; 1097 bool otg_crc_db; 1098 bool disallow_dispclk_dppclk_ds; 1099 bool disable_fpo_optimizations; 1100 bool support_eDP1_5; 1101 uint32_t fpo_vactive_margin_us; 1102 bool disable_fpo_vactive; 1103 bool disable_boot_optimizations; 1104 bool override_odm_optimization; 1105 bool minimize_dispclk_using_odm; 1106 bool disable_subvp_high_refresh; 1107 bool disable_dp_plus_plus_wa; 1108 uint32_t fpo_vactive_min_active_margin_us; 1109 uint32_t fpo_vactive_max_blank_us; 1110 bool enable_hpo_pg_support; 1111 bool enable_legacy_fast_update; 1112 bool disable_dc_mode_overwrite; 1113 bool replay_skip_crtc_disabled; 1114 bool ignore_pg;/*do nothing, let pmfw control it*/ 1115 bool psp_disabled_wa; 1116 unsigned int ips2_eval_delay_us; 1117 unsigned int ips2_entry_delay_us; 1118 bool optimize_ips_handshake; 1119 bool disable_dmub_reallow_idle; 1120 bool disable_timeout; 1121 bool disable_extblankadj; 1122 bool enable_idle_reg_checks; 1123 unsigned int static_screen_wait_frames; 1124 uint32_t pwm_freq; 1125 bool force_chroma_subsampling_1tap; 1126 unsigned int dcc_meta_propagation_delay_us; 1127 bool disable_422_left_edge_pixel; 1128 bool dml21_force_pstate_method; 1129 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1130 uint32_t dml21_disable_pstate_method_mask; 1131 union fw_assisted_mclk_switch_version fams_version; 1132 union dmub_fams2_global_feature_config fams2_config; 1133 unsigned int force_cositing; 1134 unsigned int disable_spl; 1135 unsigned int force_easf; 1136 unsigned int force_sharpness; 1137 unsigned int force_sharpness_level; 1138 unsigned int force_lls; 1139 bool notify_dpia_hr_bw; 1140 bool enable_ips_visual_confirm; 1141 unsigned int sharpen_policy; 1142 unsigned int scale_to_sharpness_policy; 1143 bool skip_full_updated_if_possible; 1144 unsigned int enable_oled_edp_power_up_opt; 1145 bool enable_hblank_borrow; 1146 bool force_subvp_df_throttle; 1147 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1148 }; 1149 1150 1151 /* Generic structure that can be used to query properties of DC. More fields 1152 * can be added as required. 1153 */ 1154 struct dc_current_properties { 1155 unsigned int cursor_size_limit; 1156 }; 1157 1158 enum frame_buffer_mode { 1159 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1160 FRAME_BUFFER_MODE_ZFB_ONLY, 1161 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1162 } ; 1163 1164 struct dchub_init_data { 1165 int64_t zfb_phys_addr_base; 1166 int64_t zfb_mc_base_addr; 1167 uint64_t zfb_size_in_byte; 1168 enum frame_buffer_mode fb_mode; 1169 bool dchub_initialzied; 1170 bool dchub_info_valid; 1171 }; 1172 1173 struct dml2_soc_bb; 1174 1175 struct dc_init_data { 1176 struct hw_asic_id asic_id; 1177 void *driver; /* ctx */ 1178 struct cgs_device *cgs_device; 1179 struct dc_bounding_box_overrides bb_overrides; 1180 1181 int num_virtual_links; 1182 /* 1183 * If 'vbios_override' not NULL, it will be called instead 1184 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1185 */ 1186 struct dc_bios *vbios_override; 1187 enum dce_environment dce_environment; 1188 1189 struct dmub_offload_funcs *dmub_if; 1190 struct dc_reg_helper_state *dmub_offload; 1191 1192 struct dc_config flags; 1193 uint64_t log_mask; 1194 1195 struct dpcd_vendor_signature vendor_signature; 1196 bool force_smu_not_present; 1197 /* 1198 * IP offset for run time initializaion of register addresses 1199 * 1200 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1201 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1202 * before them. 1203 */ 1204 uint32_t *dcn_reg_offsets; 1205 uint32_t *nbio_reg_offsets; 1206 uint32_t *clk_reg_offsets; 1207 void *bb_from_dmub; 1208 }; 1209 1210 struct dc_callback_init { 1211 struct cp_psp cp_psp; 1212 }; 1213 1214 struct dc *dc_create(const struct dc_init_data *init_params); 1215 void dc_hardware_init(struct dc *dc); 1216 1217 int dc_get_vmid_use_vector(struct dc *dc); 1218 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1219 /* Returns the number of vmids supported */ 1220 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1221 void dc_init_callbacks(struct dc *dc, 1222 const struct dc_callback_init *init_params); 1223 void dc_deinit_callbacks(struct dc *dc); 1224 void dc_destroy(struct dc **dc); 1225 1226 /* Surface Interfaces */ 1227 1228 enum { 1229 TRANSFER_FUNC_POINTS = 1025 1230 }; 1231 1232 struct dc_hdr_static_metadata { 1233 /* display chromaticities and white point in units of 0.00001 */ 1234 unsigned int chromaticity_green_x; 1235 unsigned int chromaticity_green_y; 1236 unsigned int chromaticity_blue_x; 1237 unsigned int chromaticity_blue_y; 1238 unsigned int chromaticity_red_x; 1239 unsigned int chromaticity_red_y; 1240 unsigned int chromaticity_white_point_x; 1241 unsigned int chromaticity_white_point_y; 1242 1243 uint32_t min_luminance; 1244 uint32_t max_luminance; 1245 uint32_t maximum_content_light_level; 1246 uint32_t maximum_frame_average_light_level; 1247 }; 1248 1249 enum dc_transfer_func_type { 1250 TF_TYPE_PREDEFINED, 1251 TF_TYPE_DISTRIBUTED_POINTS, 1252 TF_TYPE_BYPASS, 1253 TF_TYPE_HWPWL 1254 }; 1255 1256 struct dc_transfer_func_distributed_points { 1257 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1258 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1259 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1260 1261 uint16_t end_exponent; 1262 uint16_t x_point_at_y1_red; 1263 uint16_t x_point_at_y1_green; 1264 uint16_t x_point_at_y1_blue; 1265 }; 1266 1267 enum dc_transfer_func_predefined { 1268 TRANSFER_FUNCTION_SRGB, 1269 TRANSFER_FUNCTION_BT709, 1270 TRANSFER_FUNCTION_PQ, 1271 TRANSFER_FUNCTION_LINEAR, 1272 TRANSFER_FUNCTION_UNITY, 1273 TRANSFER_FUNCTION_HLG, 1274 TRANSFER_FUNCTION_HLG12, 1275 TRANSFER_FUNCTION_GAMMA22, 1276 TRANSFER_FUNCTION_GAMMA24, 1277 TRANSFER_FUNCTION_GAMMA26 1278 }; 1279 1280 1281 struct dc_transfer_func { 1282 struct kref refcount; 1283 enum dc_transfer_func_type type; 1284 enum dc_transfer_func_predefined tf; 1285 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1286 uint32_t sdr_ref_white_level; 1287 union { 1288 struct pwl_params pwl; 1289 struct dc_transfer_func_distributed_points tf_pts; 1290 }; 1291 }; 1292 1293 1294 union dc_3dlut_state { 1295 struct { 1296 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1297 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1298 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1299 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1300 uint32_t mpc_rmu1_mux:4; 1301 uint32_t mpc_rmu2_mux:4; 1302 uint32_t reserved:15; 1303 } bits; 1304 uint32_t raw; 1305 }; 1306 1307 1308 struct dc_rmcm_3dlut { 1309 bool isInUse; 1310 const struct dc_stream_state *stream; 1311 uint8_t protection_bits; 1312 }; 1313 1314 struct dc_3dlut { 1315 struct kref refcount; 1316 struct tetrahedral_params lut_3d; 1317 struct fixed31_32 hdr_multiplier; 1318 union dc_3dlut_state state; 1319 }; 1320 /* 1321 * This structure is filled in by dc_surface_get_status and contains 1322 * the last requested address and the currently active address so the called 1323 * can determine if there are any outstanding flips 1324 */ 1325 struct dc_plane_status { 1326 struct dc_plane_address requested_address; 1327 struct dc_plane_address current_address; 1328 bool is_flip_pending; 1329 bool is_right_eye; 1330 }; 1331 1332 union surface_update_flags { 1333 1334 struct { 1335 uint32_t addr_update:1; 1336 /* Medium updates */ 1337 uint32_t dcc_change:1; 1338 uint32_t color_space_change:1; 1339 uint32_t horizontal_mirror_change:1; 1340 uint32_t per_pixel_alpha_change:1; 1341 uint32_t global_alpha_change:1; 1342 uint32_t hdr_mult:1; 1343 uint32_t rotation_change:1; 1344 uint32_t swizzle_change:1; 1345 uint32_t scaling_change:1; 1346 uint32_t position_change:1; 1347 uint32_t in_transfer_func_change:1; 1348 uint32_t input_csc_change:1; 1349 uint32_t coeff_reduction_change:1; 1350 uint32_t output_tf_change:1; 1351 uint32_t pixel_format_change:1; 1352 uint32_t plane_size_change:1; 1353 uint32_t gamut_remap_change:1; 1354 1355 /* Full updates */ 1356 uint32_t new_plane:1; 1357 uint32_t bpp_change:1; 1358 uint32_t gamma_change:1; 1359 uint32_t bandwidth_change:1; 1360 uint32_t clock_change:1; 1361 uint32_t stereo_format_change:1; 1362 uint32_t lut_3d:1; 1363 uint32_t tmz_changed:1; 1364 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1365 uint32_t full_update:1; 1366 uint32_t sdr_white_level_nits:1; 1367 } bits; 1368 1369 uint32_t raw; 1370 }; 1371 1372 #define DC_REMOVE_PLANE_POINTERS 1 1373 1374 struct dc_plane_state { 1375 struct dc_plane_address address; 1376 struct dc_plane_flip_time time; 1377 bool triplebuffer_flips; 1378 struct scaling_taps scaling_quality; 1379 struct rect src_rect; 1380 struct rect dst_rect; 1381 struct rect clip_rect; 1382 1383 struct plane_size plane_size; 1384 struct dc_tiling_info tiling_info; 1385 1386 struct dc_plane_dcc_param dcc; 1387 1388 struct dc_gamma gamma_correction; 1389 struct dc_transfer_func in_transfer_func; 1390 struct dc_bias_and_scale bias_and_scale; 1391 struct dc_csc_transform input_csc_color_matrix; 1392 struct fixed31_32 coeff_reduction_factor; 1393 struct fixed31_32 hdr_mult; 1394 struct colorspace_transform gamut_remap_matrix; 1395 1396 // TODO: No longer used, remove 1397 struct dc_hdr_static_metadata hdr_static_ctx; 1398 1399 enum dc_color_space color_space; 1400 1401 struct dc_3dlut lut3d_func; 1402 struct dc_transfer_func in_shaper_func; 1403 struct dc_transfer_func blend_tf; 1404 1405 struct dc_transfer_func *gamcor_tf; 1406 enum surface_pixel_format format; 1407 enum dc_rotation_angle rotation; 1408 enum plane_stereo_format stereo_format; 1409 1410 bool is_tiling_rotated; 1411 bool per_pixel_alpha; 1412 bool pre_multiplied_alpha; 1413 bool global_alpha; 1414 int global_alpha_value; 1415 bool visible; 1416 bool flip_immediate; 1417 bool horizontal_mirror; 1418 int layer_index; 1419 1420 union surface_update_flags update_flags; 1421 bool flip_int_enabled; 1422 bool skip_manual_trigger; 1423 1424 /* private to DC core */ 1425 struct dc_plane_status status; 1426 struct dc_context *ctx; 1427 1428 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1429 bool force_full_update; 1430 1431 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1432 1433 /* private to dc_surface.c */ 1434 enum dc_irq_source irq_source; 1435 struct kref refcount; 1436 struct tg_color visual_confirm_color; 1437 1438 bool is_statically_allocated; 1439 enum chroma_cositing cositing; 1440 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1441 bool mcm_lut1d_enable; 1442 struct dc_cm2_func_luts mcm_luts; 1443 bool lut_bank_a; 1444 enum mpcc_movable_cm_location mcm_location; 1445 struct dc_csc_transform cursor_csc_color_matrix; 1446 bool adaptive_sharpness_en; 1447 int adaptive_sharpness_policy; 1448 int sharpness_level; 1449 enum linear_light_scaling linear_light_scaling; 1450 unsigned int sdr_white_level_nits; 1451 struct spl_sharpness_range sharpness_range; 1452 enum sharpness_range_source sharpness_source; 1453 }; 1454 1455 struct dc_plane_info { 1456 struct plane_size plane_size; 1457 struct dc_tiling_info tiling_info; 1458 struct dc_plane_dcc_param dcc; 1459 enum surface_pixel_format format; 1460 enum dc_rotation_angle rotation; 1461 enum plane_stereo_format stereo_format; 1462 enum dc_color_space color_space; 1463 bool horizontal_mirror; 1464 bool visible; 1465 bool per_pixel_alpha; 1466 bool pre_multiplied_alpha; 1467 bool global_alpha; 1468 int global_alpha_value; 1469 bool input_csc_enabled; 1470 int layer_index; 1471 enum chroma_cositing cositing; 1472 }; 1473 1474 #include "dc_stream.h" 1475 1476 struct dc_scratch_space { 1477 /* used to temporarily backup plane states of a stream during 1478 * dc update. The reason is that plane states are overwritten 1479 * with surface updates in dc update. Once they are overwritten 1480 * current state is no longer valid. We want to temporarily 1481 * store current value in plane states so we can still recover 1482 * a valid current state during dc update. 1483 */ 1484 struct dc_plane_state plane_states[MAX_SURFACES]; 1485 1486 struct dc_stream_state stream_state; 1487 }; 1488 1489 /* 1490 * A link contains one or more sinks and their connected status. 1491 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1492 */ 1493 struct dc_link { 1494 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1495 unsigned int sink_count; 1496 struct dc_sink *local_sink; 1497 unsigned int link_index; 1498 enum dc_connection_type type; 1499 enum signal_type connector_signal; 1500 enum dc_irq_source irq_source_hpd; 1501 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1502 enum dc_irq_source irq_source_read_request;/* Read Request */ 1503 1504 bool is_hpd_filter_disabled; 1505 bool dp_ss_off; 1506 1507 /** 1508 * @link_state_valid: 1509 * 1510 * If there is no link and local sink, this variable should be set to 1511 * false. Otherwise, it should be set to true; usually, the function 1512 * core_link_enable_stream sets this field to true. 1513 */ 1514 bool link_state_valid; 1515 bool aux_access_disabled; 1516 bool sync_lt_in_progress; 1517 bool skip_stream_reenable; 1518 bool is_internal_display; 1519 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1520 bool is_dig_mapping_flexible; 1521 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1522 bool is_hpd_pending; /* Indicates a new received hpd */ 1523 1524 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1525 * for every link training. This is incompatible with DP LL compliance automation, 1526 * which expects the same link settings to be used every retry on a link loss. 1527 * This flag is used to skip the fallback when link loss occurs during automation. 1528 */ 1529 bool skip_fallback_on_link_loss; 1530 1531 bool edp_sink_present; 1532 1533 struct dp_trace dp_trace; 1534 1535 /* caps is the same as reported_link_cap. link_traing use 1536 * reported_link_cap. Will clean up. TODO 1537 */ 1538 struct dc_link_settings reported_link_cap; 1539 struct dc_link_settings verified_link_cap; 1540 struct dc_link_settings cur_link_settings; 1541 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1542 struct dc_link_settings preferred_link_setting; 1543 /* preferred_training_settings are override values that 1544 * come from DM. DM is responsible for the memory 1545 * management of the override pointers. 1546 */ 1547 struct dc_link_training_overrides preferred_training_settings; 1548 struct dp_audio_test_data audio_test_data; 1549 1550 uint8_t ddc_hw_inst; 1551 1552 uint8_t hpd_src; 1553 1554 uint8_t link_enc_hw_inst; 1555 /* DIG link encoder ID. Used as index in link encoder resource pool. 1556 * For links with fixed mapping to DIG, this is not changed after dc_link 1557 * object creation. 1558 */ 1559 enum engine_id eng_id; 1560 enum engine_id dpia_preferred_eng_id; 1561 1562 bool test_pattern_enabled; 1563 /* Pending/Current test pattern are only used to perform and track 1564 * FIXED_VS retimer test pattern/lane adjustment override state. 1565 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1566 * to perform specific lane adjust overrides before setting certain 1567 * PHY test patterns. In cases when lane adjust and set test pattern 1568 * calls are not performed atomically (i.e. performing link training), 1569 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1570 * and current_test_pattern will contain required context for any future 1571 * set pattern/set lane adjust to transition between override state(s). 1572 * */ 1573 enum dp_test_pattern current_test_pattern; 1574 enum dp_test_pattern pending_test_pattern; 1575 1576 union compliance_test_state compliance_test_state; 1577 1578 void *priv; 1579 1580 struct ddc_service *ddc; 1581 1582 enum dp_panel_mode panel_mode; 1583 bool aux_mode; 1584 1585 /* Private to DC core */ 1586 1587 const struct dc *dc; 1588 1589 struct dc_context *ctx; 1590 1591 struct panel_cntl *panel_cntl; 1592 struct link_encoder *link_enc; 1593 struct graphics_object_id link_id; 1594 /* Endpoint type distinguishes display endpoints which do not have entries 1595 * in the BIOS connector table from those that do. Helps when tracking link 1596 * encoder to display endpoint assignments. 1597 */ 1598 enum display_endpoint_type ep_type; 1599 union ddi_channel_mapping ddi_channel_mapping; 1600 struct connector_device_tag_info device_tag; 1601 struct dpcd_caps dpcd_caps; 1602 uint32_t dongle_max_pix_clk; 1603 unsigned short chip_caps; 1604 unsigned int dpcd_sink_count; 1605 struct hdcp_caps hdcp_caps; 1606 enum edp_revision edp_revision; 1607 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1608 1609 struct psr_settings psr_settings; 1610 struct replay_settings replay_settings; 1611 1612 /* Drive settings read from integrated info table */ 1613 struct dc_lane_settings bios_forced_drive_settings; 1614 1615 /* Vendor specific LTTPR workaround variables */ 1616 uint8_t vendor_specific_lttpr_link_rate_wa; 1617 bool apply_vendor_specific_lttpr_link_rate_wa; 1618 1619 /* MST record stream using this link */ 1620 struct link_flags { 1621 bool dp_keep_receiver_powered; 1622 bool dp_skip_DID2; 1623 bool dp_skip_reset_segment; 1624 bool dp_skip_fs_144hz; 1625 bool dp_mot_reset_segment; 1626 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1627 bool dpia_mst_dsc_always_on; 1628 /* Forced DPIA into TBT3 compatibility mode. */ 1629 bool dpia_forced_tbt3_mode; 1630 bool dongle_mode_timing_override; 1631 bool blank_stream_on_ocs_change; 1632 bool read_dpcd204h_on_irq_hpd; 1633 bool force_dp_ffe_preset; 1634 bool skip_phy_ssc_reduction; 1635 } wa_flags; 1636 union dc_dp_ffe_preset forced_dp_ffe_preset; 1637 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1638 1639 struct dc_link_status link_status; 1640 struct dprx_states dprx_states; 1641 1642 struct gpio *hpd_gpio; 1643 enum dc_link_fec_state fec_state; 1644 bool is_dds; 1645 bool is_display_mux_present; 1646 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1647 1648 struct dc_panel_config panel_config; 1649 struct phy_state phy_state; 1650 uint32_t phy_transition_bitmask; 1651 // BW ALLOCATON USB4 ONLY 1652 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1653 bool skip_implict_edp_power_control; 1654 enum backlight_control_type backlight_control_type; 1655 }; 1656 1657 struct dc { 1658 struct dc_debug_options debug; 1659 struct dc_versions versions; 1660 struct dc_caps caps; 1661 struct dc_cap_funcs cap_funcs; 1662 struct dc_config config; 1663 struct dc_bounding_box_overrides bb_overrides; 1664 struct dc_bug_wa work_arounds; 1665 struct dc_context *ctx; 1666 struct dc_phy_addr_space_config vm_pa_config; 1667 1668 uint8_t link_count; 1669 struct dc_link *links[MAX_LINKS]; 1670 uint8_t lowest_dpia_link_index; 1671 struct link_service *link_srv; 1672 1673 struct dc_state *current_state; 1674 struct resource_pool *res_pool; 1675 1676 struct clk_mgr *clk_mgr; 1677 1678 /* Display Engine Clock levels */ 1679 struct dm_pp_clock_levels sclk_lvls; 1680 1681 /* Inputs into BW and WM calculations. */ 1682 struct bw_calcs_dceip *bw_dceip; 1683 struct bw_calcs_vbios *bw_vbios; 1684 struct dcn_soc_bounding_box *dcn_soc; 1685 struct dcn_ip_params *dcn_ip; 1686 struct display_mode_lib dml; 1687 1688 /* HW functions */ 1689 struct hw_sequencer_funcs hwss; 1690 struct dce_hwseq *hwseq; 1691 1692 /* Require to optimize clocks and bandwidth for added/removed planes */ 1693 bool optimized_required; 1694 bool wm_optimized_required; 1695 bool idle_optimizations_allowed; 1696 bool enable_c20_dtm_b0; 1697 1698 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1699 1700 /* For eDP to know the switching state of SmartMux */ 1701 bool is_switch_in_progress_orig; 1702 bool is_switch_in_progress_dest; 1703 1704 /* FBC compressor */ 1705 struct compressor *fbc_compressor; 1706 1707 struct dc_debug_data debug_data; 1708 struct dpcd_vendor_signature vendor_signature; 1709 1710 const char *build_id; 1711 struct vm_helper *vm_helper; 1712 1713 uint32_t *dcn_reg_offsets; 1714 uint32_t *nbio_reg_offsets; 1715 uint32_t *clk_reg_offsets; 1716 1717 /* Scratch memory */ 1718 struct { 1719 struct { 1720 /* 1721 * For matching clock_limits table in driver with table 1722 * from PMFW. 1723 */ 1724 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1725 } update_bw_bounding_box; 1726 struct dc_scratch_space current_state; 1727 struct dc_scratch_space new_state; 1728 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 1729 struct dc_link temp_link; 1730 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 1731 } scratch; 1732 1733 struct dml2_configuration_options dml2_options; 1734 struct dml2_configuration_options dml2_dc_power_options; 1735 enum dc_acpi_cm_power_state power_state; 1736 1737 }; 1738 1739 struct dc_scaling_info { 1740 struct rect src_rect; 1741 struct rect dst_rect; 1742 struct rect clip_rect; 1743 struct scaling_taps scaling_quality; 1744 }; 1745 1746 struct dc_fast_update { 1747 const struct dc_flip_addrs *flip_addr; 1748 const struct dc_gamma *gamma; 1749 const struct colorspace_transform *gamut_remap_matrix; 1750 const struct dc_csc_transform *input_csc_color_matrix; 1751 const struct fixed31_32 *coeff_reduction_factor; 1752 struct dc_transfer_func *out_transfer_func; 1753 struct dc_csc_transform *output_csc_transform; 1754 const struct dc_csc_transform *cursor_csc_color_matrix; 1755 }; 1756 1757 struct dc_surface_update { 1758 struct dc_plane_state *surface; 1759 1760 /* isr safe update parameters. null means no updates */ 1761 const struct dc_flip_addrs *flip_addr; 1762 const struct dc_plane_info *plane_info; 1763 const struct dc_scaling_info *scaling_info; 1764 struct fixed31_32 hdr_mult; 1765 /* following updates require alloc/sleep/spin that is not isr safe, 1766 * null means no updates 1767 */ 1768 const struct dc_gamma *gamma; 1769 const struct dc_transfer_func *in_transfer_func; 1770 1771 const struct dc_csc_transform *input_csc_color_matrix; 1772 const struct fixed31_32 *coeff_reduction_factor; 1773 const struct dc_transfer_func *func_shaper; 1774 const struct dc_3dlut *lut3d_func; 1775 const struct dc_transfer_func *blend_tf; 1776 const struct colorspace_transform *gamut_remap_matrix; 1777 /* 1778 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT) 1779 * 1780 * change cm2_params.component_settings: Full update 1781 * change cm2_params.cm2_luts: Fast update 1782 */ 1783 const struct dc_cm2_parameters *cm2_params; 1784 const struct dc_csc_transform *cursor_csc_color_matrix; 1785 unsigned int sdr_white_level_nits; 1786 struct dc_bias_and_scale bias_and_scale; 1787 }; 1788 1789 /* 1790 * Create a new surface with default parameters; 1791 */ 1792 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1793 void dc_gamma_release(struct dc_gamma **dc_gamma); 1794 struct dc_gamma *dc_create_gamma(void); 1795 1796 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1797 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1798 struct dc_transfer_func *dc_create_transfer_func(void); 1799 1800 struct dc_3dlut *dc_create_3dlut_func(void); 1801 void dc_3dlut_func_release(struct dc_3dlut *lut); 1802 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1803 1804 void dc_post_update_surfaces_to_stream( 1805 struct dc *dc); 1806 1807 #include "dc_stream.h" 1808 1809 /** 1810 * struct dc_validation_set - Struct to store surface/stream associations for validation 1811 */ 1812 struct dc_validation_set { 1813 /** 1814 * @stream: Stream state properties 1815 */ 1816 struct dc_stream_state *stream; 1817 1818 /** 1819 * @plane_states: Surface state 1820 */ 1821 struct dc_plane_state *plane_states[MAX_SURFACES]; 1822 1823 /** 1824 * @plane_count: Total of active planes 1825 */ 1826 uint8_t plane_count; 1827 }; 1828 1829 bool dc_validate_boot_timing(const struct dc *dc, 1830 const struct dc_sink *sink, 1831 struct dc_crtc_timing *crtc_timing); 1832 1833 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1834 1835 enum dc_status dc_validate_with_context(struct dc *dc, 1836 const struct dc_validation_set set[], 1837 int set_count, 1838 struct dc_state *context, 1839 enum dc_validate_mode validate_mode); 1840 1841 bool dc_set_generic_gpio_for_stereo(bool enable, 1842 struct gpio_service *gpio_service); 1843 1844 enum dc_status dc_validate_global_state( 1845 struct dc *dc, 1846 struct dc_state *new_ctx, 1847 enum dc_validate_mode validate_mode); 1848 1849 bool dc_acquire_release_mpc_3dlut( 1850 struct dc *dc, bool acquire, 1851 struct dc_stream_state *stream, 1852 struct dc_3dlut **lut, 1853 struct dc_transfer_func **shaper); 1854 1855 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1856 void get_audio_check(struct audio_info *aud_modes, 1857 struct audio_check *aud_chk); 1858 1859 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 1860 void populate_fast_updates(struct dc_fast_update *fast_update, 1861 struct dc_surface_update *srf_updates, 1862 int surface_count, 1863 struct dc_stream_update *stream_update); 1864 /* 1865 * Set up streams and links associated to drive sinks 1866 * The streams parameter is an absolute set of all active streams. 1867 * 1868 * After this call: 1869 * Phy, Encoder, Timing Generator are programmed and enabled. 1870 * New streams are enabled with blank stream; no memory read. 1871 */ 1872 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 1873 1874 1875 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1876 struct dc_stream_state *stream, 1877 int mpcc_inst); 1878 1879 1880 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1881 1882 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1883 1884 /* The function returns minimum bandwidth required to drive a given timing 1885 * return - minimum required timing bandwidth in kbps. 1886 */ 1887 uint32_t dc_bandwidth_in_kbps_from_timing( 1888 const struct dc_crtc_timing *timing, 1889 const enum dc_link_encoding_format link_encoding); 1890 1891 /* Link Interfaces */ 1892 /* Return an enumerated dc_link. 1893 * dc_link order is constant and determined at 1894 * boot time. They cannot be created or destroyed. 1895 * Use dc_get_caps() to get number of links. 1896 */ 1897 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1898 1899 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1900 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1901 const struct dc_link *link, 1902 unsigned int *inst_out); 1903 1904 /* Return an array of link pointers to edp links. */ 1905 void dc_get_edp_links(const struct dc *dc, 1906 struct dc_link **edp_links, 1907 int *edp_num); 1908 1909 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1910 bool powerOn); 1911 1912 /* The function initiates detection handshake over the given link. It first 1913 * determines if there are display connections over the link. If so it initiates 1914 * detection protocols supported by the connected receiver device. The function 1915 * contains protocol specific handshake sequences which are sometimes mandatory 1916 * to establish a proper connection between TX and RX. So it is always 1917 * recommended to call this function as the first link operation upon HPD event 1918 * or power up event. Upon completion, the function will update link structure 1919 * in place based on latest RX capabilities. The function may also cause dpms 1920 * to be reset to off for all currently enabled streams to the link. It is DM's 1921 * responsibility to serialize detection and DPMS updates. 1922 * 1923 * @reason - Indicate which event triggers this detection. dc may customize 1924 * detection flow depending on the triggering events. 1925 * return false - if detection is not fully completed. This could happen when 1926 * there is an unrecoverable error during detection or detection is partially 1927 * completed (detection has been delegated to dm mst manager ie. 1928 * link->connection_type == dc_connection_mst_branch when returning false). 1929 * return true - detection is completed, link has been fully updated with latest 1930 * detection result. 1931 */ 1932 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1933 1934 struct dc_sink_init_data; 1935 1936 /* When link connection type is dc_connection_mst_branch, remote sink can be 1937 * added to the link. The interface creates a remote sink and associates it with 1938 * current link. The sink will be retained by link until remove remote sink is 1939 * called. 1940 * 1941 * @dc_link - link the remote sink will be added to. 1942 * @edid - byte array of EDID raw data. 1943 * @len - size of the edid in byte 1944 * @init_data - 1945 */ 1946 struct dc_sink *dc_link_add_remote_sink( 1947 struct dc_link *dc_link, 1948 const uint8_t *edid, 1949 int len, 1950 struct dc_sink_init_data *init_data); 1951 1952 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1953 * @link - link the sink should be removed from 1954 * @sink - sink to be removed. 1955 */ 1956 void dc_link_remove_remote_sink( 1957 struct dc_link *link, 1958 struct dc_sink *sink); 1959 1960 /* Enable HPD interrupt handler for a given link */ 1961 void dc_link_enable_hpd(const struct dc_link *link); 1962 1963 /* Disable HPD interrupt handler for a given link */ 1964 void dc_link_disable_hpd(const struct dc_link *link); 1965 1966 /* determine if there is a sink connected to the link 1967 * 1968 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1969 * return - false if an unexpected error occurs, true otherwise. 1970 * 1971 * NOTE: This function doesn't detect downstream sink connections i.e 1972 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1973 * return dc_connection_single if the branch device is connected despite of 1974 * downstream sink's connection status. 1975 */ 1976 bool dc_link_detect_connection_type(struct dc_link *link, 1977 enum dc_connection_type *type); 1978 1979 /* query current hpd pin value 1980 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1981 * 1982 */ 1983 bool dc_link_get_hpd_state(struct dc_link *link); 1984 1985 /* Getter for cached link status from given link */ 1986 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1987 1988 /* enable/disable hardware HPD filter. 1989 * 1990 * @link - The link the HPD pin is associated with. 1991 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1992 * handler once after no HPD change has been detected within dc default HPD 1993 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1994 * pulses within default HPD interval, no HPD event will be received until HPD 1995 * toggles have stopped. Then HPD event will be queued to irq handler once after 1996 * dc default HPD filtering interval since last HPD event. 1997 * 1998 * @enable = false - disable hardware HPD filter. HPD event will be queued 1999 * immediately to irq handler after no HPD change has been detected within 2000 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 2001 */ 2002 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 2003 2004 /* submit i2c read/write payloads through ddc channel 2005 * @link_index - index to a link with ddc in i2c mode 2006 * @cmd - i2c command structure 2007 * return - true if success, false otherwise. 2008 */ 2009 bool dc_submit_i2c( 2010 struct dc *dc, 2011 uint32_t link_index, 2012 struct i2c_command *cmd); 2013 2014 /* submit i2c read/write payloads through oem channel 2015 * @link_index - index to a link with ddc in i2c mode 2016 * @cmd - i2c command structure 2017 * return - true if success, false otherwise. 2018 */ 2019 bool dc_submit_i2c_oem( 2020 struct dc *dc, 2021 struct i2c_command *cmd); 2022 2023 enum aux_return_code_type; 2024 /* Attempt to transfer the given aux payload. This function does not perform 2025 * retries or handle error states. The reply is returned in the payload->reply 2026 * and the result through operation_result. Returns the number of bytes 2027 * transferred,or -1 on a failure. 2028 */ 2029 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 2030 struct aux_payload *payload, 2031 enum aux_return_code_type *operation_result); 2032 2033 struct ddc_service * 2034 dc_get_oem_i2c_device(struct dc *dc); 2035 2036 bool dc_is_oem_i2c_device_present( 2037 struct dc *dc, 2038 size_t slave_address 2039 ); 2040 2041 /* return true if the connected receiver supports the hdcp version */ 2042 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 2043 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 2044 2045 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 2046 * 2047 * TODO - When defer_handling is true the function will have a different purpose. 2048 * It no longer does complete hpd rx irq handling. We should create a separate 2049 * interface specifically for this case. 2050 * 2051 * Return: 2052 * true - Downstream port status changed. DM should call DC to do the 2053 * detection. 2054 * false - no change in Downstream port status. No further action required 2055 * from DM. 2056 */ 2057 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 2058 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 2059 bool defer_handling, bool *has_left_work); 2060 /* handle DP specs define test automation sequence*/ 2061 void dc_link_dp_handle_automated_test(struct dc_link *link); 2062 2063 /* handle DP Link loss sequence and try to recover RX link loss with best 2064 * effort 2065 */ 2066 void dc_link_dp_handle_link_loss(struct dc_link *link); 2067 2068 /* Determine if hpd rx irq should be handled or ignored 2069 * return true - hpd rx irq should be handled. 2070 * return false - it is safe to ignore hpd rx irq event 2071 */ 2072 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 2073 2074 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 2075 * @link - link the hpd irq data associated with 2076 * @hpd_irq_dpcd_data - input hpd irq data 2077 * return - true if hpd irq data indicates a link lost 2078 */ 2079 bool dc_link_check_link_loss_status(struct dc_link *link, 2080 union hpd_irq_data *hpd_irq_dpcd_data); 2081 2082 /* Read hpd rx irq data from a given link 2083 * @link - link where the hpd irq data should be read from 2084 * @irq_data - output hpd irq data 2085 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2086 * read has failed. 2087 */ 2088 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2089 struct dc_link *link, 2090 union hpd_irq_data *irq_data); 2091 2092 /* The function clears recorded DP RX states in the link. DM should call this 2093 * function when it is resuming from S3 power state to previously connected links. 2094 * 2095 * TODO - in the future we should consider to expand link resume interface to 2096 * support clearing previous rx states. So we don't have to rely on dm to call 2097 * this interface explicitly. 2098 */ 2099 void dc_link_clear_dprx_states(struct dc_link *link); 2100 2101 /* Destruct the mst topology of the link and reset the allocated payload table 2102 * 2103 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2104 * still wants to reset MST topology on an unplug event */ 2105 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2106 2107 /* The function calculates effective DP link bandwidth when a given link is 2108 * using the given link settings. 2109 * 2110 * return - total effective link bandwidth in kbps. 2111 */ 2112 uint32_t dc_link_bandwidth_kbps( 2113 const struct dc_link *link, 2114 const struct dc_link_settings *link_setting); 2115 2116 struct dp_audio_bandwidth_params { 2117 const struct dc_crtc_timing *crtc_timing; 2118 enum dp_link_encoding link_encoding; 2119 uint32_t channel_count; 2120 uint32_t sample_rate_hz; 2121 }; 2122 2123 /* The function calculates the minimum size of hblank (in bytes) needed to 2124 * support the specified channel count and sample rate combination, given the 2125 * link encoding and timing to be used. This calculation is not supported 2126 * for 8b/10b SST. 2127 * 2128 * return - min hblank size in bytes, 0 if 8b/10b SST. 2129 */ 2130 uint32_t dc_link_required_hblank_size_bytes( 2131 const struct dc_link *link, 2132 struct dp_audio_bandwidth_params *audio_params); 2133 2134 /* The function takes a snapshot of current link resource allocation state 2135 * @dc: pointer to dc of the dm calling this 2136 * @map: a dc link resource snapshot defined internally to dc. 2137 * 2138 * DM needs to capture a snapshot of current link resource allocation mapping 2139 * and store it in its persistent storage. 2140 * 2141 * Some of the link resource is using first come first serve policy. 2142 * The allocation mapping depends on original hotplug order. This information 2143 * is lost after driver is loaded next time. The snapshot is used in order to 2144 * restore link resource to its previous state so user will get consistent 2145 * link capability allocation across reboot. 2146 * 2147 */ 2148 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2149 2150 /* This function restores link resource allocation state from a snapshot 2151 * @dc: pointer to dc of the dm calling this 2152 * @map: a dc link resource snapshot defined internally to dc. 2153 * 2154 * DM needs to call this function after initial link detection on boot and 2155 * before first commit streams to restore link resource allocation state 2156 * from previous boot session. 2157 * 2158 * Some of the link resource is using first come first serve policy. 2159 * The allocation mapping depends on original hotplug order. This information 2160 * is lost after driver is loaded next time. The snapshot is used in order to 2161 * restore link resource to its previous state so user will get consistent 2162 * link capability allocation across reboot. 2163 * 2164 */ 2165 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2166 2167 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2168 * interface i.e stream_update->dsc_config 2169 */ 2170 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2171 2172 /* translate a raw link rate data to bandwidth in kbps */ 2173 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2174 2175 /* determine the optimal bandwidth given link and required bw. 2176 * @link - current detected link 2177 * @req_bw - requested bandwidth in kbps 2178 * @link_settings - returned most optimal link settings that can fit the 2179 * requested bandwidth 2180 * return - false if link can't support requested bandwidth, true if link 2181 * settings is found. 2182 */ 2183 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2184 struct dc_link_settings *link_settings, 2185 uint32_t req_bw); 2186 2187 /* return the max dp link settings can be driven by the link without considering 2188 * connected RX device and its capability 2189 */ 2190 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2191 struct dc_link_settings *max_link_enc_cap); 2192 2193 /* determine when the link is driving MST mode, what DP link channel coding 2194 * format will be used. The decision will remain unchanged until next HPD event. 2195 * 2196 * @link - a link with DP RX connection 2197 * return - if stream is committed to this link with MST signal type, type of 2198 * channel coding format dc will choose. 2199 */ 2200 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2201 const struct dc_link *link); 2202 2203 /* get max dp link settings the link can enable with all things considered. (i.e 2204 * TX/RX/Cable capabilities and dp override policies. 2205 * 2206 * @link - a link with DP RX connection 2207 * return - max dp link settings the link can enable. 2208 * 2209 */ 2210 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2211 2212 /* Get the highest encoding format that the link supports; highest meaning the 2213 * encoding format which supports the maximum bandwidth. 2214 * 2215 * @link - a link with DP RX connection 2216 * return - highest encoding format link supports. 2217 */ 2218 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2219 2220 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2221 * to a link with dp connector signal type. 2222 * @link - a link with dp connector signal type 2223 * return - true if connected, false otherwise 2224 */ 2225 bool dc_link_is_dp_sink_present(struct dc_link *link); 2226 2227 /* Force DP lane settings update to main-link video signal and notify the change 2228 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2229 * tuning purpose. The interface assumes link has already been enabled with DP 2230 * signal. 2231 * 2232 * @lt_settings - a container structure with desired hw_lane_settings 2233 */ 2234 void dc_link_set_drive_settings(struct dc *dc, 2235 struct link_training_settings *lt_settings, 2236 struct dc_link *link); 2237 2238 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2239 * test or debugging purpose. The test pattern will remain until next un-plug. 2240 * 2241 * @link - active link with DP signal output enabled. 2242 * @test_pattern - desired test pattern to output. 2243 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2244 * @test_pattern_color_space - for video test pattern choose a desired color 2245 * space. 2246 * @p_link_settings - For PHY pattern choose a desired link settings 2247 * @p_custom_pattern - some test pattern will require a custom input to 2248 * customize some pattern details. Otherwise keep it to NULL. 2249 * @cust_pattern_size - size of the custom pattern input. 2250 * 2251 */ 2252 bool dc_link_dp_set_test_pattern( 2253 struct dc_link *link, 2254 enum dp_test_pattern test_pattern, 2255 enum dp_test_pattern_color_space test_pattern_color_space, 2256 const struct link_training_settings *p_link_settings, 2257 const unsigned char *p_custom_pattern, 2258 unsigned int cust_pattern_size); 2259 2260 /* Force DP link settings to always use a specific value until reboot to a 2261 * specific link. If link has already been enabled, the interface will also 2262 * switch to desired link settings immediately. This is a debug interface to 2263 * generic dp issue trouble shooting. 2264 */ 2265 void dc_link_set_preferred_link_settings(struct dc *dc, 2266 struct dc_link_settings *link_setting, 2267 struct dc_link *link); 2268 2269 /* Force DP link to customize a specific link training behavior by overriding to 2270 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2271 * display specific link training issues or apply some display specific 2272 * workaround in link training. 2273 * 2274 * @link_settings - if not NULL, force preferred link settings to the link. 2275 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2276 * will apply this particular override in future link training. If NULL is 2277 * passed in, dc resets previous overrides. 2278 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2279 * training settings. 2280 */ 2281 void dc_link_set_preferred_training_settings(struct dc *dc, 2282 struct dc_link_settings *link_setting, 2283 struct dc_link_training_overrides *lt_overrides, 2284 struct dc_link *link, 2285 bool skip_immediate_retrain); 2286 2287 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2288 bool dc_link_is_fec_supported(const struct dc_link *link); 2289 2290 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2291 * link enablement. 2292 * return - true if FEC should be enabled, false otherwise. 2293 */ 2294 bool dc_link_should_enable_fec(const struct dc_link *link); 2295 2296 /* determine lttpr mode the current link should be enabled with a specific link 2297 * settings. 2298 */ 2299 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2300 struct dc_link_settings *link_setting); 2301 2302 /* Force DP RX to update its power state. 2303 * NOTE: this interface doesn't update dp main-link. Calling this function will 2304 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2305 * RX power state back upon finish DM specific execution requiring DP RX in a 2306 * specific power state. 2307 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2308 * state. 2309 */ 2310 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2311 2312 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2313 * current value read from extended receiver cap from 02200h - 0220Fh. 2314 * Some DP RX has problems of providing accurate DP receiver caps from extended 2315 * field, this interface is a workaround to revert link back to use base caps. 2316 */ 2317 void dc_link_overwrite_extended_receiver_cap( 2318 struct dc_link *link); 2319 2320 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2321 bool wait_for_hpd); 2322 2323 /* Set backlight level of an embedded panel (eDP, LVDS). 2324 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2325 * and 16 bit fractional, where 1.0 is max backlight value. 2326 */ 2327 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2328 struct set_backlight_level_params *backlight_level_params); 2329 2330 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2331 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2332 bool isHDR, 2333 uint32_t backlight_millinits, 2334 uint32_t transition_time_in_ms); 2335 2336 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2337 uint32_t *backlight_millinits, 2338 uint32_t *backlight_millinits_peak); 2339 2340 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2341 2342 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2343 2344 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2345 bool wait, bool force_static, const unsigned int *power_opts); 2346 2347 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2348 2349 bool dc_link_setup_psr(struct dc_link *dc_link, 2350 const struct dc_stream_state *stream, struct psr_config *psr_config, 2351 struct psr_context *psr_context); 2352 2353 /* 2354 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2355 * 2356 * @link: pointer to the dc_link struct instance 2357 * @enable: enable(active) or disable(inactive) replay 2358 * @wait: state transition need to wait the active set completed. 2359 * @force_static: force disable(inactive) the replay 2360 * @power_opts: set power optimazation parameters to DMUB. 2361 * 2362 * return: allow Replay active will return true, else will return false. 2363 */ 2364 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2365 bool wait, bool force_static, const unsigned int *power_opts); 2366 2367 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2368 2369 /* On eDP links this function call will stall until T12 has elapsed. 2370 * If the panel is not in power off state, this function will return 2371 * immediately. 2372 */ 2373 bool dc_link_wait_for_t12(struct dc_link *link); 2374 2375 /* Determine if dp trace has been initialized to reflect upto date result * 2376 * return - true if trace is initialized and has valid data. False dp trace 2377 * doesn't have valid result. 2378 */ 2379 bool dc_dp_trace_is_initialized(struct dc_link *link); 2380 2381 /* Query a dp trace flag to indicate if the current dp trace data has been 2382 * logged before 2383 */ 2384 bool dc_dp_trace_is_logged(struct dc_link *link, 2385 bool in_detection); 2386 2387 /* Set dp trace flag to indicate whether DM has already logged the current dp 2388 * trace data. DM can set is_logged to true upon logging and check 2389 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2390 */ 2391 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2392 bool in_detection, 2393 bool is_logged); 2394 2395 /* Obtain driver time stamp for last dp link training end. The time stamp is 2396 * formatted based on dm_get_timestamp DM function. 2397 * @in_detection - true to get link training end time stamp of last link 2398 * training in detection sequence. false to get link training end time stamp 2399 * of last link training in commit (dpms) sequence 2400 */ 2401 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2402 bool in_detection); 2403 2404 /* Get how many link training attempts dc has done with latest sequence. 2405 * @in_detection - true to get link training count of last link 2406 * training in detection sequence. false to get link training count of last link 2407 * training in commit (dpms) sequence 2408 */ 2409 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2410 bool in_detection); 2411 2412 /* Get how many link loss has happened since last link training attempts */ 2413 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2414 2415 /* 2416 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2417 */ 2418 /* 2419 * Send a request from DP-Tx requesting to allocate BW remotely after 2420 * allocating it locally. This will get processed by CM and a CB function 2421 * will be called. 2422 * 2423 * @link: pointer to the dc_link struct instance 2424 * @req_bw: The requested bw in Kbyte to allocated 2425 * 2426 * return: none 2427 */ 2428 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2429 2430 /* 2431 * Handle the USB4 BW Allocation related functionality here: 2432 * Plug => Try to allocate max bw from timing parameters supported by the sink 2433 * Unplug => de-allocate bw 2434 * 2435 * @link: pointer to the dc_link struct instance 2436 * @peak_bw: Peak bw used by the link/sink 2437 * 2438 */ 2439 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2440 struct dc_link *link, int peak_bw); 2441 2442 /* 2443 * Calculates the DP tunneling bandwidth required for the stream timing 2444 * and aggregates the stream bandwidth for the respective DP tunneling link 2445 * 2446 * return: dc_status 2447 */ 2448 enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx); 2449 2450 /* Sink Interfaces - A sink corresponds to a display output device */ 2451 2452 struct dc_container_id { 2453 // 128bit GUID in binary form 2454 unsigned char guid[16]; 2455 // 8 byte port ID -> ELD.PortID 2456 unsigned int portId[2]; 2457 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2458 unsigned short manufacturerName; 2459 // 2 byte product code -> ELD.ProductCode 2460 unsigned short productCode; 2461 }; 2462 2463 2464 struct dc_sink_dsc_caps { 2465 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2466 // 'false' if they are sink's DSC caps 2467 bool is_virtual_dpcd_dsc; 2468 // 'true' if MST topology supports DSC passthrough for sink 2469 // 'false' if MST topology does not support DSC passthrough 2470 bool is_dsc_passthrough_supported; 2471 struct dsc_dec_dpcd_caps dsc_dec_caps; 2472 }; 2473 2474 struct dc_sink_hblank_expansion_caps { 2475 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 2476 // 'false' if they are sink's HBlank expansion caps 2477 bool is_virtual_dpcd_hblank_expansion; 2478 struct hblank_expansion_dpcd_caps dpcd_caps; 2479 }; 2480 2481 struct dc_sink_fec_caps { 2482 bool is_rx_fec_supported; 2483 bool is_topology_fec_supported; 2484 }; 2485 2486 struct scdc_caps { 2487 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2488 union hdmi_scdc_device_id_data device_id; 2489 }; 2490 2491 /* 2492 * The sink structure contains EDID and other display device properties 2493 */ 2494 struct dc_sink { 2495 enum signal_type sink_signal; 2496 struct dc_edid dc_edid; /* raw edid */ 2497 struct dc_edid_caps edid_caps; /* parse display caps */ 2498 struct dc_container_id *dc_container_id; 2499 uint32_t dongle_max_pix_clk; 2500 void *priv; 2501 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2502 bool converter_disable_audio; 2503 2504 struct scdc_caps scdc_caps; 2505 struct dc_sink_dsc_caps dsc_caps; 2506 struct dc_sink_fec_caps fec_caps; 2507 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 2508 2509 bool is_vsc_sdp_colorimetry_supported; 2510 2511 /* private to DC core */ 2512 struct dc_link *link; 2513 struct dc_context *ctx; 2514 2515 uint32_t sink_id; 2516 2517 /* private to dc_sink.c */ 2518 // refcount must be the last member in dc_sink, since we want the 2519 // sink structure to be logically cloneable up to (but not including) 2520 // refcount 2521 struct kref refcount; 2522 }; 2523 2524 void dc_sink_retain(struct dc_sink *sink); 2525 void dc_sink_release(struct dc_sink *sink); 2526 2527 struct dc_sink_init_data { 2528 enum signal_type sink_signal; 2529 struct dc_link *link; 2530 uint32_t dongle_max_pix_clk; 2531 bool converter_disable_audio; 2532 }; 2533 2534 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2535 2536 /* Newer interfaces */ 2537 struct dc_cursor { 2538 struct dc_plane_address address; 2539 struct dc_cursor_attributes attributes; 2540 }; 2541 2542 2543 /* Interrupt interfaces */ 2544 enum dc_irq_source dc_interrupt_to_irq_source( 2545 struct dc *dc, 2546 uint32_t src_id, 2547 uint32_t ext_id); 2548 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2549 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2550 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2551 struct dc *dc, uint32_t link_index); 2552 2553 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2554 2555 /* Power Interfaces */ 2556 2557 void dc_set_power_state( 2558 struct dc *dc, 2559 enum dc_acpi_cm_power_state power_state); 2560 void dc_resume(struct dc *dc); 2561 2562 void dc_power_down_on_boot(struct dc *dc); 2563 2564 /* 2565 * HDCP Interfaces 2566 */ 2567 enum hdcp_message_status dc_process_hdcp_msg( 2568 enum signal_type signal, 2569 struct dc_link *link, 2570 struct hdcp_protection_message *message_info); 2571 bool dc_is_dmcu_initialized(struct dc *dc); 2572 2573 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2574 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2575 2576 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 2577 unsigned int pitch, 2578 unsigned int height, 2579 enum surface_pixel_format format, 2580 struct dc_cursor_attributes *cursor_attr); 2581 2582 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 2583 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 2584 2585 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 2586 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 2587 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2588 2589 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2590 void dc_unlock_memory_clock_frequency(struct dc *dc); 2591 2592 /* set min memory clock to the min required for current mode, max to maxDPM */ 2593 void dc_lock_memory_clock_frequency(struct dc *dc); 2594 2595 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2596 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2597 2598 /* cleanup on driver unload */ 2599 void dc_hardware_release(struct dc *dc); 2600 2601 /* disables fw based mclk switch */ 2602 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2603 2604 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2605 2606 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2607 2608 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 2609 2610 void dc_z10_restore(const struct dc *dc); 2611 void dc_z10_save_init(struct dc *dc); 2612 2613 bool dc_is_dmub_outbox_supported(struct dc *dc); 2614 bool dc_enable_dmub_notifications(struct dc *dc); 2615 2616 bool dc_abm_save_restore( 2617 struct dc *dc, 2618 struct dc_stream_state *stream, 2619 struct abm_save_restore *pData); 2620 2621 void dc_enable_dmub_outbox(struct dc *dc); 2622 2623 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2624 uint32_t link_index, 2625 struct aux_payload *payload); 2626 2627 /* Get dc link index from dpia port index */ 2628 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2629 uint8_t dpia_port_index); 2630 2631 bool dc_process_dmub_set_config_async(struct dc *dc, 2632 uint32_t link_index, 2633 struct set_config_cmd_payload *payload, 2634 struct dmub_notification *notify); 2635 2636 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2637 uint32_t link_index, 2638 uint8_t mst_alloc_slots, 2639 uint8_t *mst_slots_in_use); 2640 2641 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 2642 2643 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2644 uint32_t hpd_int_enable); 2645 2646 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2647 2648 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2649 2650 struct dc_power_profile { 2651 int power_level; /* Lower is better */ 2652 }; 2653 2654 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2655 2656 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 2657 2658 bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index); 2659 2660 /* DSC Interfaces */ 2661 #include "dc_dsc.h" 2662 2663 void dc_get_visual_confirm_for_stream( 2664 struct dc *dc, 2665 struct dc_stream_state *stream_state, 2666 struct tg_color *color); 2667 2668 /* Disable acc mode Interfaces */ 2669 void dc_disable_accelerated_mode(struct dc *dc); 2670 2671 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2672 struct dc_stream_state *new_stream); 2673 2674 bool dc_is_cursor_limit_pending(struct dc *dc); 2675 bool dc_can_clear_cursor_limit(struct dc *dc); 2676 2677 #endif /* DC_INTERFACE_H_ */ 2678