1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/pci.h> 7 #include <linux/cdev.h> 8 #include <linux/uuid.h> 9 #include <linux/node.h> 10 #include <cxl/event.h> 11 #include <cxl/mailbox.h> 12 #include "cxl.h" 13 14 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 15 #define CXLMDEV_STATUS_OFFSET 0x0 16 #define CXLMDEV_DEV_FATAL BIT(0) 17 #define CXLMDEV_FW_HALT BIT(1) 18 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 19 #define CXLMDEV_MS_NOT_READY 0 20 #define CXLMDEV_MS_READY 1 21 #define CXLMDEV_MS_ERROR 2 22 #define CXLMDEV_MS_DISABLED 3 23 #define CXLMDEV_READY(status) \ 24 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 25 CXLMDEV_MS_READY) 26 #define CXLMDEV_MBOX_IF_READY BIT(4) 27 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 28 #define CXLMDEV_RESET_NEEDED_NOT 0 29 #define CXLMDEV_RESET_NEEDED_COLD 1 30 #define CXLMDEV_RESET_NEEDED_WARM 2 31 #define CXLMDEV_RESET_NEEDED_HOT 3 32 #define CXLMDEV_RESET_NEEDED_CXL 4 33 #define CXLMDEV_RESET_NEEDED(status) \ 34 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 35 CXLMDEV_RESET_NEEDED_NOT) 36 37 /** 38 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 39 * @dev: driver core device object 40 * @cdev: char dev core object for ioctl operations 41 * @cxlds: The device state backing this device 42 * @detach_work: active memdev lost a port in its ancestry 43 * @cxl_nvb: coordinate removal of @cxl_nvd if present 44 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 45 * @endpoint: connection to the CXL port topology for this memory device 46 * @attach: creator of this memdev depends on CXL link attach to operate 47 * @id: id number of this memdev instance. 48 * @depth: endpoint port depth 49 * @scrub_cycle: current scrub cycle set for this device 50 * @scrub_region_id: id number of a backed region (if any) for which current scrub cycle set 51 * @err_rec_array: List of xarrarys to store the memdev error records to 52 * check attributes for a memory repair operation are from 53 * current boot. 54 */ 55 struct cxl_memdev { 56 struct device dev; 57 struct cdev cdev; 58 struct cxl_dev_state *cxlds; 59 struct work_struct detach_work; 60 struct cxl_nvdimm_bridge *cxl_nvb; 61 struct cxl_nvdimm *cxl_nvd; 62 struct cxl_port *endpoint; 63 const struct cxl_memdev_attach *attach; 64 int id; 65 int depth; 66 u8 scrub_cycle; 67 int scrub_region_id; 68 struct cxl_mem_err_rec *err_rec_array; 69 }; 70 71 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 72 { 73 return container_of(dev, struct cxl_memdev, dev); 74 } 75 76 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 77 { 78 return to_cxl_port(cxled->cxld.dev.parent); 79 } 80 81 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 82 { 83 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 84 } 85 86 static inline struct cxl_memdev * 87 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 88 { 89 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 90 91 return to_cxl_memdev(port->uport_dev); 92 } 93 94 bool is_cxl_memdev(const struct device *dev); 95 static inline bool is_cxl_endpoint(struct cxl_port *port) 96 { 97 return is_cxl_memdev(port->uport_dev); 98 } 99 100 struct cxl_memdev_attach { 101 int (*probe)(struct cxl_memdev *cxlmd); 102 }; 103 104 /** 105 * struct cxl_attach_region - coordinate mapping a region at memdev registration 106 * @attach: common core attachment descriptor 107 * @hpa_range: physical address range of the region 108 * 109 * For the common simple case of a CXL device with private (non-general purpose 110 * / "accelerator") memory, enumerate firmware instantiated region, or 111 * instantiate a region for the device's capacity. Destroy the region on detach. 112 */ 113 struct cxl_attach_region { 114 struct cxl_memdev_attach attach; 115 struct range hpa_range; 116 }; 117 118 #ifdef CONFIG_CXL_REGION 119 int cxl_memdev_attach_region(struct cxl_memdev *cxlmd); 120 #else 121 static inline int cxl_memdev_attach_region(struct cxl_memdev *cxlmd) 122 { 123 return -EOPNOTSUPP; 124 } 125 #endif 126 127 struct cxl_memdev *devm_cxl_add_classdev(struct cxl_dev_state *cxlds); 128 struct cxl_memdev *__devm_cxl_add_memdev(struct cxl_dev_state *cxlds, 129 const struct cxl_memdev_attach *attach); 130 int devm_cxl_sanitize_setup_notifier(struct device *host, 131 struct cxl_memdev *cxlmd); 132 struct cxl_memdev_state; 133 int devm_cxl_setup_fw_upload(struct device *host, struct cxl_memdev_state *mds); 134 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 135 resource_size_t base, resource_size_t len, 136 resource_size_t skipped); 137 138 struct cxl_dpa_info { 139 u64 size; 140 struct cxl_dpa_part_info { 141 struct range range; 142 enum cxl_partition_mode mode; 143 u8 handle; 144 } part[CXL_NR_PARTITIONS_MAX]; 145 int nr_partitions; 146 }; 147 148 int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info); 149 150 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 151 struct cxl_memdev *cxlmd) 152 { 153 if (!port) 154 return NULL; 155 156 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 157 } 158 159 /* 160 * Per CXL 3.0 Section 8.2.8.4.5.1 161 */ 162 #define CMD_CMD_RC_TABLE \ 163 C(SUCCESS, 0, NULL), \ 164 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 165 C(INPUT, -ENXIO, "cmd input was invalid"), \ 166 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 167 C(INTERNAL, -ENXIO, "internal device error"), \ 168 C(RETRY, -ENXIO, "temporary error, retry once"), \ 169 C(BUSY, -ENXIO, "ongoing background operation"), \ 170 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 171 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 172 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 173 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 174 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 175 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 176 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 177 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 178 C(PADDR, -EFAULT, "physical address specified is invalid"), \ 179 C(POISONLMT, -EBUSY, "poison injection limit has been reached"), \ 180 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 181 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 182 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 183 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 184 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 185 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \ 186 C(LOG, -ENXIO, "invalid or unsupported log page"), \ 187 C(INTERRUPTED, -ENXIO, "asynchronous event occurred"), \ 188 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \ 189 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \ 190 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \ 191 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \ 192 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \ 193 C(EXTLIST, -ENXIO, "invalid Extent List"), \ 194 195 #undef C 196 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 197 enum { CMD_CMD_RC_TABLE }; 198 #undef C 199 #define C(a, b, c) { b, c } 200 struct cxl_mbox_cmd_rc { 201 int err; 202 const char *desc; 203 }; 204 205 static const 206 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 207 #undef C 208 209 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 210 { 211 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 212 } 213 214 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 215 { 216 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 217 } 218 219 /* 220 * CXL 2.0 - Memory capacity multiplier 221 * See Section 8.2.9.5 222 * 223 * Volatile, Persistent, and Partition capacities are specified to be in 224 * multiples of 256MB - define a multiplier to convert to/from bytes. 225 */ 226 #define CXL_CAPACITY_MULTIPLIER SZ_256M 227 228 /* 229 * Event Interrupt Policy 230 * 231 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52 232 */ 233 enum cxl_event_int_mode { 234 CXL_INT_NONE = 0x00, 235 CXL_INT_MSI_MSIX = 0x01, 236 CXL_INT_FW = 0x02 237 }; 238 struct cxl_event_interrupt_policy { 239 u8 info_settings; 240 u8 warn_settings; 241 u8 failure_settings; 242 u8 fatal_settings; 243 u8 dcd_settings; 244 } __packed; 245 #define CXL_EVENT_INT_POLICY_BASE_SIZE 4 /* info, warn, failure, fatal */ 246 247 /** 248 * struct cxl_event_state - Event log driver state 249 * 250 * @buf: Buffer to receive event data 251 * @log_lock: Serialize event_buf and log use 252 */ 253 struct cxl_event_state { 254 struct cxl_get_event_payload *buf; 255 struct mutex log_lock; 256 }; 257 258 /* 259 * CXL r4.0 Section 8.2.10.9 - Memory Device Command Sets. See Table 8-308. 260 * 261 * The 48h Command Set (Opcodes 4800h - 4803h) defines the device-enabled DCD 262 * commands. 263 */ 264 enum dcd_cmd_enabled_bits { 265 CXL_DCD_ENABLED_GET_CONFIG, 266 CXL_DCD_ENABLED_GET_EXTENT_LIST, 267 CXL_DCD_ENABLED_ADD_RESPONSE, 268 CXL_DCD_ENABLED_RELEASE, 269 CXL_DCD_ENABLED_MAX 270 }; 271 272 /* Device enabled poison commands */ 273 enum poison_cmd_enabled_bits { 274 CXL_POISON_ENABLED_LIST, 275 CXL_POISON_ENABLED_INJECT, 276 CXL_POISON_ENABLED_CLEAR, 277 CXL_POISON_ENABLED_SCAN_CAPS, 278 CXL_POISON_ENABLED_SCAN_MEDIA, 279 CXL_POISON_ENABLED_SCAN_RESULTS, 280 CXL_POISON_ENABLED_MAX 281 }; 282 283 /* Device enabled security commands */ 284 enum security_cmd_enabled_bits { 285 CXL_SEC_ENABLED_SANITIZE, 286 CXL_SEC_ENABLED_SECURE_ERASE, 287 CXL_SEC_ENABLED_GET_SECURITY_STATE, 288 CXL_SEC_ENABLED_SET_PASSPHRASE, 289 CXL_SEC_ENABLED_DISABLE_PASSPHRASE, 290 CXL_SEC_ENABLED_UNLOCK, 291 CXL_SEC_ENABLED_FREEZE_SECURITY, 292 CXL_SEC_ENABLED_PASSPHRASE_SECURE_ERASE, 293 CXL_SEC_ENABLED_MAX 294 }; 295 296 /** 297 * struct cxl_poison_state - Driver poison state info 298 * 299 * @max_errors: Maximum media error records held in device cache 300 * @enabled_cmds: All poison commands enabled in the CEL 301 * @list_out: The poison list payload returned by device 302 * @mutex: Protect reads of the poison list 303 * 304 * Reads of the poison list are synchronized to ensure that a reader 305 * does not get an incomplete list because their request overlapped 306 * (was interrupted or preceded by) another read request of the same 307 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1 308 */ 309 struct cxl_poison_state { 310 u32 max_errors; 311 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX); 312 struct cxl_mbox_poison_out *list_out; 313 struct mutex mutex; /* Protect reads of poison list */ 314 }; 315 316 /* 317 * Get FW Info 318 * CXL rev 3.0 section 8.2.9.3.1; Table 8-56 319 */ 320 struct cxl_mbox_get_fw_info { 321 u8 num_slots; 322 u8 slot_info; 323 u8 activation_cap; 324 u8 reserved[13]; 325 char slot_1_revision[16]; 326 char slot_2_revision[16]; 327 char slot_3_revision[16]; 328 char slot_4_revision[16]; 329 } __packed; 330 331 #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0) 332 #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3) 333 #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3 334 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0) 335 336 /* 337 * Transfer FW Input Payload 338 * CXL rev 3.0 section 8.2.9.3.2; Table 8-57 339 */ 340 struct cxl_mbox_transfer_fw { 341 u8 action; 342 u8 slot; 343 u8 reserved[2]; 344 __le32 offset; 345 u8 reserved2[0x78]; 346 u8 data[]; 347 } __packed; 348 349 #define CXL_FW_TRANSFER_ACTION_FULL 0x0 350 #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1 351 #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2 352 #define CXL_FW_TRANSFER_ACTION_END 0x3 353 #define CXL_FW_TRANSFER_ACTION_ABORT 0x4 354 355 /* 356 * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages 357 * and for each part transferred in a Transfer FW command. 358 */ 359 #define CXL_FW_TRANSFER_ALIGNMENT 128 360 361 /* 362 * Activate FW Input Payload 363 * CXL rev 3.0 section 8.2.9.3.3; Table 8-58 364 */ 365 struct cxl_mbox_activate_fw { 366 u8 action; 367 u8 slot; 368 } __packed; 369 370 #define CXL_FW_ACTIVATE_ONLINE 0x0 371 #define CXL_FW_ACTIVATE_OFFLINE 0x1 372 373 /* FW state bits */ 374 #define CXL_FW_STATE_BITS 32 375 #define CXL_FW_CANCEL 0 376 377 /** 378 * struct cxl_fw_state - Firmware upload / activation state 379 * 380 * @state: fw_uploader state bitmask 381 * @oneshot: whether the fw upload fits in a single transfer 382 * @num_slots: Number of FW slots available 383 * @cur_slot: Slot number currently active 384 * @next_slot: Slot number for the new firmware 385 */ 386 struct cxl_fw_state { 387 DECLARE_BITMAP(state, CXL_FW_STATE_BITS); 388 bool oneshot; 389 int num_slots; 390 int cur_slot; 391 int next_slot; 392 }; 393 394 /** 395 * struct cxl_security_state - Device security state 396 * 397 * @state: state of last security operation 398 * @enabled_cmds: All security commands enabled in the CEL 399 * @poll_tmo_secs: polling timeout 400 * @sanitize_active: sanitize completion pending 401 * @poll_dwork: polling work item 402 * @sanitize_node: sanitation sysfs file to notify 403 */ 404 struct cxl_security_state { 405 unsigned long state; 406 DECLARE_BITMAP(enabled_cmds, CXL_SEC_ENABLED_MAX); 407 int poll_tmo_secs; 408 bool sanitize_active; 409 struct delayed_work poll_dwork; 410 struct kernfs_node *sanitize_node; 411 }; 412 413 #define CXL_MAX_DC_PARTITIONS 8 414 415 static inline resource_size_t cxl_part_size(struct cxl_dev_state *cxlds, 416 enum cxl_partition_mode mode) 417 { 418 for (int i = 0; i < cxlds->nr_partitions; i++) 419 if (cxlds->part[i].mode == mode) 420 return resource_size(&cxlds->part[i].res); 421 return 0; 422 } 423 424 static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox) 425 { 426 return dev_get_drvdata(cxl_mbox->host); 427 } 428 429 /** 430 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data 431 * 432 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines 433 * common memory device functionality like the presence of a mailbox and 434 * the functionality related to that like Identify Memory Device and Get 435 * Partition Info 436 * @cxlds: Core driver state common across Type-2 and Type-3 devices 437 * @lsa_size: Size of Label Storage Area 438 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 439 * @firmware_version: Firmware version for the memory device. 440 * @total_bytes: sum of all possible capacities 441 * @volatile_only_bytes: hard volatile capacity 442 * @persistent_only_bytes: hard persistent capacity 443 * @partition_align_bytes: alignment size for partition-able capacity 444 * @active_volatile_bytes: sum of hard + soft volatile 445 * @active_persistent_bytes: sum of hard + soft persistent 446 * @dcd_supported: all DCD commands are supported 447 * @event: event log driver state 448 * @poison: poison driver state info 449 * @security: security driver state info 450 * @fw: firmware upload / activation state 451 * 452 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for 453 * details on capacity parameters. 454 */ 455 struct cxl_memdev_state { 456 struct cxl_dev_state cxlds; 457 size_t lsa_size; 458 char firmware_version[0x10]; 459 u64 total_bytes; 460 u64 volatile_only_bytes; 461 u64 persistent_only_bytes; 462 u64 partition_align_bytes; 463 u64 active_volatile_bytes; 464 u64 active_persistent_bytes; 465 bool dcd_supported; 466 467 struct cxl_event_state event; 468 struct cxl_poison_state poison; 469 struct cxl_security_state security; 470 struct cxl_fw_state fw; 471 }; 472 473 static inline struct cxl_memdev_state * 474 to_cxl_memdev_state(struct cxl_dev_state *cxlds) 475 { 476 if (cxlds->type != CXL_DEVTYPE_CLASSMEM) 477 return NULL; 478 return container_of(cxlds, struct cxl_memdev_state, cxlds); 479 } 480 481 enum cxl_opcode { 482 CXL_MBOX_OP_INVALID = 0x0000, 483 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 484 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, 485 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101, 486 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102, 487 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103, 488 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 489 CXL_MBOX_OP_TRANSFER_FW = 0x0201, 490 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 491 CXL_MBOX_OP_GET_TIMESTAMP = 0x0300, 492 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301, 493 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 494 CXL_MBOX_OP_GET_LOG = 0x0401, 495 CXL_MBOX_OP_GET_LOG_CAPS = 0x0402, 496 CXL_MBOX_OP_CLEAR_LOG = 0x0403, 497 CXL_MBOX_OP_GET_SUP_LOG_SUBLIST = 0x0405, 498 CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500, 499 CXL_MBOX_OP_GET_FEATURE = 0x0501, 500 CXL_MBOX_OP_SET_FEATURE = 0x0502, 501 CXL_MBOX_OP_DO_MAINTENANCE = 0x0600, 502 CXL_MBOX_OP_IDENTIFY = 0x4000, 503 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 504 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 505 CXL_MBOX_OP_GET_LSA = 0x4102, 506 CXL_MBOX_OP_SET_LSA = 0x4103, 507 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 508 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 509 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 510 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 511 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 512 CXL_MBOX_OP_GET_POISON = 0x4300, 513 CXL_MBOX_OP_INJECT_POISON = 0x4301, 514 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 515 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 516 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 517 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 518 CXL_MBOX_OP_SANITIZE = 0x4400, 519 CXL_MBOX_OP_SECURE_ERASE = 0x4401, 520 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 521 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 522 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 523 CXL_MBOX_OP_UNLOCK = 0x4503, 524 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 525 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 526 CXL_MBOX_OP_GET_DC_CONFIG = 0x4800, 527 CXL_MBOX_OP_GET_DC_EXTENT_LIST = 0x4801, 528 CXL_MBOX_OP_ADD_DC_RESPONSE = 0x4802, 529 CXL_MBOX_OP_RELEASE_DC = 0x4803, 530 CXL_MBOX_OP_MAX = 0x10000 531 }; 532 533 #define DEFINE_CXL_CEL_UUID \ 534 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 535 0x3b, 0x3f, 0x17) 536 537 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 538 UUID_INIT(0x5e1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 539 0x40, 0x3d, 0x86) 540 541 struct cxl_mbox_get_supported_logs { 542 __le16 entries; 543 u8 rsvd[6]; 544 struct cxl_gsl_entry { 545 uuid_t uuid; 546 __le32 size; 547 } __packed entry[]; 548 } __packed; 549 550 struct cxl_cel_entry { 551 __le16 opcode; 552 __le16 effect; 553 } __packed; 554 555 struct cxl_mbox_get_log { 556 uuid_t uuid; 557 __le32 offset; 558 __le32 length; 559 } __packed; 560 561 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 562 struct cxl_mbox_identify { 563 char fw_revision[0x10]; 564 __le64 total_capacity; 565 __le64 volatile_capacity; 566 __le64 persistent_capacity; 567 __le64 partition_align; 568 __le16 info_event_log_size; 569 __le16 warning_event_log_size; 570 __le16 failure_event_log_size; 571 __le16 fatal_event_log_size; 572 __le32 lsa_size; 573 u8 poison_list_max_mer[3]; 574 __le16 inject_poison_limit; 575 u8 poison_caps; 576 u8 qos_telemetry_caps; 577 } __packed; 578 579 /* 580 * General Media Event Record UUID 581 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 582 */ 583 #define CXL_EVENT_GEN_MEDIA_UUID \ 584 UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, 0x85, 0xa9, 0x08, 0x8b, 0x16, \ 585 0x21, 0xeb, 0xa6) 586 587 /* 588 * DRAM Event Record UUID 589 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 590 */ 591 #define CXL_EVENT_DRAM_UUID \ 592 UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, \ 593 0x5c, 0x96, 0x24) 594 595 /* 596 * Memory Module Event Record UUID 597 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45 598 */ 599 #define CXL_EVENT_MEM_MODULE_UUID \ 600 UUID_INIT(0xfe927475, 0xdd59, 0x4339, 0xa5, 0x86, 0x79, 0xba, 0xb1, \ 601 0x13, 0xb7, 0x74) 602 603 /* 604 * Memory Sparing Event Record UUID 605 * CXL rev 3.2 section 8.2.10.2.1.4: Table 8-60 606 */ 607 #define CXL_EVENT_MEM_SPARING_UUID \ 608 UUID_INIT(0xe71f3a40, 0x2d29, 0x4092, 0x8a, 0x39, 0x4d, 0x1c, 0x96, \ 609 0x6c, 0x7c, 0x65) 610 611 /* 612 * Get Event Records output payload 613 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50 614 */ 615 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0) 616 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1) 617 struct cxl_get_event_payload { 618 u8 flags; 619 u8 reserved1; 620 __le16 overflow_err_count; 621 __le64 first_overflow_timestamp; 622 __le64 last_overflow_timestamp; 623 __le16 record_count; 624 u8 reserved2[10]; 625 struct cxl_event_record_raw records[]; 626 } __packed; 627 628 /* 629 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49 630 */ 631 enum cxl_event_log_type { 632 CXL_EVENT_TYPE_INFO = 0x00, 633 CXL_EVENT_TYPE_WARN, 634 CXL_EVENT_TYPE_FAIL, 635 CXL_EVENT_TYPE_FATAL, 636 CXL_EVENT_TYPE_MAX 637 }; 638 639 /* 640 * Clear Event Records input payload 641 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51 642 */ 643 struct cxl_mbox_clear_event_payload { 644 u8 event_log; /* enum cxl_event_log_type */ 645 u8 clear_flags; 646 u8 nr_recs; 647 u8 reserved[3]; 648 __le16 handles[]; 649 } __packed; 650 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX 651 652 struct cxl_mbox_get_partition_info { 653 __le64 active_volatile_cap; 654 __le64 active_persistent_cap; 655 __le64 next_volatile_cap; 656 __le64 next_persistent_cap; 657 } __packed; 658 659 struct cxl_mbox_get_lsa { 660 __le32 offset; 661 __le32 length; 662 } __packed; 663 664 struct cxl_mbox_set_lsa { 665 __le32 offset; 666 __le32 reserved; 667 u8 data[]; 668 } __packed; 669 670 struct cxl_mbox_set_partition_info { 671 __le64 volatile_capacity; 672 u8 flags; 673 } __packed; 674 675 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 676 677 /* Get Health Info Output Payload CXL 3.2 Spec 8.2.10.9.3.1 Table 8-148 */ 678 struct cxl_mbox_get_health_info_out { 679 u8 health_status; 680 u8 media_status; 681 u8 additional_status; 682 u8 life_used; 683 __le16 device_temperature; 684 __le32 dirty_shutdown_cnt; 685 __le32 corrected_volatile_error_cnt; 686 __le32 corrected_persistent_error_cnt; 687 } __packed; 688 689 /* Set Shutdown State Input Payload CXL 3.2 Spec 8.2.10.9.3.5 Table 8-152 */ 690 struct cxl_mbox_set_shutdown_state_in { 691 u8 state; 692 } __packed; 693 694 /* See CXL r4.0 Table 8-345 get dynamic capacity config Input Payload */ 695 struct cxl_mbox_get_dc_config_in { 696 u8 partition_count; 697 u8 start_partition_index; 698 } __packed; 699 700 /* See CXL r4.0 Table 8-346 get dynamic capacity config Output Payload */ 701 struct cxl_mbox_get_dc_config_out { 702 u8 avail_partition_count; 703 u8 partitions_returned; 704 u8 rsvd[6]; 705 /* See CXL r4.0 Table 8-347 */ 706 struct cxl_dc_partition { 707 __le64 base; 708 __le64 decode_length; 709 __le64 length; 710 __le64 block_size; 711 __le32 dsmad_handle; 712 u8 flags; 713 u8 rsvd[3]; 714 } __packed partition[] __counted_by(partitions_returned); 715 /* Trailing extent/tag count fields unused */ 716 } __packed; 717 718 /* Trailing counts; cannot be a member after the flex array above */ 719 struct cxl_mbox_get_dc_config_tail { 720 __le32 num_extents_supported; 721 __le32 num_extents_available; 722 __le32 num_tags_supported; 723 __le32 num_tags_available; 724 } __packed; 725 #define CXL_DCD_BLOCK_LINE_SIZE 0x40 726 727 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */ 728 struct cxl_mbox_set_timestamp_in { 729 __le64 timestamp; 730 731 } __packed; 732 733 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ 734 struct cxl_mbox_poison_in { 735 __le64 offset; 736 __le64 length; 737 } __packed; 738 739 struct cxl_mbox_poison_out { 740 u8 flags; 741 u8 rsvd1; 742 __le64 overflow_ts; 743 __le16 count; 744 u8 rsvd2[20]; 745 struct cxl_poison_record { 746 __le64 address; 747 __le32 length; 748 __le32 rsvd; 749 } __packed record[]; 750 } __packed; 751 752 /* 753 * Get Poison List address field encodes the starting 754 * address of poison, and the source of the poison. 755 */ 756 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6) 757 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0) 758 759 /* Get Poison List record length is in units of 64 bytes */ 760 #define CXL_POISON_LEN_MULT 64 761 762 /* Kernel defined maximum for a list of poison errors */ 763 #define CXL_POISON_LIST_MAX 1024 764 765 /* Get Poison List: Payload out flags */ 766 #define CXL_POISON_FLAG_MORE BIT(0) 767 #define CXL_POISON_FLAG_OVERFLOW BIT(1) 768 #define CXL_POISON_FLAG_SCANNING BIT(2) 769 770 /* Get Poison List: Poison Source */ 771 #define CXL_POISON_SOURCE_UNKNOWN 0 772 #define CXL_POISON_SOURCE_EXTERNAL 1 773 #define CXL_POISON_SOURCE_INTERNAL 2 774 #define CXL_POISON_SOURCE_INJECTED 3 775 #define CXL_POISON_SOURCE_VENDOR 7 776 777 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */ 778 struct cxl_mbox_inject_poison { 779 __le64 address; 780 }; 781 782 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */ 783 struct cxl_mbox_clear_poison { 784 __le64 address; 785 u8 write_data[CXL_POISON_LEN_MULT]; 786 } __packed; 787 788 /** 789 * struct cxl_mem_command - Driver representation of a memory device command 790 * @info: Command information as it exists for the UAPI 791 * @opcode: The actual bits used for the mailbox protocol 792 * @flags: Set of flags effecting driver behavior. 793 * 794 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 795 * will be enabled by the driver regardless of what hardware may have 796 * advertised. 797 * 798 * The cxl_mem_command is the driver's internal representation of commands that 799 * are supported by the driver. Some of these commands may not be supported by 800 * the hardware. The driver will use @info to validate the fields passed in by 801 * the user then submit the @opcode to the hardware. 802 * 803 * See struct cxl_command_info. 804 */ 805 struct cxl_mem_command { 806 struct cxl_command_info info; 807 enum cxl_opcode opcode; 808 u32 flags; 809 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 810 }; 811 812 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 813 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 814 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 815 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 816 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 817 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 818 819 /* set passphrase input payload */ 820 struct cxl_set_pass { 821 u8 type; 822 u8 reserved[31]; 823 /* CXL field using NVDIMM define, same length */ 824 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 825 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 826 } __packed; 827 828 /* disable passphrase input payload */ 829 struct cxl_disable_pass { 830 u8 type; 831 u8 reserved[31]; 832 u8 pass[NVDIMM_PASSPHRASE_LEN]; 833 } __packed; 834 835 /* passphrase secure erase payload */ 836 struct cxl_pass_erase { 837 u8 type; 838 u8 reserved[31]; 839 u8 pass[NVDIMM_PASSPHRASE_LEN]; 840 } __packed; 841 842 enum { 843 CXL_PMEM_SEC_PASS_MASTER = 0, 844 CXL_PMEM_SEC_PASS_USER, 845 }; 846 847 int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox, 848 struct cxl_mbox_cmd *cmd); 849 int cxl_dev_state_identify(struct cxl_memdev_state *mds); 850 851 struct cxl_dc_partition_info { 852 u64 start; 853 u64 size; 854 u8 handle; 855 }; 856 857 int cxl_dev_dc_identify(struct cxl_mailbox *mbox, 858 struct cxl_dc_partition_info *dc_info); 859 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 860 int cxl_enumerate_cmds(struct cxl_memdev_state *mds); 861 int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info); 862 int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info); 863 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial, 864 u16 dvsec); 865 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds, 866 unsigned long *cmds); 867 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, 868 unsigned long *cmds); 869 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status); 870 void cxl_event_trace_record(struct cxl_memdev *cxlmd, 871 enum cxl_event_log_type type, 872 enum cxl_event_type event_type, 873 const uuid_t *uuid, union cxl_event *evt); 874 int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count); 875 int cxl_arm_dirty_shutdown(struct cxl_memdev_state *mds); 876 877 static inline bool cxl_dcd_supported(struct cxl_memdev_state *mds) 878 { 879 return mds->dcd_supported; 880 } 881 882 static inline void cxl_disable_dcd(struct cxl_memdev_state *mds) 883 { 884 mds->dcd_supported = false; 885 } 886 887 int cxl_set_timestamp(struct cxl_memdev_state *mds); 888 int cxl_poison_state_init(struct cxl_memdev_state *mds); 889 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, 890 struct cxl_region *cxlr); 891 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd); 892 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa); 893 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa); 894 int cxl_inject_poison_locked(struct cxl_memdev *cxlmd, u64 dpa); 895 int cxl_clear_poison_locked(struct cxl_memdev *cxlmd, u64 dpa); 896 897 #ifdef CONFIG_CXL_EDAC_MEM_FEATURES 898 int devm_cxl_memdev_edac_register(struct cxl_memdev *cxlmd); 899 int devm_cxl_region_edac_register(struct cxl_region *cxlr); 900 int cxl_store_rec_gen_media(struct cxl_memdev *cxlmd, union cxl_event *evt); 901 int cxl_store_rec_dram(struct cxl_memdev *cxlmd, union cxl_event *evt); 902 #else 903 static inline int devm_cxl_memdev_edac_register(struct cxl_memdev *cxlmd) 904 { return 0; } 905 static inline int devm_cxl_region_edac_register(struct cxl_region *cxlr) 906 { return 0; } 907 static inline int cxl_store_rec_gen_media(struct cxl_memdev *cxlmd, 908 union cxl_event *evt) 909 { return 0; } 910 static inline int cxl_store_rec_dram(struct cxl_memdev *cxlmd, 911 union cxl_event *evt) 912 { return 0; } 913 #endif 914 915 #ifdef CONFIG_CXL_SUSPEND 916 void cxl_mem_active_inc(void); 917 void cxl_mem_active_dec(void); 918 #else 919 static inline void cxl_mem_active_inc(void) 920 { 921 } 922 static inline void cxl_mem_active_dec(void) 923 { 924 } 925 #endif 926 927 int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd); 928 929 /** 930 * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities 931 * @regs: mapped registers, see devm_cxl_setup_hdm() 932 * @decoder_count: number of decoders for this port 933 * @target_count: for switch decoders, max downstream port targets 934 * @interleave_mask: interleave granularity capability, see check_interleave_cap() 935 * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap() 936 * @port: mapped cxl_port, see devm_cxl_setup_hdm() 937 */ 938 struct cxl_hdm { 939 struct cxl_component_regs regs; 940 int decoder_count; 941 unsigned int target_count; 942 unsigned int interleave_mask; 943 unsigned long iw_cap_mask; 944 struct cxl_port *port; 945 }; 946 947 struct seq_file; 948 struct dentry *cxl_debugfs_create_dir(const char *dir); 949 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 950 #endif /* __CXL_MEM_H__ */ 951