1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018-2026 Intel Corporation
4 */
5 #include <linux/firmware.h>
6 #include "iwl-drv.h"
7 #include "iwl-trans.h"
8 #include "iwl-dbg-tlv.h"
9 #include "fw/dbg.h"
10 #include "fw/runtime.h"
11
12 /**
13 * enum iwl_dbg_tlv_type - debug TLV types
14 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV
15 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV
16 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV
17 * @IWL_DBG_TLV_TYPE_REGION: region TLV
18 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV
19 * @IWL_DBG_TLV_TYPE_CONF_SET: conf set TLV
20 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs
21 */
22 enum iwl_dbg_tlv_type {
23 IWL_DBG_TLV_TYPE_DEBUG_INFO =
24 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE,
25 IWL_DBG_TLV_TYPE_BUF_ALLOC,
26 IWL_DBG_TLV_TYPE_HCMD,
27 IWL_DBG_TLV_TYPE_REGION,
28 IWL_DBG_TLV_TYPE_TRIGGER,
29 IWL_DBG_TLV_TYPE_CONF_SET,
30 IWL_DBG_TLV_TYPE_NUM,
31 };
32
33 /**
34 * struct iwl_dbg_tlv_ver_data - debug TLV version struct
35 * @min_ver: min version supported
36 * @max_ver: max version supported
37 */
38 struct iwl_dbg_tlv_ver_data {
39 int min_ver;
40 int max_ver;
41 };
42
43 /**
44 * struct iwl_dbg_tlv_timer_node - timer node struct
45 * @list: list of &struct iwl_dbg_tlv_timer_node
46 * @timer: timer
47 * @fwrt: &struct iwl_fw_runtime
48 * @tlv: TLV attach to the timer node
49 */
50 struct iwl_dbg_tlv_timer_node {
51 struct list_head list;
52 struct timer_list timer;
53 struct iwl_fw_runtime *fwrt;
54 struct iwl_ucode_tlv *tlv;
55 };
56
57 static const struct iwl_dbg_tlv_ver_data
58 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = {
59 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,},
60 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,},
61 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,},
62 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 3,},
63 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,},
64 [IWL_DBG_TLV_TYPE_CONF_SET] = {.min_ver = 1, .max_ver = 1,},
65 };
66
67 /* add a new TLV node, returning it so it can be modified */
iwl_dbg_tlv_add(const struct iwl_ucode_tlv * tlv,struct list_head * list)68 static struct iwl_ucode_tlv *iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv,
69 struct list_head *list)
70 {
71 u32 len = le32_to_cpu(tlv->length);
72 struct iwl_dbg_tlv_node *node;
73
74 node = kzalloc_flex(*node, tlv.data, len);
75 if (!node)
76 return NULL;
77
78 memcpy(&node->tlv, tlv, sizeof(node->tlv));
79 memcpy(node->tlv.data, tlv->data, len);
80 list_add_tail(&node->list, list);
81
82 return &node->tlv;
83 }
84
iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv * tlv)85 static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv)
86 {
87 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0];
88 u32 type = le32_to_cpu(tlv->type);
89 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
90 u32 ver = le32_to_cpu(hdr->version);
91
92 if (ver < dbg_ver_table[tlv_idx].min_ver ||
93 ver > dbg_ver_table[tlv_idx].max_ver)
94 return false;
95
96 return true;
97 }
98
iwl_dbg_tlv_alloc_debug_info(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv)99 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans,
100 const struct iwl_ucode_tlv *tlv)
101 {
102 const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data;
103
104 if (le32_to_cpu(tlv->length) != sizeof(*debug_info))
105 return -EINVAL;
106
107 /* we use this as a string, ensure input was NUL terminated */
108 if (strnlen(debug_info->debug_cfg_name,
109 sizeof(debug_info->debug_cfg_name)) ==
110 sizeof(debug_info->debug_cfg_name))
111 return -EINVAL;
112
113 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n",
114 debug_info->debug_cfg_name);
115
116 if (!iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list))
117 return -ENOMEM;
118 return 0;
119 }
120
iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv)121 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans,
122 const struct iwl_ucode_tlv *tlv)
123 {
124 const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data;
125 u32 buf_location;
126 u32 alloc_id;
127
128 if (le32_to_cpu(tlv->length) != sizeof(*alloc))
129 return -EINVAL;
130
131 buf_location = le32_to_cpu(alloc->buf_location);
132 alloc_id = le32_to_cpu(alloc->alloc_id);
133
134 if (buf_location == IWL_FW_INI_LOCATION_INVALID ||
135 buf_location >= IWL_FW_INI_LOCATION_NUM)
136 goto err;
137
138 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID ||
139 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
140 goto err;
141
142 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH &&
143 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
144 goto err;
145
146 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH &&
147 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
148 goto err;
149
150 if (buf_location == IWL_FW_INI_LOCATION_DRAM_PATH &&
151 alloc->req_size == 0) {
152 IWL_ERR(trans, "WRT: Invalid DRAM buffer allocation requested size (0)\n");
153 return -EINVAL;
154 }
155
156 trans->dbg.fw_mon_cfg[alloc_id] = *alloc;
157
158 return 0;
159 err:
160 IWL_ERR(trans,
161 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n",
162 alloc_id, buf_location);
163 return -EINVAL;
164 }
165
iwl_dbg_tlv_alloc_hcmd(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv)166 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans,
167 const struct iwl_ucode_tlv *tlv)
168 {
169 const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data;
170 u32 tp = le32_to_cpu(hcmd->time_point);
171
172 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd))
173 return -EINVAL;
174
175 /* Host commands can not be sent in early time point since the FW
176 * is not ready
177 */
178 if (tp == IWL_FW_INI_TIME_POINT_INVALID ||
179 tp >= IWL_FW_INI_TIME_POINT_NUM ||
180 tp == IWL_FW_INI_TIME_POINT_EARLY) {
181 IWL_ERR(trans,
182 "WRT: Invalid time point %u for host command TLV\n",
183 tp);
184 return -EINVAL;
185 }
186
187 if (!iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list))
188 return -ENOMEM;
189 return 0;
190 }
191
iwl_dbg_tlv_alloc_region(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv)192 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans,
193 const struct iwl_ucode_tlv *tlv)
194 {
195 const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data;
196 struct iwl_ucode_tlv **active_reg;
197 u32 id = le32_to_cpu(reg->id);
198 u8 type = reg->type;
199 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length);
200
201 /*
202 * The higher part of the ID from version 2 is debug policy.
203 * The id will be only lsb 16 bits, so mask it out.
204 */
205 if (le32_to_cpu(reg->hdr.version) >= 2)
206 id &= IWL_FW_INI_REGION_ID_MASK;
207
208 if (le32_to_cpu(tlv->length) < sizeof(*reg))
209 return -EINVAL;
210
211 /* for safe use of a string from FW, limit it to IWL_FW_INI_MAX_NAME */
212 IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n",
213 IWL_FW_INI_MAX_NAME, reg->name);
214
215 if (id >= IWL_FW_INI_MAX_REGION_ID) {
216 IWL_ERR(trans, "WRT: Invalid region id %u\n", id);
217 return -EINVAL;
218 }
219
220 if (type <= IWL_FW_INI_REGION_INVALID ||
221 type >= IWL_FW_INI_REGION_NUM) {
222 IWL_ERR(trans, "WRT: Invalid region type %u\n", type);
223 return -EINVAL;
224 }
225
226 if (type == IWL_FW_INI_REGION_INTERNAL_BUFFER) {
227 trans->dbg.imr_data.sram_addr =
228 le32_to_cpu(reg->internal_buffer.base_addr);
229 trans->dbg.imr_data.sram_size =
230 le32_to_cpu(reg->internal_buffer.size);
231 }
232
233
234 active_reg = &trans->dbg.active_regions[id];
235 if (*active_reg) {
236 IWL_WARN(trans, "WRT: Overriding region id %u\n", id);
237
238 kfree(*active_reg);
239 }
240
241 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL);
242 if (!*active_reg)
243 return -ENOMEM;
244
245 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type);
246
247 return 0;
248 }
249
iwl_dbg_tlv_alloc_trigger(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv)250 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
251 const struct iwl_ucode_tlv *tlv)
252 {
253 const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data;
254 u32 tp = le32_to_cpu(trig->time_point);
255 u32 rf = le32_to_cpu(trig->reset_fw);
256 struct iwl_ucode_tlv *new_tlv;
257
258 if (le32_to_cpu(tlv->length) < sizeof(*trig))
259 return -EINVAL;
260
261 if (tp <= IWL_FW_INI_TIME_POINT_INVALID ||
262 tp >= IWL_FW_INI_TIME_POINT_NUM) {
263 IWL_ERR(trans,
264 "WRT: Invalid time point %u for trigger TLV\n",
265 tp);
266 return -EINVAL;
267 }
268
269 IWL_DEBUG_FW(trans,
270 "WRT: time point %u for trigger TLV with reset_fw %u\n",
271 tp, rf);
272 trans->dbg.last_tp_resetfw = 0xFF;
273
274 new_tlv = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list);
275 if (!new_tlv)
276 return -ENOMEM;
277
278 if (!le32_to_cpu(trig->occurrences)) {
279 struct iwl_fw_ini_trigger_tlv *new_trig = (void *)new_tlv->data;
280
281 new_trig->occurrences = cpu_to_le32(-1);
282 }
283
284 return 0;
285 }
286
iwl_dbg_tlv_config_set(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv)287 static int iwl_dbg_tlv_config_set(struct iwl_trans *trans,
288 const struct iwl_ucode_tlv *tlv)
289 {
290 const struct iwl_fw_ini_conf_set_tlv *conf_set = (const void *)tlv->data;
291 u32 tp = le32_to_cpu(conf_set->time_point);
292 u32 type = le32_to_cpu(conf_set->set_type);
293
294 if (tp <= IWL_FW_INI_TIME_POINT_INVALID ||
295 tp >= IWL_FW_INI_TIME_POINT_NUM) {
296 IWL_DEBUG_FW(trans,
297 "WRT: Invalid time point %u for config set TLV\n", tp);
298 return -EINVAL;
299 }
300
301 if (type <= IWL_FW_INI_CONFIG_SET_TYPE_INVALID ||
302 type >= IWL_FW_INI_CONFIG_SET_TYPE_MAX_NUM) {
303 IWL_DEBUG_FW(trans,
304 "WRT: Invalid config set type %u for config set TLV\n", type);
305 return -EINVAL;
306 }
307
308 if (!iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list))
309 return -ENOMEM;
310 return 0;
311 }
312
313 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans,
314 const struct iwl_ucode_tlv *tlv) = {
315 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info,
316 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc,
317 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd,
318 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region,
319 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger,
320 [IWL_DBG_TLV_TYPE_CONF_SET] = iwl_dbg_tlv_config_set,
321 };
322
iwl_dbg_tlv_alloc(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv,bool ext)323 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv,
324 bool ext)
325 {
326 enum iwl_ini_cfg_state *cfg_state = ext ?
327 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg;
328 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0];
329 u32 type;
330 u32 tlv_idx;
331 u32 domain;
332 int ret;
333
334 if (le32_to_cpu(tlv->length) < sizeof(*hdr))
335 return;
336
337 type = le32_to_cpu(tlv->type);
338 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
339 domain = le32_to_cpu(hdr->domain);
340
341 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON &&
342 !(domain & trans->dbg.domains_bitmap)) {
343 IWL_DEBUG_FW(trans,
344 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n",
345 domain, trans->dbg.domains_bitmap);
346 return;
347 }
348
349 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) {
350 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type);
351 goto out_err;
352 }
353
354 if (!iwl_dbg_tlv_ver_support(tlv)) {
355 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type,
356 le32_to_cpu(hdr->version));
357 goto out_err;
358 }
359
360 ret = dbg_tlv_alloc[tlv_idx](trans, tlv);
361 if (ret) {
362 IWL_WARN(trans,
363 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n",
364 type, ret, ext);
365 goto out_err;
366 }
367
368 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED)
369 *cfg_state = IWL_INI_CFG_STATE_LOADED;
370
371 return;
372
373 out_err:
374 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED;
375 }
376
iwl_dbg_tlv_del_timers(struct iwl_trans * trans)377 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans)
378 {
379 struct list_head *timer_list = &trans->dbg.periodic_trig_list;
380 struct iwl_dbg_tlv_timer_node *node, *tmp;
381
382 list_for_each_entry_safe(node, tmp, timer_list, list) {
383 timer_shutdown_sync(&node->timer);
384 list_del(&node->list);
385 kfree(node);
386 }
387 }
388 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers);
389
iwl_dbg_tlv_fragments_free(struct iwl_trans * trans,enum iwl_fw_ini_allocation_id alloc_id)390 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans,
391 enum iwl_fw_ini_allocation_id alloc_id)
392 {
393 struct iwl_fw_mon *fw_mon;
394 int i;
395
396 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID ||
397 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
398 return;
399
400 fw_mon = &trans->dbg.fw_mon_ini[alloc_id];
401
402 for (i = 0; i < fw_mon->num_frags; i++) {
403 struct iwl_dram_data *frag = &fw_mon->frags[i];
404
405 dma_free_coherent(trans->dev, frag->size, frag->block,
406 frag->physical);
407
408 frag->physical = 0;
409 frag->block = NULL;
410 frag->size = 0;
411 }
412
413 kfree(fw_mon->frags);
414 fw_mon->frags = NULL;
415 fw_mon->num_frags = 0;
416 }
417
iwl_dbg_tlv_free(struct iwl_trans * trans)418 void iwl_dbg_tlv_free(struct iwl_trans *trans)
419 {
420 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp;
421 int i;
422
423 iwl_dbg_tlv_del_timers(trans);
424
425 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) {
426 struct iwl_ucode_tlv **active_reg =
427 &trans->dbg.active_regions[i];
428
429 kfree(*active_reg);
430 *active_reg = NULL;
431 }
432
433 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
434 &trans->dbg.debug_info_tlv_list, list) {
435 list_del(&tlv_node->list);
436 kfree(tlv_node);
437 }
438
439 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
440 struct iwl_dbg_tlv_time_point_data *tp =
441 &trans->dbg.time_point[i];
442
443 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list,
444 list) {
445 list_del(&tlv_node->list);
446 kfree(tlv_node);
447 }
448
449 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list,
450 list) {
451 list_del(&tlv_node->list);
452 kfree(tlv_node);
453 }
454
455 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
456 &tp->active_trig_list, list) {
457 list_del(&tlv_node->list);
458 kfree(tlv_node);
459 }
460
461 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
462 &tp->config_list, list) {
463 list_del(&tlv_node->list);
464 kfree(tlv_node);
465 }
466
467 }
468
469 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++)
470 iwl_dbg_tlv_fragments_free(trans, i);
471 }
472
iwl_dbg_tlv_parse_bin(struct iwl_trans * trans,const u8 * data,size_t len)473 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data,
474 size_t len)
475 {
476 const struct iwl_ucode_tlv *tlv;
477 u32 tlv_len;
478 size_t aligned_tlv_len;
479
480 while (len >= sizeof(*tlv)) {
481 len -= sizeof(*tlv);
482 tlv = (const void *)data;
483
484 tlv_len = le32_to_cpu(tlv->length);
485
486 if (len < tlv_len) {
487 IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
488 len, tlv_len);
489 return -EINVAL;
490 }
491
492 aligned_tlv_len = ALIGN(tlv_len, 4);
493 if (len < aligned_tlv_len) {
494 IWL_ERR(trans, "invalid aligned TLV len: %zd/%zu\n",
495 len, aligned_tlv_len);
496 return -EINVAL;
497 }
498
499 len -= aligned_tlv_len;
500 data += sizeof(*tlv) + aligned_tlv_len;
501
502 iwl_dbg_tlv_alloc(trans, tlv, true);
503 }
504
505 return 0;
506 }
507
iwl_dbg_tlv_load_bin(struct device * dev,struct iwl_trans * trans)508 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans)
509 {
510 const struct firmware *fw;
511 const char *yoyo_bin = "iwl-debug-yoyo.bin";
512 int res;
513
514 if (!iwlwifi_mod_params.enable_ini ||
515 trans->mac_cfg->device_family <= IWL_DEVICE_FAMILY_8000)
516 return;
517
518 res = firmware_request_nowarn(&fw, yoyo_bin, dev);
519 IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin);
520
521 if (res)
522 return;
523
524 trans->dbg.yoyo_bin_loaded = true;
525
526 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size);
527
528 release_firmware(fw);
529 }
530
iwl_dbg_tlv_init(struct iwl_trans * trans)531 void iwl_dbg_tlv_init(struct iwl_trans *trans)
532 {
533 int i;
534
535 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list);
536 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list);
537
538 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
539 struct iwl_dbg_tlv_time_point_data *tp =
540 &trans->dbg.time_point[i];
541
542 INIT_LIST_HEAD(&tp->trig_list);
543 INIT_LIST_HEAD(&tp->hcmd_list);
544 INIT_LIST_HEAD(&tp->active_trig_list);
545 INIT_LIST_HEAD(&tp->config_list);
546 }
547 }
548
iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime * fwrt,struct iwl_dram_data * frag,u32 pages)549 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt,
550 struct iwl_dram_data *frag, u32 pages)
551 {
552 void *block = NULL;
553 dma_addr_t physical;
554
555 if (!frag || frag->size || !pages)
556 return -EIO;
557
558 /*
559 * We try to allocate as many pages as we can, starting with
560 * the requested amount and going down until we can allocate
561 * something. Because of DIV_ROUND_UP(), pages will never go
562 * down to 0 and stop the loop, so stop when pages reaches 1,
563 * which is too small anyway.
564 */
565 while (pages > 1) {
566 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE,
567 &physical,
568 GFP_KERNEL | __GFP_NOWARN);
569 if (block)
570 break;
571
572 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n",
573 pages * PAGE_SIZE);
574
575 pages = DIV_ROUND_UP(pages, 2);
576 }
577
578 if (!block)
579 return -ENOMEM;
580
581 frag->physical = physical;
582 frag->block = block;
583 frag->size = pages * PAGE_SIZE;
584
585 return pages;
586 }
587
iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime * fwrt,enum iwl_fw_ini_allocation_id alloc_id)588 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt,
589 enum iwl_fw_ini_allocation_id alloc_id)
590 {
591 struct iwl_fw_mon *fw_mon;
592 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
593 u32 num_frags, remain_pages, frag_pages;
594 int i;
595
596 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
597 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
598 return -EIO;
599
600 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
601 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
602
603 if (fw_mon->num_frags) {
604 for (i = 0; i < fw_mon->num_frags; i++)
605 memset(fw_mon->frags[i].block, 0,
606 fw_mon->frags[i].size);
607 return 0;
608 }
609
610 if (fw_mon_cfg->buf_location !=
611 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH))
612 return 0;
613
614 if (!fw_mon_cfg->req_size)
615 return -EIO;
616
617 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num);
618 if (fwrt->trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
619 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
620 return -EIO;
621 num_frags = 1;
622 } else if (fwrt->trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_BZ &&
623 alloc_id > IWL_FW_INI_ALLOCATION_ID_DBGC3) {
624 return -EIO;
625 }
626
627 if (!num_frags)
628 return -EIO;
629
630 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size),
631 PAGE_SIZE);
632 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS);
633 num_frags = min_t(u32, num_frags, remain_pages);
634 frag_pages = DIV_ROUND_UP(remain_pages, num_frags);
635
636 fw_mon->frags = kzalloc_objs(*fw_mon->frags, num_frags);
637 if (!fw_mon->frags)
638 return -ENOMEM;
639
640 for (i = 0; i < num_frags; i++) {
641 int pages = min_t(u32, frag_pages, remain_pages);
642
643 IWL_DEBUG_FW(fwrt,
644 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n",
645 alloc_id, i, pages * PAGE_SIZE);
646
647 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i],
648 pages);
649 if (pages < 0) {
650 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) -
651 (remain_pages * PAGE_SIZE);
652
653 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) {
654 iwl_dbg_tlv_fragments_free(fwrt->trans,
655 alloc_id);
656 return pages;
657 }
658 break;
659 }
660
661 remain_pages -= pages;
662 fw_mon->num_frags++;
663 }
664
665 return 0;
666 }
667
iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime * fwrt,enum iwl_fw_ini_allocation_id alloc_id)668 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt,
669 enum iwl_fw_ini_allocation_id alloc_id)
670 {
671 struct iwl_fw_mon *fw_mon;
672 u32 remain_frags, num_commands;
673 int i, fw_mon_idx = 0;
674
675 if (!fw_has_capa(&fwrt->fw->ucode_capa,
676 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP))
677 return 0;
678
679 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
680 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
681 return -EIO;
682
683 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
684 IWL_FW_INI_LOCATION_DRAM_PATH)
685 return 0;
686
687 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
688
689 /* the first fragment of DBGC1 is given to the FW via register
690 * or context info
691 */
692 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1)
693 fw_mon_idx++;
694
695 remain_frags = fw_mon->num_frags - fw_mon_idx;
696 if (!remain_frags)
697 return 0;
698
699 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS);
700
701 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n",
702 alloc_id);
703
704 for (i = 0; i < num_commands; i++) {
705 u32 num_frags = min_t(u32, remain_frags,
706 BUF_ALLOC_MAX_NUM_FRAGS);
707 struct iwl_buf_alloc_cmd data = {
708 .alloc_id = cpu_to_le32(alloc_id),
709 .num_frags = cpu_to_le32(num_frags),
710 .buf_location =
711 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH),
712 };
713 struct iwl_host_cmd hcmd = {
714 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION),
715 .data[0] = &data,
716 .len[0] = sizeof(data),
717 .flags = CMD_SEND_IN_RFKILL,
718 };
719 int ret, j;
720
721 for (j = 0; j < num_frags; j++) {
722 struct iwl_buf_alloc_frag *frag = &data.frags[j];
723 struct iwl_dram_data *fw_mon_frag =
724 &fw_mon->frags[fw_mon_idx++];
725
726 frag->addr = cpu_to_le64(fw_mon_frag->physical);
727 frag->size = cpu_to_le32(fw_mon_frag->size);
728 }
729 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
730 if (ret)
731 return ret;
732
733 remain_frags -= num_frags;
734 }
735
736 return 0;
737 }
738
iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime * fwrt)739 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt)
740 {
741 int ret, i;
742
743 if (fw_has_capa(&fwrt->fw->ucode_capa,
744 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT))
745 return;
746
747 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
748 ret = iwl_dbg_tlv_apply_buffer(fwrt, i);
749 if (ret)
750 IWL_WARN(fwrt,
751 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n",
752 i, ret);
753 }
754 }
755
iwl_dbg_tlv_update_dram(struct iwl_fw_runtime * fwrt,enum iwl_fw_ini_allocation_id alloc_id,struct iwl_dram_info * dram_info)756 static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt,
757 enum iwl_fw_ini_allocation_id alloc_id,
758 struct iwl_dram_info *dram_info)
759 {
760 struct iwl_fw_mon *fw_mon;
761 u32 remain_frags, num_frags;
762 int j, fw_mon_idx = 0;
763 struct iwl_buf_alloc_cmd *data;
764
765 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
766 IWL_FW_INI_LOCATION_DRAM_PATH) {
767 IWL_DEBUG_FW(fwrt, "WRT: alloc_id %u location is not in DRAM_PATH\n",
768 alloc_id);
769 return -1;
770 }
771
772 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
773
774 /* the first fragment of DBGC1 is given to the FW via register
775 * or context info
776 */
777 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1)
778 fw_mon_idx++;
779
780 remain_frags = fw_mon->num_frags - fw_mon_idx;
781 if (!remain_frags)
782 return -1;
783
784 num_frags = min_t(u32, remain_frags, BUF_ALLOC_MAX_NUM_FRAGS);
785 data = &dram_info->dram_frags[alloc_id - 1];
786 data->alloc_id = cpu_to_le32(alloc_id);
787 data->num_frags = cpu_to_le32(num_frags);
788 data->buf_location = cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH);
789
790 IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n",
791 cpu_to_le32(alloc_id), cpu_to_le32(num_frags));
792
793 for (j = 0; j < num_frags; j++) {
794 struct iwl_buf_alloc_frag *frag = &data->frags[j];
795 struct iwl_dram_data *fw_mon_frag = &fw_mon->frags[fw_mon_idx++];
796
797 frag->addr = cpu_to_le64(fw_mon_frag->physical);
798 frag->size = cpu_to_le32(fw_mon_frag->size);
799 IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n");
800 IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n",
801 j, cpu_to_le64(fw_mon_frag->physical),
802 cpu_to_le32(fw_mon_frag->size));
803 }
804 return 0;
805 }
806
iwl_dbg_tlv_update_drams(struct iwl_fw_runtime * fwrt)807 static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt)
808 {
809 int ret, i;
810 bool dram_alloc = false;
811 struct iwl_dram_data *frags =
812 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0];
813 struct iwl_dram_info *dram_info;
814
815 if (!frags || !frags->block)
816 return;
817
818 dram_info = frags->block;
819
820 if (!fw_has_capa(&fwrt->fw->ucode_capa,
821 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT))
822 return;
823
824 memset(dram_info, 0, sizeof(*dram_info));
825
826 for (i = IWL_FW_INI_ALLOCATION_ID_DBGC1;
827 i < IWL_FW_INI_ALLOCATION_NUM; i++) {
828 if (fwrt->trans->dbg.fw_mon_cfg[i].buf_location ==
829 IWL_FW_INI_LOCATION_INVALID)
830 continue;
831
832 ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info);
833 if (!ret)
834 dram_alloc = true;
835 else
836 IWL_INFO(fwrt,
837 "WRT: Failed to set DRAM buffer for alloc id %d, ret=%d\n",
838 i, ret);
839 }
840
841 if (dram_alloc) {
842 dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD);
843 dram_info->second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD);
844 }
845 }
846
iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime * fwrt,struct list_head * hcmd_list)847 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt,
848 struct list_head *hcmd_list)
849 {
850 struct iwl_dbg_tlv_node *node;
851
852 list_for_each_entry(node, hcmd_list, list) {
853 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data;
854 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd;
855 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd);
856 struct iwl_host_cmd cmd = {
857 .id = WIDE_ID(hcmd_data->group, hcmd_data->id),
858 .len = { hcmd_len, },
859 .data = { hcmd_data->data, },
860 };
861
862 iwl_trans_send_cmd(fwrt->trans, &cmd);
863 }
864 }
865
iwl_dbg_tlv_apply_config(struct iwl_fw_runtime * fwrt,struct list_head * conf_list)866 static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt,
867 struct list_head *conf_list)
868 {
869 struct iwl_dbg_tlv_node *node;
870
871 list_for_each_entry(node, conf_list, list) {
872 struct iwl_fw_ini_conf_set_tlv *config_list = (void *)node->tlv.data;
873 u32 count, address, value;
874 u32 len = (le32_to_cpu(node->tlv.length) - sizeof(*config_list)) / 8;
875 u32 type = le32_to_cpu(config_list->set_type);
876 u32 offset = le32_to_cpu(config_list->addr_offset);
877
878 switch (type) {
879 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_PERIPHERY_MAC: {
880 if (!iwl_trans_grab_nic_access(fwrt->trans)) {
881 IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n");
882 IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n");
883 continue;
884 }
885 IWL_DEBUG_FW(fwrt, "WRT: MAC PERIPHERY config len: len %u\n", len);
886 for (count = 0; count < len; count++) {
887 address = le32_to_cpu(config_list->addr_val[count].address);
888 value = le32_to_cpu(config_list->addr_val[count].value);
889 iwl_trans_write_prph(fwrt->trans, address + offset, value);
890 }
891 iwl_trans_release_nic_access(fwrt->trans);
892 break;
893 }
894 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_MEMORY: {
895 for (count = 0; count < len; count++) {
896 address = le32_to_cpu(config_list->addr_val[count].address);
897 value = le32_to_cpu(config_list->addr_val[count].value);
898 iwl_trans_write_mem32(fwrt->trans, address + offset, value);
899 IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n",
900 count, address, value);
901 }
902 break;
903 }
904 case IWL_FW_INI_CONFIG_SET_TYPE_CSR: {
905 for (count = 0; count < len; count++) {
906 address = le32_to_cpu(config_list->addr_val[count].address);
907 value = le32_to_cpu(config_list->addr_val[count].value);
908 iwl_write32(fwrt->trans, address + offset, value);
909 IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n",
910 count, address, value);
911 }
912 break;
913 }
914 case IWL_FW_INI_CONFIG_SET_TYPE_DBGC_DRAM_ADDR: {
915 struct iwl_dbgc1_info dram_info = {};
916 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0];
917 __le64 dram_base_addr;
918 __le32 dram_size;
919 u64 dram_addr;
920 u32 ret;
921
922 if (!frags)
923 break;
924
925 dram_base_addr = cpu_to_le64(frags->physical);
926 dram_size = cpu_to_le32(frags->size);
927 dram_addr = le64_to_cpu(dram_base_addr);
928
929 IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n",
930 dram_base_addr, dram_size);
931 IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n",
932 le32_to_cpu(config_list->addr_offset));
933 for (count = 0; count < len; count++) {
934 address = le32_to_cpu(config_list->addr_val[count].address);
935 dram_info.dbgc1_add_lsb =
936 cpu_to_le32((dram_addr & 0x00000000FFFFFFFFULL) + 0x400);
937 dram_info.dbgc1_add_msb =
938 cpu_to_le32((dram_addr & 0xFFFFFFFF00000000ULL) >> 32);
939 dram_info.dbgc1_size = cpu_to_le32(le32_to_cpu(dram_size) - 0x400);
940 ret = iwl_trans_write_mem(fwrt->trans,
941 address + offset, &dram_info, 4);
942 if (ret) {
943 IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n");
944 break;
945 }
946 }
947 break;
948 }
949 case IWL_FW_INI_CONFIG_SET_TYPE_PERIPH_SCRATCH_HWM: {
950 u32 debug_token_config =
951 le32_to_cpu(config_list->addr_val[0].value);
952
953 IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n",
954 debug_token_config);
955 fwrt->trans->dbg.ucode_preset = debug_token_config;
956 break;
957 }
958 default:
959 break;
960 }
961 }
962 }
963
iwl_dbg_tlv_periodic_trig_handler(struct timer_list * t)964 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t)
965 {
966 struct iwl_dbg_tlv_timer_node *timer_node =
967 timer_container_of(timer_node, t, timer);
968 struct iwl_fwrt_dump_data dump_data = {
969 .trig = (void *)timer_node->tlv->data,
970 };
971 int ret;
972
973 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false);
974 if (!ret || ret == -EBUSY) {
975 u32 occur = le32_to_cpu(dump_data.trig->occurrences);
976 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]);
977
978 if (!occur)
979 return;
980
981 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval));
982 }
983 }
984
iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime * fwrt)985 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt)
986 {
987 struct iwl_dbg_tlv_node *node;
988 struct list_head *trig_list =
989 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
990
991 list_for_each_entry(node, trig_list, list) {
992 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data;
993 struct iwl_dbg_tlv_timer_node *timer_node;
994 u32 occur = le32_to_cpu(trig->occurrences), collect_interval;
995 u32 min_interval = 100;
996
997 if (!occur)
998 continue;
999
1000 /* make sure there is at least one dword of data for the
1001 * interval value
1002 */
1003 if (le32_to_cpu(node->tlv.length) <
1004 sizeof(*trig) + sizeof(__le32)) {
1005 IWL_ERR(fwrt,
1006 "WRT: Invalid periodic trigger data was not given\n");
1007 continue;
1008 }
1009
1010 if (le32_to_cpu(trig->data[0]) < min_interval) {
1011 IWL_WARN(fwrt,
1012 "WRT: Override min interval from %u to %u msec\n",
1013 le32_to_cpu(trig->data[0]), min_interval);
1014 trig->data[0] = cpu_to_le32(min_interval);
1015 }
1016
1017 collect_interval = le32_to_cpu(trig->data[0]);
1018
1019 timer_node = kzalloc_obj(*timer_node);
1020 if (!timer_node) {
1021 IWL_ERR(fwrt,
1022 "WRT: Failed to allocate periodic trigger\n");
1023 continue;
1024 }
1025
1026 timer_node->fwrt = fwrt;
1027 timer_node->tlv = &node->tlv;
1028 timer_setup(&timer_node->timer,
1029 iwl_dbg_tlv_periodic_trig_handler, 0);
1030
1031 list_add_tail(&timer_node->list,
1032 &fwrt->trans->dbg.periodic_trig_list);
1033
1034 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n");
1035
1036 mod_timer(&timer_node->timer,
1037 jiffies + msecs_to_jiffies(collect_interval));
1038 }
1039 }
1040
is_trig_data_contained(const struct iwl_ucode_tlv * new,const struct iwl_ucode_tlv * old)1041 static bool is_trig_data_contained(const struct iwl_ucode_tlv *new,
1042 const struct iwl_ucode_tlv *old)
1043 {
1044 const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data;
1045 const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data;
1046 const __le32 *new_data = new_trig->data, *old_data = old_trig->data;
1047 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data);
1048 u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data);
1049 int i, j;
1050
1051 for (i = 0; i < new_dwords_num; i++) {
1052 bool match = false;
1053
1054 for (j = 0; j < old_dwords_num; j++) {
1055 if (new_data[i] == old_data[j]) {
1056 match = true;
1057 break;
1058 }
1059 }
1060 if (!match)
1061 return false;
1062 }
1063
1064 return true;
1065 }
1066
iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime * fwrt,struct iwl_ucode_tlv * trig_tlv,struct iwl_dbg_tlv_node * node)1067 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt,
1068 struct iwl_ucode_tlv *trig_tlv,
1069 struct iwl_dbg_tlv_node *node)
1070 {
1071 struct iwl_ucode_tlv *node_tlv = &node->tlv;
1072 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data;
1073 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
1074 u32 policy = le32_to_cpu(trig->apply_policy);
1075 u32 size = le32_to_cpu(trig_tlv->length);
1076 u32 trig_data_len = size - sizeof(*trig);
1077 u32 offset = 0;
1078
1079 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) {
1080 u32 data_len = le32_to_cpu(node_tlv->length) -
1081 sizeof(*node_trig);
1082
1083 IWL_DEBUG_FW(fwrt,
1084 "WRT: Appending trigger data (time point %u)\n",
1085 le32_to_cpu(trig->time_point));
1086
1087 offset += data_len;
1088 size += data_len;
1089 } else {
1090 IWL_DEBUG_FW(fwrt,
1091 "WRT: Overriding trigger data (time point %u)\n",
1092 le32_to_cpu(trig->time_point));
1093 }
1094
1095 if (size != le32_to_cpu(node_tlv->length)) {
1096 struct list_head *prev = node->list.prev;
1097 struct iwl_dbg_tlv_node *tmp;
1098
1099 list_del(&node->list);
1100
1101 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL);
1102 if (!tmp) {
1103 IWL_WARN(fwrt,
1104 "WRT: No memory to override trigger (time point %u)\n",
1105 le32_to_cpu(trig->time_point));
1106
1107 list_add(&node->list, prev);
1108
1109 return -ENOMEM;
1110 }
1111
1112 list_add(&tmp->list, prev);
1113 node_tlv = &tmp->tlv;
1114 node_trig = (void *)node_tlv->data;
1115 }
1116
1117 memcpy((u8 *)node_trig->data + offset, trig->data, trig_data_len);
1118 node_tlv->length = cpu_to_le32(size);
1119
1120 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) {
1121 IWL_DEBUG_FW(fwrt,
1122 "WRT: Overriding trigger configuration (time point %u)\n",
1123 le32_to_cpu(trig->time_point));
1124
1125 /* the first 11 dwords are configuration related */
1126 memcpy(node_trig, trig, sizeof(__le32) * 11);
1127 }
1128
1129 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) {
1130 IWL_DEBUG_FW(fwrt,
1131 "WRT: Overriding trigger regions (time point %u)\n",
1132 le32_to_cpu(trig->time_point));
1133
1134 node_trig->regions_mask = trig->regions_mask;
1135 } else {
1136 IWL_DEBUG_FW(fwrt,
1137 "WRT: Appending trigger regions (time point %u)\n",
1138 le32_to_cpu(trig->time_point));
1139
1140 node_trig->regions_mask |= trig->regions_mask;
1141 }
1142
1143 return 0;
1144 }
1145
1146 static int
iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime * fwrt,struct list_head * trig_list,struct iwl_ucode_tlv * trig_tlv)1147 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt,
1148 struct list_head *trig_list,
1149 struct iwl_ucode_tlv *trig_tlv)
1150 {
1151 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
1152 struct iwl_dbg_tlv_node *node, *match = NULL;
1153 u32 policy = le32_to_cpu(trig->apply_policy);
1154
1155 list_for_each_entry(node, trig_list, list) {
1156 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT))
1157 break;
1158
1159 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) ||
1160 is_trig_data_contained(trig_tlv, &node->tlv)) {
1161 match = node;
1162 break;
1163 }
1164 }
1165
1166 if (!match) {
1167 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n",
1168 le32_to_cpu(trig->time_point));
1169 if (!iwl_dbg_tlv_add(trig_tlv, trig_list))
1170 return -ENOMEM;
1171 return 0;
1172 }
1173
1174 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match);
1175 }
1176
1177 static void
iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime * fwrt,struct iwl_dbg_tlv_time_point_data * tp)1178 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt,
1179 struct iwl_dbg_tlv_time_point_data *tp)
1180 {
1181 struct iwl_dbg_tlv_node *node;
1182 struct list_head *trig_list = &tp->trig_list;
1183 struct list_head *active_trig_list = &tp->active_trig_list;
1184
1185 list_for_each_entry(node, trig_list, list) {
1186 struct iwl_ucode_tlv *tlv = &node->tlv;
1187
1188 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv);
1189 }
1190 }
1191
iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,union iwl_dbg_tlv_tp_data * tp_data,u32 trig_data)1192 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt,
1193 struct iwl_fwrt_dump_data *dump_data,
1194 union iwl_dbg_tlv_tp_data *tp_data,
1195 u32 trig_data)
1196 {
1197 struct iwl_rx_packet *pkt = tp_data->fw_pkt;
1198 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data;
1199
1200 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd &&
1201 pkt->hdr.group_id == wanted_hdr->group_id)) {
1202 struct iwl_rx_packet *fw_pkt =
1203 kmemdup(pkt,
1204 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt),
1205 GFP_ATOMIC);
1206
1207 if (!fw_pkt)
1208 return false;
1209
1210 dump_data->fw_pkt = fw_pkt;
1211
1212 return true;
1213 }
1214
1215 return false;
1216 }
1217
1218 static int
iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime * fwrt,bool sync,struct list_head * active_trig_list,union iwl_dbg_tlv_tp_data * tp_data,bool (* data_check)(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,union iwl_dbg_tlv_tp_data * tp_data,u32 trig_data))1219 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync,
1220 struct list_head *active_trig_list,
1221 union iwl_dbg_tlv_tp_data *tp_data,
1222 bool (*data_check)(struct iwl_fw_runtime *fwrt,
1223 struct iwl_fwrt_dump_data *dump_data,
1224 union iwl_dbg_tlv_tp_data *tp_data,
1225 u32 trig_data))
1226 {
1227 struct iwl_dbg_tlv_node *node;
1228
1229 list_for_each_entry(node, active_trig_list, list) {
1230 struct iwl_fwrt_dump_data dump_data = {
1231 .trig = (void *)node->tlv.data,
1232 };
1233 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig,
1234 data);
1235 int ret, i;
1236 u32 tp = le32_to_cpu(dump_data.trig->time_point);
1237
1238
1239 if (!num_data) {
1240 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
1241 if (ret)
1242 return ret;
1243 }
1244
1245 for (i = 0; i < num_data; i++) {
1246 if (!data_check ||
1247 data_check(fwrt, &dump_data, tp_data,
1248 le32_to_cpu(dump_data.trig->data[i]))) {
1249 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
1250 if (ret)
1251 return ret;
1252
1253 break;
1254 }
1255 }
1256
1257 fwrt->trans->dbg.restart_required = false;
1258
1259 if (fwrt->trans->mac_cfg->device_family ==
1260 IWL_DEVICE_FAMILY_9000) {
1261 fwrt->trans->dbg.restart_required = true;
1262 } else if (tp == IWL_FW_INI_TIME_POINT_FW_ASSERT &&
1263 fwrt->trans->dbg.last_tp_resetfw ==
1264 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) {
1265 fwrt->trans->dbg.restart_required = false;
1266 fwrt->trans->dbg.last_tp_resetfw = 0xFF;
1267 } else if (le32_to_cpu(dump_data.trig->reset_fw) ==
1268 IWL_FW_INI_RESET_FW_MODE_STOP_AND_RELOAD_FW) {
1269 fwrt->trans->dbg.restart_required = true;
1270 } else if (le32_to_cpu(dump_data.trig->reset_fw) ==
1271 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) {
1272 fwrt->trans->dbg.restart_required = false;
1273 fwrt->trans->dbg.last_tp_resetfw =
1274 le32_to_cpu(dump_data.trig->reset_fw);
1275 } else if (le32_to_cpu(dump_data.trig->reset_fw) ==
1276 IWL_FW_INI_RESET_FW_MODE_NOTHING) {
1277 /* nothing */
1278 } else {
1279 IWL_ERR(fwrt, "WRT: wrong resetfw %d\n",
1280 le32_to_cpu(dump_data.trig->reset_fw));
1281 }
1282 }
1283 return 0;
1284 }
1285
iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime * fwrt)1286 void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
1287 {
1288 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1289 int ret, i;
1290 u32 failed_alloc = 0;
1291
1292 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) {
1293 IWL_DEBUG_FW(fwrt,
1294 "WRT: Generating active triggers list, domain 0x%x\n",
1295 fwrt->trans->dbg.domains_bitmap);
1296
1297 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1298 struct iwl_dbg_tlv_time_point_data *tp =
1299 &fwrt->trans->dbg.time_point[i];
1300
1301 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
1302 }
1303 } else if (*ini_dest != IWL_FW_INI_LOCATION_DRAM_PATH) {
1304 /* For DRAM, go through the loop below to clear all the buffers
1305 * properly on restart, otherwise garbage may be left there and
1306 * leak into new debug dumps.
1307 */
1308 return;
1309 }
1310
1311 *ini_dest = IWL_FW_INI_LOCATION_INVALID;
1312 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
1313 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
1314 &fwrt->trans->dbg.fw_mon_cfg[i];
1315 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location);
1316
1317 if (dest == IWL_FW_INI_LOCATION_INVALID) {
1318 failed_alloc |= BIT(i);
1319 continue;
1320 }
1321
1322 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID)
1323 *ini_dest = dest;
1324
1325 if (dest != *ini_dest)
1326 continue;
1327
1328 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i);
1329
1330 if (ret) {
1331 IWL_WARN(fwrt,
1332 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n",
1333 i, ret);
1334 failed_alloc |= BIT(i);
1335 }
1336 }
1337
1338 if (!failed_alloc)
1339 return;
1340
1341 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) {
1342 struct iwl_fw_ini_region_tlv *reg;
1343 struct iwl_ucode_tlv **active_reg =
1344 &fwrt->trans->dbg.active_regions[i];
1345 u32 reg_type;
1346
1347 if (!*active_reg) {
1348 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1349 continue;
1350 }
1351
1352 reg = (void *)(*active_reg)->data;
1353 reg_type = reg->type;
1354
1355 if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER ||
1356 !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc))
1357 continue;
1358
1359 IWL_DEBUG_FW(fwrt,
1360 "WRT: removing allocation id %d from region id %d\n",
1361 le32_to_cpu(reg->dram_alloc_id), i);
1362
1363 failed_alloc &= ~BIT(le32_to_cpu(reg->dram_alloc_id));
1364 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1365
1366 kfree(*active_reg);
1367 *active_reg = NULL;
1368 }
1369 }
1370
_iwl_dbg_tlv_time_point(struct iwl_fw_runtime * fwrt,enum iwl_fw_ini_time_point tp_id,union iwl_dbg_tlv_tp_data * tp_data,bool sync)1371 void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt,
1372 enum iwl_fw_ini_time_point tp_id,
1373 union iwl_dbg_tlv_tp_data *tp_data,
1374 bool sync)
1375 {
1376 struct list_head *hcmd_list, *trig_list, *conf_list;
1377
1378 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1379 tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
1380 tp_id >= IWL_FW_INI_TIME_POINT_NUM)
1381 return;
1382
1383 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1384 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1385 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list;
1386
1387 switch (tp_id) {
1388 case IWL_FW_INI_TIME_POINT_EARLY:
1389 iwl_dbg_tlv_init_cfg(fwrt);
1390 iwl_dbg_tlv_update_drams(fwrt);
1391 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1392 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1393 break;
1394 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE:
1395 iwl_dbg_tlv_apply_buffers(fwrt);
1396 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1397 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1398 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1399 break;
1400 case IWL_FW_INI_TIME_POINT_PERIODIC:
1401 iwl_dbg_tlv_set_periodic_trigs(fwrt);
1402 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1403 break;
1404 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF:
1405 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS:
1406 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION:
1407 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1408 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data,
1409 iwl_dbg_tlv_check_fw_pkt);
1410 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1411 break;
1412 default:
1413 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1414 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1415 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1416 break;
1417 }
1418 }
1419 IWL_EXPORT_SYMBOL(_iwl_dbg_tlv_time_point);
1420