1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver 4 // with eint support. 5 // 6 // Copyright (c) 2012 Samsung Electronics Co., Ltd. 7 // http://www.samsung.com 8 // Copyright (c) 2012 Linaro Ltd 9 // http://www.linaro.org 10 // Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> 11 // 12 // This file contains the Samsung Exynos specific information required by the 13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of 14 // external gpio and wakeup interrupt support. 15 16 #include <linux/slab.h> 17 #include <linux/soc/samsung/exynos-regs-pmu.h> 18 19 #include "pinctrl-samsung.h" 20 #include "pinctrl-exynos.h" 21 22 static const struct samsung_pin_bank_type bank_type_off = { 23 .fld_width = { 4, 1, 2, 2, 2, 2, }, 24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 25 }; 26 27 static const struct samsung_pin_bank_type bank_type_alive = { 28 .fld_width = { 4, 1, 2, 2, }, 29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 30 }; 31 32 /* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */ 33 static const struct samsung_pin_bank_type exynos5433_bank_type_off = { 34 .fld_width = { 4, 1, 2, 4, 2, 2, }, 35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 36 }; 37 38 static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { 39 .fld_width = { 4, 1, 2, 4, }, 40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 41 }; 42 43 /* 44 * Bank type for alive type. Bit fields: 45 * CON: 4, DAT: 1, PUD: 2, DRV: 3 46 */ 47 static const struct samsung_pin_bank_type exynos7870_bank_type_alive = { 48 .fld_width = { 4, 1, 2, 3, }, 49 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 50 }; 51 52 /* 53 * Bank type for non-alive type. Bit fields: 54 * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 55 */ 56 static const struct samsung_pin_bank_type exynos850_bank_type_off = { 57 .fld_width = { 4, 1, 4, 4, 2, 4, }, 58 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 59 }; 60 61 /* 62 * Bank type for alive type. Bit fields: 63 * CON: 4, DAT: 1, PUD: 4, DRV: 4 64 */ 65 static const struct samsung_pin_bank_type exynos850_bank_type_alive = { 66 .fld_width = { 4, 1, 4, 4, }, 67 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 68 }; 69 70 /* 71 * Bank type for non-alive type. Bit fields: 72 * CON: 4, DAT: 1, PUD: 2, DRV: 3, CONPDN: 2, PUDPDN: 2 73 */ 74 static const struct samsung_pin_bank_type exynos8895_bank_type_off = { 75 .fld_width = { 4, 1, 2, 3, 2, 2, }, 76 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 77 }; 78 79 /* Pad retention control code for accessing PMU regmap */ 80 static atomic_t exynos_shared_retention_refcnt; 81 82 /* pin banks of exynos2200 pin-controller - ALIVE */ 83 static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst = { 84 EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00), 85 EXYNOS850_PIN_BANK_EINTW(8, 0x20, "gpa1", 0x04), 86 EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa2", 0x08), 87 EXYNOS850_PIN_BANK_EINTW(8, 0x60, "gpa3", 0x0c), 88 EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpa4", 0x10), 89 EXYNOS_PIN_BANK_EINTN(4, 0xa0, "gpq0"), 90 EXYNOS_PIN_BANK_EINTN(2, 0xc0, "gpq1"), 91 EXYNOS_PIN_BANK_EINTN(2, 0xe0, "gpq2"), 92 }; 93 94 /* pin banks of exynos2200 pin-controller - CMGP */ 95 static const struct samsung_pin_bank_data exynos2200_pin_banks1[] __initconst = { 96 EXYNOS850_PIN_BANK_EINTW(2, 0x0, "gpm0", 0x00), 97 EXYNOS850_PIN_BANK_EINTW(2, 0x20, "gpm1", 0x04), 98 EXYNOS850_PIN_BANK_EINTW(2, 0x40, "gpm2", 0x08), 99 EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpm3", 0x0c), 100 EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpm4", 0x10), 101 EXYNOS850_PIN_BANK_EINTW(2, 0xa0, "gpm5", 0x14), 102 EXYNOS850_PIN_BANK_EINTW(2, 0xc0, "gpm6", 0x18), 103 EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpm7", 0x1c), 104 EXYNOS850_PIN_BANK_EINTW(2, 0x100, "gpm8", 0x20), 105 EXYNOS850_PIN_BANK_EINTW(2, 0x120, "gpm9", 0x24), 106 EXYNOS850_PIN_BANK_EINTW(2, 0x140, "gpm10", 0x28), 107 EXYNOS850_PIN_BANK_EINTW(2, 0x160, "gpm11", 0x2c), 108 EXYNOS850_PIN_BANK_EINTW(2, 0x180, "gpm12", 0x30), 109 EXYNOS850_PIN_BANK_EINTW(2, 0x1a0, "gpm13", 0x34), 110 EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38), 111 EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c), 112 EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40), 113 EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44), 114 EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm20", 0x48), 115 EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm21", 0x4c), 116 EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm22", 0x50), 117 EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpm23", 0x54), 118 EXYNOS850_PIN_BANK_EINTW(1, 0x2c0, "gpm24", 0x58), 119 }; 120 121 /* pin banks of exynos2200 pin-controller - HSI1 */ 122 static const struct samsung_pin_bank_data exynos2200_pin_banks2[] __initconst = { 123 EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpf0", 0x00), 124 }; 125 126 /* pin banks of exynos2200 pin-controller - UFS */ 127 static const struct samsung_pin_bank_data exynos2200_pin_banks3[] __initconst = { 128 EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpf1", 0x00), 129 }; 130 131 /* pin banks of exynos2200 pin-controller - HSI1UFS */ 132 static const struct samsung_pin_bank_data exynos2200_pin_banks4[] __initconst = { 133 EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gpf2", 0x00), 134 }; 135 136 /* pin banks of exynos2200 pin-controller - PERIC0 */ 137 static const struct samsung_pin_bank_data exynos2200_pin_banks5[] __initconst = { 138 EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpb0", 0x00), 139 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpb1", 0x04), 140 EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpb2", 0x08), 141 EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpb3", 0x0c), 142 EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10), 143 EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpc0", 0x14), 144 EXYNOS850_PIN_BANK_EINTG(2, 0xc0, "gpc1", 0x18), 145 EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc2", 0x1c), 146 EXYNOS850_PIN_BANK_EINTG(7, 0x100, "gpg1", 0x20), 147 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpg2", 0x24), 148 }; 149 150 /* pin banks of exynos2200 pin-controller - PERIC1 */ 151 static const struct samsung_pin_bank_data exynos2200_pin_banks6[] __initconst = { 152 EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp7", 0x00), 153 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp8", 0x04), 154 EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp9", 0x08), 155 EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp10", 0x0c), 156 }; 157 158 /* pin banks of exynos2200 pin-controller - PERIC2 */ 159 static const struct samsung_pin_bank_data exynos2200_pin_banks7[] __initconst = { 160 EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp0", 0x00), 161 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04), 162 EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08), 163 EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp3", 0x0c), 164 EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp5", 0x10), 165 EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp6", 0x14), 166 EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp11", 0x18), 167 EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc3", 0x1c), 168 EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpc4", 0x20), 169 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpc5", 0x24), 170 EXYNOS850_PIN_BANK_EINTG(2, 0x140, "gpc6", 0x28), 171 EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpc7", 0x2c), 172 EXYNOS850_PIN_BANK_EINTG(2, 0x180, "gpc8", 0x30), 173 EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpc9", 0x34), 174 EXYNOS850_PIN_BANK_EINTG(5, 0x1c0, "gpg0", 0x38), 175 }; 176 177 /* pin banks of exynos2200 pin-controller - VTS */ 178 static const struct samsung_pin_bank_data exynos2200_pin_banks8[] __initconst = { 179 EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpv0", 0x00), 180 }; 181 182 static const struct samsung_pin_ctrl exynos2200_pin_ctrl[] = { 183 { 184 /* pin-controller instance 0 ALIVE data */ 185 .pin_banks = exynos2200_pin_banks0, 186 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks0), 187 .eint_gpio_init = exynos_eint_gpio_init, 188 .eint_wkup_init = exynos_eint_wkup_init, 189 .suspend = exynos_pinctrl_suspend, 190 .resume = exynos_pinctrl_resume, 191 }, { 192 /* pin-controller instance 1 CMGP data */ 193 .pin_banks = exynos2200_pin_banks1, 194 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks1), 195 .eint_gpio_init = exynos_eint_gpio_init, 196 .eint_wkup_init = exynos_eint_wkup_init, 197 .suspend = exynos_pinctrl_suspend, 198 .resume = exynos_pinctrl_resume, 199 }, { 200 /* pin-controller instance 2 HSI1 data */ 201 .pin_banks = exynos2200_pin_banks2, 202 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks2), 203 }, { 204 /* pin-controller instance 3 UFS data */ 205 .pin_banks = exynos2200_pin_banks3, 206 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks3), 207 .eint_gpio_init = exynos_eint_gpio_init, 208 .suspend = exynos_pinctrl_suspend, 209 .resume = exynos_pinctrl_resume, 210 }, { 211 /* pin-controller instance 4 HSI1UFS data */ 212 .pin_banks = exynos2200_pin_banks4, 213 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks4), 214 .eint_gpio_init = exynos_eint_gpio_init, 215 .suspend = exynos_pinctrl_suspend, 216 .resume = exynos_pinctrl_resume, 217 }, { 218 /* pin-controller instance 5 PERIC0 data */ 219 .pin_banks = exynos2200_pin_banks5, 220 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks5), 221 .eint_gpio_init = exynos_eint_gpio_init, 222 .suspend = exynos_pinctrl_suspend, 223 .resume = exynos_pinctrl_resume, 224 }, { 225 /* pin-controller instance 6 PERIC1 data */ 226 .pin_banks = exynos2200_pin_banks6, 227 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks6), 228 .eint_gpio_init = exynos_eint_gpio_init, 229 .suspend = exynos_pinctrl_suspend, 230 .resume = exynos_pinctrl_resume, 231 }, { 232 /* pin-controller instance 7 PERIC2 data */ 233 .pin_banks = exynos2200_pin_banks7, 234 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks7), 235 .eint_gpio_init = exynos_eint_gpio_init, 236 .suspend = exynos_pinctrl_suspend, 237 .resume = exynos_pinctrl_resume, 238 }, { 239 /* pin-controller instance 8 VTS data */ 240 .pin_banks = exynos2200_pin_banks8, 241 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks8), 242 }, 243 }; 244 245 const struct samsung_pinctrl_of_match_data exynos2200_of_data __initconst = { 246 .ctrl = exynos2200_pin_ctrl, 247 .num_ctrl = ARRAY_SIZE(exynos2200_pin_ctrl), 248 }; 249 250 /* pin banks of exynos5433 pin-controller - ALIVE */ 251 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = { 252 /* Must start with EINTG banks, ordered by EINT group number. */ 253 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 254 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 255 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 256 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 257 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), 258 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), 259 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), 260 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), 261 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), 262 }; 263 264 /* pin banks of exynos5433 pin-controller - AUD */ 265 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = { 266 /* Must start with EINTG banks, ordered by EINT group number. */ 267 EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 268 EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 269 }; 270 271 /* pin banks of exynos5433 pin-controller - CPIF */ 272 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = { 273 /* Must start with EINTG banks, ordered by EINT group number. */ 274 EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), 275 }; 276 277 /* pin banks of exynos5433 pin-controller - eSE */ 278 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = { 279 /* Must start with EINTG banks, ordered by EINT group number. */ 280 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), 281 }; 282 283 /* pin banks of exynos5433 pin-controller - FINGER */ 284 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = { 285 /* Must start with EINTG banks, ordered by EINT group number. */ 286 EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), 287 }; 288 289 /* pin banks of exynos5433 pin-controller - FSYS */ 290 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = { 291 /* Must start with EINTG banks, ordered by EINT group number. */ 292 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), 293 EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), 294 EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), 295 EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), 296 EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), 297 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), 298 }; 299 300 /* pin banks of exynos5433 pin-controller - IMEM */ 301 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = { 302 /* Must start with EINTG banks, ordered by EINT group number. */ 303 EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), 304 }; 305 306 /* pin banks of exynos5433 pin-controller - NFC */ 307 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = { 308 /* Must start with EINTG banks, ordered by EINT group number. */ 309 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 310 }; 311 312 /* pin banks of exynos5433 pin-controller - PERIC */ 313 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = { 314 /* Must start with EINTG banks, ordered by EINT group number. */ 315 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), 316 EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), 317 EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), 318 EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), 319 EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), 320 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), 321 EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), 322 EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), 323 EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), 324 EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), 325 EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), 326 EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), 327 EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), 328 EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), 329 EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), 330 EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), 331 EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 332 }; 333 334 /* pin banks of exynos5433 pin-controller - TOUCH */ 335 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = { 336 /* Must start with EINTG banks, ordered by EINT group number. */ 337 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 338 }; 339 340 /* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */ 341 static const u32 exynos5433_retention_regs[] = { 342 EXYNOS5433_PAD_RETENTION_TOP_OPTION, 343 EXYNOS5433_PAD_RETENTION_UART_OPTION, 344 EXYNOS5433_PAD_RETENTION_EBIA_OPTION, 345 EXYNOS5433_PAD_RETENTION_EBIB_OPTION, 346 EXYNOS5433_PAD_RETENTION_SPI_OPTION, 347 EXYNOS5433_PAD_RETENTION_MIF_OPTION, 348 EXYNOS5433_PAD_RETENTION_USBXTI_OPTION, 349 EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION, 350 EXYNOS5433_PAD_RETENTION_UFS_OPTION, 351 EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION, 352 }; 353 354 static const struct samsung_retention_data exynos5433_retention_data __initconst = { 355 .regs = exynos5433_retention_regs, 356 .nr_regs = ARRAY_SIZE(exynos5433_retention_regs), 357 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 358 .refcnt = &exynos_shared_retention_refcnt, 359 .init = exynos_retention_init, 360 }; 361 362 /* PMU retention control for audio pins can be tied to audio pin bank */ 363 static const u32 exynos5433_audio_retention_regs[] = { 364 EXYNOS5433_PAD_RETENTION_AUD_OPTION, 365 }; 366 367 static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = { 368 .regs = exynos5433_audio_retention_regs, 369 .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs), 370 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 371 .init = exynos_retention_init, 372 }; 373 374 /* PMU retention control for mmc pins can be tied to fsys pin bank */ 375 static const u32 exynos5433_fsys_retention_regs[] = { 376 EXYNOS5433_PAD_RETENTION_MMC0_OPTION, 377 EXYNOS5433_PAD_RETENTION_MMC1_OPTION, 378 EXYNOS5433_PAD_RETENTION_MMC2_OPTION, 379 }; 380 381 static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = { 382 .regs = exynos5433_fsys_retention_regs, 383 .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs), 384 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 385 .init = exynos_retention_init, 386 }; 387 388 /* 389 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes 390 * ten gpio/pin-mux/pinconfig controllers. 391 */ 392 static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { 393 { 394 /* pin-controller instance 0 data */ 395 .pin_banks = exynos5433_pin_banks0, 396 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0), 397 .eint_wkup_init = exynos_eint_wkup_init, 398 .suspend = exynos_pinctrl_suspend, 399 .resume = exynos_pinctrl_resume, 400 .nr_ext_resources = 1, 401 .retention_data = &exynos5433_retention_data, 402 }, { 403 /* pin-controller instance 1 data */ 404 .pin_banks = exynos5433_pin_banks1, 405 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1), 406 .eint_gpio_init = exynos_eint_gpio_init, 407 .suspend = exynos_pinctrl_suspend, 408 .resume = exynos_pinctrl_resume, 409 .retention_data = &exynos5433_audio_retention_data, 410 }, { 411 /* pin-controller instance 2 data */ 412 .pin_banks = exynos5433_pin_banks2, 413 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2), 414 .eint_gpio_init = exynos_eint_gpio_init, 415 .suspend = exynos_pinctrl_suspend, 416 .resume = exynos_pinctrl_resume, 417 .retention_data = &exynos5433_retention_data, 418 }, { 419 /* pin-controller instance 3 data */ 420 .pin_banks = exynos5433_pin_banks3, 421 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3), 422 .eint_gpio_init = exynos_eint_gpio_init, 423 .suspend = exynos_pinctrl_suspend, 424 .resume = exynos_pinctrl_resume, 425 .retention_data = &exynos5433_retention_data, 426 }, { 427 /* pin-controller instance 4 data */ 428 .pin_banks = exynos5433_pin_banks4, 429 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4), 430 .eint_gpio_init = exynos_eint_gpio_init, 431 .suspend = exynos_pinctrl_suspend, 432 .resume = exynos_pinctrl_resume, 433 .retention_data = &exynos5433_retention_data, 434 }, { 435 /* pin-controller instance 5 data */ 436 .pin_banks = exynos5433_pin_banks5, 437 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5), 438 .eint_gpio_init = exynos_eint_gpio_init, 439 .suspend = exynos_pinctrl_suspend, 440 .resume = exynos_pinctrl_resume, 441 .retention_data = &exynos5433_fsys_retention_data, 442 }, { 443 /* pin-controller instance 6 data */ 444 .pin_banks = exynos5433_pin_banks6, 445 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6), 446 .eint_gpio_init = exynos_eint_gpio_init, 447 .suspend = exynos_pinctrl_suspend, 448 .resume = exynos_pinctrl_resume, 449 .retention_data = &exynos5433_retention_data, 450 }, { 451 /* pin-controller instance 7 data */ 452 .pin_banks = exynos5433_pin_banks7, 453 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7), 454 .eint_gpio_init = exynos_eint_gpio_init, 455 .suspend = exynos_pinctrl_suspend, 456 .resume = exynos_pinctrl_resume, 457 .retention_data = &exynos5433_retention_data, 458 }, { 459 /* pin-controller instance 8 data */ 460 .pin_banks = exynos5433_pin_banks8, 461 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8), 462 .eint_gpio_init = exynos_eint_gpio_init, 463 .suspend = exynos_pinctrl_suspend, 464 .resume = exynos_pinctrl_resume, 465 .retention_data = &exynos5433_retention_data, 466 }, { 467 /* pin-controller instance 9 data */ 468 .pin_banks = exynos5433_pin_banks9, 469 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9), 470 .eint_gpio_init = exynos_eint_gpio_init, 471 .suspend = exynos_pinctrl_suspend, 472 .resume = exynos_pinctrl_resume, 473 .retention_data = &exynos5433_retention_data, 474 }, 475 }; 476 477 const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = { 478 .ctrl = exynos5433_pin_ctrl, 479 .num_ctrl = ARRAY_SIZE(exynos5433_pin_ctrl), 480 }; 481 482 /* pin banks of exynos7 pin-controller - ALIVE */ 483 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { 484 /* Must start with EINTG banks, ordered by EINT group number. */ 485 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 486 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 487 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 488 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 489 }; 490 491 /* pin banks of exynos7 pin-controller - BUS0 */ 492 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { 493 /* Must start with EINTG banks, ordered by EINT group number. */ 494 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 495 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04), 496 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08), 497 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c), 498 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), 499 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 500 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 501 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c), 502 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20), 503 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24), 504 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28), 505 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c), 506 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30), 507 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), 508 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38), 509 }; 510 511 /* pin banks of exynos7 pin-controller - NFC */ 512 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = { 513 /* Must start with EINTG banks, ordered by EINT group number. */ 514 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 515 }; 516 517 /* pin banks of exynos7 pin-controller - TOUCH */ 518 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = { 519 /* Must start with EINTG banks, ordered by EINT group number. */ 520 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 521 }; 522 523 /* pin banks of exynos7 pin-controller - FF */ 524 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = { 525 /* Must start with EINTG banks, ordered by EINT group number. */ 526 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00), 527 }; 528 529 /* pin banks of exynos7 pin-controller - ESE */ 530 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = { 531 /* Must start with EINTG banks, ordered by EINT group number. */ 532 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00), 533 }; 534 535 /* pin banks of exynos7 pin-controller - FSYS0 */ 536 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = { 537 /* Must start with EINTG banks, ordered by EINT group number. */ 538 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00), 539 }; 540 541 /* pin banks of exynos7 pin-controller - FSYS1 */ 542 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { 543 /* Must start with EINTG banks, ordered by EINT group number. */ 544 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00), 545 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), 546 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08), 547 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), 548 }; 549 550 /* pin banks of exynos7 pin-controller - BUS1 */ 551 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { 552 /* Must start with EINTG banks, ordered by EINT group number. */ 553 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), 554 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), 555 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08), 556 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c), 557 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10), 558 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14), 559 EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18), 560 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c), 561 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20), 562 EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), 563 }; 564 565 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { 566 /* Must start with EINTG banks, ordered by EINT group number. */ 567 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 568 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 569 }; 570 571 static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { 572 { 573 /* pin-controller instance 0 Alive data */ 574 .pin_banks = exynos7_pin_banks0, 575 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), 576 .eint_wkup_init = exynos_eint_wkup_init, 577 }, { 578 /* pin-controller instance 1 BUS0 data */ 579 .pin_banks = exynos7_pin_banks1, 580 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1), 581 .eint_gpio_init = exynos_eint_gpio_init, 582 }, { 583 /* pin-controller instance 2 NFC data */ 584 .pin_banks = exynos7_pin_banks2, 585 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2), 586 .eint_gpio_init = exynos_eint_gpio_init, 587 }, { 588 /* pin-controller instance 3 TOUCH data */ 589 .pin_banks = exynos7_pin_banks3, 590 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3), 591 .eint_gpio_init = exynos_eint_gpio_init, 592 }, { 593 /* pin-controller instance 4 FF data */ 594 .pin_banks = exynos7_pin_banks4, 595 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4), 596 .eint_gpio_init = exynos_eint_gpio_init, 597 }, { 598 /* pin-controller instance 5 ESE data */ 599 .pin_banks = exynos7_pin_banks5, 600 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5), 601 .eint_gpio_init = exynos_eint_gpio_init, 602 }, { 603 /* pin-controller instance 6 FSYS0 data */ 604 .pin_banks = exynos7_pin_banks6, 605 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6), 606 .eint_gpio_init = exynos_eint_gpio_init, 607 }, { 608 /* pin-controller instance 7 FSYS1 data */ 609 .pin_banks = exynos7_pin_banks7, 610 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), 611 .eint_gpio_init = exynos_eint_gpio_init, 612 }, { 613 /* pin-controller instance 8 BUS1 data */ 614 .pin_banks = exynos7_pin_banks8, 615 .nr_banks = ARRAY_SIZE(exynos7_pin_banks8), 616 .eint_gpio_init = exynos_eint_gpio_init, 617 }, { 618 /* pin-controller instance 9 AUD data */ 619 .pin_banks = exynos7_pin_banks9, 620 .nr_banks = ARRAY_SIZE(exynos7_pin_banks9), 621 .eint_gpio_init = exynos_eint_gpio_init, 622 }, 623 }; 624 625 const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { 626 .ctrl = exynos7_pin_ctrl, 627 .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), 628 }; 629 630 /* pin banks of exynos7870 pin-controller 0 (ALIVE) */ 631 static const struct samsung_pin_bank_data exynos7870_pin_banks0[] __initconst = { 632 EXYNOS7870_PIN_BANK_EINTN(6, 0x000, "etc0"), 633 EXYNOS7870_PIN_BANK_EINTN(3, 0x020, "etc1"), 634 EXYNOS7870_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00), 635 EXYNOS7870_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04), 636 EXYNOS7870_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08), 637 EXYNOS7870_PIN_BANK_EINTN(2, 0x0c0, "gpq0"), 638 }; 639 640 /* pin banks of exynos7870 pin-controller 1 (DISPAUD) */ 641 static const struct samsung_pin_bank_data exynos7870_pin_banks1[] __initconst = { 642 EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpz0", 0x00), 643 EXYNOS8895_PIN_BANK_EINTG(6, 0x020, "gpz1", 0x04), 644 EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpz2", 0x08), 645 }; 646 647 /* pin banks of exynos7870 pin-controller 2 (ESE) */ 648 static const struct samsung_pin_bank_data exynos7870_pin_banks2[] __initconst = { 649 EXYNOS8895_PIN_BANK_EINTG(5, 0x000, "gpc7", 0x00), 650 }; 651 652 /* pin banks of exynos7870 pin-controller 3 (FSYS) */ 653 static const struct samsung_pin_bank_data exynos7870_pin_banks3[] __initconst = { 654 EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpr0", 0x00), 655 EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), 656 EXYNOS8895_PIN_BANK_EINTG(2, 0x040, "gpr2", 0x08), 657 EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpr3", 0x0c), 658 EXYNOS8895_PIN_BANK_EINTG(6, 0x080, "gpr4", 0x10), 659 }; 660 661 /* pin banks of exynos7870 pin-controller 4 (MIF) */ 662 static const struct samsung_pin_bank_data exynos7870_pin_banks4[] __initconst = { 663 EXYNOS8895_PIN_BANK_EINTG(2, 0x000, "gpm0", 0x00), 664 }; 665 666 /* pin banks of exynos7870 pin-controller 5 (NFC) */ 667 static const struct samsung_pin_bank_data exynos7870_pin_banks5[] __initconst = { 668 EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpc2", 0x00), 669 }; 670 671 /* pin banks of exynos7870 pin-controller 6 (TOP) */ 672 static const struct samsung_pin_bank_data exynos7870_pin_banks6[] __initconst = { 673 EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpb0", 0x00), 674 EXYNOS8895_PIN_BANK_EINTG(3, 0x020, "gpc0", 0x04), 675 EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpc1", 0x08), 676 EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpc4", 0x0c), 677 EXYNOS8895_PIN_BANK_EINTG(2, 0x080, "gpc5", 0x10), 678 EXYNOS8895_PIN_BANK_EINTG(4, 0x0a0, "gpc6", 0x14), 679 EXYNOS8895_PIN_BANK_EINTG(2, 0x0c0, "gpc8", 0x18), 680 EXYNOS8895_PIN_BANK_EINTG(2, 0x0e0, "gpc9", 0x1c), 681 EXYNOS8895_PIN_BANK_EINTG(7, 0x100, "gpd1", 0x20), 682 EXYNOS8895_PIN_BANK_EINTG(6, 0x120, "gpd2", 0x24), 683 EXYNOS8895_PIN_BANK_EINTG(8, 0x140, "gpd3", 0x28), 684 EXYNOS8895_PIN_BANK_EINTG(7, 0x160, "gpd4", 0x2c), 685 EXYNOS8895_PIN_BANK_EINTG(3, 0x1a0, "gpe0", 0x34), 686 EXYNOS8895_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), 687 EXYNOS8895_PIN_BANK_EINTG(2, 0x1e0, "gpf1", 0x3c), 688 EXYNOS8895_PIN_BANK_EINTG(2, 0x200, "gpf2", 0x40), 689 EXYNOS8895_PIN_BANK_EINTG(4, 0x220, "gpf3", 0x44), 690 EXYNOS8895_PIN_BANK_EINTG(5, 0x240, "gpf4", 0x48), 691 }; 692 693 /* pin banks of exynos7870 pin-controller 7 (TOUCH) */ 694 static const struct samsung_pin_bank_data exynos7870_pin_banks7[] __initconst = { 695 EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpc3", 0x00), 696 }; 697 698 static const struct samsung_pin_ctrl exynos7870_pin_ctrl[] __initconst = { 699 { 700 /* pin-controller instance 0 Alive data */ 701 .pin_banks = exynos7870_pin_banks0, 702 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks0), 703 .eint_wkup_init = exynos_eint_wkup_init, 704 .suspend = exynos_pinctrl_suspend, 705 .resume = exynos_pinctrl_resume, 706 }, { 707 /* pin-controller instance 1 DISPAUD data */ 708 .pin_banks = exynos7870_pin_banks1, 709 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks1), 710 }, { 711 /* pin-controller instance 2 ESE data */ 712 .pin_banks = exynos7870_pin_banks2, 713 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks2), 714 .eint_gpio_init = exynos_eint_gpio_init, 715 .suspend = exynos_pinctrl_suspend, 716 .resume = exynos_pinctrl_resume, 717 }, { 718 /* pin-controller instance 3 FSYS data */ 719 .pin_banks = exynos7870_pin_banks3, 720 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks3), 721 .eint_gpio_init = exynos_eint_gpio_init, 722 .suspend = exynos_pinctrl_suspend, 723 .resume = exynos_pinctrl_resume, 724 }, { 725 /* pin-controller instance 4 MIF data */ 726 .pin_banks = exynos7870_pin_banks4, 727 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks4), 728 .eint_gpio_init = exynos_eint_gpio_init, 729 .suspend = exynos_pinctrl_suspend, 730 .resume = exynos_pinctrl_resume, 731 }, { 732 /* pin-controller instance 5 NFC data */ 733 .pin_banks = exynos7870_pin_banks5, 734 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks5), 735 .eint_gpio_init = exynos_eint_gpio_init, 736 .suspend = exynos_pinctrl_suspend, 737 .resume = exynos_pinctrl_resume, 738 }, { 739 /* pin-controller instance 6 TOP data */ 740 .pin_banks = exynos7870_pin_banks6, 741 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks6), 742 .eint_gpio_init = exynos_eint_gpio_init, 743 .suspend = exynos_pinctrl_suspend, 744 .resume = exynos_pinctrl_resume, 745 }, { 746 /* pin-controller instance 7 TOUCH data */ 747 .pin_banks = exynos7870_pin_banks7, 748 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks7), 749 .eint_gpio_init = exynos_eint_gpio_init, 750 .suspend = exynos_pinctrl_suspend, 751 .resume = exynos_pinctrl_resume, 752 }, 753 }; 754 755 const struct samsung_pinctrl_of_match_data exynos7870_of_data __initconst = { 756 .ctrl = exynos7870_pin_ctrl, 757 .num_ctrl = ARRAY_SIZE(exynos7870_pin_ctrl), 758 }; 759 760 /* pin banks of exynos7885 pin-controller 0 (ALIVE) */ 761 static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = { 762 EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"), 763 EXYNOS_PIN_BANK_EINTN(3, 0x020, "etc1"), 764 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00), 765 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04), 766 EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08), 767 EXYNOS850_PIN_BANK_EINTW(5, 0x0a0, "gpq0", 0x0c), 768 }; 769 770 /* pin banks of exynos7885 pin-controller 1 (DISPAUD) */ 771 static const struct samsung_pin_bank_data exynos7885_pin_banks1[] __initconst = { 772 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 773 EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04), 774 EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08), 775 }; 776 777 /* pin banks of exynos7885 pin-controller 2 (FSYS) */ 778 static const struct samsung_pin_bank_data exynos7885_pin_banks2[] __initconst = { 779 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), 780 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf2", 0x04), 781 EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf3", 0x08), 782 EXYNOS850_PIN_BANK_EINTG(6, 0x060, "gpf4", 0x0c), 783 }; 784 785 /* pin banks of exynos7885 pin-controller 3 (TOP) */ 786 static const struct samsung_pin_bank_data exynos7885_pin_banks3[] __initconst = { 787 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpp0", 0x00), 788 EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gpg0", 0x04), 789 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), 790 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), 791 EXYNOS850_PIN_BANK_EINTG(3, 0x080, "gpp3", 0x10), 792 EXYNOS850_PIN_BANK_EINTG(6, 0x0a0, "gpp4", 0x14), 793 EXYNOS850_PIN_BANK_EINTG(4, 0x0c0, "gpp5", 0x18), 794 EXYNOS850_PIN_BANK_EINTG(5, 0x0e0, "gpp6", 0x1c), 795 EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpp7", 0x20), 796 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp8", 0x24), 797 EXYNOS850_PIN_BANK_EINTG(8, 0x140, "gpg1", 0x28), 798 EXYNOS850_PIN_BANK_EINTG(8, 0x160, "gpg2", 0x2c), 799 EXYNOS850_PIN_BANK_EINTG(8, 0x180, "gpg3", 0x30), 800 EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpg4", 0x34), 801 EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpc0", 0x38), 802 EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpc1", 0x3c), 803 EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpc2", 0x40), 804 }; 805 806 static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = { 807 { 808 /* pin-controller instance 0 Alive data */ 809 .pin_banks = exynos7885_pin_banks0, 810 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks0), 811 .eint_gpio_init = exynos_eint_gpio_init, 812 .eint_wkup_init = exynos_eint_wkup_init, 813 .suspend = exynos_pinctrl_suspend, 814 .resume = exynos_pinctrl_resume, 815 }, { 816 /* pin-controller instance 1 DISPAUD data */ 817 .pin_banks = exynos7885_pin_banks1, 818 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks1), 819 }, { 820 /* pin-controller instance 2 FSYS data */ 821 .pin_banks = exynos7885_pin_banks2, 822 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks2), 823 .eint_gpio_init = exynos_eint_gpio_init, 824 .suspend = exynos_pinctrl_suspend, 825 .resume = exynos_pinctrl_resume, 826 }, { 827 /* pin-controller instance 3 TOP data */ 828 .pin_banks = exynos7885_pin_banks3, 829 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks3), 830 .eint_gpio_init = exynos_eint_gpio_init, 831 .suspend = exynos_pinctrl_suspend, 832 .resume = exynos_pinctrl_resume, 833 }, 834 }; 835 836 const struct samsung_pinctrl_of_match_data exynos7885_of_data __initconst = { 837 .ctrl = exynos7885_pin_ctrl, 838 .num_ctrl = ARRAY_SIZE(exynos7885_pin_ctrl), 839 }; 840 841 /* pin banks of exynos850 pin-controller 0 (ALIVE) */ 842 static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { 843 /* Must start with EINTG banks, ordered by EINT group number. */ 844 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 845 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 846 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 847 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 848 EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), 849 EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"), 850 }; 851 852 /* pin banks of exynos850 pin-controller 1 (CMGP) */ 853 static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = { 854 /* Must start with EINTG banks, ordered by EINT group number. */ 855 EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), 856 EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), 857 EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), 858 EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c), 859 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), 860 EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14), 861 EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18), 862 EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c), 863 }; 864 865 /* pin banks of exynos850 pin-controller 2 (AUD) */ 866 static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = { 867 /* Must start with EINTG banks, ordered by EINT group number. */ 868 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 869 EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), 870 }; 871 872 /* pin banks of exynos850 pin-controller 3 (HSI) */ 873 static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = { 874 /* Must start with EINTG banks, ordered by EINT group number. */ 875 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), 876 }; 877 878 /* pin banks of exynos850 pin-controller 4 (CORE) */ 879 static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = { 880 /* Must start with EINTG banks, ordered by EINT group number. */ 881 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), 882 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), 883 }; 884 885 /* pin banks of exynos850 pin-controller 5 (PERI) */ 886 static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = { 887 /* Must start with EINTG banks, ordered by EINT group number. */ 888 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), 889 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), 890 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), 891 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), 892 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), 893 EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14), 894 EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18), 895 EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c), 896 EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), 897 }; 898 899 static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { 900 { 901 /* pin-controller instance 0 ALIVE data */ 902 .pin_banks = exynos850_pin_banks0, 903 .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), 904 .eint_wkup_init = exynos_eint_wkup_init, 905 }, { 906 /* pin-controller instance 1 CMGP data */ 907 .pin_banks = exynos850_pin_banks1, 908 .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), 909 .eint_wkup_init = exynos_eint_wkup_init, 910 }, { 911 /* pin-controller instance 2 AUD data */ 912 .pin_banks = exynos850_pin_banks2, 913 .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), 914 }, { 915 /* pin-controller instance 3 HSI data */ 916 .pin_banks = exynos850_pin_banks3, 917 .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), 918 .eint_gpio_init = exynos_eint_gpio_init, 919 }, { 920 /* pin-controller instance 4 CORE data */ 921 .pin_banks = exynos850_pin_banks4, 922 .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), 923 .eint_gpio_init = exynos_eint_gpio_init, 924 }, { 925 /* pin-controller instance 5 PERI data */ 926 .pin_banks = exynos850_pin_banks5, 927 .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), 928 .eint_gpio_init = exynos_eint_gpio_init, 929 }, 930 }; 931 932 const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { 933 .ctrl = exynos850_pin_ctrl, 934 .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), 935 }; 936 937 /* pin banks of exynos990 pin-controller 0 (ALIVE) */ 938 static struct samsung_pin_bank_data exynos990_pin_banks0[] = { 939 /* Must start with EINTG banks, ordered by EINT group number. */ 940 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 941 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 942 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 943 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 944 EXYNOS850_PIN_BANK_EINTW(2, 0x080, "gpa4", 0x10), 945 EXYNOS850_PIN_BANK_EINTN(7, 0x0A0, "gpq0"), 946 }; 947 948 /* pin banks of exynos990 pin-controller 1 (CMGP) */ 949 static struct samsung_pin_bank_data exynos990_pin_banks1[] = { 950 /* Must start with EINTG banks, ordered by EINT group number. */ 951 EXYNOS850_PIN_BANK_EINTN(1, 0x000, "gpm0"), 952 EXYNOS850_PIN_BANK_EINTN(1, 0x020, "gpm1"), 953 EXYNOS850_PIN_BANK_EINTN(1, 0x040, "gpm2"), 954 EXYNOS850_PIN_BANK_EINTN(1, 0x060, "gpm3"), 955 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x00), 956 EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x04), 957 EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x08), 958 EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x0c), 959 EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x10), 960 EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x14), 961 EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x18), 962 EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x1c), 963 EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x20), 964 EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x24), 965 EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x28), 966 EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x2c), 967 EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x30), 968 EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x34), 969 EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x38), 970 EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x3c), 971 EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x40), 972 EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x44), 973 EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x48), 974 EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x4c), 975 EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x50), 976 EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x54), 977 EXYNOS850_PIN_BANK_EINTW(1, 0x340, "gpm26", 0x58), 978 EXYNOS850_PIN_BANK_EINTW(1, 0x360, "gpm27", 0x5c), 979 EXYNOS850_PIN_BANK_EINTW(1, 0x380, "gpm28", 0x60), 980 EXYNOS850_PIN_BANK_EINTW(1, 0x3A0, "gpm29", 0x64), 981 EXYNOS850_PIN_BANK_EINTW(1, 0x3C0, "gpm30", 0x68), 982 EXYNOS850_PIN_BANK_EINTW(1, 0x3E0, "gpm31", 0x6c), 983 EXYNOS850_PIN_BANK_EINTW(1, 0x400, "gpm32", 0x70), 984 EXYNOS850_PIN_BANK_EINTW(1, 0x420, "gpm33", 0x74), 985 986 }; 987 988 /* pin banks of exynos990 pin-controller 2 (HSI1) */ 989 static struct samsung_pin_bank_data exynos990_pin_banks2[] = { 990 /* Must start with EINTG banks, ordered by EINT group number. */ 991 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), 992 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), 993 EXYNOS850_PIN_BANK_EINTG(3, 0x040, "gpf2", 0x08), 994 }; 995 996 /* pin banks of exynos990 pin-controller 3 (HSI2) */ 997 static struct samsung_pin_bank_data exynos990_pin_banks3[] = { 998 /* Must start with EINTG banks, ordered by EINT group number. */ 999 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf3", 0x00), 1000 }; 1001 1002 /* pin banks of exynos990 pin-controller 4 (PERIC0) */ 1003 static struct samsung_pin_bank_data exynos990_pin_banks4[] = { 1004 /* Must start with EINTG banks, ordered by EINT group number. */ 1005 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), 1006 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), 1007 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), 1008 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp3", 0x0C), 1009 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp4", 0x10), 1010 EXYNOS850_PIN_BANK_EINTG(2, 0x0A0, "gpg0", 0x14), 1011 }; 1012 1013 /* pin banks of exynos990 pin-controller 5 (PERIC1) */ 1014 static struct samsung_pin_bank_data exynos990_pin_banks5[] = { 1015 /* Must start with EINTG banks, ordered by EINT group number. */ 1016 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp5", 0x00), 1017 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp6", 0x04), 1018 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp7", 0x08), 1019 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp8", 0x0C), 1020 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp9", 0x10), 1021 EXYNOS850_PIN_BANK_EINTG(6, 0x0A0, "gpc0", 0x14), 1022 EXYNOS850_PIN_BANK_EINTG(4, 0x0C0, "gpg1", 0x18), 1023 EXYNOS850_PIN_BANK_EINTG(8, 0x0E0, "gpb0", 0x1C), 1024 EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb1", 0x20), 1025 EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb2", 0x24), 1026 }; 1027 1028 /* pin banks of exynos990 pin-controller 6 (VTS) */ 1029 static struct samsung_pin_bank_data exynos990_pin_banks6[] = { 1030 /* Must start with EINTG banks, ordered by EINT group number. */ 1031 EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpv0", 0x00), 1032 }; 1033 1034 static const struct samsung_pin_ctrl exynos990_pin_ctrl[] __initconst = { 1035 { 1036 /* pin-controller instance 0 ALIVE data */ 1037 .pin_banks = exynos990_pin_banks0, 1038 .nr_banks = ARRAY_SIZE(exynos990_pin_banks0), 1039 .eint_wkup_init = exynos_eint_wkup_init, 1040 }, { 1041 /* pin-controller instance 1 CMGP data */ 1042 .pin_banks = exynos990_pin_banks1, 1043 .nr_banks = ARRAY_SIZE(exynos990_pin_banks1), 1044 .eint_wkup_init = exynos_eint_wkup_init, 1045 }, { 1046 /* pin-controller instance 2 HSI1 data */ 1047 .pin_banks = exynos990_pin_banks2, 1048 .nr_banks = ARRAY_SIZE(exynos990_pin_banks2), 1049 .eint_gpio_init = exynos_eint_gpio_init, 1050 }, { 1051 /* pin-controller instance 3 HSI2 data */ 1052 .pin_banks = exynos990_pin_banks3, 1053 .nr_banks = ARRAY_SIZE(exynos990_pin_banks3), 1054 .eint_gpio_init = exynos_eint_gpio_init, 1055 }, { 1056 /* pin-controller instance 4 PERIC0 data */ 1057 .pin_banks = exynos990_pin_banks4, 1058 .nr_banks = ARRAY_SIZE(exynos990_pin_banks4), 1059 .eint_gpio_init = exynos_eint_gpio_init, 1060 }, { 1061 /* pin-controller instance 5 PERIC1 data */ 1062 .pin_banks = exynos990_pin_banks5, 1063 .nr_banks = ARRAY_SIZE(exynos990_pin_banks5), 1064 .eint_gpio_init = exynos_eint_gpio_init, 1065 }, { 1066 /* pin-controller instance 6 VTS data */ 1067 .pin_banks = exynos990_pin_banks6, 1068 .nr_banks = ARRAY_SIZE(exynos990_pin_banks6), 1069 }, 1070 }; 1071 1072 const struct samsung_pinctrl_of_match_data exynos990_of_data __initconst = { 1073 .ctrl = exynos990_pin_ctrl, 1074 .num_ctrl = ARRAY_SIZE(exynos990_pin_ctrl), 1075 }; 1076 1077 /* pin banks of exynos9810 pin-controller 0 (ALIVE) */ 1078 static const struct samsung_pin_bank_data exynos9810_pin_banks0[] __initconst = { 1079 EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc1"), 1080 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), 1081 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), 1082 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), 1083 EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), 1084 EXYNOS850_PIN_BANK_EINTN(6, 0x0A0, "gpq0"), 1085 EXYNOS850_PIN_BANK_EINTW(2, 0x0C0, "gpa4", 0x10), 1086 }; 1087 1088 /* pin banks of exynos9810 pin-controller 1 (AUD) */ 1089 static const struct samsung_pin_bank_data exynos9810_pin_banks1[] __initconst = { 1090 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 1091 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), 1092 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpb2", 0x08), 1093 }; 1094 1095 /* pin banks of exynos9810 pin-controller 2 (CHUB) */ 1096 static const struct samsung_pin_bank_data exynos9810_pin_banks2[] __initconst = { 1097 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), 1098 EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gph1", 0x04), 1099 }; 1100 1101 /* pin banks of exynos9810 pin-controller 3 (CMGP) */ 1102 static const struct samsung_pin_bank_data exynos9810_pin_banks3[] __initconst = { 1103 EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), 1104 EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), 1105 EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), 1106 EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), 1107 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), 1108 EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), 1109 EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), 1110 EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), 1111 EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm10", 0x20), 1112 EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm11", 0x24), 1113 EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm12", 0x28), 1114 EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm13", 0x2C), 1115 EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm14", 0x30), 1116 EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm15", 0x34), 1117 EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm16", 0x38), 1118 EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm17", 0x3C), 1119 EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm40", 0x40), 1120 EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm41", 0x44), 1121 EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm42", 0x48), 1122 EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm43", 0x4C), 1123 }; 1124 1125 /* pin banks of exynos9810 pin-controller 4 (FSYS0) */ 1126 static const struct samsung_pin_bank_data exynos9810_pin_banks4[] __initconst = { 1127 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf0", 0x00), 1128 }; 1129 1130 /* pin banks of exynos9810 pin-controller 5 (FSYS1) */ 1131 static const struct samsung_pin_bank_data exynos9810_pin_banks5[] __initconst = { 1132 EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpf1", 0x00), 1133 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf2", 0x04), 1134 }; 1135 1136 /* pin banks of exynos9810 pin-controller 6 (PERIC0) */ 1137 static const struct samsung_pin_bank_data exynos9810_pin_banks6[] __initconst = { 1138 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), 1139 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), 1140 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), 1141 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp3", 0x0C), 1142 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 1143 EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 1144 EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg2", 0x18), 1145 }; 1146 1147 /* pin banks of exynos9810 pin-controller 7 (PERIC1) */ 1148 static const struct samsung_pin_bank_data exynos9810_pin_banks7[] __initconst = { 1149 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp4", 0x00), 1150 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp5", 0x04), 1151 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp6", 0x08), 1152 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C), 1153 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10), 1154 EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 1155 EXYNOS850_PIN_BANK_EINTG(7, 0x0C0, "gpg3", 0x18), 1156 }; 1157 1158 /* pin banks of exynos9810 pin-controller 8 (VTS) */ 1159 static const struct samsung_pin_bank_data exynos9810_pin_banks8[] __initconst = { 1160 EXYNOS850_PIN_BANK_EINTG(3, 0x000, "gpt0", 0x00), 1161 }; 1162 1163 static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = { 1164 { 1165 /* pin-controller instance 0 ALIVE data */ 1166 .pin_banks = exynos9810_pin_banks0, 1167 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks0), 1168 .eint_wkup_init = exynos_eint_wkup_init, 1169 .eint_gpio_init = exynos_eint_gpio_init, 1170 .suspend = exynos_pinctrl_suspend, 1171 .resume = exynos_pinctrl_resume, 1172 }, { 1173 /* pin-controller instance 1 AUD data */ 1174 .pin_banks = exynos9810_pin_banks1, 1175 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks1), 1176 }, { 1177 /* pin-controller instance 2 CHUB data */ 1178 .pin_banks = exynos9810_pin_banks2, 1179 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks2), 1180 .eint_gpio_init = exynos_eint_gpio_init, 1181 .suspend = exynos_pinctrl_suspend, 1182 .resume = exynos_pinctrl_resume, 1183 }, { 1184 /* pin-controller instance 3 CMGP data */ 1185 .pin_banks = exynos9810_pin_banks3, 1186 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks3), 1187 .eint_wkup_init = exynos_eint_wkup_init, 1188 .eint_gpio_init = exynos_eint_gpio_init, 1189 .suspend = exynos_pinctrl_suspend, 1190 .resume = exynos_pinctrl_resume, 1191 }, { 1192 /* pin-controller instance 4 FSYS0 data */ 1193 .pin_banks = exynos9810_pin_banks4, 1194 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks4), 1195 .eint_gpio_init = exynos_eint_gpio_init, 1196 .suspend = exynos_pinctrl_suspend, 1197 .resume = exynos_pinctrl_resume, 1198 }, { 1199 /* pin-controller instance 5 FSYS1 data */ 1200 .pin_banks = exynos9810_pin_banks5, 1201 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks5), 1202 .eint_gpio_init = exynos_eint_gpio_init, 1203 .suspend = exynos_pinctrl_suspend, 1204 .resume = exynos_pinctrl_resume, 1205 }, { 1206 /* pin-controller instance 6 PERIC0 data */ 1207 .pin_banks = exynos9810_pin_banks6, 1208 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks6), 1209 .eint_gpio_init = exynos_eint_gpio_init, 1210 .suspend = exynos_pinctrl_suspend, 1211 .resume = exynos_pinctrl_resume, 1212 }, { 1213 /* pin-controller instance 7 PERIC1 data */ 1214 .pin_banks = exynos9810_pin_banks7, 1215 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks7), 1216 .eint_gpio_init = exynos_eint_gpio_init, 1217 .suspend = exynos_pinctrl_suspend, 1218 .resume = exynos_pinctrl_resume, 1219 }, { 1220 /* pin-controller instance 8 VTS data */ 1221 .pin_banks = exynos9810_pin_banks8, 1222 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks8), 1223 }, 1224 }; 1225 1226 const struct samsung_pinctrl_of_match_data exynos9810_of_data __initconst = { 1227 .ctrl = exynos9810_pin_ctrl, 1228 .num_ctrl = ARRAY_SIZE(exynos9810_pin_ctrl), 1229 }; 1230 1231 /* pin banks of exynosautov9 pin-controller 0 (ALIVE) */ 1232 static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = { 1233 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1234 EXYNOS850_PIN_BANK_EINTW(2, 0x020, "gpa1", 0x04), 1235 EXYNOS850_PIN_BANK_EINTN(2, 0x040, "gpq0"), 1236 }; 1237 1238 /* pin banks of exynosautov9 pin-controller 1 (AUD) */ 1239 static const struct samsung_pin_bank_data exynosautov9_pin_banks1[] __initconst = { 1240 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 1241 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), 1242 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpb2", 0x08), 1243 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpb3", 0x0C), 1244 }; 1245 1246 /* pin banks of exynosautov9 pin-controller 2 (FSYS0) */ 1247 static const struct samsung_pin_bank_data exynosautov9_pin_banks2[] __initconst = { 1248 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf0", 0x00), 1249 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), 1250 }; 1251 1252 /* pin banks of exynosautov9 pin-controller 3 (FSYS1) */ 1253 static const struct samsung_pin_bank_data exynosautov9_pin_banks3[] __initconst = { 1254 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf8", 0x00), 1255 }; 1256 1257 /* pin banks of exynosautov9 pin-controller 4 (FSYS2) */ 1258 static const struct samsung_pin_bank_data exynosautov9_pin_banks4[] __initconst = { 1259 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf2", 0x00), 1260 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf3", 0x04), 1261 EXYNOS850_PIN_BANK_EINTG(7, 0x040, "gpf4", 0x08), 1262 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpf5", 0x0C), 1263 EXYNOS850_PIN_BANK_EINTG(7, 0x080, "gpf6", 0x10), 1264 }; 1265 1266 /* pin banks of exynosautov9 pin-controller 5 (PERIC0) */ 1267 static const struct samsung_pin_bank_data exynosautov9_pin_banks5[] __initconst = { 1268 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), 1269 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), 1270 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), 1271 EXYNOS850_PIN_BANK_EINTG(5, 0x060, "gpg0", 0x0C), 1272 }; 1273 1274 /* pin banks of exynosautov9 pin-controller 6 (PERIC1) */ 1275 static const struct samsung_pin_bank_data exynosautov9_pin_banks6[] __initconst = { 1276 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp3", 0x00), 1277 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp4", 0x04), 1278 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp5", 0x08), 1279 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpg1", 0x0C), 1280 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg2", 0x10), 1281 EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpg3", 0x14), 1282 }; 1283 1284 static const struct samsung_pin_ctrl exynosautov9_pin_ctrl[] __initconst = { 1285 { 1286 /* pin-controller instance 0 ALIVE data */ 1287 .pin_banks = exynosautov9_pin_banks0, 1288 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks0), 1289 .eint_wkup_init = exynos_eint_wkup_init, 1290 .suspend = exynos_pinctrl_suspend, 1291 .resume = exynos_pinctrl_resume, 1292 }, { 1293 /* pin-controller instance 1 AUD data */ 1294 .pin_banks = exynosautov9_pin_banks1, 1295 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks1), 1296 }, { 1297 /* pin-controller instance 2 FSYS0 data */ 1298 .pin_banks = exynosautov9_pin_banks2, 1299 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks2), 1300 .eint_gpio_init = exynos_eint_gpio_init, 1301 .suspend = exynos_pinctrl_suspend, 1302 .resume = exynos_pinctrl_resume, 1303 }, { 1304 /* pin-controller instance 3 FSYS1 data */ 1305 .pin_banks = exynosautov9_pin_banks3, 1306 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks3), 1307 .eint_gpio_init = exynos_eint_gpio_init, 1308 .suspend = exynos_pinctrl_suspend, 1309 .resume = exynos_pinctrl_resume, 1310 }, { 1311 /* pin-controller instance 4 FSYS2 data */ 1312 .pin_banks = exynosautov9_pin_banks4, 1313 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks4), 1314 .eint_gpio_init = exynos_eint_gpio_init, 1315 .suspend = exynos_pinctrl_suspend, 1316 .resume = exynos_pinctrl_resume, 1317 }, { 1318 /* pin-controller instance 5 PERIC0 data */ 1319 .pin_banks = exynosautov9_pin_banks5, 1320 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks5), 1321 .eint_gpio_init = exynos_eint_gpio_init, 1322 .suspend = exynos_pinctrl_suspend, 1323 .resume = exynos_pinctrl_resume, 1324 }, { 1325 /* pin-controller instance 6 PERIC1 data */ 1326 .pin_banks = exynosautov9_pin_banks6, 1327 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks6), 1328 .eint_gpio_init = exynos_eint_gpio_init, 1329 .suspend = exynos_pinctrl_suspend, 1330 .resume = exynos_pinctrl_resume, 1331 }, 1332 }; 1333 1334 const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = { 1335 .ctrl = exynosautov9_pin_ctrl, 1336 .num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl), 1337 }; 1338 1339 /* pin banks of exynosautov920 pin-controller 0 (ALIVE) */ 1340 static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = { 1341 EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28), 1342 EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24), 1343 EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"), 1344 }; 1345 1346 /* pin banks of exynosautov920 pin-controller 1 (AUD) */ 1347 static const struct samsung_pin_bank_data exynosautov920_pin_banks1[] = { 1348 EXYNOSV920_PIN_BANK_EINTG(7, 0x0000, "gpb0", 0x18, 0x24, 0x28), 1349 EXYNOSV920_PIN_BANK_EINTG(6, 0x1000, "gpb1", 0x18, 0x24, 0x28), 1350 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpb2", 0x18, 0x24, 0x28), 1351 EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpb3", 0x18, 0x24, 0x28), 1352 EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpb4", 0x18, 0x24, 0x28), 1353 EXYNOSV920_PIN_BANK_EINTG(5, 0x5000, "gpb5", 0x18, 0x24, 0x28), 1354 EXYNOSV920_PIN_BANK_EINTG(5, 0x6000, "gpb6", 0x18, 0x24, 0x28), 1355 }; 1356 1357 /* pin banks of exynosautov920 pin-controller 2 (HSI0) */ 1358 static const struct samsung_pin_bank_data exynosautov920_pin_banks2[] = { 1359 EXYNOSV920_PIN_BANK_EINTG(6, 0x0000, "gph0", 0x18, 0x24, 0x28), 1360 EXYNOSV920_PIN_BANK_EINTG(2, 0x1000, "gph1", 0x18, 0x20, 0x24), 1361 }; 1362 1363 /* pin banks of exynosautov920 pin-controller 3 (HSI1) */ 1364 static const struct samsung_pin_bank_data exynosautov920_pin_banks3[] = { 1365 EXYNOSV920_PIN_BANK_EINTG(7, 0x000, "gph8", 0x18, 0x24, 0x28), 1366 }; 1367 1368 /* pin banks of exynosautov920 pin-controller 4 (HSI2) */ 1369 static const struct samsung_pin_bank_data exynosautov920_pin_banks4[] = { 1370 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gph3", 0x18, 0x24, 0x28), 1371 EXYNOSV920_PIN_BANK_EINTG(7, 0x1000, "gph4", 0x18, 0x24, 0x28), 1372 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gph5", 0x18, 0x24, 0x28), 1373 EXYNOSV920_PIN_BANK_EINTG(7, 0x3000, "gph6", 0x18, 0x24, 0x28), 1374 }; 1375 1376 /* pin banks of exynosautov920 pin-controller 5 (HSI2UFS) */ 1377 static const struct samsung_pin_bank_data exynosautov920_pin_banks5[] = { 1378 EXYNOSV920_PIN_BANK_EINTG(4, 0x000, "gph2", 0x18, 0x20, 0x24), 1379 }; 1380 1381 /* pin banks of exynosautov920 pin-controller 6 (PERIC0) */ 1382 static const struct samsung_pin_bank_data exynosautov920_pin_banks6[] = { 1383 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp0", 0x18, 0x24, 0x28), 1384 EXYNOSV920_PIN_BANK_EINTG(8, 0x1000, "gpp1", 0x18, 0x24, 0x28), 1385 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpp2", 0x18, 0x24, 0x28), 1386 EXYNOSV920_PIN_BANK_EINTG(5, 0x3000, "gpg0", 0x18, 0x24, 0x28), 1387 EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpp3", 0x18, 0x24, 0x28), 1388 EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp4", 0x18, 0x20, 0x24), 1389 EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpg2", 0x18, 0x20, 0x24), 1390 EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpg5", 0x18, 0x20, 0x24), 1391 EXYNOSV920_PIN_BANK_EINTG(3, 0x8000, "gpg3", 0x18, 0x20, 0x24), 1392 EXYNOSV920_PIN_BANK_EINTG(5, 0x9000, "gpg4", 0x18, 0x24, 0x28), 1393 }; 1394 1395 /* pin banks of exynosautov920 pin-controller 7 (PERIC1) */ 1396 static const struct samsung_pin_bank_data exynosautov920_pin_banks7[] = { 1397 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp5", 0x18, 0x24, 0x28), 1398 EXYNOSV920_PIN_BANK_EINTG(5, 0x1000, "gpp6", 0x18, 0x24, 0x28), 1399 EXYNOSV920_PIN_BANK_EINTG(4, 0x2000, "gpp10", 0x18, 0x20, 0x24), 1400 EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpp7", 0x18, 0x24, 0x28), 1401 EXYNOSV920_PIN_BANK_EINTG(4, 0x4000, "gpp8", 0x18, 0x20, 0x24), 1402 EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp11", 0x18, 0x20, 0x24), 1403 EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpp9", 0x18, 0x20, 0x24), 1404 EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpp12", 0x18, 0x20, 0x24), 1405 EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28), 1406 }; 1407 1408 static const struct samsung_retention_data exynosautov920_retention_data __initconst = { 1409 .regs = NULL, 1410 .nr_regs = 0, 1411 .value = 0, 1412 .refcnt = &exynos_shared_retention_refcnt, 1413 .init = exynos_retention_init, 1414 }; 1415 1416 static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = { 1417 { 1418 /* pin-controller instance 0 ALIVE data */ 1419 .pin_banks = exynosautov920_pin_banks0, 1420 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0), 1421 .eint_wkup_init = exynos_eint_wkup_init, 1422 .suspend = exynosautov920_pinctrl_suspend, 1423 .resume = exynosautov920_pinctrl_resume, 1424 .retention_data = &exynosautov920_retention_data, 1425 }, { 1426 /* pin-controller instance 1 AUD data */ 1427 .pin_banks = exynosautov920_pin_banks1, 1428 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks1), 1429 }, { 1430 /* pin-controller instance 2 HSI0 data */ 1431 .pin_banks = exynosautov920_pin_banks2, 1432 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2), 1433 .eint_gpio_init = exynos_eint_gpio_init, 1434 .suspend = exynosautov920_pinctrl_suspend, 1435 .resume = exynosautov920_pinctrl_resume, 1436 }, { 1437 /* pin-controller instance 3 HSI1 data */ 1438 .pin_banks = exynosautov920_pin_banks3, 1439 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3), 1440 .eint_gpio_init = exynos_eint_gpio_init, 1441 .suspend = exynosautov920_pinctrl_suspend, 1442 .resume = exynosautov920_pinctrl_resume, 1443 }, { 1444 /* pin-controller instance 4 HSI2 data */ 1445 .pin_banks = exynosautov920_pin_banks4, 1446 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4), 1447 .eint_gpio_init = exynos_eint_gpio_init, 1448 .suspend = exynosautov920_pinctrl_suspend, 1449 .resume = exynosautov920_pinctrl_resume, 1450 }, { 1451 /* pin-controller instance 5 HSI2UFS data */ 1452 .pin_banks = exynosautov920_pin_banks5, 1453 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5), 1454 .eint_gpio_init = exynos_eint_gpio_init, 1455 .suspend = exynosautov920_pinctrl_suspend, 1456 .resume = exynosautov920_pinctrl_resume, 1457 }, { 1458 /* pin-controller instance 6 PERIC0 data */ 1459 .pin_banks = exynosautov920_pin_banks6, 1460 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6), 1461 .eint_gpio_init = exynos_eint_gpio_init, 1462 .suspend = exynosautov920_pinctrl_suspend, 1463 .resume = exynosautov920_pinctrl_resume, 1464 }, { 1465 /* pin-controller instance 7 PERIC1 data */ 1466 .pin_banks = exynosautov920_pin_banks7, 1467 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7), 1468 .eint_gpio_init = exynos_eint_gpio_init, 1469 .suspend = exynosautov920_pinctrl_suspend, 1470 .resume = exynosautov920_pinctrl_resume, 1471 }, 1472 }; 1473 1474 const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = { 1475 .ctrl = exynosautov920_pin_ctrl, 1476 .num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl), 1477 }; 1478 1479 /* pin banks of exynos8895 pin-controller 0 (ALIVE) */ 1480 static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = { 1481 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), 1482 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), 1483 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), 1484 EXYNOS_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), 1485 EXYNOS_PIN_BANK_EINTW(7, 0x0a0, "gpa4", 0x24), 1486 }; 1487 1488 /* pin banks of exynos8895 pin-controller 1 (ABOX) */ 1489 static const struct samsung_pin_bank_data exynos8895_pin_banks1[] __initconst = { 1490 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), 1491 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gph1", 0x04), 1492 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gph3", 0x08), 1493 }; 1494 1495 /* pin banks of exynos8895 pin-controller 2 (VTS) */ 1496 static const struct samsung_pin_bank_data exynos8895_pin_banks2[] __initconst = { 1497 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gph2", 0x00), 1498 }; 1499 1500 /* pin banks of exynos8895 pin-controller 3 (FSYS0) */ 1501 static const struct samsung_pin_bank_data exynos8895_pin_banks3[] __initconst = { 1502 EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpi0", 0x00), 1503 EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi1", 0x04), 1504 }; 1505 1506 /* pin banks of exynos8895 pin-controller 4 (FSYS1) */ 1507 static const struct samsung_pin_bank_data exynos8895_pin_banks4[] __initconst = { 1508 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj1", 0x00), 1509 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpj0", 0x04), 1510 }; 1511 1512 /* pin banks of exynos8895 pin-controller 5 (BUSC) */ 1513 static const struct samsung_pin_bank_data exynos8895_pin_banks5[] __initconst = { 1514 EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpb2", 0x00), 1515 }; 1516 1517 /* pin banks of exynos8895 pin-controller 6 (PERIC0) */ 1518 static const struct samsung_pin_bank_data exynos8895_pin_banks6[] __initconst = { 1519 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpd0", 0x00), 1520 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpd1", 0x04), 1521 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpd2", 0x08), 1522 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpd3", 0x0C), 1523 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), 1524 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpe7", 0x14), 1525 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf1", 0x18), 1526 }; 1527 1528 /* pin banks of exynos8895 pin-controller 7 (PERIC1) */ 1529 static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst = { 1530 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpb0", 0x00), 1531 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpc0", 0x04), 1532 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpc1", 0x08), 1533 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpc2", 0x0C), 1534 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), 1535 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpk0", 0x14), 1536 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpe5", 0x18), 1537 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe6", 0x1C), 1538 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe2", 0x20), 1539 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpe3", 0x24), 1540 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe4", 0x28), 1541 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpf0", 0x2C), 1542 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe1", 0x30), 1543 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), 1544 }; 1545 1546 static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = { 1547 { 1548 /* pin-controller instance 0 ALIVE data */ 1549 .pin_banks = exynos8895_pin_banks0, 1550 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks0), 1551 .eint_gpio_init = exynos_eint_gpio_init, 1552 .eint_wkup_init = exynos_eint_wkup_init, 1553 .suspend = exynos_pinctrl_suspend, 1554 .resume = exynos_pinctrl_resume, 1555 }, { 1556 /* pin-controller instance 1 ABOX data */ 1557 .pin_banks = exynos8895_pin_banks1, 1558 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks1), 1559 }, { 1560 /* pin-controller instance 2 VTS data */ 1561 .pin_banks = exynos8895_pin_banks2, 1562 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks2), 1563 .eint_gpio_init = exynos_eint_gpio_init, 1564 }, { 1565 /* pin-controller instance 3 FSYS0 data */ 1566 .pin_banks = exynos8895_pin_banks3, 1567 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks3), 1568 .eint_gpio_init = exynos_eint_gpio_init, 1569 .suspend = exynos_pinctrl_suspend, 1570 .resume = exynos_pinctrl_resume, 1571 }, { 1572 /* pin-controller instance 4 FSYS1 data */ 1573 .pin_banks = exynos8895_pin_banks4, 1574 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks4), 1575 .eint_gpio_init = exynos_eint_gpio_init, 1576 .suspend = exynos_pinctrl_suspend, 1577 .resume = exynos_pinctrl_resume, 1578 }, { 1579 /* pin-controller instance 5 BUSC data */ 1580 .pin_banks = exynos8895_pin_banks5, 1581 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks5), 1582 .eint_gpio_init = exynos_eint_gpio_init, 1583 .suspend = exynos_pinctrl_suspend, 1584 .resume = exynos_pinctrl_resume, 1585 }, { 1586 /* pin-controller instance 6 PERIC0 data */ 1587 .pin_banks = exynos8895_pin_banks6, 1588 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks6), 1589 .eint_gpio_init = exynos_eint_gpio_init, 1590 .suspend = exynos_pinctrl_suspend, 1591 .resume = exynos_pinctrl_resume, 1592 }, { 1593 /* pin-controller instance 7 PERIC1 data */ 1594 .pin_banks = exynos8895_pin_banks7, 1595 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks7), 1596 .eint_gpio_init = exynos_eint_gpio_init, 1597 .suspend = exynos_pinctrl_suspend, 1598 .resume = exynos_pinctrl_resume, 1599 }, 1600 }; 1601 1602 const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = { 1603 .ctrl = exynos8895_pin_ctrl, 1604 .num_ctrl = ARRAY_SIZE(exynos8895_pin_ctrl), 1605 }; 1606 1607 /* 1608 * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three 1609 * gpio/pin-mux/pinconfig controllers. 1610 */ 1611 1612 /* pin banks of FSD pin-controller 0 (FSYS) */ 1613 static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = { 1614 EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00), 1615 EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04), 1616 EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08), 1617 EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c), 1618 EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10), 1619 }; 1620 1621 /* pin banks of FSD pin-controller 1 (PERIC) */ 1622 static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = { 1623 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00), 1624 EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04), 1625 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08), 1626 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c), 1627 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10), 1628 EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14), 1629 EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18), 1630 EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c), 1631 EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20), 1632 EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24), 1633 EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28), 1634 EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), 1635 EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30), 1636 EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34), 1637 EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38), 1638 EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c), 1639 EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 1640 EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44), 1641 EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48), 1642 EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c), 1643 EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50), 1644 }; 1645 1646 /* pin banks of FSD pin-controller 2 (PMU) */ 1647 static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = { 1648 EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"), 1649 }; 1650 1651 static const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = { 1652 { 1653 /* pin-controller instance 0 FSYS0 data */ 1654 .pin_banks = fsd_pin_banks0, 1655 .nr_banks = ARRAY_SIZE(fsd_pin_banks0), 1656 .eint_gpio_init = exynos_eint_gpio_init, 1657 .suspend = exynos_pinctrl_suspend, 1658 .resume = exynos_pinctrl_resume, 1659 }, { 1660 /* pin-controller instance 1 PERIC data */ 1661 .pin_banks = fsd_pin_banks1, 1662 .nr_banks = ARRAY_SIZE(fsd_pin_banks1), 1663 .eint_gpio_init = exynos_eint_gpio_init, 1664 .suspend = exynos_pinctrl_suspend, 1665 .resume = exynos_pinctrl_resume, 1666 }, { 1667 /* pin-controller instance 2 PMU data */ 1668 .pin_banks = fsd_pin_banks2, 1669 .nr_banks = ARRAY_SIZE(fsd_pin_banks2), 1670 }, 1671 }; 1672 1673 const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { 1674 .ctrl = fsd_pin_ctrl, 1675 .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), 1676 }; 1677 1678 /* pin banks of gs101 pin-controller (ALIVE) */ 1679 static const struct samsung_pin_bank_data gs101_pin_alive[] = { 1680 GS101_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00, 0x00), 1681 GS101_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04, 0x08), 1682 GS101_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08, 0x10), 1683 GS101_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c, 0x18), 1684 GS101_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10, 0x1c), 1685 GS101_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14, 0x20), 1686 GS101_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18, 0x28), 1687 GS101_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c, 0x30), 1688 }; 1689 1690 /* pin banks of gs101 pin-controller (FAR_ALIVE) */ 1691 static const struct samsung_pin_bank_data gs101_pin_far_alive[] = { 1692 GS101_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00, 0x00), 1693 GS101_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04, 0x08), 1694 GS101_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08, 0x0c), 1695 GS101_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c, 0x14), 1696 }; 1697 1698 /* pin banks of gs101 pin-controller (GSACORE) */ 1699 static const struct samsung_pin_bank_data gs101_pin_gsacore[] = { 1700 GS101_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00, 0x00), 1701 GS101_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04, 0x04), 1702 GS101_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08, 0x0c), 1703 }; 1704 1705 /* pin banks of gs101 pin-controller (GSACTRL) */ 1706 static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = { 1707 GS101_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00, 0x00), 1708 }; 1709 1710 /* pin banks of gs101 pin-controller (PERIC0) */ 1711 static const struct samsung_pin_bank_data gs101_pin_peric0[] = { 1712 GS101_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00, 0x00), 1713 GS101_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04, 0x08), 1714 GS101_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08, 0x0c), 1715 GS101_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c, 0x10), 1716 GS101_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10, 0x14), 1717 GS101_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14, 0x18), 1718 GS101_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18, 0x1c), 1719 GS101_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c, 0x20), 1720 GS101_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20, 0x24), 1721 GS101_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24, 0x28), 1722 GS101_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28, 0x2c), 1723 GS101_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c, 0x30), 1724 GS101_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30, 0x34), 1725 GS101_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34, 0x38), 1726 GS101_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38, 0x3c), 1727 GS101_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c, 0x40), 1728 GS101_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40, 0x44), 1729 GS101_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44, 0x48), 1730 GS101_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48, 0x4c), 1731 GS101_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c, 0x50), 1732 }; 1733 1734 /* pin banks of gs101 pin-controller (PERIC1) */ 1735 static const struct samsung_pin_bank_data gs101_pin_peric1[] = { 1736 GS101_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00, 0x00), 1737 GS101_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04, 0x08), 1738 GS101_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08, 0x0c), 1739 GS101_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c, 0x10), 1740 GS101_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10, 0x18), 1741 GS101_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14, 0x1c), 1742 GS101_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18, 0x20), 1743 GS101_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c, 0x28), 1744 }; 1745 1746 /* pin banks of gs101 pin-controller (HSI1) */ 1747 static const struct samsung_pin_bank_data gs101_pin_hsi1[] = { 1748 GS101_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00, 0x00), 1749 GS101_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04, 0x08), 1750 }; 1751 1752 /* pin banks of gs101 pin-controller (HSI2) */ 1753 static const struct samsung_pin_bank_data gs101_pin_hsi2[] = { 1754 GS101_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00, 0x00), 1755 GS101_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04, 0x08), 1756 GS101_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08, 0x0c), 1757 }; 1758 1759 static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { 1760 { 1761 /* pin banks of gs101 pin-controller (ALIVE) */ 1762 .pin_banks = gs101_pin_alive, 1763 .nr_banks = ARRAY_SIZE(gs101_pin_alive), 1764 .eint_wkup_init = exynos_eint_wkup_init, 1765 .suspend = gs101_pinctrl_suspend, 1766 .resume = gs101_pinctrl_resume, 1767 }, { 1768 /* pin banks of gs101 pin-controller (FAR_ALIVE) */ 1769 .pin_banks = gs101_pin_far_alive, 1770 .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), 1771 .eint_wkup_init = exynos_eint_wkup_init, 1772 .suspend = gs101_pinctrl_suspend, 1773 .resume = gs101_pinctrl_resume, 1774 }, { 1775 /* pin banks of gs101 pin-controller (GSACORE) */ 1776 .pin_banks = gs101_pin_gsacore, 1777 .nr_banks = ARRAY_SIZE(gs101_pin_gsacore), 1778 }, { 1779 /* pin banks of gs101 pin-controller (GSACTRL) */ 1780 .pin_banks = gs101_pin_gsactrl, 1781 .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl), 1782 }, { 1783 /* pin banks of gs101 pin-controller (PERIC0) */ 1784 .pin_banks = gs101_pin_peric0, 1785 .nr_banks = ARRAY_SIZE(gs101_pin_peric0), 1786 .eint_gpio_init = exynos_eint_gpio_init, 1787 .suspend = gs101_pinctrl_suspend, 1788 .resume = gs101_pinctrl_resume, 1789 }, { 1790 /* pin banks of gs101 pin-controller (PERIC1) */ 1791 .pin_banks = gs101_pin_peric1, 1792 .nr_banks = ARRAY_SIZE(gs101_pin_peric1), 1793 .eint_gpio_init = exynos_eint_gpio_init, 1794 .suspend = gs101_pinctrl_suspend, 1795 .resume = gs101_pinctrl_resume, 1796 }, { 1797 /* pin banks of gs101 pin-controller (HSI1) */ 1798 .pin_banks = gs101_pin_hsi1, 1799 .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), 1800 .eint_gpio_init = exynos_eint_gpio_init, 1801 .suspend = gs101_pinctrl_suspend, 1802 .resume = gs101_pinctrl_resume, 1803 }, { 1804 /* pin banks of gs101 pin-controller (HSI2) */ 1805 .pin_banks = gs101_pin_hsi2, 1806 .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), 1807 .eint_gpio_init = exynos_eint_gpio_init, 1808 .suspend = gs101_pinctrl_suspend, 1809 .resume = gs101_pinctrl_resume, 1810 }, 1811 }; 1812 1813 const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = { 1814 .ctrl = gs101_pin_ctrl, 1815 .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl), 1816 }; 1817