1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver 4 // with eint support. 5 // 6 // Copyright (c) 2012 Samsung Electronics Co., Ltd. 7 // http://www.samsung.com 8 // Copyright (c) 2012 Linaro Ltd 9 // http://www.linaro.org 10 // Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> 11 // 12 // This file contains the Samsung Exynos specific information required by the 13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of 14 // external gpio and wakeup interrupt support. 15 16 #include <linux/slab.h> 17 #include <linux/soc/samsung/exynos-regs-pmu.h> 18 19 #include "pinctrl-samsung.h" 20 #include "pinctrl-exynos.h" 21 22 static const struct samsung_pin_bank_type bank_type_off = { 23 .fld_width = { 4, 1, 2, 2, 2, 2, }, 24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 25 }; 26 27 static const struct samsung_pin_bank_type bank_type_alive = { 28 .fld_width = { 4, 1, 2, 2, }, 29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 30 }; 31 32 /* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */ 33 static const struct samsung_pin_bank_type exynos5433_bank_type_off = { 34 .fld_width = { 4, 1, 2, 4, 2, 2, }, 35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 36 }; 37 38 static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { 39 .fld_width = { 4, 1, 2, 4, }, 40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 41 }; 42 43 /* 44 * Bank type for non-alive type. Bit fields: 45 * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 46 */ 47 static const struct samsung_pin_bank_type exynos850_bank_type_off = { 48 .fld_width = { 4, 1, 4, 4, 2, 4, }, 49 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 50 }; 51 52 /* 53 * Bank type for alive type. Bit fields: 54 * CON: 4, DAT: 1, PUD: 4, DRV: 4 55 */ 56 static const struct samsung_pin_bank_type exynos850_bank_type_alive = { 57 .fld_width = { 4, 1, 4, 4, }, 58 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 59 }; 60 61 /* 62 * Bank type for non-alive type. Bit fields: 63 * CON: 4, DAT: 1, PUD: 2, DRV: 3, CONPDN: 2, PUDPDN: 2 64 */ 65 static const struct samsung_pin_bank_type exynos8895_bank_type_off = { 66 .fld_width = { 4, 1, 2, 3, 2, 2, }, 67 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 68 }; 69 70 /* Pad retention control code for accessing PMU regmap */ 71 static atomic_t exynos_shared_retention_refcnt; 72 73 /* pin banks of exynos5433 pin-controller - ALIVE */ 74 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = { 75 /* Must start with EINTG banks, ordered by EINT group number. */ 76 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 77 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 78 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 79 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 80 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), 81 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), 82 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), 83 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), 84 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), 85 }; 86 87 /* pin banks of exynos5433 pin-controller - AUD */ 88 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = { 89 /* Must start with EINTG banks, ordered by EINT group number. */ 90 EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 91 EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 92 }; 93 94 /* pin banks of exynos5433 pin-controller - CPIF */ 95 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = { 96 /* Must start with EINTG banks, ordered by EINT group number. */ 97 EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), 98 }; 99 100 /* pin banks of exynos5433 pin-controller - eSE */ 101 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = { 102 /* Must start with EINTG banks, ordered by EINT group number. */ 103 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), 104 }; 105 106 /* pin banks of exynos5433 pin-controller - FINGER */ 107 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = { 108 /* Must start with EINTG banks, ordered by EINT group number. */ 109 EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), 110 }; 111 112 /* pin banks of exynos5433 pin-controller - FSYS */ 113 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = { 114 /* Must start with EINTG banks, ordered by EINT group number. */ 115 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), 116 EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), 117 EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), 118 EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), 119 EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), 120 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), 121 }; 122 123 /* pin banks of exynos5433 pin-controller - IMEM */ 124 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = { 125 /* Must start with EINTG banks, ordered by EINT group number. */ 126 EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), 127 }; 128 129 /* pin banks of exynos5433 pin-controller - NFC */ 130 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = { 131 /* Must start with EINTG banks, ordered by EINT group number. */ 132 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 133 }; 134 135 /* pin banks of exynos5433 pin-controller - PERIC */ 136 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = { 137 /* Must start with EINTG banks, ordered by EINT group number. */ 138 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), 139 EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), 140 EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), 141 EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), 142 EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), 143 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), 144 EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), 145 EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), 146 EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), 147 EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), 148 EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), 149 EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), 150 EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), 151 EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), 152 EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), 153 EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), 154 EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 155 }; 156 157 /* pin banks of exynos5433 pin-controller - TOUCH */ 158 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = { 159 /* Must start with EINTG banks, ordered by EINT group number. */ 160 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 161 }; 162 163 /* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */ 164 static const u32 exynos5433_retention_regs[] = { 165 EXYNOS5433_PAD_RETENTION_TOP_OPTION, 166 EXYNOS5433_PAD_RETENTION_UART_OPTION, 167 EXYNOS5433_PAD_RETENTION_EBIA_OPTION, 168 EXYNOS5433_PAD_RETENTION_EBIB_OPTION, 169 EXYNOS5433_PAD_RETENTION_SPI_OPTION, 170 EXYNOS5433_PAD_RETENTION_MIF_OPTION, 171 EXYNOS5433_PAD_RETENTION_USBXTI_OPTION, 172 EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION, 173 EXYNOS5433_PAD_RETENTION_UFS_OPTION, 174 EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION, 175 }; 176 177 static const struct samsung_retention_data exynos5433_retention_data __initconst = { 178 .regs = exynos5433_retention_regs, 179 .nr_regs = ARRAY_SIZE(exynos5433_retention_regs), 180 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 181 .refcnt = &exynos_shared_retention_refcnt, 182 .init = exynos_retention_init, 183 }; 184 185 /* PMU retention control for audio pins can be tied to audio pin bank */ 186 static const u32 exynos5433_audio_retention_regs[] = { 187 EXYNOS5433_PAD_RETENTION_AUD_OPTION, 188 }; 189 190 static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = { 191 .regs = exynos5433_audio_retention_regs, 192 .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs), 193 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 194 .init = exynos_retention_init, 195 }; 196 197 /* PMU retention control for mmc pins can be tied to fsys pin bank */ 198 static const u32 exynos5433_fsys_retention_regs[] = { 199 EXYNOS5433_PAD_RETENTION_MMC0_OPTION, 200 EXYNOS5433_PAD_RETENTION_MMC1_OPTION, 201 EXYNOS5433_PAD_RETENTION_MMC2_OPTION, 202 }; 203 204 static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = { 205 .regs = exynos5433_fsys_retention_regs, 206 .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs), 207 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 208 .init = exynos_retention_init, 209 }; 210 211 /* 212 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes 213 * ten gpio/pin-mux/pinconfig controllers. 214 */ 215 static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { 216 { 217 /* pin-controller instance 0 data */ 218 .pin_banks = exynos5433_pin_banks0, 219 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0), 220 .eint_wkup_init = exynos_eint_wkup_init, 221 .suspend = exynos_pinctrl_suspend, 222 .resume = exynos_pinctrl_resume, 223 .nr_ext_resources = 1, 224 .retention_data = &exynos5433_retention_data, 225 }, { 226 /* pin-controller instance 1 data */ 227 .pin_banks = exynos5433_pin_banks1, 228 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1), 229 .eint_gpio_init = exynos_eint_gpio_init, 230 .suspend = exynos_pinctrl_suspend, 231 .resume = exynos_pinctrl_resume, 232 .retention_data = &exynos5433_audio_retention_data, 233 }, { 234 /* pin-controller instance 2 data */ 235 .pin_banks = exynos5433_pin_banks2, 236 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2), 237 .eint_gpio_init = exynos_eint_gpio_init, 238 .suspend = exynos_pinctrl_suspend, 239 .resume = exynos_pinctrl_resume, 240 .retention_data = &exynos5433_retention_data, 241 }, { 242 /* pin-controller instance 3 data */ 243 .pin_banks = exynos5433_pin_banks3, 244 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3), 245 .eint_gpio_init = exynos_eint_gpio_init, 246 .suspend = exynos_pinctrl_suspend, 247 .resume = exynos_pinctrl_resume, 248 .retention_data = &exynos5433_retention_data, 249 }, { 250 /* pin-controller instance 4 data */ 251 .pin_banks = exynos5433_pin_banks4, 252 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4), 253 .eint_gpio_init = exynos_eint_gpio_init, 254 .suspend = exynos_pinctrl_suspend, 255 .resume = exynos_pinctrl_resume, 256 .retention_data = &exynos5433_retention_data, 257 }, { 258 /* pin-controller instance 5 data */ 259 .pin_banks = exynos5433_pin_banks5, 260 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5), 261 .eint_gpio_init = exynos_eint_gpio_init, 262 .suspend = exynos_pinctrl_suspend, 263 .resume = exynos_pinctrl_resume, 264 .retention_data = &exynos5433_fsys_retention_data, 265 }, { 266 /* pin-controller instance 6 data */ 267 .pin_banks = exynos5433_pin_banks6, 268 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6), 269 .eint_gpio_init = exynos_eint_gpio_init, 270 .suspend = exynos_pinctrl_suspend, 271 .resume = exynos_pinctrl_resume, 272 .retention_data = &exynos5433_retention_data, 273 }, { 274 /* pin-controller instance 7 data */ 275 .pin_banks = exynos5433_pin_banks7, 276 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7), 277 .eint_gpio_init = exynos_eint_gpio_init, 278 .suspend = exynos_pinctrl_suspend, 279 .resume = exynos_pinctrl_resume, 280 .retention_data = &exynos5433_retention_data, 281 }, { 282 /* pin-controller instance 8 data */ 283 .pin_banks = exynos5433_pin_banks8, 284 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8), 285 .eint_gpio_init = exynos_eint_gpio_init, 286 .suspend = exynos_pinctrl_suspend, 287 .resume = exynos_pinctrl_resume, 288 .retention_data = &exynos5433_retention_data, 289 }, { 290 /* pin-controller instance 9 data */ 291 .pin_banks = exynos5433_pin_banks9, 292 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9), 293 .eint_gpio_init = exynos_eint_gpio_init, 294 .suspend = exynos_pinctrl_suspend, 295 .resume = exynos_pinctrl_resume, 296 .retention_data = &exynos5433_retention_data, 297 }, 298 }; 299 300 const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = { 301 .ctrl = exynos5433_pin_ctrl, 302 .num_ctrl = ARRAY_SIZE(exynos5433_pin_ctrl), 303 }; 304 305 /* pin banks of exynos7 pin-controller - ALIVE */ 306 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { 307 /* Must start with EINTG banks, ordered by EINT group number. */ 308 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 309 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 310 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 311 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 312 }; 313 314 /* pin banks of exynos7 pin-controller - BUS0 */ 315 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { 316 /* Must start with EINTG banks, ordered by EINT group number. */ 317 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 318 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04), 319 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08), 320 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c), 321 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), 322 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 323 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 324 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c), 325 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20), 326 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24), 327 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28), 328 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c), 329 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30), 330 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), 331 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38), 332 }; 333 334 /* pin banks of exynos7 pin-controller - NFC */ 335 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = { 336 /* Must start with EINTG banks, ordered by EINT group number. */ 337 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 338 }; 339 340 /* pin banks of exynos7 pin-controller - TOUCH */ 341 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = { 342 /* Must start with EINTG banks, ordered by EINT group number. */ 343 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 344 }; 345 346 /* pin banks of exynos7 pin-controller - FF */ 347 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = { 348 /* Must start with EINTG banks, ordered by EINT group number. */ 349 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00), 350 }; 351 352 /* pin banks of exynos7 pin-controller - ESE */ 353 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = { 354 /* Must start with EINTG banks, ordered by EINT group number. */ 355 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00), 356 }; 357 358 /* pin banks of exynos7 pin-controller - FSYS0 */ 359 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = { 360 /* Must start with EINTG banks, ordered by EINT group number. */ 361 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00), 362 }; 363 364 /* pin banks of exynos7 pin-controller - FSYS1 */ 365 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { 366 /* Must start with EINTG banks, ordered by EINT group number. */ 367 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00), 368 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), 369 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08), 370 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), 371 }; 372 373 /* pin banks of exynos7 pin-controller - BUS1 */ 374 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { 375 /* Must start with EINTG banks, ordered by EINT group number. */ 376 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), 377 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), 378 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08), 379 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c), 380 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10), 381 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14), 382 EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18), 383 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c), 384 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20), 385 EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), 386 }; 387 388 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { 389 /* Must start with EINTG banks, ordered by EINT group number. */ 390 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 391 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 392 }; 393 394 static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { 395 { 396 /* pin-controller instance 0 Alive data */ 397 .pin_banks = exynos7_pin_banks0, 398 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), 399 .eint_wkup_init = exynos_eint_wkup_init, 400 }, { 401 /* pin-controller instance 1 BUS0 data */ 402 .pin_banks = exynos7_pin_banks1, 403 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1), 404 .eint_gpio_init = exynos_eint_gpio_init, 405 }, { 406 /* pin-controller instance 2 NFC data */ 407 .pin_banks = exynos7_pin_banks2, 408 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2), 409 .eint_gpio_init = exynos_eint_gpio_init, 410 }, { 411 /* pin-controller instance 3 TOUCH data */ 412 .pin_banks = exynos7_pin_banks3, 413 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3), 414 .eint_gpio_init = exynos_eint_gpio_init, 415 }, { 416 /* pin-controller instance 4 FF data */ 417 .pin_banks = exynos7_pin_banks4, 418 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4), 419 .eint_gpio_init = exynos_eint_gpio_init, 420 }, { 421 /* pin-controller instance 5 ESE data */ 422 .pin_banks = exynos7_pin_banks5, 423 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5), 424 .eint_gpio_init = exynos_eint_gpio_init, 425 }, { 426 /* pin-controller instance 6 FSYS0 data */ 427 .pin_banks = exynos7_pin_banks6, 428 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6), 429 .eint_gpio_init = exynos_eint_gpio_init, 430 }, { 431 /* pin-controller instance 7 FSYS1 data */ 432 .pin_banks = exynos7_pin_banks7, 433 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), 434 .eint_gpio_init = exynos_eint_gpio_init, 435 }, { 436 /* pin-controller instance 8 BUS1 data */ 437 .pin_banks = exynos7_pin_banks8, 438 .nr_banks = ARRAY_SIZE(exynos7_pin_banks8), 439 .eint_gpio_init = exynos_eint_gpio_init, 440 }, { 441 /* pin-controller instance 9 AUD data */ 442 .pin_banks = exynos7_pin_banks9, 443 .nr_banks = ARRAY_SIZE(exynos7_pin_banks9), 444 .eint_gpio_init = exynos_eint_gpio_init, 445 }, 446 }; 447 448 const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { 449 .ctrl = exynos7_pin_ctrl, 450 .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), 451 }; 452 453 /* pin banks of exynos7885 pin-controller 0 (ALIVE) */ 454 static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = { 455 EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"), 456 EXYNOS_PIN_BANK_EINTN(3, 0x020, "etc1"), 457 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00), 458 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04), 459 EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08), 460 EXYNOS850_PIN_BANK_EINTW(5, 0x0a0, "gpq0", 0x0c), 461 }; 462 463 /* pin banks of exynos7885 pin-controller 1 (DISPAUD) */ 464 static const struct samsung_pin_bank_data exynos7885_pin_banks1[] __initconst = { 465 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 466 EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04), 467 EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08), 468 }; 469 470 /* pin banks of exynos7885 pin-controller 2 (FSYS) */ 471 static const struct samsung_pin_bank_data exynos7885_pin_banks2[] __initconst = { 472 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), 473 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf2", 0x04), 474 EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf3", 0x08), 475 EXYNOS850_PIN_BANK_EINTG(6, 0x060, "gpf4", 0x0c), 476 }; 477 478 /* pin banks of exynos7885 pin-controller 3 (TOP) */ 479 static const struct samsung_pin_bank_data exynos7885_pin_banks3[] __initconst = { 480 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpp0", 0x00), 481 EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gpg0", 0x04), 482 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), 483 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), 484 EXYNOS850_PIN_BANK_EINTG(3, 0x080, "gpp3", 0x10), 485 EXYNOS850_PIN_BANK_EINTG(6, 0x0a0, "gpp4", 0x14), 486 EXYNOS850_PIN_BANK_EINTG(4, 0x0c0, "gpp5", 0x18), 487 EXYNOS850_PIN_BANK_EINTG(5, 0x0e0, "gpp6", 0x1c), 488 EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpp7", 0x20), 489 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp8", 0x24), 490 EXYNOS850_PIN_BANK_EINTG(8, 0x140, "gpg1", 0x28), 491 EXYNOS850_PIN_BANK_EINTG(8, 0x160, "gpg2", 0x2c), 492 EXYNOS850_PIN_BANK_EINTG(8, 0x180, "gpg3", 0x30), 493 EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpg4", 0x34), 494 EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpc0", 0x38), 495 EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpc1", 0x3c), 496 EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpc2", 0x40), 497 }; 498 499 static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = { 500 { 501 /* pin-controller instance 0 Alive data */ 502 .pin_banks = exynos7885_pin_banks0, 503 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks0), 504 .eint_gpio_init = exynos_eint_gpio_init, 505 .eint_wkup_init = exynos_eint_wkup_init, 506 .suspend = exynos_pinctrl_suspend, 507 .resume = exynos_pinctrl_resume, 508 }, { 509 /* pin-controller instance 1 DISPAUD data */ 510 .pin_banks = exynos7885_pin_banks1, 511 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks1), 512 }, { 513 /* pin-controller instance 2 FSYS data */ 514 .pin_banks = exynos7885_pin_banks2, 515 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks2), 516 .eint_gpio_init = exynos_eint_gpio_init, 517 .suspend = exynos_pinctrl_suspend, 518 .resume = exynos_pinctrl_resume, 519 }, { 520 /* pin-controller instance 3 TOP data */ 521 .pin_banks = exynos7885_pin_banks3, 522 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks3), 523 .eint_gpio_init = exynos_eint_gpio_init, 524 .suspend = exynos_pinctrl_suspend, 525 .resume = exynos_pinctrl_resume, 526 }, 527 }; 528 529 const struct samsung_pinctrl_of_match_data exynos7885_of_data __initconst = { 530 .ctrl = exynos7885_pin_ctrl, 531 .num_ctrl = ARRAY_SIZE(exynos7885_pin_ctrl), 532 }; 533 534 /* pin banks of exynos850 pin-controller 0 (ALIVE) */ 535 static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { 536 /* Must start with EINTG banks, ordered by EINT group number. */ 537 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 538 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 539 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 540 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 541 EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), 542 EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"), 543 }; 544 545 /* pin banks of exynos850 pin-controller 1 (CMGP) */ 546 static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = { 547 /* Must start with EINTG banks, ordered by EINT group number. */ 548 EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), 549 EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), 550 EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), 551 EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c), 552 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), 553 EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14), 554 EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18), 555 EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c), 556 }; 557 558 /* pin banks of exynos850 pin-controller 2 (AUD) */ 559 static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = { 560 /* Must start with EINTG banks, ordered by EINT group number. */ 561 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 562 EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), 563 }; 564 565 /* pin banks of exynos850 pin-controller 3 (HSI) */ 566 static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = { 567 /* Must start with EINTG banks, ordered by EINT group number. */ 568 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), 569 }; 570 571 /* pin banks of exynos850 pin-controller 4 (CORE) */ 572 static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = { 573 /* Must start with EINTG banks, ordered by EINT group number. */ 574 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), 575 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), 576 }; 577 578 /* pin banks of exynos850 pin-controller 5 (PERI) */ 579 static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = { 580 /* Must start with EINTG banks, ordered by EINT group number. */ 581 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), 582 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), 583 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), 584 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), 585 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), 586 EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14), 587 EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18), 588 EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c), 589 EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), 590 }; 591 592 static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { 593 { 594 /* pin-controller instance 0 ALIVE data */ 595 .pin_banks = exynos850_pin_banks0, 596 .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), 597 .eint_wkup_init = exynos_eint_wkup_init, 598 }, { 599 /* pin-controller instance 1 CMGP data */ 600 .pin_banks = exynos850_pin_banks1, 601 .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), 602 .eint_wkup_init = exynos_eint_wkup_init, 603 }, { 604 /* pin-controller instance 2 AUD data */ 605 .pin_banks = exynos850_pin_banks2, 606 .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), 607 }, { 608 /* pin-controller instance 3 HSI data */ 609 .pin_banks = exynos850_pin_banks3, 610 .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), 611 .eint_gpio_init = exynos_eint_gpio_init, 612 }, { 613 /* pin-controller instance 4 CORE data */ 614 .pin_banks = exynos850_pin_banks4, 615 .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), 616 .eint_gpio_init = exynos_eint_gpio_init, 617 }, { 618 /* pin-controller instance 5 PERI data */ 619 .pin_banks = exynos850_pin_banks5, 620 .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), 621 .eint_gpio_init = exynos_eint_gpio_init, 622 }, 623 }; 624 625 const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { 626 .ctrl = exynos850_pin_ctrl, 627 .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), 628 }; 629 630 /* pin banks of exynos990 pin-controller 0 (ALIVE) */ 631 static struct samsung_pin_bank_data exynos990_pin_banks0[] = { 632 /* Must start with EINTG banks, ordered by EINT group number. */ 633 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 634 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 635 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 636 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 637 EXYNOS850_PIN_BANK_EINTW(2, 0x080, "gpa4", 0x10), 638 EXYNOS850_PIN_BANK_EINTN(7, 0x0A0, "gpq0"), 639 }; 640 641 /* pin banks of exynos990 pin-controller 1 (CMGP) */ 642 static struct samsung_pin_bank_data exynos990_pin_banks1[] = { 643 /* Must start with EINTG banks, ordered by EINT group number. */ 644 EXYNOS850_PIN_BANK_EINTN(1, 0x000, "gpm0"), 645 EXYNOS850_PIN_BANK_EINTN(1, 0x020, "gpm1"), 646 EXYNOS850_PIN_BANK_EINTN(1, 0x040, "gpm2"), 647 EXYNOS850_PIN_BANK_EINTN(1, 0x060, "gpm3"), 648 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x00), 649 EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x04), 650 EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x08), 651 EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x0c), 652 EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x10), 653 EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x14), 654 EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x18), 655 EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x1c), 656 EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x20), 657 EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x24), 658 EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x28), 659 EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x2c), 660 EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x30), 661 EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x34), 662 EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x38), 663 EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x3c), 664 EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x40), 665 EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x44), 666 EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x48), 667 EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x4c), 668 EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x50), 669 EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x54), 670 EXYNOS850_PIN_BANK_EINTW(1, 0x340, "gpm26", 0x58), 671 EXYNOS850_PIN_BANK_EINTW(1, 0x360, "gpm27", 0x5c), 672 EXYNOS850_PIN_BANK_EINTW(1, 0x380, "gpm28", 0x60), 673 EXYNOS850_PIN_BANK_EINTW(1, 0x3A0, "gpm29", 0x64), 674 EXYNOS850_PIN_BANK_EINTW(1, 0x3C0, "gpm30", 0x68), 675 EXYNOS850_PIN_BANK_EINTW(1, 0x3E0, "gpm31", 0x6c), 676 EXYNOS850_PIN_BANK_EINTW(1, 0x400, "gpm32", 0x70), 677 EXYNOS850_PIN_BANK_EINTW(1, 0x420, "gpm33", 0x74), 678 679 }; 680 681 /* pin banks of exynos990 pin-controller 2 (HSI1) */ 682 static struct samsung_pin_bank_data exynos990_pin_banks2[] = { 683 /* Must start with EINTG banks, ordered by EINT group number. */ 684 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), 685 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), 686 EXYNOS850_PIN_BANK_EINTG(3, 0x040, "gpf2", 0x08), 687 }; 688 689 /* pin banks of exynos990 pin-controller 3 (HSI2) */ 690 static struct samsung_pin_bank_data exynos990_pin_banks3[] = { 691 /* Must start with EINTG banks, ordered by EINT group number. */ 692 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf3", 0x00), 693 }; 694 695 /* pin banks of exynos990 pin-controller 4 (PERIC0) */ 696 static struct samsung_pin_bank_data exynos990_pin_banks4[] = { 697 /* Must start with EINTG banks, ordered by EINT group number. */ 698 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), 699 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), 700 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), 701 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp3", 0x0C), 702 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp4", 0x10), 703 EXYNOS850_PIN_BANK_EINTG(2, 0x0A0, "gpg0", 0x14), 704 }; 705 706 /* pin banks of exynos990 pin-controller 5 (PERIC1) */ 707 static struct samsung_pin_bank_data exynos990_pin_banks5[] = { 708 /* Must start with EINTG banks, ordered by EINT group number. */ 709 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp5", 0x00), 710 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp6", 0x04), 711 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp7", 0x08), 712 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp8", 0x0C), 713 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp9", 0x10), 714 EXYNOS850_PIN_BANK_EINTG(6, 0x0A0, "gpc0", 0x14), 715 EXYNOS850_PIN_BANK_EINTG(4, 0x0C0, "gpg1", 0x18), 716 EXYNOS850_PIN_BANK_EINTG(8, 0x0E0, "gpb0", 0x1C), 717 EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb1", 0x20), 718 EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb2", 0x24), 719 }; 720 721 /* pin banks of exynos990 pin-controller 6 (VTS) */ 722 static struct samsung_pin_bank_data exynos990_pin_banks6[] = { 723 /* Must start with EINTG banks, ordered by EINT group number. */ 724 EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpv0", 0x00), 725 }; 726 727 static const struct samsung_pin_ctrl exynos990_pin_ctrl[] __initconst = { 728 { 729 /* pin-controller instance 0 ALIVE data */ 730 .pin_banks = exynos990_pin_banks0, 731 .nr_banks = ARRAY_SIZE(exynos990_pin_banks0), 732 .eint_wkup_init = exynos_eint_wkup_init, 733 }, { 734 /* pin-controller instance 1 CMGP data */ 735 .pin_banks = exynos990_pin_banks1, 736 .nr_banks = ARRAY_SIZE(exynos990_pin_banks1), 737 .eint_wkup_init = exynos_eint_wkup_init, 738 }, { 739 /* pin-controller instance 2 HSI1 data */ 740 .pin_banks = exynos990_pin_banks2, 741 .nr_banks = ARRAY_SIZE(exynos990_pin_banks2), 742 .eint_gpio_init = exynos_eint_gpio_init, 743 }, { 744 /* pin-controller instance 3 HSI2 data */ 745 .pin_banks = exynos990_pin_banks3, 746 .nr_banks = ARRAY_SIZE(exynos990_pin_banks3), 747 .eint_gpio_init = exynos_eint_gpio_init, 748 }, { 749 /* pin-controller instance 4 PERIC0 data */ 750 .pin_banks = exynos990_pin_banks4, 751 .nr_banks = ARRAY_SIZE(exynos990_pin_banks4), 752 .eint_gpio_init = exynos_eint_gpio_init, 753 }, { 754 /* pin-controller instance 5 PERIC1 data */ 755 .pin_banks = exynos990_pin_banks5, 756 .nr_banks = ARRAY_SIZE(exynos990_pin_banks5), 757 .eint_gpio_init = exynos_eint_gpio_init, 758 }, { 759 /* pin-controller instance 6 VTS data */ 760 .pin_banks = exynos990_pin_banks6, 761 .nr_banks = ARRAY_SIZE(exynos990_pin_banks6), 762 }, 763 }; 764 765 const struct samsung_pinctrl_of_match_data exynos990_of_data __initconst = { 766 .ctrl = exynos990_pin_ctrl, 767 .num_ctrl = ARRAY_SIZE(exynos990_pin_ctrl), 768 }; 769 770 /* pin banks of exynos9810 pin-controller 0 (ALIVE) */ 771 static const struct samsung_pin_bank_data exynos9810_pin_banks0[] __initconst = { 772 EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc1"), 773 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), 774 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), 775 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), 776 EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), 777 EXYNOS850_PIN_BANK_EINTN(6, 0x0A0, "gpq0"), 778 EXYNOS850_PIN_BANK_EINTW(2, 0x0C0, "gpa4", 0x10), 779 }; 780 781 /* pin banks of exynos9810 pin-controller 1 (AUD) */ 782 static const struct samsung_pin_bank_data exynos9810_pin_banks1[] __initconst = { 783 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 784 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), 785 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpb2", 0x08), 786 }; 787 788 /* pin banks of exynos9810 pin-controller 2 (CHUB) */ 789 static const struct samsung_pin_bank_data exynos9810_pin_banks2[] __initconst = { 790 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), 791 EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gph1", 0x04), 792 }; 793 794 /* pin banks of exynos9810 pin-controller 3 (CMGP) */ 795 static const struct samsung_pin_bank_data exynos9810_pin_banks3[] __initconst = { 796 EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), 797 EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), 798 EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), 799 EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), 800 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), 801 EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), 802 EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), 803 EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), 804 EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm10", 0x20), 805 EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm11", 0x24), 806 EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm12", 0x28), 807 EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm13", 0x2C), 808 EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm14", 0x30), 809 EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm15", 0x34), 810 EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm16", 0x38), 811 EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm17", 0x3C), 812 EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm40", 0x40), 813 EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm41", 0x44), 814 EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm42", 0x48), 815 EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm43", 0x4C), 816 }; 817 818 /* pin banks of exynos9810 pin-controller 4 (FSYS0) */ 819 static const struct samsung_pin_bank_data exynos9810_pin_banks4[] __initconst = { 820 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf0", 0x00), 821 }; 822 823 /* pin banks of exynos9810 pin-controller 5 (FSYS1) */ 824 static const struct samsung_pin_bank_data exynos9810_pin_banks5[] __initconst = { 825 EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpf1", 0x00), 826 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf2", 0x04), 827 }; 828 829 /* pin banks of exynos9810 pin-controller 6 (PERIC0) */ 830 static const struct samsung_pin_bank_data exynos9810_pin_banks6[] __initconst = { 831 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), 832 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), 833 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), 834 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp3", 0x0C), 835 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 836 EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 837 EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg2", 0x18), 838 }; 839 840 /* pin banks of exynos9810 pin-controller 7 (PERIC1) */ 841 static const struct samsung_pin_bank_data exynos9810_pin_banks7[] __initconst = { 842 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp4", 0x00), 843 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp5", 0x04), 844 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp6", 0x08), 845 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C), 846 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10), 847 EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 848 EXYNOS850_PIN_BANK_EINTG(7, 0x0C0, "gpg3", 0x18), 849 }; 850 851 /* pin banks of exynos9810 pin-controller 8 (VTS) */ 852 static const struct samsung_pin_bank_data exynos9810_pin_banks8[] __initconst = { 853 EXYNOS850_PIN_BANK_EINTG(3, 0x000, "gpt0", 0x00), 854 }; 855 856 static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = { 857 { 858 /* pin-controller instance 0 ALIVE data */ 859 .pin_banks = exynos9810_pin_banks0, 860 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks0), 861 .eint_wkup_init = exynos_eint_wkup_init, 862 .eint_gpio_init = exynos_eint_gpio_init, 863 .suspend = exynos_pinctrl_suspend, 864 .resume = exynos_pinctrl_resume, 865 }, { 866 /* pin-controller instance 1 AUD data */ 867 .pin_banks = exynos9810_pin_banks1, 868 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks1), 869 }, { 870 /* pin-controller instance 2 CHUB data */ 871 .pin_banks = exynos9810_pin_banks2, 872 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks2), 873 .eint_gpio_init = exynos_eint_gpio_init, 874 .suspend = exynos_pinctrl_suspend, 875 .resume = exynos_pinctrl_resume, 876 }, { 877 /* pin-controller instance 3 CMGP data */ 878 .pin_banks = exynos9810_pin_banks3, 879 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks3), 880 .eint_wkup_init = exynos_eint_wkup_init, 881 .eint_gpio_init = exynos_eint_gpio_init, 882 .suspend = exynos_pinctrl_suspend, 883 .resume = exynos_pinctrl_resume, 884 }, { 885 /* pin-controller instance 4 FSYS0 data */ 886 .pin_banks = exynos9810_pin_banks4, 887 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks4), 888 .eint_gpio_init = exynos_eint_gpio_init, 889 .suspend = exynos_pinctrl_suspend, 890 .resume = exynos_pinctrl_resume, 891 }, { 892 /* pin-controller instance 5 FSYS1 data */ 893 .pin_banks = exynos9810_pin_banks5, 894 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks5), 895 .eint_gpio_init = exynos_eint_gpio_init, 896 .suspend = exynos_pinctrl_suspend, 897 .resume = exynos_pinctrl_resume, 898 }, { 899 /* pin-controller instance 6 PERIC0 data */ 900 .pin_banks = exynos9810_pin_banks6, 901 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks6), 902 .eint_gpio_init = exynos_eint_gpio_init, 903 .suspend = exynos_pinctrl_suspend, 904 .resume = exynos_pinctrl_resume, 905 }, { 906 /* pin-controller instance 7 PERIC1 data */ 907 .pin_banks = exynos9810_pin_banks7, 908 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks7), 909 .eint_gpio_init = exynos_eint_gpio_init, 910 .suspend = exynos_pinctrl_suspend, 911 .resume = exynos_pinctrl_resume, 912 }, { 913 /* pin-controller instance 8 VTS data */ 914 .pin_banks = exynos9810_pin_banks8, 915 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks8), 916 }, 917 }; 918 919 const struct samsung_pinctrl_of_match_data exynos9810_of_data __initconst = { 920 .ctrl = exynos9810_pin_ctrl, 921 .num_ctrl = ARRAY_SIZE(exynos9810_pin_ctrl), 922 }; 923 924 /* pin banks of exynosautov9 pin-controller 0 (ALIVE) */ 925 static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = { 926 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 927 EXYNOS850_PIN_BANK_EINTW(2, 0x020, "gpa1", 0x04), 928 EXYNOS850_PIN_BANK_EINTN(2, 0x040, "gpq0"), 929 }; 930 931 /* pin banks of exynosautov9 pin-controller 1 (AUD) */ 932 static const struct samsung_pin_bank_data exynosautov9_pin_banks1[] __initconst = { 933 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 934 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), 935 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpb2", 0x08), 936 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpb3", 0x0C), 937 }; 938 939 /* pin banks of exynosautov9 pin-controller 2 (FSYS0) */ 940 static const struct samsung_pin_bank_data exynosautov9_pin_banks2[] __initconst = { 941 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf0", 0x00), 942 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), 943 }; 944 945 /* pin banks of exynosautov9 pin-controller 3 (FSYS1) */ 946 static const struct samsung_pin_bank_data exynosautov9_pin_banks3[] __initconst = { 947 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf8", 0x00), 948 }; 949 950 /* pin banks of exynosautov9 pin-controller 4 (FSYS2) */ 951 static const struct samsung_pin_bank_data exynosautov9_pin_banks4[] __initconst = { 952 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf2", 0x00), 953 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf3", 0x04), 954 EXYNOS850_PIN_BANK_EINTG(7, 0x040, "gpf4", 0x08), 955 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpf5", 0x0C), 956 EXYNOS850_PIN_BANK_EINTG(7, 0x080, "gpf6", 0x10), 957 }; 958 959 /* pin banks of exynosautov9 pin-controller 5 (PERIC0) */ 960 static const struct samsung_pin_bank_data exynosautov9_pin_banks5[] __initconst = { 961 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), 962 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), 963 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), 964 EXYNOS850_PIN_BANK_EINTG(5, 0x060, "gpg0", 0x0C), 965 }; 966 967 /* pin banks of exynosautov9 pin-controller 6 (PERIC1) */ 968 static const struct samsung_pin_bank_data exynosautov9_pin_banks6[] __initconst = { 969 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp3", 0x00), 970 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp4", 0x04), 971 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp5", 0x08), 972 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpg1", 0x0C), 973 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg2", 0x10), 974 EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpg3", 0x14), 975 }; 976 977 static const struct samsung_pin_ctrl exynosautov9_pin_ctrl[] __initconst = { 978 { 979 /* pin-controller instance 0 ALIVE data */ 980 .pin_banks = exynosautov9_pin_banks0, 981 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks0), 982 .eint_wkup_init = exynos_eint_wkup_init, 983 .suspend = exynos_pinctrl_suspend, 984 .resume = exynos_pinctrl_resume, 985 }, { 986 /* pin-controller instance 1 AUD data */ 987 .pin_banks = exynosautov9_pin_banks1, 988 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks1), 989 }, { 990 /* pin-controller instance 2 FSYS0 data */ 991 .pin_banks = exynosautov9_pin_banks2, 992 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks2), 993 .eint_gpio_init = exynos_eint_gpio_init, 994 .suspend = exynos_pinctrl_suspend, 995 .resume = exynos_pinctrl_resume, 996 }, { 997 /* pin-controller instance 3 FSYS1 data */ 998 .pin_banks = exynosautov9_pin_banks3, 999 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks3), 1000 .eint_gpio_init = exynos_eint_gpio_init, 1001 .suspend = exynos_pinctrl_suspend, 1002 .resume = exynos_pinctrl_resume, 1003 }, { 1004 /* pin-controller instance 4 FSYS2 data */ 1005 .pin_banks = exynosautov9_pin_banks4, 1006 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks4), 1007 .eint_gpio_init = exynos_eint_gpio_init, 1008 .suspend = exynos_pinctrl_suspend, 1009 .resume = exynos_pinctrl_resume, 1010 }, { 1011 /* pin-controller instance 5 PERIC0 data */ 1012 .pin_banks = exynosautov9_pin_banks5, 1013 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks5), 1014 .eint_gpio_init = exynos_eint_gpio_init, 1015 .suspend = exynos_pinctrl_suspend, 1016 .resume = exynos_pinctrl_resume, 1017 }, { 1018 /* pin-controller instance 6 PERIC1 data */ 1019 .pin_banks = exynosautov9_pin_banks6, 1020 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks6), 1021 .eint_gpio_init = exynos_eint_gpio_init, 1022 .suspend = exynos_pinctrl_suspend, 1023 .resume = exynos_pinctrl_resume, 1024 }, 1025 }; 1026 1027 const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = { 1028 .ctrl = exynosautov9_pin_ctrl, 1029 .num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl), 1030 }; 1031 1032 /* pin banks of exynosautov920 pin-controller 0 (ALIVE) */ 1033 static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = { 1034 EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28), 1035 EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24), 1036 EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"), 1037 }; 1038 1039 /* pin banks of exynosautov920 pin-controller 1 (AUD) */ 1040 static const struct samsung_pin_bank_data exynosautov920_pin_banks1[] = { 1041 EXYNOSV920_PIN_BANK_EINTG(7, 0x0000, "gpb0", 0x18, 0x24, 0x28), 1042 EXYNOSV920_PIN_BANK_EINTG(6, 0x1000, "gpb1", 0x18, 0x24, 0x28), 1043 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpb2", 0x18, 0x24, 0x28), 1044 EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpb3", 0x18, 0x24, 0x28), 1045 EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpb4", 0x18, 0x24, 0x28), 1046 EXYNOSV920_PIN_BANK_EINTG(5, 0x5000, "gpb5", 0x18, 0x24, 0x28), 1047 EXYNOSV920_PIN_BANK_EINTG(5, 0x6000, "gpb6", 0x18, 0x24, 0x28), 1048 }; 1049 1050 /* pin banks of exynosautov920 pin-controller 2 (HSI0) */ 1051 static const struct samsung_pin_bank_data exynosautov920_pin_banks2[] = { 1052 EXYNOSV920_PIN_BANK_EINTG(6, 0x0000, "gph0", 0x18, 0x24, 0x28), 1053 EXYNOSV920_PIN_BANK_EINTG(2, 0x1000, "gph1", 0x18, 0x20, 0x24), 1054 }; 1055 1056 /* pin banks of exynosautov920 pin-controller 3 (HSI1) */ 1057 static const struct samsung_pin_bank_data exynosautov920_pin_banks3[] = { 1058 EXYNOSV920_PIN_BANK_EINTG(7, 0x000, "gph8", 0x18, 0x24, 0x28), 1059 }; 1060 1061 /* pin banks of exynosautov920 pin-controller 4 (HSI2) */ 1062 static const struct samsung_pin_bank_data exynosautov920_pin_banks4[] = { 1063 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gph3", 0x18, 0x24, 0x28), 1064 EXYNOSV920_PIN_BANK_EINTG(7, 0x1000, "gph4", 0x18, 0x24, 0x28), 1065 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gph5", 0x18, 0x24, 0x28), 1066 EXYNOSV920_PIN_BANK_EINTG(7, 0x3000, "gph6", 0x18, 0x24, 0x28), 1067 }; 1068 1069 /* pin banks of exynosautov920 pin-controller 5 (HSI2UFS) */ 1070 static const struct samsung_pin_bank_data exynosautov920_pin_banks5[] = { 1071 EXYNOSV920_PIN_BANK_EINTG(4, 0x000, "gph2", 0x18, 0x20, 0x24), 1072 }; 1073 1074 /* pin banks of exynosautov920 pin-controller 6 (PERIC0) */ 1075 static const struct samsung_pin_bank_data exynosautov920_pin_banks6[] = { 1076 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp0", 0x18, 0x24, 0x28), 1077 EXYNOSV920_PIN_BANK_EINTG(8, 0x1000, "gpp1", 0x18, 0x24, 0x28), 1078 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpp2", 0x18, 0x24, 0x28), 1079 EXYNOSV920_PIN_BANK_EINTG(5, 0x3000, "gpg0", 0x18, 0x24, 0x28), 1080 EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpp3", 0x18, 0x24, 0x28), 1081 EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp4", 0x18, 0x20, 0x24), 1082 EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpg2", 0x18, 0x20, 0x24), 1083 EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpg5", 0x18, 0x20, 0x24), 1084 EXYNOSV920_PIN_BANK_EINTG(3, 0x8000, "gpg3", 0x18, 0x20, 0x24), 1085 EXYNOSV920_PIN_BANK_EINTG(5, 0x9000, "gpg4", 0x18, 0x24, 0x28), 1086 }; 1087 1088 /* pin banks of exynosautov920 pin-controller 7 (PERIC1) */ 1089 static const struct samsung_pin_bank_data exynosautov920_pin_banks7[] = { 1090 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp5", 0x18, 0x24, 0x28), 1091 EXYNOSV920_PIN_BANK_EINTG(5, 0x1000, "gpp6", 0x18, 0x24, 0x28), 1092 EXYNOSV920_PIN_BANK_EINTG(4, 0x2000, "gpp10", 0x18, 0x20, 0x24), 1093 EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpp7", 0x18, 0x24, 0x28), 1094 EXYNOSV920_PIN_BANK_EINTG(4, 0x4000, "gpp8", 0x18, 0x20, 0x24), 1095 EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp11", 0x18, 0x20, 0x24), 1096 EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpp9", 0x18, 0x20, 0x24), 1097 EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpp12", 0x18, 0x20, 0x24), 1098 EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28), 1099 }; 1100 1101 static const struct samsung_retention_data exynosautov920_retention_data __initconst = { 1102 .regs = NULL, 1103 .nr_regs = 0, 1104 .value = 0, 1105 .refcnt = &exynos_shared_retention_refcnt, 1106 .init = exynos_retention_init, 1107 }; 1108 1109 static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = { 1110 { 1111 /* pin-controller instance 0 ALIVE data */ 1112 .pin_banks = exynosautov920_pin_banks0, 1113 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0), 1114 .eint_wkup_init = exynos_eint_wkup_init, 1115 .suspend = exynos_pinctrl_suspend, 1116 .resume = exynos_pinctrl_resume, 1117 .retention_data = &exynosautov920_retention_data, 1118 }, { 1119 /* pin-controller instance 1 AUD data */ 1120 .pin_banks = exynosautov920_pin_banks1, 1121 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks1), 1122 }, { 1123 /* pin-controller instance 2 HSI0 data */ 1124 .pin_banks = exynosautov920_pin_banks2, 1125 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2), 1126 .eint_gpio_init = exynos_eint_gpio_init, 1127 .suspend = exynos_pinctrl_suspend, 1128 .resume = exynos_pinctrl_resume, 1129 }, { 1130 /* pin-controller instance 3 HSI1 data */ 1131 .pin_banks = exynosautov920_pin_banks3, 1132 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3), 1133 .eint_gpio_init = exynos_eint_gpio_init, 1134 .suspend = exynos_pinctrl_suspend, 1135 .resume = exynos_pinctrl_resume, 1136 }, { 1137 /* pin-controller instance 4 HSI2 data */ 1138 .pin_banks = exynosautov920_pin_banks4, 1139 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4), 1140 .eint_gpio_init = exynos_eint_gpio_init, 1141 .suspend = exynos_pinctrl_suspend, 1142 .resume = exynos_pinctrl_resume, 1143 }, { 1144 /* pin-controller instance 5 HSI2UFS data */ 1145 .pin_banks = exynosautov920_pin_banks5, 1146 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5), 1147 .eint_gpio_init = exynos_eint_gpio_init, 1148 .suspend = exynos_pinctrl_suspend, 1149 .resume = exynos_pinctrl_resume, 1150 }, { 1151 /* pin-controller instance 6 PERIC0 data */ 1152 .pin_banks = exynosautov920_pin_banks6, 1153 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6), 1154 .eint_gpio_init = exynos_eint_gpio_init, 1155 .suspend = exynos_pinctrl_suspend, 1156 .resume = exynos_pinctrl_resume, 1157 }, { 1158 /* pin-controller instance 7 PERIC1 data */ 1159 .pin_banks = exynosautov920_pin_banks7, 1160 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7), 1161 .eint_gpio_init = exynos_eint_gpio_init, 1162 .suspend = exynos_pinctrl_suspend, 1163 .resume = exynos_pinctrl_resume, 1164 }, 1165 }; 1166 1167 const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = { 1168 .ctrl = exynosautov920_pin_ctrl, 1169 .num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl), 1170 }; 1171 1172 /* pin banks of exynos8895 pin-controller 0 (ALIVE) */ 1173 static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = { 1174 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), 1175 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), 1176 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), 1177 EXYNOS_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), 1178 EXYNOS_PIN_BANK_EINTW(7, 0x0a0, "gpa4", 0x24), 1179 }; 1180 1181 /* pin banks of exynos8895 pin-controller 1 (ABOX) */ 1182 static const struct samsung_pin_bank_data exynos8895_pin_banks1[] __initconst = { 1183 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), 1184 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gph1", 0x04), 1185 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gph3", 0x08), 1186 }; 1187 1188 /* pin banks of exynos8895 pin-controller 2 (VTS) */ 1189 static const struct samsung_pin_bank_data exynos8895_pin_banks2[] __initconst = { 1190 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gph2", 0x00), 1191 }; 1192 1193 /* pin banks of exynos8895 pin-controller 3 (FSYS0) */ 1194 static const struct samsung_pin_bank_data exynos8895_pin_banks3[] __initconst = { 1195 EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpi0", 0x00), 1196 EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi1", 0x04), 1197 }; 1198 1199 /* pin banks of exynos8895 pin-controller 4 (FSYS1) */ 1200 static const struct samsung_pin_bank_data exynos8895_pin_banks4[] __initconst = { 1201 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj1", 0x00), 1202 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpj0", 0x04), 1203 }; 1204 1205 /* pin banks of exynos8895 pin-controller 5 (BUSC) */ 1206 static const struct samsung_pin_bank_data exynos8895_pin_banks5[] __initconst = { 1207 EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpb2", 0x00), 1208 }; 1209 1210 /* pin banks of exynos8895 pin-controller 6 (PERIC0) */ 1211 static const struct samsung_pin_bank_data exynos8895_pin_banks6[] __initconst = { 1212 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpd0", 0x00), 1213 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpd1", 0x04), 1214 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpd2", 0x08), 1215 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpd3", 0x0C), 1216 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), 1217 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpe7", 0x14), 1218 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf1", 0x18), 1219 }; 1220 1221 /* pin banks of exynos8895 pin-controller 7 (PERIC1) */ 1222 static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst = { 1223 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpb0", 0x00), 1224 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpc0", 0x04), 1225 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpc1", 0x08), 1226 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpc2", 0x0C), 1227 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), 1228 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpk0", 0x14), 1229 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpe5", 0x18), 1230 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe6", 0x1C), 1231 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe2", 0x20), 1232 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpe3", 0x24), 1233 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe4", 0x28), 1234 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpf0", 0x2C), 1235 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe1", 0x30), 1236 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), 1237 }; 1238 1239 static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = { 1240 { 1241 /* pin-controller instance 0 ALIVE data */ 1242 .pin_banks = exynos8895_pin_banks0, 1243 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks0), 1244 .eint_gpio_init = exynos_eint_gpio_init, 1245 .eint_wkup_init = exynos_eint_wkup_init, 1246 .suspend = exynos_pinctrl_suspend, 1247 .resume = exynos_pinctrl_resume, 1248 }, { 1249 /* pin-controller instance 1 ABOX data */ 1250 .pin_banks = exynos8895_pin_banks1, 1251 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks1), 1252 }, { 1253 /* pin-controller instance 2 VTS data */ 1254 .pin_banks = exynos8895_pin_banks2, 1255 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks2), 1256 .eint_gpio_init = exynos_eint_gpio_init, 1257 }, { 1258 /* pin-controller instance 3 FSYS0 data */ 1259 .pin_banks = exynos8895_pin_banks3, 1260 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks3), 1261 .eint_gpio_init = exynos_eint_gpio_init, 1262 .suspend = exynos_pinctrl_suspend, 1263 .resume = exynos_pinctrl_resume, 1264 }, { 1265 /* pin-controller instance 4 FSYS1 data */ 1266 .pin_banks = exynos8895_pin_banks4, 1267 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks4), 1268 .eint_gpio_init = exynos_eint_gpio_init, 1269 .suspend = exynos_pinctrl_suspend, 1270 .resume = exynos_pinctrl_resume, 1271 }, { 1272 /* pin-controller instance 5 BUSC data */ 1273 .pin_banks = exynos8895_pin_banks5, 1274 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks5), 1275 .eint_gpio_init = exynos_eint_gpio_init, 1276 .suspend = exynos_pinctrl_suspend, 1277 .resume = exynos_pinctrl_resume, 1278 }, { 1279 /* pin-controller instance 6 PERIC0 data */ 1280 .pin_banks = exynos8895_pin_banks6, 1281 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks6), 1282 .eint_gpio_init = exynos_eint_gpio_init, 1283 .suspend = exynos_pinctrl_suspend, 1284 .resume = exynos_pinctrl_resume, 1285 }, { 1286 /* pin-controller instance 7 PERIC1 data */ 1287 .pin_banks = exynos8895_pin_banks7, 1288 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks7), 1289 .eint_gpio_init = exynos_eint_gpio_init, 1290 .suspend = exynos_pinctrl_suspend, 1291 .resume = exynos_pinctrl_resume, 1292 }, 1293 }; 1294 1295 const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = { 1296 .ctrl = exynos8895_pin_ctrl, 1297 .num_ctrl = ARRAY_SIZE(exynos8895_pin_ctrl), 1298 }; 1299 1300 /* 1301 * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three 1302 * gpio/pin-mux/pinconfig controllers. 1303 */ 1304 1305 /* pin banks of FSD pin-controller 0 (FSYS) */ 1306 static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = { 1307 EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00), 1308 EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04), 1309 EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08), 1310 EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c), 1311 EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10), 1312 }; 1313 1314 /* pin banks of FSD pin-controller 1 (PERIC) */ 1315 static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = { 1316 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00), 1317 EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04), 1318 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08), 1319 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c), 1320 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10), 1321 EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14), 1322 EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18), 1323 EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c), 1324 EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20), 1325 EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24), 1326 EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28), 1327 EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), 1328 EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30), 1329 EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34), 1330 EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38), 1331 EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c), 1332 EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 1333 EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44), 1334 EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48), 1335 EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c), 1336 EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50), 1337 }; 1338 1339 /* pin banks of FSD pin-controller 2 (PMU) */ 1340 static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = { 1341 EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"), 1342 }; 1343 1344 static const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = { 1345 { 1346 /* pin-controller instance 0 FSYS0 data */ 1347 .pin_banks = fsd_pin_banks0, 1348 .nr_banks = ARRAY_SIZE(fsd_pin_banks0), 1349 .eint_gpio_init = exynos_eint_gpio_init, 1350 .suspend = exynos_pinctrl_suspend, 1351 .resume = exynos_pinctrl_resume, 1352 }, { 1353 /* pin-controller instance 1 PERIC data */ 1354 .pin_banks = fsd_pin_banks1, 1355 .nr_banks = ARRAY_SIZE(fsd_pin_banks1), 1356 .eint_gpio_init = exynos_eint_gpio_init, 1357 .suspend = exynos_pinctrl_suspend, 1358 .resume = exynos_pinctrl_resume, 1359 }, { 1360 /* pin-controller instance 2 PMU data */ 1361 .pin_banks = fsd_pin_banks2, 1362 .nr_banks = ARRAY_SIZE(fsd_pin_banks2), 1363 }, 1364 }; 1365 1366 const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { 1367 .ctrl = fsd_pin_ctrl, 1368 .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), 1369 }; 1370 1371 /* pin banks of gs101 pin-controller (ALIVE) */ 1372 static const struct samsung_pin_bank_data gs101_pin_alive[] = { 1373 EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00), 1374 EXYNOS850_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04), 1375 EXYNOS850_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08), 1376 EXYNOS850_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c), 1377 EXYNOS850_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10), 1378 EXYNOS850_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14), 1379 EXYNOS850_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18), 1380 EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c), 1381 }; 1382 1383 /* pin banks of gs101 pin-controller (FAR_ALIVE) */ 1384 static const struct samsung_pin_bank_data gs101_pin_far_alive[] = { 1385 EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00), 1386 EXYNOS850_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04), 1387 EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08), 1388 EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c), 1389 }; 1390 1391 /* pin banks of gs101 pin-controller (GSACORE) */ 1392 static const struct samsung_pin_bank_data gs101_pin_gsacore[] = { 1393 EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00), 1394 EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04), 1395 EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08), 1396 }; 1397 1398 /* pin banks of gs101 pin-controller (GSACTRL) */ 1399 static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = { 1400 EXYNOS850_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00), 1401 }; 1402 1403 /* pin banks of gs101 pin-controller (PERIC0) */ 1404 static const struct samsung_pin_bank_data gs101_pin_peric0[] = { 1405 EXYNOS850_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00), 1406 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04), 1407 EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08), 1408 EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c), 1409 EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10), 1410 EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14), 1411 EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18), 1412 EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c), 1413 EXYNOS850_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20), 1414 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24), 1415 EXYNOS850_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28), 1416 EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c), 1417 EXYNOS850_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30), 1418 EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34), 1419 EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38), 1420 EXYNOS850_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c), 1421 EXYNOS850_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40), 1422 EXYNOS850_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44), 1423 EXYNOS850_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48), 1424 EXYNOS850_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c), 1425 }; 1426 1427 /* pin banks of gs101 pin-controller (PERIC1) */ 1428 static const struct samsung_pin_bank_data gs101_pin_peric1[] = { 1429 EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00), 1430 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04), 1431 EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08), 1432 EXYNOS850_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c), 1433 EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10), 1434 EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14), 1435 EXYNOS850_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18), 1436 EXYNOS850_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c), 1437 }; 1438 1439 /* pin banks of gs101 pin-controller (HSI1) */ 1440 static const struct samsung_pin_bank_data gs101_pin_hsi1[] = { 1441 EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00), 1442 EXYNOS850_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04), 1443 }; 1444 1445 /* pin banks of gs101 pin-controller (HSI2) */ 1446 static const struct samsung_pin_bank_data gs101_pin_hsi2[] = { 1447 EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00), 1448 EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04), 1449 EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08), 1450 }; 1451 1452 static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { 1453 { 1454 /* pin banks of gs101 pin-controller (ALIVE) */ 1455 .pin_banks = gs101_pin_alive, 1456 .nr_banks = ARRAY_SIZE(gs101_pin_alive), 1457 .eint_wkup_init = exynos_eint_wkup_init, 1458 .suspend = exynos_pinctrl_suspend, 1459 .resume = exynos_pinctrl_resume, 1460 }, { 1461 /* pin banks of gs101 pin-controller (FAR_ALIVE) */ 1462 .pin_banks = gs101_pin_far_alive, 1463 .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), 1464 .eint_wkup_init = exynos_eint_wkup_init, 1465 .suspend = exynos_pinctrl_suspend, 1466 .resume = exynos_pinctrl_resume, 1467 }, { 1468 /* pin banks of gs101 pin-controller (GSACORE) */ 1469 .pin_banks = gs101_pin_gsacore, 1470 .nr_banks = ARRAY_SIZE(gs101_pin_gsacore), 1471 }, { 1472 /* pin banks of gs101 pin-controller (GSACTRL) */ 1473 .pin_banks = gs101_pin_gsactrl, 1474 .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl), 1475 }, { 1476 /* pin banks of gs101 pin-controller (PERIC0) */ 1477 .pin_banks = gs101_pin_peric0, 1478 .nr_banks = ARRAY_SIZE(gs101_pin_peric0), 1479 .eint_gpio_init = exynos_eint_gpio_init, 1480 .suspend = exynos_pinctrl_suspend, 1481 .resume = exynos_pinctrl_resume, 1482 }, { 1483 /* pin banks of gs101 pin-controller (PERIC1) */ 1484 .pin_banks = gs101_pin_peric1, 1485 .nr_banks = ARRAY_SIZE(gs101_pin_peric1), 1486 .eint_gpio_init = exynos_eint_gpio_init, 1487 .suspend = exynos_pinctrl_suspend, 1488 .resume = exynos_pinctrl_resume, 1489 }, { 1490 /* pin banks of gs101 pin-controller (HSI1) */ 1491 .pin_banks = gs101_pin_hsi1, 1492 .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), 1493 .eint_gpio_init = exynos_eint_gpio_init, 1494 .suspend = exynos_pinctrl_suspend, 1495 .resume = exynos_pinctrl_resume, 1496 }, { 1497 /* pin banks of gs101 pin-controller (HSI2) */ 1498 .pin_banks = gs101_pin_hsi2, 1499 .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), 1500 .eint_gpio_init = exynos_eint_gpio_init, 1501 .suspend = exynos_pinctrl_suspend, 1502 .resume = exynos_pinctrl_resume, 1503 }, 1504 }; 1505 1506 const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = { 1507 .ctrl = gs101_pin_ctrl, 1508 .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl), 1509 }; 1510