1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef OTX2_COMMON_H 9 #define OTX2_COMMON_H 10 11 #include <linux/ethtool.h> 12 #include <linux/pci.h> 13 #include <linux/iommu.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/ptp_clock_kernel.h> 16 #include <linux/timecounter.h> 17 #include <linux/soc/marvell/silicons.h> 18 #include <linux/soc/marvell/octeontx2/asm.h> 19 #include <net/macsec.h> 20 #include <net/pkt_cls.h> 21 #include <net/devlink.h> 22 #include <linux/time64.h> 23 #include <linux/dim.h> 24 #include <uapi/linux/if_macsec.h> 25 #include <net/page_pool/helpers.h> 26 27 #include <mbox.h> 28 #include <npc.h> 29 #include "otx2_reg.h" 30 #include "otx2_txrx.h" 31 #include "otx2_devlink.h" 32 #include <rvu.h> 33 #include <rvu_trace.h> 34 #include "qos.h" 35 #include "rep.h" 36 #include "cn10k_ipsec.h" 37 #include "cn20k.h" 38 39 /* IPv4 flag more fragment bit */ 40 #define IPV4_FLAG_MORE 0x20 41 42 /* PCI device IDs */ 43 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 44 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 45 46 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 47 #define PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF 0xB900 48 #define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF 0xBD00 49 50 #define PCI_DEVID_OCTEONTX2_SDP_REP 0xA0F7 51 52 /* PCI BAR nos */ 53 #define PCI_CFG_REG_BAR_NUM 2 54 #define PCI_MBOX_BAR_NUM 4 55 56 #define NAME_SIZE 32 57 58 #ifdef CONFIG_DCB 59 /* Max priority supported for PFC */ 60 #define NIX_PF_PFC_PRIO_MAX 8 61 #endif 62 63 /* Number of segments per SG structure */ 64 #define MAX_SEGS_PER_SG 3 65 66 irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq); 67 irqreturn_t cn20k_pfaf_mbox_intr_handler(int irq, void *pf_irq); 68 irqreturn_t cn20k_vfaf_mbox_intr_handler(int irq, void *vf_irq); 69 irqreturn_t cn20k_pfvf_mbox_intr_handler(int irq, void *pf_irq); 70 irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq); 71 72 enum arua_mapped_qtypes { 73 AURA_NIX_RQ, 74 AURA_NIX_SQ, 75 }; 76 77 /* NIX LF interrupts range*/ 78 #define NIX_LF_QINT_VEC_START 0x00 79 #define NIX_LF_CINT_VEC_START 0x40 80 #define NIX_LF_GINT_VEC 0x80 81 #define NIX_LF_ERR_VEC 0x81 82 #define NIX_LF_POISON_VEC 0x82 83 84 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 85 #define SEND_CQ_SKID 2000 86 87 #define OTX2_GET_RX_STATS(reg) \ 88 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 89 #define OTX2_GET_TX_STATS(reg) \ 90 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 91 92 struct otx2_lmt_info { 93 u64 lmt_addr; 94 u16 lmt_id; 95 }; 96 97 struct otx2_rss_info { 98 u8 enable; 99 u32 flowkey_cfg; 100 u16 rss_size; 101 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 102 u8 key[RSS_HASH_KEY_SIZE]; 103 u32 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 104 }; 105 106 /* NIX (or NPC) RX errors */ 107 enum otx2_errlvl { 108 NPC_ERRLVL_RE, 109 NPC_ERRLVL_LID_LA, 110 NPC_ERRLVL_LID_LB, 111 NPC_ERRLVL_LID_LC, 112 NPC_ERRLVL_LID_LD, 113 NPC_ERRLVL_LID_LE, 114 NPC_ERRLVL_LID_LF, 115 NPC_ERRLVL_LID_LG, 116 NPC_ERRLVL_LID_LH, 117 NPC_ERRLVL_NIX = 0x0F, 118 }; 119 120 enum otx2_errcodes_re { 121 /* NPC_ERRLVL_RE errcodes */ 122 ERRCODE_FCS = 0x7, 123 ERRCODE_FCS_RCV = 0x8, 124 ERRCODE_UNDERSIZE = 0x10, 125 ERRCODE_OVERSIZE = 0x11, 126 ERRCODE_OL2_LEN_MISMATCH = 0x12, 127 /* NPC_ERRLVL_NIX errcodes */ 128 ERRCODE_OL3_LEN = 0x10, 129 ERRCODE_OL4_LEN = 0x11, 130 ERRCODE_OL4_CSUM = 0x12, 131 ERRCODE_IL3_LEN = 0x20, 132 ERRCODE_IL4_LEN = 0x21, 133 ERRCODE_IL4_CSUM = 0x22, 134 }; 135 136 enum otx2_xdp_action { 137 OTX2_XDP_TX = BIT(0), 138 OTX2_XDP_REDIRECT = BIT(1), 139 OTX2_AF_XDP_FRAME = BIT(2), 140 }; 141 142 struct otx2_dev_stats { 143 u64 rx_bytes; 144 u64 rx_frames; 145 u64 rx_ucast_frames; 146 u64 rx_bcast_frames; 147 u64 rx_mcast_frames; 148 u64 rx_drops; 149 150 u64 tx_bytes; 151 u64 tx_frames; 152 u64 tx_ucast_frames; 153 u64 tx_bcast_frames; 154 u64 tx_mcast_frames; 155 u64 tx_drops; 156 atomic_long_t tx_discards; 157 }; 158 159 /* Driver counted stats */ 160 struct otx2_drv_stats { 161 atomic_t rx_fcs_errs; 162 atomic_t rx_oversize_errs; 163 atomic_t rx_undersize_errs; 164 atomic_t rx_csum_errs; 165 atomic_t rx_len_errs; 166 atomic_t rx_other_errs; 167 }; 168 169 struct mbox { 170 struct otx2_mbox mbox; 171 struct work_struct mbox_wrk; 172 struct otx2_mbox mbox_up; 173 struct work_struct mbox_up_wrk; 174 struct otx2_nic *pfvf; 175 void *bbuf_base; /* Bounce buffer for mbox memory */ 176 struct mutex lock; /* serialize mailbox access */ 177 int num_msgs; /* mbox number of messages */ 178 int up_num_msgs; /* mbox_up number of messages */ 179 }; 180 181 /* Egress rate limiting definitions */ 182 #define MAX_BURST_EXPONENT 0x0FULL 183 #define MAX_BURST_MANTISSA 0xFFULL 184 #define MAX_BURST_SIZE 130816ULL 185 #define MAX_RATE_DIVIDER_EXPONENT 12ULL 186 #define MAX_RATE_EXPONENT 0x0FULL 187 #define MAX_RATE_MANTISSA 0xFFULL 188 189 /* Bitfields in NIX_TLX_PIR register */ 190 #define TLX_RATE_MANTISSA GENMASK_ULL(8, 1) 191 #define TLX_RATE_EXPONENT GENMASK_ULL(12, 9) 192 #define TLX_RATE_DIVIDER_EXPONENT GENMASK_ULL(16, 13) 193 #define TLX_BURST_MANTISSA GENMASK_ULL(36, 29) 194 #define TLX_BURST_EXPONENT GENMASK_ULL(40, 37) 195 196 struct otx2_hw { 197 struct pci_dev *pdev; 198 struct otx2_rss_info rss_info; 199 u16 rx_queues; 200 u16 tx_queues; 201 u16 xdp_queues; 202 u16 tc_tx_queues; 203 u16 non_qos_queues; /* tx queues plus xdp queues */ 204 u16 max_queues; 205 u16 pool_cnt; 206 u16 rqpool_cnt; 207 u16 sqpool_cnt; 208 209 #define OTX2_DEFAULT_RBUF_LEN 2048 210 u16 rbuf_len; 211 u32 xqe_size; 212 213 /* NPA */ 214 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 215 u32 stack_pg_bytes; /* Size of stack page */ 216 u16 sqb_size; 217 218 /* NIX */ 219 u8 txschq_link_cfg_lvl; 220 u8 txschq_cnt[NIX_TXSCH_LVL_CNT]; 221 u8 txschq_aggr_lvl_rr_prio; 222 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 223 u16 matchall_ipolicer; 224 u32 dwrr_mtu; 225 u32 max_mtu; 226 u8 smq_link_type; 227 228 /* HW settings, coalescing etc */ 229 u16 rx_chan_base; 230 u16 tx_chan_base; 231 u8 rx_chan_cnt; 232 u8 tx_chan_cnt; 233 u16 cq_qcount_wait; 234 u16 cq_ecount_wait; 235 u16 rq_skid; 236 u8 cq_time_wait; 237 238 /* Segmentation */ 239 u8 lso_tsov4_idx; 240 u8 lso_tsov6_idx; 241 u8 lso_udpv4_idx; 242 u8 lso_udpv6_idx; 243 244 /* RSS */ 245 u8 flowkey_alg_idx; 246 247 /* MSI-X */ 248 u8 cint_cnt; /* CQ interrupt count */ 249 u16 npa_msixoff; /* Offset of NPA vectors */ 250 u16 nix_msixoff; /* Offset of NIX vectors */ 251 char *irq_name; 252 cpumask_var_t *affinity_mask; 253 struct pf_irq_data *pfvf_irq_devid[4]; 254 255 /* Stats */ 256 struct otx2_dev_stats dev_stats; 257 struct otx2_drv_stats drv_stats; 258 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 259 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 260 u64 cgx_fec_corr_blks; 261 u64 cgx_fec_uncorr_blks; 262 u8 cgx_links; /* No. of CGX links present in HW */ 263 u8 lbk_links; /* No. of LBK links present in HW */ 264 u8 tx_link; /* Transmit channel link number */ 265 #define HW_TSO 0 266 #define CN10K_MBOX 1 267 #define CN10K_LMTST 2 268 #define CN10K_RPM 3 269 #define CN10K_PTP_ONESTEP 4 270 #define CN10K_HW_MACSEC 5 271 #define QOS_CIR_PIR_SUPPORT 6 272 unsigned long cap_flag; 273 274 #define LMT_LINE_SIZE 128 275 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */ 276 u64 *lmt_base; 277 struct otx2_lmt_info __percpu *lmt_info; 278 }; 279 280 enum vfperm { 281 OTX2_RESET_VF_PERM, 282 OTX2_TRUSTED_VF, 283 }; 284 285 struct otx2_vf_config { 286 struct otx2_nic *pf; 287 struct delayed_work link_event_work; 288 bool intf_down; /* interface was either configured or not */ 289 u8 mac[ETH_ALEN]; 290 u16 vlan; 291 int tx_vtag_idx; 292 bool trusted; 293 }; 294 295 struct flr_work { 296 struct work_struct work; 297 struct otx2_nic *pf; 298 }; 299 300 struct refill_work { 301 struct delayed_work pool_refill_work; 302 struct otx2_nic *pf; 303 struct napi_struct *napi; 304 }; 305 306 /* PTPv2 originTimestamp structure */ 307 struct ptpv2_tstamp { 308 __be16 seconds_msb; /* 16 bits + */ 309 __be32 seconds_lsb; /* 32 bits = 48 bits*/ 310 __be32 nanoseconds; 311 } __packed; 312 313 struct otx2_ptp { 314 struct ptp_clock_info ptp_info; 315 struct ptp_clock *ptp_clock; 316 struct otx2_nic *nic; 317 318 struct cyclecounter cycle_counter; 319 struct timecounter time_counter; 320 321 struct delayed_work extts_work; 322 u64 last_extts; 323 u64 thresh; 324 325 struct ptp_pin_desc extts_config; 326 u64 (*convert_rx_ptp_tstmp)(u64 timestamp); 327 u64 (*convert_tx_ptp_tstmp)(u64 timestamp); 328 u64 (*ptp_tstamp2nsec)(const struct timecounter *time_counter, u64 timestamp); 329 struct delayed_work synctstamp_work; 330 u64 tstamp; 331 u32 base_ns; 332 }; 333 334 #define OTX2_HW_TIMESTAMP_LEN 8 335 336 struct otx2_mac_table { 337 u8 addr[ETH_ALEN]; 338 u16 mcam_entry; 339 bool inuse; 340 }; 341 342 struct otx2_flow_config { 343 u16 *flow_ent; 344 u16 *def_ent; 345 u16 nr_flows; 346 #define OTX2_DEFAULT_FLOWCOUNT 16 347 #define OTX2_DEFAULT_UNICAST_FLOWS 4 348 #define OTX2_MAX_VLAN_FLOWS 1 349 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT 350 u16 unicast_offset; 351 u16 rx_vlan_offset; 352 u16 vf_vlan_offset; 353 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ 354 #define OTX2_VF_VLAN_RX_INDEX 0 355 #define OTX2_VF_VLAN_TX_INDEX 1 356 u32 *bmap_to_dmacindex; 357 unsigned long *dmacflt_bmap; 358 struct list_head flow_list; 359 u32 dmacflt_max_flows; 360 u16 max_flows; 361 refcount_t mark_flows; 362 struct list_head flow_list_tc; 363 u8 ucast_flt_cnt; 364 bool ntuple; 365 u16 ntuple_cnt; 366 }; 367 368 struct otx2_tc_flow_stats { 369 u64 bytes; 370 u64 pkts; 371 u64 used; 372 }; 373 374 struct otx2_tc_flow { 375 struct list_head list; 376 unsigned long cookie; 377 struct rcu_head rcu; 378 struct otx2_tc_flow_stats stats; 379 spinlock_t lock; /* lock for stats */ 380 u16 rq; 381 u16 entry; 382 u16 leaf_profile; 383 bool is_act_police; 384 u32 prio; 385 struct npc_install_flow_req req; 386 u64 rate; 387 u32 burst; 388 u32 mcast_grp_idx; 389 bool is_pps; 390 u8 kw_type; /* X2/X4 */ 391 }; 392 393 struct dev_hw_ops { 394 int (*sq_aq_init)(void *dev, u16 qidx, u8 chan_offset, 395 u16 sqb_aura); 396 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 397 int size, int qidx); 398 int (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 399 void (*aura_freeptr)(void *dev, int aura, u64 buf); 400 irqreturn_t (*pfaf_mbox_intr_handler)(int irq, void *pf_irq); 401 irqreturn_t (*vfaf_mbox_intr_handler)(int irq, void *pf_irq); 402 irqreturn_t (*pfvf_mbox_intr_handler)(int irq, void *pf_irq); 403 int (*aura_aq_init)(struct otx2_nic *pfvf, int aura_id, 404 int pool_id, int numptrs); 405 int (*pool_aq_init)(struct otx2_nic *pfvf, u16 pool_id, 406 int stack_pages, int numptrs, int buf_size, 407 int type); 408 }; 409 410 #define CN10K_MCS_SA_PER_SC 4 411 412 /* Stats which need to be accumulated in software because 413 * of shared counters in hardware. 414 */ 415 struct cn10k_txsc_stats { 416 u64 InPktsUntagged; 417 u64 InPktsNoTag; 418 u64 InPktsBadTag; 419 u64 InPktsUnknownSCI; 420 u64 InPktsNoSCI; 421 u64 InPktsOverrun; 422 }; 423 424 struct cn10k_rxsc_stats { 425 u64 InOctetsValidated; 426 u64 InOctetsDecrypted; 427 u64 InPktsUnchecked; 428 u64 InPktsDelayed; 429 u64 InPktsOK; 430 u64 InPktsInvalid; 431 u64 InPktsLate; 432 u64 InPktsNotValid; 433 u64 InPktsNotUsingSA; 434 u64 InPktsUnusedSA; 435 }; 436 437 struct cn10k_mcs_txsc { 438 struct macsec_secy *sw_secy; 439 struct cn10k_txsc_stats stats; 440 struct list_head entry; 441 enum macsec_validation_type last_validate_frames; 442 bool last_replay_protect; 443 u16 hw_secy_id_tx; 444 u16 hw_secy_id_rx; 445 u16 hw_flow_id; 446 u16 hw_sc_id; 447 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 448 u8 sa_bmap; 449 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 450 u8 encoding_sa; 451 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 452 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 453 bool vlan_dev; /* macsec running on VLAN ? */ 454 }; 455 456 struct cn10k_mcs_rxsc { 457 struct macsec_secy *sw_secy; 458 struct macsec_rx_sc *sw_rxsc; 459 struct cn10k_rxsc_stats stats; 460 struct list_head entry; 461 u16 hw_flow_id; 462 u16 hw_sc_id; 463 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 464 u8 sa_bmap; 465 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 466 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 467 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 468 }; 469 470 struct cn10k_mcs_cfg { 471 struct list_head txsc_list; 472 struct list_head rxsc_list; 473 }; 474 475 struct pf_irq_data { 476 u64 intr_status; 477 void (*pf_queue_work_hdlr)(struct mbox *mb, struct workqueue_struct *mw, 478 int first, int mdevs, u64 intr); 479 struct otx2_nic *pf; 480 int vec_num; 481 int start; 482 int mdevs; 483 }; 484 485 struct otx2_nic { 486 void __iomem *reg_base; 487 struct net_device *netdev; 488 struct dev_hw_ops *hw_ops; 489 void *iommu_domain; 490 u16 tx_max_pktlen; 491 u16 rbsize; /* Receive buffer size */ 492 493 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 494 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 495 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 496 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 497 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 498 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 499 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 500 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 501 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 502 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 503 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 504 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 505 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 506 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) 507 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) 508 #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15) 509 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) 510 #define OTX2_FLAG_TC_MARK_ENABLED BIT_ULL(17) 511 #define OTX2_FLAG_REP_MODE_ENABLED BIT_ULL(18) 512 #define OTX2_FLAG_PORT_UP BIT_ULL(19) 513 #define OTX2_FLAG_IPSEC_OFFLOAD_ENABLED BIT_ULL(20) 514 u64 flags; 515 u64 *cq_op_addr; 516 517 struct bpf_prog *xdp_prog; 518 struct otx2_qset qset; 519 struct otx2_hw hw; 520 struct pci_dev *pdev; 521 struct device *dev; 522 523 /* Mbox */ 524 struct mbox mbox; 525 struct mbox *mbox_pfvf; 526 struct workqueue_struct *mbox_wq; 527 struct workqueue_struct *mbox_pfvf_wq; 528 struct qmem *pfvf_mbox_addr; 529 530 u8 total_vfs; 531 u16 pcifunc; /* RVU PF_FUNC */ 532 u16 bpid[NIX_MAX_BPID_CHAN]; 533 struct otx2_vf_config *vf_configs; 534 struct cgx_link_user_info linfo; 535 536 /* NPC MCAM */ 537 struct otx2_flow_config *flow_cfg; 538 struct otx2_mac_table *mac_table; 539 540 u64 reset_count; 541 struct work_struct reset_task; 542 struct workqueue_struct *flr_wq; 543 struct flr_work *flr_wrk; 544 struct refill_work *refill_wrk; 545 struct workqueue_struct *otx2_wq; 546 struct work_struct rx_mode_work; 547 548 /* Ethtool stuff */ 549 u32 msg_enable; 550 551 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 552 int nix_blkaddr; 553 /* LMTST Lines info */ 554 struct qmem *dync_lmt; 555 u16 tot_lmt_lines; 556 u16 npa_lmt_lines; 557 u32 nix_lmt_size; 558 559 struct otx2_ptp *ptp; 560 struct kernel_hwtstamp_config tstamp; 561 562 unsigned long rq_bmap; 563 564 /* Devlink */ 565 struct otx2_devlink *dl; 566 /* PFC */ 567 u8 pfc_en; 568 #ifdef CONFIG_DCB 569 u8 *queue_to_pfc_map; 570 u16 pfc_schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 571 bool pfc_alloc_status[NIX_PF_PFC_PRIO_MAX]; 572 #endif 573 /* qos */ 574 struct otx2_qos qos; 575 576 /* napi event count. It is needed for adaptive irq coalescing. */ 577 u32 napi_events; 578 579 #if IS_ENABLED(CONFIG_MACSEC) 580 struct cn10k_mcs_cfg *macsec_cfg; 581 #endif 582 583 #if IS_ENABLED(CONFIG_RVU_ESWITCH) 584 struct rep_dev **reps; 585 int rep_cnt; 586 u16 rep_pf_map[RVU_MAX_REP]; 587 u16 esw_mode; 588 #endif 589 590 /* Inline ipsec */ 591 struct cn10k_ipsec ipsec; 592 /* af_xdp zero-copy */ 593 unsigned long *af_xdp_zc_qidx; 594 }; 595 596 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 597 { 598 return (pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF) || 599 (pdev->device == PCI_DEVID_RVU_REP); 600 } 601 602 static inline bool is_96xx_A0(struct pci_dev *pdev) 603 { 604 return (pdev->revision == 0x00) && 605 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 606 } 607 608 static inline bool is_96xx_B0(struct pci_dev *pdev) 609 { 610 return (pdev->revision == 0x01) && 611 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 612 } 613 614 static inline bool is_otx2_sdp_rep(struct pci_dev *pdev) 615 { 616 return pdev->device == PCI_DEVID_OCTEONTX2_SDP_REP; 617 } 618 619 /* REVID for PCIe devices. 620 * Bits 0..1: minor pass, bit 3..2: major pass 621 * bits 7..4: midr id 622 */ 623 #define PCI_REVISION_ID_96XX 0x00 624 #define PCI_REVISION_ID_95XX 0x10 625 #define PCI_REVISION_ID_95XXN 0x20 626 #define PCI_REVISION_ID_98XX 0x30 627 #define PCI_REVISION_ID_95XXMM 0x40 628 #define PCI_REVISION_ID_95XXO 0xE0 629 630 static inline bool is_dev_otx2(struct pci_dev *pdev) 631 { 632 u8 midr = pdev->revision & 0xF0; 633 634 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 635 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 636 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 637 } 638 639 static inline bool is_dev_cn10kb(struct pci_dev *pdev) 640 { 641 return pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF; 642 } 643 644 static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev) 645 { 646 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A_RVU_PFVF && 647 (pdev->revision & 0xFF) == 0x54) 648 return true; 649 650 return false; 651 } 652 653 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 654 { 655 struct otx2_hw *hw = &pfvf->hw; 656 657 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 658 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 659 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 660 661 __set_bit(HW_TSO, &hw->cap_flag); 662 663 if (is_96xx_A0(pfvf->pdev)) { 664 __clear_bit(HW_TSO, &hw->cap_flag); 665 666 /* Time based irq coalescing is not supported */ 667 pfvf->hw.cq_qcount_wait = 0x0; 668 669 /* Due to HW issue previous silicons required minimum 670 * 600 unused CQE to avoid CQ overflow. 671 */ 672 pfvf->hw.rq_skid = 600; 673 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 674 } 675 if (is_96xx_B0(pfvf->pdev)) 676 __clear_bit(HW_TSO, &hw->cap_flag); 677 678 if (!is_dev_otx2(pfvf->pdev)) { 679 __set_bit(CN10K_MBOX, &hw->cap_flag); 680 __set_bit(CN10K_LMTST, &hw->cap_flag); 681 __set_bit(CN10K_RPM, &hw->cap_flag); 682 __set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag); 683 __set_bit(QOS_CIR_PIR_SUPPORT, &hw->cap_flag); 684 } 685 } 686 687 /* Register read/write APIs */ 688 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 689 { 690 u64 blkaddr; 691 692 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 693 case BLKTYPE_NIX: 694 blkaddr = nic->nix_blkaddr; 695 break; 696 case BLKTYPE_NPA: 697 blkaddr = BLKADDR_NPA; 698 break; 699 case BLKTYPE_CPT: 700 blkaddr = BLKADDR_CPT0; 701 break; 702 default: 703 blkaddr = BLKADDR_RVUM; 704 break; 705 } 706 707 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 708 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 709 710 return nic->reg_base + offset; 711 } 712 713 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 714 { 715 void __iomem *addr = otx2_get_regaddr(nic, offset); 716 717 writeq(val, addr); 718 } 719 720 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 721 { 722 void __iomem *addr = otx2_get_regaddr(nic, offset); 723 724 return readq(addr); 725 } 726 727 /* Mbox bounce buffer APIs */ 728 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 729 { 730 struct otx2_mbox *otx2_mbox; 731 struct otx2_mbox_dev *mdev; 732 733 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 734 if (!mbox->bbuf_base) 735 return -ENOMEM; 736 737 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 738 * prepare all mbox messages in bounce buffer instead of directly 739 * in hw mbox memory. 740 */ 741 otx2_mbox = &mbox->mbox; 742 mdev = &otx2_mbox->dev[0]; 743 mdev->mbase = mbox->bbuf_base; 744 745 otx2_mbox = &mbox->mbox_up; 746 mdev = &otx2_mbox->dev[0]; 747 mdev->mbase = mbox->bbuf_base; 748 return 0; 749 } 750 751 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 752 { 753 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 754 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 755 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 756 struct mbox_hdr *hdr; 757 u64 msg_size; 758 759 if (mdev->mbase == hw_mbase) 760 return; 761 762 hdr = hw_mbase + mbox->rx_start; 763 msg_size = hdr->msg_size; 764 765 if (msg_size > mbox->rx_size - msgs_offset) 766 msg_size = mbox->rx_size - msgs_offset; 767 768 /* Copy mbox messages from mbox memory to bounce buffer */ 769 memcpy(mdev->mbase + mbox->rx_start, 770 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 771 } 772 773 /* With the absence of API for 128-bit IO memory access for arm64, 774 * implement required operations at place. 775 */ 776 #if defined(CONFIG_ARM64) 777 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 778 { 779 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 780 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 781 } 782 783 static inline u64 otx2_atomic64_add(u64 incr, void __iomem *addr) 784 { 785 u64 __iomem *ptr = addr; 786 u64 result; 787 788 __asm__ volatile(".arch_extension lse\n" 789 "ldadd %x[i], %x[r], [%[b]]" 790 : [r]"=r"(result), "+m"(*ptr) 791 : [i]"r"(incr), [b]"r"(ptr) 792 : "memory"); 793 return result; 794 } 795 796 #else 797 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 798 799 static inline u64 otx2_atomic64_add(u64 incr, void __iomem *addr) 800 { 801 return 0; 802 } 803 #endif 804 805 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 806 u64 *ptrs, u64 num_ptrs) 807 { 808 struct otx2_lmt_info *lmt_info; 809 u64 size = 0, count_eot = 0; 810 u64 tar_addr, val = 0; 811 812 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id()); 813 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 814 /* LMTID is same as AURA Id */ 815 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63); 816 /* Meaning of count_eot 817 * CN10K: count_eot = 0 if the number of pointers to free is even, 818 * count_eot = 1 if the number of pointers to free is odd. 819 * 820 * CN20K: count_eot represents the least significant 2 bits of the 821 * total number of valid pointers to free. 822 * Example: if 7 pointers are freed (0b111), count_eot = 0b11. 823 */ 824 count_eot = (num_ptrs - 1) & 0x3ULL; 825 /* Set AURA ID to free pointer */ 826 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 827 /* Target address for LMTST flush tells HW how many 128bit 828 * words are valid from NPA_LF_AURA_BATCH_FREE0. 829 * 830 * tar_addr[6:4] is LMTST size-1 in units of 128b. 831 */ 832 if (num_ptrs > 2) { 833 size = (sizeof(u64) * num_ptrs) / 16; 834 if (!(count_eot & 1)) 835 size++; 836 tar_addr |= ((size - 1) & 0x7) << 4; 837 } 838 dma_wmb(); 839 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs); 840 /* Perform LMTST flush */ 841 cn10k_lmt_flush(val, tar_addr); 842 } 843 844 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 845 { 846 struct otx2_nic *pfvf = dev; 847 u64 ptrs[2]; 848 849 ptrs[1] = buf; 850 get_cpu(); 851 /* Free only one buffer at time during init and teardown */ 852 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2); 853 put_cpu(); 854 } 855 856 /* Alloc pointer from pool/aura */ 857 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 858 { 859 void __iomem *ptr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_ALLOCX(0)); 860 u64 incr = (u64)aura | BIT_ULL(63); 861 862 return otx2_atomic64_add(incr, ptr); 863 } 864 865 /* Free pointer to a pool/aura */ 866 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 867 { 868 struct otx2_nic *pfvf = dev; 869 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 870 871 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 872 } 873 874 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 875 { 876 if (type == AURA_NIX_SQ) 877 return pfvf->hw.rqpool_cnt + idx; 878 879 /* AURA_NIX_RQ */ 880 return idx; 881 } 882 883 /* Mbox APIs */ 884 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 885 { 886 int err; 887 888 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 889 return 0; 890 otx2_mbox_msg_send(&mbox->mbox, 0); 891 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 892 if (err) 893 return err; 894 895 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 896 } 897 898 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 899 { 900 int err; 901 902 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 903 return 0; 904 otx2_mbox_msg_send_up(&mbox->mbox_up, devid); 905 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 906 if (err) 907 return err; 908 909 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 910 } 911 912 /* Use this API to send mbox msgs in atomic context 913 * where sleeping is not allowed 914 */ 915 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 916 { 917 int err; 918 919 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 920 return 0; 921 otx2_mbox_msg_send(&mbox->mbox, 0); 922 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 923 if (err) 924 return err; 925 926 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 927 } 928 929 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 930 static struct _req_type __maybe_unused \ 931 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 932 { \ 933 struct _req_type *req; \ 934 u16 pcifunc = mbox->pfvf->pcifunc; \ 935 \ 936 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 937 &mbox->mbox, 0, sizeof(struct _req_type), \ 938 sizeof(struct _rsp_type)); \ 939 if (!req) \ 940 return NULL; \ 941 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 942 req->hdr.id = _id; \ 943 req->hdr.pcifunc = pcifunc; \ 944 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req), pcifunc); \ 945 return req; \ 946 } 947 948 MBOX_MESSAGES 949 #undef M 950 951 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 952 int \ 953 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 954 struct _req_type *req, \ 955 struct _rsp_type *rsp); \ 956 957 MBOX_UP_CGX_MESSAGES 958 MBOX_UP_MCS_MESSAGES 959 #undef M 960 961 /* Time to wait before watchdog kicks off */ 962 #define OTX2_TX_TIMEOUT (100 * HZ) 963 964 static inline bool is_otx2_vf(u16 pcifunc) 965 { 966 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 967 } 968 969 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 970 struct page *page, 971 size_t offset, size_t size, 972 enum dma_data_direction dir) 973 { 974 return dma_map_page_attrs(pfvf->dev, page, 975 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 976 } 977 978 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 979 dma_addr_t addr, size_t size, 980 enum dma_data_direction dir) 981 { 982 dma_unmap_page_attrs(pfvf->dev, addr, size, 983 dir, DMA_ATTR_SKIP_CPU_SYNC); 984 } 985 986 static inline u16 otx2_get_smq_idx(struct otx2_nic *pfvf, u16 qidx) 987 { 988 u16 smq; 989 int idx; 990 991 #ifdef CONFIG_DCB 992 if (qidx < NIX_PF_PFC_PRIO_MAX && pfvf->pfc_alloc_status[qidx]) 993 return pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][qidx]; 994 #endif 995 /* check if qidx falls under QOS queues */ 996 if (qidx >= pfvf->hw.non_qos_queues) { 997 smq = pfvf->qos.qid_to_sqmap[qidx - pfvf->hw.non_qos_queues]; 998 } else { 999 idx = qidx % pfvf->hw.txschq_cnt[NIX_TXSCH_LVL_SMQ]; 1000 smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][idx]; 1001 } 1002 1003 return smq; 1004 } 1005 1006 static inline u16 otx2_get_total_tx_queues(struct otx2_nic *pfvf) 1007 { 1008 return pfvf->hw.non_qos_queues + pfvf->hw.tc_tx_queues; 1009 } 1010 1011 static inline u64 otx2_convert_rate(u64 rate) 1012 { 1013 u64 converted_rate; 1014 1015 /* Convert bytes per second to Mbps */ 1016 converted_rate = rate * 8; 1017 converted_rate = max_t(u64, converted_rate / 1000000, 1); 1018 1019 return converted_rate; 1020 } 1021 1022 static inline int otx2_tc_flower_rule_cnt(struct otx2_nic *pfvf) 1023 { 1024 /* return here if MCAM entries not allocated */ 1025 if (!pfvf->flow_cfg) 1026 return 0; 1027 1028 return pfvf->flow_cfg->nr_flows; 1029 } 1030 1031 static inline u8 otx2_get_bpid_idx(struct otx2_nic *pfvf, int qidx) 1032 { 1033 #ifdef CONFIG_DCB 1034 if (pfvf->queue_to_pfc_map) 1035 return pfvf->queue_to_pfc_map[qidx]; 1036 #endif 1037 return 0; 1038 } 1039 1040 /* MSI-X APIs */ 1041 void otx2_free_cints(struct otx2_nic *pfvf, int n); 1042 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 1043 int otx2_set_mac_address(struct net_device *netdev, void *p); 1044 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 1045 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 1046 void otx2_get_mac_from_af(struct net_device *netdev); 1047 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 1048 int otx2_config_pause_frm(struct otx2_nic *pfvf); 1049 void otx2_setup_segmentation(struct otx2_nic *pfvf); 1050 int otx2_reset_mac_stats(struct otx2_nic *pfvf); 1051 1052 /* RVU block related APIs */ 1053 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 1054 int otx2_detach_resources(struct mbox *mbox); 1055 int otx2_config_npa(struct otx2_nic *pfvf); 1056 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 1057 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 1058 void otx2_aura_pool_free(struct otx2_nic *pfvf); 1059 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 1060 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 1061 int otx2_config_nix(struct otx2_nic *pfvf); 1062 int otx2_config_nix_queues(struct otx2_nic *pfvf); 1063 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool pfc_en); 1064 int otx2_txsch_alloc(struct otx2_nic *pfvf); 1065 void otx2_txschq_stop(struct otx2_nic *pfvf); 1066 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq); 1067 void otx2_free_pending_sqe(struct otx2_nic *pfvf); 1068 void otx2_sqb_flush(struct otx2_nic *pfvf); 1069 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 1070 dma_addr_t *dma, int qidx, int idx); 1071 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 1072 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 1073 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 1074 int otx2_nix_cpt_config_bp(struct otx2_nic *pfvf, bool enable); 1075 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx); 1076 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 1077 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura); 1078 int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); 1079 int cn10k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); 1080 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 1081 dma_addr_t *dma); 1082 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1083 int stack_pages, int numptrs, int buf_size, int type); 1084 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1085 int pool_id, int numptrs); 1086 int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf); 1087 void otx2_free_queue_mem(struct otx2_qset *qset); 1088 int otx2_alloc_queue_mem(struct otx2_nic *pf); 1089 int otx2_init_hw_resources(struct otx2_nic *pfvf); 1090 void otx2_free_hw_resources(struct otx2_nic *pf); 1091 int otx2_wq_init(struct otx2_nic *pf); 1092 int otx2_check_pf_usable(struct otx2_nic *pf); 1093 int otx2_pfaf_mbox_init(struct otx2_nic *pf); 1094 int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af); 1095 int otx2_realloc_msix_vectors(struct otx2_nic *pf); 1096 void otx2_pfaf_mbox_destroy(struct otx2_nic *pf); 1097 void otx2_disable_mbox_intr(struct otx2_nic *pf); 1098 void otx2_disable_napi(struct otx2_nic *pf); 1099 irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq); 1100 int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura); 1101 int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx); 1102 int otx2_set_hw_capabilities(struct otx2_nic *pfvf); 1103 int otx2_aura_aq_init(struct otx2_nic *pfvf, int aura_id, 1104 int pool_id, int numptrs); 1105 int otx2_pool_aq_init(struct otx2_nic *pfvf, u16 pool_id, 1106 int stack_pages, int numptrs, int buf_size, int type); 1107 1108 /* RSS configuration APIs*/ 1109 int otx2_rss_init(struct otx2_nic *pfvf); 1110 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 1111 void otx2_set_rss_key(struct otx2_nic *pfvf); 1112 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id, const u32 *ind_tbl); 1113 1114 /* Mbox handlers */ 1115 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1116 struct msix_offset_rsp *rsp); 1117 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1118 struct npa_lf_alloc_rsp *rsp); 1119 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1120 struct nix_lf_alloc_rsp *rsp); 1121 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1122 struct nix_txsch_alloc_rsp *rsp); 1123 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1124 struct cgx_stats_rsp *rsp); 1125 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1126 struct cgx_fec_stats_rsp *rsp); 1127 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 1128 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1129 struct nix_bp_cfg_rsp *rsp); 1130 1131 /* Device stats APIs */ 1132 void otx2_get_dev_stats(struct otx2_nic *pfvf); 1133 void otx2_get_stats64(struct net_device *netdev, 1134 struct rtnl_link_stats64 *stats); 1135 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 1136 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 1137 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 1138 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 1139 void otx2_set_ethtool_ops(struct net_device *netdev); 1140 void otx2vf_set_ethtool_ops(struct net_device *netdev); 1141 1142 int otx2_open(struct net_device *netdev); 1143 int otx2_stop(struct net_device *netdev); 1144 int otx2_set_real_num_queues(struct net_device *netdev, 1145 int tx_queues, int rx_queues); 1146 int otx2_config_hwtstamp_get(struct net_device *netdev, 1147 struct kernel_hwtstamp_config *config); 1148 int otx2_config_hwtstamp_set(struct net_device *netdev, 1149 struct kernel_hwtstamp_config *config, 1150 struct netlink_ext_ack *extack); 1151 1152 /* MCAM filter related APIs */ 1153 int otx2_mcam_flow_init(struct otx2_nic *pf); 1154 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf); 1155 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count); 1156 void otx2_mcam_flow_del(struct otx2_nic *pf); 1157 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 1158 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 1159 int otx2_get_flow(struct otx2_nic *pfvf, 1160 struct ethtool_rxnfc *nfc, u32 location); 1161 int otx2_get_all_flows(struct otx2_nic *pfvf, 1162 struct ethtool_rxnfc *nfc, u32 *rule_locs); 1163 int otx2_add_flow(struct otx2_nic *pfvf, 1164 struct ethtool_rxnfc *nfc); 1165 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 1166 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg); 1167 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 1168 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 1169 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 1170 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 1171 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 1172 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, struct xdp_frame *xdpf, 1173 u64 iova, int len, u16 qidx, u16 flags); 1174 void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, struct xdp_frame *xdpf, 1175 u64 dma_addr, int len, int *offset, u16 flags); 1176 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 1177 int otx2_handle_ntuple_tc_features(struct net_device *netdev, 1178 netdev_features_t features); 1179 int otx2_smq_flush(struct otx2_nic *pfvf, int smq); 1180 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1181 u64 iova, int size); 1182 int otx2_mcam_entry_init(struct otx2_nic *pfvf); 1183 1184 /* tc support */ 1185 int otx2_init_tc(struct otx2_nic *nic); 1186 void otx2_shutdown_tc(struct otx2_nic *nic); 1187 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 1188 void *type_data); 1189 void otx2_tc_apply_ingress_police_rules(struct otx2_nic *nic); 1190 1191 /* CGX/RPM DMAC filters support */ 1192 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf); 1193 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1194 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1195 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos); 1196 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf); 1197 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf); 1198 1199 #ifdef CONFIG_DCB 1200 /* DCB support*/ 1201 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable); 1202 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf); 1203 int otx2_dcbnl_set_ops(struct net_device *dev); 1204 /* PFC support */ 1205 int otx2_pfc_txschq_config(struct otx2_nic *pfvf); 1206 int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf); 1207 int otx2_pfc_txschq_update(struct otx2_nic *pfvf); 1208 int otx2_pfc_txschq_stop(struct otx2_nic *pfvf); 1209 #endif 1210 1211 #if IS_ENABLED(CONFIG_MACSEC) 1212 /* MACSEC offload support */ 1213 int cn10k_mcs_init(struct otx2_nic *pfvf); 1214 void cn10k_mcs_free(struct otx2_nic *pfvf); 1215 void cn10k_handle_mcs_event(struct otx2_nic *pfvf, struct mcs_intr_info *event); 1216 #else 1217 static inline int cn10k_mcs_init(struct otx2_nic *pfvf) { return 0; } 1218 static inline void cn10k_mcs_free(struct otx2_nic *pfvf) {} 1219 static inline void cn10k_handle_mcs_event(struct otx2_nic *pfvf, 1220 struct mcs_intr_info *event) 1221 {} 1222 #endif /* CONFIG_MACSEC */ 1223 1224 /* qos support */ 1225 static inline void otx2_qos_init(struct otx2_nic *pfvf, int qos_txqs) 1226 { 1227 struct otx2_hw *hw = &pfvf->hw; 1228 1229 hw->tc_tx_queues = qos_txqs; 1230 INIT_LIST_HEAD(&pfvf->qos.qos_tree); 1231 mutex_init(&pfvf->qos.qos_lock); 1232 } 1233 1234 static inline void otx2_shutdown_qos(struct otx2_nic *pfvf) 1235 { 1236 mutex_destroy(&pfvf->qos.qos_lock); 1237 } 1238 1239 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 1240 struct net_device *sb_dev); 1241 int otx2_get_txq_by_classid(struct otx2_nic *pfvf, u16 classid); 1242 void otx2_qos_config_txschq(struct otx2_nic *pfvf); 1243 void otx2_clean_qos_queues(struct otx2_nic *pfvf); 1244 int rvu_event_up_notify(struct otx2_nic *pf, struct rep_event *info); 1245 int otx2_setup_tc_cls_flower(struct otx2_nic *nic, 1246 struct flow_cls_offload *cls_flower); 1247 1248 static inline int mcam_entry_cmp(const void *a, const void *b) 1249 { 1250 return *(u16 *)a - *(u16 *)b; 1251 } 1252 1253 dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, 1254 struct sk_buff *skb, int seg, int *len); 1255 void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg); 1256 int otx2_read_free_sqe(struct otx2_nic *pfvf, u16 qidx); 1257 void otx2_queue_vf_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 1258 int first, int mdevs, u64 intr); 1259 int otx2_del_mcam_flow_entry(struct otx2_nic *nic, u16 entry, 1260 u16 *cntr_val); 1261 int otx2_add_mcam_flow_entry(struct otx2_nic *nic, 1262 struct npc_install_flow_req *req); 1263 int otx2_tc_add_to_flow_list(struct otx2_flow_config *flow_cfg, 1264 struct otx2_tc_flow *node); 1265 1266 struct otx2_tc_flow * 1267 otx2_tc_get_entry_by_index(struct otx2_flow_config *flow_cfg, 1268 int index); 1269 #endif /* OTX2_COMMON_H */ 1270