1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 #include <linux/iopoll.h> 34 35 #include <drm/drm_print.h> 36 #include <drm/display/drm_hdcp_helper.h> 37 38 #include "i915_reg.h" 39 #include "intel_de.h" 40 #include "intel_display_regs.h" 41 #include "intel_display_types.h" 42 #include "intel_display_wa.h" 43 #include "intel_gmbus.h" 44 #include "intel_gmbus_regs.h" 45 #include "intel_parent.h" 46 47 struct intel_gmbus { 48 struct i2c_adapter adapter; 49 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 50 u32 force_bit; 51 u32 reg0; 52 i915_reg_t gpio_reg; 53 struct i2c_algo_bit_data bit_algo; 54 struct intel_display *display; 55 }; 56 57 enum gmbus_gpio { 58 GPIOA, 59 GPIOB, 60 GPIOC, 61 GPIOD, 62 GPIOE, 63 GPIOF, 64 GPIOG, 65 GPIOH, 66 __GPIOI_UNUSED, 67 GPIOJ, 68 GPIOK, 69 GPIOL, 70 GPIOM, 71 GPION, 72 GPIOO, 73 }; 74 75 struct gmbus_pin { 76 const char *name; 77 enum gmbus_gpio gpio; 78 }; 79 80 /* Map gmbus pin pairs to names and registers. */ 81 static const struct gmbus_pin gmbus_pins[] = { 82 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 83 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 84 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 85 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 86 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 87 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 88 }; 89 90 static const struct gmbus_pin gmbus_pins_bdw[] = { 91 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 92 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 93 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 94 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 95 }; 96 97 static const struct gmbus_pin gmbus_pins_skl[] = { 98 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 99 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 100 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 101 }; 102 103 static const struct gmbus_pin gmbus_pins_bxt[] = { 104 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 105 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 106 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 107 }; 108 109 static const struct gmbus_pin gmbus_pins_cnp[] = { 110 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 111 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 112 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 113 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 114 }; 115 116 static const struct gmbus_pin gmbus_pins_icp[] = { 117 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 118 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 119 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 120 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 121 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 122 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 123 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 124 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 125 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 126 }; 127 128 static const struct gmbus_pin gmbus_pins_dg1[] = { 129 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 130 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 131 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 132 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 133 }; 134 135 static const struct gmbus_pin gmbus_pins_dg2[] = { 136 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 137 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 138 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 139 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 140 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 141 }; 142 143 static const struct gmbus_pin gmbus_pins_mtp[] = { 144 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 145 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 146 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 147 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 148 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, 149 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 150 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 151 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 152 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 153 }; 154 155 static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, 156 unsigned int pin) 157 { 158 const struct gmbus_pin *pins; 159 size_t size; 160 161 if (INTEL_PCH_TYPE(display) >= PCH_MTL) { 162 pins = gmbus_pins_mtp; 163 size = ARRAY_SIZE(gmbus_pins_mtp); 164 } else if (INTEL_PCH_TYPE(display) >= PCH_DG2) { 165 pins = gmbus_pins_dg2; 166 size = ARRAY_SIZE(gmbus_pins_dg2); 167 } else if (INTEL_PCH_TYPE(display) >= PCH_DG1) { 168 pins = gmbus_pins_dg1; 169 size = ARRAY_SIZE(gmbus_pins_dg1); 170 } else if (INTEL_PCH_TYPE(display) >= PCH_ICP) { 171 pins = gmbus_pins_icp; 172 size = ARRAY_SIZE(gmbus_pins_icp); 173 } else if (HAS_PCH_CNP(display)) { 174 pins = gmbus_pins_cnp; 175 size = ARRAY_SIZE(gmbus_pins_cnp); 176 } else if (display->platform.geminilake || display->platform.broxton) { 177 pins = gmbus_pins_bxt; 178 size = ARRAY_SIZE(gmbus_pins_bxt); 179 } else if (DISPLAY_VER(display) == 9) { 180 pins = gmbus_pins_skl; 181 size = ARRAY_SIZE(gmbus_pins_skl); 182 } else if (display->platform.broadwell) { 183 pins = gmbus_pins_bdw; 184 size = ARRAY_SIZE(gmbus_pins_bdw); 185 } else { 186 pins = gmbus_pins; 187 size = ARRAY_SIZE(gmbus_pins); 188 } 189 190 if (pin >= size || !pins[pin].name) 191 return NULL; 192 193 return &pins[pin]; 194 } 195 196 bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin) 197 { 198 return get_gmbus_pin(display, pin); 199 } 200 201 /* Intel GPIO access functions */ 202 203 #define I2C_RISEFALL_TIME 10 204 205 static inline struct intel_gmbus * 206 to_intel_gmbus(struct i2c_adapter *i2c) 207 { 208 return container_of(i2c, struct intel_gmbus, adapter); 209 } 210 211 void 212 intel_gmbus_reset(struct intel_display *display) 213 { 214 intel_de_write(display, GMBUS0(display), 0); 215 intel_de_write(display, GMBUS4(display), 0); 216 } 217 218 static void pnv_gmbus_clock_gating(struct intel_display *display, 219 bool enable) 220 { 221 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 222 intel_de_rmw(display, DSPCLK_GATE_D, 223 PNV_GMBUSUNIT_CLOCK_GATE_DISABLE, 224 !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 225 } 226 227 static void pch_gmbus_clock_gating(struct intel_display *display, 228 bool enable) 229 { 230 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 231 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 232 !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 233 } 234 235 static void bxt_gmbus_clock_gating(struct intel_display *display, 236 bool enable) 237 { 238 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS, 239 !enable ? BXT_GMBUS_GATING_DIS : 0); 240 } 241 242 static u32 get_reserved(struct intel_gmbus *bus) 243 { 244 struct intel_display *display = bus->display; 245 u32 preserve_bits = 0; 246 247 if (display->platform.i830 || display->platform.i845g) 248 return 0; 249 250 /* On most chips, these bits must be preserved in software. */ 251 preserve_bits |= GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE; 252 253 /* Wa_16025573575: the masks bits need to be preserved through out */ 254 if (intel_display_wa(display, 16025573575)) 255 preserve_bits |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK | 256 GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK; 257 258 return intel_de_read_notrace(display, bus->gpio_reg) & preserve_bits; 259 } 260 261 static int get_clock(void *data) 262 { 263 struct intel_gmbus *bus = data; 264 struct intel_display *display = bus->display; 265 u32 reserved = get_reserved(bus); 266 267 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 268 intel_de_write_notrace(display, bus->gpio_reg, reserved); 269 270 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 271 } 272 273 static int get_data(void *data) 274 { 275 struct intel_gmbus *bus = data; 276 struct intel_display *display = bus->display; 277 u32 reserved = get_reserved(bus); 278 279 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 280 intel_de_write_notrace(display, bus->gpio_reg, reserved); 281 282 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 283 } 284 285 static void set_clock(void *data, int state_high) 286 { 287 struct intel_gmbus *bus = data; 288 struct intel_display *display = bus->display; 289 u32 reserved = get_reserved(bus); 290 u32 clock_bits; 291 292 if (state_high) 293 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 294 else 295 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 296 GPIO_CLOCK_VAL_MASK; 297 298 intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits); 299 intel_de_posting_read(display, bus->gpio_reg); 300 } 301 302 static void set_data(void *data, int state_high) 303 { 304 struct intel_gmbus *bus = data; 305 struct intel_display *display = bus->display; 306 u32 reserved = get_reserved(bus); 307 u32 data_bits; 308 309 if (state_high) 310 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 311 else 312 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 313 GPIO_DATA_VAL_MASK; 314 315 intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits); 316 intel_de_posting_read(display, bus->gpio_reg); 317 } 318 319 static void 320 ptl_handle_mask_bits(struct intel_gmbus *bus, bool set) 321 { 322 struct intel_display *display = bus->display; 323 u32 reg_val = intel_de_read_notrace(display, bus->gpio_reg); 324 u32 mask_bits = GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK | 325 GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK; 326 if (set) 327 reg_val |= mask_bits; 328 else 329 reg_val &= ~mask_bits; 330 331 intel_de_write_notrace(display, bus->gpio_reg, reg_val); 332 intel_de_posting_read(display, bus->gpio_reg); 333 } 334 335 static int 336 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 337 { 338 struct intel_gmbus *bus = to_intel_gmbus(adapter); 339 struct intel_display *display = bus->display; 340 341 intel_gmbus_reset(display); 342 343 if (display->platform.pineview) 344 pnv_gmbus_clock_gating(display, false); 345 346 if (intel_display_wa(display, 16025573575)) 347 ptl_handle_mask_bits(bus, true); 348 349 set_data(bus, 1); 350 set_clock(bus, 1); 351 udelay(I2C_RISEFALL_TIME); 352 return 0; 353 } 354 355 static void 356 intel_gpio_post_xfer(struct i2c_adapter *adapter) 357 { 358 struct intel_gmbus *bus = to_intel_gmbus(adapter); 359 struct intel_display *display = bus->display; 360 361 set_data(bus, 1); 362 set_clock(bus, 1); 363 364 if (display->platform.pineview) 365 pnv_gmbus_clock_gating(display, true); 366 367 if (intel_display_wa(display, 16025573575)) 368 ptl_handle_mask_bits(bus, false); 369 } 370 371 static void 372 intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 373 { 374 struct i2c_algo_bit_data *algo; 375 376 algo = &bus->bit_algo; 377 378 bus->gpio_reg = gpio_reg; 379 bus->adapter.algo_data = algo; 380 algo->setsda = set_data; 381 algo->setscl = set_clock; 382 algo->getsda = get_data; 383 algo->getscl = get_clock; 384 algo->pre_xfer = intel_gpio_pre_xfer; 385 algo->post_xfer = intel_gpio_post_xfer; 386 algo->udelay = I2C_RISEFALL_TIME; 387 algo->timeout = usecs_to_jiffies(2200); 388 algo->data = bus; 389 } 390 391 static bool has_gmbus_irq(struct intel_display *display) 392 { 393 /* 394 * encoder->shutdown() may want to use GMBUS 395 * after irqs have already been disabled. 396 */ 397 return HAS_GMBUS_IRQ(display) && intel_parent_irq_enabled(display); 398 } 399 400 static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en) 401 { 402 DEFINE_WAIT(wait); 403 u32 gmbus2; 404 int ret; 405 406 /* Important: The hw handles only the first bit, so set only one! Since 407 * we also need to check for NAKs besides the hw ready/idle signal, we 408 * need to wake up periodically and check that ourselves. 409 */ 410 if (!has_gmbus_irq(display)) 411 irq_en = 0; 412 413 add_wait_queue(&display->gmbus.wait_queue, &wait); 414 intel_de_write_fw(display, GMBUS4(display), irq_en); 415 416 status |= GMBUS_SATOER; 417 418 ret = poll_timeout_us_atomic(gmbus2 = intel_de_read_fw(display, GMBUS2(display)), 419 gmbus2 & status, 420 0, 2, false); 421 if (ret) 422 ret = poll_timeout_us(gmbus2 = intel_de_read_fw(display, GMBUS2(display)), 423 gmbus2 & status, 424 500, 50 * 1000, false); 425 426 intel_de_write_fw(display, GMBUS4(display), 0); 427 remove_wait_queue(&display->gmbus.wait_queue, &wait); 428 429 if (gmbus2 & GMBUS_SATOER) 430 return -ENXIO; 431 432 return ret; 433 } 434 435 static int 436 gmbus_wait_idle(struct intel_display *display) 437 { 438 DEFINE_WAIT(wait); 439 u32 irq_enable; 440 int ret; 441 442 /* Important: The hw handles only the first bit, so set only one! */ 443 irq_enable = 0; 444 if (has_gmbus_irq(display)) 445 irq_enable = GMBUS_IDLE_EN; 446 447 add_wait_queue(&display->gmbus.wait_queue, &wait); 448 intel_de_write_fw(display, GMBUS4(display), irq_enable); 449 450 ret = intel_de_wait_fw_ms(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10, NULL); 451 452 intel_de_write_fw(display, GMBUS4(display), 0); 453 remove_wait_queue(&display->gmbus.wait_queue, &wait); 454 455 return ret; 456 } 457 458 static unsigned int gmbus_max_xfer_size(struct intel_display *display) 459 { 460 return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 461 GMBUS_BYTE_COUNT_MAX; 462 } 463 464 static int 465 gmbus_xfer_read_chunk(struct intel_display *display, 466 unsigned short addr, u8 *buf, unsigned int len, 467 u32 gmbus0_reg, u32 gmbus1_index) 468 { 469 unsigned int size = len; 470 bool burst_read = len > gmbus_max_xfer_size(display); 471 bool extra_byte_added = false; 472 473 if (burst_read) { 474 /* 475 * As per HW Spec, for 512Bytes need to read extra Byte and 476 * Ignore the extra byte read. 477 */ 478 if (len == 512) { 479 extra_byte_added = true; 480 len++; 481 } 482 size = len % 256 + 256; 483 intel_de_write_fw(display, GMBUS0(display), 484 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 485 } 486 487 intel_de_write_fw(display, GMBUS1(display), 488 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 489 while (len) { 490 int ret; 491 u32 val, loop = 0; 492 493 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 494 if (ret) 495 return ret; 496 497 val = intel_de_read_fw(display, GMBUS3(display)); 498 do { 499 if (extra_byte_added && len == 1) { 500 len--; 501 break; 502 } 503 504 *buf++ = val & 0xff; 505 val >>= 8; 506 } while (--len && ++loop < 4); 507 508 if (burst_read && len == size - 4) 509 /* Reset the override bit */ 510 intel_de_write_fw(display, GMBUS0(display), gmbus0_reg); 511 } 512 513 return 0; 514 } 515 516 /* 517 * HW spec says that 512Bytes in Burst read need special treatment. 518 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 519 * an I2C target, which supports such a lengthy burst read too for experiments. 520 * 521 * So until things get clarified on HW support, to avoid the burst read length 522 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 523 */ 524 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 525 526 static int 527 gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg, 528 u32 gmbus0_reg, u32 gmbus1_index) 529 { 530 u8 *buf = msg->buf; 531 unsigned int rx_size = msg->len; 532 unsigned int len; 533 int ret; 534 535 do { 536 if (HAS_GMBUS_BURST_READ(display)) 537 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 538 else 539 len = min(rx_size, gmbus_max_xfer_size(display)); 540 541 ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len, 542 gmbus0_reg, gmbus1_index); 543 if (ret) 544 return ret; 545 546 rx_size -= len; 547 buf += len; 548 } while (rx_size != 0); 549 550 return 0; 551 } 552 553 static int 554 gmbus_xfer_write_chunk(struct intel_display *display, 555 unsigned short addr, u8 *buf, unsigned int len, 556 u32 gmbus1_index) 557 { 558 unsigned int chunk_size = len; 559 u32 val, loop; 560 561 val = loop = 0; 562 while (len && loop < 4) { 563 val |= *buf++ << (8 * loop++); 564 len -= 1; 565 } 566 567 intel_de_write_fw(display, GMBUS3(display), val); 568 intel_de_write_fw(display, GMBUS1(display), 569 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 570 while (len) { 571 int ret; 572 573 val = loop = 0; 574 do { 575 val |= *buf++ << (8 * loop); 576 } while (--len && ++loop < 4); 577 578 intel_de_write_fw(display, GMBUS3(display), val); 579 580 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 581 if (ret) 582 return ret; 583 } 584 585 return 0; 586 } 587 588 static int 589 gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg, 590 u32 gmbus1_index) 591 { 592 u8 *buf = msg->buf; 593 unsigned int tx_size = msg->len; 594 unsigned int len; 595 int ret; 596 597 do { 598 len = min(tx_size, gmbus_max_xfer_size(display)); 599 600 ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len, 601 gmbus1_index); 602 if (ret) 603 return ret; 604 605 buf += len; 606 tx_size -= len; 607 } while (tx_size != 0); 608 609 return 0; 610 } 611 612 /* 613 * The gmbus controller can combine a 1 or 2 byte write with another read/write 614 * that immediately follows it by using an "INDEX" cycle. 615 */ 616 static bool 617 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 618 { 619 return (i + 1 < num && 620 msgs[i].addr == msgs[i + 1].addr && 621 !(msgs[i].flags & I2C_M_RD) && 622 (msgs[i].len == 1 || msgs[i].len == 2) && 623 msgs[i + 1].len > 0); 624 } 625 626 static int 627 gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs, 628 u32 gmbus0_reg) 629 { 630 u32 gmbus1_index = 0; 631 u32 gmbus5 = 0; 632 int ret; 633 634 if (msgs[0].len == 2) 635 gmbus5 = GMBUS_2BYTE_INDEX_EN | 636 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 637 if (msgs[0].len == 1) 638 gmbus1_index = GMBUS_CYCLE_INDEX | 639 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 640 641 /* GMBUS5 holds 16-bit index */ 642 if (gmbus5) 643 intel_de_write_fw(display, GMBUS5(display), gmbus5); 644 645 if (msgs[1].flags & I2C_M_RD) 646 ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg, 647 gmbus1_index); 648 else 649 ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index); 650 651 /* Clear GMBUS5 after each index transfer */ 652 if (gmbus5) 653 intel_de_write_fw(display, GMBUS5(display), 0); 654 655 return ret; 656 } 657 658 static int 659 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 660 u32 gmbus0_source) 661 { 662 struct intel_gmbus *bus = to_intel_gmbus(adapter); 663 struct intel_display *display = bus->display; 664 int i = 0, inc, try = 0; 665 int ret = 0; 666 667 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 668 if (display->platform.geminilake || display->platform.broxton) 669 bxt_gmbus_clock_gating(display, false); 670 else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display)) 671 pch_gmbus_clock_gating(display, false); 672 673 retry: 674 intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0); 675 676 for (; i < num; i += inc) { 677 inc = 1; 678 if (gmbus_is_index_xfer(msgs, i, num)) { 679 ret = gmbus_index_xfer(display, &msgs[i], 680 gmbus0_source | bus->reg0); 681 inc = 2; /* an index transmission is two msgs */ 682 } else if (msgs[i].flags & I2C_M_RD) { 683 ret = gmbus_xfer_read(display, &msgs[i], 684 gmbus0_source | bus->reg0, 0); 685 } else { 686 ret = gmbus_xfer_write(display, &msgs[i], 0); 687 } 688 689 if (!ret) 690 ret = gmbus_wait(display, 691 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 692 if (ret == -ETIMEDOUT) 693 goto timeout; 694 else if (ret) 695 goto clear_err; 696 } 697 698 /* Generate a STOP condition on the bus. Note that gmbus can't generata 699 * a STOP on the very first cycle. To simplify the code we 700 * unconditionally generate the STOP condition with an additional gmbus 701 * cycle. */ 702 intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 703 704 /* Mark the GMBUS interface as disabled after waiting for idle. 705 * We will re-enable it at the start of the next xfer, 706 * till then let it sleep. 707 */ 708 if (gmbus_wait_idle(display)) { 709 drm_dbg_kms(display->drm, 710 "GMBUS [%s] timed out waiting for idle\n", 711 adapter->name); 712 ret = -ETIMEDOUT; 713 } 714 intel_de_write_fw(display, GMBUS0(display), 0); 715 ret = ret ?: i; 716 goto out; 717 718 clear_err: 719 /* 720 * Wait for bus to IDLE before clearing NAK. 721 * If we clear the NAK while bus is still active, then it will stay 722 * active and the next transaction may fail. 723 * 724 * If no ACK is received during the address phase of a transaction, the 725 * adapter must report -ENXIO. It is not clear what to return if no ACK 726 * is received at other times. But we have to be careful to not return 727 * spurious -ENXIO because that will prevent i2c and drm edid functions 728 * from retrying. So return -ENXIO only when gmbus properly quiescents - 729 * timing out seems to happen when there _is_ a ddc chip present, but 730 * it's slow responding and only answers on the 2nd retry. 731 */ 732 ret = -ENXIO; 733 if (gmbus_wait_idle(display)) { 734 drm_dbg_kms(display->drm, 735 "GMBUS [%s] timed out after NAK\n", 736 adapter->name); 737 ret = -ETIMEDOUT; 738 } 739 740 /* Toggle the Software Clear Interrupt bit. This has the effect 741 * of resetting the GMBUS controller and so clearing the 742 * BUS_ERROR raised by the target's NAK. 743 */ 744 intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT); 745 intel_de_write_fw(display, GMBUS1(display), 0); 746 intel_de_write_fw(display, GMBUS0(display), 0); 747 748 drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 749 adapter->name, msgs[i].addr, 750 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 751 752 /* 753 * Passive adapters sometimes NAK the first probe. Retry the first 754 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 755 * has retries internally. See also the retry loop in 756 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 757 */ 758 if (ret == -ENXIO && i == 0 && try++ == 0) { 759 drm_dbg_kms(display->drm, 760 "GMBUS [%s] NAK on first message, retry\n", 761 adapter->name); 762 goto retry; 763 } 764 765 goto out; 766 767 timeout: 768 drm_dbg_kms(display->drm, 769 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 770 bus->adapter.name, bus->reg0 & 0xff); 771 intel_de_write_fw(display, GMBUS0(display), 0); 772 773 /* 774 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 775 * instead. Use EAGAIN to have i2c core retry. 776 */ 777 ret = -EAGAIN; 778 779 out: 780 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 781 if (display->platform.geminilake || display->platform.broxton) 782 bxt_gmbus_clock_gating(display, true); 783 else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display)) 784 pch_gmbus_clock_gating(display, true); 785 786 return ret; 787 } 788 789 static int 790 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 791 { 792 struct intel_gmbus *bus = to_intel_gmbus(adapter); 793 struct intel_display *display = bus->display; 794 struct ref_tracker *wakeref; 795 int ret; 796 797 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 798 799 if (bus->force_bit) { 800 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 801 if (ret < 0) 802 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 803 } else { 804 ret = do_gmbus_xfer(adapter, msgs, num, 0); 805 if (ret == -EAGAIN) 806 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 807 } 808 809 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 810 811 return ret; 812 } 813 814 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 815 { 816 struct intel_gmbus *bus = to_intel_gmbus(adapter); 817 struct intel_display *display = bus->display; 818 u8 cmd = DRM_HDCP_DDC_AKSV; 819 u8 buf[DRM_HDCP_KSV_LEN] = {}; 820 struct i2c_msg msgs[] = { 821 { 822 .addr = DRM_HDCP_DDC_ADDR, 823 .flags = 0, 824 .len = sizeof(cmd), 825 .buf = &cmd, 826 }, 827 { 828 .addr = DRM_HDCP_DDC_ADDR, 829 .flags = 0, 830 .len = sizeof(buf), 831 .buf = buf, 832 } 833 }; 834 struct ref_tracker *wakeref; 835 int ret; 836 837 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 838 mutex_lock(&display->gmbus.mutex); 839 840 /* 841 * In order to output Aksv to the receiver, use an indexed write to 842 * pass the i2c command, and tell GMBUS to use the HW-provided value 843 * instead of sourcing GMBUS3 for the data. 844 */ 845 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 846 847 mutex_unlock(&display->gmbus.mutex); 848 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 849 850 return ret; 851 } 852 853 static u32 gmbus_func(struct i2c_adapter *adapter) 854 { 855 return i2c_bit_algo.functionality(adapter) & 856 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 857 /* I2C_FUNC_10BIT_ADDR | */ 858 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 859 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 860 } 861 862 static const struct i2c_algorithm gmbus_algorithm = { 863 .master_xfer = gmbus_xfer, 864 .functionality = gmbus_func 865 }; 866 867 static void gmbus_lock_bus(struct i2c_adapter *adapter, 868 unsigned int flags) 869 { 870 struct intel_gmbus *bus = to_intel_gmbus(adapter); 871 struct intel_display *display = bus->display; 872 873 mutex_lock(&display->gmbus.mutex); 874 } 875 876 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 877 unsigned int flags) 878 { 879 struct intel_gmbus *bus = to_intel_gmbus(adapter); 880 struct intel_display *display = bus->display; 881 882 return mutex_trylock(&display->gmbus.mutex); 883 } 884 885 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 886 unsigned int flags) 887 { 888 struct intel_gmbus *bus = to_intel_gmbus(adapter); 889 struct intel_display *display = bus->display; 890 891 mutex_unlock(&display->gmbus.mutex); 892 } 893 894 static const struct i2c_lock_operations gmbus_lock_ops = { 895 .lock_bus = gmbus_lock_bus, 896 .trylock_bus = gmbus_trylock_bus, 897 .unlock_bus = gmbus_unlock_bus, 898 }; 899 900 /** 901 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 902 * @display: display device 903 */ 904 int intel_gmbus_setup(struct intel_display *display) 905 { 906 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 907 unsigned int pin; 908 int ret; 909 910 if (display->platform.valleyview || display->platform.cherryview) 911 display->gmbus.mmio_base = VLV_DISPLAY_BASE; 912 else if (!HAS_GMCH(display)) 913 /* 914 * Broxton uses the same PCH offsets for South Display Engine, 915 * even though it doesn't have a PCH. 916 */ 917 display->gmbus.mmio_base = PCH_DISPLAY_BASE; 918 919 mutex_init(&display->gmbus.mutex); 920 init_waitqueue_head(&display->gmbus.wait_queue); 921 922 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) { 923 const struct gmbus_pin *gmbus_pin; 924 struct intel_gmbus *bus; 925 926 gmbus_pin = get_gmbus_pin(display, pin); 927 if (!gmbus_pin) 928 continue; 929 930 bus = kzalloc_obj(*bus); 931 if (!bus) { 932 ret = -ENOMEM; 933 goto err; 934 } 935 936 bus->adapter.owner = THIS_MODULE; 937 snprintf(bus->adapter.name, 938 sizeof(bus->adapter.name), 939 "i915 gmbus %s", gmbus_pin->name); 940 941 bus->adapter.dev.parent = &pdev->dev; 942 bus->display = display; 943 944 bus->adapter.algo = &gmbus_algorithm; 945 bus->adapter.lock_ops = &gmbus_lock_ops; 946 947 /* 948 * We wish to retry with bit banging 949 * after a timed out GMBUS attempt. 950 */ 951 bus->adapter.retries = 1; 952 953 /* By default use a conservative clock rate */ 954 bus->reg0 = pin | GMBUS_RATE_100KHZ; 955 956 /* gmbus seems to be broken on i830 */ 957 if (display->platform.i830) 958 bus->force_bit = 1; 959 960 intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio)); 961 962 ret = i2c_add_adapter(&bus->adapter); 963 if (ret) { 964 kfree(bus); 965 goto err; 966 } 967 968 display->gmbus.bus[pin] = bus; 969 } 970 971 intel_gmbus_reset(display); 972 973 return 0; 974 975 err: 976 intel_gmbus_teardown(display); 977 978 return ret; 979 } 980 981 struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display, 982 unsigned int pin) 983 { 984 if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) || 985 !display->gmbus.bus[pin])) 986 return NULL; 987 988 return &display->gmbus.bus[pin]->adapter; 989 } 990 991 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 992 { 993 struct intel_gmbus *bus = to_intel_gmbus(adapter); 994 struct intel_display *display = bus->display; 995 996 mutex_lock(&display->gmbus.mutex); 997 998 bus->force_bit += force_bit ? 1 : -1; 999 drm_dbg_kms(display->drm, 1000 "%sabling bit-banging on %s. force bit now %d\n", 1001 force_bit ? "en" : "dis", adapter->name, 1002 bus->force_bit); 1003 1004 mutex_unlock(&display->gmbus.mutex); 1005 } 1006 1007 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1008 { 1009 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1010 1011 return bus->force_bit; 1012 } 1013 1014 void intel_gmbus_teardown(struct intel_display *display) 1015 { 1016 unsigned int pin; 1017 1018 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) { 1019 struct intel_gmbus *bus; 1020 1021 bus = display->gmbus.bus[pin]; 1022 if (!bus) 1023 continue; 1024 1025 i2c_del_adapter(&bus->adapter); 1026 1027 kfree(bus); 1028 display->gmbus.bus[pin] = NULL; 1029 } 1030 } 1031 1032 void intel_gmbus_irq_handler(struct intel_display *display) 1033 { 1034 wake_up_all(&display->gmbus.wait_queue); 1035 } 1036