1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
17 #include <linux/kvm_host.h>
18
19 #include <asm/cpufeature.h>
20 #include <asm/debugreg.h>
21 #include <asm/hardirq.h>
22 #include <asm/intel-family.h>
23 #include <asm/intel_pt.h>
24 #include <asm/apic.h>
25 #include <asm/cpu_device_id.h>
26 #include <asm/msr.h>
27
28 #include "../perf_event.h"
29
30 /*
31 * Intel PerfMon, used on Core and later.
32 */
33 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
34 {
35 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
36 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
37 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
38 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
39 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
40 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
41 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
42 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
43 };
44
45 static struct event_constraint intel_core_event_constraints[] __read_mostly =
46 {
47 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
48 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
49 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
50 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
51 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
52 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
53 EVENT_CONSTRAINT_END
54 };
55
56 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
57 {
58 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
59 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
60 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
61 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
62 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
63 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
64 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
65 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
66 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
67 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
68 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
69 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
70 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
71 EVENT_CONSTRAINT_END
72 };
73
74 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
75 {
76 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
77 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
78 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
79 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
80 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
81 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
82 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
83 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
84 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
85 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
86 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
87 EVENT_CONSTRAINT_END
88 };
89
90 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
91 {
92 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
93 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
94 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
95 EVENT_EXTRA_END
96 };
97
98 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
99 {
100 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
101 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
102 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
103 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
104 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
105 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
106 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
107 EVENT_CONSTRAINT_END
108 };
109
110 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
111 {
112 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
113 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
114 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
116 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
118 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
119 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
120 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
121 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
122 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
123 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
124
125 /*
126 * When HT is off these events can only run on the bottom 4 counters
127 * When HT is on, they are impacted by the HT bug and require EXCL access
128 */
129 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
130 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
131 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
132 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
133
134 EVENT_CONSTRAINT_END
135 };
136
137 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
138 {
139 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
140 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
141 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
142 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
144 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
145 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
146 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
147 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
149 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
150 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
151 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
152
153 /*
154 * When HT is off these events can only run on the bottom 4 counters
155 * When HT is on, they are impacted by the HT bug and require EXCL access
156 */
157 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
158 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
159 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
160 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
161
162 EVENT_CONSTRAINT_END
163 };
164
165 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
166 {
167 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
168 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
169 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
170 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
171 EVENT_EXTRA_END
172 };
173
174 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
175 {
176 EVENT_CONSTRAINT_END
177 };
178
179 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
180 {
181 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
182 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
183 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
184 EVENT_CONSTRAINT_END
185 };
186
187 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
188 {
189 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
190 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
191 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
192 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
193 FIXED_EVENT_CONSTRAINT(0x0500, 4),
194 FIXED_EVENT_CONSTRAINT(0x0600, 5),
195 FIXED_EVENT_CONSTRAINT(0x0700, 6),
196 FIXED_EVENT_CONSTRAINT(0x0800, 7),
197 FIXED_EVENT_CONSTRAINT(0x0900, 8),
198 FIXED_EVENT_CONSTRAINT(0x0a00, 9),
199 FIXED_EVENT_CONSTRAINT(0x0b00, 10),
200 FIXED_EVENT_CONSTRAINT(0x0c00, 11),
201 FIXED_EVENT_CONSTRAINT(0x0d00, 12),
202 FIXED_EVENT_CONSTRAINT(0x0e00, 13),
203 FIXED_EVENT_CONSTRAINT(0x0f00, 14),
204 FIXED_EVENT_CONSTRAINT(0x1000, 15),
205 EVENT_CONSTRAINT_END
206 };
207
208 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
209 {
210 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
211 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
212 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
213 EVENT_CONSTRAINT_END
214 };
215
216 static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
217 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
218 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
219 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
220 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
221 EVENT_CONSTRAINT_END
222 };
223
224 static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
225 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
226 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
227 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
228 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
229 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
230 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
231 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
232 EVENT_CONSTRAINT_END
233 };
234
235 static struct event_constraint intel_skl_event_constraints[] = {
236 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
237 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
238 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
239 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
240
241 /*
242 * when HT is off, these can only run on the bottom 4 counters
243 */
244 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
245 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
246 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
247 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
248 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
249
250 EVENT_CONSTRAINT_END
251 };
252
253 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
254 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
255 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
256 EVENT_EXTRA_END
257 };
258
259 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
260 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
261 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
262 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
263 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
264 EVENT_EXTRA_END
265 };
266
267 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
268 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
269 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
270 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
271 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
272 EVENT_EXTRA_END
273 };
274
275 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
276 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
277 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
278 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
279 /*
280 * Note the low 8 bits eventsel code is not a continuous field, containing
281 * some #GPing bits. These are masked out.
282 */
283 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
284 EVENT_EXTRA_END
285 };
286
287 static struct event_constraint intel_icl_event_constraints[] = {
288 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
289 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
290 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
291 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
292 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
293 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
294 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
295 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
297 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
298 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
299 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
300 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
301 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf),
302 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
303 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
304 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
305 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
306 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
307 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
308 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
309 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
310 INTEL_EVENT_CONSTRAINT(0xef, 0xf),
311 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
312 EVENT_CONSTRAINT_END
313 };
314
315 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
316 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
317 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
318 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
319 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
320 EVENT_EXTRA_END
321 };
322
323 static struct extra_reg intel_glc_extra_regs[] __read_mostly = {
324 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
325 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
326 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
327 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
328 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
329 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
330 EVENT_EXTRA_END
331 };
332
333 static struct event_constraint intel_glc_event_constraints[] = {
334 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
335 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
336 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
337 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
338 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
339 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
340 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
341 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
342 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
343 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
344 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
345 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
346 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
347 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
348
349 INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
350 INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
351 /*
352 * Generally event codes < 0x90 are restricted to counters 0-3.
353 * The 0x2E and 0x3C are exception, which has no restriction.
354 */
355 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
356
357 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
358 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
359 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
360 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
361 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
362 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
363 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
364 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
365 /*
366 * Generally event codes >= 0x90 are likely to have no restrictions.
367 * The exception are defined as above.
368 */
369 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
370
371 EVENT_CONSTRAINT_END
372 };
373
374 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = {
375 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
376 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
377 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
378 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
379 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
380 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
381 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
382 EVENT_EXTRA_END
383 };
384
385 static struct event_constraint intel_lnc_event_constraints[] = {
386 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
387 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
388 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
389 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
390 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
391 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
392 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
393 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
394 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
395 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
396 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
397 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
398 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
399 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
400
401 INTEL_EVENT_CONSTRAINT(0x20, 0xf),
402
403 INTEL_UEVENT_CONSTRAINT(0x012a, 0xf),
404 INTEL_UEVENT_CONSTRAINT(0x012b, 0xf),
405 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
406 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),
407
408 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff),
409 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff),
410
411 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
412 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
413 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
414 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
415 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1),
416 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
417 INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc),
418 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
419
420 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
421
422 INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf),
423
424 EVENT_CONSTRAINT_END
425 };
426
427 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {
428 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0),
429 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1),
430 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
431 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
432 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
433 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
434 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
435 EVENT_EXTRA_END
436 };
437
438 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
439 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
440 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
441
442 static struct attribute *nhm_mem_events_attrs[] = {
443 EVENT_PTR(mem_ld_nhm),
444 NULL,
445 };
446
447 /*
448 * topdown events for Intel Core CPUs.
449 *
450 * The events are all in slots, which is a free slot in a 4 wide
451 * pipeline. Some events are already reported in slots, for cycle
452 * events we multiply by the pipeline width (4).
453 *
454 * With Hyper Threading on, topdown metrics are either summed or averaged
455 * between the threads of a core: (count_t0 + count_t1).
456 *
457 * For the average case the metric is always scaled to pipeline width,
458 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
459 */
460
461 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
462 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
463 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
464 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
465 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
466 "event=0xe,umask=0x1"); /* uops_issued.any */
467 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
468 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
469 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
470 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
471 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
472 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
473 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
474 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
475 "4", "2");
476
477 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
478 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
479 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
480 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
481 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
482 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84");
483 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85");
484 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
485 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87");
486
487 static struct attribute *snb_events_attrs[] = {
488 EVENT_PTR(td_slots_issued),
489 EVENT_PTR(td_slots_retired),
490 EVENT_PTR(td_fetch_bubbles),
491 EVENT_PTR(td_total_slots),
492 EVENT_PTR(td_total_slots_scale),
493 EVENT_PTR(td_recovery_bubbles),
494 EVENT_PTR(td_recovery_bubbles_scale),
495 NULL,
496 };
497
498 static struct attribute *snb_mem_events_attrs[] = {
499 EVENT_PTR(mem_ld_snb),
500 EVENT_PTR(mem_st_snb),
501 NULL,
502 };
503
504 static struct event_constraint intel_hsw_event_constraints[] = {
505 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
506 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
507 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
508 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
509 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
510 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
511 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
512 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
513 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
514 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
515 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
516 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
517
518 /*
519 * When HT is off these events can only run on the bottom 4 counters
520 * When HT is on, they are impacted by the HT bug and require EXCL access
521 */
522 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
523 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
524 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
525 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
526
527 EVENT_CONSTRAINT_END
528 };
529
530 static struct event_constraint intel_bdw_event_constraints[] = {
531 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
532 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
533 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
534 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
535 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
536 /*
537 * when HT is off, these can only run on the bottom 4 counters
538 */
539 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
540 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
541 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
542 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
543 EVENT_CONSTRAINT_END
544 };
545
intel_pmu_event_map(int hw_event)546 static u64 intel_pmu_event_map(int hw_event)
547 {
548 return intel_perfmon_event_map[hw_event];
549 }
550
551 static __initconst const u64 glc_hw_cache_event_ids
552 [PERF_COUNT_HW_CACHE_MAX]
553 [PERF_COUNT_HW_CACHE_OP_MAX]
554 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
555 {
556 [ C(L1D ) ] = {
557 [ C(OP_READ) ] = {
558 [ C(RESULT_ACCESS) ] = 0x81d0,
559 [ C(RESULT_MISS) ] = 0xe124,
560 },
561 [ C(OP_WRITE) ] = {
562 [ C(RESULT_ACCESS) ] = 0x82d0,
563 },
564 },
565 [ C(L1I ) ] = {
566 [ C(OP_READ) ] = {
567 [ C(RESULT_MISS) ] = 0xe424,
568 },
569 [ C(OP_WRITE) ] = {
570 [ C(RESULT_ACCESS) ] = -1,
571 [ C(RESULT_MISS) ] = -1,
572 },
573 },
574 [ C(LL ) ] = {
575 [ C(OP_READ) ] = {
576 [ C(RESULT_ACCESS) ] = 0x12a,
577 [ C(RESULT_MISS) ] = 0x12a,
578 },
579 [ C(OP_WRITE) ] = {
580 [ C(RESULT_ACCESS) ] = 0x12a,
581 [ C(RESULT_MISS) ] = 0x12a,
582 },
583 },
584 [ C(DTLB) ] = {
585 [ C(OP_READ) ] = {
586 [ C(RESULT_ACCESS) ] = 0x81d0,
587 [ C(RESULT_MISS) ] = 0xe12,
588 },
589 [ C(OP_WRITE) ] = {
590 [ C(RESULT_ACCESS) ] = 0x82d0,
591 [ C(RESULT_MISS) ] = 0xe13,
592 },
593 },
594 [ C(ITLB) ] = {
595 [ C(OP_READ) ] = {
596 [ C(RESULT_ACCESS) ] = -1,
597 [ C(RESULT_MISS) ] = 0xe11,
598 },
599 [ C(OP_WRITE) ] = {
600 [ C(RESULT_ACCESS) ] = -1,
601 [ C(RESULT_MISS) ] = -1,
602 },
603 [ C(OP_PREFETCH) ] = {
604 [ C(RESULT_ACCESS) ] = -1,
605 [ C(RESULT_MISS) ] = -1,
606 },
607 },
608 [ C(BPU ) ] = {
609 [ C(OP_READ) ] = {
610 [ C(RESULT_ACCESS) ] = 0x4c4,
611 [ C(RESULT_MISS) ] = 0x4c5,
612 },
613 [ C(OP_WRITE) ] = {
614 [ C(RESULT_ACCESS) ] = -1,
615 [ C(RESULT_MISS) ] = -1,
616 },
617 [ C(OP_PREFETCH) ] = {
618 [ C(RESULT_ACCESS) ] = -1,
619 [ C(RESULT_MISS) ] = -1,
620 },
621 },
622 [ C(NODE) ] = {
623 [ C(OP_READ) ] = {
624 [ C(RESULT_ACCESS) ] = 0x12a,
625 [ C(RESULT_MISS) ] = 0x12a,
626 },
627 },
628 };
629
630 static __initconst const u64 glc_hw_cache_extra_regs
631 [PERF_COUNT_HW_CACHE_MAX]
632 [PERF_COUNT_HW_CACHE_OP_MAX]
633 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
634 {
635 [ C(LL ) ] = {
636 [ C(OP_READ) ] = {
637 [ C(RESULT_ACCESS) ] = 0x10001,
638 [ C(RESULT_MISS) ] = 0x3fbfc00001,
639 },
640 [ C(OP_WRITE) ] = {
641 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
642 [ C(RESULT_MISS) ] = 0x3f3fc00002,
643 },
644 },
645 [ C(NODE) ] = {
646 [ C(OP_READ) ] = {
647 [ C(RESULT_ACCESS) ] = 0x10c000001,
648 [ C(RESULT_MISS) ] = 0x3fb3000001,
649 },
650 },
651 };
652
653 /*
654 * Notes on the events:
655 * - data reads do not include code reads (comparable to earlier tables)
656 * - data counts include speculative execution (except L1 write, dtlb, bpu)
657 * - remote node access includes remote memory, remote cache, remote mmio.
658 * - prefetches are not included in the counts.
659 * - icache miss does not include decoded icache
660 */
661
662 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
663 #define SKL_DEMAND_RFO BIT_ULL(1)
664 #define SKL_ANY_RESPONSE BIT_ULL(16)
665 #define SKL_SUPPLIER_NONE BIT_ULL(17)
666 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
667 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
668 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
669 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
670 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
671 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
672 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
673 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
674 #define SKL_SPL_HIT BIT_ULL(30)
675 #define SKL_SNOOP_NONE BIT_ULL(31)
676 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
677 #define SKL_SNOOP_MISS BIT_ULL(33)
678 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
679 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
680 #define SKL_SNOOP_HITM BIT_ULL(36)
681 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
682 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
683 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
684 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
685 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
686 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
687 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
688 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
689 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
690 SKL_SNOOP_HITM|SKL_SPL_HIT)
691 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
692 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
693 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
694 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
695 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
696
697 static __initconst const u64 skl_hw_cache_event_ids
698 [PERF_COUNT_HW_CACHE_MAX]
699 [PERF_COUNT_HW_CACHE_OP_MAX]
700 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
701 {
702 [ C(L1D ) ] = {
703 [ C(OP_READ) ] = {
704 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
705 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
706 },
707 [ C(OP_WRITE) ] = {
708 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
709 [ C(RESULT_MISS) ] = 0x0,
710 },
711 [ C(OP_PREFETCH) ] = {
712 [ C(RESULT_ACCESS) ] = 0x0,
713 [ C(RESULT_MISS) ] = 0x0,
714 },
715 },
716 [ C(L1I ) ] = {
717 [ C(OP_READ) ] = {
718 [ C(RESULT_ACCESS) ] = 0x0,
719 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
720 },
721 [ C(OP_WRITE) ] = {
722 [ C(RESULT_ACCESS) ] = -1,
723 [ C(RESULT_MISS) ] = -1,
724 },
725 [ C(OP_PREFETCH) ] = {
726 [ C(RESULT_ACCESS) ] = 0x0,
727 [ C(RESULT_MISS) ] = 0x0,
728 },
729 },
730 [ C(LL ) ] = {
731 [ C(OP_READ) ] = {
732 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
733 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
734 },
735 [ C(OP_WRITE) ] = {
736 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
737 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
738 },
739 [ C(OP_PREFETCH) ] = {
740 [ C(RESULT_ACCESS) ] = 0x0,
741 [ C(RESULT_MISS) ] = 0x0,
742 },
743 },
744 [ C(DTLB) ] = {
745 [ C(OP_READ) ] = {
746 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
747 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
748 },
749 [ C(OP_WRITE) ] = {
750 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
751 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
752 },
753 [ C(OP_PREFETCH) ] = {
754 [ C(RESULT_ACCESS) ] = 0x0,
755 [ C(RESULT_MISS) ] = 0x0,
756 },
757 },
758 [ C(ITLB) ] = {
759 [ C(OP_READ) ] = {
760 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
761 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
762 },
763 [ C(OP_WRITE) ] = {
764 [ C(RESULT_ACCESS) ] = -1,
765 [ C(RESULT_MISS) ] = -1,
766 },
767 [ C(OP_PREFETCH) ] = {
768 [ C(RESULT_ACCESS) ] = -1,
769 [ C(RESULT_MISS) ] = -1,
770 },
771 },
772 [ C(BPU ) ] = {
773 [ C(OP_READ) ] = {
774 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
775 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
776 },
777 [ C(OP_WRITE) ] = {
778 [ C(RESULT_ACCESS) ] = -1,
779 [ C(RESULT_MISS) ] = -1,
780 },
781 [ C(OP_PREFETCH) ] = {
782 [ C(RESULT_ACCESS) ] = -1,
783 [ C(RESULT_MISS) ] = -1,
784 },
785 },
786 [ C(NODE) ] = {
787 [ C(OP_READ) ] = {
788 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
789 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
790 },
791 [ C(OP_WRITE) ] = {
792 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
793 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
794 },
795 [ C(OP_PREFETCH) ] = {
796 [ C(RESULT_ACCESS) ] = 0x0,
797 [ C(RESULT_MISS) ] = 0x0,
798 },
799 },
800 };
801
802 static __initconst const u64 skl_hw_cache_extra_regs
803 [PERF_COUNT_HW_CACHE_MAX]
804 [PERF_COUNT_HW_CACHE_OP_MAX]
805 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
806 {
807 [ C(LL ) ] = {
808 [ C(OP_READ) ] = {
809 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
810 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
811 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
812 SKL_L3_MISS|SKL_ANY_SNOOP|
813 SKL_SUPPLIER_NONE,
814 },
815 [ C(OP_WRITE) ] = {
816 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
817 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
818 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
819 SKL_L3_MISS|SKL_ANY_SNOOP|
820 SKL_SUPPLIER_NONE,
821 },
822 [ C(OP_PREFETCH) ] = {
823 [ C(RESULT_ACCESS) ] = 0x0,
824 [ C(RESULT_MISS) ] = 0x0,
825 },
826 },
827 [ C(NODE) ] = {
828 [ C(OP_READ) ] = {
829 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
830 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
831 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
832 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
833 },
834 [ C(OP_WRITE) ] = {
835 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
836 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
837 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
838 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
839 },
840 [ C(OP_PREFETCH) ] = {
841 [ C(RESULT_ACCESS) ] = 0x0,
842 [ C(RESULT_MISS) ] = 0x0,
843 },
844 },
845 };
846
847 #define SNB_DMND_DATA_RD (1ULL << 0)
848 #define SNB_DMND_RFO (1ULL << 1)
849 #define SNB_DMND_IFETCH (1ULL << 2)
850 #define SNB_DMND_WB (1ULL << 3)
851 #define SNB_PF_DATA_RD (1ULL << 4)
852 #define SNB_PF_RFO (1ULL << 5)
853 #define SNB_PF_IFETCH (1ULL << 6)
854 #define SNB_LLC_DATA_RD (1ULL << 7)
855 #define SNB_LLC_RFO (1ULL << 8)
856 #define SNB_LLC_IFETCH (1ULL << 9)
857 #define SNB_BUS_LOCKS (1ULL << 10)
858 #define SNB_STRM_ST (1ULL << 11)
859 #define SNB_OTHER (1ULL << 15)
860 #define SNB_RESP_ANY (1ULL << 16)
861 #define SNB_NO_SUPP (1ULL << 17)
862 #define SNB_LLC_HITM (1ULL << 18)
863 #define SNB_LLC_HITE (1ULL << 19)
864 #define SNB_LLC_HITS (1ULL << 20)
865 #define SNB_LLC_HITF (1ULL << 21)
866 #define SNB_LOCAL (1ULL << 22)
867 #define SNB_REMOTE (0xffULL << 23)
868 #define SNB_SNP_NONE (1ULL << 31)
869 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
870 #define SNB_SNP_MISS (1ULL << 33)
871 #define SNB_NO_FWD (1ULL << 34)
872 #define SNB_SNP_FWD (1ULL << 35)
873 #define SNB_HITM (1ULL << 36)
874 #define SNB_NON_DRAM (1ULL << 37)
875
876 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
877 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
878 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
879
880 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
881 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
882 SNB_HITM)
883
884 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
885 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
886
887 #define SNB_L3_ACCESS SNB_RESP_ANY
888 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
889
890 static __initconst const u64 snb_hw_cache_extra_regs
891 [PERF_COUNT_HW_CACHE_MAX]
892 [PERF_COUNT_HW_CACHE_OP_MAX]
893 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
894 {
895 [ C(LL ) ] = {
896 [ C(OP_READ) ] = {
897 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
898 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
899 },
900 [ C(OP_WRITE) ] = {
901 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
902 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
903 },
904 [ C(OP_PREFETCH) ] = {
905 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
906 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
907 },
908 },
909 [ C(NODE) ] = {
910 [ C(OP_READ) ] = {
911 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
912 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
913 },
914 [ C(OP_WRITE) ] = {
915 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
916 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
917 },
918 [ C(OP_PREFETCH) ] = {
919 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
920 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
921 },
922 },
923 };
924
925 static __initconst const u64 snb_hw_cache_event_ids
926 [PERF_COUNT_HW_CACHE_MAX]
927 [PERF_COUNT_HW_CACHE_OP_MAX]
928 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
929 {
930 [ C(L1D) ] = {
931 [ C(OP_READ) ] = {
932 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
933 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
934 },
935 [ C(OP_WRITE) ] = {
936 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
937 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
938 },
939 [ C(OP_PREFETCH) ] = {
940 [ C(RESULT_ACCESS) ] = 0x0,
941 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
942 },
943 },
944 [ C(L1I ) ] = {
945 [ C(OP_READ) ] = {
946 [ C(RESULT_ACCESS) ] = 0x0,
947 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
948 },
949 [ C(OP_WRITE) ] = {
950 [ C(RESULT_ACCESS) ] = -1,
951 [ C(RESULT_MISS) ] = -1,
952 },
953 [ C(OP_PREFETCH) ] = {
954 [ C(RESULT_ACCESS) ] = 0x0,
955 [ C(RESULT_MISS) ] = 0x0,
956 },
957 },
958 [ C(LL ) ] = {
959 [ C(OP_READ) ] = {
960 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
961 [ C(RESULT_ACCESS) ] = 0x01b7,
962 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
963 [ C(RESULT_MISS) ] = 0x01b7,
964 },
965 [ C(OP_WRITE) ] = {
966 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
967 [ C(RESULT_ACCESS) ] = 0x01b7,
968 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
969 [ C(RESULT_MISS) ] = 0x01b7,
970 },
971 [ C(OP_PREFETCH) ] = {
972 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
973 [ C(RESULT_ACCESS) ] = 0x01b7,
974 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
975 [ C(RESULT_MISS) ] = 0x01b7,
976 },
977 },
978 [ C(DTLB) ] = {
979 [ C(OP_READ) ] = {
980 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
981 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
982 },
983 [ C(OP_WRITE) ] = {
984 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
985 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
986 },
987 [ C(OP_PREFETCH) ] = {
988 [ C(RESULT_ACCESS) ] = 0x0,
989 [ C(RESULT_MISS) ] = 0x0,
990 },
991 },
992 [ C(ITLB) ] = {
993 [ C(OP_READ) ] = {
994 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
995 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
996 },
997 [ C(OP_WRITE) ] = {
998 [ C(RESULT_ACCESS) ] = -1,
999 [ C(RESULT_MISS) ] = -1,
1000 },
1001 [ C(OP_PREFETCH) ] = {
1002 [ C(RESULT_ACCESS) ] = -1,
1003 [ C(RESULT_MISS) ] = -1,
1004 },
1005 },
1006 [ C(BPU ) ] = {
1007 [ C(OP_READ) ] = {
1008 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1009 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1010 },
1011 [ C(OP_WRITE) ] = {
1012 [ C(RESULT_ACCESS) ] = -1,
1013 [ C(RESULT_MISS) ] = -1,
1014 },
1015 [ C(OP_PREFETCH) ] = {
1016 [ C(RESULT_ACCESS) ] = -1,
1017 [ C(RESULT_MISS) ] = -1,
1018 },
1019 },
1020 [ C(NODE) ] = {
1021 [ C(OP_READ) ] = {
1022 [ C(RESULT_ACCESS) ] = 0x01b7,
1023 [ C(RESULT_MISS) ] = 0x01b7,
1024 },
1025 [ C(OP_WRITE) ] = {
1026 [ C(RESULT_ACCESS) ] = 0x01b7,
1027 [ C(RESULT_MISS) ] = 0x01b7,
1028 },
1029 [ C(OP_PREFETCH) ] = {
1030 [ C(RESULT_ACCESS) ] = 0x01b7,
1031 [ C(RESULT_MISS) ] = 0x01b7,
1032 },
1033 },
1034
1035 };
1036
1037 /*
1038 * Notes on the events:
1039 * - data reads do not include code reads (comparable to earlier tables)
1040 * - data counts include speculative execution (except L1 write, dtlb, bpu)
1041 * - remote node access includes remote memory, remote cache, remote mmio.
1042 * - prefetches are not included in the counts because they are not
1043 * reliably counted.
1044 */
1045
1046 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
1047 #define HSW_DEMAND_RFO BIT_ULL(1)
1048 #define HSW_ANY_RESPONSE BIT_ULL(16)
1049 #define HSW_SUPPLIER_NONE BIT_ULL(17)
1050 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
1051 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
1052 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
1053 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
1054 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
1055 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1056 HSW_L3_MISS_REMOTE_HOP2P)
1057 #define HSW_SNOOP_NONE BIT_ULL(31)
1058 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
1059 #define HSW_SNOOP_MISS BIT_ULL(33)
1060 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
1061 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
1062 #define HSW_SNOOP_HITM BIT_ULL(36)
1063 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
1064 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
1065 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
1066 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
1067 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
1068 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
1069 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
1070 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
1071 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
1072 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
1073 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
1074
1075 #define BDW_L3_MISS_LOCAL BIT(26)
1076 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
1077 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1078 HSW_L3_MISS_REMOTE_HOP2P)
1079
1080
1081 static __initconst const u64 hsw_hw_cache_event_ids
1082 [PERF_COUNT_HW_CACHE_MAX]
1083 [PERF_COUNT_HW_CACHE_OP_MAX]
1084 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1085 {
1086 [ C(L1D ) ] = {
1087 [ C(OP_READ) ] = {
1088 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1089 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1090 },
1091 [ C(OP_WRITE) ] = {
1092 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1093 [ C(RESULT_MISS) ] = 0x0,
1094 },
1095 [ C(OP_PREFETCH) ] = {
1096 [ C(RESULT_ACCESS) ] = 0x0,
1097 [ C(RESULT_MISS) ] = 0x0,
1098 },
1099 },
1100 [ C(L1I ) ] = {
1101 [ C(OP_READ) ] = {
1102 [ C(RESULT_ACCESS) ] = 0x0,
1103 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1104 },
1105 [ C(OP_WRITE) ] = {
1106 [ C(RESULT_ACCESS) ] = -1,
1107 [ C(RESULT_MISS) ] = -1,
1108 },
1109 [ C(OP_PREFETCH) ] = {
1110 [ C(RESULT_ACCESS) ] = 0x0,
1111 [ C(RESULT_MISS) ] = 0x0,
1112 },
1113 },
1114 [ C(LL ) ] = {
1115 [ C(OP_READ) ] = {
1116 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1117 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1118 },
1119 [ C(OP_WRITE) ] = {
1120 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1121 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1122 },
1123 [ C(OP_PREFETCH) ] = {
1124 [ C(RESULT_ACCESS) ] = 0x0,
1125 [ C(RESULT_MISS) ] = 0x0,
1126 },
1127 },
1128 [ C(DTLB) ] = {
1129 [ C(OP_READ) ] = {
1130 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1131 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1132 },
1133 [ C(OP_WRITE) ] = {
1134 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1135 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1136 },
1137 [ C(OP_PREFETCH) ] = {
1138 [ C(RESULT_ACCESS) ] = 0x0,
1139 [ C(RESULT_MISS) ] = 0x0,
1140 },
1141 },
1142 [ C(ITLB) ] = {
1143 [ C(OP_READ) ] = {
1144 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1145 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1146 },
1147 [ C(OP_WRITE) ] = {
1148 [ C(RESULT_ACCESS) ] = -1,
1149 [ C(RESULT_MISS) ] = -1,
1150 },
1151 [ C(OP_PREFETCH) ] = {
1152 [ C(RESULT_ACCESS) ] = -1,
1153 [ C(RESULT_MISS) ] = -1,
1154 },
1155 },
1156 [ C(BPU ) ] = {
1157 [ C(OP_READ) ] = {
1158 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1159 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1160 },
1161 [ C(OP_WRITE) ] = {
1162 [ C(RESULT_ACCESS) ] = -1,
1163 [ C(RESULT_MISS) ] = -1,
1164 },
1165 [ C(OP_PREFETCH) ] = {
1166 [ C(RESULT_ACCESS) ] = -1,
1167 [ C(RESULT_MISS) ] = -1,
1168 },
1169 },
1170 [ C(NODE) ] = {
1171 [ C(OP_READ) ] = {
1172 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1173 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1174 },
1175 [ C(OP_WRITE) ] = {
1176 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1177 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1178 },
1179 [ C(OP_PREFETCH) ] = {
1180 [ C(RESULT_ACCESS) ] = 0x0,
1181 [ C(RESULT_MISS) ] = 0x0,
1182 },
1183 },
1184 };
1185
1186 static __initconst const u64 hsw_hw_cache_extra_regs
1187 [PERF_COUNT_HW_CACHE_MAX]
1188 [PERF_COUNT_HW_CACHE_OP_MAX]
1189 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1190 {
1191 [ C(LL ) ] = {
1192 [ C(OP_READ) ] = {
1193 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1194 HSW_LLC_ACCESS,
1195 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1196 HSW_L3_MISS|HSW_ANY_SNOOP,
1197 },
1198 [ C(OP_WRITE) ] = {
1199 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1200 HSW_LLC_ACCESS,
1201 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1202 HSW_L3_MISS|HSW_ANY_SNOOP,
1203 },
1204 [ C(OP_PREFETCH) ] = {
1205 [ C(RESULT_ACCESS) ] = 0x0,
1206 [ C(RESULT_MISS) ] = 0x0,
1207 },
1208 },
1209 [ C(NODE) ] = {
1210 [ C(OP_READ) ] = {
1211 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1212 HSW_L3_MISS_LOCAL_DRAM|
1213 HSW_SNOOP_DRAM,
1214 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1215 HSW_L3_MISS_REMOTE|
1216 HSW_SNOOP_DRAM,
1217 },
1218 [ C(OP_WRITE) ] = {
1219 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1220 HSW_L3_MISS_LOCAL_DRAM|
1221 HSW_SNOOP_DRAM,
1222 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1223 HSW_L3_MISS_REMOTE|
1224 HSW_SNOOP_DRAM,
1225 },
1226 [ C(OP_PREFETCH) ] = {
1227 [ C(RESULT_ACCESS) ] = 0x0,
1228 [ C(RESULT_MISS) ] = 0x0,
1229 },
1230 },
1231 };
1232
1233 static __initconst const u64 westmere_hw_cache_event_ids
1234 [PERF_COUNT_HW_CACHE_MAX]
1235 [PERF_COUNT_HW_CACHE_OP_MAX]
1236 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1237 {
1238 [ C(L1D) ] = {
1239 [ C(OP_READ) ] = {
1240 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1241 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1242 },
1243 [ C(OP_WRITE) ] = {
1244 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1245 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1246 },
1247 [ C(OP_PREFETCH) ] = {
1248 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1249 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1250 },
1251 },
1252 [ C(L1I ) ] = {
1253 [ C(OP_READ) ] = {
1254 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1255 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1256 },
1257 [ C(OP_WRITE) ] = {
1258 [ C(RESULT_ACCESS) ] = -1,
1259 [ C(RESULT_MISS) ] = -1,
1260 },
1261 [ C(OP_PREFETCH) ] = {
1262 [ C(RESULT_ACCESS) ] = 0x0,
1263 [ C(RESULT_MISS) ] = 0x0,
1264 },
1265 },
1266 [ C(LL ) ] = {
1267 [ C(OP_READ) ] = {
1268 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1269 [ C(RESULT_ACCESS) ] = 0x01b7,
1270 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1271 [ C(RESULT_MISS) ] = 0x01b7,
1272 },
1273 /*
1274 * Use RFO, not WRITEBACK, because a write miss would typically occur
1275 * on RFO.
1276 */
1277 [ C(OP_WRITE) ] = {
1278 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1279 [ C(RESULT_ACCESS) ] = 0x01b7,
1280 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1281 [ C(RESULT_MISS) ] = 0x01b7,
1282 },
1283 [ C(OP_PREFETCH) ] = {
1284 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1285 [ C(RESULT_ACCESS) ] = 0x01b7,
1286 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1287 [ C(RESULT_MISS) ] = 0x01b7,
1288 },
1289 },
1290 [ C(DTLB) ] = {
1291 [ C(OP_READ) ] = {
1292 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1293 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1294 },
1295 [ C(OP_WRITE) ] = {
1296 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1297 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1298 },
1299 [ C(OP_PREFETCH) ] = {
1300 [ C(RESULT_ACCESS) ] = 0x0,
1301 [ C(RESULT_MISS) ] = 0x0,
1302 },
1303 },
1304 [ C(ITLB) ] = {
1305 [ C(OP_READ) ] = {
1306 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1307 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1308 },
1309 [ C(OP_WRITE) ] = {
1310 [ C(RESULT_ACCESS) ] = -1,
1311 [ C(RESULT_MISS) ] = -1,
1312 },
1313 [ C(OP_PREFETCH) ] = {
1314 [ C(RESULT_ACCESS) ] = -1,
1315 [ C(RESULT_MISS) ] = -1,
1316 },
1317 },
1318 [ C(BPU ) ] = {
1319 [ C(OP_READ) ] = {
1320 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1321 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1322 },
1323 [ C(OP_WRITE) ] = {
1324 [ C(RESULT_ACCESS) ] = -1,
1325 [ C(RESULT_MISS) ] = -1,
1326 },
1327 [ C(OP_PREFETCH) ] = {
1328 [ C(RESULT_ACCESS) ] = -1,
1329 [ C(RESULT_MISS) ] = -1,
1330 },
1331 },
1332 [ C(NODE) ] = {
1333 [ C(OP_READ) ] = {
1334 [ C(RESULT_ACCESS) ] = 0x01b7,
1335 [ C(RESULT_MISS) ] = 0x01b7,
1336 },
1337 [ C(OP_WRITE) ] = {
1338 [ C(RESULT_ACCESS) ] = 0x01b7,
1339 [ C(RESULT_MISS) ] = 0x01b7,
1340 },
1341 [ C(OP_PREFETCH) ] = {
1342 [ C(RESULT_ACCESS) ] = 0x01b7,
1343 [ C(RESULT_MISS) ] = 0x01b7,
1344 },
1345 },
1346 };
1347
1348 /*
1349 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1350 * See IA32 SDM Vol 3B 30.6.1.3
1351 */
1352
1353 #define NHM_DMND_DATA_RD (1 << 0)
1354 #define NHM_DMND_RFO (1 << 1)
1355 #define NHM_DMND_IFETCH (1 << 2)
1356 #define NHM_DMND_WB (1 << 3)
1357 #define NHM_PF_DATA_RD (1 << 4)
1358 #define NHM_PF_DATA_RFO (1 << 5)
1359 #define NHM_PF_IFETCH (1 << 6)
1360 #define NHM_OFFCORE_OTHER (1 << 7)
1361 #define NHM_UNCORE_HIT (1 << 8)
1362 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1363 #define NHM_OTHER_CORE_HITM (1 << 10)
1364 /* reserved */
1365 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1366 #define NHM_REMOTE_DRAM (1 << 13)
1367 #define NHM_LOCAL_DRAM (1 << 14)
1368 #define NHM_NON_DRAM (1 << 15)
1369
1370 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1371 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1372
1373 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1374 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1375 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1376
1377 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1378 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1379 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1380
1381 static __initconst const u64 nehalem_hw_cache_extra_regs
1382 [PERF_COUNT_HW_CACHE_MAX]
1383 [PERF_COUNT_HW_CACHE_OP_MAX]
1384 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1385 {
1386 [ C(LL ) ] = {
1387 [ C(OP_READ) ] = {
1388 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1389 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1390 },
1391 [ C(OP_WRITE) ] = {
1392 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1393 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1394 },
1395 [ C(OP_PREFETCH) ] = {
1396 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1397 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1398 },
1399 },
1400 [ C(NODE) ] = {
1401 [ C(OP_READ) ] = {
1402 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1403 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1404 },
1405 [ C(OP_WRITE) ] = {
1406 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1407 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1408 },
1409 [ C(OP_PREFETCH) ] = {
1410 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1411 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1412 },
1413 },
1414 };
1415
1416 static __initconst const u64 nehalem_hw_cache_event_ids
1417 [PERF_COUNT_HW_CACHE_MAX]
1418 [PERF_COUNT_HW_CACHE_OP_MAX]
1419 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1420 {
1421 [ C(L1D) ] = {
1422 [ C(OP_READ) ] = {
1423 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1424 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1425 },
1426 [ C(OP_WRITE) ] = {
1427 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1428 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1429 },
1430 [ C(OP_PREFETCH) ] = {
1431 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1432 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1433 },
1434 },
1435 [ C(L1I ) ] = {
1436 [ C(OP_READ) ] = {
1437 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1438 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1439 },
1440 [ C(OP_WRITE) ] = {
1441 [ C(RESULT_ACCESS) ] = -1,
1442 [ C(RESULT_MISS) ] = -1,
1443 },
1444 [ C(OP_PREFETCH) ] = {
1445 [ C(RESULT_ACCESS) ] = 0x0,
1446 [ C(RESULT_MISS) ] = 0x0,
1447 },
1448 },
1449 [ C(LL ) ] = {
1450 [ C(OP_READ) ] = {
1451 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1452 [ C(RESULT_ACCESS) ] = 0x01b7,
1453 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1454 [ C(RESULT_MISS) ] = 0x01b7,
1455 },
1456 /*
1457 * Use RFO, not WRITEBACK, because a write miss would typically occur
1458 * on RFO.
1459 */
1460 [ C(OP_WRITE) ] = {
1461 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1462 [ C(RESULT_ACCESS) ] = 0x01b7,
1463 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1464 [ C(RESULT_MISS) ] = 0x01b7,
1465 },
1466 [ C(OP_PREFETCH) ] = {
1467 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1468 [ C(RESULT_ACCESS) ] = 0x01b7,
1469 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1470 [ C(RESULT_MISS) ] = 0x01b7,
1471 },
1472 },
1473 [ C(DTLB) ] = {
1474 [ C(OP_READ) ] = {
1475 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1476 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1477 },
1478 [ C(OP_WRITE) ] = {
1479 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1480 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1481 },
1482 [ C(OP_PREFETCH) ] = {
1483 [ C(RESULT_ACCESS) ] = 0x0,
1484 [ C(RESULT_MISS) ] = 0x0,
1485 },
1486 },
1487 [ C(ITLB) ] = {
1488 [ C(OP_READ) ] = {
1489 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1490 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1491 },
1492 [ C(OP_WRITE) ] = {
1493 [ C(RESULT_ACCESS) ] = -1,
1494 [ C(RESULT_MISS) ] = -1,
1495 },
1496 [ C(OP_PREFETCH) ] = {
1497 [ C(RESULT_ACCESS) ] = -1,
1498 [ C(RESULT_MISS) ] = -1,
1499 },
1500 },
1501 [ C(BPU ) ] = {
1502 [ C(OP_READ) ] = {
1503 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1504 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1505 },
1506 [ C(OP_WRITE) ] = {
1507 [ C(RESULT_ACCESS) ] = -1,
1508 [ C(RESULT_MISS) ] = -1,
1509 },
1510 [ C(OP_PREFETCH) ] = {
1511 [ C(RESULT_ACCESS) ] = -1,
1512 [ C(RESULT_MISS) ] = -1,
1513 },
1514 },
1515 [ C(NODE) ] = {
1516 [ C(OP_READ) ] = {
1517 [ C(RESULT_ACCESS) ] = 0x01b7,
1518 [ C(RESULT_MISS) ] = 0x01b7,
1519 },
1520 [ C(OP_WRITE) ] = {
1521 [ C(RESULT_ACCESS) ] = 0x01b7,
1522 [ C(RESULT_MISS) ] = 0x01b7,
1523 },
1524 [ C(OP_PREFETCH) ] = {
1525 [ C(RESULT_ACCESS) ] = 0x01b7,
1526 [ C(RESULT_MISS) ] = 0x01b7,
1527 },
1528 },
1529 };
1530
1531 static __initconst const u64 core2_hw_cache_event_ids
1532 [PERF_COUNT_HW_CACHE_MAX]
1533 [PERF_COUNT_HW_CACHE_OP_MAX]
1534 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1535 {
1536 [ C(L1D) ] = {
1537 [ C(OP_READ) ] = {
1538 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1539 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1540 },
1541 [ C(OP_WRITE) ] = {
1542 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1543 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1544 },
1545 [ C(OP_PREFETCH) ] = {
1546 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1547 [ C(RESULT_MISS) ] = 0,
1548 },
1549 },
1550 [ C(L1I ) ] = {
1551 [ C(OP_READ) ] = {
1552 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1553 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1554 },
1555 [ C(OP_WRITE) ] = {
1556 [ C(RESULT_ACCESS) ] = -1,
1557 [ C(RESULT_MISS) ] = -1,
1558 },
1559 [ C(OP_PREFETCH) ] = {
1560 [ C(RESULT_ACCESS) ] = 0,
1561 [ C(RESULT_MISS) ] = 0,
1562 },
1563 },
1564 [ C(LL ) ] = {
1565 [ C(OP_READ) ] = {
1566 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1567 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1568 },
1569 [ C(OP_WRITE) ] = {
1570 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1571 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1572 },
1573 [ C(OP_PREFETCH) ] = {
1574 [ C(RESULT_ACCESS) ] = 0,
1575 [ C(RESULT_MISS) ] = 0,
1576 },
1577 },
1578 [ C(DTLB) ] = {
1579 [ C(OP_READ) ] = {
1580 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1581 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1582 },
1583 [ C(OP_WRITE) ] = {
1584 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1585 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1586 },
1587 [ C(OP_PREFETCH) ] = {
1588 [ C(RESULT_ACCESS) ] = 0,
1589 [ C(RESULT_MISS) ] = 0,
1590 },
1591 },
1592 [ C(ITLB) ] = {
1593 [ C(OP_READ) ] = {
1594 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1595 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1596 },
1597 [ C(OP_WRITE) ] = {
1598 [ C(RESULT_ACCESS) ] = -1,
1599 [ C(RESULT_MISS) ] = -1,
1600 },
1601 [ C(OP_PREFETCH) ] = {
1602 [ C(RESULT_ACCESS) ] = -1,
1603 [ C(RESULT_MISS) ] = -1,
1604 },
1605 },
1606 [ C(BPU ) ] = {
1607 [ C(OP_READ) ] = {
1608 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1609 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1610 },
1611 [ C(OP_WRITE) ] = {
1612 [ C(RESULT_ACCESS) ] = -1,
1613 [ C(RESULT_MISS) ] = -1,
1614 },
1615 [ C(OP_PREFETCH) ] = {
1616 [ C(RESULT_ACCESS) ] = -1,
1617 [ C(RESULT_MISS) ] = -1,
1618 },
1619 },
1620 };
1621
1622 static __initconst const u64 atom_hw_cache_event_ids
1623 [PERF_COUNT_HW_CACHE_MAX]
1624 [PERF_COUNT_HW_CACHE_OP_MAX]
1625 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1626 {
1627 [ C(L1D) ] = {
1628 [ C(OP_READ) ] = {
1629 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1630 [ C(RESULT_MISS) ] = 0,
1631 },
1632 [ C(OP_WRITE) ] = {
1633 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1634 [ C(RESULT_MISS) ] = 0,
1635 },
1636 [ C(OP_PREFETCH) ] = {
1637 [ C(RESULT_ACCESS) ] = 0x0,
1638 [ C(RESULT_MISS) ] = 0,
1639 },
1640 },
1641 [ C(L1I ) ] = {
1642 [ C(OP_READ) ] = {
1643 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1644 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1645 },
1646 [ C(OP_WRITE) ] = {
1647 [ C(RESULT_ACCESS) ] = -1,
1648 [ C(RESULT_MISS) ] = -1,
1649 },
1650 [ C(OP_PREFETCH) ] = {
1651 [ C(RESULT_ACCESS) ] = 0,
1652 [ C(RESULT_MISS) ] = 0,
1653 },
1654 },
1655 [ C(LL ) ] = {
1656 [ C(OP_READ) ] = {
1657 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1658 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1659 },
1660 [ C(OP_WRITE) ] = {
1661 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1662 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1663 },
1664 [ C(OP_PREFETCH) ] = {
1665 [ C(RESULT_ACCESS) ] = 0,
1666 [ C(RESULT_MISS) ] = 0,
1667 },
1668 },
1669 [ C(DTLB) ] = {
1670 [ C(OP_READ) ] = {
1671 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1672 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1673 },
1674 [ C(OP_WRITE) ] = {
1675 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1676 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1677 },
1678 [ C(OP_PREFETCH) ] = {
1679 [ C(RESULT_ACCESS) ] = 0,
1680 [ C(RESULT_MISS) ] = 0,
1681 },
1682 },
1683 [ C(ITLB) ] = {
1684 [ C(OP_READ) ] = {
1685 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1686 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1687 },
1688 [ C(OP_WRITE) ] = {
1689 [ C(RESULT_ACCESS) ] = -1,
1690 [ C(RESULT_MISS) ] = -1,
1691 },
1692 [ C(OP_PREFETCH) ] = {
1693 [ C(RESULT_ACCESS) ] = -1,
1694 [ C(RESULT_MISS) ] = -1,
1695 },
1696 },
1697 [ C(BPU ) ] = {
1698 [ C(OP_READ) ] = {
1699 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1700 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1701 },
1702 [ C(OP_WRITE) ] = {
1703 [ C(RESULT_ACCESS) ] = -1,
1704 [ C(RESULT_MISS) ] = -1,
1705 },
1706 [ C(OP_PREFETCH) ] = {
1707 [ C(RESULT_ACCESS) ] = -1,
1708 [ C(RESULT_MISS) ] = -1,
1709 },
1710 },
1711 };
1712
1713 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1714 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1715 /* no_alloc_cycles.not_delivered */
1716 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1717 "event=0xca,umask=0x50");
1718 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1719 /* uops_retired.all */
1720 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1721 "event=0xc2,umask=0x10");
1722 /* uops_retired.all */
1723 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1724 "event=0xc2,umask=0x10");
1725
1726 static struct attribute *slm_events_attrs[] = {
1727 EVENT_PTR(td_total_slots_slm),
1728 EVENT_PTR(td_total_slots_scale_slm),
1729 EVENT_PTR(td_fetch_bubbles_slm),
1730 EVENT_PTR(td_fetch_bubbles_scale_slm),
1731 EVENT_PTR(td_slots_issued_slm),
1732 EVENT_PTR(td_slots_retired_slm),
1733 NULL
1734 };
1735
1736 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1737 {
1738 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1739 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1740 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1741 EVENT_EXTRA_END
1742 };
1743
1744 #define SLM_DMND_READ SNB_DMND_DATA_RD
1745 #define SLM_DMND_WRITE SNB_DMND_RFO
1746 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1747
1748 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1749 #define SLM_LLC_ACCESS SNB_RESP_ANY
1750 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1751
1752 static __initconst const u64 slm_hw_cache_extra_regs
1753 [PERF_COUNT_HW_CACHE_MAX]
1754 [PERF_COUNT_HW_CACHE_OP_MAX]
1755 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1756 {
1757 [ C(LL ) ] = {
1758 [ C(OP_READ) ] = {
1759 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1760 [ C(RESULT_MISS) ] = 0,
1761 },
1762 [ C(OP_WRITE) ] = {
1763 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1764 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1765 },
1766 [ C(OP_PREFETCH) ] = {
1767 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1768 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1769 },
1770 },
1771 };
1772
1773 static __initconst const u64 slm_hw_cache_event_ids
1774 [PERF_COUNT_HW_CACHE_MAX]
1775 [PERF_COUNT_HW_CACHE_OP_MAX]
1776 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1777 {
1778 [ C(L1D) ] = {
1779 [ C(OP_READ) ] = {
1780 [ C(RESULT_ACCESS) ] = 0,
1781 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1782 },
1783 [ C(OP_WRITE) ] = {
1784 [ C(RESULT_ACCESS) ] = 0,
1785 [ C(RESULT_MISS) ] = 0,
1786 },
1787 [ C(OP_PREFETCH) ] = {
1788 [ C(RESULT_ACCESS) ] = 0,
1789 [ C(RESULT_MISS) ] = 0,
1790 },
1791 },
1792 [ C(L1I ) ] = {
1793 [ C(OP_READ) ] = {
1794 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1795 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1796 },
1797 [ C(OP_WRITE) ] = {
1798 [ C(RESULT_ACCESS) ] = -1,
1799 [ C(RESULT_MISS) ] = -1,
1800 },
1801 [ C(OP_PREFETCH) ] = {
1802 [ C(RESULT_ACCESS) ] = 0,
1803 [ C(RESULT_MISS) ] = 0,
1804 },
1805 },
1806 [ C(LL ) ] = {
1807 [ C(OP_READ) ] = {
1808 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1809 [ C(RESULT_ACCESS) ] = 0x01b7,
1810 [ C(RESULT_MISS) ] = 0,
1811 },
1812 [ C(OP_WRITE) ] = {
1813 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1814 [ C(RESULT_ACCESS) ] = 0x01b7,
1815 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1816 [ C(RESULT_MISS) ] = 0x01b7,
1817 },
1818 [ C(OP_PREFETCH) ] = {
1819 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1820 [ C(RESULT_ACCESS) ] = 0x01b7,
1821 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1822 [ C(RESULT_MISS) ] = 0x01b7,
1823 },
1824 },
1825 [ C(DTLB) ] = {
1826 [ C(OP_READ) ] = {
1827 [ C(RESULT_ACCESS) ] = 0,
1828 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1829 },
1830 [ C(OP_WRITE) ] = {
1831 [ C(RESULT_ACCESS) ] = 0,
1832 [ C(RESULT_MISS) ] = 0,
1833 },
1834 [ C(OP_PREFETCH) ] = {
1835 [ C(RESULT_ACCESS) ] = 0,
1836 [ C(RESULT_MISS) ] = 0,
1837 },
1838 },
1839 [ C(ITLB) ] = {
1840 [ C(OP_READ) ] = {
1841 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1842 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1843 },
1844 [ C(OP_WRITE) ] = {
1845 [ C(RESULT_ACCESS) ] = -1,
1846 [ C(RESULT_MISS) ] = -1,
1847 },
1848 [ C(OP_PREFETCH) ] = {
1849 [ C(RESULT_ACCESS) ] = -1,
1850 [ C(RESULT_MISS) ] = -1,
1851 },
1852 },
1853 [ C(BPU ) ] = {
1854 [ C(OP_READ) ] = {
1855 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1856 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1857 },
1858 [ C(OP_WRITE) ] = {
1859 [ C(RESULT_ACCESS) ] = -1,
1860 [ C(RESULT_MISS) ] = -1,
1861 },
1862 [ C(OP_PREFETCH) ] = {
1863 [ C(RESULT_ACCESS) ] = -1,
1864 [ C(RESULT_MISS) ] = -1,
1865 },
1866 },
1867 };
1868
1869 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1870 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1871 /* UOPS_NOT_DELIVERED.ANY */
1872 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1873 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1874 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1875 /* UOPS_RETIRED.ANY */
1876 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1877 /* UOPS_ISSUED.ANY */
1878 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1879
1880 static struct attribute *glm_events_attrs[] = {
1881 EVENT_PTR(td_total_slots_glm),
1882 EVENT_PTR(td_total_slots_scale_glm),
1883 EVENT_PTR(td_fetch_bubbles_glm),
1884 EVENT_PTR(td_recovery_bubbles_glm),
1885 EVENT_PTR(td_slots_issued_glm),
1886 EVENT_PTR(td_slots_retired_glm),
1887 NULL
1888 };
1889
1890 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1891 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1892 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1893 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1894 EVENT_EXTRA_END
1895 };
1896
1897 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1898 #define GLM_DEMAND_RFO BIT_ULL(1)
1899 #define GLM_ANY_RESPONSE BIT_ULL(16)
1900 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1901 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1902 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1903 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1904 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1905 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1906 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1907
1908 static __initconst const u64 glm_hw_cache_event_ids
1909 [PERF_COUNT_HW_CACHE_MAX]
1910 [PERF_COUNT_HW_CACHE_OP_MAX]
1911 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1912 [C(L1D)] = {
1913 [C(OP_READ)] = {
1914 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1915 [C(RESULT_MISS)] = 0x0,
1916 },
1917 [C(OP_WRITE)] = {
1918 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1919 [C(RESULT_MISS)] = 0x0,
1920 },
1921 [C(OP_PREFETCH)] = {
1922 [C(RESULT_ACCESS)] = 0x0,
1923 [C(RESULT_MISS)] = 0x0,
1924 },
1925 },
1926 [C(L1I)] = {
1927 [C(OP_READ)] = {
1928 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1929 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1930 },
1931 [C(OP_WRITE)] = {
1932 [C(RESULT_ACCESS)] = -1,
1933 [C(RESULT_MISS)] = -1,
1934 },
1935 [C(OP_PREFETCH)] = {
1936 [C(RESULT_ACCESS)] = 0x0,
1937 [C(RESULT_MISS)] = 0x0,
1938 },
1939 },
1940 [C(LL)] = {
1941 [C(OP_READ)] = {
1942 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1943 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1944 },
1945 [C(OP_WRITE)] = {
1946 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1947 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1948 },
1949 [C(OP_PREFETCH)] = {
1950 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1951 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1952 },
1953 },
1954 [C(DTLB)] = {
1955 [C(OP_READ)] = {
1956 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1957 [C(RESULT_MISS)] = 0x0,
1958 },
1959 [C(OP_WRITE)] = {
1960 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1961 [C(RESULT_MISS)] = 0x0,
1962 },
1963 [C(OP_PREFETCH)] = {
1964 [C(RESULT_ACCESS)] = 0x0,
1965 [C(RESULT_MISS)] = 0x0,
1966 },
1967 },
1968 [C(ITLB)] = {
1969 [C(OP_READ)] = {
1970 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1971 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1972 },
1973 [C(OP_WRITE)] = {
1974 [C(RESULT_ACCESS)] = -1,
1975 [C(RESULT_MISS)] = -1,
1976 },
1977 [C(OP_PREFETCH)] = {
1978 [C(RESULT_ACCESS)] = -1,
1979 [C(RESULT_MISS)] = -1,
1980 },
1981 },
1982 [C(BPU)] = {
1983 [C(OP_READ)] = {
1984 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1985 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1986 },
1987 [C(OP_WRITE)] = {
1988 [C(RESULT_ACCESS)] = -1,
1989 [C(RESULT_MISS)] = -1,
1990 },
1991 [C(OP_PREFETCH)] = {
1992 [C(RESULT_ACCESS)] = -1,
1993 [C(RESULT_MISS)] = -1,
1994 },
1995 },
1996 };
1997
1998 static __initconst const u64 glm_hw_cache_extra_regs
1999 [PERF_COUNT_HW_CACHE_MAX]
2000 [PERF_COUNT_HW_CACHE_OP_MAX]
2001 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2002 [C(LL)] = {
2003 [C(OP_READ)] = {
2004 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2005 GLM_LLC_ACCESS,
2006 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2007 GLM_LLC_MISS,
2008 },
2009 [C(OP_WRITE)] = {
2010 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2011 GLM_LLC_ACCESS,
2012 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2013 GLM_LLC_MISS,
2014 },
2015 [C(OP_PREFETCH)] = {
2016 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
2017 GLM_LLC_ACCESS,
2018 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
2019 GLM_LLC_MISS,
2020 },
2021 },
2022 };
2023
2024 static __initconst const u64 glp_hw_cache_event_ids
2025 [PERF_COUNT_HW_CACHE_MAX]
2026 [PERF_COUNT_HW_CACHE_OP_MAX]
2027 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2028 [C(L1D)] = {
2029 [C(OP_READ)] = {
2030 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2031 [C(RESULT_MISS)] = 0x0,
2032 },
2033 [C(OP_WRITE)] = {
2034 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2035 [C(RESULT_MISS)] = 0x0,
2036 },
2037 [C(OP_PREFETCH)] = {
2038 [C(RESULT_ACCESS)] = 0x0,
2039 [C(RESULT_MISS)] = 0x0,
2040 },
2041 },
2042 [C(L1I)] = {
2043 [C(OP_READ)] = {
2044 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
2045 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
2046 },
2047 [C(OP_WRITE)] = {
2048 [C(RESULT_ACCESS)] = -1,
2049 [C(RESULT_MISS)] = -1,
2050 },
2051 [C(OP_PREFETCH)] = {
2052 [C(RESULT_ACCESS)] = 0x0,
2053 [C(RESULT_MISS)] = 0x0,
2054 },
2055 },
2056 [C(LL)] = {
2057 [C(OP_READ)] = {
2058 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2059 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2060 },
2061 [C(OP_WRITE)] = {
2062 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2063 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2064 },
2065 [C(OP_PREFETCH)] = {
2066 [C(RESULT_ACCESS)] = 0x0,
2067 [C(RESULT_MISS)] = 0x0,
2068 },
2069 },
2070 [C(DTLB)] = {
2071 [C(OP_READ)] = {
2072 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2073 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
2074 },
2075 [C(OP_WRITE)] = {
2076 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2077 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
2078 },
2079 [C(OP_PREFETCH)] = {
2080 [C(RESULT_ACCESS)] = 0x0,
2081 [C(RESULT_MISS)] = 0x0,
2082 },
2083 },
2084 [C(ITLB)] = {
2085 [C(OP_READ)] = {
2086 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2087 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2088 },
2089 [C(OP_WRITE)] = {
2090 [C(RESULT_ACCESS)] = -1,
2091 [C(RESULT_MISS)] = -1,
2092 },
2093 [C(OP_PREFETCH)] = {
2094 [C(RESULT_ACCESS)] = -1,
2095 [C(RESULT_MISS)] = -1,
2096 },
2097 },
2098 [C(BPU)] = {
2099 [C(OP_READ)] = {
2100 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2101 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2102 },
2103 [C(OP_WRITE)] = {
2104 [C(RESULT_ACCESS)] = -1,
2105 [C(RESULT_MISS)] = -1,
2106 },
2107 [C(OP_PREFETCH)] = {
2108 [C(RESULT_ACCESS)] = -1,
2109 [C(RESULT_MISS)] = -1,
2110 },
2111 },
2112 };
2113
2114 static __initconst const u64 glp_hw_cache_extra_regs
2115 [PERF_COUNT_HW_CACHE_MAX]
2116 [PERF_COUNT_HW_CACHE_OP_MAX]
2117 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2118 [C(LL)] = {
2119 [C(OP_READ)] = {
2120 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2121 GLM_LLC_ACCESS,
2122 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2123 GLM_LLC_MISS,
2124 },
2125 [C(OP_WRITE)] = {
2126 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2127 GLM_LLC_ACCESS,
2128 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2129 GLM_LLC_MISS,
2130 },
2131 [C(OP_PREFETCH)] = {
2132 [C(RESULT_ACCESS)] = 0x0,
2133 [C(RESULT_MISS)] = 0x0,
2134 },
2135 },
2136 };
2137
2138 #define TNT_LOCAL_DRAM BIT_ULL(26)
2139 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
2140 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
2141 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
2142 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2143 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2144 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2145
2146 static __initconst const u64 tnt_hw_cache_extra_regs
2147 [PERF_COUNT_HW_CACHE_MAX]
2148 [PERF_COUNT_HW_CACHE_OP_MAX]
2149 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2150 [C(LL)] = {
2151 [C(OP_READ)] = {
2152 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2153 TNT_LLC_ACCESS,
2154 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2155 TNT_LLC_MISS,
2156 },
2157 [C(OP_WRITE)] = {
2158 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2159 TNT_LLC_ACCESS,
2160 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2161 TNT_LLC_MISS,
2162 },
2163 [C(OP_PREFETCH)] = {
2164 [C(RESULT_ACCESS)] = 0x0,
2165 [C(RESULT_MISS)] = 0x0,
2166 },
2167 },
2168 };
2169
2170 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
2171 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
2172 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
2173 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0");
2174
2175 static struct attribute *tnt_events_attrs[] = {
2176 EVENT_PTR(td_fe_bound_tnt),
2177 EVENT_PTR(td_retiring_tnt),
2178 EVENT_PTR(td_bad_spec_tnt),
2179 EVENT_PTR(td_be_bound_tnt),
2180 NULL,
2181 };
2182
2183 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2184 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2185 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2186 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2187 EVENT_EXTRA_END
2188 };
2189
2190 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3");
2191 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6");
2192
2193 static struct attribute *grt_mem_attrs[] = {
2194 EVENT_PTR(mem_ld_grt),
2195 EVENT_PTR(mem_st_grt),
2196 NULL
2197 };
2198
2199 static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2200 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2201 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
2202 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
2203 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2204 EVENT_EXTRA_END
2205 };
2206
2207 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0");
2208 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0");
2209
2210 static struct attribute *cmt_events_attrs[] = {
2211 EVENT_PTR(td_fe_bound_tnt),
2212 EVENT_PTR(td_retiring_cmt),
2213 EVENT_PTR(td_bad_spec_cmt),
2214 EVENT_PTR(td_be_bound_tnt),
2215 NULL
2216 };
2217
2218 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
2219 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2220 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0),
2221 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1),
2222 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2223 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2224 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2225 EVENT_EXTRA_END
2226 };
2227
2228 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_skt, "event=0x9c,umask=0x01");
2229 EVENT_ATTR_STR(topdown-retiring, td_retiring_skt, "event=0xc2,umask=0x02");
2230 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_skt, "event=0xa4,umask=0x02");
2231
2232 static struct attribute *skt_events_attrs[] = {
2233 EVENT_PTR(td_fe_bound_skt),
2234 EVENT_PTR(td_retiring_skt),
2235 EVENT_PTR(td_bad_spec_cmt),
2236 EVENT_PTR(td_be_bound_skt),
2237 NULL,
2238 };
2239
2240 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
2241 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
2242 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
2243 #define KNL_MCDRAM_FAR BIT_ULL(22)
2244 #define KNL_DDR_LOCAL BIT_ULL(23)
2245 #define KNL_DDR_FAR BIT_ULL(24)
2246 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2247 KNL_DDR_LOCAL | KNL_DDR_FAR)
2248 #define KNL_L2_READ SLM_DMND_READ
2249 #define KNL_L2_WRITE SLM_DMND_WRITE
2250 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
2251 #define KNL_L2_ACCESS SLM_LLC_ACCESS
2252 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2253 KNL_DRAM_ANY | SNB_SNP_ANY | \
2254 SNB_NON_DRAM)
2255
2256 static __initconst const u64 knl_hw_cache_extra_regs
2257 [PERF_COUNT_HW_CACHE_MAX]
2258 [PERF_COUNT_HW_CACHE_OP_MAX]
2259 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2260 [C(LL)] = {
2261 [C(OP_READ)] = {
2262 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2263 [C(RESULT_MISS)] = 0,
2264 },
2265 [C(OP_WRITE)] = {
2266 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2267 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2268 },
2269 [C(OP_PREFETCH)] = {
2270 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2271 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2272 },
2273 },
2274 };
2275
2276 /*
2277 * Used from PMIs where the LBRs are already disabled.
2278 *
2279 * This function could be called consecutively. It is required to remain in
2280 * disabled state if called consecutively.
2281 *
2282 * During consecutive calls, the same disable value will be written to related
2283 * registers, so the PMU state remains unchanged.
2284 *
2285 * intel_bts events don't coexist with intel PMU's BTS events because of
2286 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2287 * disabled around intel PMU's event batching etc, only inside the PMI handler.
2288 *
2289 * Avoid PEBS_ENABLE MSR access in PMIs.
2290 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2291 * It doesn't matter if the PEBS is enabled or not.
2292 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2293 * access PEBS_ENABLE MSR in disable_all()/enable_all().
2294 * However, there are some cases which may change PEBS status, e.g. PMI
2295 * throttle. The PEBS_ENABLE should be updated where the status changes.
2296 */
__intel_pmu_disable_all(bool bts)2297 static __always_inline void __intel_pmu_disable_all(bool bts)
2298 {
2299 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2300
2301 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2302
2303 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2304 intel_pmu_disable_bts();
2305 }
2306
intel_pmu_disable_all(void)2307 static __always_inline void intel_pmu_disable_all(void)
2308 {
2309 __intel_pmu_disable_all(true);
2310 static_call_cond(x86_pmu_pebs_disable_all)();
2311 intel_pmu_lbr_disable_all();
2312 }
2313
__intel_pmu_enable_all(int added,bool pmi)2314 static void __intel_pmu_enable_all(int added, bool pmi)
2315 {
2316 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2317 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2318
2319 intel_pmu_lbr_enable_all(pmi);
2320
2321 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) {
2322 wrmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val);
2323 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val;
2324 }
2325
2326 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL,
2327 intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2328
2329 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2330 struct perf_event *event =
2331 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2332
2333 if (WARN_ON_ONCE(!event))
2334 return;
2335
2336 intel_pmu_enable_bts(event->hw.config);
2337 }
2338 }
2339
intel_pmu_enable_all(int added)2340 static void intel_pmu_enable_all(int added)
2341 {
2342 static_call_cond(x86_pmu_pebs_enable_all)();
2343 __intel_pmu_enable_all(added, false);
2344 }
2345
2346 static noinline int
__intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt,unsigned long flags)2347 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries,
2348 unsigned int cnt, unsigned long flags)
2349 {
2350 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2351
2352 intel_pmu_lbr_read();
2353 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr);
2354
2355 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);
2356 intel_pmu_enable_all(0);
2357 local_irq_restore(flags);
2358 return cnt;
2359 }
2360
2361 static int
intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2362 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2363 {
2364 unsigned long flags;
2365
2366 /* must not have branches... */
2367 local_irq_save(flags);
2368 __intel_pmu_disable_all(false); /* we don't care about BTS */
2369 __intel_pmu_lbr_disable();
2370 /* ... until here */
2371 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2372 }
2373
2374 static int
intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2375 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2376 {
2377 unsigned long flags;
2378
2379 /* must not have branches... */
2380 local_irq_save(flags);
2381 __intel_pmu_disable_all(false); /* we don't care about BTS */
2382 __intel_pmu_arch_lbr_disable();
2383 /* ... until here */
2384 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2385 }
2386
2387 /*
2388 * Workaround for:
2389 * Intel Errata AAK100 (model 26)
2390 * Intel Errata AAP53 (model 30)
2391 * Intel Errata BD53 (model 44)
2392 *
2393 * The official story:
2394 * These chips need to be 'reset' when adding counters by programming the
2395 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2396 * in sequence on the same PMC or on different PMCs.
2397 *
2398 * In practice it appears some of these events do in fact count, and
2399 * we need to program all 4 events.
2400 */
intel_pmu_nhm_workaround(void)2401 static void intel_pmu_nhm_workaround(void)
2402 {
2403 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2404 static const unsigned long nhm_magic[4] = {
2405 0x4300B5,
2406 0x4300D2,
2407 0x4300B1,
2408 0x4300B1
2409 };
2410 struct perf_event *event;
2411 int i;
2412
2413 /*
2414 * The Errata requires below steps:
2415 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2416 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2417 * the corresponding PMCx;
2418 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2419 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2420 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2421 */
2422
2423 /*
2424 * The real steps we choose are a little different from above.
2425 * A) To reduce MSR operations, we don't run step 1) as they
2426 * are already cleared before this function is called;
2427 * B) Call x86_perf_event_update to save PMCx before configuring
2428 * PERFEVTSELx with magic number;
2429 * C) With step 5), we do clear only when the PERFEVTSELx is
2430 * not used currently.
2431 * D) Call x86_perf_event_set_period to restore PMCx;
2432 */
2433
2434 /* We always operate 4 pairs of PERF Counters */
2435 for (i = 0; i < 4; i++) {
2436 event = cpuc->events[i];
2437 if (event)
2438 static_call(x86_pmu_update)(event);
2439 }
2440
2441 for (i = 0; i < 4; i++) {
2442 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2443 wrmsrq(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2444 }
2445
2446 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2447 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2448
2449 for (i = 0; i < 4; i++) {
2450 event = cpuc->events[i];
2451
2452 if (event) {
2453 static_call(x86_pmu_set_period)(event);
2454 __x86_pmu_enable_event(&event->hw,
2455 ARCH_PERFMON_EVENTSEL_ENABLE);
2456 } else
2457 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2458 }
2459 }
2460
intel_pmu_nhm_enable_all(int added)2461 static void intel_pmu_nhm_enable_all(int added)
2462 {
2463 if (added)
2464 intel_pmu_nhm_workaround();
2465 intel_pmu_enable_all(added);
2466 }
2467
intel_set_tfa(struct cpu_hw_events * cpuc,bool on)2468 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2469 {
2470 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2471
2472 if (cpuc->tfa_shadow != val) {
2473 cpuc->tfa_shadow = val;
2474 wrmsrq(MSR_TSX_FORCE_ABORT, val);
2475 }
2476 }
2477
intel_tfa_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)2478 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2479 {
2480 /*
2481 * We're going to use PMC3, make sure TFA is set before we touch it.
2482 */
2483 if (cntr == 3)
2484 intel_set_tfa(cpuc, true);
2485 }
2486
intel_tfa_pmu_enable_all(int added)2487 static void intel_tfa_pmu_enable_all(int added)
2488 {
2489 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2490
2491 /*
2492 * If we find PMC3 is no longer used when we enable the PMU, we can
2493 * clear TFA.
2494 */
2495 if (!test_bit(3, cpuc->active_mask))
2496 intel_set_tfa(cpuc, false);
2497
2498 intel_pmu_enable_all(added);
2499 }
2500
intel_pmu_get_status(void)2501 static inline u64 intel_pmu_get_status(void)
2502 {
2503 u64 status;
2504
2505 rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status);
2506
2507 return status;
2508 }
2509
intel_pmu_ack_status(u64 ack)2510 static inline void intel_pmu_ack_status(u64 ack)
2511 {
2512 wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2513 }
2514
event_is_checkpointed(struct perf_event * event)2515 static inline bool event_is_checkpointed(struct perf_event *event)
2516 {
2517 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2518 }
2519
intel_set_masks(struct perf_event * event,int idx)2520 static inline void intel_set_masks(struct perf_event *event, int idx)
2521 {
2522 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2523
2524 if (event->attr.exclude_host)
2525 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2526 if (event->attr.exclude_guest)
2527 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2528 if (event_is_checkpointed(event))
2529 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2530 }
2531
intel_clear_masks(struct perf_event * event,int idx)2532 static inline void intel_clear_masks(struct perf_event *event, int idx)
2533 {
2534 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2535
2536 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2537 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2538 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2539 }
2540
intel_pmu_disable_fixed(struct perf_event * event)2541 static void intel_pmu_disable_fixed(struct perf_event *event)
2542 {
2543 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2544 struct hw_perf_event *hwc = &event->hw;
2545 int idx = hwc->idx;
2546 u64 mask;
2547
2548 if (is_topdown_idx(idx)) {
2549 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2550
2551 /*
2552 * When there are other active TopDown events,
2553 * don't disable the fixed counter 3.
2554 */
2555 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2556 return;
2557 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2558 }
2559
2560 intel_clear_masks(event, idx);
2561
2562 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK);
2563 cpuc->fixed_ctrl_val &= ~mask;
2564 }
2565
__intel_pmu_update_event_ext(int idx,u64 ext)2566 static inline void __intel_pmu_update_event_ext(int idx, u64 ext)
2567 {
2568 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2569 u32 msr;
2570
2571 if (idx < INTEL_PMC_IDX_FIXED) {
2572 msr = MSR_IA32_PMC_V6_GP0_CFG_C +
2573 x86_pmu.addr_offset(idx, false);
2574 } else {
2575 msr = MSR_IA32_PMC_V6_FX0_CFG_C +
2576 x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);
2577 }
2578
2579 cpuc->cfg_c_val[idx] = ext;
2580 wrmsrq(msr, ext);
2581 }
2582
intel_pmu_disable_event_ext(struct perf_event * event)2583 static void intel_pmu_disable_event_ext(struct perf_event *event)
2584 {
2585 /*
2586 * Only clear CFG_C MSR for PEBS counter group events,
2587 * it avoids the HW counter's value to be added into
2588 * other PEBS records incorrectly after PEBS counter
2589 * group events are disabled.
2590 *
2591 * For other events, it's unnecessary to clear CFG_C MSRs
2592 * since CFG_C doesn't take effect if counter is in
2593 * disabled state. That helps to reduce the WRMSR overhead
2594 * in context switches.
2595 */
2596 if (!is_pebs_counter_event_group(event))
2597 return;
2598
2599 __intel_pmu_update_event_ext(event->hw.idx, 0);
2600 }
2601
2602 DEFINE_STATIC_CALL_NULL(intel_pmu_disable_event_ext, intel_pmu_disable_event_ext);
2603
intel_pmu_disable_event(struct perf_event * event)2604 static void intel_pmu_disable_event(struct perf_event *event)
2605 {
2606 struct hw_perf_event *hwc = &event->hw;
2607 int idx = hwc->idx;
2608
2609 switch (idx) {
2610 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2611 intel_clear_masks(event, idx);
2612 static_call_cond(intel_pmu_disable_event_ext)(event);
2613 x86_pmu_disable_event(event);
2614 break;
2615 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2616 static_call_cond(intel_pmu_disable_event_ext)(event);
2617 fallthrough;
2618 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2619 intel_pmu_disable_fixed(event);
2620 break;
2621 case INTEL_PMC_IDX_FIXED_BTS:
2622 intel_pmu_disable_bts();
2623 intel_pmu_drain_bts_buffer();
2624 return;
2625 case INTEL_PMC_IDX_FIXED_VLBR:
2626 intel_clear_masks(event, idx);
2627 break;
2628 default:
2629 intel_clear_masks(event, idx);
2630 pr_warn("Failed to disable the event with invalid index %d\n",
2631 idx);
2632 return;
2633 }
2634
2635 /*
2636 * Needs to be called after x86_pmu_disable_event,
2637 * so we don't trigger the event without PEBS bit set.
2638 */
2639 if (unlikely(event->attr.precise_ip))
2640 static_call(x86_pmu_pebs_disable)(event);
2641 }
2642
intel_pmu_assign_event(struct perf_event * event,int idx)2643 static void intel_pmu_assign_event(struct perf_event *event, int idx)
2644 {
2645 if (is_pebs_pt(event))
2646 perf_report_aux_output_id(event, idx);
2647 }
2648
intel_pmu_needs_branch_stack(struct perf_event * event)2649 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event)
2650 {
2651 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK;
2652 }
2653
intel_pmu_del_event(struct perf_event * event)2654 static void intel_pmu_del_event(struct perf_event *event)
2655 {
2656 if (intel_pmu_needs_branch_stack(event))
2657 intel_pmu_lbr_del(event);
2658 if (event->attr.precise_ip)
2659 intel_pmu_pebs_del(event);
2660 if (is_pebs_counter_event_group(event) ||
2661 is_acr_event_group(event))
2662 this_cpu_ptr(&cpu_hw_events)->n_late_setup--;
2663 }
2664
icl_set_topdown_event_period(struct perf_event * event)2665 static int icl_set_topdown_event_period(struct perf_event *event)
2666 {
2667 struct hw_perf_event *hwc = &event->hw;
2668 s64 left = local64_read(&hwc->period_left);
2669
2670 /*
2671 * The values in PERF_METRICS MSR are derived from fixed counter 3.
2672 * Software should start both registers, PERF_METRICS and fixed
2673 * counter 3, from zero.
2674 * Clear PERF_METRICS and Fixed counter 3 in initialization.
2675 * After that, both MSRs will be cleared for each read.
2676 * Don't need to clear them again.
2677 */
2678 if (left == x86_pmu.max_period) {
2679 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0);
2680 wrmsrq(MSR_PERF_METRICS, 0);
2681 hwc->saved_slots = 0;
2682 hwc->saved_metric = 0;
2683 }
2684
2685 if ((hwc->saved_slots) && is_slots_event(event)) {
2686 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2687 wrmsrq(MSR_PERF_METRICS, hwc->saved_metric);
2688 }
2689
2690 perf_event_update_userpage(event);
2691
2692 return 0;
2693 }
2694
2695 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period);
2696
icl_get_metrics_event_value(u64 metric,u64 slots,int idx)2697 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2698 {
2699 u32 val;
2700
2701 /*
2702 * The metric is reported as an 8bit integer fraction
2703 * summing up to 0xff.
2704 * slots-in-metric = (Metric / 0xff) * slots
2705 */
2706 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2707 return mul_u64_u32_div(slots, val, 0xff);
2708 }
2709
icl_get_topdown_value(struct perf_event * event,u64 slots,u64 metrics)2710 static u64 icl_get_topdown_value(struct perf_event *event,
2711 u64 slots, u64 metrics)
2712 {
2713 int idx = event->hw.idx;
2714 u64 delta;
2715
2716 if (is_metric_idx(idx))
2717 delta = icl_get_metrics_event_value(metrics, slots, idx);
2718 else
2719 delta = slots;
2720
2721 return delta;
2722 }
2723
__icl_update_topdown_event(struct perf_event * event,u64 slots,u64 metrics,u64 last_slots,u64 last_metrics)2724 static void __icl_update_topdown_event(struct perf_event *event,
2725 u64 slots, u64 metrics,
2726 u64 last_slots, u64 last_metrics)
2727 {
2728 u64 delta, last = 0;
2729
2730 delta = icl_get_topdown_value(event, slots, metrics);
2731 if (last_slots)
2732 last = icl_get_topdown_value(event, last_slots, last_metrics);
2733
2734 /*
2735 * The 8bit integer fraction of metric may be not accurate,
2736 * especially when the changes is very small.
2737 * For example, if only a few bad_spec happens, the fraction
2738 * may be reduced from 1 to 0. If so, the bad_spec event value
2739 * will be 0 which is definitely less than the last value.
2740 * Avoid update event->count for this case.
2741 */
2742 if (delta > last) {
2743 delta -= last;
2744 local64_add(delta, &event->count);
2745 }
2746 }
2747
update_saved_topdown_regs(struct perf_event * event,u64 slots,u64 metrics,int metric_end)2748 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
2749 u64 metrics, int metric_end)
2750 {
2751 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2752 struct perf_event *other;
2753 int idx;
2754
2755 event->hw.saved_slots = slots;
2756 event->hw.saved_metric = metrics;
2757
2758 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2759 if (!is_topdown_idx(idx))
2760 continue;
2761 other = cpuc->events[idx];
2762 other->hw.saved_slots = slots;
2763 other->hw.saved_metric = metrics;
2764 }
2765 }
2766
2767 /*
2768 * Update all active Topdown events.
2769 *
2770 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2771 * modify by a NMI. PMU has to be disabled before calling this function.
2772 */
2773
intel_update_topdown_event(struct perf_event * event,int metric_end,u64 * val)2774 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end, u64 *val)
2775 {
2776 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2777 struct perf_event *other;
2778 u64 slots, metrics;
2779 bool reset = true;
2780 int idx;
2781
2782 if (!val) {
2783 /* read Fixed counter 3 */
2784 slots = rdpmc(3 | INTEL_PMC_FIXED_RDPMC_BASE);
2785 if (!slots)
2786 return 0;
2787
2788 /* read PERF_METRICS */
2789 metrics = rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS);
2790 } else {
2791 slots = val[0];
2792 metrics = val[1];
2793 /*
2794 * Don't reset the PERF_METRICS and Fixed counter 3
2795 * for each PEBS record read. Utilize the RDPMC metrics
2796 * clear mode.
2797 */
2798 reset = false;
2799 }
2800
2801 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2802 if (!is_topdown_idx(idx))
2803 continue;
2804 other = cpuc->events[idx];
2805 __icl_update_topdown_event(other, slots, metrics,
2806 event ? event->hw.saved_slots : 0,
2807 event ? event->hw.saved_metric : 0);
2808 }
2809
2810 /*
2811 * Check and update this event, which may have been cleared
2812 * in active_mask e.g. x86_pmu_stop()
2813 */
2814 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2815 __icl_update_topdown_event(event, slots, metrics,
2816 event->hw.saved_slots,
2817 event->hw.saved_metric);
2818
2819 /*
2820 * In x86_pmu_stop(), the event is cleared in active_mask first,
2821 * then drain the delta, which indicates context switch for
2822 * counting.
2823 * Save metric and slots for context switch.
2824 * Don't need to reset the PERF_METRICS and Fixed counter 3.
2825 * Because the values will be restored in next schedule in.
2826 */
2827 update_saved_topdown_regs(event, slots, metrics, metric_end);
2828 reset = false;
2829 }
2830
2831 if (reset) {
2832 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2833 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0);
2834 wrmsrq(MSR_PERF_METRICS, 0);
2835 if (event)
2836 update_saved_topdown_regs(event, 0, 0, metric_end);
2837 }
2838
2839 return slots;
2840 }
2841
icl_update_topdown_event(struct perf_event * event,u64 * val)2842 static u64 icl_update_topdown_event(struct perf_event *event, u64 *val)
2843 {
2844 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
2845 x86_pmu.num_topdown_events - 1,
2846 val);
2847 }
2848
2849 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update);
2850
intel_pmu_read_event(struct perf_event * event)2851 static void intel_pmu_read_event(struct perf_event *event)
2852 {
2853 if (event->hw.flags & (PERF_X86_EVENT_AUTO_RELOAD | PERF_X86_EVENT_TOPDOWN) ||
2854 is_pebs_counter_event_group(event)) {
2855 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2856 bool pmu_enabled = cpuc->enabled;
2857
2858 /* Only need to call update_topdown_event() once for group read. */
2859 if (is_metric_event(event) && (cpuc->txn_flags & PERF_PMU_TXN_READ))
2860 return;
2861
2862 cpuc->enabled = 0;
2863 if (pmu_enabled)
2864 intel_pmu_disable_all();
2865
2866 /*
2867 * If the PEBS counters snapshotting is enabled,
2868 * the topdown event is available in PEBS records.
2869 */
2870 if (is_topdown_count(event) && !is_pebs_counter_event_group(event))
2871 static_call(intel_pmu_update_topdown_event)(event, NULL);
2872 else
2873 intel_pmu_drain_pebs_buffer();
2874
2875 cpuc->enabled = pmu_enabled;
2876 if (pmu_enabled)
2877 intel_pmu_enable_all(0);
2878
2879 return;
2880 }
2881
2882 x86_perf_event_update(event);
2883 }
2884
intel_pmu_enable_fixed(struct perf_event * event)2885 static void intel_pmu_enable_fixed(struct perf_event *event)
2886 {
2887 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2888 struct hw_perf_event *hwc = &event->hw;
2889 int idx = hwc->idx;
2890 u64 bits = 0;
2891
2892 if (is_topdown_idx(idx)) {
2893 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2894 /*
2895 * When there are other active TopDown events,
2896 * don't enable the fixed counter 3 again.
2897 */
2898 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2899 return;
2900
2901 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2902
2903 if (event->attr.config1 & INTEL_TD_CFG_METRIC_CLEAR)
2904 bits |= INTEL_FIXED_3_METRICS_CLEAR;
2905 }
2906
2907 intel_set_masks(event, idx);
2908
2909 /*
2910 * Enable IRQ generation (0x8), if not PEBS,
2911 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2912 * if requested:
2913 */
2914 if (!event->attr.precise_ip)
2915 bits |= INTEL_FIXED_0_ENABLE_PMI;
2916 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2917 bits |= INTEL_FIXED_0_USER;
2918 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2919 bits |= INTEL_FIXED_0_KERNEL;
2920
2921 /*
2922 * ANY bit is supported in v3 and up
2923 */
2924 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2925 bits |= INTEL_FIXED_0_ANYTHREAD;
2926
2927 idx -= INTEL_PMC_IDX_FIXED;
2928 bits = intel_fixed_bits_by_idx(idx, bits);
2929 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip)
2930 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
2931
2932 cpuc->fixed_ctrl_val &= ~intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK);
2933 cpuc->fixed_ctrl_val |= bits;
2934 }
2935
intel_pmu_config_acr(int idx,u64 mask,u32 reload)2936 static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
2937 {
2938 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2939 int msr_b, msr_c;
2940 int msr_offset;
2941
2942 if (!mask && !cpuc->acr_cfg_b[idx])
2943 return;
2944
2945 if (idx < INTEL_PMC_IDX_FIXED) {
2946 msr_b = MSR_IA32_PMC_V6_GP0_CFG_B;
2947 msr_c = MSR_IA32_PMC_V6_GP0_CFG_C;
2948 msr_offset = x86_pmu.addr_offset(idx, false);
2949 } else {
2950 msr_b = MSR_IA32_PMC_V6_FX0_CFG_B;
2951 msr_c = MSR_IA32_PMC_V6_FX0_CFG_C;
2952 msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);
2953 }
2954
2955 if (cpuc->acr_cfg_b[idx] != mask) {
2956 wrmsrl(msr_b + msr_offset, mask);
2957 cpuc->acr_cfg_b[idx] = mask;
2958 }
2959 /* Only need to update the reload value when there is a valid config value. */
2960 if (mask && cpuc->acr_cfg_c[idx] != reload) {
2961 wrmsrl(msr_c + msr_offset, reload);
2962 cpuc->acr_cfg_c[idx] = reload;
2963 }
2964 }
2965
intel_pmu_enable_acr(struct perf_event * event)2966 static void intel_pmu_enable_acr(struct perf_event *event)
2967 {
2968 struct hw_perf_event *hwc = &event->hw;
2969
2970 if (!is_acr_event_group(event) || !event->attr.config2) {
2971 /*
2972 * The disable doesn't clear the ACR CFG register.
2973 * Check and clear the ACR CFG register.
2974 */
2975 intel_pmu_config_acr(hwc->idx, 0, 0);
2976 return;
2977 }
2978
2979 intel_pmu_config_acr(hwc->idx, hwc->config1, -hwc->sample_period);
2980 }
2981
2982 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
2983
intel_pmu_enable_event_ext(struct perf_event * event)2984 static void intel_pmu_enable_event_ext(struct perf_event *event)
2985 {
2986 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2987 struct hw_perf_event *hwc = &event->hw;
2988 union arch_pebs_index old, new;
2989 struct arch_pebs_cap cap;
2990 u64 ext = 0;
2991
2992 cap = hybrid(cpuc->pmu, arch_pebs_cap);
2993
2994 if (event->attr.precise_ip) {
2995 u64 pebs_data_cfg = intel_get_arch_pebs_data_config(event);
2996
2997 ext |= ARCH_PEBS_EN;
2998 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD)
2999 ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD;
3000
3001 if (pebs_data_cfg && cap.caps) {
3002 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
3003 ext |= ARCH_PEBS_AUX & cap.caps;
3004
3005 if (pebs_data_cfg & PEBS_DATACFG_GP)
3006 ext |= ARCH_PEBS_GPR & cap.caps;
3007
3008 if (pebs_data_cfg & PEBS_DATACFG_XMMS)
3009 ext |= ARCH_PEBS_VECR_XMM & cap.caps;
3010
3011 if (pebs_data_cfg & PEBS_DATACFG_LBRS)
3012 ext |= ARCH_PEBS_LBR & cap.caps;
3013
3014 if (pebs_data_cfg &
3015 (PEBS_DATACFG_CNTR_MASK << PEBS_DATACFG_CNTR_SHIFT))
3016 ext |= ARCH_PEBS_CNTR_GP & cap.caps;
3017
3018 if (pebs_data_cfg &
3019 (PEBS_DATACFG_FIX_MASK << PEBS_DATACFG_FIX_SHIFT))
3020 ext |= ARCH_PEBS_CNTR_FIXED & cap.caps;
3021
3022 if (pebs_data_cfg & PEBS_DATACFG_METRICS)
3023 ext |= ARCH_PEBS_CNTR_METRICS & cap.caps;
3024 }
3025
3026 if (cpuc->n_pebs == cpuc->n_large_pebs)
3027 new.thresh = ARCH_PEBS_THRESH_MULTI;
3028 else
3029 new.thresh = ARCH_PEBS_THRESH_SINGLE;
3030
3031 rdmsrq(MSR_IA32_PEBS_INDEX, old.whole);
3032 if (new.thresh != old.thresh || !old.en) {
3033 if (old.thresh == ARCH_PEBS_THRESH_MULTI && old.wr > 0) {
3034 /*
3035 * Large PEBS was enabled.
3036 * Drain PEBS buffer before applying the single PEBS.
3037 */
3038 intel_pmu_drain_pebs_buffer();
3039 } else {
3040 new.wr = 0;
3041 new.full = 0;
3042 new.en = 1;
3043 wrmsrq(MSR_IA32_PEBS_INDEX, new.whole);
3044 }
3045 }
3046 }
3047
3048 if (is_pebs_counter_event_group(event))
3049 ext |= ARCH_PEBS_CNTR_ALLOW;
3050
3051 if (cpuc->cfg_c_val[hwc->idx] != ext)
3052 __intel_pmu_update_event_ext(hwc->idx, ext);
3053 }
3054
3055 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_event_ext, intel_pmu_enable_event_ext);
3056
intel_pmu_enable_event(struct perf_event * event)3057 static void intel_pmu_enable_event(struct perf_event *event)
3058 {
3059 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE;
3060 struct hw_perf_event *hwc = &event->hw;
3061 int idx = hwc->idx;
3062
3063 if (unlikely(event->attr.precise_ip))
3064 static_call(x86_pmu_pebs_enable)(event);
3065
3066 switch (idx) {
3067 case 0 ... INTEL_PMC_IDX_FIXED - 1:
3068 if (branch_sample_counters(event))
3069 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR;
3070 intel_set_masks(event, idx);
3071 static_call_cond(intel_pmu_enable_acr_event)(event);
3072 static_call_cond(intel_pmu_enable_event_ext)(event);
3073 __x86_pmu_enable_event(hwc, enable_mask);
3074 break;
3075 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
3076 static_call_cond(intel_pmu_enable_acr_event)(event);
3077 static_call_cond(intel_pmu_enable_event_ext)(event);
3078 fallthrough;
3079 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
3080 intel_pmu_enable_fixed(event);
3081 break;
3082 case INTEL_PMC_IDX_FIXED_BTS:
3083 if (!__this_cpu_read(cpu_hw_events.enabled))
3084 return;
3085 intel_pmu_enable_bts(hwc->config);
3086 break;
3087 case INTEL_PMC_IDX_FIXED_VLBR:
3088 intel_set_masks(event, idx);
3089 break;
3090 default:
3091 pr_warn("Failed to enable the event with invalid index %d\n",
3092 idx);
3093 }
3094 }
3095
intel_pmu_acr_late_setup(struct cpu_hw_events * cpuc)3096 static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc)
3097 {
3098 struct perf_event *event, *leader;
3099 int i, j, idx;
3100
3101 for (i = 0; i < cpuc->n_events; i++) {
3102 leader = cpuc->event_list[i];
3103 if (!is_acr_event_group(leader))
3104 continue;
3105
3106 /* The ACR events must be contiguous. */
3107 for (j = i; j < cpuc->n_events; j++) {
3108 event = cpuc->event_list[j];
3109 if (event->group_leader != leader->group_leader)
3110 break;
3111 for_each_set_bit(idx, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) {
3112 if (i + idx >= cpuc->n_events ||
3113 !is_acr_event_group(cpuc->event_list[i + idx]))
3114 return;
3115 __set_bit(cpuc->assign[i + idx], (unsigned long *)&event->hw.config1);
3116 }
3117 }
3118 i = j - 1;
3119 }
3120 }
3121
intel_pmu_late_setup(void)3122 void intel_pmu_late_setup(void)
3123 {
3124 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3125
3126 if (!cpuc->n_late_setup)
3127 return;
3128
3129 intel_pmu_pebs_late_setup(cpuc);
3130 intel_pmu_acr_late_setup(cpuc);
3131 }
3132
intel_pmu_add_event(struct perf_event * event)3133 static void intel_pmu_add_event(struct perf_event *event)
3134 {
3135 if (event->attr.precise_ip)
3136 intel_pmu_pebs_add(event);
3137 if (intel_pmu_needs_branch_stack(event))
3138 intel_pmu_lbr_add(event);
3139 if (is_pebs_counter_event_group(event) ||
3140 is_acr_event_group(event))
3141 this_cpu_ptr(&cpu_hw_events)->n_late_setup++;
3142 }
3143
3144 /*
3145 * Save and restart an expired event. Called by NMI contexts,
3146 * so it has to be careful about preempting normal event ops:
3147 */
intel_pmu_save_and_restart(struct perf_event * event)3148 int intel_pmu_save_and_restart(struct perf_event *event)
3149 {
3150 static_call(x86_pmu_update)(event);
3151 /*
3152 * For a checkpointed counter always reset back to 0. This
3153 * avoids a situation where the counter overflows, aborts the
3154 * transaction and is then set back to shortly before the
3155 * overflow, and overflows and aborts again.
3156 */
3157 if (unlikely(event_is_checkpointed(event))) {
3158 /* No race with NMIs because the counter should not be armed */
3159 wrmsrq(event->hw.event_base, 0);
3160 local64_set(&event->hw.prev_count, 0);
3161 }
3162 return static_call(x86_pmu_set_period)(event);
3163 }
3164
intel_pmu_set_period(struct perf_event * event)3165 static int intel_pmu_set_period(struct perf_event *event)
3166 {
3167 if (unlikely(is_topdown_count(event)))
3168 return static_call(intel_pmu_set_topdown_event_period)(event);
3169
3170 return x86_perf_event_set_period(event);
3171 }
3172
intel_pmu_update(struct perf_event * event)3173 static u64 intel_pmu_update(struct perf_event *event)
3174 {
3175 if (unlikely(is_topdown_count(event)))
3176 return static_call(intel_pmu_update_topdown_event)(event, NULL);
3177
3178 return x86_perf_event_update(event);
3179 }
3180
intel_pmu_reset(void)3181 static void intel_pmu_reset(void)
3182 {
3183 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
3184 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3185 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask);
3186 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);
3187 unsigned long flags;
3188 int idx;
3189
3190 if (!*(u64 *)cntr_mask)
3191 return;
3192
3193 local_irq_save(flags);
3194
3195 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
3196
3197 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) {
3198 wrmsrq_safe(x86_pmu_config_addr(idx), 0ull);
3199 wrmsrq_safe(x86_pmu_event_addr(idx), 0ull);
3200 }
3201 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) {
3202 if (fixed_counter_disabled(idx, cpuc->pmu))
3203 continue;
3204 wrmsrq_safe(x86_pmu_fixed_ctr_addr(idx), 0ull);
3205 }
3206
3207 if (ds)
3208 ds->bts_index = ds->bts_buffer_base;
3209
3210 /* Ack all overflows and disable fixed counters */
3211 if (x86_pmu.version >= 2) {
3212 intel_pmu_ack_status(intel_pmu_get_status());
3213 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0);
3214 }
3215
3216 /* Reset LBRs and LBR freezing */
3217 if (x86_pmu.lbr_nr) {
3218 update_debugctlmsr(get_debugctlmsr() &
3219 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
3220 }
3221
3222 local_irq_restore(flags);
3223 }
3224
3225 /*
3226 * We may be running with guest PEBS events created by KVM, and the
3227 * PEBS records are logged into the guest's DS and invisible to host.
3228 *
3229 * In the case of guest PEBS overflow, we only trigger a fake event
3230 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM.
3231 * The guest will then vm-entry and check the guest DS area to read
3232 * the guest PEBS records.
3233 *
3234 * The contents and other behavior of the guest event do not matter.
3235 */
x86_pmu_handle_guest_pebs(struct pt_regs * regs,struct perf_sample_data * data)3236 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs,
3237 struct perf_sample_data *data)
3238 {
3239 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3240 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask;
3241 struct perf_event *event = NULL;
3242 int bit;
3243
3244 if (!unlikely(perf_guest_state()))
3245 return;
3246
3247 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active ||
3248 !guest_pebs_idxs)
3249 return;
3250
3251 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) {
3252 event = cpuc->events[bit];
3253 if (!event->attr.precise_ip)
3254 continue;
3255
3256 perf_sample_data_init(data, 0, event->hw.last_period);
3257 perf_event_overflow(event, data, regs);
3258
3259 /* Inject one fake event is enough. */
3260 break;
3261 }
3262 }
3263
handle_pmi_common(struct pt_regs * regs,u64 status)3264 static int handle_pmi_common(struct pt_regs *regs, u64 status)
3265 {
3266 struct perf_sample_data data;
3267 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3268 int bit;
3269 int handled = 0;
3270
3271 inc_irq_stat(apic_perf_irqs);
3272
3273 /*
3274 * Ignore a range of extra bits in status that do not indicate
3275 * overflow by themselves.
3276 */
3277 status &= ~(GLOBAL_STATUS_COND_CHG |
3278 GLOBAL_STATUS_ASIF |
3279 GLOBAL_STATUS_LBRS_FROZEN);
3280 if (!status)
3281 return 0;
3282 /*
3283 * In case multiple PEBS events are sampled at the same time,
3284 * it is possible to have GLOBAL_STATUS bit 62 set indicating
3285 * PEBS buffer overflow and also seeing at most 3 PEBS counters
3286 * having their bits set in the status register. This is a sign
3287 * that there was at least one PEBS record pending at the time
3288 * of the PMU interrupt. PEBS counters must only be processed
3289 * via the drain_pebs() calls and not via the regular sample
3290 * processing loop coming after that the function, otherwise
3291 * phony regular samples may be generated in the sampling buffer
3292 * not marked with the EXACT tag. Another possibility is to have
3293 * one PEBS event and at least one non-PEBS event which overflows
3294 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
3295 * not be set, yet the overflow status bit for the PEBS counter will
3296 * be on Skylake.
3297 *
3298 * To avoid this problem, we systematically ignore the PEBS-enabled
3299 * counters from the GLOBAL_STATUS mask and we always process PEBS
3300 * events via drain_pebs().
3301 */
3302 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
3303
3304 /*
3305 * PEBS overflow sets bit 62 in the global status register
3306 */
3307 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
3308 u64 pebs_enabled = cpuc->pebs_enabled;
3309
3310 handled++;
3311 x86_pmu_handle_guest_pebs(regs, &data);
3312 static_call(x86_pmu_drain_pebs)(regs, &data);
3313
3314 /*
3315 * PMI throttle may be triggered, which stops the PEBS event.
3316 * Although cpuc->pebs_enabled is updated accordingly, the
3317 * MSR_IA32_PEBS_ENABLE is not updated. Because the
3318 * cpuc->enabled has been forced to 0 in PMI.
3319 * Update the MSR if pebs_enabled is changed.
3320 */
3321 if (pebs_enabled != cpuc->pebs_enabled)
3322 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
3323
3324 /*
3325 * Above PEBS handler (PEBS counters snapshotting) has updated fixed
3326 * counter 3 and perf metrics counts if they are in counter group,
3327 * unnecessary to update again.
3328 */
3329 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] &&
3330 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS]))
3331 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;
3332 }
3333
3334 /*
3335 * Arch PEBS sets bit 54 in the global status register
3336 */
3337 if (__test_and_clear_bit(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT,
3338 (unsigned long *)&status)) {
3339 handled++;
3340 static_call(x86_pmu_drain_pebs)(regs, &data);
3341
3342 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] &&
3343 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS]))
3344 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;
3345 }
3346
3347 /*
3348 * Intel PT
3349 */
3350 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
3351 handled++;
3352 if (!perf_guest_handle_intel_pt_intr())
3353 intel_pt_interrupt();
3354 }
3355
3356 /*
3357 * Intel Perf metrics
3358 */
3359 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
3360 handled++;
3361 static_call(intel_pmu_update_topdown_event)(NULL, NULL);
3362 }
3363
3364 status &= hybrid(cpuc->pmu, intel_ctrl);
3365
3366 /*
3367 * Checkpointed counters can lead to 'spurious' PMIs because the
3368 * rollback caused by the PMI will have cleared the overflow status
3369 * bit. Therefore always force probe these counters.
3370 */
3371 status |= cpuc->intel_cp_status;
3372
3373 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
3374 struct perf_event *event = cpuc->events[bit];
3375 u64 last_period;
3376
3377 handled++;
3378
3379 if (!test_bit(bit, cpuc->active_mask))
3380 continue;
3381
3382 /*
3383 * There may be unprocessed PEBS records in the PEBS buffer,
3384 * which still stores the previous values.
3385 * Process those records first before handling the latest value.
3386 * For example,
3387 * A is a regular counter
3388 * B is a PEBS event which reads A
3389 * C is a PEBS event
3390 *
3391 * The following can happen:
3392 * B-assist A=1
3393 * C A=2
3394 * B-assist A=3
3395 * A-overflow-PMI A=4
3396 * C-assist-PMI (PEBS buffer) A=5
3397 *
3398 * The PEBS buffer has to be drained before handling the A-PMI
3399 */
3400 if (is_pebs_counter_event_group(event))
3401 static_call(x86_pmu_drain_pebs)(regs, &data);
3402
3403 last_period = event->hw.last_period;
3404
3405 if (!intel_pmu_save_and_restart(event))
3406 continue;
3407
3408 perf_sample_data_init(&data, 0, last_period);
3409
3410 if (has_branch_stack(event))
3411 intel_pmu_lbr_save_brstack(&data, cpuc, event);
3412
3413 perf_event_overflow(event, &data, regs);
3414 }
3415
3416 return handled;
3417 }
3418
3419 /*
3420 * This handler is triggered by the local APIC, so the APIC IRQ handling
3421 * rules apply:
3422 */
intel_pmu_handle_irq(struct pt_regs * regs)3423 static int intel_pmu_handle_irq(struct pt_regs *regs)
3424 {
3425 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3426 bool late_ack = hybrid_bit(cpuc->pmu, late_ack);
3427 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack);
3428 int loops;
3429 u64 status;
3430 int handled;
3431 int pmu_enabled;
3432
3433 /*
3434 * Save the PMU state.
3435 * It needs to be restored when leaving the handler.
3436 */
3437 pmu_enabled = cpuc->enabled;
3438 /*
3439 * In general, the early ACK is only applied for old platforms.
3440 * For the big core starts from Haswell, the late ACK should be
3441 * applied.
3442 * For the small core after Tremont, we have to do the ACK right
3443 * before re-enabling counters, which is in the middle of the
3444 * NMI handler.
3445 */
3446 if (!late_ack && !mid_ack)
3447 apic_write(APIC_LVTPC, APIC_DM_NMI);
3448 intel_bts_disable_local();
3449 cpuc->enabled = 0;
3450 __intel_pmu_disable_all(true);
3451 handled = intel_pmu_drain_bts_buffer();
3452 handled += intel_bts_interrupt();
3453 status = intel_pmu_get_status();
3454 if (!status)
3455 goto done;
3456
3457 loops = 0;
3458 again:
3459 intel_pmu_lbr_read();
3460 intel_pmu_ack_status(status);
3461 if (++loops > 100) {
3462 static bool warned;
3463
3464 if (!warned) {
3465 WARN(1, "perfevents: irq loop stuck!\n");
3466 perf_event_print_debug();
3467 warned = true;
3468 }
3469 intel_pmu_reset();
3470 goto done;
3471 }
3472
3473 handled += handle_pmi_common(regs, status);
3474
3475 /*
3476 * Repeat if there is more work to be done:
3477 */
3478 status = intel_pmu_get_status();
3479 if (status)
3480 goto again;
3481
3482 done:
3483 if (mid_ack)
3484 apic_write(APIC_LVTPC, APIC_DM_NMI);
3485 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
3486 cpuc->enabled = pmu_enabled;
3487 if (pmu_enabled)
3488 __intel_pmu_enable_all(0, true);
3489 intel_bts_enable_local();
3490
3491 /*
3492 * Only unmask the NMI after the overflow counters
3493 * have been reset. This avoids spurious NMIs on
3494 * Haswell CPUs.
3495 */
3496 if (late_ack)
3497 apic_write(APIC_LVTPC, APIC_DM_NMI);
3498 return handled;
3499 }
3500
3501 static struct event_constraint *
intel_bts_constraints(struct perf_event * event)3502 intel_bts_constraints(struct perf_event *event)
3503 {
3504 if (unlikely(intel_pmu_has_bts(event)))
3505 return &bts_constraint;
3506
3507 return NULL;
3508 }
3509
3510 /*
3511 * Note: matches a fake event, like Fixed2.
3512 */
3513 static struct event_constraint *
intel_vlbr_constraints(struct perf_event * event)3514 intel_vlbr_constraints(struct perf_event *event)
3515 {
3516 struct event_constraint *c = &vlbr_constraint;
3517
3518 if (unlikely(constraint_match(c, event->hw.config))) {
3519 event->hw.flags |= c->flags;
3520 return c;
3521 }
3522
3523 return NULL;
3524 }
3525
intel_alt_er(struct cpu_hw_events * cpuc,int idx,u64 config)3526 static int intel_alt_er(struct cpu_hw_events *cpuc,
3527 int idx, u64 config)
3528 {
3529 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
3530 int alt_idx = idx;
3531
3532 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
3533 return idx;
3534
3535 if (idx == EXTRA_REG_RSP_0)
3536 alt_idx = EXTRA_REG_RSP_1;
3537
3538 if (idx == EXTRA_REG_RSP_1)
3539 alt_idx = EXTRA_REG_RSP_0;
3540
3541 if (config & ~extra_regs[alt_idx].valid_mask)
3542 return idx;
3543
3544 return alt_idx;
3545 }
3546
intel_fixup_er(struct perf_event * event,int idx)3547 static void intel_fixup_er(struct perf_event *event, int idx)
3548 {
3549 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
3550 event->hw.extra_reg.idx = idx;
3551
3552 if (idx == EXTRA_REG_RSP_0) {
3553 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3554 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
3555 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
3556 } else if (idx == EXTRA_REG_RSP_1) {
3557 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3558 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
3559 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
3560 }
3561 }
3562
3563 /*
3564 * manage allocation of shared extra msr for certain events
3565 *
3566 * sharing can be:
3567 * per-cpu: to be shared between the various events on a single PMU
3568 * per-core: per-cpu + shared by HT threads
3569 */
3570 static struct event_constraint *
__intel_shared_reg_get_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,struct hw_perf_event_extra * reg)3571 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
3572 struct perf_event *event,
3573 struct hw_perf_event_extra *reg)
3574 {
3575 struct event_constraint *c = &emptyconstraint;
3576 struct er_account *era;
3577 unsigned long flags;
3578 int idx = reg->idx;
3579
3580 /*
3581 * reg->alloc can be set due to existing state, so for fake cpuc we
3582 * need to ignore this, otherwise we might fail to allocate proper fake
3583 * state for this extra reg constraint. Also see the comment below.
3584 */
3585 if (reg->alloc && !cpuc->is_fake)
3586 return NULL; /* call x86_get_event_constraint() */
3587
3588 again:
3589 era = &cpuc->shared_regs->regs[idx];
3590 /*
3591 * we use spin_lock_irqsave() to avoid lockdep issues when
3592 * passing a fake cpuc
3593 */
3594 raw_spin_lock_irqsave(&era->lock, flags);
3595
3596 if (!atomic_read(&era->ref) || era->config == reg->config) {
3597
3598 /*
3599 * If its a fake cpuc -- as per validate_{group,event}() we
3600 * shouldn't touch event state and we can avoid doing so
3601 * since both will only call get_event_constraints() once
3602 * on each event, this avoids the need for reg->alloc.
3603 *
3604 * Not doing the ER fixup will only result in era->reg being
3605 * wrong, but since we won't actually try and program hardware
3606 * this isn't a problem either.
3607 */
3608 if (!cpuc->is_fake) {
3609 if (idx != reg->idx)
3610 intel_fixup_er(event, idx);
3611
3612 /*
3613 * x86_schedule_events() can call get_event_constraints()
3614 * multiple times on events in the case of incremental
3615 * scheduling(). reg->alloc ensures we only do the ER
3616 * allocation once.
3617 */
3618 reg->alloc = 1;
3619 }
3620
3621 /* lock in msr value */
3622 era->config = reg->config;
3623 era->reg = reg->reg;
3624
3625 /* one more user */
3626 atomic_inc(&era->ref);
3627
3628 /*
3629 * need to call x86_get_event_constraint()
3630 * to check if associated event has constraints
3631 */
3632 c = NULL;
3633 } else {
3634 idx = intel_alt_er(cpuc, idx, reg->config);
3635 if (idx != reg->idx) {
3636 raw_spin_unlock_irqrestore(&era->lock, flags);
3637 goto again;
3638 }
3639 }
3640 raw_spin_unlock_irqrestore(&era->lock, flags);
3641
3642 return c;
3643 }
3644
3645 static void
__intel_shared_reg_put_constraints(struct cpu_hw_events * cpuc,struct hw_perf_event_extra * reg)3646 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3647 struct hw_perf_event_extra *reg)
3648 {
3649 struct er_account *era;
3650
3651 /*
3652 * Only put constraint if extra reg was actually allocated. Also takes
3653 * care of event which do not use an extra shared reg.
3654 *
3655 * Also, if this is a fake cpuc we shouldn't touch any event state
3656 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3657 * either since it'll be thrown out.
3658 */
3659 if (!reg->alloc || cpuc->is_fake)
3660 return;
3661
3662 era = &cpuc->shared_regs->regs[reg->idx];
3663
3664 /* one fewer user */
3665 atomic_dec(&era->ref);
3666
3667 /* allocate again next time */
3668 reg->alloc = 0;
3669 }
3670
3671 static struct event_constraint *
intel_shared_regs_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3672 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3673 struct perf_event *event)
3674 {
3675 struct event_constraint *c = NULL, *d;
3676 struct hw_perf_event_extra *xreg, *breg;
3677
3678 xreg = &event->hw.extra_reg;
3679 if (xreg->idx != EXTRA_REG_NONE) {
3680 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3681 if (c == &emptyconstraint)
3682 return c;
3683 }
3684 breg = &event->hw.branch_reg;
3685 if (breg->idx != EXTRA_REG_NONE) {
3686 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3687 if (d == &emptyconstraint) {
3688 __intel_shared_reg_put_constraints(cpuc, xreg);
3689 c = d;
3690 }
3691 }
3692 return c;
3693 }
3694
3695 struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3696 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3697 struct perf_event *event)
3698 {
3699 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
3700 struct event_constraint *c;
3701
3702 if (event_constraints) {
3703 for_each_event_constraint(c, event_constraints) {
3704 if (constraint_match(c, event->hw.config)) {
3705 event->hw.flags |= c->flags;
3706 return c;
3707 }
3708 }
3709 }
3710
3711 return &hybrid_var(cpuc->pmu, unconstrained);
3712 }
3713
3714 static struct event_constraint *
__intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3715 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3716 struct perf_event *event)
3717 {
3718 struct event_constraint *c;
3719
3720 c = intel_vlbr_constraints(event);
3721 if (c)
3722 return c;
3723
3724 c = intel_bts_constraints(event);
3725 if (c)
3726 return c;
3727
3728 c = intel_shared_regs_constraints(cpuc, event);
3729 if (c)
3730 return c;
3731
3732 c = intel_pebs_constraints(event);
3733 if (c)
3734 return c;
3735
3736 return x86_get_event_constraints(cpuc, idx, event);
3737 }
3738
3739 static void
intel_start_scheduling(struct cpu_hw_events * cpuc)3740 intel_start_scheduling(struct cpu_hw_events *cpuc)
3741 {
3742 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3743 struct intel_excl_states *xl;
3744 int tid = cpuc->excl_thread_id;
3745
3746 /*
3747 * nothing needed if in group validation mode
3748 */
3749 if (cpuc->is_fake || !is_ht_workaround_enabled())
3750 return;
3751
3752 /*
3753 * no exclusion needed
3754 */
3755 if (WARN_ON_ONCE(!excl_cntrs))
3756 return;
3757
3758 xl = &excl_cntrs->states[tid];
3759
3760 xl->sched_started = true;
3761 /*
3762 * lock shared state until we are done scheduling
3763 * in stop_event_scheduling()
3764 * makes scheduling appear as a transaction
3765 */
3766 raw_spin_lock(&excl_cntrs->lock);
3767 }
3768
intel_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)3769 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3770 {
3771 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3772 struct event_constraint *c = cpuc->event_constraint[idx];
3773 struct intel_excl_states *xl;
3774 int tid = cpuc->excl_thread_id;
3775
3776 if (cpuc->is_fake || !is_ht_workaround_enabled())
3777 return;
3778
3779 if (WARN_ON_ONCE(!excl_cntrs))
3780 return;
3781
3782 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3783 return;
3784
3785 xl = &excl_cntrs->states[tid];
3786
3787 lockdep_assert_held(&excl_cntrs->lock);
3788
3789 if (c->flags & PERF_X86_EVENT_EXCL)
3790 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3791 else
3792 xl->state[cntr] = INTEL_EXCL_SHARED;
3793 }
3794
3795 static void
intel_stop_scheduling(struct cpu_hw_events * cpuc)3796 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3797 {
3798 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3799 struct intel_excl_states *xl;
3800 int tid = cpuc->excl_thread_id;
3801
3802 /*
3803 * nothing needed if in group validation mode
3804 */
3805 if (cpuc->is_fake || !is_ht_workaround_enabled())
3806 return;
3807 /*
3808 * no exclusion needed
3809 */
3810 if (WARN_ON_ONCE(!excl_cntrs))
3811 return;
3812
3813 xl = &excl_cntrs->states[tid];
3814
3815 xl->sched_started = false;
3816 /*
3817 * release shared state lock (acquired in intel_start_scheduling())
3818 */
3819 raw_spin_unlock(&excl_cntrs->lock);
3820 }
3821
3822 static struct event_constraint *
dyn_constraint(struct cpu_hw_events * cpuc,struct event_constraint * c,int idx)3823 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3824 {
3825 WARN_ON_ONCE(!cpuc->constraint_list);
3826
3827 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3828 struct event_constraint *cx;
3829
3830 /*
3831 * grab pre-allocated constraint entry
3832 */
3833 cx = &cpuc->constraint_list[idx];
3834
3835 /*
3836 * initialize dynamic constraint
3837 * with static constraint
3838 */
3839 *cx = *c;
3840
3841 /*
3842 * mark constraint as dynamic
3843 */
3844 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3845 c = cx;
3846 }
3847
3848 return c;
3849 }
3850
3851 static struct event_constraint *
intel_get_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,int idx,struct event_constraint * c)3852 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3853 int idx, struct event_constraint *c)
3854 {
3855 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3856 struct intel_excl_states *xlo;
3857 int tid = cpuc->excl_thread_id;
3858 int is_excl, i, w;
3859
3860 /*
3861 * validating a group does not require
3862 * enforcing cross-thread exclusion
3863 */
3864 if (cpuc->is_fake || !is_ht_workaround_enabled())
3865 return c;
3866
3867 /*
3868 * no exclusion needed
3869 */
3870 if (WARN_ON_ONCE(!excl_cntrs))
3871 return c;
3872
3873 /*
3874 * because we modify the constraint, we need
3875 * to make a copy. Static constraints come
3876 * from static const tables.
3877 *
3878 * only needed when constraint has not yet
3879 * been cloned (marked dynamic)
3880 */
3881 c = dyn_constraint(cpuc, c, idx);
3882
3883 /*
3884 * From here on, the constraint is dynamic.
3885 * Either it was just allocated above, or it
3886 * was allocated during a earlier invocation
3887 * of this function
3888 */
3889
3890 /*
3891 * state of sibling HT
3892 */
3893 xlo = &excl_cntrs->states[tid ^ 1];
3894
3895 /*
3896 * event requires exclusive counter access
3897 * across HT threads
3898 */
3899 is_excl = c->flags & PERF_X86_EVENT_EXCL;
3900 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3901 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3902 if (!cpuc->n_excl++)
3903 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3904 }
3905
3906 /*
3907 * Modify static constraint with current dynamic
3908 * state of thread
3909 *
3910 * EXCLUSIVE: sibling counter measuring exclusive event
3911 * SHARED : sibling counter measuring non-exclusive event
3912 * UNUSED : sibling counter unused
3913 */
3914 w = c->weight;
3915 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3916 /*
3917 * exclusive event in sibling counter
3918 * our corresponding counter cannot be used
3919 * regardless of our event
3920 */
3921 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3922 __clear_bit(i, c->idxmsk);
3923 w--;
3924 continue;
3925 }
3926 /*
3927 * if measuring an exclusive event, sibling
3928 * measuring non-exclusive, then counter cannot
3929 * be used
3930 */
3931 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3932 __clear_bit(i, c->idxmsk);
3933 w--;
3934 continue;
3935 }
3936 }
3937
3938 /*
3939 * if we return an empty mask, then switch
3940 * back to static empty constraint to avoid
3941 * the cost of freeing later on
3942 */
3943 if (!w)
3944 c = &emptyconstraint;
3945
3946 c->weight = w;
3947
3948 return c;
3949 }
3950
3951 static struct event_constraint *
intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3952 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3953 struct perf_event *event)
3954 {
3955 struct event_constraint *c1, *c2;
3956
3957 c1 = cpuc->event_constraint[idx];
3958
3959 /*
3960 * first time only
3961 * - static constraint: no change across incremental scheduling calls
3962 * - dynamic constraint: handled by intel_get_excl_constraints()
3963 */
3964 c2 = __intel_get_event_constraints(cpuc, idx, event);
3965 if (c1) {
3966 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3967 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3968 c1->weight = c2->weight;
3969 c2 = c1;
3970 }
3971
3972 if (cpuc->excl_cntrs)
3973 return intel_get_excl_constraints(cpuc, event, idx, c2);
3974
3975 if (event->hw.dyn_constraint != ~0ULL) {
3976 c2 = dyn_constraint(cpuc, c2, idx);
3977 c2->idxmsk64 &= event->hw.dyn_constraint;
3978 c2->weight = hweight64(c2->idxmsk64);
3979 }
3980
3981 return c2;
3982 }
3983
intel_put_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3984 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3985 struct perf_event *event)
3986 {
3987 struct hw_perf_event *hwc = &event->hw;
3988 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3989 int tid = cpuc->excl_thread_id;
3990 struct intel_excl_states *xl;
3991
3992 /*
3993 * nothing needed if in group validation mode
3994 */
3995 if (cpuc->is_fake)
3996 return;
3997
3998 if (WARN_ON_ONCE(!excl_cntrs))
3999 return;
4000
4001 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
4002 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
4003 if (!--cpuc->n_excl)
4004 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
4005 }
4006
4007 /*
4008 * If event was actually assigned, then mark the counter state as
4009 * unused now.
4010 */
4011 if (hwc->idx >= 0) {
4012 xl = &excl_cntrs->states[tid];
4013
4014 /*
4015 * put_constraint may be called from x86_schedule_events()
4016 * which already has the lock held so here make locking
4017 * conditional.
4018 */
4019 if (!xl->sched_started)
4020 raw_spin_lock(&excl_cntrs->lock);
4021
4022 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
4023
4024 if (!xl->sched_started)
4025 raw_spin_unlock(&excl_cntrs->lock);
4026 }
4027 }
4028
4029 static void
intel_put_shared_regs_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4030 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
4031 struct perf_event *event)
4032 {
4033 struct hw_perf_event_extra *reg;
4034
4035 reg = &event->hw.extra_reg;
4036 if (reg->idx != EXTRA_REG_NONE)
4037 __intel_shared_reg_put_constraints(cpuc, reg);
4038
4039 reg = &event->hw.branch_reg;
4040 if (reg->idx != EXTRA_REG_NONE)
4041 __intel_shared_reg_put_constraints(cpuc, reg);
4042 }
4043
intel_put_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4044 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
4045 struct perf_event *event)
4046 {
4047 intel_put_shared_regs_event_constraints(cpuc, event);
4048
4049 /*
4050 * is PMU has exclusive counter restrictions, then
4051 * all events are subject to and must call the
4052 * put_excl_constraints() routine
4053 */
4054 if (cpuc->excl_cntrs)
4055 intel_put_excl_constraints(cpuc, event);
4056 }
4057
intel_pebs_aliases_core2(struct perf_event * event)4058 static void intel_pebs_aliases_core2(struct perf_event *event)
4059 {
4060 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
4061 /*
4062 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
4063 * (0x003c) so that we can use it with PEBS.
4064 *
4065 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
4066 * PEBS capable. However we can use INST_RETIRED.ANY_P
4067 * (0x00c0), which is a PEBS capable event, to get the same
4068 * count.
4069 *
4070 * INST_RETIRED.ANY_P counts the number of cycles that retires
4071 * CNTMASK instructions. By setting CNTMASK to a value (16)
4072 * larger than the maximum number of instructions that can be
4073 * retired per cycle (4) and then inverting the condition, we
4074 * count all cycles that retire 16 or less instructions, which
4075 * is every cycle.
4076 *
4077 * Thereby we gain a PEBS capable cycle counter.
4078 */
4079 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
4080
4081 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
4082 event->hw.config = alt_config;
4083 }
4084 }
4085
intel_pebs_aliases_snb(struct perf_event * event)4086 static void intel_pebs_aliases_snb(struct perf_event *event)
4087 {
4088 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
4089 /*
4090 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
4091 * (0x003c) so that we can use it with PEBS.
4092 *
4093 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
4094 * PEBS capable. However we can use UOPS_RETIRED.ALL
4095 * (0x01c2), which is a PEBS capable event, to get the same
4096 * count.
4097 *
4098 * UOPS_RETIRED.ALL counts the number of cycles that retires
4099 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
4100 * larger than the maximum number of micro-ops that can be
4101 * retired per cycle (4) and then inverting the condition, we
4102 * count all cycles that retire 16 or less micro-ops, which
4103 * is every cycle.
4104 *
4105 * Thereby we gain a PEBS capable cycle counter.
4106 */
4107 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
4108
4109 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
4110 event->hw.config = alt_config;
4111 }
4112 }
4113
intel_pebs_aliases_precdist(struct perf_event * event)4114 static void intel_pebs_aliases_precdist(struct perf_event *event)
4115 {
4116 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
4117 /*
4118 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
4119 * (0x003c) so that we can use it with PEBS.
4120 *
4121 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
4122 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
4123 * (0x01c0), which is a PEBS capable event, to get the same
4124 * count.
4125 *
4126 * The PREC_DIST event has special support to minimize sample
4127 * shadowing effects. One drawback is that it can be
4128 * only programmed on counter 1, but that seems like an
4129 * acceptable trade off.
4130 */
4131 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
4132
4133 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
4134 event->hw.config = alt_config;
4135 }
4136 }
4137
intel_pebs_aliases_ivb(struct perf_event * event)4138 static void intel_pebs_aliases_ivb(struct perf_event *event)
4139 {
4140 if (event->attr.precise_ip < 3)
4141 return intel_pebs_aliases_snb(event);
4142 return intel_pebs_aliases_precdist(event);
4143 }
4144
intel_pebs_aliases_skl(struct perf_event * event)4145 static void intel_pebs_aliases_skl(struct perf_event *event)
4146 {
4147 if (event->attr.precise_ip < 3)
4148 return intel_pebs_aliases_core2(event);
4149 return intel_pebs_aliases_precdist(event);
4150 }
4151
intel_pmu_large_pebs_flags(struct perf_event * event)4152 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
4153 {
4154 unsigned long flags = x86_pmu.large_pebs_flags;
4155
4156 if (event->attr.use_clockid)
4157 flags &= ~PERF_SAMPLE_TIME;
4158 if (!event->attr.exclude_kernel)
4159 flags &= ~PERF_SAMPLE_REGS_USER;
4160 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
4161 flags &= ~PERF_SAMPLE_REGS_USER;
4162 if (event->attr.sample_regs_intr & ~PEBS_GP_REGS)
4163 flags &= ~PERF_SAMPLE_REGS_INTR;
4164 return flags;
4165 }
4166
intel_pmu_bts_config(struct perf_event * event)4167 static int intel_pmu_bts_config(struct perf_event *event)
4168 {
4169 struct perf_event_attr *attr = &event->attr;
4170
4171 if (unlikely(intel_pmu_has_bts(event))) {
4172 /* BTS is not supported by this architecture. */
4173 if (!x86_pmu.bts_active)
4174 return -EOPNOTSUPP;
4175
4176 /* BTS is currently only allowed for user-mode. */
4177 if (!attr->exclude_kernel)
4178 return -EOPNOTSUPP;
4179
4180 /* BTS is not allowed for precise events. */
4181 if (attr->precise_ip)
4182 return -EOPNOTSUPP;
4183
4184 /* disallow bts if conflicting events are present */
4185 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
4186 return -EBUSY;
4187
4188 event->destroy = hw_perf_lbr_event_destroy;
4189 }
4190
4191 return 0;
4192 }
4193
core_pmu_hw_config(struct perf_event * event)4194 static int core_pmu_hw_config(struct perf_event *event)
4195 {
4196 int ret = x86_pmu_hw_config(event);
4197
4198 if (ret)
4199 return ret;
4200
4201 return intel_pmu_bts_config(event);
4202 }
4203
4204 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \
4205 ((x86_pmu.num_topdown_events - 1) << 8))
4206
is_available_metric_event(struct perf_event * event)4207 static bool is_available_metric_event(struct perf_event *event)
4208 {
4209 return is_metric_event(event) &&
4210 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
4211 }
4212
is_mem_loads_event(struct perf_event * event)4213 static inline bool is_mem_loads_event(struct perf_event *event)
4214 {
4215 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
4216 }
4217
is_mem_loads_aux_event(struct perf_event * event)4218 static inline bool is_mem_loads_aux_event(struct perf_event *event)
4219 {
4220 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
4221 }
4222
require_mem_loads_aux_event(struct perf_event * event)4223 static inline bool require_mem_loads_aux_event(struct perf_event *event)
4224 {
4225 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
4226 return false;
4227
4228 if (is_hybrid())
4229 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big;
4230
4231 return true;
4232 }
4233
intel_pmu_has_cap(struct perf_event * event,int idx)4234 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
4235 {
4236 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
4237
4238 return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
4239 }
4240
intel_pmu_freq_start_period(struct perf_event * event)4241 static u64 intel_pmu_freq_start_period(struct perf_event *event)
4242 {
4243 int type = event->attr.type;
4244 u64 config, factor;
4245 s64 start;
4246
4247 /*
4248 * The 127 is the lowest possible recommended SAV (sample after value)
4249 * for a 4000 freq (default freq), according to the event list JSON file.
4250 * Also, assume the workload is idle 50% time.
4251 */
4252 factor = 64 * 4000;
4253 if (type != PERF_TYPE_HARDWARE && type != PERF_TYPE_HW_CACHE)
4254 goto end;
4255
4256 /*
4257 * The estimation of the start period in the freq mode is
4258 * based on the below assumption.
4259 *
4260 * For a cycles or an instructions event, 1GHZ of the
4261 * underlying platform, 1 IPC. The workload is idle 50% time.
4262 * The start period = 1,000,000,000 * 1 / freq / 2.
4263 * = 500,000,000 / freq
4264 *
4265 * Usually, the branch-related events occur less than the
4266 * instructions event. According to the Intel event list JSON
4267 * file, the SAV (sample after value) of a branch-related event
4268 * is usually 1/4 of an instruction event.
4269 * The start period of branch-related events = 125,000,000 / freq.
4270 *
4271 * The cache-related events occurs even less. The SAV is usually
4272 * 1/20 of an instruction event.
4273 * The start period of cache-related events = 25,000,000 / freq.
4274 */
4275 config = event->attr.config & PERF_HW_EVENT_MASK;
4276 if (type == PERF_TYPE_HARDWARE) {
4277 switch (config) {
4278 case PERF_COUNT_HW_CPU_CYCLES:
4279 case PERF_COUNT_HW_INSTRUCTIONS:
4280 case PERF_COUNT_HW_BUS_CYCLES:
4281 case PERF_COUNT_HW_STALLED_CYCLES_FRONTEND:
4282 case PERF_COUNT_HW_STALLED_CYCLES_BACKEND:
4283 case PERF_COUNT_HW_REF_CPU_CYCLES:
4284 factor = 500000000;
4285 break;
4286 case PERF_COUNT_HW_BRANCH_INSTRUCTIONS:
4287 case PERF_COUNT_HW_BRANCH_MISSES:
4288 factor = 125000000;
4289 break;
4290 case PERF_COUNT_HW_CACHE_REFERENCES:
4291 case PERF_COUNT_HW_CACHE_MISSES:
4292 factor = 25000000;
4293 break;
4294 default:
4295 goto end;
4296 }
4297 }
4298
4299 if (type == PERF_TYPE_HW_CACHE)
4300 factor = 25000000;
4301 end:
4302 /*
4303 * Usually, a prime or a number with less factors (close to prime)
4304 * is chosen as an SAV, which makes it less likely that the sampling
4305 * period synchronizes with some periodic event in the workload.
4306 * Minus 1 to make it at least avoiding values near power of twos
4307 * for the default freq.
4308 */
4309 start = DIV_ROUND_UP_ULL(factor, event->attr.sample_freq) - 1;
4310
4311 if (start > x86_pmu.max_period)
4312 start = x86_pmu.max_period;
4313
4314 if (x86_pmu.limit_period)
4315 x86_pmu.limit_period(event, &start);
4316
4317 return start;
4318 }
4319
intel_pmu_has_acr(struct pmu * pmu)4320 static inline bool intel_pmu_has_acr(struct pmu *pmu)
4321 {
4322 return !!hybrid(pmu, acr_cause_mask64);
4323 }
4324
intel_pmu_is_acr_group(struct perf_event * event)4325 static bool intel_pmu_is_acr_group(struct perf_event *event)
4326 {
4327 /* The group leader has the ACR flag set */
4328 if (is_acr_event_group(event))
4329 return true;
4330
4331 /* The acr_mask is set */
4332 if (event->attr.config2)
4333 return true;
4334
4335 return false;
4336 }
4337
intel_pmu_has_pebs_counter_group(struct pmu * pmu)4338 static inline bool intel_pmu_has_pebs_counter_group(struct pmu *pmu)
4339 {
4340 u64 caps;
4341
4342 if (x86_pmu.intel_cap.pebs_format >= 6 && x86_pmu.intel_cap.pebs_baseline)
4343 return true;
4344
4345 caps = hybrid(pmu, arch_pebs_cap).caps;
4346 if (x86_pmu.arch_pebs && (caps & ARCH_PEBS_CNTR_MASK))
4347 return true;
4348
4349 return false;
4350 }
4351
intel_pmu_set_acr_cntr_constr(struct perf_event * event,u64 * cause_mask,int * num)4352 static inline void intel_pmu_set_acr_cntr_constr(struct perf_event *event,
4353 u64 *cause_mask, int *num)
4354 {
4355 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cntr_mask64);
4356 *cause_mask |= event->attr.config2;
4357 *num += 1;
4358 }
4359
intel_pmu_set_acr_caused_constr(struct perf_event * event,int idx,u64 cause_mask)4360 static inline void intel_pmu_set_acr_caused_constr(struct perf_event *event,
4361 int idx, u64 cause_mask)
4362 {
4363 if (test_bit(idx, (unsigned long *)&cause_mask))
4364 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cause_mask64);
4365 }
4366
intel_pmu_hw_config(struct perf_event * event)4367 static int intel_pmu_hw_config(struct perf_event *event)
4368 {
4369 int ret = x86_pmu_hw_config(event);
4370
4371 if (ret)
4372 return ret;
4373
4374 ret = intel_pmu_bts_config(event);
4375 if (ret)
4376 return ret;
4377
4378 if (event->attr.freq && event->attr.sample_freq) {
4379 event->hw.sample_period = intel_pmu_freq_start_period(event);
4380 event->hw.last_period = event->hw.sample_period;
4381 local64_set(&event->hw.period_left, event->hw.sample_period);
4382 }
4383
4384 if (event->attr.precise_ip) {
4385 struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap);
4386
4387 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
4388 return -EINVAL;
4389
4390 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
4391 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
4392 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) &&
4393 !has_aux_action(event)) {
4394 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
4395 event->attach_state |= PERF_ATTACH_SCHED_CB;
4396 }
4397 }
4398 if (x86_pmu.pebs_aliases)
4399 x86_pmu.pebs_aliases(event);
4400
4401 if (x86_pmu.arch_pebs) {
4402 u64 cntr_mask = hybrid(event->pmu, intel_ctrl) &
4403 ~GLOBAL_CTRL_EN_PERF_METRICS;
4404 u64 pebs_mask = event->attr.precise_ip >= 3 ?
4405 pebs_cap.pdists : pebs_cap.counters;
4406 if (cntr_mask != pebs_mask)
4407 event->hw.dyn_constraint &= pebs_mask;
4408 }
4409 }
4410
4411 if (needs_branch_stack(event)) {
4412 /* Avoid branch stack setup for counting events in SAMPLE READ */
4413 if (is_sampling_event(event) ||
4414 !(event->attr.sample_type & PERF_SAMPLE_READ))
4415 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK;
4416 }
4417
4418 if (branch_sample_counters(event)) {
4419 struct perf_event *leader, *sibling;
4420 int num = 0;
4421
4422 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) ||
4423 (event->attr.config & ~INTEL_ARCH_EVENT_MASK))
4424 return -EINVAL;
4425
4426 /*
4427 * The branch counter logging is not supported in the call stack
4428 * mode yet, since we cannot simply flush the LBR during e.g.,
4429 * multiplexing. Also, there is no obvious usage with the call
4430 * stack mode. Simply forbids it for now.
4431 *
4432 * If any events in the group enable the branch counter logging
4433 * feature, the group is treated as a branch counter logging
4434 * group, which requires the extra space to store the counters.
4435 */
4436 leader = event->group_leader;
4437 if (branch_sample_call_stack(leader))
4438 return -EINVAL;
4439 if (branch_sample_counters(leader)) {
4440 num++;
4441 leader->hw.dyn_constraint &= x86_pmu.lbr_counters;
4442 }
4443 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS;
4444
4445 for_each_sibling_event(sibling, leader) {
4446 if (branch_sample_call_stack(sibling))
4447 return -EINVAL;
4448 if (branch_sample_counters(sibling)) {
4449 num++;
4450 sibling->hw.dyn_constraint &= x86_pmu.lbr_counters;
4451 }
4452 }
4453
4454 if (num > fls(x86_pmu.lbr_counters))
4455 return -EINVAL;
4456 /*
4457 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't
4458 * require any branch stack setup.
4459 * Clear the bit to avoid unnecessary branch stack setup.
4460 */
4461 if (0 == (event->attr.branch_sample_type &
4462 ~(PERF_SAMPLE_BRANCH_PLM_ALL |
4463 PERF_SAMPLE_BRANCH_COUNTERS)))
4464 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK;
4465
4466 /*
4467 * Force the leader to be a LBR event. So LBRs can be reset
4468 * with the leader event. See intel_pmu_lbr_del() for details.
4469 */
4470 if (!intel_pmu_needs_branch_stack(leader))
4471 return -EINVAL;
4472 }
4473
4474 if (intel_pmu_needs_branch_stack(event)) {
4475 ret = intel_pmu_setup_lbr_filter(event);
4476 if (ret)
4477 return ret;
4478 event->attach_state |= PERF_ATTACH_SCHED_CB;
4479
4480 /*
4481 * BTS is set up earlier in this path, so don't account twice
4482 */
4483 if (!unlikely(intel_pmu_has_bts(event))) {
4484 /* disallow lbr if conflicting events are present */
4485 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
4486 return -EBUSY;
4487
4488 event->destroy = hw_perf_lbr_event_destroy;
4489 }
4490 }
4491
4492 if (event->attr.aux_output) {
4493 if (!event->attr.precise_ip)
4494 return -EINVAL;
4495
4496 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
4497 }
4498
4499 if ((event->attr.sample_type & PERF_SAMPLE_READ) &&
4500 intel_pmu_has_pebs_counter_group(event->pmu) &&
4501 is_sampling_event(event) &&
4502 event->attr.precise_ip)
4503 event->group_leader->hw.flags |= PERF_X86_EVENT_PEBS_CNTR;
4504
4505 if (intel_pmu_has_acr(event->pmu) && intel_pmu_is_acr_group(event)) {
4506 struct perf_event *sibling, *leader = event->group_leader;
4507 struct pmu *pmu = event->pmu;
4508 bool has_sw_event = false;
4509 int num = 0, idx = 0;
4510 u64 cause_mask = 0;
4511
4512 /* Not support perf metrics */
4513 if (is_metric_event(event))
4514 return -EINVAL;
4515
4516 /* Not support freq mode */
4517 if (event->attr.freq)
4518 return -EINVAL;
4519
4520 /* PDist is not supported */
4521 if (event->attr.config2 && event->attr.precise_ip > 2)
4522 return -EINVAL;
4523
4524 /* The reload value cannot exceeds the max period */
4525 if (event->attr.sample_period > x86_pmu.max_period)
4526 return -EINVAL;
4527 /*
4528 * The counter-constraints of each event cannot be finalized
4529 * unless the whole group is scanned. However, it's hard
4530 * to know whether the event is the last one of the group.
4531 * Recalculate the counter-constraints for each event when
4532 * adding a new event.
4533 *
4534 * The group is traversed twice, which may be optimized later.
4535 * In the first round,
4536 * - Find all events which do reload when other events
4537 * overflow and set the corresponding counter-constraints
4538 * - Add all events, which can cause other events reload,
4539 * in the cause_mask
4540 * - Error out if the number of events exceeds the HW limit
4541 * - The ACR events must be contiguous.
4542 * Error out if there are non-X86 events between ACR events.
4543 * This is not a HW limit, but a SW limit.
4544 * With the assumption, the intel_pmu_acr_late_setup() can
4545 * easily convert the event idx to counter idx without
4546 * traversing the whole event list.
4547 */
4548 if (!is_x86_event(leader))
4549 return -EINVAL;
4550
4551 if (leader->attr.config2)
4552 intel_pmu_set_acr_cntr_constr(leader, &cause_mask, &num);
4553
4554 if (leader->nr_siblings) {
4555 for_each_sibling_event(sibling, leader) {
4556 if (!is_x86_event(sibling)) {
4557 has_sw_event = true;
4558 continue;
4559 }
4560 if (!sibling->attr.config2)
4561 continue;
4562 if (has_sw_event)
4563 return -EINVAL;
4564 intel_pmu_set_acr_cntr_constr(sibling, &cause_mask, &num);
4565 }
4566 }
4567 if (leader != event && event->attr.config2) {
4568 if (has_sw_event)
4569 return -EINVAL;
4570 intel_pmu_set_acr_cntr_constr(event, &cause_mask, &num);
4571 }
4572
4573 if (hweight64(cause_mask) > hweight64(hybrid(pmu, acr_cause_mask64)) ||
4574 num > hweight64(hybrid(event->pmu, acr_cntr_mask64)))
4575 return -EINVAL;
4576 /*
4577 * In the second round, apply the counter-constraints for
4578 * the events which can cause other events reload.
4579 */
4580 intel_pmu_set_acr_caused_constr(leader, idx++, cause_mask);
4581
4582 if (leader->nr_siblings) {
4583 for_each_sibling_event(sibling, leader)
4584 intel_pmu_set_acr_caused_constr(sibling, idx++, cause_mask);
4585 }
4586
4587 if (leader != event)
4588 intel_pmu_set_acr_caused_constr(event, idx, cause_mask);
4589
4590 leader->hw.flags |= PERF_X86_EVENT_ACR;
4591 }
4592
4593 if ((event->attr.type == PERF_TYPE_HARDWARE) ||
4594 (event->attr.type == PERF_TYPE_HW_CACHE))
4595 return 0;
4596
4597 /*
4598 * Config Topdown slots and metric events
4599 *
4600 * The slots event on Fixed Counter 3 can support sampling,
4601 * which will be handled normally in x86_perf_event_update().
4602 *
4603 * Metric events don't support sampling and require being paired
4604 * with a slots event as group leader. When the slots event
4605 * is used in a metrics group, it too cannot support sampling.
4606 */
4607 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
4608 /* The metrics_clear can only be set for the slots event */
4609 if (event->attr.config1 &&
4610 (!is_slots_event(event) || (event->attr.config1 & ~INTEL_TD_CFG_METRIC_CLEAR)))
4611 return -EINVAL;
4612
4613 if (event->attr.config2)
4614 return -EINVAL;
4615
4616 /*
4617 * The TopDown metrics events and slots event don't
4618 * support any filters.
4619 */
4620 if (event->attr.config & X86_ALL_EVENT_FLAGS)
4621 return -EINVAL;
4622
4623 if (is_available_metric_event(event)) {
4624 struct perf_event *leader = event->group_leader;
4625
4626 /* The metric events don't support sampling. */
4627 if (is_sampling_event(event))
4628 return -EINVAL;
4629
4630 /* The metric events require a slots group leader. */
4631 if (!is_slots_event(leader))
4632 return -EINVAL;
4633
4634 /*
4635 * The leader/SLOTS must not be a sampling event for
4636 * metric use; hardware requires it starts at 0 when used
4637 * in conjunction with MSR_PERF_METRICS.
4638 */
4639 if (is_sampling_event(leader))
4640 return -EINVAL;
4641
4642 event->event_caps |= PERF_EV_CAP_SIBLING;
4643 /*
4644 * Only once we have a METRICs sibling do we
4645 * need TopDown magic.
4646 */
4647 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
4648 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
4649 }
4650 }
4651
4652 /*
4653 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
4654 * doesn't function quite right. As a work-around it needs to always be
4655 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
4656 * The actual count of this second event is irrelevant it just needs
4657 * to be active to make the first event function correctly.
4658 *
4659 * In a group, the auxiliary event must be in front of the load latency
4660 * event. The rule is to simplify the implementation of the check.
4661 * That's because perf cannot have a complete group at the moment.
4662 */
4663 if (require_mem_loads_aux_event(event) &&
4664 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
4665 is_mem_loads_event(event)) {
4666 struct perf_event *leader = event->group_leader;
4667 struct perf_event *sibling = NULL;
4668
4669 /*
4670 * When this memload event is also the first event (no group
4671 * exists yet), then there is no aux event before it.
4672 */
4673 if (leader == event)
4674 return -ENODATA;
4675
4676 if (!is_mem_loads_aux_event(leader)) {
4677 for_each_sibling_event(sibling, leader) {
4678 if (is_mem_loads_aux_event(sibling))
4679 break;
4680 }
4681 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
4682 return -ENODATA;
4683 }
4684 }
4685
4686 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
4687 return 0;
4688
4689 if (x86_pmu.version < 3)
4690 return -EINVAL;
4691
4692 ret = perf_allow_cpu();
4693 if (ret)
4694 return ret;
4695
4696 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
4697
4698 return 0;
4699 }
4700
4701 /*
4702 * Currently, the only caller of this function is the atomic_switch_perf_msrs().
4703 * The host perf context helps to prepare the values of the real hardware for
4704 * a set of msrs that need to be switched atomically in a vmx transaction.
4705 *
4706 * For example, the pseudocode needed to add a new msr should look like:
4707 *
4708 * arr[(*nr)++] = (struct perf_guest_switch_msr){
4709 * .msr = the hardware msr address,
4710 * .host = the value the hardware has when it doesn't run a guest,
4711 * .guest = the value the hardware has when it runs a guest,
4712 * };
4713 *
4714 * These values have nothing to do with the emulated values the guest sees
4715 * when it uses {RD,WR}MSR, which should be handled by the KVM context,
4716 * specifically in the intel_pmu_{get,set}_msr().
4717 */
intel_guest_get_msrs(int * nr,void * data)4718 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
4719 {
4720 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4721 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4722 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data;
4723 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
4724 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
4725 int global_ctrl, pebs_enable;
4726
4727 /*
4728 * In addition to obeying exclude_guest/exclude_host, remove bits being
4729 * used for PEBS when running a guest, because PEBS writes to virtual
4730 * addresses (not physical addresses).
4731 */
4732 *nr = 0;
4733 global_ctrl = (*nr)++;
4734 arr[global_ctrl] = (struct perf_guest_switch_msr){
4735 .msr = MSR_CORE_PERF_GLOBAL_CTRL,
4736 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
4737 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask,
4738 };
4739
4740 if (!x86_pmu.ds_pebs)
4741 return arr;
4742
4743 /*
4744 * If PMU counter has PEBS enabled it is not enough to
4745 * disable counter on a guest entry since PEBS memory
4746 * write can overshoot guest entry and corrupt guest
4747 * memory. Disabling PEBS solves the problem.
4748 *
4749 * Don't do this if the CPU already enforces it.
4750 */
4751 if (x86_pmu.pebs_no_isolation) {
4752 arr[(*nr)++] = (struct perf_guest_switch_msr){
4753 .msr = MSR_IA32_PEBS_ENABLE,
4754 .host = cpuc->pebs_enabled,
4755 .guest = 0,
4756 };
4757 return arr;
4758 }
4759
4760 if (!kvm_pmu || !x86_pmu.pebs_ept)
4761 return arr;
4762
4763 arr[(*nr)++] = (struct perf_guest_switch_msr){
4764 .msr = MSR_IA32_DS_AREA,
4765 .host = (unsigned long)cpuc->ds,
4766 .guest = kvm_pmu->ds_area,
4767 };
4768
4769 if (x86_pmu.intel_cap.pebs_baseline) {
4770 arr[(*nr)++] = (struct perf_guest_switch_msr){
4771 .msr = MSR_PEBS_DATA_CFG,
4772 .host = cpuc->active_pebs_data_cfg,
4773 .guest = kvm_pmu->pebs_data_cfg,
4774 };
4775 }
4776
4777 pebs_enable = (*nr)++;
4778 arr[pebs_enable] = (struct perf_guest_switch_msr){
4779 .msr = MSR_IA32_PEBS_ENABLE,
4780 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask,
4781 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask & kvm_pmu->pebs_enable,
4782 };
4783
4784 if (arr[pebs_enable].host) {
4785 /* Disable guest PEBS if host PEBS is enabled. */
4786 arr[pebs_enable].guest = 0;
4787 } else {
4788 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */
4789 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask;
4790 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask;
4791 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
4792 arr[global_ctrl].guest |= arr[pebs_enable].guest;
4793 }
4794
4795 return arr;
4796 }
4797
core_guest_get_msrs(int * nr,void * data)4798 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data)
4799 {
4800 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4801 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4802 int idx;
4803
4804 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
4805 struct perf_event *event = cpuc->events[idx];
4806
4807 arr[idx].msr = x86_pmu_config_addr(idx);
4808 arr[idx].host = arr[idx].guest = 0;
4809
4810 if (!test_bit(idx, cpuc->active_mask))
4811 continue;
4812
4813 arr[idx].host = arr[idx].guest =
4814 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
4815
4816 if (event->attr.exclude_host)
4817 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4818 else if (event->attr.exclude_guest)
4819 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4820 }
4821
4822 *nr = x86_pmu_max_num_counters(cpuc->pmu);
4823 return arr;
4824 }
4825
core_pmu_enable_event(struct perf_event * event)4826 static void core_pmu_enable_event(struct perf_event *event)
4827 {
4828 if (!event->attr.exclude_host)
4829 x86_pmu_enable_event(event);
4830 }
4831
core_pmu_enable_all(int added)4832 static void core_pmu_enable_all(int added)
4833 {
4834 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4835 int idx;
4836
4837 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
4838 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
4839
4840 if (!test_bit(idx, cpuc->active_mask) ||
4841 cpuc->events[idx]->attr.exclude_host)
4842 continue;
4843
4844 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
4845 }
4846 }
4847
hsw_hw_config(struct perf_event * event)4848 static int hsw_hw_config(struct perf_event *event)
4849 {
4850 int ret = intel_pmu_hw_config(event);
4851
4852 if (ret)
4853 return ret;
4854 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
4855 return 0;
4856 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
4857
4858 /*
4859 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
4860 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
4861 * this combination.
4862 */
4863 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
4864 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
4865 event->attr.precise_ip > 0))
4866 return -EOPNOTSUPP;
4867
4868 if (event_is_checkpointed(event)) {
4869 /*
4870 * Sampling of checkpointed events can cause situations where
4871 * the CPU constantly aborts because of a overflow, which is
4872 * then checkpointed back and ignored. Forbid checkpointing
4873 * for sampling.
4874 *
4875 * But still allow a long sampling period, so that perf stat
4876 * from KVM works.
4877 */
4878 if (event->attr.sample_period > 0 &&
4879 event->attr.sample_period < 0x7fffffff)
4880 return -EOPNOTSUPP;
4881 }
4882 return 0;
4883 }
4884
4885 static struct event_constraint counter0_constraint =
4886 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
4887
4888 static struct event_constraint counter1_constraint =
4889 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2);
4890
4891 static struct event_constraint counter0_1_constraint =
4892 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3);
4893
4894 static struct event_constraint counter2_constraint =
4895 EVENT_CONSTRAINT(0, 0x4, 0);
4896
4897 static struct event_constraint fixed0_constraint =
4898 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
4899
4900 static struct event_constraint fixed0_counter0_constraint =
4901 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
4902
4903 static struct event_constraint fixed0_counter0_1_constraint =
4904 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL);
4905
4906 static struct event_constraint counters_1_7_constraint =
4907 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL);
4908
4909 static struct event_constraint *
hsw_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4910 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4911 struct perf_event *event)
4912 {
4913 struct event_constraint *c;
4914
4915 c = intel_get_event_constraints(cpuc, idx, event);
4916
4917 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
4918 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
4919 if (c->idxmsk64 & (1U << 2))
4920 return &counter2_constraint;
4921 return &emptyconstraint;
4922 }
4923
4924 return c;
4925 }
4926
4927 static struct event_constraint *
icl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4928 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4929 struct perf_event *event)
4930 {
4931 /*
4932 * Fixed counter 0 has less skid.
4933 * Force instruction:ppp in Fixed counter 0
4934 */
4935 if ((event->attr.precise_ip == 3) &&
4936 constraint_match(&fixed0_constraint, event->hw.config))
4937 return &fixed0_constraint;
4938
4939 return hsw_get_event_constraints(cpuc, idx, event);
4940 }
4941
4942 static struct event_constraint *
glc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4943 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4944 struct perf_event *event)
4945 {
4946 struct event_constraint *c;
4947
4948 c = icl_get_event_constraints(cpuc, idx, event);
4949
4950 /*
4951 * The :ppp indicates the Precise Distribution (PDist) facility, which
4952 * is only supported on the GP counter 0. If a :ppp event which is not
4953 * available on the GP counter 0, error out.
4954 * Exception: Instruction PDIR is only available on the fixed counter 0.
4955 */
4956 if ((event->attr.precise_ip == 3) &&
4957 !constraint_match(&fixed0_constraint, event->hw.config)) {
4958 if (c->idxmsk64 & BIT_ULL(0))
4959 return &counter0_constraint;
4960
4961 return &emptyconstraint;
4962 }
4963
4964 return c;
4965 }
4966
4967 static struct event_constraint *
glp_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4968 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4969 struct perf_event *event)
4970 {
4971 struct event_constraint *c;
4972
4973 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
4974 if (event->attr.precise_ip == 3)
4975 return &counter0_constraint;
4976
4977 c = intel_get_event_constraints(cpuc, idx, event);
4978
4979 return c;
4980 }
4981
4982 static struct event_constraint *
tnt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4983 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4984 struct perf_event *event)
4985 {
4986 struct event_constraint *c;
4987
4988 c = intel_get_event_constraints(cpuc, idx, event);
4989
4990 /*
4991 * :ppp means to do reduced skid PEBS,
4992 * which is available on PMC0 and fixed counter 0.
4993 */
4994 if (event->attr.precise_ip == 3) {
4995 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
4996 if (constraint_match(&fixed0_constraint, event->hw.config))
4997 return &fixed0_counter0_constraint;
4998
4999 return &counter0_constraint;
5000 }
5001
5002 return c;
5003 }
5004
5005 static bool allow_tsx_force_abort = true;
5006
5007 static struct event_constraint *
tfa_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5008 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5009 struct perf_event *event)
5010 {
5011 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
5012
5013 /*
5014 * Without TFA we must not use PMC3.
5015 */
5016 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
5017 c = dyn_constraint(cpuc, c, idx);
5018 c->idxmsk64 &= ~(1ULL << 3);
5019 c->weight--;
5020 }
5021
5022 return c;
5023 }
5024
5025 static struct event_constraint *
adl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5026 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5027 struct perf_event *event)
5028 {
5029 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5030
5031 if (pmu->pmu_type == hybrid_big)
5032 return glc_get_event_constraints(cpuc, idx, event);
5033 else if (pmu->pmu_type == hybrid_small)
5034 return tnt_get_event_constraints(cpuc, idx, event);
5035
5036 WARN_ON(1);
5037 return &emptyconstraint;
5038 }
5039
5040 static struct event_constraint *
cmt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5041 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5042 struct perf_event *event)
5043 {
5044 struct event_constraint *c;
5045
5046 c = intel_get_event_constraints(cpuc, idx, event);
5047
5048 /*
5049 * The :ppp indicates the Precise Distribution (PDist) facility, which
5050 * is only supported on the GP counter 0 & 1 and Fixed counter 0.
5051 * If a :ppp event which is not available on the above eligible counters,
5052 * error out.
5053 */
5054 if (event->attr.precise_ip == 3) {
5055 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */
5056 if (constraint_match(&fixed0_constraint, event->hw.config)) {
5057 /* The fixed counter 0 doesn't support LBR event logging. */
5058 if (branch_sample_counters(event))
5059 return &counter0_1_constraint;
5060 else
5061 return &fixed0_counter0_1_constraint;
5062 }
5063
5064 switch (c->idxmsk64 & 0x3ull) {
5065 case 0x1:
5066 return &counter0_constraint;
5067 case 0x2:
5068 return &counter1_constraint;
5069 case 0x3:
5070 return &counter0_1_constraint;
5071 }
5072 return &emptyconstraint;
5073 }
5074
5075 return c;
5076 }
5077
5078 static struct event_constraint *
rwc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5079 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5080 struct perf_event *event)
5081 {
5082 struct event_constraint *c;
5083
5084 c = glc_get_event_constraints(cpuc, idx, event);
5085
5086 /* The Retire Latency is not supported by the fixed counter 0. */
5087 if (event->attr.precise_ip &&
5088 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
5089 constraint_match(&fixed0_constraint, event->hw.config)) {
5090 /*
5091 * The Instruction PDIR is only available
5092 * on the fixed counter 0. Error out for this case.
5093 */
5094 if (event->attr.precise_ip == 3)
5095 return &emptyconstraint;
5096 return &counters_1_7_constraint;
5097 }
5098
5099 return c;
5100 }
5101
5102 static struct event_constraint *
mtl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5103 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5104 struct perf_event *event)
5105 {
5106 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5107
5108 if (pmu->pmu_type == hybrid_big)
5109 return rwc_get_event_constraints(cpuc, idx, event);
5110 if (pmu->pmu_type == hybrid_small)
5111 return cmt_get_event_constraints(cpuc, idx, event);
5112
5113 WARN_ON(1);
5114 return &emptyconstraint;
5115 }
5116
adl_hw_config(struct perf_event * event)5117 static int adl_hw_config(struct perf_event *event)
5118 {
5119 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5120
5121 if (pmu->pmu_type == hybrid_big)
5122 return hsw_hw_config(event);
5123 else if (pmu->pmu_type == hybrid_small)
5124 return intel_pmu_hw_config(event);
5125
5126 WARN_ON(1);
5127 return -EOPNOTSUPP;
5128 }
5129
adl_get_hybrid_cpu_type(void)5130 static enum intel_cpu_type adl_get_hybrid_cpu_type(void)
5131 {
5132 return INTEL_CPU_TYPE_CORE;
5133 }
5134
erratum_hsw11(struct perf_event * event)5135 static inline bool erratum_hsw11(struct perf_event *event)
5136 {
5137 return (event->hw.config & INTEL_ARCH_EVENT_MASK) ==
5138 X86_CONFIG(.event=0xc0, .umask=0x01);
5139 }
5140
5141 static struct event_constraint *
arl_h_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5142 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5143 struct perf_event *event)
5144 {
5145 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5146
5147 if (pmu->pmu_type == hybrid_tiny)
5148 return cmt_get_event_constraints(cpuc, idx, event);
5149
5150 return mtl_get_event_constraints(cpuc, idx, event);
5151 }
5152
arl_h_hw_config(struct perf_event * event)5153 static int arl_h_hw_config(struct perf_event *event)
5154 {
5155 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5156
5157 if (pmu->pmu_type == hybrid_tiny)
5158 return intel_pmu_hw_config(event);
5159
5160 return adl_hw_config(event);
5161 }
5162
5163 /*
5164 * The HSW11 requires a period larger than 100 which is the same as the BDM11.
5165 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL.
5166 *
5167 * The message 'interrupt took too long' can be observed on any counter which
5168 * was armed with a period < 32 and two events expired in the same NMI.
5169 * A minimum period of 32 is enforced for the rest of the events.
5170 */
hsw_limit_period(struct perf_event * event,s64 * left)5171 static void hsw_limit_period(struct perf_event *event, s64 *left)
5172 {
5173 *left = max(*left, erratum_hsw11(event) ? 128 : 32);
5174 }
5175
5176 /*
5177 * Broadwell:
5178 *
5179 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
5180 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
5181 * the two to enforce a minimum period of 128 (the smallest value that has bits
5182 * 0-5 cleared and >= 100).
5183 *
5184 * Because of how the code in x86_perf_event_set_period() works, the truncation
5185 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
5186 * to make up for the 'lost' events due to carrying the 'error' in period_left.
5187 *
5188 * Therefore the effective (average) period matches the requested period,
5189 * despite coarser hardware granularity.
5190 */
bdw_limit_period(struct perf_event * event,s64 * left)5191 static void bdw_limit_period(struct perf_event *event, s64 *left)
5192 {
5193 if (erratum_hsw11(event)) {
5194 if (*left < 128)
5195 *left = 128;
5196 *left &= ~0x3fULL;
5197 }
5198 }
5199
nhm_limit_period(struct perf_event * event,s64 * left)5200 static void nhm_limit_period(struct perf_event *event, s64 *left)
5201 {
5202 *left = max(*left, 32LL);
5203 }
5204
glc_limit_period(struct perf_event * event,s64 * left)5205 static void glc_limit_period(struct perf_event *event, s64 *left)
5206 {
5207 if (event->attr.precise_ip == 3)
5208 *left = max(*left, 128LL);
5209 }
5210
5211 PMU_FORMAT_ATTR(event, "config:0-7" );
5212 PMU_FORMAT_ATTR(umask, "config:8-15" );
5213 PMU_FORMAT_ATTR(edge, "config:18" );
5214 PMU_FORMAT_ATTR(pc, "config:19" );
5215 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
5216 PMU_FORMAT_ATTR(inv, "config:23" );
5217 PMU_FORMAT_ATTR(cmask, "config:24-31" );
5218 PMU_FORMAT_ATTR(in_tx, "config:32" );
5219 PMU_FORMAT_ATTR(in_tx_cp, "config:33" );
5220 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */
5221
5222 PMU_FORMAT_ATTR(metrics_clear, "config1:0"); /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
5223
umask2_show(struct device * dev,struct device_attribute * attr,char * page)5224 static ssize_t umask2_show(struct device *dev,
5225 struct device_attribute *attr,
5226 char *page)
5227 {
5228 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2;
5229
5230 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2)
5231 return sprintf(page, "config:8-15,40-47\n");
5232
5233 /* Roll back to the old format if umask2 is not supported. */
5234 return sprintf(page, "config:8-15\n");
5235 }
5236
5237 static struct device_attribute format_attr_umask2 =
5238 __ATTR(umask, 0444, umask2_show, NULL);
5239
5240 static struct attribute *format_evtsel_ext_attrs[] = {
5241 &format_attr_umask2.attr,
5242 &format_attr_eq.attr,
5243 &format_attr_metrics_clear.attr,
5244 NULL
5245 };
5246
5247 static umode_t
evtsel_ext_is_visible(struct kobject * kobj,struct attribute * attr,int i)5248 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5249 {
5250 struct device *dev = kobj_to_dev(kobj);
5251 u64 mask;
5252
5253 /*
5254 * The umask and umask2 have different formats but share the
5255 * same attr name. In update mode, the previous value of the
5256 * umask is unconditionally removed before is_visible. If
5257 * umask2 format is not enumerated, it's impossible to roll
5258 * back to the old format.
5259 * Does the check in umask2_show rather than is_visible.
5260 */
5261 if (i == 0)
5262 return attr->mode;
5263
5264 mask = hybrid(dev_get_drvdata(dev), config_mask);
5265 if (i == 1)
5266 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0;
5267
5268 /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
5269 if (i == 2) {
5270 union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap);
5271
5272 return intel_cap.rdpmc_metrics_clear ? attr->mode : 0;
5273 }
5274
5275 return 0;
5276 }
5277
5278 static struct attribute *intel_arch_formats_attr[] = {
5279 &format_attr_event.attr,
5280 &format_attr_umask.attr,
5281 &format_attr_edge.attr,
5282 &format_attr_pc.attr,
5283 &format_attr_inv.attr,
5284 &format_attr_cmask.attr,
5285 NULL,
5286 };
5287
intel_event_sysfs_show(char * page,u64 config)5288 ssize_t intel_event_sysfs_show(char *page, u64 config)
5289 {
5290 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
5291
5292 return x86_event_sysfs_show(page, config, event);
5293 }
5294
allocate_shared_regs(int cpu)5295 static struct intel_shared_regs *allocate_shared_regs(int cpu)
5296 {
5297 struct intel_shared_regs *regs;
5298 int i;
5299
5300 regs = kzalloc_node(sizeof(struct intel_shared_regs),
5301 GFP_KERNEL, cpu_to_node(cpu));
5302 if (regs) {
5303 /*
5304 * initialize the locks to keep lockdep happy
5305 */
5306 for (i = 0; i < EXTRA_REG_MAX; i++)
5307 raw_spin_lock_init(®s->regs[i].lock);
5308
5309 regs->core_id = -1;
5310 }
5311 return regs;
5312 }
5313
allocate_excl_cntrs(int cpu)5314 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
5315 {
5316 struct intel_excl_cntrs *c;
5317
5318 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
5319 GFP_KERNEL, cpu_to_node(cpu));
5320 if (c) {
5321 raw_spin_lock_init(&c->lock);
5322 c->core_id = -1;
5323 }
5324 return c;
5325 }
5326
5327
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)5328 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
5329 {
5330 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
5331
5332 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
5333 cpuc->shared_regs = allocate_shared_regs(cpu);
5334 if (!cpuc->shared_regs)
5335 goto err;
5336 }
5337
5338 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_DYN_CONSTRAINT)) {
5339 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
5340
5341 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
5342 if (!cpuc->constraint_list)
5343 goto err_shared_regs;
5344 }
5345
5346 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
5347 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
5348 if (!cpuc->excl_cntrs)
5349 goto err_constraint_list;
5350
5351 cpuc->excl_thread_id = 0;
5352 }
5353
5354 return 0;
5355
5356 err_constraint_list:
5357 kfree(cpuc->constraint_list);
5358 cpuc->constraint_list = NULL;
5359
5360 err_shared_regs:
5361 kfree(cpuc->shared_regs);
5362 cpuc->shared_regs = NULL;
5363
5364 err:
5365 return -ENOMEM;
5366 }
5367
intel_pmu_cpu_prepare(int cpu)5368 static int intel_pmu_cpu_prepare(int cpu)
5369 {
5370 int ret;
5371
5372 ret = intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
5373 if (ret)
5374 return ret;
5375
5376 return alloc_arch_pebs_buf_on_cpu(cpu);
5377 }
5378
flip_smm_bit(void * data)5379 static void flip_smm_bit(void *data)
5380 {
5381 unsigned long set = *(unsigned long *)data;
5382
5383 if (set > 0) {
5384 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
5385 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
5386 } else {
5387 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
5388 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
5389 }
5390 }
5391
intel_pmu_check_counters_mask(u64 * cntr_mask,u64 * fixed_cntr_mask,u64 * intel_ctrl)5392 static void intel_pmu_check_counters_mask(u64 *cntr_mask,
5393 u64 *fixed_cntr_mask,
5394 u64 *intel_ctrl)
5395 {
5396 unsigned int bit;
5397
5398 bit = fls64(*cntr_mask);
5399 if (bit > INTEL_PMC_MAX_GENERIC) {
5400 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5401 bit, INTEL_PMC_MAX_GENERIC);
5402 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
5403 }
5404 *intel_ctrl = *cntr_mask;
5405
5406 bit = fls64(*fixed_cntr_mask);
5407 if (bit > INTEL_PMC_MAX_FIXED) {
5408 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5409 bit, INTEL_PMC_MAX_FIXED);
5410 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
5411 }
5412
5413 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED;
5414 }
5415
5416 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
5417 u64 cntr_mask,
5418 u64 fixed_cntr_mask,
5419 u64 intel_ctrl);
5420
5421 enum dyn_constr_type {
5422 DYN_CONSTR_NONE,
5423 DYN_CONSTR_BR_CNTR,
5424 DYN_CONSTR_ACR_CNTR,
5425 DYN_CONSTR_ACR_CAUSE,
5426 DYN_CONSTR_PEBS,
5427 DYN_CONSTR_PDIST,
5428
5429 DYN_CONSTR_MAX,
5430 };
5431
5432 static const char * const dyn_constr_type_name[] = {
5433 [DYN_CONSTR_NONE] = "a normal event",
5434 [DYN_CONSTR_BR_CNTR] = "a branch counter logging event",
5435 [DYN_CONSTR_ACR_CNTR] = "an auto-counter reload event",
5436 [DYN_CONSTR_ACR_CAUSE] = "an auto-counter reload cause event",
5437 [DYN_CONSTR_PEBS] = "a PEBS event",
5438 [DYN_CONSTR_PDIST] = "a PEBS PDIST event",
5439 };
5440
__intel_pmu_check_dyn_constr(struct event_constraint * constr,enum dyn_constr_type type,u64 mask)5441 static void __intel_pmu_check_dyn_constr(struct event_constraint *constr,
5442 enum dyn_constr_type type, u64 mask)
5443 {
5444 struct event_constraint *c1, *c2;
5445 int new_weight, check_weight;
5446 u64 new_mask, check_mask;
5447
5448 for_each_event_constraint(c1, constr) {
5449 new_mask = c1->idxmsk64 & mask;
5450 new_weight = hweight64(new_mask);
5451
5452 /* ignore topdown perf metrics event */
5453 if (c1->idxmsk64 & INTEL_PMC_MSK_TOPDOWN)
5454 continue;
5455
5456 if (!new_weight && fls64(c1->idxmsk64) < INTEL_PMC_IDX_FIXED) {
5457 pr_info("The event 0x%llx is not supported as %s.\n",
5458 c1->code, dyn_constr_type_name[type]);
5459 }
5460
5461 if (new_weight <= 1)
5462 continue;
5463
5464 for_each_event_constraint(c2, c1 + 1) {
5465 bool check_fail = false;
5466
5467 check_mask = c2->idxmsk64 & mask;
5468 check_weight = hweight64(check_mask);
5469
5470 if (c2->idxmsk64 & INTEL_PMC_MSK_TOPDOWN ||
5471 !check_weight)
5472 continue;
5473
5474 /* The same constraints or no overlap */
5475 if (new_mask == check_mask ||
5476 (new_mask ^ check_mask) == (new_mask | check_mask))
5477 continue;
5478
5479 /*
5480 * A scheduler issue may be triggered in the following cases.
5481 * - Two overlap constraints have the same weight.
5482 * E.g., A constraints: 0x3, B constraints: 0x6
5483 * event counter failure case
5484 * B PMC[2:1] 1
5485 * A PMC[1:0] 0
5486 * A PMC[1:0] FAIL
5487 * - Two overlap constraints have different weight.
5488 * The constraint has a low weight, but has high last bit.
5489 * E.g., A constraints: 0x7, B constraints: 0xC
5490 * event counter failure case
5491 * B PMC[3:2] 2
5492 * A PMC[2:0] 0
5493 * A PMC[2:0] 1
5494 * A PMC[2:0] FAIL
5495 */
5496 if (new_weight == check_weight) {
5497 check_fail = true;
5498 } else if (new_weight < check_weight) {
5499 if ((new_mask | check_mask) != check_mask &&
5500 fls64(new_mask) > fls64(check_mask))
5501 check_fail = true;
5502 } else {
5503 if ((new_mask | check_mask) != new_mask &&
5504 fls64(new_mask) < fls64(check_mask))
5505 check_fail = true;
5506 }
5507
5508 if (check_fail) {
5509 pr_info("The two events 0x%llx and 0x%llx may not be "
5510 "fully scheduled under some circumstances as "
5511 "%s.\n",
5512 c1->code, c2->code, dyn_constr_type_name[type]);
5513 }
5514 }
5515 }
5516 }
5517
intel_pmu_check_dyn_constr(struct pmu * pmu,struct event_constraint * constr,u64 cntr_mask)5518 static void intel_pmu_check_dyn_constr(struct pmu *pmu,
5519 struct event_constraint *constr,
5520 u64 cntr_mask)
5521 {
5522 enum dyn_constr_type i;
5523 u64 mask;
5524
5525 for (i = DYN_CONSTR_NONE; i < DYN_CONSTR_MAX; i++) {
5526 mask = 0;
5527 switch (i) {
5528 case DYN_CONSTR_NONE:
5529 mask = cntr_mask;
5530 break;
5531 case DYN_CONSTR_BR_CNTR:
5532 if (x86_pmu.flags & PMU_FL_BR_CNTR)
5533 mask = x86_pmu.lbr_counters;
5534 break;
5535 case DYN_CONSTR_ACR_CNTR:
5536 mask = hybrid(pmu, acr_cntr_mask64) & GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
5537 break;
5538 case DYN_CONSTR_ACR_CAUSE:
5539 if (hybrid(pmu, acr_cntr_mask64) == hybrid(pmu, acr_cause_mask64))
5540 continue;
5541 mask = hybrid(pmu, acr_cause_mask64) & GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
5542 break;
5543 case DYN_CONSTR_PEBS:
5544 if (x86_pmu.arch_pebs)
5545 mask = hybrid(pmu, arch_pebs_cap).counters;
5546 break;
5547 case DYN_CONSTR_PDIST:
5548 if (x86_pmu.arch_pebs)
5549 mask = hybrid(pmu, arch_pebs_cap).pdists;
5550 break;
5551 default:
5552 pr_warn("Unsupported dynamic constraint type %d\n", i);
5553 }
5554
5555 if (mask)
5556 __intel_pmu_check_dyn_constr(constr, i, mask);
5557 }
5558 }
5559
intel_pmu_check_event_constraints_all(struct pmu * pmu)5560 static void intel_pmu_check_event_constraints_all(struct pmu *pmu)
5561 {
5562 struct event_constraint *event_constraints = hybrid(pmu, event_constraints);
5563 struct event_constraint *pebs_constraints = hybrid(pmu, pebs_constraints);
5564 u64 cntr_mask = hybrid(pmu, cntr_mask64);
5565 u64 fixed_cntr_mask = hybrid(pmu, fixed_cntr_mask64);
5566 u64 intel_ctrl = hybrid(pmu, intel_ctrl);
5567
5568 intel_pmu_check_event_constraints(event_constraints, cntr_mask,
5569 fixed_cntr_mask, intel_ctrl);
5570
5571 if (event_constraints)
5572 intel_pmu_check_dyn_constr(pmu, event_constraints, cntr_mask);
5573
5574 if (pebs_constraints)
5575 intel_pmu_check_dyn_constr(pmu, pebs_constraints, cntr_mask);
5576 }
5577
5578 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs);
5579
intel_pmu_broken_perf_cap(void)5580 static inline bool intel_pmu_broken_perf_cap(void)
5581 {
5582 /* The Perf Metric (Bit 15) is always cleared */
5583 if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE ||
5584 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L)
5585 return true;
5586
5587 return false;
5588 }
5589
__intel_update_pmu_caps(struct pmu * pmu)5590 static inline void __intel_update_pmu_caps(struct pmu *pmu)
5591 {
5592 struct pmu *dest_pmu = pmu ? pmu : x86_get_pmu(smp_processor_id());
5593
5594 if (hybrid(pmu, arch_pebs_cap).caps & ARCH_PEBS_VECR_XMM)
5595 dest_pmu->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
5596 }
5597
__intel_update_large_pebs_flags(struct pmu * pmu)5598 static inline void __intel_update_large_pebs_flags(struct pmu *pmu)
5599 {
5600 u64 caps = hybrid(pmu, arch_pebs_cap).caps;
5601
5602 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
5603 if (caps & ARCH_PEBS_LBR)
5604 x86_pmu.large_pebs_flags |= PERF_SAMPLE_BRANCH_STACK;
5605 if (caps & ARCH_PEBS_CNTR_MASK)
5606 x86_pmu.large_pebs_flags |= PERF_SAMPLE_READ;
5607
5608 if (!(caps & ARCH_PEBS_AUX))
5609 x86_pmu.large_pebs_flags &= ~PERF_SAMPLE_DATA_SRC;
5610 if (!(caps & ARCH_PEBS_GPR)) {
5611 x86_pmu.large_pebs_flags &=
5612 ~(PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
5613 }
5614 }
5615
5616 #define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) << INTEL_PMC_IDX_FIXED))
5617
update_pmu_cap(struct pmu * pmu)5618 static void update_pmu_cap(struct pmu *pmu)
5619 {
5620 unsigned int eax, ebx, ecx, edx;
5621 union cpuid35_eax eax_0;
5622 union cpuid35_ebx ebx_0;
5623 u64 cntrs_mask = 0;
5624 u64 pebs_mask = 0;
5625 u64 pdists_mask = 0;
5626
5627 cpuid(ARCH_PERFMON_EXT_LEAF, &eax_0.full, &ebx_0.full, &ecx, &edx);
5628
5629 if (ebx_0.split.umask2)
5630 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2;
5631 if (ebx_0.split.eq)
5632 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ;
5633
5634 if (eax_0.split.cntr_subleaf) {
5635 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
5636 &eax, &ebx, &ecx, &edx);
5637 hybrid(pmu, cntr_mask64) = eax;
5638 hybrid(pmu, fixed_cntr_mask64) = ebx;
5639 cntrs_mask = counter_mask(eax, ebx);
5640 }
5641
5642 if (eax_0.split.acr_subleaf) {
5643 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_ACR_LEAF,
5644 &eax, &ebx, &ecx, &edx);
5645 /* The mask of the counters which can be reloaded */
5646 hybrid(pmu, acr_cntr_mask64) = counter_mask(eax, ebx);
5647 /* The mask of the counters which can cause a reload of reloadable counters */
5648 hybrid(pmu, acr_cause_mask64) = counter_mask(ecx, edx);
5649 }
5650
5651 /* Bits[5:4] should be set simultaneously if arch-PEBS is supported */
5652 if (eax_0.split.pebs_caps_subleaf && eax_0.split.pebs_cnts_subleaf) {
5653 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_CAP_LEAF,
5654 &eax, &ebx, &ecx, &edx);
5655 hybrid(pmu, arch_pebs_cap).caps = (u64)ebx << 32;
5656
5657 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_COUNTER_LEAF,
5658 &eax, &ebx, &ecx, &edx);
5659 pebs_mask = counter_mask(eax, ecx);
5660 pdists_mask = counter_mask(ebx, edx);
5661 hybrid(pmu, arch_pebs_cap).counters = pebs_mask;
5662 hybrid(pmu, arch_pebs_cap).pdists = pdists_mask;
5663
5664 if (WARN_ON((pebs_mask | pdists_mask) & ~cntrs_mask)) {
5665 x86_pmu.arch_pebs = 0;
5666 } else {
5667 __intel_update_pmu_caps(pmu);
5668 __intel_update_large_pebs_flags(pmu);
5669 }
5670 } else {
5671 WARN_ON(x86_pmu.arch_pebs == 1);
5672 x86_pmu.arch_pebs = 0;
5673 }
5674
5675 if (!intel_pmu_broken_perf_cap()) {
5676 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */
5677 rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities);
5678 }
5679 }
5680
intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu * pmu)5681 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu)
5682 {
5683 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64,
5684 &pmu->intel_ctrl);
5685 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
5686 pmu->unconstrained = (struct event_constraint)
5687 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
5688 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
5689
5690 if (pmu->intel_cap.perf_metrics)
5691 pmu->intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS;
5692 else
5693 pmu->intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS;
5694
5695 intel_pmu_check_event_constraints_all(&pmu->pmu);
5696
5697 intel_pmu_check_extra_regs(pmu->extra_regs);
5698 }
5699
find_hybrid_pmu_for_cpu(void)5700 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void)
5701 {
5702 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
5703 enum intel_cpu_type cpu_type = c->topo.intel_type;
5704 int i;
5705
5706 /*
5707 * This is running on a CPU model that is known to have hybrid
5708 * configurations. But the CPU told us it is not hybrid, shame
5709 * on it. There should be a fixup function provided for these
5710 * troublesome CPUs (->get_hybrid_cpu_type).
5711 */
5712 if (cpu_type == INTEL_CPU_TYPE_UNKNOWN) {
5713 if (x86_pmu.get_hybrid_cpu_type)
5714 cpu_type = x86_pmu.get_hybrid_cpu_type();
5715 else
5716 return NULL;
5717 }
5718
5719 /*
5720 * This essentially just maps between the 'hybrid_cpu_type'
5721 * and 'hybrid_pmu_type' enums except for ARL-H processor
5722 * which needs to compare atom uarch native id since ARL-H
5723 * contains two different atom uarchs.
5724 */
5725 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
5726 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type;
5727 u32 native_id;
5728
5729 if (cpu_type == INTEL_CPU_TYPE_CORE && pmu_type == hybrid_big)
5730 return &x86_pmu.hybrid_pmu[i];
5731 if (cpu_type == INTEL_CPU_TYPE_ATOM) {
5732 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small)
5733 return &x86_pmu.hybrid_pmu[i];
5734
5735 native_id = c->topo.intel_native_model_id;
5736 if (native_id == INTEL_ATOM_SKT_NATIVE_ID && pmu_type == hybrid_small)
5737 return &x86_pmu.hybrid_pmu[i];
5738 if (native_id == INTEL_ATOM_CMT_NATIVE_ID && pmu_type == hybrid_tiny)
5739 return &x86_pmu.hybrid_pmu[i];
5740 }
5741 }
5742
5743 return NULL;
5744 }
5745
init_hybrid_pmu(int cpu)5746 static bool init_hybrid_pmu(int cpu)
5747 {
5748 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5749 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu();
5750
5751 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
5752 cpuc->pmu = NULL;
5753 return false;
5754 }
5755
5756 /* Only check and dump the PMU information for the first CPU */
5757 if (!cpumask_empty(&pmu->supported_cpus))
5758 goto end;
5759
5760 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
5761 update_pmu_cap(&pmu->pmu);
5762
5763 intel_pmu_check_hybrid_pmus(pmu);
5764
5765 if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask))
5766 return false;
5767
5768 pr_info("%s PMU driver: ", pmu->name);
5769
5770 pr_cont("\n");
5771
5772 x86_pmu_show_pmu_cap(&pmu->pmu);
5773
5774 end:
5775 cpumask_set_cpu(cpu, &pmu->supported_cpus);
5776 cpuc->pmu = &pmu->pmu;
5777
5778 return true;
5779 }
5780
intel_pmu_cpu_starting(int cpu)5781 static void intel_pmu_cpu_starting(int cpu)
5782 {
5783 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5784 int core_id = topology_core_id(cpu);
5785 int i;
5786
5787 if (is_hybrid() && !init_hybrid_pmu(cpu))
5788 return;
5789
5790 init_debug_store_on_cpu(cpu);
5791 init_arch_pebs_on_cpu(cpu);
5792 /*
5793 * Deal with CPUs that don't clear their LBRs on power-up, and that may
5794 * even boot with LBRs enabled.
5795 */
5796 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr)
5797 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT);
5798 intel_pmu_lbr_reset();
5799
5800 cpuc->lbr_sel = NULL;
5801
5802 if (x86_pmu.flags & PMU_FL_TFA) {
5803 WARN_ON_ONCE(cpuc->tfa_shadow);
5804 cpuc->tfa_shadow = ~0ULL;
5805 intel_set_tfa(cpuc, false);
5806 }
5807
5808 if (x86_pmu.version > 1)
5809 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
5810
5811 /*
5812 * Disable perf metrics if any added CPU doesn't support it.
5813 *
5814 * Turn off the check for a hybrid architecture, because the
5815 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
5816 * the architecture features. The perf metrics is a model-specific
5817 * feature for now. The corresponding bit should always be 0 on
5818 * a hybrid platform, e.g., Alder Lake.
5819 */
5820 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
5821 union perf_capabilities perf_cap;
5822
5823 rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
5824 if (!perf_cap.perf_metrics) {
5825 x86_pmu.intel_cap.perf_metrics = 0;
5826 x86_pmu.intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS;
5827 }
5828 }
5829
5830 __intel_update_pmu_caps(cpuc->pmu);
5831
5832 if (!cpuc->shared_regs)
5833 return;
5834
5835 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
5836 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
5837 struct intel_shared_regs *pc;
5838
5839 pc = per_cpu(cpu_hw_events, i).shared_regs;
5840 if (pc && pc->core_id == core_id) {
5841 cpuc->kfree_on_online[0] = cpuc->shared_regs;
5842 cpuc->shared_regs = pc;
5843 break;
5844 }
5845 }
5846 cpuc->shared_regs->core_id = core_id;
5847 cpuc->shared_regs->refcnt++;
5848 }
5849
5850 if (x86_pmu.lbr_sel_map)
5851 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
5852
5853 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
5854 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
5855 struct cpu_hw_events *sibling;
5856 struct intel_excl_cntrs *c;
5857
5858 sibling = &per_cpu(cpu_hw_events, i);
5859 c = sibling->excl_cntrs;
5860 if (c && c->core_id == core_id) {
5861 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
5862 cpuc->excl_cntrs = c;
5863 if (!sibling->excl_thread_id)
5864 cpuc->excl_thread_id = 1;
5865 break;
5866 }
5867 }
5868 cpuc->excl_cntrs->core_id = core_id;
5869 cpuc->excl_cntrs->refcnt++;
5870 }
5871 }
5872
free_excl_cntrs(struct cpu_hw_events * cpuc)5873 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
5874 {
5875 struct intel_excl_cntrs *c;
5876
5877 c = cpuc->excl_cntrs;
5878 if (c) {
5879 if (c->core_id == -1 || --c->refcnt == 0)
5880 kfree(c);
5881 cpuc->excl_cntrs = NULL;
5882 }
5883
5884 kfree(cpuc->constraint_list);
5885 cpuc->constraint_list = NULL;
5886 }
5887
intel_pmu_cpu_dying(int cpu)5888 static void intel_pmu_cpu_dying(int cpu)
5889 {
5890 fini_debug_store_on_cpu(cpu);
5891 fini_arch_pebs_on_cpu(cpu);
5892 }
5893
intel_cpuc_finish(struct cpu_hw_events * cpuc)5894 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
5895 {
5896 struct intel_shared_regs *pc;
5897
5898 pc = cpuc->shared_regs;
5899 if (pc) {
5900 if (pc->core_id == -1 || --pc->refcnt == 0)
5901 kfree(pc);
5902 cpuc->shared_regs = NULL;
5903 }
5904
5905 free_excl_cntrs(cpuc);
5906 }
5907
intel_pmu_cpu_dead(int cpu)5908 static void intel_pmu_cpu_dead(int cpu)
5909 {
5910 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5911
5912 release_arch_pebs_buf_on_cpu(cpu);
5913 intel_cpuc_finish(cpuc);
5914
5915 if (is_hybrid() && cpuc->pmu)
5916 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
5917 }
5918
intel_pmu_sched_task(struct perf_event_pmu_context * pmu_ctx,struct task_struct * task,bool sched_in)5919 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
5920 struct task_struct *task, bool sched_in)
5921 {
5922 intel_pmu_pebs_sched_task(pmu_ctx, sched_in);
5923 intel_pmu_lbr_sched_task(pmu_ctx, task, sched_in);
5924 }
5925
intel_pmu_check_period(struct perf_event * event,u64 value)5926 static int intel_pmu_check_period(struct perf_event *event, u64 value)
5927 {
5928 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
5929 }
5930
intel_aux_output_init(void)5931 static void intel_aux_output_init(void)
5932 {
5933 /* Refer also intel_pmu_aux_output_match() */
5934 if (x86_pmu.intel_cap.pebs_output_pt_available)
5935 x86_pmu.assign = intel_pmu_assign_event;
5936 }
5937
intel_pmu_aux_output_match(struct perf_event * event)5938 static int intel_pmu_aux_output_match(struct perf_event *event)
5939 {
5940 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */
5941 if (!x86_pmu.intel_cap.pebs_output_pt_available)
5942 return 0;
5943
5944 return is_intel_pt_event(event);
5945 }
5946
intel_pmu_filter(struct pmu * pmu,int cpu,bool * ret)5947 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret)
5948 {
5949 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu);
5950
5951 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus);
5952 }
5953
5954 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
5955
5956 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
5957
5958 PMU_FORMAT_ATTR(frontend, "config1:0-23");
5959
5960 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
5961
5962 static struct attribute *intel_arch3_formats_attr[] = {
5963 &format_attr_event.attr,
5964 &format_attr_umask.attr,
5965 &format_attr_edge.attr,
5966 &format_attr_pc.attr,
5967 &format_attr_any.attr,
5968 &format_attr_inv.attr,
5969 &format_attr_cmask.attr,
5970 NULL,
5971 };
5972
5973 static struct attribute *hsw_format_attr[] = {
5974 &format_attr_in_tx.attr,
5975 &format_attr_in_tx_cp.attr,
5976 &format_attr_offcore_rsp.attr,
5977 &format_attr_ldlat.attr,
5978 NULL
5979 };
5980
5981 static struct attribute *nhm_format_attr[] = {
5982 &format_attr_offcore_rsp.attr,
5983 &format_attr_ldlat.attr,
5984 NULL
5985 };
5986
5987 static struct attribute *slm_format_attr[] = {
5988 &format_attr_offcore_rsp.attr,
5989 NULL
5990 };
5991
5992 static struct attribute *cmt_format_attr[] = {
5993 &format_attr_offcore_rsp.attr,
5994 &format_attr_ldlat.attr,
5995 &format_attr_snoop_rsp.attr,
5996 NULL
5997 };
5998
5999 static struct attribute *skl_format_attr[] = {
6000 &format_attr_frontend.attr,
6001 NULL,
6002 };
6003
6004 static __initconst const struct x86_pmu core_pmu = {
6005 .name = "core",
6006 .handle_irq = x86_pmu_handle_irq,
6007 .disable_all = x86_pmu_disable_all,
6008 .enable_all = core_pmu_enable_all,
6009 .enable = core_pmu_enable_event,
6010 .disable = x86_pmu_disable_event,
6011 .hw_config = core_pmu_hw_config,
6012 .schedule_events = x86_schedule_events,
6013 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
6014 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
6015 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
6016 .event_map = intel_pmu_event_map,
6017 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
6018 .apic = 1,
6019 .large_pebs_flags = LARGE_PEBS_FLAGS,
6020
6021 /*
6022 * Intel PMCs cannot be accessed sanely above 32-bit width,
6023 * so we install an artificial 1<<31 period regardless of
6024 * the generic event period:
6025 */
6026 .max_period = (1ULL<<31) - 1,
6027 .get_event_constraints = intel_get_event_constraints,
6028 .put_event_constraints = intel_put_event_constraints,
6029 .event_constraints = intel_core_event_constraints,
6030 .guest_get_msrs = core_guest_get_msrs,
6031 .format_attrs = intel_arch_formats_attr,
6032 .events_sysfs_show = intel_event_sysfs_show,
6033
6034 /*
6035 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
6036 * together with PMU version 1 and thus be using core_pmu with
6037 * shared_regs. We need following callbacks here to allocate
6038 * it properly.
6039 */
6040 .cpu_prepare = intel_pmu_cpu_prepare,
6041 .cpu_starting = intel_pmu_cpu_starting,
6042 .cpu_dying = intel_pmu_cpu_dying,
6043 .cpu_dead = intel_pmu_cpu_dead,
6044
6045 .check_period = intel_pmu_check_period,
6046
6047 .lbr_reset = intel_pmu_lbr_reset_64,
6048 .lbr_read = intel_pmu_lbr_read_64,
6049 .lbr_save = intel_pmu_lbr_save,
6050 .lbr_restore = intel_pmu_lbr_restore,
6051 };
6052
6053 static __initconst const struct x86_pmu intel_pmu = {
6054 .name = "Intel",
6055 .handle_irq = intel_pmu_handle_irq,
6056 .disable_all = intel_pmu_disable_all,
6057 .enable_all = intel_pmu_enable_all,
6058 .enable = intel_pmu_enable_event,
6059 .disable = intel_pmu_disable_event,
6060 .add = intel_pmu_add_event,
6061 .del = intel_pmu_del_event,
6062 .read = intel_pmu_read_event,
6063 .set_period = intel_pmu_set_period,
6064 .update = intel_pmu_update,
6065 .hw_config = intel_pmu_hw_config,
6066 .schedule_events = x86_schedule_events,
6067 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
6068 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
6069 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
6070 .event_map = intel_pmu_event_map,
6071 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
6072 .apic = 1,
6073 .large_pebs_flags = LARGE_PEBS_FLAGS,
6074 /*
6075 * Intel PMCs cannot be accessed sanely above 32 bit width,
6076 * so we install an artificial 1<<31 period regardless of
6077 * the generic event period:
6078 */
6079 .max_period = (1ULL << 31) - 1,
6080 .get_event_constraints = intel_get_event_constraints,
6081 .put_event_constraints = intel_put_event_constraints,
6082 .pebs_aliases = intel_pebs_aliases_core2,
6083
6084 .format_attrs = intel_arch3_formats_attr,
6085 .events_sysfs_show = intel_event_sysfs_show,
6086
6087 .cpu_prepare = intel_pmu_cpu_prepare,
6088 .cpu_starting = intel_pmu_cpu_starting,
6089 .cpu_dying = intel_pmu_cpu_dying,
6090 .cpu_dead = intel_pmu_cpu_dead,
6091
6092 .guest_get_msrs = intel_guest_get_msrs,
6093 .sched_task = intel_pmu_sched_task,
6094
6095 .check_period = intel_pmu_check_period,
6096
6097 .aux_output_match = intel_pmu_aux_output_match,
6098
6099 .lbr_reset = intel_pmu_lbr_reset_64,
6100 .lbr_read = intel_pmu_lbr_read_64,
6101 .lbr_save = intel_pmu_lbr_save,
6102 .lbr_restore = intel_pmu_lbr_restore,
6103
6104 /*
6105 * SMM has access to all 4 rings and while traditionally SMM code only
6106 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
6107 *
6108 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
6109 * between SMM or not, this results in what should be pure userspace
6110 * counters including SMM data.
6111 *
6112 * This is a clear privilege issue, therefore globally disable
6113 * counting SMM by default.
6114 */
6115 .attr_freeze_on_smi = 1,
6116 };
6117
intel_clovertown_quirk(void)6118 static __init void intel_clovertown_quirk(void)
6119 {
6120 /*
6121 * PEBS is unreliable due to:
6122 *
6123 * AJ67 - PEBS may experience CPL leaks
6124 * AJ68 - PEBS PMI may be delayed by one event
6125 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
6126 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
6127 *
6128 * AJ67 could be worked around by restricting the OS/USR flags.
6129 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
6130 *
6131 * AJ106 could possibly be worked around by not allowing LBR
6132 * usage from PEBS, including the fixup.
6133 * AJ68 could possibly be worked around by always programming
6134 * a pebs_event_reset[0] value and coping with the lost events.
6135 *
6136 * But taken together it might just make sense to not enable PEBS on
6137 * these chips.
6138 */
6139 pr_warn("PEBS disabled due to CPU errata\n");
6140 x86_pmu.ds_pebs = 0;
6141 x86_pmu.pebs_constraints = NULL;
6142 }
6143
6144 static const struct x86_cpu_id isolation_ucodes[] = {
6145 X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f),
6146 X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e),
6147 X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015),
6148 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037),
6149 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a),
6150 X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023),
6151 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014),
6152 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010),
6153 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009),
6154 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009),
6155 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002),
6156 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014),
6157 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021),
6158 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000),
6159 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000),
6160 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c),
6161 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c),
6162 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e),
6163 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e),
6164 {}
6165 };
6166
intel_check_pebs_isolation(void)6167 static void intel_check_pebs_isolation(void)
6168 {
6169 x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes);
6170 }
6171
intel_pebs_isolation_quirk(void)6172 static __init void intel_pebs_isolation_quirk(void)
6173 {
6174 WARN_ON_ONCE(x86_pmu.check_microcode);
6175 x86_pmu.check_microcode = intel_check_pebs_isolation;
6176 intel_check_pebs_isolation();
6177 }
6178
6179 static const struct x86_cpu_id pebs_ucodes[] = {
6180 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028),
6181 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618),
6182 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c),
6183 {}
6184 };
6185
intel_snb_pebs_broken(void)6186 static bool intel_snb_pebs_broken(void)
6187 {
6188 return !x86_match_min_microcode_rev(pebs_ucodes);
6189 }
6190
intel_snb_check_microcode(void)6191 static void intel_snb_check_microcode(void)
6192 {
6193 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
6194 return;
6195
6196 /*
6197 * Serialized by the microcode lock..
6198 */
6199 if (x86_pmu.pebs_broken) {
6200 pr_info("PEBS enabled due to microcode update\n");
6201 x86_pmu.pebs_broken = 0;
6202 } else {
6203 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
6204 x86_pmu.pebs_broken = 1;
6205 }
6206 }
6207
is_lbr_from(unsigned long msr)6208 static bool is_lbr_from(unsigned long msr)
6209 {
6210 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
6211
6212 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
6213 }
6214
6215 /*
6216 * Under certain circumstances, access certain MSR may cause #GP.
6217 * The function tests if the input MSR can be safely accessed.
6218 */
check_msr(unsigned long msr,u64 mask)6219 static bool check_msr(unsigned long msr, u64 mask)
6220 {
6221 u64 val_old, val_new, val_tmp;
6222
6223 /*
6224 * Disable the check for real HW, so we don't
6225 * mess with potentially enabled registers:
6226 */
6227 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
6228 return true;
6229
6230 /*
6231 * Read the current value, change it and read it back to see if it
6232 * matches, this is needed to detect certain hardware emulators
6233 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
6234 */
6235 if (rdmsrq_safe(msr, &val_old))
6236 return false;
6237
6238 /*
6239 * Only change the bits which can be updated by wrmsrq.
6240 */
6241 val_tmp = val_old ^ mask;
6242
6243 if (is_lbr_from(msr))
6244 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
6245
6246 if (wrmsrq_safe(msr, val_tmp) ||
6247 rdmsrq_safe(msr, &val_new))
6248 return false;
6249
6250 /*
6251 * Quirk only affects validation in wrmsr(), so wrmsrq()'s value
6252 * should equal rdmsrq()'s even with the quirk.
6253 */
6254 if (val_new != val_tmp)
6255 return false;
6256
6257 if (is_lbr_from(msr))
6258 val_old = lbr_from_signext_quirk_wr(val_old);
6259
6260 /* Here it's sure that the MSR can be safely accessed.
6261 * Restore the old value and return.
6262 */
6263 wrmsrq(msr, val_old);
6264
6265 return true;
6266 }
6267
intel_sandybridge_quirk(void)6268 static __init void intel_sandybridge_quirk(void)
6269 {
6270 x86_pmu.check_microcode = intel_snb_check_microcode;
6271 cpus_read_lock();
6272 intel_snb_check_microcode();
6273 cpus_read_unlock();
6274 }
6275
6276 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
6277 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
6278 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
6279 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
6280 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
6281 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
6282 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
6283 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
6284 };
6285
intel_arch_events_quirk(void)6286 static __init void intel_arch_events_quirk(void)
6287 {
6288 int bit;
6289
6290 /* disable event that reported as not present by cpuid */
6291 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
6292 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
6293 pr_warn("CPUID marked event: \'%s\' unavailable\n",
6294 intel_arch_events_map[bit].name);
6295 }
6296 }
6297
intel_nehalem_quirk(void)6298 static __init void intel_nehalem_quirk(void)
6299 {
6300 union cpuid10_ebx ebx;
6301
6302 ebx.full = x86_pmu.events_maskl;
6303 if (ebx.split.no_branch_misses_retired) {
6304 /*
6305 * Erratum AAJ80 detected, we work it around by using
6306 * the BR_MISP_EXEC.ANY event. This will over-count
6307 * branch-misses, but it's still much better than the
6308 * architectural event which is often completely bogus:
6309 */
6310 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
6311 ebx.split.no_branch_misses_retired = 0;
6312 x86_pmu.events_maskl = ebx.full;
6313 pr_info("CPU erratum AAJ80 worked around\n");
6314 }
6315 }
6316
6317 /*
6318 * enable software workaround for errata:
6319 * SNB: BJ122
6320 * IVB: BV98
6321 * HSW: HSD29
6322 *
6323 * Only needed when HT is enabled. However detecting
6324 * if HT is enabled is difficult (model specific). So instead,
6325 * we enable the workaround in the early boot, and verify if
6326 * it is needed in a later initcall phase once we have valid
6327 * topology information to check if HT is actually enabled
6328 */
intel_ht_bug(void)6329 static __init void intel_ht_bug(void)
6330 {
6331 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
6332
6333 x86_pmu.start_scheduling = intel_start_scheduling;
6334 x86_pmu.commit_scheduling = intel_commit_scheduling;
6335 x86_pmu.stop_scheduling = intel_stop_scheduling;
6336 }
6337
6338 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
6339 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
6340
6341 /* Haswell special events */
6342 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
6343 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
6344 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
6345 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
6346 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
6347 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
6348 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
6349 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
6350 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
6351 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
6352 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
6353 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
6354
6355 static struct attribute *hsw_events_attrs[] = {
6356 EVENT_PTR(td_slots_issued),
6357 EVENT_PTR(td_slots_retired),
6358 EVENT_PTR(td_fetch_bubbles),
6359 EVENT_PTR(td_total_slots),
6360 EVENT_PTR(td_total_slots_scale),
6361 EVENT_PTR(td_recovery_bubbles),
6362 EVENT_PTR(td_recovery_bubbles_scale),
6363 NULL
6364 };
6365
6366 static struct attribute *hsw_mem_events_attrs[] = {
6367 EVENT_PTR(mem_ld_hsw),
6368 EVENT_PTR(mem_st_hsw),
6369 NULL,
6370 };
6371
6372 static struct attribute *hsw_tsx_events_attrs[] = {
6373 EVENT_PTR(tx_start),
6374 EVENT_PTR(tx_commit),
6375 EVENT_PTR(tx_abort),
6376 EVENT_PTR(tx_capacity),
6377 EVENT_PTR(tx_conflict),
6378 EVENT_PTR(el_start),
6379 EVENT_PTR(el_commit),
6380 EVENT_PTR(el_abort),
6381 EVENT_PTR(el_capacity),
6382 EVENT_PTR(el_conflict),
6383 EVENT_PTR(cycles_t),
6384 EVENT_PTR(cycles_ct),
6385 NULL
6386 };
6387
6388 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
6389 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
6390 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
6391 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
6392
6393 static struct attribute *icl_events_attrs[] = {
6394 EVENT_PTR(mem_ld_hsw),
6395 EVENT_PTR(mem_st_hsw),
6396 NULL,
6397 };
6398
6399 static struct attribute *icl_td_events_attrs[] = {
6400 EVENT_PTR(slots),
6401 EVENT_PTR(td_retiring),
6402 EVENT_PTR(td_bad_spec),
6403 EVENT_PTR(td_fe_bound),
6404 EVENT_PTR(td_be_bound),
6405 NULL,
6406 };
6407
6408 static struct attribute *icl_tsx_events_attrs[] = {
6409 EVENT_PTR(tx_start),
6410 EVENT_PTR(tx_abort),
6411 EVENT_PTR(tx_commit),
6412 EVENT_PTR(tx_capacity_read),
6413 EVENT_PTR(tx_capacity_write),
6414 EVENT_PTR(tx_conflict),
6415 EVENT_PTR(el_start),
6416 EVENT_PTR(el_abort),
6417 EVENT_PTR(el_commit),
6418 EVENT_PTR(el_capacity_read),
6419 EVENT_PTR(el_capacity_write),
6420 EVENT_PTR(el_conflict),
6421 EVENT_PTR(cycles_t),
6422 EVENT_PTR(cycles_ct),
6423 NULL,
6424 };
6425
6426
6427 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
6428 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82");
6429
6430 static struct attribute *glc_events_attrs[] = {
6431 EVENT_PTR(mem_ld_hsw),
6432 EVENT_PTR(mem_st_spr),
6433 EVENT_PTR(mem_ld_aux),
6434 NULL,
6435 };
6436
6437 static struct attribute *glc_td_events_attrs[] = {
6438 EVENT_PTR(slots),
6439 EVENT_PTR(td_retiring),
6440 EVENT_PTR(td_bad_spec),
6441 EVENT_PTR(td_fe_bound),
6442 EVENT_PTR(td_be_bound),
6443 EVENT_PTR(td_heavy_ops),
6444 EVENT_PTR(td_br_mispredict),
6445 EVENT_PTR(td_fetch_lat),
6446 EVENT_PTR(td_mem_bound),
6447 NULL,
6448 };
6449
6450 static struct attribute *glc_tsx_events_attrs[] = {
6451 EVENT_PTR(tx_start),
6452 EVENT_PTR(tx_abort),
6453 EVENT_PTR(tx_commit),
6454 EVENT_PTR(tx_capacity_read),
6455 EVENT_PTR(tx_capacity_write),
6456 EVENT_PTR(tx_conflict),
6457 EVENT_PTR(cycles_t),
6458 EVENT_PTR(cycles_ct),
6459 NULL,
6460 };
6461
freeze_on_smi_show(struct device * cdev,struct device_attribute * attr,char * buf)6462 static ssize_t freeze_on_smi_show(struct device *cdev,
6463 struct device_attribute *attr,
6464 char *buf)
6465 {
6466 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
6467 }
6468
6469 static DEFINE_MUTEX(freeze_on_smi_mutex);
6470
freeze_on_smi_store(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)6471 static ssize_t freeze_on_smi_store(struct device *cdev,
6472 struct device_attribute *attr,
6473 const char *buf, size_t count)
6474 {
6475 unsigned long val;
6476 ssize_t ret;
6477
6478 ret = kstrtoul(buf, 0, &val);
6479 if (ret)
6480 return ret;
6481
6482 if (val > 1)
6483 return -EINVAL;
6484
6485 mutex_lock(&freeze_on_smi_mutex);
6486
6487 if (x86_pmu.attr_freeze_on_smi == val)
6488 goto done;
6489
6490 x86_pmu.attr_freeze_on_smi = val;
6491
6492 cpus_read_lock();
6493 on_each_cpu(flip_smm_bit, &val, 1);
6494 cpus_read_unlock();
6495 done:
6496 mutex_unlock(&freeze_on_smi_mutex);
6497
6498 return count;
6499 }
6500
update_tfa_sched(void * ignored)6501 static void update_tfa_sched(void *ignored)
6502 {
6503 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
6504
6505 /*
6506 * check if PMC3 is used
6507 * and if so force schedule out for all event types all contexts
6508 */
6509 if (test_bit(3, cpuc->active_mask))
6510 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
6511 }
6512
show_sysctl_tfa(struct device * cdev,struct device_attribute * attr,char * buf)6513 static ssize_t show_sysctl_tfa(struct device *cdev,
6514 struct device_attribute *attr,
6515 char *buf)
6516 {
6517 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
6518 }
6519
set_sysctl_tfa(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)6520 static ssize_t set_sysctl_tfa(struct device *cdev,
6521 struct device_attribute *attr,
6522 const char *buf, size_t count)
6523 {
6524 bool val;
6525 ssize_t ret;
6526
6527 ret = kstrtobool(buf, &val);
6528 if (ret)
6529 return ret;
6530
6531 /* no change */
6532 if (val == allow_tsx_force_abort)
6533 return count;
6534
6535 allow_tsx_force_abort = val;
6536
6537 cpus_read_lock();
6538 on_each_cpu(update_tfa_sched, NULL, 1);
6539 cpus_read_unlock();
6540
6541 return count;
6542 }
6543
6544
6545 static DEVICE_ATTR_RW(freeze_on_smi);
6546
branches_show(struct device * cdev,struct device_attribute * attr,char * buf)6547 static ssize_t branches_show(struct device *cdev,
6548 struct device_attribute *attr,
6549 char *buf)
6550 {
6551 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
6552 }
6553
6554 static DEVICE_ATTR_RO(branches);
6555
branch_counter_nr_show(struct device * cdev,struct device_attribute * attr,char * buf)6556 static ssize_t branch_counter_nr_show(struct device *cdev,
6557 struct device_attribute *attr,
6558 char *buf)
6559 {
6560 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters));
6561 }
6562
6563 static DEVICE_ATTR_RO(branch_counter_nr);
6564
branch_counter_width_show(struct device * cdev,struct device_attribute * attr,char * buf)6565 static ssize_t branch_counter_width_show(struct device *cdev,
6566 struct device_attribute *attr,
6567 char *buf)
6568 {
6569 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS);
6570 }
6571
6572 static DEVICE_ATTR_RO(branch_counter_width);
6573
6574 static struct attribute *lbr_attrs[] = {
6575 &dev_attr_branches.attr,
6576 &dev_attr_branch_counter_nr.attr,
6577 &dev_attr_branch_counter_width.attr,
6578 NULL
6579 };
6580
6581 static umode_t
lbr_is_visible(struct kobject * kobj,struct attribute * attr,int i)6582 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
6583 {
6584 /* branches */
6585 if (i == 0)
6586 return x86_pmu.lbr_nr ? attr->mode : 0;
6587
6588 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0;
6589 }
6590
6591 static char pmu_name_str[30];
6592
6593 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str);
6594
6595 static struct attribute *intel_pmu_caps_attrs[] = {
6596 &dev_attr_pmu_name.attr.attr,
6597 NULL
6598 };
6599
6600 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
6601 show_sysctl_tfa,
6602 set_sysctl_tfa);
6603
6604 static struct attribute *intel_pmu_attrs[] = {
6605 &dev_attr_freeze_on_smi.attr,
6606 &dev_attr_allow_tsx_force_abort.attr,
6607 NULL,
6608 };
6609
6610 static umode_t
default_is_visible(struct kobject * kobj,struct attribute * attr,int i)6611 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
6612 {
6613 if (attr == &dev_attr_allow_tsx_force_abort.attr)
6614 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
6615
6616 return attr->mode;
6617 }
6618
6619 static umode_t
tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)6620 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
6621 {
6622 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
6623 }
6624
6625 static umode_t
pebs_is_visible(struct kobject * kobj,struct attribute * attr,int i)6626 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
6627 {
6628 return intel_pmu_has_pebs() ? attr->mode : 0;
6629 }
6630
6631 static umode_t
mem_is_visible(struct kobject * kobj,struct attribute * attr,int i)6632 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i)
6633 {
6634 if (attr == &event_attr_mem_ld_aux.attr.attr)
6635 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0;
6636
6637 return pebs_is_visible(kobj, attr, i);
6638 }
6639
6640 static umode_t
exra_is_visible(struct kobject * kobj,struct attribute * attr,int i)6641 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
6642 {
6643 return x86_pmu.version >= 2 ? attr->mode : 0;
6644 }
6645
6646 static umode_t
td_is_visible(struct kobject * kobj,struct attribute * attr,int i)6647 td_is_visible(struct kobject *kobj, struct attribute *attr, int i)
6648 {
6649 /*
6650 * Hide the perf metrics topdown events
6651 * if the feature is not enumerated.
6652 */
6653 if (x86_pmu.num_topdown_events)
6654 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0;
6655
6656 return attr->mode;
6657 }
6658
6659 PMU_FORMAT_ATTR(acr_mask, "config2:0-63");
6660
6661 static struct attribute *format_acr_attrs[] = {
6662 &format_attr_acr_mask.attr,
6663 NULL
6664 };
6665
6666 static umode_t
acr_is_visible(struct kobject * kobj,struct attribute * attr,int i)6667 acr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
6668 {
6669 struct device *dev = kobj_to_dev(kobj);
6670
6671 return intel_pmu_has_acr(dev_get_drvdata(dev)) ? attr->mode : 0;
6672 }
6673
6674 static struct attribute_group group_events_td = {
6675 .name = "events",
6676 .is_visible = td_is_visible,
6677 };
6678
6679 static struct attribute_group group_events_mem = {
6680 .name = "events",
6681 .is_visible = mem_is_visible,
6682 };
6683
6684 static struct attribute_group group_events_tsx = {
6685 .name = "events",
6686 .is_visible = tsx_is_visible,
6687 };
6688
6689 static struct attribute_group group_caps_gen = {
6690 .name = "caps",
6691 .attrs = intel_pmu_caps_attrs,
6692 };
6693
6694 static struct attribute_group group_caps_lbr = {
6695 .name = "caps",
6696 .attrs = lbr_attrs,
6697 .is_visible = lbr_is_visible,
6698 };
6699
6700 static struct attribute_group group_format_extra = {
6701 .name = "format",
6702 .is_visible = exra_is_visible,
6703 };
6704
6705 static struct attribute_group group_format_extra_skl = {
6706 .name = "format",
6707 .is_visible = exra_is_visible,
6708 };
6709
6710 static struct attribute_group group_format_evtsel_ext = {
6711 .name = "format",
6712 .attrs = format_evtsel_ext_attrs,
6713 .is_visible = evtsel_ext_is_visible,
6714 };
6715
6716 static struct attribute_group group_format_acr = {
6717 .name = "format",
6718 .attrs = format_acr_attrs,
6719 .is_visible = acr_is_visible,
6720 };
6721
6722 static struct attribute_group group_default = {
6723 .attrs = intel_pmu_attrs,
6724 .is_visible = default_is_visible,
6725 };
6726
6727 static const struct attribute_group *attr_update[] = {
6728 &group_events_td,
6729 &group_events_mem,
6730 &group_events_tsx,
6731 &group_caps_gen,
6732 &group_caps_lbr,
6733 &group_format_extra,
6734 &group_format_extra_skl,
6735 &group_format_evtsel_ext,
6736 &group_format_acr,
6737 &group_default,
6738 NULL,
6739 };
6740
6741 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big);
6742 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
6743 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
6744 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
6745 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
6746 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big);
6747 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big);
6748 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big);
6749 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big);
6750
6751 static struct attribute *adl_hybrid_events_attrs[] = {
6752 EVENT_PTR(slots_adl),
6753 EVENT_PTR(td_retiring_adl),
6754 EVENT_PTR(td_bad_spec_adl),
6755 EVENT_PTR(td_fe_bound_adl),
6756 EVENT_PTR(td_be_bound_adl),
6757 EVENT_PTR(td_heavy_ops_adl),
6758 EVENT_PTR(td_br_mis_adl),
6759 EVENT_PTR(td_fetch_lat_adl),
6760 EVENT_PTR(td_mem_bound_adl),
6761 NULL,
6762 };
6763
6764 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small);
6765 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small);
6766 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small);
6767
6768 static struct attribute *lnl_hybrid_events_attrs[] = {
6769 EVENT_PTR(slots_adl),
6770 EVENT_PTR(td_retiring_lnl),
6771 EVENT_PTR(td_bad_spec_adl),
6772 EVENT_PTR(td_fe_bound_lnl),
6773 EVENT_PTR(td_be_bound_lnl),
6774 EVENT_PTR(td_heavy_ops_adl),
6775 EVENT_PTR(td_br_mis_adl),
6776 EVENT_PTR(td_fetch_lat_adl),
6777 EVENT_PTR(td_mem_bound_adl),
6778 NULL
6779 };
6780
6781 /* The event string must be in PMU IDX order. */
6782 EVENT_ATTR_STR_HYBRID(topdown-retiring,
6783 td_retiring_arl_h,
6784 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0",
6785 hybrid_big_small_tiny);
6786 EVENT_ATTR_STR_HYBRID(topdown-bad-spec,
6787 td_bad_spec_arl_h,
6788 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0",
6789 hybrid_big_small_tiny);
6790 EVENT_ATTR_STR_HYBRID(topdown-fe-bound,
6791 td_fe_bound_arl_h,
6792 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0",
6793 hybrid_big_small_tiny);
6794 EVENT_ATTR_STR_HYBRID(topdown-be-bound,
6795 td_be_bound_arl_h,
6796 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0",
6797 hybrid_big_small_tiny);
6798
6799 static struct attribute *arl_h_hybrid_events_attrs[] = {
6800 EVENT_PTR(slots_adl),
6801 EVENT_PTR(td_retiring_arl_h),
6802 EVENT_PTR(td_bad_spec_arl_h),
6803 EVENT_PTR(td_fe_bound_arl_h),
6804 EVENT_PTR(td_be_bound_arl_h),
6805 EVENT_PTR(td_heavy_ops_adl),
6806 EVENT_PTR(td_br_mis_adl),
6807 EVENT_PTR(td_fetch_lat_adl),
6808 EVENT_PTR(td_mem_bound_adl),
6809 NULL,
6810 };
6811
6812 /* Must be in IDX order */
6813 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
6814 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
6815 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big);
6816
6817 static struct attribute *adl_hybrid_mem_attrs[] = {
6818 EVENT_PTR(mem_ld_adl),
6819 EVENT_PTR(mem_st_adl),
6820 EVENT_PTR(mem_ld_aux_adl),
6821 NULL,
6822 };
6823
6824 static struct attribute *mtl_hybrid_mem_attrs[] = {
6825 EVENT_PTR(mem_ld_adl),
6826 EVENT_PTR(mem_st_adl),
6827 NULL
6828 };
6829
6830 EVENT_ATTR_STR_HYBRID(mem-loads,
6831 mem_ld_arl_h,
6832 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3",
6833 hybrid_big_small_tiny);
6834 EVENT_ATTR_STR_HYBRID(mem-stores,
6835 mem_st_arl_h,
6836 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6",
6837 hybrid_big_small_tiny);
6838
6839 static struct attribute *arl_h_hybrid_mem_attrs[] = {
6840 EVENT_PTR(mem_ld_arl_h),
6841 EVENT_PTR(mem_st_arl_h),
6842 NULL,
6843 };
6844
6845 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big);
6846 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big);
6847 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big);
6848 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big);
6849 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big);
6850 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
6851 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big);
6852 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big);
6853
6854 static struct attribute *adl_hybrid_tsx_attrs[] = {
6855 EVENT_PTR(tx_start_adl),
6856 EVENT_PTR(tx_abort_adl),
6857 EVENT_PTR(tx_commit_adl),
6858 EVENT_PTR(tx_capacity_read_adl),
6859 EVENT_PTR(tx_capacity_write_adl),
6860 EVENT_PTR(tx_conflict_adl),
6861 EVENT_PTR(cycles_t_adl),
6862 EVENT_PTR(cycles_ct_adl),
6863 NULL,
6864 };
6865
6866 FORMAT_ATTR_HYBRID(in_tx, hybrid_big);
6867 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big);
6868 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny);
6869 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny);
6870 FORMAT_ATTR_HYBRID(frontend, hybrid_big);
6871
6872 #define ADL_HYBRID_RTM_FORMAT_ATTR \
6873 FORMAT_HYBRID_PTR(in_tx), \
6874 FORMAT_HYBRID_PTR(in_tx_cp)
6875
6876 #define ADL_HYBRID_FORMAT_ATTR \
6877 FORMAT_HYBRID_PTR(offcore_rsp), \
6878 FORMAT_HYBRID_PTR(ldlat), \
6879 FORMAT_HYBRID_PTR(frontend)
6880
6881 static struct attribute *adl_hybrid_extra_attr_rtm[] = {
6882 ADL_HYBRID_RTM_FORMAT_ATTR,
6883 ADL_HYBRID_FORMAT_ATTR,
6884 NULL
6885 };
6886
6887 static struct attribute *adl_hybrid_extra_attr[] = {
6888 ADL_HYBRID_FORMAT_ATTR,
6889 NULL
6890 };
6891
6892 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny);
6893
6894 static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
6895 ADL_HYBRID_RTM_FORMAT_ATTR,
6896 ADL_HYBRID_FORMAT_ATTR,
6897 FORMAT_HYBRID_PTR(snoop_rsp),
6898 NULL
6899 };
6900
6901 static struct attribute *mtl_hybrid_extra_attr[] = {
6902 ADL_HYBRID_FORMAT_ATTR,
6903 FORMAT_HYBRID_PTR(snoop_rsp),
6904 NULL
6905 };
6906
is_attr_for_this_pmu(struct kobject * kobj,struct attribute * attr)6907 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
6908 {
6909 struct device *dev = kobj_to_dev(kobj);
6910 struct x86_hybrid_pmu *pmu =
6911 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6912 struct perf_pmu_events_hybrid_attr *pmu_attr =
6913 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
6914
6915 return pmu->pmu_type & pmu_attr->pmu_type;
6916 }
6917
hybrid_events_is_visible(struct kobject * kobj,struct attribute * attr,int i)6918 static umode_t hybrid_events_is_visible(struct kobject *kobj,
6919 struct attribute *attr, int i)
6920 {
6921 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
6922 }
6923
hybrid_find_supported_cpu(struct x86_hybrid_pmu * pmu)6924 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
6925 {
6926 int cpu = cpumask_first(&pmu->supported_cpus);
6927
6928 return (cpu >= nr_cpu_ids) ? -1 : cpu;
6929 }
6930
hybrid_tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)6931 static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
6932 struct attribute *attr, int i)
6933 {
6934 struct device *dev = kobj_to_dev(kobj);
6935 struct x86_hybrid_pmu *pmu =
6936 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6937 int cpu = hybrid_find_supported_cpu(pmu);
6938
6939 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
6940 }
6941
hybrid_format_is_visible(struct kobject * kobj,struct attribute * attr,int i)6942 static umode_t hybrid_format_is_visible(struct kobject *kobj,
6943 struct attribute *attr, int i)
6944 {
6945 struct device *dev = kobj_to_dev(kobj);
6946 struct x86_hybrid_pmu *pmu =
6947 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6948 struct perf_pmu_format_hybrid_attr *pmu_attr =
6949 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
6950 int cpu = hybrid_find_supported_cpu(pmu);
6951
6952 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0;
6953 }
6954
hybrid_td_is_visible(struct kobject * kobj,struct attribute * attr,int i)6955 static umode_t hybrid_td_is_visible(struct kobject *kobj,
6956 struct attribute *attr, int i)
6957 {
6958 struct device *dev = kobj_to_dev(kobj);
6959 struct x86_hybrid_pmu *pmu =
6960 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6961
6962 if (!is_attr_for_this_pmu(kobj, attr))
6963 return 0;
6964
6965
6966 /* Only the big core supports perf metrics */
6967 if (pmu->pmu_type == hybrid_big)
6968 return pmu->intel_cap.perf_metrics ? attr->mode : 0;
6969
6970 return attr->mode;
6971 }
6972
6973 static struct attribute_group hybrid_group_events_td = {
6974 .name = "events",
6975 .is_visible = hybrid_td_is_visible,
6976 };
6977
6978 static struct attribute_group hybrid_group_events_mem = {
6979 .name = "events",
6980 .is_visible = hybrid_events_is_visible,
6981 };
6982
6983 static struct attribute_group hybrid_group_events_tsx = {
6984 .name = "events",
6985 .is_visible = hybrid_tsx_is_visible,
6986 };
6987
6988 static struct attribute_group hybrid_group_format_extra = {
6989 .name = "format",
6990 .is_visible = hybrid_format_is_visible,
6991 };
6992
intel_hybrid_get_attr_cpus(struct device * dev,struct device_attribute * attr,char * buf)6993 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
6994 struct device_attribute *attr,
6995 char *buf)
6996 {
6997 struct x86_hybrid_pmu *pmu =
6998 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6999
7000 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus);
7001 }
7002
7003 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
7004 static struct attribute *intel_hybrid_cpus_attrs[] = {
7005 &dev_attr_cpus.attr,
7006 NULL,
7007 };
7008
7009 static struct attribute_group hybrid_group_cpus = {
7010 .attrs = intel_hybrid_cpus_attrs,
7011 };
7012
7013 static const struct attribute_group *hybrid_attr_update[] = {
7014 &hybrid_group_events_td,
7015 &hybrid_group_events_mem,
7016 &hybrid_group_events_tsx,
7017 &group_caps_gen,
7018 &group_caps_lbr,
7019 &hybrid_group_format_extra,
7020 &group_format_evtsel_ext,
7021 &group_format_acr,
7022 &group_default,
7023 &hybrid_group_cpus,
7024 NULL,
7025 };
7026
7027 static struct attribute *empty_attrs;
7028
intel_pmu_check_event_constraints(struct event_constraint * event_constraints,u64 cntr_mask,u64 fixed_cntr_mask,u64 intel_ctrl)7029 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
7030 u64 cntr_mask,
7031 u64 fixed_cntr_mask,
7032 u64 intel_ctrl)
7033 {
7034 struct event_constraint *c;
7035
7036 if (!event_constraints)
7037 return;
7038
7039 /*
7040 * event on fixed counter2 (REF_CYCLES) only works on this
7041 * counter, so do not extend mask to generic counters
7042 */
7043 for_each_event_constraint(c, event_constraints) {
7044 /*
7045 * Don't extend the topdown slots and metrics
7046 * events to the generic counters.
7047 */
7048 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
7049 /*
7050 * Disable topdown slots and metrics events,
7051 * if slots event is not in CPUID.
7052 */
7053 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
7054 c->idxmsk64 = 0;
7055 c->weight = hweight64(c->idxmsk64);
7056 continue;
7057 }
7058
7059 if (c->cmask == FIXED_EVENT_FLAGS) {
7060 /* Disabled fixed counters which are not in CPUID */
7061 c->idxmsk64 &= intel_ctrl;
7062
7063 /*
7064 * Don't extend the pseudo-encoding to the
7065 * generic counters
7066 */
7067 if (!use_fixed_pseudo_encoding(c->code))
7068 c->idxmsk64 |= cntr_mask;
7069 }
7070 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED);
7071 c->weight = hweight64(c->idxmsk64);
7072 }
7073 }
7074
intel_pmu_check_extra_regs(struct extra_reg * extra_regs)7075 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
7076 {
7077 struct extra_reg *er;
7078
7079 /*
7080 * Access extra MSR may cause #GP under certain circumstances.
7081 * E.g. KVM doesn't support offcore event
7082 * Check all extra_regs here.
7083 */
7084 if (!extra_regs)
7085 return;
7086
7087 for (er = extra_regs; er->msr; er++) {
7088 er->extra_msr_access = check_msr(er->msr, 0x11UL);
7089 /* Disable LBR select mapping */
7090 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
7091 x86_pmu.lbr_sel_map = NULL;
7092 }
7093 }
7094
intel_pmu_v6_addr_offset(int index,bool eventsel)7095 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel)
7096 {
7097 return MSR_IA32_PMC_V6_STEP * index;
7098 }
7099
7100 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = {
7101 { hybrid_small, "cpu_atom" },
7102 { hybrid_big, "cpu_core" },
7103 { hybrid_tiny, "cpu_lowpower" },
7104 };
7105
intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)7106 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)
7107 {
7108 unsigned long pmus_mask = pmus;
7109 struct x86_hybrid_pmu *pmu;
7110 int idx = 0, bit;
7111
7112 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask);
7113 x86_pmu.hybrid_pmu = kcalloc(x86_pmu.num_hybrid_pmus,
7114 sizeof(struct x86_hybrid_pmu),
7115 GFP_KERNEL);
7116 if (!x86_pmu.hybrid_pmu)
7117 return -ENOMEM;
7118
7119 static_branch_enable(&perf_is_hybrid);
7120 x86_pmu.filter = intel_pmu_filter;
7121
7122 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) {
7123 pmu = &x86_pmu.hybrid_pmu[idx++];
7124 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id;
7125 pmu->name = intel_hybrid_pmu_type_map[bit].name;
7126
7127 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7128 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7129 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
7130 pmu->config_mask = X86_RAW_EVENT_MASK;
7131 pmu->unconstrained = (struct event_constraint)
7132 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
7133 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
7134
7135 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
7136 if (pmu->pmu_type & hybrid_small_tiny) {
7137 pmu->intel_cap.perf_metrics = 0;
7138 pmu->mid_ack = true;
7139 } else if (pmu->pmu_type & hybrid_big) {
7140 pmu->intel_cap.perf_metrics = 1;
7141 pmu->late_ack = true;
7142 }
7143 }
7144
7145 return 0;
7146 }
7147
intel_pmu_ref_cycles_ext(void)7148 static __always_inline void intel_pmu_ref_cycles_ext(void)
7149 {
7150 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED)))
7151 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c;
7152 }
7153
intel_pmu_init_glc(struct pmu * pmu)7154 static __always_inline void intel_pmu_init_glc(struct pmu *pmu)
7155 {
7156 x86_pmu.late_ack = true;
7157 x86_pmu.limit_period = glc_limit_period;
7158 x86_pmu.pebs_aliases = NULL;
7159 x86_pmu.pebs_prec_dist = true;
7160 x86_pmu.pebs_block = true;
7161 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7162 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7163 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
7164 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
7165 x86_pmu.lbr_pt_coexist = true;
7166 x86_pmu.num_topdown_events = 8;
7167 static_call_update(intel_pmu_update_topdown_event,
7168 &icl_update_topdown_event);
7169 static_call_update(intel_pmu_set_topdown_event_period,
7170 &icl_set_topdown_event_period);
7171
7172 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7173 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7174 hybrid(pmu, event_constraints) = intel_glc_event_constraints;
7175 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;
7176
7177 intel_pmu_ref_cycles_ext();
7178 }
7179
intel_pmu_init_grt(struct pmu * pmu)7180 static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
7181 {
7182 x86_pmu.mid_ack = true;
7183 x86_pmu.limit_period = glc_limit_period;
7184 x86_pmu.pebs_aliases = NULL;
7185 x86_pmu.pebs_prec_dist = true;
7186 x86_pmu.pebs_block = true;
7187 x86_pmu.lbr_pt_coexist = true;
7188 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7189 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
7190
7191 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7192 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7193 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
7194 hybrid(pmu, event_constraints) = intel_grt_event_constraints;
7195 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;
7196 hybrid(pmu, extra_regs) = intel_grt_extra_regs;
7197
7198 intel_pmu_ref_cycles_ext();
7199 }
7200
intel_pmu_init_lnc(struct pmu * pmu)7201 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
7202 {
7203 intel_pmu_init_glc(pmu);
7204 hybrid(pmu, event_constraints) = intel_lnc_event_constraints;
7205 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;
7206 hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
7207 }
7208
intel_pmu_init_skt(struct pmu * pmu)7209 static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
7210 {
7211 intel_pmu_init_grt(pmu);
7212 hybrid(pmu, event_constraints) = intel_skt_event_constraints;
7213 hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
7214 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7215 }
7216
intel_pmu_init(void)7217 __init int intel_pmu_init(void)
7218 {
7219 struct attribute **extra_skl_attr = &empty_attrs;
7220 struct attribute **extra_attr = &empty_attrs;
7221 struct attribute **td_attr = &empty_attrs;
7222 struct attribute **mem_attr = &empty_attrs;
7223 struct attribute **tsx_attr = &empty_attrs;
7224 union cpuid10_edx edx;
7225 union cpuid10_eax eax;
7226 union cpuid10_ebx ebx;
7227 unsigned int fixed_mask;
7228 bool pmem = false;
7229 int version, i;
7230 char *name;
7231 struct x86_hybrid_pmu *pmu;
7232
7233 /* Architectural Perfmon was introduced starting with Core "Yonah" */
7234 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
7235 switch (boot_cpu_data.x86) {
7236 case 6:
7237 if (boot_cpu_data.x86_vfm < INTEL_CORE_YONAH)
7238 return p6_pmu_init();
7239 break;
7240 case 11:
7241 return knc_pmu_init();
7242 case 15:
7243 return p4_pmu_init();
7244 }
7245
7246 pr_cont("unsupported CPU family %d model %d ",
7247 boot_cpu_data.x86, boot_cpu_data.x86_model);
7248 return -ENODEV;
7249 }
7250
7251 /*
7252 * Check whether the Architectural PerfMon supports
7253 * Branch Misses Retired hw_event or not.
7254 */
7255 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
7256 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
7257 return -ENODEV;
7258
7259 version = eax.split.version_id;
7260 if (version < 2)
7261 x86_pmu = core_pmu;
7262 else
7263 x86_pmu = intel_pmu;
7264
7265 x86_pmu.version = version;
7266 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0);
7267 x86_pmu.cntval_bits = eax.split.bit_width;
7268 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
7269
7270 x86_pmu.events_maskl = ebx.full;
7271 x86_pmu.events_mask_len = eax.split.mask_length;
7272
7273 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64);
7274 x86_pmu.pebs_capable = PEBS_COUNTER_MASK;
7275 x86_pmu.config_mask = X86_RAW_EVENT_MASK;
7276
7277 /*
7278 * Quirk: v2 perfmon does not report fixed-purpose events, so
7279 * assume at least 3 events, when not running in a hypervisor:
7280 */
7281 if (version > 1 && version < 5) {
7282 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
7283
7284 x86_pmu.fixed_cntr_mask64 =
7285 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0);
7286 } else if (version >= 5)
7287 x86_pmu.fixed_cntr_mask64 = fixed_mask;
7288
7289 if (boot_cpu_has(X86_FEATURE_PDCM)) {
7290 u64 capabilities;
7291
7292 rdmsrq(MSR_IA32_PERF_CAPABILITIES, capabilities);
7293 x86_pmu.intel_cap.capabilities = capabilities;
7294 }
7295
7296 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
7297 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
7298 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
7299 }
7300
7301 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
7302 intel_pmu_arch_lbr_init();
7303
7304 intel_pebs_init();
7305
7306 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
7307
7308 if (version >= 5) {
7309 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
7310 if (x86_pmu.intel_cap.anythread_deprecated)
7311 pr_cont(" AnyThread deprecated, ");
7312 }
7313
7314 /*
7315 * Many features on and after V6 require dynamic constraint,
7316 * e.g., Arch PEBS, ACR.
7317 */
7318 if (version >= 6) {
7319 x86_pmu.flags |= PMU_FL_DYN_CONSTRAINT;
7320 x86_pmu.late_setup = intel_pmu_late_setup;
7321 }
7322
7323 /*
7324 * Install the hw-cache-events table:
7325 */
7326 switch (boot_cpu_data.x86_vfm) {
7327 case INTEL_CORE_YONAH:
7328 pr_cont("Core events, ");
7329 name = "core";
7330 break;
7331
7332 case INTEL_CORE2_MEROM:
7333 x86_add_quirk(intel_clovertown_quirk);
7334 fallthrough;
7335
7336 case INTEL_CORE2_MEROM_L:
7337 case INTEL_CORE2_PENRYN:
7338 case INTEL_CORE2_DUNNINGTON:
7339 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
7340 sizeof(hw_cache_event_ids));
7341
7342 intel_pmu_lbr_init_core();
7343
7344 x86_pmu.event_constraints = intel_core2_event_constraints;
7345 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
7346 pr_cont("Core2 events, ");
7347 name = "core2";
7348 break;
7349
7350 case INTEL_NEHALEM:
7351 case INTEL_NEHALEM_EP:
7352 case INTEL_NEHALEM_EX:
7353 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
7354 sizeof(hw_cache_event_ids));
7355 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
7356 sizeof(hw_cache_extra_regs));
7357
7358 intel_pmu_lbr_init_nhm();
7359
7360 x86_pmu.event_constraints = intel_nehalem_event_constraints;
7361 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
7362 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
7363 x86_pmu.extra_regs = intel_nehalem_extra_regs;
7364 x86_pmu.limit_period = nhm_limit_period;
7365
7366 mem_attr = nhm_mem_events_attrs;
7367
7368 /* UOPS_ISSUED.STALLED_CYCLES */
7369 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
7370 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
7371 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
7372 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
7373 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
7374
7375 intel_pmu_pebs_data_source_nhm();
7376 x86_add_quirk(intel_nehalem_quirk);
7377 x86_pmu.pebs_no_tlb = 1;
7378 extra_attr = nhm_format_attr;
7379
7380 pr_cont("Nehalem events, ");
7381 name = "nehalem";
7382 break;
7383
7384 case INTEL_ATOM_BONNELL:
7385 case INTEL_ATOM_BONNELL_MID:
7386 case INTEL_ATOM_SALTWELL:
7387 case INTEL_ATOM_SALTWELL_MID:
7388 case INTEL_ATOM_SALTWELL_TABLET:
7389 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
7390 sizeof(hw_cache_event_ids));
7391
7392 intel_pmu_lbr_init_atom();
7393
7394 x86_pmu.event_constraints = intel_gen_event_constraints;
7395 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
7396 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
7397 pr_cont("Atom events, ");
7398 name = "bonnell";
7399 break;
7400
7401 case INTEL_ATOM_SILVERMONT:
7402 case INTEL_ATOM_SILVERMONT_D:
7403 case INTEL_ATOM_SILVERMONT_MID:
7404 case INTEL_ATOM_AIRMONT:
7405 case INTEL_ATOM_SILVERMONT_MID2:
7406 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
7407 sizeof(hw_cache_event_ids));
7408 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
7409 sizeof(hw_cache_extra_regs));
7410
7411 intel_pmu_lbr_init_slm();
7412
7413 x86_pmu.event_constraints = intel_slm_event_constraints;
7414 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
7415 x86_pmu.extra_regs = intel_slm_extra_regs;
7416 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7417 td_attr = slm_events_attrs;
7418 extra_attr = slm_format_attr;
7419 pr_cont("Silvermont events, ");
7420 name = "silvermont";
7421 break;
7422
7423 case INTEL_ATOM_GOLDMONT:
7424 case INTEL_ATOM_GOLDMONT_D:
7425 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
7426 sizeof(hw_cache_event_ids));
7427 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
7428 sizeof(hw_cache_extra_regs));
7429
7430 intel_pmu_lbr_init_skl();
7431
7432 x86_pmu.event_constraints = intel_slm_event_constraints;
7433 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
7434 x86_pmu.extra_regs = intel_glm_extra_regs;
7435 /*
7436 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
7437 * for precise cycles.
7438 * :pp is identical to :ppp
7439 */
7440 x86_pmu.pebs_aliases = NULL;
7441 x86_pmu.pebs_prec_dist = true;
7442 x86_pmu.lbr_pt_coexist = true;
7443 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7444 td_attr = glm_events_attrs;
7445 extra_attr = slm_format_attr;
7446 pr_cont("Goldmont events, ");
7447 name = "goldmont";
7448 break;
7449
7450 case INTEL_ATOM_GOLDMONT_PLUS:
7451 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
7452 sizeof(hw_cache_event_ids));
7453 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
7454 sizeof(hw_cache_extra_regs));
7455
7456 intel_pmu_lbr_init_skl();
7457
7458 x86_pmu.event_constraints = intel_slm_event_constraints;
7459 x86_pmu.extra_regs = intel_glm_extra_regs;
7460 /*
7461 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
7462 * for precise cycles.
7463 */
7464 x86_pmu.pebs_aliases = NULL;
7465 x86_pmu.pebs_prec_dist = true;
7466 x86_pmu.lbr_pt_coexist = true;
7467 x86_pmu.pebs_capable = ~0ULL;
7468 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7469 x86_pmu.flags |= PMU_FL_PEBS_ALL;
7470 x86_pmu.get_event_constraints = glp_get_event_constraints;
7471 td_attr = glm_events_attrs;
7472 /* Goldmont Plus has 4-wide pipeline */
7473 event_attr_td_total_slots_scale_glm.event_str = "4";
7474 extra_attr = slm_format_attr;
7475 pr_cont("Goldmont plus events, ");
7476 name = "goldmont_plus";
7477 break;
7478
7479 case INTEL_ATOM_TREMONT_D:
7480 case INTEL_ATOM_TREMONT:
7481 case INTEL_ATOM_TREMONT_L:
7482 x86_pmu.late_ack = true;
7483 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
7484 sizeof(hw_cache_event_ids));
7485 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
7486 sizeof(hw_cache_extra_regs));
7487 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
7488
7489 intel_pmu_lbr_init_skl();
7490
7491 x86_pmu.event_constraints = intel_slm_event_constraints;
7492 x86_pmu.extra_regs = intel_tnt_extra_regs;
7493 /*
7494 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
7495 * for precise cycles.
7496 */
7497 x86_pmu.pebs_aliases = NULL;
7498 x86_pmu.pebs_prec_dist = true;
7499 x86_pmu.lbr_pt_coexist = true;
7500 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7501 x86_pmu.get_event_constraints = tnt_get_event_constraints;
7502 td_attr = tnt_events_attrs;
7503 extra_attr = slm_format_attr;
7504 pr_cont("Tremont events, ");
7505 name = "Tremont";
7506 break;
7507
7508 case INTEL_ATOM_GRACEMONT:
7509 intel_pmu_init_grt(NULL);
7510 intel_pmu_pebs_data_source_grt();
7511 x86_pmu.pebs_latency_data = grt_latency_data;
7512 x86_pmu.get_event_constraints = tnt_get_event_constraints;
7513 td_attr = tnt_events_attrs;
7514 mem_attr = grt_mem_attrs;
7515 extra_attr = nhm_format_attr;
7516 pr_cont("Gracemont events, ");
7517 name = "gracemont";
7518 break;
7519
7520 case INTEL_ATOM_CRESTMONT:
7521 case INTEL_ATOM_CRESTMONT_X:
7522 intel_pmu_init_grt(NULL);
7523 x86_pmu.extra_regs = intel_cmt_extra_regs;
7524 intel_pmu_pebs_data_source_cmt();
7525 x86_pmu.pebs_latency_data = cmt_latency_data;
7526 x86_pmu.get_event_constraints = cmt_get_event_constraints;
7527 td_attr = cmt_events_attrs;
7528 mem_attr = grt_mem_attrs;
7529 extra_attr = cmt_format_attr;
7530 pr_cont("Crestmont events, ");
7531 name = "crestmont";
7532 break;
7533
7534 case INTEL_ATOM_DARKMONT_X:
7535 intel_pmu_init_skt(NULL);
7536 intel_pmu_pebs_data_source_cmt();
7537 x86_pmu.pebs_latency_data = cmt_latency_data;
7538 x86_pmu.get_event_constraints = cmt_get_event_constraints;
7539 td_attr = skt_events_attrs;
7540 mem_attr = grt_mem_attrs;
7541 extra_attr = cmt_format_attr;
7542 pr_cont("Darkmont events, ");
7543 name = "darkmont";
7544 break;
7545
7546 case INTEL_WESTMERE:
7547 case INTEL_WESTMERE_EP:
7548 case INTEL_WESTMERE_EX:
7549 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
7550 sizeof(hw_cache_event_ids));
7551 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
7552 sizeof(hw_cache_extra_regs));
7553
7554 intel_pmu_lbr_init_nhm();
7555
7556 x86_pmu.event_constraints = intel_westmere_event_constraints;
7557 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
7558 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
7559 x86_pmu.extra_regs = intel_westmere_extra_regs;
7560 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7561
7562 mem_attr = nhm_mem_events_attrs;
7563
7564 /* UOPS_ISSUED.STALLED_CYCLES */
7565 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
7566 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
7567 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
7568 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
7569 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
7570
7571 intel_pmu_pebs_data_source_nhm();
7572 extra_attr = nhm_format_attr;
7573 pr_cont("Westmere events, ");
7574 name = "westmere";
7575 break;
7576
7577 case INTEL_SANDYBRIDGE:
7578 case INTEL_SANDYBRIDGE_X:
7579 x86_add_quirk(intel_sandybridge_quirk);
7580 x86_add_quirk(intel_ht_bug);
7581 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
7582 sizeof(hw_cache_event_ids));
7583 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
7584 sizeof(hw_cache_extra_regs));
7585
7586 intel_pmu_lbr_init_snb();
7587
7588 x86_pmu.event_constraints = intel_snb_event_constraints;
7589 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
7590 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
7591 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X)
7592 x86_pmu.extra_regs = intel_snbep_extra_regs;
7593 else
7594 x86_pmu.extra_regs = intel_snb_extra_regs;
7595
7596
7597 /* all extra regs are per-cpu when HT is on */
7598 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7599 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7600
7601 td_attr = snb_events_attrs;
7602 mem_attr = snb_mem_events_attrs;
7603
7604 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
7605 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
7606 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
7607 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
7608 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
7609 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
7610
7611 extra_attr = nhm_format_attr;
7612
7613 pr_cont("SandyBridge events, ");
7614 name = "sandybridge";
7615 break;
7616
7617 case INTEL_IVYBRIDGE:
7618 case INTEL_IVYBRIDGE_X:
7619 x86_add_quirk(intel_ht_bug);
7620 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
7621 sizeof(hw_cache_event_ids));
7622 /* dTLB-load-misses on IVB is different than SNB */
7623 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
7624
7625 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
7626 sizeof(hw_cache_extra_regs));
7627
7628 intel_pmu_lbr_init_snb();
7629
7630 x86_pmu.event_constraints = intel_ivb_event_constraints;
7631 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
7632 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
7633 x86_pmu.pebs_prec_dist = true;
7634 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X)
7635 x86_pmu.extra_regs = intel_snbep_extra_regs;
7636 else
7637 x86_pmu.extra_regs = intel_snb_extra_regs;
7638 /* all extra regs are per-cpu when HT is on */
7639 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7640 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7641
7642 td_attr = snb_events_attrs;
7643 mem_attr = snb_mem_events_attrs;
7644
7645 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
7646 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
7647 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
7648
7649 extra_attr = nhm_format_attr;
7650
7651 pr_cont("IvyBridge events, ");
7652 name = "ivybridge";
7653 break;
7654
7655
7656 case INTEL_HASWELL:
7657 case INTEL_HASWELL_X:
7658 case INTEL_HASWELL_L:
7659 case INTEL_HASWELL_G:
7660 x86_add_quirk(intel_ht_bug);
7661 x86_add_quirk(intel_pebs_isolation_quirk);
7662 x86_pmu.late_ack = true;
7663 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7664 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7665
7666 intel_pmu_lbr_init_hsw();
7667
7668 x86_pmu.event_constraints = intel_hsw_event_constraints;
7669 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
7670 x86_pmu.extra_regs = intel_snbep_extra_regs;
7671 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
7672 x86_pmu.pebs_prec_dist = true;
7673 /* all extra regs are per-cpu when HT is on */
7674 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7675 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7676
7677 x86_pmu.hw_config = hsw_hw_config;
7678 x86_pmu.get_event_constraints = hsw_get_event_constraints;
7679 x86_pmu.limit_period = hsw_limit_period;
7680 x86_pmu.lbr_double_abort = true;
7681 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7682 hsw_format_attr : nhm_format_attr;
7683 td_attr = hsw_events_attrs;
7684 mem_attr = hsw_mem_events_attrs;
7685 tsx_attr = hsw_tsx_events_attrs;
7686 pr_cont("Haswell events, ");
7687 name = "haswell";
7688 break;
7689
7690 case INTEL_BROADWELL:
7691 case INTEL_BROADWELL_D:
7692 case INTEL_BROADWELL_G:
7693 case INTEL_BROADWELL_X:
7694 x86_add_quirk(intel_pebs_isolation_quirk);
7695 x86_pmu.late_ack = true;
7696 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7697 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7698
7699 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
7700 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
7701 BDW_L3_MISS|HSW_SNOOP_DRAM;
7702 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
7703 HSW_SNOOP_DRAM;
7704 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
7705 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
7706 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
7707 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
7708
7709 intel_pmu_lbr_init_hsw();
7710
7711 x86_pmu.event_constraints = intel_bdw_event_constraints;
7712 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
7713 x86_pmu.extra_regs = intel_snbep_extra_regs;
7714 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
7715 x86_pmu.pebs_prec_dist = true;
7716 /* all extra regs are per-cpu when HT is on */
7717 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7718 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7719
7720 x86_pmu.hw_config = hsw_hw_config;
7721 x86_pmu.get_event_constraints = hsw_get_event_constraints;
7722 x86_pmu.limit_period = bdw_limit_period;
7723 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7724 hsw_format_attr : nhm_format_attr;
7725 td_attr = hsw_events_attrs;
7726 mem_attr = hsw_mem_events_attrs;
7727 tsx_attr = hsw_tsx_events_attrs;
7728 pr_cont("Broadwell events, ");
7729 name = "broadwell";
7730 break;
7731
7732 case INTEL_XEON_PHI_KNL:
7733 case INTEL_XEON_PHI_KNM:
7734 memcpy(hw_cache_event_ids,
7735 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7736 memcpy(hw_cache_extra_regs,
7737 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7738 intel_pmu_lbr_init_knl();
7739
7740 x86_pmu.event_constraints = intel_slm_event_constraints;
7741 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
7742 x86_pmu.extra_regs = intel_knl_extra_regs;
7743
7744 /* all extra regs are per-cpu when HT is on */
7745 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7746 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7747 extra_attr = slm_format_attr;
7748 pr_cont("Knights Landing/Mill events, ");
7749 name = "knights-landing";
7750 break;
7751
7752 case INTEL_SKYLAKE_X:
7753 pmem = true;
7754 fallthrough;
7755 case INTEL_SKYLAKE_L:
7756 case INTEL_SKYLAKE:
7757 case INTEL_KABYLAKE_L:
7758 case INTEL_KABYLAKE:
7759 case INTEL_COMETLAKE_L:
7760 case INTEL_COMETLAKE:
7761 x86_add_quirk(intel_pebs_isolation_quirk);
7762 x86_pmu.late_ack = true;
7763 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7764 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7765 intel_pmu_lbr_init_skl();
7766
7767 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
7768 event_attr_td_recovery_bubbles.event_str_noht =
7769 "event=0xd,umask=0x1,cmask=1";
7770 event_attr_td_recovery_bubbles.event_str_ht =
7771 "event=0xd,umask=0x1,cmask=1,any=1";
7772
7773 x86_pmu.event_constraints = intel_skl_event_constraints;
7774 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
7775 x86_pmu.extra_regs = intel_skl_extra_regs;
7776 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
7777 x86_pmu.pebs_prec_dist = true;
7778 /* all extra regs are per-cpu when HT is on */
7779 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7780 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7781
7782 x86_pmu.hw_config = hsw_hw_config;
7783 x86_pmu.get_event_constraints = hsw_get_event_constraints;
7784 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7785 hsw_format_attr : nhm_format_attr;
7786 extra_skl_attr = skl_format_attr;
7787 td_attr = hsw_events_attrs;
7788 mem_attr = hsw_mem_events_attrs;
7789 tsx_attr = hsw_tsx_events_attrs;
7790 intel_pmu_pebs_data_source_skl(pmem);
7791
7792 /*
7793 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
7794 * TSX force abort hooks are not required on these systems. Only deploy
7795 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
7796 */
7797 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
7798 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
7799 x86_pmu.flags |= PMU_FL_TFA;
7800 x86_pmu.get_event_constraints = tfa_get_event_constraints;
7801 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
7802 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
7803 }
7804
7805 pr_cont("Skylake events, ");
7806 name = "skylake";
7807 break;
7808
7809 case INTEL_ICELAKE_X:
7810 case INTEL_ICELAKE_D:
7811 x86_pmu.pebs_ept = 1;
7812 pmem = true;
7813 fallthrough;
7814 case INTEL_ICELAKE_L:
7815 case INTEL_ICELAKE:
7816 case INTEL_TIGERLAKE_L:
7817 case INTEL_TIGERLAKE:
7818 case INTEL_ROCKETLAKE:
7819 x86_pmu.late_ack = true;
7820 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7821 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7822 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
7823 intel_pmu_lbr_init_skl();
7824
7825 x86_pmu.event_constraints = intel_icl_event_constraints;
7826 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
7827 x86_pmu.extra_regs = intel_icl_extra_regs;
7828 x86_pmu.pebs_aliases = NULL;
7829 x86_pmu.pebs_prec_dist = true;
7830 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7831 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7832
7833 x86_pmu.hw_config = hsw_hw_config;
7834 x86_pmu.get_event_constraints = icl_get_event_constraints;
7835 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7836 hsw_format_attr : nhm_format_attr;
7837 extra_skl_attr = skl_format_attr;
7838 mem_attr = icl_events_attrs;
7839 td_attr = icl_td_events_attrs;
7840 tsx_attr = icl_tsx_events_attrs;
7841 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
7842 x86_pmu.lbr_pt_coexist = true;
7843 intel_pmu_pebs_data_source_skl(pmem);
7844 x86_pmu.num_topdown_events = 4;
7845 static_call_update(intel_pmu_update_topdown_event,
7846 &icl_update_topdown_event);
7847 static_call_update(intel_pmu_set_topdown_event_period,
7848 &icl_set_topdown_event_period);
7849 pr_cont("Icelake events, ");
7850 name = "icelake";
7851 break;
7852
7853 case INTEL_SAPPHIRERAPIDS_X:
7854 case INTEL_EMERALDRAPIDS_X:
7855 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
7856 x86_pmu.extra_regs = intel_glc_extra_regs;
7857 pr_cont("Sapphire Rapids events, ");
7858 name = "sapphire_rapids";
7859 goto glc_common;
7860
7861 case INTEL_GRANITERAPIDS_X:
7862 case INTEL_GRANITERAPIDS_D:
7863 x86_pmu.extra_regs = intel_rwc_extra_regs;
7864 pr_cont("Granite Rapids events, ");
7865 name = "granite_rapids";
7866
7867 glc_common:
7868 intel_pmu_init_glc(NULL);
7869 x86_pmu.pebs_ept = 1;
7870 x86_pmu.hw_config = hsw_hw_config;
7871 x86_pmu.get_event_constraints = glc_get_event_constraints;
7872 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7873 hsw_format_attr : nhm_format_attr;
7874 extra_skl_attr = skl_format_attr;
7875 mem_attr = glc_events_attrs;
7876 td_attr = glc_td_events_attrs;
7877 tsx_attr = glc_tsx_events_attrs;
7878 intel_pmu_pebs_data_source_skl(true);
7879 break;
7880
7881 case INTEL_ALDERLAKE:
7882 case INTEL_ALDERLAKE_L:
7883 case INTEL_RAPTORLAKE:
7884 case INTEL_RAPTORLAKE_P:
7885 case INTEL_RAPTORLAKE_S:
7886 /*
7887 * Alder Lake has 2 types of CPU, core and atom.
7888 *
7889 * Initialize the common PerfMon capabilities here.
7890 */
7891 intel_pmu_init_hybrid(hybrid_big_small);
7892
7893 x86_pmu.pebs_latency_data = grt_latency_data;
7894 x86_pmu.get_event_constraints = adl_get_event_constraints;
7895 x86_pmu.hw_config = adl_hw_config;
7896 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
7897
7898 td_attr = adl_hybrid_events_attrs;
7899 mem_attr = adl_hybrid_mem_attrs;
7900 tsx_attr = adl_hybrid_tsx_attrs;
7901 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7902 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
7903
7904 /* Initialize big core specific PerfMon capabilities.*/
7905 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7906 intel_pmu_init_glc(&pmu->pmu);
7907 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
7908 pmu->cntr_mask64 <<= 2;
7909 pmu->cntr_mask64 |= 0x3;
7910 pmu->fixed_cntr_mask64 <<= 1;
7911 pmu->fixed_cntr_mask64 |= 0x1;
7912 } else {
7913 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7914 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7915 }
7916
7917 /*
7918 * Quirk: For some Alder Lake machine, when all E-cores are disabled in
7919 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
7920 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
7921 * mistakenly add extra counters for P-cores. Correct the number of
7922 * counters here.
7923 */
7924 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) {
7925 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7926 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7927 }
7928
7929 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
7930 pmu->unconstrained = (struct event_constraint)
7931 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
7932 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
7933
7934 pmu->extra_regs = intel_glc_extra_regs;
7935
7936 /* Initialize Atom core specific PerfMon capabilities.*/
7937 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7938 intel_pmu_init_grt(&pmu->pmu);
7939
7940 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
7941 intel_pmu_pebs_data_source_adl();
7942 pr_cont("Alderlake Hybrid events, ");
7943 name = "alderlake_hybrid";
7944 break;
7945
7946 case INTEL_METEORLAKE:
7947 case INTEL_METEORLAKE_L:
7948 case INTEL_ARROWLAKE_U:
7949 intel_pmu_init_hybrid(hybrid_big_small);
7950
7951 x86_pmu.pebs_latency_data = cmt_latency_data;
7952 x86_pmu.get_event_constraints = mtl_get_event_constraints;
7953 x86_pmu.hw_config = adl_hw_config;
7954
7955 td_attr = adl_hybrid_events_attrs;
7956 mem_attr = mtl_hybrid_mem_attrs;
7957 tsx_attr = adl_hybrid_tsx_attrs;
7958 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7959 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7960
7961 /* Initialize big core specific PerfMon capabilities.*/
7962 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7963 intel_pmu_init_glc(&pmu->pmu);
7964 pmu->extra_regs = intel_rwc_extra_regs;
7965
7966 /* Initialize Atom core specific PerfMon capabilities.*/
7967 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7968 intel_pmu_init_grt(&pmu->pmu);
7969 pmu->extra_regs = intel_cmt_extra_regs;
7970
7971 intel_pmu_pebs_data_source_mtl();
7972 pr_cont("Meteorlake Hybrid events, ");
7973 name = "meteorlake_hybrid";
7974 break;
7975
7976 case INTEL_PANTHERLAKE_L:
7977 case INTEL_WILDCATLAKE_L:
7978 pr_cont("Pantherlake Hybrid events, ");
7979 name = "pantherlake_hybrid";
7980 goto lnl_common;
7981
7982 case INTEL_LUNARLAKE_M:
7983 case INTEL_ARROWLAKE:
7984 pr_cont("Lunarlake Hybrid events, ");
7985 name = "lunarlake_hybrid";
7986
7987 lnl_common:
7988 intel_pmu_init_hybrid(hybrid_big_small);
7989
7990 x86_pmu.pebs_latency_data = lnl_latency_data;
7991 x86_pmu.get_event_constraints = mtl_get_event_constraints;
7992 x86_pmu.hw_config = adl_hw_config;
7993
7994 td_attr = lnl_hybrid_events_attrs;
7995 mem_attr = mtl_hybrid_mem_attrs;
7996 tsx_attr = adl_hybrid_tsx_attrs;
7997 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7998 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7999
8000 /* Initialize big core specific PerfMon capabilities.*/
8001 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8002 intel_pmu_init_lnc(&pmu->pmu);
8003
8004 /* Initialize Atom core specific PerfMon capabilities.*/
8005 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8006 intel_pmu_init_skt(&pmu->pmu);
8007
8008 intel_pmu_pebs_data_source_lnl();
8009 break;
8010
8011 case INTEL_ARROWLAKE_H:
8012 intel_pmu_init_hybrid(hybrid_big_small_tiny);
8013
8014 x86_pmu.pebs_latency_data = arl_h_latency_data;
8015 x86_pmu.get_event_constraints = arl_h_get_event_constraints;
8016 x86_pmu.hw_config = arl_h_hw_config;
8017
8018 td_attr = arl_h_hybrid_events_attrs;
8019 mem_attr = arl_h_hybrid_mem_attrs;
8020 tsx_attr = adl_hybrid_tsx_attrs;
8021 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8022 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8023
8024 /* Initialize big core specific PerfMon capabilities. */
8025 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8026 intel_pmu_init_lnc(&pmu->pmu);
8027
8028 /* Initialize Atom core specific PerfMon capabilities. */
8029 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8030 intel_pmu_init_skt(&pmu->pmu);
8031
8032 /* Initialize Lower Power Atom specific PerfMon capabilities. */
8033 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX];
8034 intel_pmu_init_grt(&pmu->pmu);
8035 pmu->extra_regs = intel_cmt_extra_regs;
8036
8037 intel_pmu_pebs_data_source_arl_h();
8038 pr_cont("ArrowLake-H Hybrid events, ");
8039 name = "arrowlake_h_hybrid";
8040 break;
8041
8042 default:
8043 switch (x86_pmu.version) {
8044 case 1:
8045 x86_pmu.event_constraints = intel_v1_event_constraints;
8046 pr_cont("generic architected perfmon v1, ");
8047 name = "generic_arch_v1";
8048 break;
8049 case 2:
8050 case 3:
8051 case 4:
8052 /*
8053 * default constraints for v2 and up
8054 */
8055 x86_pmu.event_constraints = intel_gen_event_constraints;
8056 pr_cont("generic architected perfmon, ");
8057 name = "generic_arch_v2+";
8058 break;
8059 default:
8060 /*
8061 * The default constraints for v5 and up can support up to
8062 * 16 fixed counters. For the fixed counters 4 and later,
8063 * the pseudo-encoding is applied.
8064 * The constraints may be cut according to the CPUID enumeration
8065 * by inserting the EVENT_CONSTRAINT_END.
8066 */
8067 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED)
8068 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
8069 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1;
8070 x86_pmu.event_constraints = intel_v5_gen_event_constraints;
8071 pr_cont("generic architected perfmon, ");
8072 name = "generic_arch_v5+";
8073 break;
8074 }
8075 }
8076
8077 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
8078
8079 if (!is_hybrid()) {
8080 group_events_td.attrs = td_attr;
8081 group_events_mem.attrs = mem_attr;
8082 group_events_tsx.attrs = tsx_attr;
8083 group_format_extra.attrs = extra_attr;
8084 group_format_extra_skl.attrs = extra_skl_attr;
8085
8086 x86_pmu.attr_update = attr_update;
8087 } else {
8088 hybrid_group_events_td.attrs = td_attr;
8089 hybrid_group_events_mem.attrs = mem_attr;
8090 hybrid_group_events_tsx.attrs = tsx_attr;
8091 hybrid_group_format_extra.attrs = extra_attr;
8092
8093 x86_pmu.attr_update = hybrid_attr_update;
8094 }
8095
8096 /*
8097 * The archPerfmonExt (0x23) includes an enhanced enumeration of
8098 * PMU architectural features with a per-core view. For non-hybrid,
8099 * each core has the same PMU capabilities. It's good enough to
8100 * update the x86_pmu from the booting CPU. For hybrid, the x86_pmu
8101 * is used to keep the common capabilities. Still keep the values
8102 * from the leaf 0xa. The core specific update will be done later
8103 * when a new type is online.
8104 */
8105 if (!is_hybrid() && boot_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
8106 update_pmu_cap(NULL);
8107
8108 if (x86_pmu.arch_pebs) {
8109 static_call_update(intel_pmu_disable_event_ext,
8110 intel_pmu_disable_event_ext);
8111 static_call_update(intel_pmu_enable_event_ext,
8112 intel_pmu_enable_event_ext);
8113 pr_cont("Architectural PEBS, ");
8114 }
8115
8116 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64,
8117 &x86_pmu.fixed_cntr_mask64,
8118 &x86_pmu.intel_ctrl);
8119
8120 /* AnyThread may be deprecated on arch perfmon v5 or later */
8121 if (x86_pmu.intel_cap.anythread_deprecated)
8122 x86_pmu.format_attrs = intel_arch_formats_attr;
8123
8124 intel_pmu_check_event_constraints_all(NULL);
8125
8126 /*
8127 * Access LBR MSR may cause #GP under certain circumstances.
8128 * Check all LBR MSR here.
8129 * Disable LBR access if any LBR MSRs can not be accessed.
8130 */
8131 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
8132 x86_pmu.lbr_nr = 0;
8133 for (i = 0; i < x86_pmu.lbr_nr; i++) {
8134 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
8135 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
8136 x86_pmu.lbr_nr = 0;
8137 }
8138
8139 if (x86_pmu.lbr_nr) {
8140 intel_pmu_lbr_init();
8141
8142 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
8143
8144 /* only support branch_stack snapshot for perfmon >= v2 */
8145 if (x86_pmu.disable_all == intel_pmu_disable_all) {
8146 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) {
8147 static_call_update(perf_snapshot_branch_stack,
8148 intel_pmu_snapshot_arch_branch_stack);
8149 } else {
8150 static_call_update(perf_snapshot_branch_stack,
8151 intel_pmu_snapshot_branch_stack);
8152 }
8153 }
8154 }
8155
8156 intel_pmu_check_extra_regs(x86_pmu.extra_regs);
8157
8158 /* Support full width counters using alternative MSR range */
8159 if (x86_pmu.intel_cap.full_width_write) {
8160 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
8161 x86_pmu.perfctr = MSR_IA32_PMC0;
8162 pr_cont("full-width counters, ");
8163 }
8164
8165 /* Support V6+ MSR Aliasing */
8166 if (x86_pmu.version >= 6) {
8167 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR;
8168 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A;
8169 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR;
8170 x86_pmu.addr_offset = intel_pmu_v6_addr_offset;
8171 }
8172
8173 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
8174 x86_pmu.intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS;
8175
8176 if (x86_pmu.intel_cap.pebs_timing_info)
8177 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY;
8178
8179 intel_aux_output_init();
8180
8181 return 0;
8182 }
8183
8184 /*
8185 * HT bug: phase 2 init
8186 * Called once we have valid topology information to check
8187 * whether or not HT is enabled
8188 * If HT is off, then we disable the workaround
8189 */
fixup_ht_bug(void)8190 static __init int fixup_ht_bug(void)
8191 {
8192 int c;
8193 /*
8194 * problem not present on this CPU model, nothing to do
8195 */
8196 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
8197 return 0;
8198
8199 if (topology_max_smt_threads() > 1) {
8200 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
8201 return 0;
8202 }
8203
8204 cpus_read_lock();
8205
8206 hardlockup_detector_perf_stop();
8207
8208 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
8209
8210 x86_pmu.start_scheduling = NULL;
8211 x86_pmu.commit_scheduling = NULL;
8212 x86_pmu.stop_scheduling = NULL;
8213
8214 hardlockup_detector_perf_restart();
8215
8216 for_each_online_cpu(c)
8217 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
8218
8219 cpus_read_unlock();
8220 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
8221 return 0;
8222 }
8223 subsys_initcall(fixup_ht_bug)
8224