1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip switch driver main logic
4 *
5 * Copyright (C) 2017-2025 Microchip Technology Inc.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/dsa/ksz_common.h>
10 #include <linux/export.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_data/microchip-ksz.h>
15 #include <linux/phy.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/of.h>
22 #include <linux/of_mdio.h>
23 #include <linux/of_net.h>
24 #include <linux/micrel_phy.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <net/dsa.h>
27 #include <net/ieee8021q.h>
28 #include <net/pkt_cls.h>
29 #include <net/switchdev.h>
30
31 #include "ksz_common.h"
32 #include "ksz_dcb.h"
33 #include "ksz_ptp.h"
34 #include "ksz8.h"
35 #include "ksz9477.h"
36 #include "lan937x.h"
37
38 #define MIB_COUNTER_NUM 0x20
39
40 static const struct ksz_mib_names ksz88xx_mib_names[] = {
41 { 0x00, "rx" },
42 { 0x01, "rx_hi" },
43 { 0x02, "rx_undersize" },
44 { 0x03, "rx_fragments" },
45 { 0x04, "rx_oversize" },
46 { 0x05, "rx_jabbers" },
47 { 0x06, "rx_symbol_err" },
48 { 0x07, "rx_crc_err" },
49 { 0x08, "rx_align_err" },
50 { 0x09, "rx_mac_ctrl" },
51 { 0x0a, "rx_pause" },
52 { 0x0b, "rx_bcast" },
53 { 0x0c, "rx_mcast" },
54 { 0x0d, "rx_ucast" },
55 { 0x0e, "rx_64_or_less" },
56 { 0x0f, "rx_65_127" },
57 { 0x10, "rx_128_255" },
58 { 0x11, "rx_256_511" },
59 { 0x12, "rx_512_1023" },
60 { 0x13, "rx_1024_1522" },
61 { 0x14, "tx" },
62 { 0x15, "tx_hi" },
63 { 0x16, "tx_late_col" },
64 { 0x17, "tx_pause" },
65 { 0x18, "tx_bcast" },
66 { 0x19, "tx_mcast" },
67 { 0x1a, "tx_ucast" },
68 { 0x1b, "tx_deferred" },
69 { 0x1c, "tx_total_col" },
70 { 0x1d, "tx_exc_col" },
71 { 0x1e, "tx_single_col" },
72 { 0x1f, "tx_mult_col" },
73 { 0x100, "rx_discards" },
74 { 0x101, "tx_discards" },
75 };
76
77 static const struct ksz_mib_names ksz9477_mib_names[] = {
78 { 0x00, "rx_hi" },
79 { 0x01, "rx_undersize" },
80 { 0x02, "rx_fragments" },
81 { 0x03, "rx_oversize" },
82 { 0x04, "rx_jabbers" },
83 { 0x05, "rx_symbol_err" },
84 { 0x06, "rx_crc_err" },
85 { 0x07, "rx_align_err" },
86 { 0x08, "rx_mac_ctrl" },
87 { 0x09, "rx_pause" },
88 { 0x0A, "rx_bcast" },
89 { 0x0B, "rx_mcast" },
90 { 0x0C, "rx_ucast" },
91 { 0x0D, "rx_64_or_less" },
92 { 0x0E, "rx_65_127" },
93 { 0x0F, "rx_128_255" },
94 { 0x10, "rx_256_511" },
95 { 0x11, "rx_512_1023" },
96 { 0x12, "rx_1024_1522" },
97 { 0x13, "rx_1523_2000" },
98 { 0x14, "rx_2001" },
99 { 0x15, "tx_hi" },
100 { 0x16, "tx_late_col" },
101 { 0x17, "tx_pause" },
102 { 0x18, "tx_bcast" },
103 { 0x19, "tx_mcast" },
104 { 0x1A, "tx_ucast" },
105 { 0x1B, "tx_deferred" },
106 { 0x1C, "tx_total_col" },
107 { 0x1D, "tx_exc_col" },
108 { 0x1E, "tx_single_col" },
109 { 0x1F, "tx_mult_col" },
110 { 0x80, "rx_total" },
111 { 0x81, "tx_total" },
112 { 0x82, "rx_discards" },
113 { 0x83, "tx_discards" },
114 };
115
116 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants
117 *
118 * This values are not documented in KSZ9477 variants but confirmed by
119 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893
120 * and KSZ8563 are using same register (drive strength) settings like KSZ8795.
121 *
122 * Documentation in KSZ8795CLX provides more information with some
123 * recommendations:
124 * - for high speed signals
125 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using
126 * 2.5V or 3.3V VDDIO.
127 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with
128 * using 1.8V VDDIO.
129 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V
130 * or 3.3V VDDIO.
131 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO.
132 * 5. In same interface, the heavy loading should use higher one of the
133 * drive current strength.
134 * - for low speed signals
135 * 1. 3.3V VDDIO, use either 4 mA or 8 mA.
136 * 2. 2.5V VDDIO, use either 8 mA or 12 mA.
137 * 3. 1.8V VDDIO, use either 12 mA or 16 mA.
138 * 4. If it is heavy loading, can use higher drive current strength.
139 */
140 static const struct ksz_drive_strength ksz9477_drive_strengths[] = {
141 { SW_DRIVE_STRENGTH_2MA, 2000 },
142 { SW_DRIVE_STRENGTH_4MA, 4000 },
143 { SW_DRIVE_STRENGTH_8MA, 8000 },
144 { SW_DRIVE_STRENGTH_12MA, 12000 },
145 { SW_DRIVE_STRENGTH_16MA, 16000 },
146 { SW_DRIVE_STRENGTH_20MA, 20000 },
147 { SW_DRIVE_STRENGTH_24MA, 24000 },
148 { SW_DRIVE_STRENGTH_28MA, 28000 },
149 };
150
151 /**
152 * ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy)
153 * @config: phylink config structure
154 *
155 * This function is a dummy handler. See ksz_phylink_mac_enable_tx_lpi() for
156 * a detailed explanation of EEE/LPI handling in KSZ switches.
157 */
ksz_phylink_mac_disable_tx_lpi(struct phylink_config * config)158 void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config)
159 {
160 }
161
162 /**
163 * ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy)
164 * @config: phylink config structure
165 * @timer: timer value before entering LPI (unused)
166 * @tx_clock_stop: whether to stop the TX clock in LPI mode (unused)
167 *
168 * This function signals to phylink that the driver architecture supports
169 * LPI management, enabling phylink to control EEE advertisement during
170 * negotiation according to IEEE Std 802.3 (Clause 78).
171 *
172 * Hardware Management of EEE/LPI State:
173 * For KSZ switch ports with integrated PHYs (e.g., KSZ9893R ports 1-2),
174 * observation and testing suggest that the actual EEE / Low Power Idle (LPI)
175 * state transitions are managed autonomously by the hardware based on
176 * the auto-negotiation results. (Note: While the datasheet describes EEE
177 * operation based on negotiation, it doesn't explicitly detail the internal
178 * MAC/PHY interaction, so autonomous hardware management of the MAC state
179 * for LPI is inferred from observed behavior).
180 * This hardware control, consistent with the switch's ability to operate
181 * autonomously via strapping, means MAC-level software intervention is not
182 * required or exposed for managing the LPI state once EEE is negotiated.
183 * (Ref: KSZ9893R Data Sheet DS00002420D, primarily Section 4.7.5 explaining
184 * EEE, also Sections 4.1.7 on Auto-Negotiation and 3.2.1 on Configuration
185 * Straps).
186 *
187 * Additionally, ports configured as MAC interfaces (e.g., KSZ9893R port 3)
188 * lack documented MAC-level LPI control.
189 *
190 * Therefore, this callback performs no action and serves primarily to inform
191 * phylink of LPI awareness and to document the inferred hardware behavior.
192 *
193 * Returns: 0 (Always success)
194 */
ksz_phylink_mac_enable_tx_lpi(struct phylink_config * config,u32 timer,bool tx_clock_stop)195 int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config,
196 u32 timer, bool tx_clock_stop)
197 {
198 return 0;
199 }
200
201 static const u16 ksz8463_regs[] = {
202 [REG_SW_MAC_ADDR] = 0x10,
203 [REG_IND_CTRL_0] = 0x30,
204 [REG_IND_DATA_8] = 0x26,
205 [REG_IND_DATA_CHECK] = 0x26,
206 [REG_IND_DATA_HI] = 0x28,
207 [REG_IND_DATA_LO] = 0x2C,
208 [REG_IND_MIB_CHECK] = 0x2F,
209 [P_FORCE_CTRL] = 0x0C,
210 [P_LINK_STATUS] = 0x0E,
211 [P_LOCAL_CTRL] = 0x0C,
212 [P_NEG_RESTART_CTRL] = 0x0D,
213 [P_REMOTE_STATUS] = 0x0E,
214 [P_SPEED_STATUS] = 0x0F,
215 [S_TAIL_TAG_CTRL] = 0xAD,
216 [P_STP_CTRL] = 0x6F,
217 [S_START_CTRL] = 0x01,
218 [S_BROADCAST_CTRL] = 0x06,
219 [S_MULTICAST_CTRL] = 0x04,
220 [PTP_CLK_CTRL] = 0x0600,
221 [PTP_RTC_NANOSEC] = 0x0604,
222 [PTP_RTC_SEC] = 0x0608,
223 [PTP_RTC_SUB_NANOSEC] = 0x060C,
224 [PTP_SUBNANOSEC_RATE] = 0x0610,
225 [PTP_MSG_CONF1] = 0x0620,
226 };
227
228 static const u32 ksz8463_masks[] = {
229 [PORT_802_1P_REMAPPING] = BIT(3),
230 [SW_TAIL_TAG_ENABLE] = BIT(0),
231 [MIB_COUNTER_OVERFLOW] = BIT(7),
232 [MIB_COUNTER_VALID] = BIT(6),
233 [VLAN_TABLE_FID] = GENMASK(15, 12),
234 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
235 [VLAN_TABLE_VALID] = BIT(19),
236 [STATIC_MAC_TABLE_VALID] = BIT(19),
237 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
238 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
239 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
240 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
241 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
242 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
243 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
244 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
245 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
246 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
247 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
248 };
249
250 static u8 ksz8463_shifts[] = {
251 [VLAN_TABLE_MEMBERSHIP_S] = 16,
252 [STATIC_MAC_FWD_PORTS] = 16,
253 [STATIC_MAC_FID] = 22,
254 [DYNAMIC_MAC_ENTRIES_H] = 8,
255 [DYNAMIC_MAC_ENTRIES] = 24,
256 [DYNAMIC_MAC_FID] = 16,
257 [DYNAMIC_MAC_TIMESTAMP] = 22,
258 [DYNAMIC_MAC_SRC_PORT] = 20,
259 };
260
261 static const u16 ksz8795_regs[] = {
262 [REG_SW_MAC_ADDR] = 0x68,
263 [REG_IND_CTRL_0] = 0x6E,
264 [REG_IND_DATA_8] = 0x70,
265 [REG_IND_DATA_CHECK] = 0x72,
266 [REG_IND_DATA_HI] = 0x71,
267 [REG_IND_DATA_LO] = 0x75,
268 [REG_IND_MIB_CHECK] = 0x74,
269 [REG_IND_BYTE] = 0xA0,
270 [P_FORCE_CTRL] = 0x0C,
271 [P_LINK_STATUS] = 0x0E,
272 [P_LOCAL_CTRL] = 0x07,
273 [P_NEG_RESTART_CTRL] = 0x0D,
274 [P_REMOTE_STATUS] = 0x08,
275 [P_SPEED_STATUS] = 0x09,
276 [S_TAIL_TAG_CTRL] = 0x0C,
277 [P_STP_CTRL] = 0x02,
278 [S_START_CTRL] = 0x01,
279 [S_BROADCAST_CTRL] = 0x06,
280 [S_MULTICAST_CTRL] = 0x04,
281 [P_XMII_CTRL_0] = 0x06,
282 [P_XMII_CTRL_1] = 0x06,
283 [REG_SW_PME_CTRL] = 0x8003,
284 [REG_PORT_PME_STATUS] = 0x8003,
285 [REG_PORT_PME_CTRL] = 0x8007,
286 };
287
288 static const u32 ksz8795_masks[] = {
289 [PORT_802_1P_REMAPPING] = BIT(7),
290 [SW_TAIL_TAG_ENABLE] = BIT(1),
291 [MIB_COUNTER_OVERFLOW] = BIT(6),
292 [MIB_COUNTER_VALID] = BIT(5),
293 [VLAN_TABLE_FID] = GENMASK(6, 0),
294 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
295 [VLAN_TABLE_VALID] = BIT(12),
296 [STATIC_MAC_TABLE_VALID] = BIT(21),
297 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
298 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
299 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
300 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
301 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
302 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
303 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
304 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
305 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
306 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
307 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
308 [P_MII_TX_FLOW_CTRL] = BIT(5),
309 [P_MII_RX_FLOW_CTRL] = BIT(5),
310 };
311
312 static const u8 ksz8795_xmii_ctrl0[] = {
313 [P_MII_100MBIT] = 0,
314 [P_MII_10MBIT] = 1,
315 [P_MII_FULL_DUPLEX] = 0,
316 [P_MII_HALF_DUPLEX] = 1,
317 };
318
319 static const u8 ksz8795_xmii_ctrl1[] = {
320 [P_RGMII_SEL] = 3,
321 [P_GMII_SEL] = 2,
322 [P_RMII_SEL] = 1,
323 [P_MII_SEL] = 0,
324 [P_GMII_1GBIT] = 1,
325 [P_GMII_NOT_1GBIT] = 0,
326 };
327
328 static const u8 ksz8795_shifts[] = {
329 [VLAN_TABLE_MEMBERSHIP_S] = 7,
330 [VLAN_TABLE] = 16,
331 [STATIC_MAC_FWD_PORTS] = 16,
332 [STATIC_MAC_FID] = 24,
333 [DYNAMIC_MAC_ENTRIES_H] = 3,
334 [DYNAMIC_MAC_ENTRIES] = 29,
335 [DYNAMIC_MAC_FID] = 16,
336 [DYNAMIC_MAC_TIMESTAMP] = 27,
337 [DYNAMIC_MAC_SRC_PORT] = 24,
338 };
339
340 static const u16 ksz8863_regs[] = {
341 [REG_SW_MAC_ADDR] = 0x70,
342 [REG_IND_CTRL_0] = 0x79,
343 [REG_IND_DATA_8] = 0x7B,
344 [REG_IND_DATA_CHECK] = 0x7B,
345 [REG_IND_DATA_HI] = 0x7C,
346 [REG_IND_DATA_LO] = 0x80,
347 [REG_IND_MIB_CHECK] = 0x80,
348 [P_FORCE_CTRL] = 0x0C,
349 [P_LINK_STATUS] = 0x0E,
350 [P_LOCAL_CTRL] = 0x0C,
351 [P_NEG_RESTART_CTRL] = 0x0D,
352 [P_REMOTE_STATUS] = 0x0E,
353 [P_SPEED_STATUS] = 0x0F,
354 [S_TAIL_TAG_CTRL] = 0x03,
355 [P_STP_CTRL] = 0x02,
356 [S_START_CTRL] = 0x01,
357 [S_BROADCAST_CTRL] = 0x06,
358 [S_MULTICAST_CTRL] = 0x04,
359 };
360
361 static const u32 ksz8863_masks[] = {
362 [PORT_802_1P_REMAPPING] = BIT(3),
363 [SW_TAIL_TAG_ENABLE] = BIT(6),
364 [MIB_COUNTER_OVERFLOW] = BIT(7),
365 [MIB_COUNTER_VALID] = BIT(6),
366 [VLAN_TABLE_FID] = GENMASK(15, 12),
367 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
368 [VLAN_TABLE_VALID] = BIT(19),
369 [STATIC_MAC_TABLE_VALID] = BIT(19),
370 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
371 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
372 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
373 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
374 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
375 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
376 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
377 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
378 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
379 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
380 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
381 };
382
383 static u8 ksz8863_shifts[] = {
384 [VLAN_TABLE_MEMBERSHIP_S] = 16,
385 [STATIC_MAC_FWD_PORTS] = 16,
386 [STATIC_MAC_FID] = 22,
387 [DYNAMIC_MAC_ENTRIES_H] = 8,
388 [DYNAMIC_MAC_ENTRIES] = 24,
389 [DYNAMIC_MAC_FID] = 16,
390 [DYNAMIC_MAC_TIMESTAMP] = 22,
391 [DYNAMIC_MAC_SRC_PORT] = 20,
392 };
393
394 static const u16 ksz8895_regs[] = {
395 [REG_SW_MAC_ADDR] = 0x68,
396 [REG_IND_CTRL_0] = 0x6E,
397 [REG_IND_DATA_8] = 0x70,
398 [REG_IND_DATA_CHECK] = 0x72,
399 [REG_IND_DATA_HI] = 0x71,
400 [REG_IND_DATA_LO] = 0x75,
401 [REG_IND_MIB_CHECK] = 0x75,
402 [P_FORCE_CTRL] = 0x0C,
403 [P_LINK_STATUS] = 0x0E,
404 [P_LOCAL_CTRL] = 0x0C,
405 [P_NEG_RESTART_CTRL] = 0x0D,
406 [P_REMOTE_STATUS] = 0x0E,
407 [P_SPEED_STATUS] = 0x09,
408 [S_TAIL_TAG_CTRL] = 0x0C,
409 [P_STP_CTRL] = 0x02,
410 [S_START_CTRL] = 0x01,
411 [S_BROADCAST_CTRL] = 0x06,
412 [S_MULTICAST_CTRL] = 0x04,
413 };
414
415 static const u32 ksz8895_masks[] = {
416 [PORT_802_1P_REMAPPING] = BIT(7),
417 [SW_TAIL_TAG_ENABLE] = BIT(1),
418 [MIB_COUNTER_OVERFLOW] = BIT(7),
419 [MIB_COUNTER_VALID] = BIT(6),
420 [VLAN_TABLE_FID] = GENMASK(6, 0),
421 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
422 [VLAN_TABLE_VALID] = BIT(12),
423 [STATIC_MAC_TABLE_VALID] = BIT(21),
424 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
425 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
426 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
427 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
428 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
429 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
430 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
431 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
432 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
433 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
434 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
435 };
436
437 static const u8 ksz8895_shifts[] = {
438 [VLAN_TABLE_MEMBERSHIP_S] = 7,
439 [VLAN_TABLE] = 13,
440 [STATIC_MAC_FWD_PORTS] = 16,
441 [STATIC_MAC_FID] = 24,
442 [DYNAMIC_MAC_ENTRIES_H] = 3,
443 [DYNAMIC_MAC_ENTRIES] = 29,
444 [DYNAMIC_MAC_FID] = 16,
445 [DYNAMIC_MAC_TIMESTAMP] = 27,
446 [DYNAMIC_MAC_SRC_PORT] = 24,
447 };
448
449 static const u16 ksz9477_regs[] = {
450 [REG_SW_MAC_ADDR] = 0x0302,
451 [P_STP_CTRL] = 0x0B04,
452 [S_START_CTRL] = 0x0300,
453 [S_BROADCAST_CTRL] = 0x0332,
454 [S_MULTICAST_CTRL] = 0x0331,
455 [P_XMII_CTRL_0] = 0x0300,
456 [P_XMII_CTRL_1] = 0x0301,
457 [REG_SW_PME_CTRL] = 0x0006,
458 [REG_PORT_PME_STATUS] = 0x0013,
459 [REG_PORT_PME_CTRL] = 0x0017,
460 [PTP_CLK_CTRL] = 0x0500,
461 [PTP_RTC_SUB_NANOSEC] = 0x0502,
462 [PTP_RTC_NANOSEC] = 0x0504,
463 [PTP_RTC_SEC] = 0x0508,
464 [PTP_SUBNANOSEC_RATE] = 0x050C,
465 [PTP_MSG_CONF1] = 0x0514,
466 };
467
468 static const u32 ksz9477_masks[] = {
469 [ALU_STAT_WRITE] = 0,
470 [ALU_STAT_READ] = 1,
471 [ALU_STAT_DIRECT] = 0,
472 [ALU_RESV_MCAST_ADDR] = BIT(1),
473 [P_MII_TX_FLOW_CTRL] = BIT(5),
474 [P_MII_RX_FLOW_CTRL] = BIT(3),
475 };
476
477 static const u8 ksz9477_shifts[] = {
478 [ALU_STAT_INDEX] = 16,
479 };
480
481 static const u8 ksz9477_xmii_ctrl0[] = {
482 [P_MII_100MBIT] = 1,
483 [P_MII_10MBIT] = 0,
484 [P_MII_FULL_DUPLEX] = 1,
485 [P_MII_HALF_DUPLEX] = 0,
486 };
487
488 static const u8 ksz9477_xmii_ctrl1[] = {
489 [P_RGMII_SEL] = 0,
490 [P_RMII_SEL] = 1,
491 [P_GMII_SEL] = 2,
492 [P_MII_SEL] = 3,
493 [P_GMII_1GBIT] = 0,
494 [P_GMII_NOT_1GBIT] = 1,
495 };
496
497 static const u32 lan937x_masks[] = {
498 [ALU_STAT_WRITE] = 1,
499 [ALU_STAT_READ] = 2,
500 [ALU_STAT_DIRECT] = BIT(3),
501 [ALU_RESV_MCAST_ADDR] = BIT(2),
502 [P_MII_TX_FLOW_CTRL] = BIT(5),
503 [P_MII_RX_FLOW_CTRL] = BIT(3),
504 };
505
506 static const u8 lan937x_shifts[] = {
507 [ALU_STAT_INDEX] = 8,
508 };
509
510 static const struct regmap_range ksz8563_valid_regs[] = {
511 regmap_reg_range(0x0000, 0x0003),
512 regmap_reg_range(0x0006, 0x0006),
513 regmap_reg_range(0x000f, 0x001f),
514 regmap_reg_range(0x0100, 0x0100),
515 regmap_reg_range(0x0104, 0x0107),
516 regmap_reg_range(0x010d, 0x010d),
517 regmap_reg_range(0x0110, 0x0113),
518 regmap_reg_range(0x0120, 0x012b),
519 regmap_reg_range(0x0201, 0x0201),
520 regmap_reg_range(0x0210, 0x0213),
521 regmap_reg_range(0x0300, 0x0300),
522 regmap_reg_range(0x0302, 0x031b),
523 regmap_reg_range(0x0320, 0x032b),
524 regmap_reg_range(0x0330, 0x0336),
525 regmap_reg_range(0x0338, 0x033e),
526 regmap_reg_range(0x0340, 0x035f),
527 regmap_reg_range(0x0370, 0x0370),
528 regmap_reg_range(0x0378, 0x0378),
529 regmap_reg_range(0x037c, 0x037d),
530 regmap_reg_range(0x0390, 0x0393),
531 regmap_reg_range(0x0400, 0x040e),
532 regmap_reg_range(0x0410, 0x042f),
533 regmap_reg_range(0x0500, 0x0519),
534 regmap_reg_range(0x0520, 0x054b),
535 regmap_reg_range(0x0550, 0x05b3),
536
537 /* port 1 */
538 regmap_reg_range(0x1000, 0x1001),
539 regmap_reg_range(0x1004, 0x100b),
540 regmap_reg_range(0x1013, 0x1013),
541 regmap_reg_range(0x1017, 0x1017),
542 regmap_reg_range(0x101b, 0x101b),
543 regmap_reg_range(0x101f, 0x1021),
544 regmap_reg_range(0x1030, 0x1030),
545 regmap_reg_range(0x1100, 0x1111),
546 regmap_reg_range(0x111a, 0x111d),
547 regmap_reg_range(0x1122, 0x1127),
548 regmap_reg_range(0x112a, 0x112b),
549 regmap_reg_range(0x1136, 0x1139),
550 regmap_reg_range(0x113e, 0x113f),
551 regmap_reg_range(0x1400, 0x1401),
552 regmap_reg_range(0x1403, 0x1403),
553 regmap_reg_range(0x1410, 0x1417),
554 regmap_reg_range(0x1420, 0x1423),
555 regmap_reg_range(0x1500, 0x1507),
556 regmap_reg_range(0x1600, 0x1612),
557 regmap_reg_range(0x1800, 0x180f),
558 regmap_reg_range(0x1900, 0x1907),
559 regmap_reg_range(0x1914, 0x191b),
560 regmap_reg_range(0x1a00, 0x1a03),
561 regmap_reg_range(0x1a04, 0x1a08),
562 regmap_reg_range(0x1b00, 0x1b01),
563 regmap_reg_range(0x1b04, 0x1b04),
564 regmap_reg_range(0x1c00, 0x1c05),
565 regmap_reg_range(0x1c08, 0x1c1b),
566
567 /* port 2 */
568 regmap_reg_range(0x2000, 0x2001),
569 regmap_reg_range(0x2004, 0x200b),
570 regmap_reg_range(0x2013, 0x2013),
571 regmap_reg_range(0x2017, 0x2017),
572 regmap_reg_range(0x201b, 0x201b),
573 regmap_reg_range(0x201f, 0x2021),
574 regmap_reg_range(0x2030, 0x2030),
575 regmap_reg_range(0x2100, 0x2111),
576 regmap_reg_range(0x211a, 0x211d),
577 regmap_reg_range(0x2122, 0x2127),
578 regmap_reg_range(0x212a, 0x212b),
579 regmap_reg_range(0x2136, 0x2139),
580 regmap_reg_range(0x213e, 0x213f),
581 regmap_reg_range(0x2400, 0x2401),
582 regmap_reg_range(0x2403, 0x2403),
583 regmap_reg_range(0x2410, 0x2417),
584 regmap_reg_range(0x2420, 0x2423),
585 regmap_reg_range(0x2500, 0x2507),
586 regmap_reg_range(0x2600, 0x2612),
587 regmap_reg_range(0x2800, 0x280f),
588 regmap_reg_range(0x2900, 0x2907),
589 regmap_reg_range(0x2914, 0x291b),
590 regmap_reg_range(0x2a00, 0x2a03),
591 regmap_reg_range(0x2a04, 0x2a08),
592 regmap_reg_range(0x2b00, 0x2b01),
593 regmap_reg_range(0x2b04, 0x2b04),
594 regmap_reg_range(0x2c00, 0x2c05),
595 regmap_reg_range(0x2c08, 0x2c1b),
596
597 /* port 3 */
598 regmap_reg_range(0x3000, 0x3001),
599 regmap_reg_range(0x3004, 0x300b),
600 regmap_reg_range(0x3013, 0x3013),
601 regmap_reg_range(0x3017, 0x3017),
602 regmap_reg_range(0x301b, 0x301b),
603 regmap_reg_range(0x301f, 0x3021),
604 regmap_reg_range(0x3030, 0x3030),
605 regmap_reg_range(0x3300, 0x3301),
606 regmap_reg_range(0x3303, 0x3303),
607 regmap_reg_range(0x3400, 0x3401),
608 regmap_reg_range(0x3403, 0x3403),
609 regmap_reg_range(0x3410, 0x3417),
610 regmap_reg_range(0x3420, 0x3423),
611 regmap_reg_range(0x3500, 0x3507),
612 regmap_reg_range(0x3600, 0x3612),
613 regmap_reg_range(0x3800, 0x380f),
614 regmap_reg_range(0x3900, 0x3907),
615 regmap_reg_range(0x3914, 0x391b),
616 regmap_reg_range(0x3a00, 0x3a03),
617 regmap_reg_range(0x3a04, 0x3a08),
618 regmap_reg_range(0x3b00, 0x3b01),
619 regmap_reg_range(0x3b04, 0x3b04),
620 regmap_reg_range(0x3c00, 0x3c05),
621 regmap_reg_range(0x3c08, 0x3c1b),
622 };
623
624 static const struct regmap_access_table ksz8563_register_set = {
625 .yes_ranges = ksz8563_valid_regs,
626 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
627 };
628
629 static const struct regmap_range ksz9477_valid_regs[] = {
630 regmap_reg_range(0x0000, 0x0003),
631 regmap_reg_range(0x0006, 0x0006),
632 regmap_reg_range(0x0010, 0x001f),
633 regmap_reg_range(0x0100, 0x0100),
634 regmap_reg_range(0x0103, 0x0107),
635 regmap_reg_range(0x010d, 0x010d),
636 regmap_reg_range(0x0110, 0x0113),
637 regmap_reg_range(0x0120, 0x012b),
638 regmap_reg_range(0x0201, 0x0201),
639 regmap_reg_range(0x0210, 0x0213),
640 regmap_reg_range(0x0300, 0x0300),
641 regmap_reg_range(0x0302, 0x031b),
642 regmap_reg_range(0x0320, 0x032b),
643 regmap_reg_range(0x0330, 0x0336),
644 regmap_reg_range(0x0338, 0x033b),
645 regmap_reg_range(0x033e, 0x033e),
646 regmap_reg_range(0x0340, 0x035f),
647 regmap_reg_range(0x0370, 0x0370),
648 regmap_reg_range(0x0378, 0x0378),
649 regmap_reg_range(0x037c, 0x037d),
650 regmap_reg_range(0x0390, 0x0393),
651 regmap_reg_range(0x0400, 0x040e),
652 regmap_reg_range(0x0410, 0x042f),
653 regmap_reg_range(0x0444, 0x044b),
654 regmap_reg_range(0x0450, 0x046f),
655 regmap_reg_range(0x0500, 0x0519),
656 regmap_reg_range(0x0520, 0x054b),
657 regmap_reg_range(0x0550, 0x05b3),
658 regmap_reg_range(0x0604, 0x060b),
659 regmap_reg_range(0x0610, 0x0612),
660 regmap_reg_range(0x0614, 0x062c),
661 regmap_reg_range(0x0640, 0x0645),
662 regmap_reg_range(0x0648, 0x064d),
663
664 /* port 1 */
665 regmap_reg_range(0x1000, 0x1001),
666 regmap_reg_range(0x1013, 0x1013),
667 regmap_reg_range(0x1017, 0x1017),
668 regmap_reg_range(0x101b, 0x101b),
669 regmap_reg_range(0x101f, 0x1020),
670 regmap_reg_range(0x1030, 0x1030),
671 regmap_reg_range(0x1100, 0x1115),
672 regmap_reg_range(0x111a, 0x111f),
673 regmap_reg_range(0x1120, 0x112b),
674 regmap_reg_range(0x1134, 0x113b),
675 regmap_reg_range(0x113c, 0x113f),
676 regmap_reg_range(0x1400, 0x1401),
677 regmap_reg_range(0x1403, 0x1403),
678 regmap_reg_range(0x1410, 0x1417),
679 regmap_reg_range(0x1420, 0x1423),
680 regmap_reg_range(0x1500, 0x1507),
681 regmap_reg_range(0x1600, 0x1613),
682 regmap_reg_range(0x1800, 0x180f),
683 regmap_reg_range(0x1820, 0x1827),
684 regmap_reg_range(0x1830, 0x1837),
685 regmap_reg_range(0x1840, 0x184b),
686 regmap_reg_range(0x1900, 0x1907),
687 regmap_reg_range(0x1914, 0x191b),
688 regmap_reg_range(0x1920, 0x1920),
689 regmap_reg_range(0x1923, 0x1927),
690 regmap_reg_range(0x1a00, 0x1a03),
691 regmap_reg_range(0x1a04, 0x1a07),
692 regmap_reg_range(0x1b00, 0x1b01),
693 regmap_reg_range(0x1b04, 0x1b04),
694 regmap_reg_range(0x1c00, 0x1c05),
695 regmap_reg_range(0x1c08, 0x1c1b),
696
697 /* port 2 */
698 regmap_reg_range(0x2000, 0x2001),
699 regmap_reg_range(0x2013, 0x2013),
700 regmap_reg_range(0x2017, 0x2017),
701 regmap_reg_range(0x201b, 0x201b),
702 regmap_reg_range(0x201f, 0x2020),
703 regmap_reg_range(0x2030, 0x2030),
704 regmap_reg_range(0x2100, 0x2115),
705 regmap_reg_range(0x211a, 0x211f),
706 regmap_reg_range(0x2120, 0x212b),
707 regmap_reg_range(0x2134, 0x213b),
708 regmap_reg_range(0x213c, 0x213f),
709 regmap_reg_range(0x2400, 0x2401),
710 regmap_reg_range(0x2403, 0x2403),
711 regmap_reg_range(0x2410, 0x2417),
712 regmap_reg_range(0x2420, 0x2423),
713 regmap_reg_range(0x2500, 0x2507),
714 regmap_reg_range(0x2600, 0x2613),
715 regmap_reg_range(0x2800, 0x280f),
716 regmap_reg_range(0x2820, 0x2827),
717 regmap_reg_range(0x2830, 0x2837),
718 regmap_reg_range(0x2840, 0x284b),
719 regmap_reg_range(0x2900, 0x2907),
720 regmap_reg_range(0x2914, 0x291b),
721 regmap_reg_range(0x2920, 0x2920),
722 regmap_reg_range(0x2923, 0x2927),
723 regmap_reg_range(0x2a00, 0x2a03),
724 regmap_reg_range(0x2a04, 0x2a07),
725 regmap_reg_range(0x2b00, 0x2b01),
726 regmap_reg_range(0x2b04, 0x2b04),
727 regmap_reg_range(0x2c00, 0x2c05),
728 regmap_reg_range(0x2c08, 0x2c1b),
729
730 /* port 3 */
731 regmap_reg_range(0x3000, 0x3001),
732 regmap_reg_range(0x3013, 0x3013),
733 regmap_reg_range(0x3017, 0x3017),
734 regmap_reg_range(0x301b, 0x301b),
735 regmap_reg_range(0x301f, 0x3020),
736 regmap_reg_range(0x3030, 0x3030),
737 regmap_reg_range(0x3100, 0x3115),
738 regmap_reg_range(0x311a, 0x311f),
739 regmap_reg_range(0x3120, 0x312b),
740 regmap_reg_range(0x3134, 0x313b),
741 regmap_reg_range(0x313c, 0x313f),
742 regmap_reg_range(0x3400, 0x3401),
743 regmap_reg_range(0x3403, 0x3403),
744 regmap_reg_range(0x3410, 0x3417),
745 regmap_reg_range(0x3420, 0x3423),
746 regmap_reg_range(0x3500, 0x3507),
747 regmap_reg_range(0x3600, 0x3613),
748 regmap_reg_range(0x3800, 0x380f),
749 regmap_reg_range(0x3820, 0x3827),
750 regmap_reg_range(0x3830, 0x3837),
751 regmap_reg_range(0x3840, 0x384b),
752 regmap_reg_range(0x3900, 0x3907),
753 regmap_reg_range(0x3914, 0x391b),
754 regmap_reg_range(0x3920, 0x3920),
755 regmap_reg_range(0x3923, 0x3927),
756 regmap_reg_range(0x3a00, 0x3a03),
757 regmap_reg_range(0x3a04, 0x3a07),
758 regmap_reg_range(0x3b00, 0x3b01),
759 regmap_reg_range(0x3b04, 0x3b04),
760 regmap_reg_range(0x3c00, 0x3c05),
761 regmap_reg_range(0x3c08, 0x3c1b),
762
763 /* port 4 */
764 regmap_reg_range(0x4000, 0x4001),
765 regmap_reg_range(0x4013, 0x4013),
766 regmap_reg_range(0x4017, 0x4017),
767 regmap_reg_range(0x401b, 0x401b),
768 regmap_reg_range(0x401f, 0x4020),
769 regmap_reg_range(0x4030, 0x4030),
770 regmap_reg_range(0x4100, 0x4115),
771 regmap_reg_range(0x411a, 0x411f),
772 regmap_reg_range(0x4120, 0x412b),
773 regmap_reg_range(0x4134, 0x413b),
774 regmap_reg_range(0x413c, 0x413f),
775 regmap_reg_range(0x4400, 0x4401),
776 regmap_reg_range(0x4403, 0x4403),
777 regmap_reg_range(0x4410, 0x4417),
778 regmap_reg_range(0x4420, 0x4423),
779 regmap_reg_range(0x4500, 0x4507),
780 regmap_reg_range(0x4600, 0x4613),
781 regmap_reg_range(0x4800, 0x480f),
782 regmap_reg_range(0x4820, 0x4827),
783 regmap_reg_range(0x4830, 0x4837),
784 regmap_reg_range(0x4840, 0x484b),
785 regmap_reg_range(0x4900, 0x4907),
786 regmap_reg_range(0x4914, 0x491b),
787 regmap_reg_range(0x4920, 0x4920),
788 regmap_reg_range(0x4923, 0x4927),
789 regmap_reg_range(0x4a00, 0x4a03),
790 regmap_reg_range(0x4a04, 0x4a07),
791 regmap_reg_range(0x4b00, 0x4b01),
792 regmap_reg_range(0x4b04, 0x4b04),
793 regmap_reg_range(0x4c00, 0x4c05),
794 regmap_reg_range(0x4c08, 0x4c1b),
795
796 /* port 5 */
797 regmap_reg_range(0x5000, 0x5001),
798 regmap_reg_range(0x5013, 0x5013),
799 regmap_reg_range(0x5017, 0x5017),
800 regmap_reg_range(0x501b, 0x501b),
801 regmap_reg_range(0x501f, 0x5020),
802 regmap_reg_range(0x5030, 0x5030),
803 regmap_reg_range(0x5100, 0x5115),
804 regmap_reg_range(0x511a, 0x511f),
805 regmap_reg_range(0x5120, 0x512b),
806 regmap_reg_range(0x5134, 0x513b),
807 regmap_reg_range(0x513c, 0x513f),
808 regmap_reg_range(0x5400, 0x5401),
809 regmap_reg_range(0x5403, 0x5403),
810 regmap_reg_range(0x5410, 0x5417),
811 regmap_reg_range(0x5420, 0x5423),
812 regmap_reg_range(0x5500, 0x5507),
813 regmap_reg_range(0x5600, 0x5613),
814 regmap_reg_range(0x5800, 0x580f),
815 regmap_reg_range(0x5820, 0x5827),
816 regmap_reg_range(0x5830, 0x5837),
817 regmap_reg_range(0x5840, 0x584b),
818 regmap_reg_range(0x5900, 0x5907),
819 regmap_reg_range(0x5914, 0x591b),
820 regmap_reg_range(0x5920, 0x5920),
821 regmap_reg_range(0x5923, 0x5927),
822 regmap_reg_range(0x5a00, 0x5a03),
823 regmap_reg_range(0x5a04, 0x5a07),
824 regmap_reg_range(0x5b00, 0x5b01),
825 regmap_reg_range(0x5b04, 0x5b04),
826 regmap_reg_range(0x5c00, 0x5c05),
827 regmap_reg_range(0x5c08, 0x5c1b),
828
829 /* port 6 */
830 regmap_reg_range(0x6000, 0x6001),
831 regmap_reg_range(0x6013, 0x6013),
832 regmap_reg_range(0x6017, 0x6017),
833 regmap_reg_range(0x601b, 0x601b),
834 regmap_reg_range(0x601f, 0x6020),
835 regmap_reg_range(0x6030, 0x6030),
836 regmap_reg_range(0x6300, 0x6301),
837 regmap_reg_range(0x6400, 0x6401),
838 regmap_reg_range(0x6403, 0x6403),
839 regmap_reg_range(0x6410, 0x6417),
840 regmap_reg_range(0x6420, 0x6423),
841 regmap_reg_range(0x6500, 0x6507),
842 regmap_reg_range(0x6600, 0x6613),
843 regmap_reg_range(0x6800, 0x680f),
844 regmap_reg_range(0x6820, 0x6827),
845 regmap_reg_range(0x6830, 0x6837),
846 regmap_reg_range(0x6840, 0x684b),
847 regmap_reg_range(0x6900, 0x6907),
848 regmap_reg_range(0x6914, 0x691b),
849 regmap_reg_range(0x6920, 0x6920),
850 regmap_reg_range(0x6923, 0x6927),
851 regmap_reg_range(0x6a00, 0x6a03),
852 regmap_reg_range(0x6a04, 0x6a07),
853 regmap_reg_range(0x6b00, 0x6b01),
854 regmap_reg_range(0x6b04, 0x6b04),
855 regmap_reg_range(0x6c00, 0x6c05),
856 regmap_reg_range(0x6c08, 0x6c1b),
857
858 /* port 7 */
859 regmap_reg_range(0x7000, 0x7001),
860 regmap_reg_range(0x7013, 0x7013),
861 regmap_reg_range(0x7017, 0x7017),
862 regmap_reg_range(0x701b, 0x701b),
863 regmap_reg_range(0x701f, 0x7020),
864 regmap_reg_range(0x7030, 0x7030),
865 regmap_reg_range(0x7200, 0x7207),
866 regmap_reg_range(0x7300, 0x7301),
867 regmap_reg_range(0x7400, 0x7401),
868 regmap_reg_range(0x7403, 0x7403),
869 regmap_reg_range(0x7410, 0x7417),
870 regmap_reg_range(0x7420, 0x7423),
871 regmap_reg_range(0x7500, 0x7507),
872 regmap_reg_range(0x7600, 0x7613),
873 regmap_reg_range(0x7800, 0x780f),
874 regmap_reg_range(0x7820, 0x7827),
875 regmap_reg_range(0x7830, 0x7837),
876 regmap_reg_range(0x7840, 0x784b),
877 regmap_reg_range(0x7900, 0x7907),
878 regmap_reg_range(0x7914, 0x791b),
879 regmap_reg_range(0x7920, 0x7920),
880 regmap_reg_range(0x7923, 0x7927),
881 regmap_reg_range(0x7a00, 0x7a03),
882 regmap_reg_range(0x7a04, 0x7a07),
883 regmap_reg_range(0x7b00, 0x7b01),
884 regmap_reg_range(0x7b04, 0x7b04),
885 regmap_reg_range(0x7c00, 0x7c05),
886 regmap_reg_range(0x7c08, 0x7c1b),
887 };
888
889 static const struct regmap_access_table ksz9477_register_set = {
890 .yes_ranges = ksz9477_valid_regs,
891 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
892 };
893
894 static const struct regmap_range ksz9896_valid_regs[] = {
895 regmap_reg_range(0x0000, 0x0003),
896 regmap_reg_range(0x0006, 0x0006),
897 regmap_reg_range(0x0010, 0x001f),
898 regmap_reg_range(0x0100, 0x0100),
899 regmap_reg_range(0x0103, 0x0107),
900 regmap_reg_range(0x010d, 0x010d),
901 regmap_reg_range(0x0110, 0x0113),
902 regmap_reg_range(0x0120, 0x0127),
903 regmap_reg_range(0x0201, 0x0201),
904 regmap_reg_range(0x0210, 0x0213),
905 regmap_reg_range(0x0300, 0x0300),
906 regmap_reg_range(0x0302, 0x030b),
907 regmap_reg_range(0x0310, 0x031b),
908 regmap_reg_range(0x0320, 0x032b),
909 regmap_reg_range(0x0330, 0x0336),
910 regmap_reg_range(0x0338, 0x033b),
911 regmap_reg_range(0x033e, 0x033e),
912 regmap_reg_range(0x0340, 0x035f),
913 regmap_reg_range(0x0370, 0x0370),
914 regmap_reg_range(0x0378, 0x0378),
915 regmap_reg_range(0x037c, 0x037d),
916 regmap_reg_range(0x0390, 0x0393),
917 regmap_reg_range(0x0400, 0x040e),
918 regmap_reg_range(0x0410, 0x042f),
919
920 /* port 1 */
921 regmap_reg_range(0x1000, 0x1001),
922 regmap_reg_range(0x1013, 0x1013),
923 regmap_reg_range(0x1017, 0x1017),
924 regmap_reg_range(0x101b, 0x101b),
925 regmap_reg_range(0x101f, 0x1020),
926 regmap_reg_range(0x1030, 0x1030),
927 regmap_reg_range(0x1100, 0x1115),
928 regmap_reg_range(0x111a, 0x111f),
929 regmap_reg_range(0x1120, 0x112b),
930 regmap_reg_range(0x1134, 0x113b),
931 regmap_reg_range(0x113c, 0x113f),
932 regmap_reg_range(0x1400, 0x1401),
933 regmap_reg_range(0x1403, 0x1403),
934 regmap_reg_range(0x1410, 0x1417),
935 regmap_reg_range(0x1420, 0x1423),
936 regmap_reg_range(0x1500, 0x1507),
937 regmap_reg_range(0x1600, 0x1612),
938 regmap_reg_range(0x1800, 0x180f),
939 regmap_reg_range(0x1820, 0x1827),
940 regmap_reg_range(0x1830, 0x1837),
941 regmap_reg_range(0x1840, 0x184b),
942 regmap_reg_range(0x1900, 0x1907),
943 regmap_reg_range(0x1914, 0x1915),
944 regmap_reg_range(0x1a00, 0x1a03),
945 regmap_reg_range(0x1a04, 0x1a07),
946 regmap_reg_range(0x1b00, 0x1b01),
947 regmap_reg_range(0x1b04, 0x1b04),
948
949 /* port 2 */
950 regmap_reg_range(0x2000, 0x2001),
951 regmap_reg_range(0x2013, 0x2013),
952 regmap_reg_range(0x2017, 0x2017),
953 regmap_reg_range(0x201b, 0x201b),
954 regmap_reg_range(0x201f, 0x2020),
955 regmap_reg_range(0x2030, 0x2030),
956 regmap_reg_range(0x2100, 0x2115),
957 regmap_reg_range(0x211a, 0x211f),
958 regmap_reg_range(0x2120, 0x212b),
959 regmap_reg_range(0x2134, 0x213b),
960 regmap_reg_range(0x213c, 0x213f),
961 regmap_reg_range(0x2400, 0x2401),
962 regmap_reg_range(0x2403, 0x2403),
963 regmap_reg_range(0x2410, 0x2417),
964 regmap_reg_range(0x2420, 0x2423),
965 regmap_reg_range(0x2500, 0x2507),
966 regmap_reg_range(0x2600, 0x2612),
967 regmap_reg_range(0x2800, 0x280f),
968 regmap_reg_range(0x2820, 0x2827),
969 regmap_reg_range(0x2830, 0x2837),
970 regmap_reg_range(0x2840, 0x284b),
971 regmap_reg_range(0x2900, 0x2907),
972 regmap_reg_range(0x2914, 0x2915),
973 regmap_reg_range(0x2a00, 0x2a03),
974 regmap_reg_range(0x2a04, 0x2a07),
975 regmap_reg_range(0x2b00, 0x2b01),
976 regmap_reg_range(0x2b04, 0x2b04),
977
978 /* port 3 */
979 regmap_reg_range(0x3000, 0x3001),
980 regmap_reg_range(0x3013, 0x3013),
981 regmap_reg_range(0x3017, 0x3017),
982 regmap_reg_range(0x301b, 0x301b),
983 regmap_reg_range(0x301f, 0x3020),
984 regmap_reg_range(0x3030, 0x3030),
985 regmap_reg_range(0x3100, 0x3115),
986 regmap_reg_range(0x311a, 0x311f),
987 regmap_reg_range(0x3120, 0x312b),
988 regmap_reg_range(0x3134, 0x313b),
989 regmap_reg_range(0x313c, 0x313f),
990 regmap_reg_range(0x3400, 0x3401),
991 regmap_reg_range(0x3403, 0x3403),
992 regmap_reg_range(0x3410, 0x3417),
993 regmap_reg_range(0x3420, 0x3423),
994 regmap_reg_range(0x3500, 0x3507),
995 regmap_reg_range(0x3600, 0x3612),
996 regmap_reg_range(0x3800, 0x380f),
997 regmap_reg_range(0x3820, 0x3827),
998 regmap_reg_range(0x3830, 0x3837),
999 regmap_reg_range(0x3840, 0x384b),
1000 regmap_reg_range(0x3900, 0x3907),
1001 regmap_reg_range(0x3914, 0x3915),
1002 regmap_reg_range(0x3a00, 0x3a03),
1003 regmap_reg_range(0x3a04, 0x3a07),
1004 regmap_reg_range(0x3b00, 0x3b01),
1005 regmap_reg_range(0x3b04, 0x3b04),
1006
1007 /* port 4 */
1008 regmap_reg_range(0x4000, 0x4001),
1009 regmap_reg_range(0x4013, 0x4013),
1010 regmap_reg_range(0x4017, 0x4017),
1011 regmap_reg_range(0x401b, 0x401b),
1012 regmap_reg_range(0x401f, 0x4020),
1013 regmap_reg_range(0x4030, 0x4030),
1014 regmap_reg_range(0x4100, 0x4115),
1015 regmap_reg_range(0x411a, 0x411f),
1016 regmap_reg_range(0x4120, 0x412b),
1017 regmap_reg_range(0x4134, 0x413b),
1018 regmap_reg_range(0x413c, 0x413f),
1019 regmap_reg_range(0x4400, 0x4401),
1020 regmap_reg_range(0x4403, 0x4403),
1021 regmap_reg_range(0x4410, 0x4417),
1022 regmap_reg_range(0x4420, 0x4423),
1023 regmap_reg_range(0x4500, 0x4507),
1024 regmap_reg_range(0x4600, 0x4612),
1025 regmap_reg_range(0x4800, 0x480f),
1026 regmap_reg_range(0x4820, 0x4827),
1027 regmap_reg_range(0x4830, 0x4837),
1028 regmap_reg_range(0x4840, 0x484b),
1029 regmap_reg_range(0x4900, 0x4907),
1030 regmap_reg_range(0x4914, 0x4915),
1031 regmap_reg_range(0x4a00, 0x4a03),
1032 regmap_reg_range(0x4a04, 0x4a07),
1033 regmap_reg_range(0x4b00, 0x4b01),
1034 regmap_reg_range(0x4b04, 0x4b04),
1035
1036 /* port 5 */
1037 regmap_reg_range(0x5000, 0x5001),
1038 regmap_reg_range(0x5013, 0x5013),
1039 regmap_reg_range(0x5017, 0x5017),
1040 regmap_reg_range(0x501b, 0x501b),
1041 regmap_reg_range(0x501f, 0x5020),
1042 regmap_reg_range(0x5030, 0x5030),
1043 regmap_reg_range(0x5100, 0x5115),
1044 regmap_reg_range(0x511a, 0x511f),
1045 regmap_reg_range(0x5120, 0x512b),
1046 regmap_reg_range(0x5134, 0x513b),
1047 regmap_reg_range(0x513c, 0x513f),
1048 regmap_reg_range(0x5400, 0x5401),
1049 regmap_reg_range(0x5403, 0x5403),
1050 regmap_reg_range(0x5410, 0x5417),
1051 regmap_reg_range(0x5420, 0x5423),
1052 regmap_reg_range(0x5500, 0x5507),
1053 regmap_reg_range(0x5600, 0x5612),
1054 regmap_reg_range(0x5800, 0x580f),
1055 regmap_reg_range(0x5820, 0x5827),
1056 regmap_reg_range(0x5830, 0x5837),
1057 regmap_reg_range(0x5840, 0x584b),
1058 regmap_reg_range(0x5900, 0x5907),
1059 regmap_reg_range(0x5914, 0x5915),
1060 regmap_reg_range(0x5a00, 0x5a03),
1061 regmap_reg_range(0x5a04, 0x5a07),
1062 regmap_reg_range(0x5b00, 0x5b01),
1063 regmap_reg_range(0x5b04, 0x5b04),
1064
1065 /* port 6 */
1066 regmap_reg_range(0x6000, 0x6001),
1067 regmap_reg_range(0x6013, 0x6013),
1068 regmap_reg_range(0x6017, 0x6017),
1069 regmap_reg_range(0x601b, 0x601b),
1070 regmap_reg_range(0x601f, 0x6020),
1071 regmap_reg_range(0x6030, 0x6030),
1072 regmap_reg_range(0x6100, 0x6115),
1073 regmap_reg_range(0x611a, 0x611f),
1074 regmap_reg_range(0x6120, 0x612b),
1075 regmap_reg_range(0x6134, 0x613b),
1076 regmap_reg_range(0x613c, 0x613f),
1077 regmap_reg_range(0x6300, 0x6301),
1078 regmap_reg_range(0x6400, 0x6401),
1079 regmap_reg_range(0x6403, 0x6403),
1080 regmap_reg_range(0x6410, 0x6417),
1081 regmap_reg_range(0x6420, 0x6423),
1082 regmap_reg_range(0x6500, 0x6507),
1083 regmap_reg_range(0x6600, 0x6612),
1084 regmap_reg_range(0x6800, 0x680f),
1085 regmap_reg_range(0x6820, 0x6827),
1086 regmap_reg_range(0x6830, 0x6837),
1087 regmap_reg_range(0x6840, 0x684b),
1088 regmap_reg_range(0x6900, 0x6907),
1089 regmap_reg_range(0x6914, 0x6915),
1090 regmap_reg_range(0x6a00, 0x6a03),
1091 regmap_reg_range(0x6a04, 0x6a07),
1092 regmap_reg_range(0x6b00, 0x6b01),
1093 regmap_reg_range(0x6b04, 0x6b04),
1094 };
1095
1096 static const struct regmap_access_table ksz9896_register_set = {
1097 .yes_ranges = ksz9896_valid_regs,
1098 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1099 };
1100
1101 static const struct regmap_range ksz8873_valid_regs[] = {
1102 regmap_reg_range(0x00, 0x01),
1103 /* global control register */
1104 regmap_reg_range(0x02, 0x0f),
1105
1106 /* port registers */
1107 regmap_reg_range(0x10, 0x1d),
1108 regmap_reg_range(0x1e, 0x1f),
1109 regmap_reg_range(0x20, 0x2d),
1110 regmap_reg_range(0x2e, 0x2f),
1111 regmap_reg_range(0x30, 0x39),
1112 regmap_reg_range(0x3f, 0x3f),
1113
1114 /* advanced control registers */
1115 regmap_reg_range(0x43, 0x43),
1116 regmap_reg_range(0x60, 0x6f),
1117 regmap_reg_range(0x70, 0x75),
1118 regmap_reg_range(0x76, 0x78),
1119 regmap_reg_range(0x79, 0x7a),
1120 regmap_reg_range(0x7b, 0x83),
1121 regmap_reg_range(0x8e, 0x99),
1122 regmap_reg_range(0x9a, 0xa5),
1123 regmap_reg_range(0xa6, 0xa6),
1124 regmap_reg_range(0xa7, 0xaa),
1125 regmap_reg_range(0xab, 0xae),
1126 regmap_reg_range(0xaf, 0xba),
1127 regmap_reg_range(0xbb, 0xbc),
1128 regmap_reg_range(0xbd, 0xbd),
1129 regmap_reg_range(0xc0, 0xc0),
1130 regmap_reg_range(0xc2, 0xc2),
1131 regmap_reg_range(0xc3, 0xc3),
1132 regmap_reg_range(0xc4, 0xc4),
1133 regmap_reg_range(0xc6, 0xc6),
1134 };
1135
1136 static const struct regmap_access_table ksz8873_register_set = {
1137 .yes_ranges = ksz8873_valid_regs,
1138 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1139 };
1140
1141 const struct ksz_chip_data ksz_switch_chips[] = {
1142 [KSZ8463] = {
1143 .chip_id = KSZ8463_CHIP_ID,
1144 .dev_name = "KSZ8463",
1145 .num_vlans = 16,
1146 .num_alus = 0,
1147 .num_statics = 8,
1148 .cpu_ports = 0x4, /* can be configured as cpu port */
1149 .port_cnt = 3,
1150 .num_tx_queues = 4,
1151 .num_ipms = 4,
1152 .ops = &ksz8463_dev_ops,
1153 .switch_ops = &ksz8463_switch_ops,
1154 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1155 .mib_names = ksz88xx_mib_names,
1156 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1157 .reg_mib_cnt = MIB_COUNTER_NUM,
1158 .regs = ksz8463_regs,
1159 .masks = ksz8463_masks,
1160 .shifts = ksz8463_shifts,
1161 .supports_mii = {false, false, true},
1162 .supports_rmii = {false, false, true},
1163 .internal_phy = {true, true, false},
1164 },
1165
1166 [KSZ8563] = {
1167 .chip_id = KSZ8563_CHIP_ID,
1168 .dev_name = "KSZ8563",
1169 .num_vlans = 4096,
1170 .num_alus = 4096,
1171 .num_statics = 16,
1172 .cpu_ports = 0x07, /* can be configured as cpu port */
1173 .port_cnt = 3, /* total port count */
1174 .port_nirqs = 3,
1175 .num_tx_queues = 4,
1176 .num_ipms = 8,
1177 .tc_cbs_supported = true,
1178 .ops = &ksz9477_dev_ops,
1179 .switch_ops = &ksz9477_switch_ops,
1180 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1181 .mib_names = ksz9477_mib_names,
1182 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1183 .reg_mib_cnt = MIB_COUNTER_NUM,
1184 .regs = ksz9477_regs,
1185 .masks = ksz9477_masks,
1186 .shifts = ksz9477_shifts,
1187 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1188 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1189 .supports_mii = {false, false, true},
1190 .supports_rmii = {false, false, true},
1191 .supports_rgmii = {false, false, true},
1192 .internal_phy = {true, true, false},
1193 .gbit_capable = {false, false, true},
1194 .ptp_capable = true,
1195 .wr_table = &ksz8563_register_set,
1196 .rd_table = &ksz8563_register_set,
1197 },
1198
1199 [KSZ8795] = {
1200 .chip_id = KSZ8795_CHIP_ID,
1201 .dev_name = "KSZ8795",
1202 .num_vlans = 4096,
1203 .num_alus = 0,
1204 .num_statics = 32,
1205 .cpu_ports = 0x10, /* can be configured as cpu port */
1206 .port_cnt = 5, /* total cpu and user ports */
1207 .num_tx_queues = 4,
1208 .num_ipms = 4,
1209 .ops = &ksz87xx_dev_ops,
1210 .switch_ops = &ksz87xx_switch_ops,
1211 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1212 .ksz87xx_eee_link_erratum = true,
1213 .mib_names = ksz9477_mib_names,
1214 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1215 .reg_mib_cnt = MIB_COUNTER_NUM,
1216 .regs = ksz8795_regs,
1217 .masks = ksz8795_masks,
1218 .shifts = ksz8795_shifts,
1219 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1220 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1221 .supports_mii = {false, false, false, false, true},
1222 .supports_rmii = {false, false, false, false, true},
1223 .supports_rgmii = {false, false, false, false, true},
1224 .internal_phy = {true, true, true, true, false},
1225 },
1226
1227 [KSZ8794] = {
1228 /* WARNING
1229 * =======
1230 * KSZ8794 is similar to KSZ8795, except the port map
1231 * contains a gap between external and CPU ports, the
1232 * port map is NOT continuous. The per-port register
1233 * map is shifted accordingly too, i.e. registers at
1234 * offset 0x40 are NOT used on KSZ8794 and they ARE
1235 * used on KSZ8795 for external port 3.
1236 * external cpu
1237 * KSZ8794 0,1,2 4
1238 * KSZ8795 0,1,2,3 4
1239 * KSZ8765 0,1,2,3 4
1240 * port_cnt is configured as 5, even though it is 4
1241 */
1242 .chip_id = KSZ8794_CHIP_ID,
1243 .dev_name = "KSZ8794",
1244 .num_vlans = 4096,
1245 .num_alus = 0,
1246 .num_statics = 32,
1247 .cpu_ports = 0x10, /* can be configured as cpu port */
1248 .port_cnt = 5, /* total cpu and user ports */
1249 .num_tx_queues = 4,
1250 .num_ipms = 4,
1251 .ops = &ksz87xx_dev_ops,
1252 .switch_ops = &ksz87xx_switch_ops,
1253 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1254 .ksz87xx_eee_link_erratum = true,
1255 .mib_names = ksz9477_mib_names,
1256 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1257 .reg_mib_cnt = MIB_COUNTER_NUM,
1258 .regs = ksz8795_regs,
1259 .masks = ksz8795_masks,
1260 .shifts = ksz8795_shifts,
1261 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1262 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1263 .supports_mii = {false, false, false, false, true},
1264 .supports_rmii = {false, false, false, false, true},
1265 .supports_rgmii = {false, false, false, false, true},
1266 .internal_phy = {true, true, true, false, false},
1267 },
1268
1269 [KSZ8765] = {
1270 .chip_id = KSZ8765_CHIP_ID,
1271 .dev_name = "KSZ8765",
1272 .num_vlans = 4096,
1273 .num_alus = 0,
1274 .num_statics = 32,
1275 .cpu_ports = 0x10, /* can be configured as cpu port */
1276 .port_cnt = 5, /* total cpu and user ports */
1277 .num_tx_queues = 4,
1278 .num_ipms = 4,
1279 .ops = &ksz87xx_dev_ops,
1280 .switch_ops = &ksz87xx_switch_ops,
1281 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1282 .ksz87xx_eee_link_erratum = true,
1283 .mib_names = ksz9477_mib_names,
1284 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1285 .reg_mib_cnt = MIB_COUNTER_NUM,
1286 .regs = ksz8795_regs,
1287 .masks = ksz8795_masks,
1288 .shifts = ksz8795_shifts,
1289 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1290 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1291 .supports_mii = {false, false, false, false, true},
1292 .supports_rmii = {false, false, false, false, true},
1293 .supports_rgmii = {false, false, false, false, true},
1294 .internal_phy = {true, true, true, true, false},
1295 },
1296
1297 [KSZ88X3] = {
1298 .chip_id = KSZ88X3_CHIP_ID,
1299 .dev_name = "KSZ8863/KSZ8873",
1300 .num_vlans = 16,
1301 .num_alus = 0,
1302 .num_statics = 8,
1303 .cpu_ports = 0x4, /* can be configured as cpu port */
1304 .port_cnt = 3,
1305 .num_tx_queues = 4,
1306 .num_ipms = 4,
1307 .ops = &ksz88xx_dev_ops,
1308 .switch_ops = &ksz88xx_switch_ops,
1309 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1310 .mib_names = ksz88xx_mib_names,
1311 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1312 .reg_mib_cnt = MIB_COUNTER_NUM,
1313 .regs = ksz8863_regs,
1314 .masks = ksz8863_masks,
1315 .shifts = ksz8863_shifts,
1316 .supports_mii = {false, false, true},
1317 .supports_rmii = {false, false, true},
1318 .internal_phy = {true, true, false},
1319 .wr_table = &ksz8873_register_set,
1320 .rd_table = &ksz8873_register_set,
1321 },
1322
1323 [KSZ8864] = {
1324 /* WARNING
1325 * =======
1326 * KSZ8864 is similar to KSZ8895, except the first port
1327 * does not exist.
1328 * external cpu
1329 * KSZ8864 1,2,3 4
1330 * KSZ8895 0,1,2,3 4
1331 * port_cnt is configured as 5, even though it is 4
1332 */
1333 .chip_id = KSZ8864_CHIP_ID,
1334 .dev_name = "KSZ8864",
1335 .num_vlans = 4096,
1336 .num_alus = 0,
1337 .num_statics = 32,
1338 .cpu_ports = 0x10, /* can be configured as cpu port */
1339 .port_cnt = 5, /* total cpu and user ports */
1340 .num_tx_queues = 4,
1341 .num_ipms = 4,
1342 .ops = &ksz88xx_dev_ops,
1343 .switch_ops = &ksz88xx_switch_ops,
1344 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1345 .mib_names = ksz88xx_mib_names,
1346 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1347 .reg_mib_cnt = MIB_COUNTER_NUM,
1348 .regs = ksz8895_regs,
1349 .masks = ksz8895_masks,
1350 .shifts = ksz8895_shifts,
1351 .supports_mii = {false, false, false, false, true},
1352 .supports_rmii = {false, false, false, false, true},
1353 .internal_phy = {false, true, true, true, false},
1354 },
1355
1356 [KSZ8895] = {
1357 .chip_id = KSZ8895_CHIP_ID,
1358 .dev_name = "KSZ8895",
1359 .num_vlans = 4096,
1360 .num_alus = 0,
1361 .num_statics = 32,
1362 .cpu_ports = 0x10, /* can be configured as cpu port */
1363 .port_cnt = 5, /* total cpu and user ports */
1364 .num_tx_queues = 4,
1365 .num_ipms = 4,
1366 .ops = &ksz88xx_dev_ops,
1367 .switch_ops = &ksz88xx_switch_ops,
1368 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1369 .mib_names = ksz88xx_mib_names,
1370 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1371 .reg_mib_cnt = MIB_COUNTER_NUM,
1372 .regs = ksz8895_regs,
1373 .masks = ksz8895_masks,
1374 .shifts = ksz8895_shifts,
1375 .supports_mii = {false, false, false, false, true},
1376 .supports_rmii = {false, false, false, false, true},
1377 .internal_phy = {true, true, true, true, false},
1378 },
1379
1380 [KSZ9477] = {
1381 .chip_id = KSZ9477_CHIP_ID,
1382 .dev_name = "KSZ9477",
1383 .num_vlans = 4096,
1384 .num_alus = 4096,
1385 .num_statics = 16,
1386 .cpu_ports = 0x7F, /* can be configured as cpu port */
1387 .port_cnt = 7, /* total physical port count */
1388 .port_nirqs = 4,
1389 .num_tx_queues = 4,
1390 .num_ipms = 8,
1391 .tc_cbs_supported = true,
1392 .ops = &ksz9477_dev_ops,
1393 .switch_ops = &ksz9477_switch_ops,
1394 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1395 .phy_errata_9477 = true,
1396 .mib_names = ksz9477_mib_names,
1397 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1398 .reg_mib_cnt = MIB_COUNTER_NUM,
1399 .regs = ksz9477_regs,
1400 .masks = ksz9477_masks,
1401 .shifts = ksz9477_shifts,
1402 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1403 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1404 .supports_mii = {false, false, false, false,
1405 false, true, false},
1406 .supports_rmii = {false, false, false, false,
1407 false, true, false},
1408 .supports_rgmii = {false, false, false, false,
1409 false, true, false},
1410 .internal_phy = {true, true, true, true,
1411 true, false, false},
1412 .gbit_capable = {true, true, true, true, true, true, true},
1413 .ptp_capable = true,
1414 .sgmii_port = 7,
1415 .wr_table = &ksz9477_register_set,
1416 .rd_table = &ksz9477_register_set,
1417 },
1418
1419 [KSZ9896] = {
1420 .chip_id = KSZ9896_CHIP_ID,
1421 .dev_name = "KSZ9896",
1422 .num_vlans = 4096,
1423 .num_alus = 4096,
1424 .num_statics = 16,
1425 .cpu_ports = 0x3F, /* can be configured as cpu port */
1426 .port_cnt = 6, /* total physical port count */
1427 .port_nirqs = 2,
1428 .num_tx_queues = 4,
1429 .num_ipms = 8,
1430 .ops = &ksz9477_dev_ops,
1431 .switch_ops = &ksz9477_switch_ops,
1432 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1433 .phy_errata_9477 = true,
1434 .mib_names = ksz9477_mib_names,
1435 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1436 .reg_mib_cnt = MIB_COUNTER_NUM,
1437 .regs = ksz9477_regs,
1438 .masks = ksz9477_masks,
1439 .shifts = ksz9477_shifts,
1440 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1441 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1442 .supports_mii = {false, false, false, false,
1443 false, true},
1444 .supports_rmii = {false, false, false, false,
1445 false, true},
1446 .supports_rgmii = {false, false, false, false,
1447 false, true},
1448 .internal_phy = {true, true, true, true,
1449 true, false},
1450 .gbit_capable = {true, true, true, true, true, true},
1451 .wr_table = &ksz9896_register_set,
1452 .rd_table = &ksz9896_register_set,
1453 },
1454
1455 [KSZ9897] = {
1456 .chip_id = KSZ9897_CHIP_ID,
1457 .dev_name = "KSZ9897",
1458 .num_vlans = 4096,
1459 .num_alus = 4096,
1460 .num_statics = 16,
1461 .cpu_ports = 0x7F, /* can be configured as cpu port */
1462 .port_cnt = 7, /* total physical port count */
1463 .port_nirqs = 2,
1464 .num_tx_queues = 4,
1465 .num_ipms = 8,
1466 .ops = &ksz9477_dev_ops,
1467 .switch_ops = &ksz9477_switch_ops,
1468 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1469 .phy_errata_9477 = true,
1470 .mib_names = ksz9477_mib_names,
1471 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1472 .reg_mib_cnt = MIB_COUNTER_NUM,
1473 .regs = ksz9477_regs,
1474 .masks = ksz9477_masks,
1475 .shifts = ksz9477_shifts,
1476 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1477 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1478 .supports_mii = {false, false, false, false,
1479 false, true, true},
1480 .supports_rmii = {false, false, false, false,
1481 false, true, true},
1482 .supports_rgmii = {false, false, false, false,
1483 false, true, true},
1484 .internal_phy = {true, true, true, true,
1485 true, false, false},
1486 .gbit_capable = {true, true, true, true, true, true, true},
1487 },
1488
1489 [KSZ9893] = {
1490 .chip_id = KSZ9893_CHIP_ID,
1491 .dev_name = "KSZ9893",
1492 .num_vlans = 4096,
1493 .num_alus = 4096,
1494 .num_statics = 16,
1495 .cpu_ports = 0x07, /* can be configured as cpu port */
1496 .port_cnt = 3, /* total port count */
1497 .port_nirqs = 2,
1498 .num_tx_queues = 4,
1499 .num_ipms = 8,
1500 .ops = &ksz9477_dev_ops,
1501 .switch_ops = &ksz9477_switch_ops,
1502 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1503 .mib_names = ksz9477_mib_names,
1504 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1505 .reg_mib_cnt = MIB_COUNTER_NUM,
1506 .regs = ksz9477_regs,
1507 .masks = ksz9477_masks,
1508 .shifts = ksz9477_shifts,
1509 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1510 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1511 .supports_mii = {false, false, true},
1512 .supports_rmii = {false, false, true},
1513 .supports_rgmii = {false, false, true},
1514 .internal_phy = {true, true, false},
1515 .gbit_capable = {true, true, true},
1516 },
1517
1518 [KSZ9563] = {
1519 .chip_id = KSZ9563_CHIP_ID,
1520 .dev_name = "KSZ9563",
1521 .num_vlans = 4096,
1522 .num_alus = 4096,
1523 .num_statics = 16,
1524 .cpu_ports = 0x07, /* can be configured as cpu port */
1525 .port_cnt = 3, /* total port count */
1526 .port_nirqs = 3,
1527 .num_tx_queues = 4,
1528 .num_ipms = 8,
1529 .tc_cbs_supported = true,
1530 .ops = &ksz9477_dev_ops,
1531 .switch_ops = &ksz9477_switch_ops,
1532 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1533 .mib_names = ksz9477_mib_names,
1534 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1535 .reg_mib_cnt = MIB_COUNTER_NUM,
1536 .regs = ksz9477_regs,
1537 .masks = ksz9477_masks,
1538 .shifts = ksz9477_shifts,
1539 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1540 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1541 .supports_mii = {false, false, true},
1542 .supports_rmii = {false, false, true},
1543 .supports_rgmii = {false, false, true},
1544 .internal_phy = {true, true, false},
1545 .gbit_capable = {true, true, true},
1546 .ptp_capable = true,
1547 },
1548
1549 [KSZ8567] = {
1550 .chip_id = KSZ8567_CHIP_ID,
1551 .dev_name = "KSZ8567",
1552 .num_vlans = 4096,
1553 .num_alus = 4096,
1554 .num_statics = 16,
1555 .cpu_ports = 0x7F, /* can be configured as cpu port */
1556 .port_cnt = 7, /* total port count */
1557 .port_nirqs = 3,
1558 .num_tx_queues = 4,
1559 .num_ipms = 8,
1560 .tc_cbs_supported = true,
1561 .ops = &ksz9477_dev_ops,
1562 .switch_ops = &ksz9477_switch_ops,
1563 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1564 .phy_errata_9477 = true,
1565 .mib_names = ksz9477_mib_names,
1566 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1567 .reg_mib_cnt = MIB_COUNTER_NUM,
1568 .regs = ksz9477_regs,
1569 .masks = ksz9477_masks,
1570 .shifts = ksz9477_shifts,
1571 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1572 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1573 .supports_mii = {false, false, false, false,
1574 false, true, true},
1575 .supports_rmii = {false, false, false, false,
1576 false, true, true},
1577 .supports_rgmii = {false, false, false, false,
1578 false, true, true},
1579 .internal_phy = {true, true, true, true,
1580 true, false, false},
1581 .gbit_capable = {false, false, false, false, false,
1582 true, true},
1583 .ptp_capable = true,
1584 },
1585
1586 [KSZ9567] = {
1587 .chip_id = KSZ9567_CHIP_ID,
1588 .dev_name = "KSZ9567",
1589 .num_vlans = 4096,
1590 .num_alus = 4096,
1591 .num_statics = 16,
1592 .cpu_ports = 0x7F, /* can be configured as cpu port */
1593 .port_cnt = 7, /* total physical port count */
1594 .port_nirqs = 3,
1595 .num_tx_queues = 4,
1596 .num_ipms = 8,
1597 .tc_cbs_supported = true,
1598 .ops = &ksz9477_dev_ops,
1599 .switch_ops = &ksz9477_switch_ops,
1600 .mib_names = ksz9477_mib_names,
1601 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1602 .reg_mib_cnt = MIB_COUNTER_NUM,
1603 .regs = ksz9477_regs,
1604 .masks = ksz9477_masks,
1605 .shifts = ksz9477_shifts,
1606 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1607 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1608 .supports_mii = {false, false, false, false,
1609 false, true, true},
1610 .supports_rmii = {false, false, false, false,
1611 false, true, true},
1612 .supports_rgmii = {false, false, false, false,
1613 false, true, true},
1614 .internal_phy = {true, true, true, true,
1615 true, false, false},
1616 .gbit_capable = {true, true, true, true, true, true, true},
1617 .ptp_capable = true,
1618 },
1619
1620 [LAN9370] = {
1621 .chip_id = LAN9370_CHIP_ID,
1622 .dev_name = "LAN9370",
1623 .num_vlans = 4096,
1624 .num_alus = 1024,
1625 .num_statics = 256,
1626 .cpu_ports = 0x10, /* can be configured as cpu port */
1627 .port_cnt = 5, /* total physical port count */
1628 .port_nirqs = 6,
1629 .num_tx_queues = 8,
1630 .num_ipms = 8,
1631 .tc_cbs_supported = true,
1632 .phy_side_mdio_supported = true,
1633 .ops = &lan937x_dev_ops,
1634 .switch_ops = &lan937x_switch_ops,
1635 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1636 .mib_names = ksz9477_mib_names,
1637 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1638 .reg_mib_cnt = MIB_COUNTER_NUM,
1639 .regs = ksz9477_regs,
1640 .masks = lan937x_masks,
1641 .shifts = lan937x_shifts,
1642 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1643 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1644 .supports_mii = {false, false, false, false, true},
1645 .supports_rmii = {false, false, false, false, true},
1646 .supports_rgmii = {false, false, false, false, true},
1647 .internal_phy = {true, true, true, true, false},
1648 .ptp_capable = true,
1649 },
1650
1651 [LAN9371] = {
1652 .chip_id = LAN9371_CHIP_ID,
1653 .dev_name = "LAN9371",
1654 .num_vlans = 4096,
1655 .num_alus = 1024,
1656 .num_statics = 256,
1657 .cpu_ports = 0x30, /* can be configured as cpu port */
1658 .port_cnt = 6, /* total physical port count */
1659 .port_nirqs = 6,
1660 .num_tx_queues = 8,
1661 .num_ipms = 8,
1662 .tc_cbs_supported = true,
1663 .phy_side_mdio_supported = true,
1664 .ops = &lan937x_dev_ops,
1665 .switch_ops = &lan937x_switch_ops,
1666 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1667 .mib_names = ksz9477_mib_names,
1668 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1669 .reg_mib_cnt = MIB_COUNTER_NUM,
1670 .regs = ksz9477_regs,
1671 .masks = lan937x_masks,
1672 .shifts = lan937x_shifts,
1673 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1674 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1675 .supports_mii = {false, false, false, false, true, true},
1676 .supports_rmii = {false, false, false, false, true, true},
1677 .supports_rgmii = {false, false, false, false, true, true},
1678 .internal_phy = {true, true, true, true, false, false},
1679 .ptp_capable = true,
1680 },
1681
1682 [LAN9372] = {
1683 .chip_id = LAN9372_CHIP_ID,
1684 .dev_name = "LAN9372",
1685 .num_vlans = 4096,
1686 .num_alus = 1024,
1687 .num_statics = 256,
1688 .cpu_ports = 0x30, /* can be configured as cpu port */
1689 .port_cnt = 8, /* total physical port count */
1690 .port_nirqs = 6,
1691 .num_tx_queues = 8,
1692 .num_ipms = 8,
1693 .tc_cbs_supported = true,
1694 .phy_side_mdio_supported = true,
1695 .ops = &lan937x_dev_ops,
1696 .switch_ops = &lan937x_switch_ops,
1697 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1698 .mib_names = ksz9477_mib_names,
1699 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1700 .reg_mib_cnt = MIB_COUNTER_NUM,
1701 .regs = ksz9477_regs,
1702 .masks = lan937x_masks,
1703 .shifts = lan937x_shifts,
1704 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1705 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1706 .supports_mii = {false, false, false, false,
1707 true, true, false, false},
1708 .supports_rmii = {false, false, false, false,
1709 true, true, false, false},
1710 .supports_rgmii = {false, false, false, false,
1711 true, true, false, false},
1712 .internal_phy = {true, true, true, true,
1713 false, false, true, true},
1714 .ptp_capable = true,
1715 },
1716
1717 [LAN9373] = {
1718 .chip_id = LAN9373_CHIP_ID,
1719 .dev_name = "LAN9373",
1720 .num_vlans = 4096,
1721 .num_alus = 1024,
1722 .num_statics = 256,
1723 .cpu_ports = 0x38, /* can be configured as cpu port */
1724 .port_cnt = 5, /* total physical port count */
1725 .port_nirqs = 6,
1726 .num_tx_queues = 8,
1727 .num_ipms = 8,
1728 .tc_cbs_supported = true,
1729 .phy_side_mdio_supported = true,
1730 .ops = &lan937x_dev_ops,
1731 .switch_ops = &lan937x_switch_ops,
1732 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1733 .mib_names = ksz9477_mib_names,
1734 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1735 .reg_mib_cnt = MIB_COUNTER_NUM,
1736 .regs = ksz9477_regs,
1737 .masks = lan937x_masks,
1738 .shifts = lan937x_shifts,
1739 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1740 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1741 .supports_mii = {false, false, false, false,
1742 true, true, false, false},
1743 .supports_rmii = {false, false, false, false,
1744 true, true, false, false},
1745 .supports_rgmii = {false, false, false, false,
1746 true, true, false, false},
1747 .internal_phy = {true, true, true, false,
1748 false, false, true, true},
1749 .ptp_capable = true,
1750 },
1751
1752 [LAN9374] = {
1753 .chip_id = LAN9374_CHIP_ID,
1754 .dev_name = "LAN9374",
1755 .num_vlans = 4096,
1756 .num_alus = 1024,
1757 .num_statics = 256,
1758 .cpu_ports = 0x30, /* can be configured as cpu port */
1759 .port_cnt = 8, /* total physical port count */
1760 .port_nirqs = 6,
1761 .num_tx_queues = 8,
1762 .num_ipms = 8,
1763 .tc_cbs_supported = true,
1764 .phy_side_mdio_supported = true,
1765 .ops = &lan937x_dev_ops,
1766 .switch_ops = &lan937x_switch_ops,
1767 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1768 .mib_names = ksz9477_mib_names,
1769 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1770 .reg_mib_cnt = MIB_COUNTER_NUM,
1771 .regs = ksz9477_regs,
1772 .masks = lan937x_masks,
1773 .shifts = lan937x_shifts,
1774 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1775 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1776 .supports_mii = {false, false, false, false,
1777 true, true, false, false},
1778 .supports_rmii = {false, false, false, false,
1779 true, true, false, false},
1780 .supports_rgmii = {false, false, false, false,
1781 true, true, false, false},
1782 .internal_phy = {true, true, true, true,
1783 false, false, true, true},
1784 .ptp_capable = true,
1785 },
1786
1787 [LAN9646] = {
1788 .chip_id = LAN9646_CHIP_ID,
1789 .dev_name = "LAN9646",
1790 .num_vlans = 4096,
1791 .num_alus = 4096,
1792 .num_statics = 16,
1793 .cpu_ports = 0x7F, /* can be configured as cpu port */
1794 .port_cnt = 7, /* total physical port count */
1795 .port_nirqs = 4,
1796 .num_tx_queues = 4,
1797 .num_ipms = 8,
1798 .ops = &ksz9477_dev_ops,
1799 .switch_ops = &ksz9477_switch_ops,
1800 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1801 .phy_errata_9477 = true,
1802 .mib_names = ksz9477_mib_names,
1803 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1804 .reg_mib_cnt = MIB_COUNTER_NUM,
1805 .regs = ksz9477_regs,
1806 .masks = ksz9477_masks,
1807 .shifts = ksz9477_shifts,
1808 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1809 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1810 .supports_mii = {false, false, false, false,
1811 false, true, true},
1812 .supports_rmii = {false, false, false, false,
1813 false, true, true},
1814 .supports_rgmii = {false, false, false, false,
1815 false, true, true},
1816 .internal_phy = {true, true, true, true,
1817 true, false, false},
1818 .gbit_capable = {true, true, true, true, true, true, true},
1819 .sgmii_port = 7,
1820 .wr_table = &ksz9477_register_set,
1821 .rd_table = &ksz9477_register_set,
1822 },
1823 };
1824 EXPORT_SYMBOL_GPL(ksz_switch_chips);
1825
ksz_lookup_info(unsigned int prod_num)1826 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1827 {
1828 int i;
1829
1830 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1831 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1832
1833 if (chip->chip_id == prod_num)
1834 return chip;
1835 }
1836
1837 return NULL;
1838 }
1839
ksz_check_device_id(struct ksz_device * dev)1840 static int ksz_check_device_id(struct ksz_device *dev)
1841 {
1842 const struct ksz_chip_data *expected_chip_data;
1843 u32 expected_chip_id;
1844
1845 if (dev->pdata) {
1846 expected_chip_id = dev->pdata->chip_id;
1847 expected_chip_data = ksz_lookup_info(expected_chip_id);
1848 if (WARN_ON(!expected_chip_data))
1849 return -ENODEV;
1850 } else {
1851 expected_chip_data = of_device_get_match_data(dev->dev);
1852 expected_chip_id = expected_chip_data->chip_id;
1853 }
1854
1855 if (expected_chip_id != dev->chip_id) {
1856 dev_err(dev->dev,
1857 "Device tree specifies chip %s but found %s, please fix it!\n",
1858 expected_chip_data->dev_name, dev->info->dev_name);
1859 return -ENODEV;
1860 }
1861
1862 return 0;
1863 }
1864
ksz_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1865 void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1866 struct phylink_config *config)
1867 {
1868 struct ksz_device *dev = ds->priv;
1869
1870 if (dev->info->supports_mii[port])
1871 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1872
1873 if (dev->info->supports_rmii[port])
1874 __set_bit(PHY_INTERFACE_MODE_RMII,
1875 config->supported_interfaces);
1876
1877 if (dev->info->supports_rgmii[port])
1878 phy_interface_set_rgmii(config->supported_interfaces);
1879
1880 if (dev->info->internal_phy[port]) {
1881 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1882 config->supported_interfaces);
1883 /* Compatibility for phylib's default interface type when the
1884 * phy-mode property is absent
1885 */
1886 __set_bit(PHY_INTERFACE_MODE_GMII,
1887 config->supported_interfaces);
1888 }
1889
1890 if (ds->ops->support_eee && ds->ops->support_eee(ds, port)) {
1891 memcpy(config->lpi_interfaces, config->supported_interfaces,
1892 sizeof(config->lpi_interfaces));
1893
1894 config->lpi_capabilities = MAC_100FD;
1895 if (dev->info->gbit_capable[port])
1896 config->lpi_capabilities |= MAC_1000FD;
1897
1898 /* EEE is fully operational */
1899 config->eee_enabled_default = true;
1900 }
1901 }
1902
ksz_r_mib_stats64(struct ksz_device * dev,int port)1903 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1904 {
1905 struct ethtool_pause_stats *pstats;
1906 struct rtnl_link_stats64 *stats;
1907 struct ksz_stats_raw *raw;
1908 struct ksz_port_mib *mib;
1909
1910 mib = &dev->ports[port].mib;
1911 stats = &mib->stats64;
1912 pstats = &mib->pause_stats;
1913 raw = (struct ksz_stats_raw *)mib->counters;
1914
1915 spin_lock(&mib->stats64_lock);
1916
1917 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1918 raw->rx_pause;
1919 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1920 raw->tx_pause;
1921
1922 /* HW counters are counting bytes + FCS which is not acceptable
1923 * for rtnl_link_stats64 interface
1924 */
1925 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1926 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1927
1928 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1929 raw->rx_oversize;
1930
1931 stats->rx_crc_errors = raw->rx_crc_err;
1932 stats->rx_frame_errors = raw->rx_align_err;
1933 stats->rx_dropped = raw->rx_discards;
1934 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1935 stats->rx_frame_errors + stats->rx_dropped;
1936
1937 stats->tx_window_errors = raw->tx_late_col;
1938 stats->tx_fifo_errors = raw->tx_discards;
1939 stats->tx_aborted_errors = raw->tx_exc_col;
1940 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1941 stats->tx_aborted_errors;
1942
1943 stats->multicast = raw->rx_mcast;
1944 stats->collisions = raw->tx_total_col;
1945
1946 pstats->tx_pause_frames = raw->tx_pause;
1947 pstats->rx_pause_frames = raw->rx_pause;
1948
1949 spin_unlock(&mib->stats64_lock);
1950 }
1951
ksz_get_stats64(struct dsa_switch * ds,int port,struct rtnl_link_stats64 * s)1952 void ksz_get_stats64(struct dsa_switch *ds, int port,
1953 struct rtnl_link_stats64 *s)
1954 {
1955 struct ksz_device *dev = ds->priv;
1956 struct ksz_port_mib *mib;
1957
1958 mib = &dev->ports[port].mib;
1959
1960 spin_lock(&mib->stats64_lock);
1961 memcpy(s, &mib->stats64, sizeof(*s));
1962 spin_unlock(&mib->stats64_lock);
1963 }
1964
ksz_get_pause_stats(struct dsa_switch * ds,int port,struct ethtool_pause_stats * pause_stats)1965 void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1966 struct ethtool_pause_stats *pause_stats)
1967 {
1968 struct ksz_device *dev = ds->priv;
1969 struct ksz_port_mib *mib;
1970
1971 mib = &dev->ports[port].mib;
1972
1973 spin_lock(&mib->stats64_lock);
1974 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1975 spin_unlock(&mib->stats64_lock);
1976 }
1977
ksz_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * buf)1978 void ksz_get_strings(struct dsa_switch *ds, int port,
1979 u32 stringset, uint8_t *buf)
1980 {
1981 struct ksz_device *dev = ds->priv;
1982 int i;
1983
1984 if (stringset != ETH_SS_STATS)
1985 return;
1986
1987 for (i = 0; i < dev->info->mib_cnt; i++)
1988 ethtool_puts(&buf, dev->info->mib_names[i].string);
1989 }
1990
1991 /**
1992 * ksz_update_port_member - Adjust port forwarding rules based on STP state and
1993 * isolation settings.
1994 * @dev: A pointer to the struct ksz_device representing the device.
1995 * @port: The port number to adjust.
1996 *
1997 * This function dynamically adjusts the port membership configuration for a
1998 * specified port and other device ports, based on Spanning Tree Protocol (STP)
1999 * states and port isolation settings. Each port, including the CPU port, has a
2000 * membership register, represented as a bitfield, where each bit corresponds
2001 * to a port number. A set bit indicates permission to forward frames to that
2002 * port. This function iterates over all ports, updating the membership register
2003 * to reflect current forwarding permissions:
2004 *
2005 * 1. Forwards frames only to ports that are part of the same bridge group and
2006 * in the BR_STATE_FORWARDING state.
2007 * 2. Takes into account the isolation status of ports; ports in the
2008 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward
2009 * frames to each other, even if they are in the same bridge group.
2010 * 3. Ensures that the CPU port is included in the membership based on its
2011 * upstream port configuration, allowing for management and control traffic
2012 * to flow as required.
2013 */
ksz_update_port_member(struct ksz_device * dev,int port)2014 static void ksz_update_port_member(struct ksz_device *dev, int port)
2015 {
2016 struct ksz_port *p = &dev->ports[port];
2017 struct dsa_switch *ds = dev->ds;
2018 u8 port_member = 0, cpu_port;
2019 const struct dsa_port *dp;
2020 int i, j;
2021
2022 if (!dsa_is_user_port(ds, port))
2023 return;
2024
2025 dp = dsa_to_port(ds, port);
2026 cpu_port = BIT(dsa_upstream_port(ds, port));
2027
2028 for (i = 0; i < ds->num_ports; i++) {
2029 const struct dsa_port *other_dp = dsa_to_port(ds, i);
2030 struct ksz_port *other_p = &dev->ports[i];
2031 u8 val = 0;
2032
2033 if (!dsa_is_user_port(ds, i))
2034 continue;
2035 if (port == i)
2036 continue;
2037 if (!dsa_port_bridge_same(dp, other_dp))
2038 continue;
2039 if (other_p->stp_state != BR_STATE_FORWARDING)
2040 continue;
2041
2042 /* At this point we know that "port" and "other" port [i] are in
2043 * the same bridge group and that "other" port [i] is in
2044 * forwarding stp state. If "port" is also in forwarding stp
2045 * state, we can allow forwarding from port [port] to port [i].
2046 * Except if both ports are isolated.
2047 */
2048 if (p->stp_state == BR_STATE_FORWARDING &&
2049 !(p->isolated && other_p->isolated)) {
2050 val |= BIT(port);
2051 port_member |= BIT(i);
2052 }
2053
2054 /* Retain port [i]'s relationship to other ports than [port] */
2055 for (j = 0; j < ds->num_ports; j++) {
2056 const struct dsa_port *third_dp;
2057 struct ksz_port *third_p;
2058
2059 if (j == i)
2060 continue;
2061 if (j == port)
2062 continue;
2063 if (!dsa_is_user_port(ds, j))
2064 continue;
2065 third_p = &dev->ports[j];
2066 if (third_p->stp_state != BR_STATE_FORWARDING)
2067 continue;
2068
2069 third_dp = dsa_to_port(ds, j);
2070
2071 /* Now we updating relation of the "other" port [i] to
2072 * the "third" port [j]. We already know that "other"
2073 * port [i] is in forwarding stp state and that "third"
2074 * port [j] is in forwarding stp state too.
2075 * We need to check if "other" port [i] and "third" port
2076 * [j] are in the same bridge group and not isolated
2077 * before allowing forwarding from port [i] to port [j].
2078 */
2079 if (dsa_port_bridge_same(other_dp, third_dp) &&
2080 !(other_p->isolated && third_p->isolated))
2081 val |= BIT(j);
2082 }
2083
2084 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
2085 }
2086
2087 /* HSR ports are setup once so need to use the assigned membership
2088 * when the port is enabled.
2089 */
2090 if (!port_member && p->stp_state == BR_STATE_FORWARDING &&
2091 (dev->hsr_ports & BIT(port)))
2092 port_member = dev->hsr_ports;
2093 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
2094 }
2095
ksz_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)2096 int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
2097 {
2098 struct ksz_device *dev = bus->priv;
2099 struct dsa_switch *ds = dev->ds;
2100
2101 return ds->ops->phy_read(ds, addr, regnum);
2102 }
2103
ksz_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)2104 int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)
2105 {
2106 struct ksz_device *dev = bus->priv;
2107 struct dsa_switch *ds = dev->ds;
2108
2109 return ds->ops->phy_write(ds, addr, regnum, val);
2110 }
2111
2112 /**
2113 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus.
2114 * @bus: MDIO bus structure.
2115 * @addr: PHY address on the parent MDIO bus.
2116 * @regnum: Register number to read.
2117 *
2118 * This function provides a direct read operation on the parent MDIO bus for
2119 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus
2120 * to retrieve data from the PHY registers at the specified address and register
2121 * number.
2122 *
2123 * Return: Value of the PHY register, or a negative error code on failure.
2124 */
ksz_parent_mdio_read(struct mii_bus * bus,int addr,int regnum)2125 int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum)
2126 {
2127 struct ksz_device *dev = bus->priv;
2128
2129 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum);
2130 }
2131
2132 /**
2133 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus.
2134 * @bus: MDIO bus structure.
2135 * @addr: PHY address on the parent MDIO bus.
2136 * @regnum: Register number to write to.
2137 * @val: Value to write to the PHY register.
2138 *
2139 * This function provides a direct write operation on the parent MDIO bus for
2140 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus
2141 * to modify the PHY register values at the specified address.
2142 *
2143 * Return: 0 on success, or a negative error code on failure.
2144 */
ksz_parent_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)2145 int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)
2146 {
2147 struct ksz_device *dev = bus->priv;
2148
2149 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val);
2150 }
2151
2152 /**
2153 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port.
2154 * @dev: Pointer to device structure.
2155 * @addr: PHY address to map to a port.
2156 *
2157 * This function finds the corresponding switch port for a given PHY address by
2158 * iterating over all user ports on the device. It checks if a port's PHY
2159 * address in `phy_addr_map` matches the specified address and if the port
2160 * contains an internal PHY. If a match is found, the index of the port is
2161 * returned.
2162 *
2163 * Return: Port index on success, or -EINVAL if no matching port is found.
2164 */
ksz_phy_addr_to_port(struct ksz_device * dev,int addr)2165 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr)
2166 {
2167 struct dsa_switch *ds = dev->ds;
2168 struct dsa_port *dp;
2169
2170 dsa_switch_for_each_user_port(dp, ds) {
2171 if (dev->info->internal_phy[dp->index] &&
2172 dev->phy_addr_map[dp->index] == addr)
2173 return dp->index;
2174 }
2175
2176 return -EINVAL;
2177 }
2178
2179 /**
2180 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device.
2181 * @dev: Pointer to the KSZ device structure.
2182 *
2183 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the
2184 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in
2185 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain.
2186 *
2187 * Return: 0 on success, or a negative error code on failure.
2188 */
ksz_irq_phy_setup(struct ksz_device * dev)2189 static int ksz_irq_phy_setup(struct ksz_device *dev)
2190 {
2191 struct dsa_switch *ds = dev->ds;
2192 int phy, port;
2193 int irq;
2194 int ret;
2195
2196 for (phy = 0; phy < PHY_MAX_ADDR; phy++) {
2197 if (BIT(phy) & ds->phys_mii_mask) {
2198 port = ksz_phy_addr_to_port(dev, phy);
2199 if (port < 0) {
2200 ret = port;
2201 goto out;
2202 }
2203
2204 irq = irq_find_mapping(dev->ports[port].pirq.domain,
2205 PORT_SRC_PHY_INT);
2206 if (!irq) {
2207 ret = -EINVAL;
2208 goto out;
2209 }
2210 ds->user_mii_bus->irq[phy] = irq;
2211 }
2212 }
2213 return 0;
2214 out:
2215 while (phy--)
2216 if (BIT(phy) & ds->phys_mii_mask)
2217 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2218
2219 return ret;
2220 }
2221
2222 /**
2223 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device.
2224 * @dev: Pointer to the KSZ device structure.
2225 *
2226 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ
2227 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure.
2228 */
ksz_irq_phy_free(struct ksz_device * dev)2229 static void ksz_irq_phy_free(struct ksz_device *dev)
2230 {
2231 struct dsa_switch *ds = dev->ds;
2232 int phy;
2233
2234 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
2235 if (BIT(phy) & ds->phys_mii_mask)
2236 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2237 }
2238
2239 /**
2240 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT
2241 * @dev: pointer to the KSZ device structure
2242 * @bus: pointer to the MII bus structure
2243 * @mdio_np: pointer to the MDIO node in the device tree
2244 *
2245 * This function parses and validates PHY configurations for each user port
2246 * defined in the device tree for a KSZ switch device. It verifies that the
2247 * `phy-handle` properties are correctly set and that the internal PHYs match
2248 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if
2249 * all validations pass. Logs error messages for any mismatches or missing data.
2250 *
2251 * Return: 0 on success, or a negative error code on failure.
2252 */
ksz_parse_dt_phy_config(struct ksz_device * dev,struct mii_bus * bus,struct device_node * mdio_np)2253 int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus,
2254 struct device_node *mdio_np)
2255 {
2256 struct device_node *phy_node, *phy_parent_node;
2257 bool phys_are_valid = true;
2258 struct dsa_port *dp;
2259 u32 phy_addr;
2260 int ret;
2261
2262 dsa_switch_for_each_user_port(dp, dev->ds) {
2263 if (!dev->info->internal_phy[dp->index])
2264 continue;
2265
2266 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0);
2267 if (!phy_node) {
2268 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n",
2269 dp->index);
2270 phys_are_valid = false;
2271 continue;
2272 }
2273
2274 phy_parent_node = of_get_parent(phy_node);
2275 if (!phy_parent_node) {
2276 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n",
2277 dp->index);
2278 phys_are_valid = false;
2279 } else if (phy_parent_node != mdio_np) {
2280 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n",
2281 dp->index, mdio_np, phy_parent_node);
2282 phys_are_valid = false;
2283 } else {
2284 ret = of_property_read_u32(phy_node, "reg", &phy_addr);
2285 if (ret < 0) {
2286 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n",
2287 dp->index, ret);
2288 phys_are_valid = false;
2289 } else if (phy_addr != dev->phy_addr_map[dp->index]) {
2290 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n",
2291 dp->index, dev->phy_addr_map[dp->index],
2292 phy_addr);
2293 phys_are_valid = false;
2294 } else {
2295 bus->phy_mask |= BIT(phy_addr);
2296 }
2297 }
2298
2299 of_node_put(phy_node);
2300 of_node_put(phy_parent_node);
2301 }
2302
2303 if (!phys_are_valid)
2304 return -EINVAL;
2305
2306 return 0;
2307 }
2308
2309 /**
2310 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device.
2311 * @dev: Pointer to the KSZ device structure.
2312 *
2313 * This function sets up and registers an MDIO bus for the KSZ switch device,
2314 * allowing access to its internal PHYs. If the device supports side MDIO,
2315 * the function will configure the external MDIO controller specified by the
2316 * "mdio-parent-bus" device tree property to directly manage internal PHYs.
2317 * Otherwise, SPI or I2C access is set up for PHY access.
2318 *
2319 * Return: 0 on success, or a negative error code on failure.
2320 */
ksz_mdio_register(struct ksz_device * dev)2321 int ksz_mdio_register(struct ksz_device *dev)
2322 {
2323 struct device_node *parent_bus_node;
2324 struct mii_bus *parent_bus = NULL;
2325 struct dsa_switch *ds = dev->ds;
2326 struct device_node *mdio_np;
2327 struct mii_bus *bus;
2328 int ret, i;
2329
2330 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
2331 if (!mdio_np)
2332 return 0;
2333
2334 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0);
2335 if (parent_bus_node && !dev->info->phy_side_mdio_supported) {
2336 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n");
2337 ret = -EINVAL;
2338
2339 goto put_mdio_node;
2340 } else if (parent_bus_node) {
2341 parent_bus = of_mdio_find_bus(parent_bus_node);
2342 if (!parent_bus) {
2343 ret = -EPROBE_DEFER;
2344
2345 goto put_mdio_node;
2346 }
2347
2348 dev->parent_mdio_bus = parent_bus;
2349 }
2350
2351 bus = devm_mdiobus_alloc(ds->dev);
2352 if (!bus) {
2353 ret = -ENOMEM;
2354 goto put_mdio_node;
2355 }
2356
2357 for (i = 0; i < dev->info->port_cnt; i++)
2358 dev->phy_addr_map[i] = i;
2359
2360 bus->priv = dev;
2361 if (parent_bus) {
2362 bus->read = ksz_parent_mdio_read;
2363 bus->write = ksz_parent_mdio_write;
2364 bus->name = "KSZ side MDIO";
2365 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d",
2366 ds->index);
2367 } else {
2368 bus->read = ksz_sw_mdio_read;
2369 bus->write = ksz_sw_mdio_write;
2370 bus->name = "ksz user smi";
2371 if (ds->dst->index != 0) {
2372 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", ds->dst->index, ds->index);
2373 } else {
2374 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
2375 }
2376 }
2377
2378 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np);
2379 if (ret)
2380 goto put_mdio_node;
2381
2382 ds->phys_mii_mask = bus->phy_mask;
2383 bus->parent = ds->dev;
2384
2385 ds->user_mii_bus = bus;
2386
2387 if (dev->irq > 0) {
2388 ret = ksz_irq_phy_setup(dev);
2389 if (ret)
2390 goto put_mdio_node;
2391 }
2392
2393 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
2394 if (ret) {
2395 dev_err(ds->dev, "unable to register MDIO bus %s\n",
2396 bus->id);
2397 if (dev->irq > 0)
2398 ksz_irq_phy_free(dev);
2399 }
2400
2401 put_mdio_node:
2402 of_node_put(mdio_np);
2403 of_node_put(parent_bus_node);
2404
2405 return ret;
2406 }
2407
ksz_irq_mask(struct irq_data * d)2408 static void ksz_irq_mask(struct irq_data *d)
2409 {
2410 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2411
2412 kirq->masked |= BIT(d->hwirq);
2413 }
2414
ksz_irq_unmask(struct irq_data * d)2415 static void ksz_irq_unmask(struct irq_data *d)
2416 {
2417 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2418
2419 kirq->masked &= ~BIT(d->hwirq);
2420 }
2421
ksz_irq_bus_lock(struct irq_data * d)2422 void ksz_irq_bus_lock(struct irq_data *d)
2423 {
2424 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2425
2426 mutex_lock(&kirq->dev->lock_irq);
2427 }
2428
ksz_irq_bus_sync_unlock(struct irq_data * d)2429 void ksz_irq_bus_sync_unlock(struct irq_data *d)
2430 {
2431 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2432 struct ksz_device *dev = kirq->dev;
2433 int ret;
2434
2435 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked);
2436 if (ret)
2437 dev_err(dev->dev, "failed to change IRQ mask\n");
2438
2439 mutex_unlock(&dev->lock_irq);
2440 }
2441
2442 static const struct irq_chip ksz_irq_chip = {
2443 .name = "ksz-irq",
2444 .irq_mask = ksz_irq_mask,
2445 .irq_unmask = ksz_irq_unmask,
2446 .irq_bus_lock = ksz_irq_bus_lock,
2447 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
2448 };
2449
ksz_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)2450 static int ksz_irq_domain_map(struct irq_domain *d,
2451 unsigned int irq, irq_hw_number_t hwirq)
2452 {
2453 irq_set_chip_data(irq, d->host_data);
2454 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
2455 irq_set_noprobe(irq);
2456
2457 return 0;
2458 }
2459
2460 static const struct irq_domain_ops ksz_irq_domain_ops = {
2461 .map = ksz_irq_domain_map,
2462 .xlate = irq_domain_xlate_twocell,
2463 };
2464
ksz_irq_free(struct ksz_irq * kirq)2465 void ksz_irq_free(struct ksz_irq *kirq)
2466 {
2467 int irq, virq;
2468
2469 free_irq(kirq->irq_num, kirq);
2470
2471 for (irq = 0; irq < kirq->nirqs; irq++) {
2472 virq = irq_find_mapping(kirq->domain, irq);
2473 irq_dispose_mapping(virq);
2474 }
2475
2476 irq_domain_remove(kirq->domain);
2477 }
2478
ksz_irq_thread_fn(int irq,void * dev_id)2479 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2480 {
2481 struct ksz_irq *kirq = dev_id;
2482 unsigned int nhandled = 0;
2483 struct ksz_device *dev;
2484 unsigned int sub_irq;
2485 u8 data;
2486 int ret;
2487 u8 n;
2488
2489 dev = kirq->dev;
2490
2491 /* Read interrupt status register */
2492 ret = ksz_read8(dev, kirq->reg_status, &data);
2493 if (ret)
2494 goto out;
2495
2496 for (n = 0; n < kirq->nirqs; ++n) {
2497 if (data & BIT(n)) {
2498 sub_irq = irq_find_mapping(kirq->domain, n);
2499 handle_nested_irq(sub_irq);
2500 ++nhandled;
2501 }
2502 }
2503 out:
2504 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2505 }
2506
ksz_irq_common_setup(struct ksz_device * dev,struct ksz_irq * kirq,const struct irq_domain_ops * ops)2507 int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq,
2508 const struct irq_domain_ops *ops)
2509 {
2510 int ret, n;
2511
2512 kirq->dev = dev;
2513
2514 kirq->domain = irq_domain_create_simple(dev_fwnode(dev->dev),
2515 kirq->nirqs, 0, ops, kirq);
2516 if (!kirq->domain)
2517 return -ENOMEM;
2518
2519 for (n = 0; n < kirq->nirqs; n++)
2520 irq_create_mapping(kirq->domain, n);
2521
2522 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
2523 IRQF_ONESHOT, kirq->name, kirq);
2524 if (ret)
2525 goto out;
2526
2527 return 0;
2528
2529 out:
2530 ksz_irq_free(kirq);
2531
2532 return ret;
2533 }
2534
ksz_girq_setup(struct ksz_device * dev)2535 int ksz_girq_setup(struct ksz_device *dev)
2536 {
2537 struct ksz_irq *girq = &dev->girq;
2538
2539 girq->nirqs = dev->info->port_cnt;
2540 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2541 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2542 girq->masked = ~0;
2543 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
2544
2545 girq->irq_num = dev->irq;
2546
2547 return ksz_irq_common_setup(dev, girq, &ksz_irq_domain_ops);
2548 }
2549
ksz_pirq_setup(struct ksz_device * dev,u8 p)2550 int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2551 {
2552 struct ksz_irq *pirq = &dev->ports[p].pirq;
2553
2554 pirq->nirqs = dev->info->port_nirqs;
2555 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2556 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2557 pirq->masked = ~0;
2558 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
2559
2560 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2561 if (!pirq->irq_num)
2562 return -EINVAL;
2563
2564 return ksz_irq_common_setup(dev, pirq, &ksz_irq_domain_ops);
2565 }
2566
ksz_teardown(struct dsa_switch * ds)2567 void ksz_teardown(struct dsa_switch *ds)
2568 {
2569 struct ksz_device *dev = ds->priv;
2570 struct dsa_port *dp;
2571
2572 if (dev->info->ptp_capable)
2573 ksz_ptp_clock_unregister(ds);
2574
2575 if (dev->irq > 0) {
2576 dsa_switch_for_each_user_port(dp, dev->ds) {
2577 if (dev->info->ptp_capable)
2578 ksz_ptp_irq_free(ds, dp->index);
2579
2580 ksz_irq_free(&dev->ports[dp->index].pirq);
2581 }
2582
2583 ksz_irq_free(&dev->girq);
2584 }
2585 }
2586
port_r_cnt(struct ksz_device * dev,int port)2587 static void port_r_cnt(struct ksz_device *dev, int port)
2588 {
2589 struct ksz_port_mib *mib = &dev->ports[port].mib;
2590 u64 *dropped;
2591
2592 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2593 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2594 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2595 &mib->counters[mib->cnt_ptr]);
2596 ++mib->cnt_ptr;
2597 }
2598
2599 /* last one in storage */
2600 dropped = &mib->counters[dev->info->mib_cnt];
2601
2602 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2603 while (mib->cnt_ptr < dev->info->mib_cnt) {
2604 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2605 dropped, &mib->counters[mib->cnt_ptr]);
2606 ++mib->cnt_ptr;
2607 }
2608 mib->cnt_ptr = 0;
2609 }
2610
ksz_mib_read_work(struct work_struct * work)2611 static void ksz_mib_read_work(struct work_struct *work)
2612 {
2613 struct ksz_device *dev = container_of(work, struct ksz_device,
2614 mib_read.work);
2615 struct ksz_port_mib *mib;
2616 struct ksz_port *p;
2617 int i;
2618
2619 for (i = 0; i < dev->info->port_cnt; i++) {
2620 if (dsa_is_unused_port(dev->ds, i))
2621 continue;
2622
2623 p = &dev->ports[i];
2624 mib = &p->mib;
2625 mutex_lock(&mib->cnt_mutex);
2626
2627 /* Only read MIB counters when the port is told to do.
2628 * If not, read only dropped counters when link is not up.
2629 */
2630 if (!p->read) {
2631 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2632
2633 if (!netif_carrier_ok(dp->user))
2634 mib->cnt_ptr = dev->info->reg_mib_cnt;
2635 }
2636 port_r_cnt(dev, i);
2637 p->read = false;
2638
2639 if (dev->dev_ops->r_mib_stat64)
2640 dev->dev_ops->r_mib_stat64(dev, i);
2641
2642 mutex_unlock(&mib->cnt_mutex);
2643 }
2644
2645 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
2646 }
2647
ksz_init_mib_timer(struct ksz_device * dev)2648 void ksz_init_mib_timer(struct ksz_device *dev)
2649 {
2650 int i;
2651
2652 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2653
2654 for (i = 0; i < dev->info->port_cnt; i++) {
2655 struct ksz_port_mib *mib = &dev->ports[i].mib;
2656
2657 dev->dev_ops->port_init_cnt(dev, i);
2658
2659 mib->cnt_ptr = 0;
2660 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2661 }
2662 }
2663
ksz_phylink_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)2664 void ksz_phylink_mac_link_down(struct phylink_config *config,
2665 unsigned int mode,
2666 phy_interface_t interface)
2667 {
2668 struct dsa_port *dp = dsa_phylink_to_port(config);
2669 struct ksz_device *dev = dp->ds->priv;
2670
2671 /* Read all MIB counters when the link is going down. */
2672 dev->ports[dp->index].read = true;
2673 /* timer started */
2674 if (dev->mib_read_interval)
2675 schedule_delayed_work(&dev->mib_read, 0);
2676 }
2677
ksz_sset_count(struct dsa_switch * ds,int port,int sset)2678 int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
2679 {
2680 struct ksz_device *dev = ds->priv;
2681
2682 if (sset != ETH_SS_STATS)
2683 return 0;
2684
2685 return dev->info->mib_cnt;
2686 }
2687
ksz_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * buf)2688 void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
2689 uint64_t *buf)
2690 {
2691 const struct dsa_port *dp = dsa_to_port(ds, port);
2692 struct ksz_device *dev = ds->priv;
2693 struct ksz_port_mib *mib;
2694
2695 mib = &dev->ports[port].mib;
2696 mutex_lock(&mib->cnt_mutex);
2697
2698 /* Only read dropped counters if no link. */
2699 if (!netif_carrier_ok(dp->user))
2700 mib->cnt_ptr = dev->info->reg_mib_cnt;
2701 port_r_cnt(dev, port);
2702 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
2703 mutex_unlock(&mib->cnt_mutex);
2704 }
2705
ksz_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)2706 int ksz_port_bridge_join(struct dsa_switch *ds, int port,
2707 struct dsa_bridge bridge,
2708 bool *tx_fwd_offload,
2709 struct netlink_ext_ack *extack)
2710 {
2711 /* port_stp_state_set() will be called after to put the port in
2712 * appropriate state so there is no need to do anything.
2713 */
2714
2715 return 0;
2716 }
2717
ksz_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)2718 void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
2719 struct dsa_bridge bridge)
2720 {
2721 /* port_stp_state_set() will be called after to put the port in
2722 * forwarding state so there is no need to do anything.
2723 */
2724 }
2725
ksz_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)2726 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
2727 {
2728 struct ksz_device *dev = ds->priv;
2729 struct ksz_port *p;
2730 const u16 *regs;
2731 u8 data;
2732
2733 regs = dev->info->regs;
2734
2735 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
2736 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2737
2738 p = &dev->ports[port];
2739
2740 switch (state) {
2741 case BR_STATE_DISABLED:
2742 data |= PORT_LEARN_DISABLE;
2743 break;
2744 case BR_STATE_LISTENING:
2745 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2746 break;
2747 case BR_STATE_LEARNING:
2748 data |= PORT_RX_ENABLE;
2749 if (!p->learning)
2750 data |= PORT_LEARN_DISABLE;
2751 break;
2752 case BR_STATE_FORWARDING:
2753 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2754 if (!p->learning)
2755 data |= PORT_LEARN_DISABLE;
2756 break;
2757 case BR_STATE_BLOCKING:
2758 data |= PORT_LEARN_DISABLE;
2759 break;
2760 default:
2761 dev_err(ds->dev, "invalid STP state: %d\n", state);
2762 return;
2763 }
2764
2765 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
2766
2767 p->stp_state = state;
2768
2769 ksz_update_port_member(dev, port);
2770 }
2771
ksz_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2772 int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2773 struct switchdev_brport_flags flags,
2774 struct netlink_ext_ack *extack)
2775 {
2776 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED))
2777 return -EINVAL;
2778
2779 return 0;
2780 }
2781
ksz_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2782 int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2783 struct switchdev_brport_flags flags,
2784 struct netlink_ext_ack *extack)
2785 {
2786 struct ksz_device *dev = ds->priv;
2787 struct ksz_port *p = &dev->ports[port];
2788
2789 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) {
2790 if (flags.mask & BR_LEARNING)
2791 p->learning = !!(flags.val & BR_LEARNING);
2792
2793 if (flags.mask & BR_ISOLATED)
2794 p->isolated = !!(flags.val & BR_ISOLATED);
2795
2796 /* Make the change take effect immediately */
2797 ksz_port_stp_state_set(ds, port, p->stp_state);
2798 }
2799
2800 return 0;
2801 }
2802
ksz_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_keee * e)2803 int ksz_set_mac_eee(struct dsa_switch *ds, int port,
2804 struct ethtool_keee *e)
2805 {
2806 struct ksz_device *dev = ds->priv;
2807
2808 if (!e->tx_lpi_enabled) {
2809 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
2810 return -EINVAL;
2811 }
2812
2813 if (e->tx_lpi_timer) {
2814 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
2815 return -EINVAL;
2816 }
2817
2818 return 0;
2819 }
2820
ksz_set_xmii(struct ksz_device * dev,int port,phy_interface_t interface)2821 void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
2822 {
2823 const u8 *bitval = dev->info->xmii_ctrl1;
2824 struct ksz_port *p = &dev->ports[port];
2825 const u16 *regs = dev->info->regs;
2826 u8 data8;
2827
2828 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2829
2830 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
2831 P_RGMII_ID_EG_ENABLE);
2832
2833 switch (interface) {
2834 case PHY_INTERFACE_MODE_MII:
2835 data8 |= bitval[P_MII_SEL];
2836 break;
2837 case PHY_INTERFACE_MODE_RMII:
2838 data8 |= bitval[P_RMII_SEL];
2839 break;
2840 case PHY_INTERFACE_MODE_GMII:
2841 data8 |= bitval[P_GMII_SEL];
2842 break;
2843 case PHY_INTERFACE_MODE_RGMII:
2844 case PHY_INTERFACE_MODE_RGMII_ID:
2845 case PHY_INTERFACE_MODE_RGMII_TXID:
2846 case PHY_INTERFACE_MODE_RGMII_RXID:
2847 data8 |= bitval[P_RGMII_SEL];
2848 /* On KSZ9893, disable RGMII in-band status support */
2849 if (dev->chip_id == KSZ9893_CHIP_ID ||
2850 dev->chip_id == KSZ8563_CHIP_ID ||
2851 dev->chip_id == KSZ9563_CHIP_ID ||
2852 is_lan937x(dev))
2853 data8 &= ~P_MII_MAC_MODE;
2854 break;
2855 default:
2856 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
2857 phy_modes(interface), port);
2858 return;
2859 }
2860
2861 if (p->rgmii_tx_val)
2862 data8 |= P_RGMII_ID_EG_ENABLE;
2863
2864 if (p->rgmii_rx_val)
2865 data8 |= P_RGMII_ID_IG_ENABLE;
2866
2867 /* Write the updated value */
2868 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2869 }
2870
ksz_phylink_need_config(struct phylink_config * config,unsigned int mode)2871 bool ksz_phylink_need_config(struct phylink_config *config,
2872 unsigned int mode)
2873 {
2874 struct dsa_port *dp = dsa_phylink_to_port(config);
2875 struct ksz_device *dev = dp->ds->priv;
2876 int port = dp->index;
2877
2878 /* Internal PHYs */
2879 if (dev->info->internal_phy[port])
2880 return false;
2881
2882 /* No need to configure XMII control register when using SGMII. */
2883 if (ksz_is_sgmii_port(dev, port))
2884 return false;
2885
2886 if (phylink_autoneg_inband(mode)) {
2887 dev_err(dev->dev, "In-band AN not supported!\n");
2888 return false;
2889 }
2890
2891 return true;
2892 }
2893
ksz_phylink_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)2894 void ksz_phylink_mac_config(struct phylink_config *config,
2895 unsigned int mode,
2896 const struct phylink_link_state *state)
2897 {
2898 struct dsa_port *dp = dsa_phylink_to_port(config);
2899 struct ksz_device *dev = dp->ds->priv;
2900 int port = dp->index;
2901
2902 if (ksz_phylink_need_config(config, mode))
2903 ksz_set_xmii(dev, port, state->interface);
2904 }
2905
ksz_switch_detect(struct ksz_device * dev)2906 static int ksz_switch_detect(struct ksz_device *dev)
2907 {
2908 u8 id1, id2, id4;
2909 u16 id16;
2910 u32 id32;
2911 int ret;
2912
2913 /* read chip id */
2914 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
2915 if (ret)
2916 return ret;
2917
2918 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
2919 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
2920
2921 switch (id1) {
2922 case KSZ84_FAMILY_ID:
2923 dev->chip_id = KSZ8463_CHIP_ID;
2924 break;
2925 case KSZ87_FAMILY_ID:
2926 if (id2 == KSZ87_CHIP_ID_95) {
2927 u8 val;
2928
2929 dev->chip_id = KSZ8795_CHIP_ID;
2930
2931 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
2932 if (val & KSZ8_PORT_FIBER_MODE)
2933 dev->chip_id = KSZ8765_CHIP_ID;
2934 } else if (id2 == KSZ87_CHIP_ID_94) {
2935 dev->chip_id = KSZ8794_CHIP_ID;
2936 } else {
2937 return -ENODEV;
2938 }
2939 break;
2940 case KSZ88_FAMILY_ID:
2941 if (id2 == KSZ88_CHIP_ID_63)
2942 dev->chip_id = KSZ88X3_CHIP_ID;
2943 else
2944 return -ENODEV;
2945 break;
2946 case KSZ8895_FAMILY_ID:
2947 if (id2 == KSZ8895_CHIP_ID_95 ||
2948 id2 == KSZ8895_CHIP_ID_95R)
2949 dev->chip_id = KSZ8895_CHIP_ID;
2950 else
2951 return -ENODEV;
2952 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4);
2953 if (ret)
2954 return ret;
2955 if (id4 & SW_KSZ8864)
2956 dev->chip_id = KSZ8864_CHIP_ID;
2957 break;
2958 default:
2959 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
2960 if (ret)
2961 return ret;
2962
2963 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
2964 id32 &= ~0xFF;
2965
2966 switch (id32) {
2967 case KSZ9477_CHIP_ID:
2968 case KSZ9896_CHIP_ID:
2969 case KSZ9897_CHIP_ID:
2970 case KSZ9567_CHIP_ID:
2971 case KSZ8567_CHIP_ID:
2972 case LAN9370_CHIP_ID:
2973 case LAN9371_CHIP_ID:
2974 case LAN9372_CHIP_ID:
2975 case LAN9373_CHIP_ID:
2976 case LAN9374_CHIP_ID:
2977
2978 /* LAN9646 does not have its own chip id. */
2979 if (dev->chip_id != LAN9646_CHIP_ID)
2980 dev->chip_id = id32;
2981 break;
2982 case KSZ9893_CHIP_ID:
2983 ret = ksz_read8(dev, REG_CHIP_ID4,
2984 &id4);
2985 if (ret)
2986 return ret;
2987
2988 if (id4 == SKU_ID_KSZ8563)
2989 dev->chip_id = KSZ8563_CHIP_ID;
2990 else if (id4 == SKU_ID_KSZ9563)
2991 dev->chip_id = KSZ9563_CHIP_ID;
2992 else
2993 dev->chip_id = KSZ9893_CHIP_ID;
2994
2995 break;
2996 default:
2997 dev_err(dev->dev,
2998 "unsupported switch detected (0x%x)\n", id32);
2999 return -ENODEV;
3000 }
3001 }
3002 return 0;
3003 }
3004
3005 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
3006 * is converted to Hex-decimal using the successive multiplication method. On
3007 * every step, integer part is taken and decimal part is carry forwarded.
3008 */
cinc_cal(s32 idle_slope,s32 send_slope,u32 * bw)3009 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
3010 {
3011 u32 cinc = 0;
3012 u32 txrate;
3013 u32 rate;
3014 u8 temp;
3015 u8 i;
3016
3017 txrate = idle_slope - send_slope;
3018
3019 if (!txrate)
3020 return -EINVAL;
3021
3022 rate = idle_slope;
3023
3024 /* 24 bit register */
3025 for (i = 0; i < 6; i++) {
3026 rate = rate * 16;
3027
3028 temp = rate / txrate;
3029
3030 rate %= txrate;
3031
3032 cinc = ((cinc << 4) | temp);
3033 }
3034
3035 *bw = cinc;
3036
3037 return 0;
3038 }
3039
ksz_setup_tc_mode(struct ksz_device * dev,int port,u8 scheduler,u8 shaper)3040 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
3041 u8 shaper)
3042 {
3043 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
3044 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
3045 FIELD_PREP(MTI_SHAPING_M, shaper));
3046 }
3047
ksz_setup_tc_cbs(struct dsa_switch * ds,int port,struct tc_cbs_qopt_offload * qopt)3048 int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
3049 struct tc_cbs_qopt_offload *qopt)
3050 {
3051 struct ksz_device *dev = ds->priv;
3052 int ret;
3053 u32 bw;
3054
3055 if (!dev->info->tc_cbs_supported)
3056 return -EOPNOTSUPP;
3057
3058 if (qopt->queue > dev->info->num_tx_queues)
3059 return -EINVAL;
3060
3061 /* Queue Selection */
3062 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue);
3063 if (ret)
3064 return ret;
3065
3066 if (!qopt->enable)
3067 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3068 MTI_SHAPING_OFF);
3069
3070 /* High Credit */
3071 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
3072 qopt->hicredit);
3073 if (ret)
3074 return ret;
3075
3076 /* Low Credit */
3077 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
3078 qopt->locredit);
3079 if (ret)
3080 return ret;
3081
3082 /* Credit Increment Register */
3083 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw);
3084 if (ret)
3085 return ret;
3086
3087 if (dev->dev_ops->tc_cbs_set_cinc) {
3088 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
3089 if (ret)
3090 return ret;
3091 }
3092
3093 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3094 MTI_SHAPING_SRP);
3095 }
3096
ksz_disable_egress_rate_limit(struct ksz_device * dev,int port)3097 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
3098 {
3099 int queue, ret;
3100
3101 /* Configuration will not take effect until the last Port Queue X
3102 * Egress Limit Control Register is written.
3103 */
3104 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3105 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
3106 KSZ9477_OUT_RATE_NO_LIMIT);
3107 if (ret)
3108 return ret;
3109 }
3110
3111 return 0;
3112 }
3113
ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params * p,int band)3114 int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
3115 int band)
3116 {
3117 /* Compared to queues, bands prioritize packets differently. In strict
3118 * priority mode, the lowest priority is assigned to Queue 0 while the
3119 * highest priority is given to Band 0.
3120 */
3121 return p->bands - 1 - band;
3122 }
3123
ksz_queue_set_strict(struct ksz_device * dev,int port,int queue)3124 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
3125 {
3126 int ret;
3127
3128 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3129 if (ret)
3130 return ret;
3131
3132 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3133 MTI_SHAPING_OFF);
3134 }
3135
ksz_queue_set_wrr(struct ksz_device * dev,int port,int queue,int weight)3136 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
3137 int weight)
3138 {
3139 int ret;
3140
3141 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3142 if (ret)
3143 return ret;
3144
3145 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3146 MTI_SHAPING_OFF);
3147 if (ret)
3148 return ret;
3149
3150 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight);
3151 }
3152
ksz_tc_ets_add(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)3153 static int ksz_tc_ets_add(struct ksz_device *dev, int port,
3154 struct tc_ets_qopt_offload_replace_params *p)
3155 {
3156 int ret, band, tc_prio;
3157 u32 queue_map = 0;
3158
3159 /* In order to ensure proper prioritization, it is necessary to set the
3160 * rate limit for the related queue to zero. Otherwise strict priority
3161 * or WRR mode will not work. This is a hardware limitation.
3162 */
3163 ret = ksz_disable_egress_rate_limit(dev, port);
3164 if (ret)
3165 return ret;
3166
3167 /* Configure queue scheduling mode for all bands. Currently only strict
3168 * prio mode is supported.
3169 */
3170 for (band = 0; band < p->bands; band++) {
3171 int queue = ksz_ets_band_to_queue(p, band);
3172
3173 ret = ksz_queue_set_strict(dev, port, queue);
3174 if (ret)
3175 return ret;
3176 }
3177
3178 /* Configure the mapping between traffic classes and queues. Note:
3179 * priomap variable support 16 traffic classes, but the chip can handle
3180 * only 8 classes.
3181 */
3182 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
3183 int queue;
3184
3185 if (tc_prio >= dev->info->num_ipms)
3186 break;
3187
3188 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]);
3189 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3190 }
3191
3192 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3193 }
3194
ksz_tc_ets_del(struct ksz_device * dev,int port)3195 static int ksz_tc_ets_del(struct ksz_device *dev, int port)
3196 {
3197 int ret, queue;
3198
3199 /* To restore the default chip configuration, set all queues to use the
3200 * WRR scheduler with a weight of 1.
3201 */
3202 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3203 ret = ksz_queue_set_wrr(dev, port, queue,
3204 KSZ9477_DEFAULT_WRR_WEIGHT);
3205
3206 if (ret)
3207 return ret;
3208 }
3209
3210 /* Revert the queue mapping for TC-priority to its default setting on
3211 * the chip.
3212 */
3213 return ksz9477_set_default_prio_queue_mapping(dev, port);
3214 }
3215
ksz_tc_ets_validate(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)3216 int ksz_tc_ets_validate(struct ksz_device *dev, int port,
3217 struct tc_ets_qopt_offload_replace_params *p)
3218 {
3219 int band;
3220
3221 /* Since it is not feasible to share one port among multiple qdisc,
3222 * the user must configure all available queues appropriately.
3223 */
3224 if (p->bands != dev->info->num_tx_queues) {
3225 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
3226 dev->info->num_tx_queues);
3227 return -EOPNOTSUPP;
3228 }
3229
3230 for (band = 0; band < p->bands; ++band) {
3231 /* The KSZ switches utilize a weighted round robin configuration
3232 * where a certain number of packets can be transmitted from a
3233 * queue before the next queue is serviced. For more information
3234 * on this, refer to section 5.2.8.4 of the KSZ8565R
3235 * documentation on the Port Transmit Queue Control 1 Register.
3236 * However, the current ETS Qdisc implementation (as of February
3237 * 2023) assigns a weight to each queue based on the number of
3238 * bytes or extrapolated bandwidth in percentages. Since this
3239 * differs from the KSZ switches' method and we don't want to
3240 * fake support by converting bytes to packets, it is better to
3241 * return an error instead.
3242 */
3243 if (p->quanta[band]) {
3244 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
3245 return -EOPNOTSUPP;
3246 }
3247 }
3248
3249 return 0;
3250 }
3251
ksz_tc_setup_qdisc_ets(struct dsa_switch * ds,int port,struct tc_ets_qopt_offload * qopt)3252 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
3253 struct tc_ets_qopt_offload *qopt)
3254 {
3255 struct ksz_device *dev = ds->priv;
3256 int ret;
3257
3258 if (qopt->parent != TC_H_ROOT) {
3259 dev_err(dev->dev, "Parent should be \"root\"\n");
3260 return -EOPNOTSUPP;
3261 }
3262
3263 switch (qopt->command) {
3264 case TC_ETS_REPLACE:
3265 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params);
3266 if (ret)
3267 return ret;
3268
3269 return ksz_tc_ets_add(dev, port, &qopt->replace_params);
3270 case TC_ETS_DESTROY:
3271 return ksz_tc_ets_del(dev, port);
3272 case TC_ETS_STATS:
3273 case TC_ETS_GRAFT:
3274 return -EOPNOTSUPP;
3275 }
3276
3277 return -EOPNOTSUPP;
3278 }
3279
ksz_setup_tc(struct dsa_switch * ds,int port,enum tc_setup_type type,void * type_data)3280 int ksz_setup_tc(struct dsa_switch *ds, int port,
3281 enum tc_setup_type type, void *type_data)
3282 {
3283 switch (type) {
3284 case TC_SETUP_QDISC_CBS:
3285 return ksz_setup_tc_cbs(ds, port, type_data);
3286 case TC_SETUP_QDISC_ETS:
3287 return ksz_tc_setup_qdisc_ets(ds, port, type_data);
3288 default:
3289 return -EOPNOTSUPP;
3290 }
3291 }
3292
3293 /**
3294 * ksz_handle_wake_reason - Handle wake reason on a specified port.
3295 * @dev: The device structure.
3296 * @port: The port number.
3297 *
3298 * This function reads the PME (Power Management Event) status register of a
3299 * specified port to determine the wake reason. If there is no wake event, it
3300 * returns early. Otherwise, it logs the wake reason which could be due to a
3301 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register
3302 * is then cleared to acknowledge the handling of the wake event.
3303 *
3304 * Return: 0 on success, or an error code on failure.
3305 */
ksz_handle_wake_reason(struct ksz_device * dev,int port)3306 int ksz_handle_wake_reason(struct ksz_device *dev, int port)
3307 {
3308 const struct ksz_dev_ops *ops = dev->dev_ops;
3309 const u16 *regs = dev->info->regs;
3310 u8 pme_status;
3311 int ret;
3312
3313 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS],
3314 &pme_status);
3315 if (ret)
3316 return ret;
3317
3318 if (!pme_status)
3319 return 0;
3320
3321 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port,
3322 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "",
3323 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "",
3324 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : "");
3325
3326 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS],
3327 pme_status);
3328 }
3329
3330 /**
3331 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port
3332 * can be used as a global address.
3333 * @ds: Pointer to the DSA switch structure.
3334 * @port: The port number on which the MAC address is to be checked.
3335 *
3336 * This function examines the MAC address set on the specified port and
3337 * determines if it can be used as a global address for the switch.
3338 *
3339 * Return: true if the port's MAC address can be used as a global address, false
3340 * otherwise.
3341 */
ksz_is_port_mac_global_usable(struct dsa_switch * ds,int port)3342 static bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port)
3343 {
3344 struct net_device *user = dsa_to_port(ds, port)->user;
3345 const unsigned char *addr = user->dev_addr;
3346 struct ksz_switch_macaddr *switch_macaddr;
3347 struct ksz_device *dev = ds->priv;
3348
3349 ASSERT_RTNL();
3350
3351 switch_macaddr = dev->switch_macaddr;
3352 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr))
3353 return false;
3354
3355 return true;
3356 }
3357
3358 /**
3359 * ksz_get_wol - Get Wake-on-LAN settings for a specified port.
3360 * @ds: The dsa_switch structure.
3361 * @port: The port number.
3362 * @wol: Pointer to ethtool Wake-on-LAN settings structure.
3363 *
3364 * This function checks the device PME wakeup_source flag and chip_id.
3365 * If enabled and supported, it sets the supported and active WoL
3366 * flags.
3367 */
ksz_get_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)3368 void ksz_get_wol(struct dsa_switch *ds, int port,
3369 struct ethtool_wolinfo *wol)
3370 {
3371 struct ksz_device *dev = ds->priv;
3372 const u16 *regs = dev->info->regs;
3373 u8 pme_ctrl;
3374 int ret;
3375
3376 if (!dev->wakeup_source)
3377 return;
3378
3379 wol->supported = WAKE_PHY;
3380
3381 /* Check if the current MAC address on this port can be set
3382 * as global for WAKE_MAGIC support. The result may vary
3383 * dynamically based on other ports configurations.
3384 */
3385 if (ksz_is_port_mac_global_usable(dev->ds, port))
3386 wol->supported |= WAKE_MAGIC;
3387
3388 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
3389 &pme_ctrl);
3390 if (ret)
3391 return;
3392
3393 if (pme_ctrl & PME_WOL_MAGICPKT)
3394 wol->wolopts |= WAKE_MAGIC;
3395 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY))
3396 wol->wolopts |= WAKE_PHY;
3397 }
3398
3399 /**
3400 * ksz_set_wol - Set Wake-on-LAN settings for a specified port.
3401 * @ds: The dsa_switch structure.
3402 * @port: The port number.
3403 * @wol: Pointer to ethtool Wake-on-LAN settings structure.
3404 *
3405 * This function configures Wake-on-LAN (WoL) settings for a specified
3406 * port. It validates the provided WoL options, checks if PME is
3407 * enabled and supported, clears any previous wake reasons, and sets
3408 * the Magic Packet flag in the port's PME control register if
3409 * specified.
3410 *
3411 * Return: 0 on success, or other error codes on failure.
3412 */
ksz_set_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)3413 int ksz_set_wol(struct dsa_switch *ds, int port,
3414 struct ethtool_wolinfo *wol)
3415 {
3416 u8 pme_ctrl = 0, pme_ctrl_old = 0;
3417 struct ksz_device *dev = ds->priv;
3418 const u16 *regs = dev->info->regs;
3419 bool magic_switched_off;
3420 bool magic_switched_on;
3421 int ret;
3422
3423 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
3424 return -EINVAL;
3425
3426 if (!dev->wakeup_source)
3427 return -EOPNOTSUPP;
3428
3429 ret = ksz_handle_wake_reason(dev, port);
3430 if (ret)
3431 return ret;
3432
3433 if (wol->wolopts & WAKE_MAGIC)
3434 pme_ctrl |= PME_WOL_MAGICPKT;
3435 if (wol->wolopts & WAKE_PHY)
3436 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY;
3437
3438 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
3439 &pme_ctrl_old);
3440 if (ret)
3441 return ret;
3442
3443 if (pme_ctrl_old == pme_ctrl)
3444 return 0;
3445
3446 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) &&
3447 !(pme_ctrl & PME_WOL_MAGICPKT);
3448 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) &&
3449 (pme_ctrl & PME_WOL_MAGICPKT);
3450
3451 /* To keep reference count of MAC address, we should do this
3452 * operation only on change of WOL settings.
3453 */
3454 if (magic_switched_on) {
3455 ret = ksz_switch_macaddr_get(dev->ds, port, NULL);
3456 if (ret)
3457 return ret;
3458 } else if (magic_switched_off) {
3459 ksz_switch_macaddr_put(dev->ds);
3460 }
3461
3462 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL],
3463 pme_ctrl);
3464 if (ret) {
3465 if (magic_switched_on)
3466 ksz_switch_macaddr_put(dev->ds);
3467 return ret;
3468 }
3469
3470 return 0;
3471 }
3472
3473 /**
3474 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while
3475 * considering Wake-on-LAN (WoL) settings.
3476 * @dev: The switch device structure.
3477 *
3478 * This function prepares the switch device for a safe shutdown while taking
3479 * into account the Wake-on-LAN (WoL) settings on the user ports.
3480 */
ksz_wol_pre_shutdown(struct ksz_device * dev)3481 static void ksz_wol_pre_shutdown(struct ksz_device *dev)
3482 {
3483 const struct ksz_dev_ops *ops = dev->dev_ops;
3484 const u16 *regs = dev->info->regs;
3485 struct dsa_switch *ds = dev->ds;
3486 u8 pme_pin_en = PME_ENABLE;
3487 bool wol_enabled = false;
3488 struct dsa_port *dp;
3489 int ret;
3490
3491 if (!ds->ops->set_wol)
3492 return;
3493
3494 if (!dev->wakeup_source)
3495 return;
3496
3497 dsa_switch_for_each_user_port(dp, dev->ds) {
3498 u8 pme_ctrl = 0;
3499
3500 ret = ops->pme_pread8(dev, dp->index,
3501 regs[REG_PORT_PME_CTRL], &pme_ctrl);
3502 if (!ret && pme_ctrl)
3503 wol_enabled = true;
3504
3505 /* make sure there are no pending wake events which would
3506 * prevent the device from going to sleep/shutdown.
3507 */
3508 ksz_handle_wake_reason(dev, dp->index);
3509 }
3510
3511 /* Now we are save to enable PME pin. */
3512 if (wol_enabled) {
3513 if (dev->pme_active_high)
3514 pme_pin_en |= PME_POLARITY;
3515 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en);
3516 if (ksz_is_ksz87xx(dev))
3517 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK);
3518 }
3519 }
3520
ksz_port_set_mac_address(struct dsa_switch * ds,int port,const unsigned char * addr)3521 int ksz_port_set_mac_address(struct dsa_switch *ds, int port,
3522 const unsigned char *addr)
3523 {
3524 struct dsa_port *dp = dsa_to_port(ds, port);
3525 struct ethtool_wolinfo wol;
3526
3527 if (dp->hsr_dev) {
3528 dev_err(ds->dev,
3529 "Cannot change MAC address on port %d with active HSR offload\n",
3530 port);
3531 return -EBUSY;
3532 }
3533
3534 /* Need to initialize variable as the code to fill in settings may
3535 * not be executed.
3536 */
3537 wol.wolopts = 0;
3538
3539 if (ds->ops->get_wol)
3540 ds->ops->get_wol(ds, dp->index, &wol);
3541 if (wol.wolopts & WAKE_MAGIC) {
3542 dev_err(ds->dev,
3543 "Cannot change MAC address on port %d with active Wake on Magic Packet\n",
3544 port);
3545 return -EBUSY;
3546 }
3547
3548 return 0;
3549 }
3550
3551 /**
3552 * ksz_switch_macaddr_get - Program the switch's MAC address register.
3553 * @ds: DSA switch instance.
3554 * @port: Port number.
3555 * @extack: Netlink extended acknowledgment.
3556 *
3557 * This function programs the switch's MAC address register with the MAC address
3558 * of the requesting user port. This single address is used by the switch for
3559 * multiple features like HSR self-address filtering and WoL. Other user ports
3560 * can share ownership of this address as long as their MAC address is the same.
3561 * The MAC addresses of user ports must not change while they have ownership of
3562 * the switch MAC address.
3563 *
3564 * Return: 0 on success, or other error codes on failure.
3565 */
ksz_switch_macaddr_get(struct dsa_switch * ds,int port,struct netlink_ext_ack * extack)3566 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
3567 struct netlink_ext_ack *extack)
3568 {
3569 struct net_device *user = dsa_to_port(ds, port)->user;
3570 const unsigned char *addr = user->dev_addr;
3571 struct ksz_switch_macaddr *switch_macaddr;
3572 struct ksz_device *dev = ds->priv;
3573 const u16 *regs = dev->info->regs;
3574 int i, ret;
3575
3576 /* Make sure concurrent MAC address changes are blocked */
3577 ASSERT_RTNL();
3578
3579 switch_macaddr = dev->switch_macaddr;
3580 if (switch_macaddr) {
3581 if (!ether_addr_equal(switch_macaddr->addr, addr)) {
3582 NL_SET_ERR_MSG_FMT_MOD(extack,
3583 "Switch already configured for MAC address %pM",
3584 switch_macaddr->addr);
3585 return -EBUSY;
3586 }
3587
3588 refcount_inc(&switch_macaddr->refcount);
3589 return 0;
3590 }
3591
3592 switch_macaddr = kzalloc_obj(*switch_macaddr);
3593 if (!switch_macaddr)
3594 return -ENOMEM;
3595
3596 ether_addr_copy(switch_macaddr->addr, addr);
3597 refcount_set(&switch_macaddr->refcount, 1);
3598 dev->switch_macaddr = switch_macaddr;
3599
3600 /* Program the switch MAC address to hardware */
3601 for (i = 0; i < ETH_ALEN; i++) {
3602 if (ksz_is_ksz8463(dev)) {
3603 u16 addr16 = ((u16)addr[i] << 8) | addr[i + 1];
3604
3605 ret = ksz_write16(dev, regs[REG_SW_MAC_ADDR] + i,
3606 addr16);
3607 i++;
3608 } else {
3609 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i,
3610 addr[i]);
3611 }
3612 if (ret)
3613 goto macaddr_drop;
3614 }
3615
3616 return 0;
3617
3618 macaddr_drop:
3619 dev->switch_macaddr = NULL;
3620 refcount_set(&switch_macaddr->refcount, 0);
3621 kfree(switch_macaddr);
3622
3623 return ret;
3624 }
3625
ksz_switch_macaddr_put(struct dsa_switch * ds)3626 void ksz_switch_macaddr_put(struct dsa_switch *ds)
3627 {
3628 struct ksz_switch_macaddr *switch_macaddr;
3629 struct ksz_device *dev = ds->priv;
3630 const u16 *regs = dev->info->regs;
3631 int i;
3632
3633 /* Make sure concurrent MAC address changes are blocked */
3634 ASSERT_RTNL();
3635
3636 switch_macaddr = dev->switch_macaddr;
3637 if (!refcount_dec_and_test(&switch_macaddr->refcount))
3638 return;
3639
3640 for (i = 0; i < ETH_ALEN; i++)
3641 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0);
3642
3643 dev->switch_macaddr = NULL;
3644 kfree(switch_macaddr);
3645 }
3646
ksz_suspend(struct dsa_switch * ds)3647 int ksz_suspend(struct dsa_switch *ds)
3648 {
3649 struct ksz_device *dev = ds->priv;
3650
3651 cancel_delayed_work_sync(&dev->mib_read);
3652 return 0;
3653 }
3654
ksz_resume(struct dsa_switch * ds)3655 int ksz_resume(struct dsa_switch *ds)
3656 {
3657 struct ksz_device *dev = ds->priv;
3658
3659 if (dev->mib_read_interval)
3660 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
3661 return 0;
3662 }
3663
ksz_switch_alloc(struct device * base,const struct ksz_chip_data * chip,void * priv)3664 struct ksz_device *ksz_switch_alloc(struct device *base,
3665 const struct ksz_chip_data *chip,
3666 void *priv)
3667 {
3668 struct dsa_switch *ds;
3669 struct ksz_device *swdev;
3670
3671 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
3672 if (!ds)
3673 return NULL;
3674
3675 ds->dev = base;
3676 ds->num_ports = DSA_MAX_PORTS;
3677 ds->ops = chip->switch_ops;
3678
3679 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
3680 if (!swdev)
3681 return NULL;
3682
3683 ds->priv = swdev;
3684 swdev->dev = base;
3685
3686 swdev->ds = ds;
3687 swdev->priv = priv;
3688
3689 return swdev;
3690 }
3691 EXPORT_SYMBOL(ksz_switch_alloc);
3692
3693 /**
3694 * ksz_switch_shutdown - Shutdown routine for the switch device.
3695 * @dev: The switch device structure.
3696 *
3697 * This function is responsible for initiating a shutdown sequence for the
3698 * switch device. Subsequently, it calls the DSA framework's shutdown function
3699 * to ensure a proper shutdown of the DSA switch.
3700 */
ksz_switch_shutdown(struct ksz_device * dev)3701 void ksz_switch_shutdown(struct ksz_device *dev)
3702 {
3703 ksz_wol_pre_shutdown(dev);
3704 dsa_switch_shutdown(dev->ds);
3705 }
3706 EXPORT_SYMBOL(ksz_switch_shutdown);
3707
ksz_parse_rgmii_delay(struct ksz_device * dev,int port_num,struct device_node * port_dn)3708 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
3709 struct device_node *port_dn)
3710 {
3711 phy_interface_t phy_mode = dev->ports[port_num].interface;
3712 int rx_delay = -1, tx_delay = -1;
3713
3714 if (!phy_interface_mode_is_rgmii(phy_mode))
3715 return;
3716
3717 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
3718 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
3719
3720 if (rx_delay == -1 && tx_delay == -1) {
3721 dev_warn(dev->dev,
3722 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
3723 "please update device tree to specify \"rx-internal-delay-ps\" and "
3724 "\"tx-internal-delay-ps\"",
3725 port_num);
3726
3727 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
3728 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3729 rx_delay = 2000;
3730
3731 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
3732 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3733 tx_delay = 2000;
3734 }
3735
3736 if (rx_delay < 0)
3737 rx_delay = 0;
3738 if (tx_delay < 0)
3739 tx_delay = 0;
3740
3741 dev->ports[port_num].rgmii_rx_val = rx_delay;
3742 dev->ports[port_num].rgmii_tx_val = tx_delay;
3743 }
3744
3745 /**
3746 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding
3747 * register value.
3748 * @array: The array of drive strength values to search.
3749 * @array_size: The size of the array.
3750 * @microamp: The drive strength value in microamp to be converted.
3751 *
3752 * This function searches the array of drive strength values for the given
3753 * microamp value and returns the corresponding register value for that drive.
3754 *
3755 * Returns: If found, the corresponding register value for that drive strength
3756 * is returned. Otherwise, -EINVAL is returned indicating an invalid value.
3757 */
ksz_drive_strength_to_reg(const struct ksz_drive_strength * array,size_t array_size,int microamp)3758 int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array,
3759 size_t array_size, int microamp)
3760 {
3761 int i;
3762
3763 for (i = 0; i < array_size; i++) {
3764 if (array[i].microamp == microamp)
3765 return array[i].reg_val;
3766 }
3767
3768 return -EINVAL;
3769 }
3770
3771 /**
3772 * ksz_drive_strength_error() - Report invalid drive strength value
3773 * @dev: ksz device
3774 * @array: The array of drive strength values to search.
3775 * @array_size: The size of the array.
3776 * @microamp: Invalid drive strength value in microamp
3777 *
3778 * This function logs an error message when an unsupported drive strength value
3779 * is detected. It lists out all the supported drive strength values for
3780 * reference in the error message.
3781 */
ksz_drive_strength_error(struct ksz_device * dev,const struct ksz_drive_strength * array,size_t array_size,int microamp)3782 void ksz_drive_strength_error(struct ksz_device *dev,
3783 const struct ksz_drive_strength *array,
3784 size_t array_size, int microamp)
3785 {
3786 char supported_values[100];
3787 size_t remaining_size;
3788 int added_len;
3789 char *ptr;
3790 int i;
3791
3792 remaining_size = sizeof(supported_values);
3793 ptr = supported_values;
3794
3795 for (i = 0; i < array_size; i++) {
3796 added_len = snprintf(ptr, remaining_size,
3797 i == 0 ? "%d" : ", %d", array[i].microamp);
3798
3799 if (added_len >= remaining_size)
3800 break;
3801
3802 ptr += added_len;
3803 remaining_size -= added_len;
3804 }
3805
3806 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n",
3807 microamp, supported_values);
3808 }
3809
3810 /**
3811 * ksz_drive_strength_write() - Set the drive strength for specific KSZ9477
3812 * and the KSZ87xx chip variants.
3813 * @dev: ksz device
3814 * @props: Array of drive strength properties to be applied
3815 * @num_props: Number of properties in the array
3816 *
3817 * This function configures the drive strength for various KSZ9477 chip variants
3818 * based on the provided properties. It handles chip-specific nuances and
3819 * ensures only valid drive strengths are written to the respective chip.
3820 *
3821 * Return: 0 on successful configuration, a negative error code on failure.
3822 */
ksz_drive_strength_write(struct ksz_device * dev,struct ksz_driver_strength_prop * props,int num_props)3823 int ksz_drive_strength_write(struct ksz_device *dev,
3824 struct ksz_driver_strength_prop *props,
3825 int num_props)
3826 {
3827 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths);
3828 int i, ret, reg;
3829 u8 mask = 0;
3830 u8 val = 0;
3831
3832 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1)
3833 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
3834 props[KSZ_DRIVER_STRENGTH_IO].name);
3835
3836 if (dev->chip_id == KSZ8795_CHIP_ID ||
3837 dev->chip_id == KSZ8794_CHIP_ID ||
3838 dev->chip_id == KSZ8765_CHIP_ID)
3839 reg = KSZ8795_REG_SW_CTRL_20;
3840 else
3841 reg = KSZ9477_REG_SW_IO_STRENGTH;
3842
3843 for (i = 0; i < num_props; i++) {
3844 if (props[i].value == -1)
3845 continue;
3846
3847 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths,
3848 array_size, props[i].value);
3849 if (ret < 0) {
3850 ksz_drive_strength_error(dev, ksz9477_drive_strengths,
3851 array_size, props[i].value);
3852 return ret;
3853 }
3854
3855 mask |= SW_DRIVE_STRENGTH_M << props[i].offset;
3856 val |= ret << props[i].offset;
3857 }
3858
3859 return ksz_rmw8(dev, reg, mask, val);
3860 }
3861
ksz8463_configure_straps_spi(struct ksz_device * dev)3862 static int ksz8463_configure_straps_spi(struct ksz_device *dev)
3863 {
3864 struct pinctrl *pinctrl;
3865 struct gpio_desc *rxd0;
3866 struct gpio_desc *rxd1;
3867
3868 rxd0 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 0, GPIOD_OUT_LOW);
3869 if (IS_ERR(rxd0))
3870 return PTR_ERR(rxd0);
3871
3872 rxd1 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 1, GPIOD_OUT_HIGH);
3873 if (IS_ERR(rxd1))
3874 return PTR_ERR(rxd1);
3875
3876 if (!rxd0 && !rxd1)
3877 return 0;
3878
3879 if ((rxd0 && !rxd1) || (rxd1 && !rxd0))
3880 return -EINVAL;
3881
3882 pinctrl = devm_pinctrl_get_select(dev->dev, "reset");
3883 if (IS_ERR(pinctrl))
3884 return PTR_ERR(pinctrl);
3885
3886 return 0;
3887 }
3888
ksz8463_release_straps_spi(struct ksz_device * dev)3889 static int ksz8463_release_straps_spi(struct ksz_device *dev)
3890 {
3891 return pinctrl_select_default_state(dev->dev);
3892 }
3893
ksz_switch_register(struct ksz_device * dev)3894 int ksz_switch_register(struct ksz_device *dev)
3895 {
3896 const struct ksz_chip_data *info;
3897 struct device_node *ports;
3898 phy_interface_t interface;
3899 unsigned int port_num;
3900 int ret;
3901 int i;
3902
3903 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
3904 GPIOD_OUT_LOW);
3905 if (IS_ERR(dev->reset_gpio))
3906 return PTR_ERR(dev->reset_gpio);
3907
3908 if (dev->reset_gpio) {
3909 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) {
3910 ret = ksz8463_configure_straps_spi(dev);
3911 if (ret)
3912 return ret;
3913 }
3914
3915 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3916 usleep_range(10000, 12000);
3917 gpiod_set_value_cansleep(dev->reset_gpio, 0);
3918 msleep(100);
3919
3920 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) {
3921 ret = ksz8463_release_straps_spi(dev);
3922 if (ret)
3923 return ret;
3924 }
3925 }
3926
3927 mutex_init(&dev->dev_mutex);
3928 mutex_init(&dev->regmap_mutex);
3929 mutex_init(&dev->alu_mutex);
3930 mutex_init(&dev->vlan_mutex);
3931
3932 ret = ksz_switch_detect(dev);
3933 if (ret)
3934 return ret;
3935
3936 info = ksz_lookup_info(dev->chip_id);
3937 if (!info)
3938 return -ENODEV;
3939
3940 /* Update the compatible info with the probed one */
3941 dev->info = info;
3942
3943 dev_info(dev->dev, "found switch: %s, rev %i\n",
3944 dev->info->dev_name, dev->chip_rev);
3945
3946 ret = ksz_check_device_id(dev);
3947 if (ret)
3948 return ret;
3949
3950 dev->dev_ops = dev->info->ops;
3951
3952 ret = dev->dev_ops->init(dev);
3953 if (ret)
3954 return ret;
3955
3956 dev->ports = devm_kzalloc(dev->dev,
3957 dev->info->port_cnt * sizeof(struct ksz_port),
3958 GFP_KERNEL);
3959 if (!dev->ports)
3960 return -ENOMEM;
3961
3962 for (i = 0; i < dev->info->port_cnt; i++) {
3963 spin_lock_init(&dev->ports[i].mib.stats64_lock);
3964 mutex_init(&dev->ports[i].mib.cnt_mutex);
3965 dev->ports[i].mib.counters =
3966 devm_kzalloc(dev->dev,
3967 sizeof(u64) * (dev->info->mib_cnt + 1),
3968 GFP_KERNEL);
3969 if (!dev->ports[i].mib.counters)
3970 return -ENOMEM;
3971
3972 dev->ports[i].ksz_dev = dev;
3973 dev->ports[i].num = i;
3974 }
3975
3976 /* set the real number of ports */
3977 dev->ds->num_ports = dev->info->port_cnt;
3978
3979 /* set the phylink ops */
3980 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops;
3981
3982 /* Host port interface will be self detected, or specifically set in
3983 * device tree.
3984 */
3985 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
3986 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
3987 if (dev->dev->of_node) {
3988 ret = of_get_phy_mode(dev->dev->of_node, &interface);
3989 if (ret == 0)
3990 dev->compat_interface = interface;
3991 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
3992 if (!ports)
3993 ports = of_get_child_by_name(dev->dev->of_node, "ports");
3994 if (ports) {
3995 for_each_available_child_of_node_scoped(ports, port) {
3996 if (of_property_read_u32(port, "reg",
3997 &port_num))
3998 continue;
3999 if (!(dev->port_mask & BIT(port_num))) {
4000 of_node_put(ports);
4001 return -EINVAL;
4002 }
4003 of_get_phy_mode(port,
4004 &dev->ports[port_num].interface);
4005
4006 ksz_parse_rgmii_delay(dev, port_num, port);
4007 dev->ports[port_num].fiber =
4008 of_property_read_bool(port,
4009 "micrel,fiber-mode");
4010 }
4011 of_node_put(ports);
4012 }
4013 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
4014 "microchip,synclko-125");
4015 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
4016 "microchip,synclko-disable");
4017 if (dev->synclko_125 && dev->synclko_disable) {
4018 dev_err(dev->dev, "inconsistent synclko settings\n");
4019 return -EINVAL;
4020 }
4021
4022 dev->wakeup_source = of_property_read_bool(dev->dev->of_node,
4023 "wakeup-source");
4024 dev->pme_active_high = of_property_read_bool(dev->dev->of_node,
4025 "microchip,pme-active-high");
4026 }
4027
4028 ret = dsa_register_switch(dev->ds);
4029 if (ret)
4030 return ret;
4031
4032 /* Read MIB counters every 30 seconds to avoid overflow. */
4033 dev->mib_read_interval = msecs_to_jiffies(5000);
4034
4035 /* Start the MIB timer. */
4036 schedule_delayed_work(&dev->mib_read, 0);
4037
4038 return ret;
4039 }
4040 EXPORT_SYMBOL(ksz_switch_register);
4041
ksz_switch_remove(struct ksz_device * dev)4042 void ksz_switch_remove(struct ksz_device *dev)
4043 {
4044 /* timer started */
4045 if (dev->mib_read_interval) {
4046 dev->mib_read_interval = 0;
4047 cancel_delayed_work_sync(&dev->mib_read);
4048 }
4049
4050 dsa_unregister_switch(dev->ds);
4051 }
4052 EXPORT_SYMBOL(ksz_switch_remove);
4053
4054 #ifdef CONFIG_PM_SLEEP
ksz_switch_suspend(struct device * dev)4055 int ksz_switch_suspend(struct device *dev)
4056 {
4057 struct ksz_device *priv = dev_get_drvdata(dev);
4058
4059 return dsa_switch_suspend(priv->ds);
4060 }
4061 EXPORT_SYMBOL(ksz_switch_suspend);
4062
ksz_switch_resume(struct device * dev)4063 int ksz_switch_resume(struct device *dev)
4064 {
4065 struct ksz_device *priv = dev_get_drvdata(dev);
4066
4067 return dsa_switch_resume(priv->ds);
4068 }
4069 EXPORT_SYMBOL(ksz_switch_resume);
4070 #endif
4071
4072 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
4073 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
4074 MODULE_LICENSE("GPL");
4075