1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 28 #include "core_types.h" 29 #include "link_encoder.h" 30 #include "dce_link_encoder.h" 31 #include "stream_encoder.h" 32 #include "dc_bios_types.h" 33 34 #include "gpio_service_interface.h" 35 36 #include "dce/dce_11_0_d.h" 37 #include "dce/dce_11_0_sh_mask.h" 38 #include "dce/dce_11_0_enum.h" 39 40 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 41 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa 42 #endif 43 44 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 45 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L 46 #endif 47 48 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 49 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L 50 #endif 51 52 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 53 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c 54 #endif 55 56 #define CTX \ 57 enc110->base.ctx 58 #define DC_LOGGER \ 59 enc110->base.ctx->logger 60 61 #define REG(reg)\ 62 (enc110->link_regs->reg) 63 64 #define AUX_REG(reg)\ 65 (enc110->aux_regs->reg) 66 67 #define HPD_REG(reg)\ 68 (enc110->hpd_regs->reg) 69 70 #define DEFAULT_AUX_MAX_DATA_SIZE 16 71 #define AUX_MAX_DEFER_WRITE_RETRY 20 72 /* 73 * @brief 74 * Trigger Source Select 75 * ASIC-dependent, actual values for register programming 76 */ 77 #define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0 78 #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1 79 #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2 80 #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4 81 #define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08 82 #define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10 83 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20 84 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40 85 86 enum { 87 DP_MST_UPDATE_MAX_RETRY = 50 88 }; 89 90 #define DIG_REG(reg)\ 91 (reg + enc110->offsets.dig) 92 93 #define DP_REG(reg)\ 94 (reg + enc110->offsets.dp) 95 96 static const struct link_encoder_funcs dce110_lnk_enc_funcs = { 97 .validate_output_with_stream = 98 dce110_link_encoder_validate_output_with_stream, 99 .hw_init = dce110_link_encoder_hw_init, 100 .setup = dce110_link_encoder_setup, 101 .enable_tmds_output = dce110_link_encoder_enable_tmds_output, 102 .enable_dp_output = dce110_link_encoder_enable_dp_output, 103 .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output, 104 .enable_lvds_output = dce110_link_encoder_enable_lvds_output, 105 .disable_output = dce110_link_encoder_disable_output, 106 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, 107 .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, 108 .update_mst_stream_allocation_table = 109 dce110_link_encoder_update_mst_stream_allocation_table, 110 .psr_program_dp_dphy_fast_training = 111 dce110_psr_program_dp_dphy_fast_training, 112 .psr_program_secondary_packet = dce110_psr_program_secondary_packet, 113 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, 114 .enable_hpd = dce110_link_encoder_enable_hpd, 115 .disable_hpd = dce110_link_encoder_disable_hpd, 116 .is_dig_enabled = dce110_is_dig_enabled, 117 .destroy = dce110_link_encoder_destroy, 118 .get_max_link_cap = dce110_link_encoder_get_max_link_cap, 119 .get_dig_frontend = dce110_get_dig_frontend, 120 }; 121 122 static enum bp_result link_transmitter_control( 123 struct dce110_link_encoder *enc110, 124 struct bp_transmitter_control *cntl) 125 { 126 enum bp_result result; 127 struct dc_bios *bp = enc110->base.ctx->dc_bios; 128 129 result = bp->funcs->transmitter_control(bp, cntl); 130 131 return result; 132 } 133 134 static void enable_phy_bypass_mode( 135 struct dce110_link_encoder *enc110, 136 bool enable) 137 { 138 /* This register resides in DP back end block; 139 * transmitter is used for the offset */ 140 141 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); 142 143 } 144 145 static void disable_prbs_symbols( 146 struct dce110_link_encoder *enc110, 147 bool disable) 148 { 149 /* This register resides in DP back end block; 150 * transmitter is used for the offset */ 151 152 REG_UPDATE_4(DP_DPHY_CNTL, 153 DPHY_ATEST_SEL_LANE0, disable, 154 DPHY_ATEST_SEL_LANE1, disable, 155 DPHY_ATEST_SEL_LANE2, disable, 156 DPHY_ATEST_SEL_LANE3, disable); 157 } 158 159 static void disable_prbs_mode( 160 struct dce110_link_encoder *enc110) 161 { 162 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); 163 } 164 165 static void program_pattern_symbols( 166 struct dce110_link_encoder *enc110, 167 uint16_t pattern_symbols[8]) 168 { 169 /* This register resides in DP back end block; 170 * transmitter is used for the offset */ 171 172 REG_SET_3(DP_DPHY_SYM0, 0, 173 DPHY_SYM1, pattern_symbols[0], 174 DPHY_SYM2, pattern_symbols[1], 175 DPHY_SYM3, pattern_symbols[2]); 176 177 /* This register resides in DP back end block; 178 * transmitter is used for the offset */ 179 180 REG_SET_3(DP_DPHY_SYM1, 0, 181 DPHY_SYM4, pattern_symbols[3], 182 DPHY_SYM5, pattern_symbols[4], 183 DPHY_SYM6, pattern_symbols[5]); 184 185 /* This register resides in DP back end block; 186 * transmitter is used for the offset */ 187 188 REG_SET_2(DP_DPHY_SYM2, 0, 189 DPHY_SYM7, pattern_symbols[6], 190 DPHY_SYM8, pattern_symbols[7]); 191 } 192 193 static void set_dp_phy_pattern_d102( 194 struct dce110_link_encoder *enc110) 195 { 196 /* Disable PHY Bypass mode to setup the test pattern */ 197 enable_phy_bypass_mode(enc110, false); 198 199 /* For 10-bit PRBS or debug symbols 200 * please use the following sequence: */ 201 202 /* Enable debug symbols on the lanes */ 203 204 disable_prbs_symbols(enc110, true); 205 206 /* Disable PRBS mode */ 207 disable_prbs_mode(enc110); 208 209 /* Program debug symbols to be output */ 210 { 211 uint16_t pattern_symbols[8] = { 212 0x2AA, 0x2AA, 0x2AA, 0x2AA, 213 0x2AA, 0x2AA, 0x2AA, 0x2AA 214 }; 215 216 program_pattern_symbols(enc110, pattern_symbols); 217 } 218 219 /* Enable phy bypass mode to enable the test pattern */ 220 221 enable_phy_bypass_mode(enc110, true); 222 } 223 224 static void set_link_training_complete( 225 struct dce110_link_encoder *enc110, 226 bool complete) 227 { 228 /* This register resides in DP back end block; 229 * transmitter is used for the offset */ 230 231 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); 232 233 } 234 235 unsigned int dce110_get_dig_frontend(struct link_encoder *enc) 236 { 237 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 238 u32 value; 239 enum engine_id result; 240 241 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); 242 243 switch (value) { 244 case DCE110_DIG_FE_SOURCE_SELECT_DIGA: 245 result = ENGINE_ID_DIGA; 246 break; 247 case DCE110_DIG_FE_SOURCE_SELECT_DIGB: 248 result = ENGINE_ID_DIGB; 249 break; 250 case DCE110_DIG_FE_SOURCE_SELECT_DIGC: 251 result = ENGINE_ID_DIGC; 252 break; 253 case DCE110_DIG_FE_SOURCE_SELECT_DIGD: 254 result = ENGINE_ID_DIGD; 255 break; 256 case DCE110_DIG_FE_SOURCE_SELECT_DIGE: 257 result = ENGINE_ID_DIGE; 258 break; 259 case DCE110_DIG_FE_SOURCE_SELECT_DIGF: 260 result = ENGINE_ID_DIGF; 261 break; 262 case DCE110_DIG_FE_SOURCE_SELECT_DIGG: 263 result = ENGINE_ID_DIGG; 264 break; 265 default: 266 // invalid source select DIG 267 result = ENGINE_ID_UNKNOWN; 268 } 269 270 return result; 271 } 272 273 void dce110_link_encoder_set_dp_phy_pattern_training_pattern( 274 struct link_encoder *enc, 275 uint32_t index) 276 { 277 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 278 /* Write Training Pattern */ 279 280 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index); 281 282 /* Set HW Register Training Complete to false */ 283 284 set_link_training_complete(enc110, false); 285 286 /* Disable PHY Bypass mode to output Training Pattern */ 287 288 enable_phy_bypass_mode(enc110, false); 289 290 /* Disable PRBS mode */ 291 disable_prbs_mode(enc110); 292 } 293 294 static void setup_panel_mode( 295 struct dce110_link_encoder *enc110, 296 enum dp_panel_mode panel_mode) 297 { 298 uint32_t value; 299 struct dc_context *ctx = enc110->base.ctx; 300 301 /* if psp set panel mode, dal should be program it */ 302 if (ctx->dc->caps.psp_setup_panel_mode) 303 return; 304 305 /* The code below is only applicable to encoders with a digital transmitter. */ 306 if (enc110->base.transmitter == TRANSMITTER_UNKNOWN) 307 return; 308 309 ASSERT(REG(DP_DPHY_INTERNAL_CTRL)); 310 value = REG_READ(DP_DPHY_INTERNAL_CTRL); 311 312 switch (panel_mode) { 313 case DP_PANEL_MODE_EDP: 314 value = 0x1; 315 break; 316 case DP_PANEL_MODE_SPECIAL: 317 value = 0x11; 318 break; 319 default: 320 value = 0x0; 321 break; 322 } 323 324 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value); 325 } 326 327 static void set_dp_phy_pattern_symbol_error( 328 struct dce110_link_encoder *enc110) 329 { 330 /* Disable PHY Bypass mode to setup the test pattern */ 331 enable_phy_bypass_mode(enc110, false); 332 333 /* program correct panel mode*/ 334 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 335 336 /* A PRBS23 pattern is used for most DP electrical measurements. */ 337 338 /* Enable PRBS symbols on the lanes */ 339 disable_prbs_symbols(enc110, false); 340 341 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */ 342 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 343 DPHY_PRBS_SEL, 1, 344 DPHY_PRBS_EN, 1); 345 346 /* Enable phy bypass mode to enable the test pattern */ 347 enable_phy_bypass_mode(enc110, true); 348 } 349 350 static void set_dp_phy_pattern_prbs7( 351 struct dce110_link_encoder *enc110) 352 { 353 /* Disable PHY Bypass mode to setup the test pattern */ 354 enable_phy_bypass_mode(enc110, false); 355 356 /* A PRBS7 pattern is used for most DP electrical measurements. */ 357 358 /* Enable PRBS symbols on the lanes */ 359 disable_prbs_symbols(enc110, false); 360 361 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */ 362 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 363 DPHY_PRBS_SEL, 0, 364 DPHY_PRBS_EN, 1); 365 366 /* Enable phy bypass mode to enable the test pattern */ 367 enable_phy_bypass_mode(enc110, true); 368 } 369 370 static void set_dp_phy_pattern_80bit_custom( 371 struct dce110_link_encoder *enc110, 372 const uint8_t *pattern) 373 { 374 /* Disable PHY Bypass mode to setup the test pattern */ 375 enable_phy_bypass_mode(enc110, false); 376 377 /* Enable debug symbols on the lanes */ 378 379 disable_prbs_symbols(enc110, true); 380 381 /* Enable PHY bypass mode to enable the test pattern */ 382 /* TODO is it really needed ? */ 383 384 enable_phy_bypass_mode(enc110, true); 385 386 /* Program 80 bit custom pattern */ 387 { 388 uint16_t pattern_symbols[8]; 389 390 pattern_symbols[0] = 391 ((pattern[1] & 0x03) << 8) | pattern[0]; 392 pattern_symbols[1] = 393 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f); 394 pattern_symbols[2] = 395 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f); 396 pattern_symbols[3] = 397 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03); 398 pattern_symbols[4] = 399 ((pattern[6] & 0x03) << 8) | pattern[5]; 400 pattern_symbols[5] = 401 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f); 402 pattern_symbols[6] = 403 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f); 404 pattern_symbols[7] = 405 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03); 406 407 program_pattern_symbols(enc110, pattern_symbols); 408 } 409 410 /* Enable phy bypass mode to enable the test pattern */ 411 412 enable_phy_bypass_mode(enc110, true); 413 } 414 415 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2( 416 struct dce110_link_encoder *enc110, 417 unsigned int cp2520_pattern) 418 { 419 420 /* previously there is a register DP_HBR2_EYE_PATTERN 421 * that is enabled to get the pattern. 422 * But it does not work with the latest spec change, 423 * so we are programming the following registers manually. 424 * 425 * The following settings have been confirmed 426 * by Nick Chorney and Sandra Liu */ 427 428 /* Disable PHY Bypass mode to setup the test pattern */ 429 430 enable_phy_bypass_mode(enc110, false); 431 432 /* Setup DIG encoder in DP SST mode */ 433 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); 434 435 /* ensure normal panel mode. */ 436 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 437 438 /* no vbid after BS (SR) 439 * DP_LINK_FRAMING_CNTL changed history Sandra Liu 440 * 11000260 / 11000104 / 110000FC */ 441 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 442 DP_IDLE_BS_INTERVAL, 0xFC, 443 DP_VBID_DISABLE, 1, 444 DP_VID_ENHANCED_FRAME_MODE, 1); 445 446 /* swap every BS with SR */ 447 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); 448 449 /* select cp2520 patterns */ 450 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) 451 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, 452 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); 453 else 454 /* pre-DCE11 can only generate CP2520 pattern 2 */ 455 ASSERT(cp2520_pattern == 2); 456 457 /* set link training complete */ 458 set_link_training_complete(enc110, true); 459 460 /* disable video stream */ 461 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 462 463 /* Disable PHY Bypass mode to setup the test pattern */ 464 enable_phy_bypass_mode(enc110, false); 465 } 466 467 #if defined(CONFIG_DRM_AMD_DC_SI) 468 static void dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2( 469 struct dce110_link_encoder *enc110, 470 unsigned int cp2520_pattern) 471 { 472 473 /* previously there is a register DP_HBR2_EYE_PATTERN 474 * that is enabled to get the pattern. 475 * But it does not work with the latest spec change, 476 * so we are programming the following registers manually. 477 * 478 * The following settings have been confirmed 479 * by Nick Chorney and Sandra Liu */ 480 481 /* Disable PHY Bypass mode to setup the test pattern */ 482 483 enable_phy_bypass_mode(enc110, false); 484 485 /* Setup DIG encoder in DP SST mode */ 486 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); 487 488 /* ensure normal panel mode. */ 489 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 490 491 /* no vbid after BS (SR) 492 * DP_LINK_FRAMING_CNTL changed history Sandra Liu 493 * 11000260 / 11000104 / 110000FC */ 494 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 495 DP_IDLE_BS_INTERVAL, 0xFC, 496 DP_VBID_DISABLE, 1, 497 DP_VID_ENHANCED_FRAME_MODE, 1); 498 499 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip swap BS with SR */ 500 501 /* select cp2520 patterns */ 502 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) 503 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, 504 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); 505 else 506 /* pre-DCE11 can only generate CP2520 pattern 2 */ 507 ASSERT(cp2520_pattern == 2); 508 509 /* set link training complete */ 510 set_link_training_complete(enc110, true); 511 512 /* disable video stream */ 513 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 514 515 /* Disable PHY Bypass mode to setup the test pattern */ 516 enable_phy_bypass_mode(enc110, false); 517 } 518 #endif 519 520 static void set_dp_phy_pattern_passthrough_mode( 521 struct dce110_link_encoder *enc110, 522 enum dp_panel_mode panel_mode) 523 { 524 /* program correct panel mode */ 525 setup_panel_mode(enc110, panel_mode); 526 527 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT 528 * in case we were doing HBR2 compliance pattern before 529 */ 530 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 531 DP_IDLE_BS_INTERVAL, 0x2000, 532 DP_VBID_DISABLE, 0, 533 DP_VID_ENHANCED_FRAME_MODE, 1); 534 535 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); 536 537 /* set link training complete */ 538 set_link_training_complete(enc110, true); 539 540 /* Disable PHY Bypass mode to setup the test pattern */ 541 enable_phy_bypass_mode(enc110, false); 542 543 /* Disable PRBS mode */ 544 disable_prbs_mode(enc110); 545 } 546 547 #if defined(CONFIG_DRM_AMD_DC_SI) 548 static void dce60_set_dp_phy_pattern_passthrough_mode( 549 struct dce110_link_encoder *enc110, 550 enum dp_panel_mode panel_mode) 551 { 552 /* program correct panel mode */ 553 setup_panel_mode(enc110, panel_mode); 554 555 /* restore LINK_FRAMING_CNTL 556 * in case we were doing HBR2 compliance pattern before 557 */ 558 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 559 DP_IDLE_BS_INTERVAL, 0x2000, 560 DP_VBID_DISABLE, 0, 561 DP_VID_ENHANCED_FRAME_MODE, 1); 562 563 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip DPHY_SCRAMBLER_BS_COUNT restore */ 564 565 /* set link training complete */ 566 set_link_training_complete(enc110, true); 567 568 /* Disable PHY Bypass mode to setup the test pattern */ 569 enable_phy_bypass_mode(enc110, false); 570 571 /* Disable PRBS mode */ 572 disable_prbs_mode(enc110); 573 } 574 #endif 575 576 /* return value is bit-vector */ 577 static uint8_t get_frontend_source( 578 enum engine_id engine) 579 { 580 switch (engine) { 581 case ENGINE_ID_DIGA: 582 return DCE110_DIG_FE_SOURCE_SELECT_DIGA; 583 case ENGINE_ID_DIGB: 584 return DCE110_DIG_FE_SOURCE_SELECT_DIGB; 585 case ENGINE_ID_DIGC: 586 return DCE110_DIG_FE_SOURCE_SELECT_DIGC; 587 case ENGINE_ID_DIGD: 588 return DCE110_DIG_FE_SOURCE_SELECT_DIGD; 589 case ENGINE_ID_DIGE: 590 return DCE110_DIG_FE_SOURCE_SELECT_DIGE; 591 case ENGINE_ID_DIGF: 592 return DCE110_DIG_FE_SOURCE_SELECT_DIGF; 593 case ENGINE_ID_DIGG: 594 return DCE110_DIG_FE_SOURCE_SELECT_DIGG; 595 default: 596 ASSERT_CRITICAL(false); 597 return DCE110_DIG_FE_SOURCE_SELECT_INVALID; 598 } 599 } 600 601 static void configure_encoder( 602 struct dce110_link_encoder *enc110, 603 const struct dc_link_settings *link_settings) 604 { 605 /* set number of lanes */ 606 607 REG_SET(DP_CONFIG, 0, 608 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); 609 610 /* setup scrambler */ 611 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); 612 } 613 614 #if defined(CONFIG_DRM_AMD_DC_SI) 615 static void dce60_configure_encoder( 616 struct dce110_link_encoder *enc110, 617 const struct dc_link_settings *link_settings) 618 { 619 /* set number of lanes */ 620 621 REG_SET(DP_CONFIG, 0, 622 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); 623 624 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip setup scrambler */ 625 } 626 #endif 627 628 static void aux_initialize( 629 struct dce110_link_encoder *enc110) 630 { 631 struct dc_context *ctx = enc110->base.ctx; 632 enum hpd_source_id hpd_source = enc110->base.hpd_source; 633 uint32_t addr = AUX_REG(AUX_CONTROL); 634 uint32_t value = dm_read_reg(ctx, addr); 635 636 set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL); 637 set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN); 638 dm_write_reg(ctx, addr, value); 639 640 addr = AUX_REG(AUX_DPHY_RX_CONTROL0); 641 value = dm_read_reg(ctx, addr); 642 643 /* 1/4 window (the maximum allowed) */ 644 set_reg_field_value(value, 1, 645 AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW); 646 dm_write_reg(ctx, addr, value); 647 648 } 649 650 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc, 651 bool exit_link_training_required) 652 { 653 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 654 655 if (exit_link_training_required) 656 REG_UPDATE(DP_DPHY_FAST_TRAINING, 657 DPHY_RX_FAST_TRAINING_CAPABLE, 1); 658 else { 659 REG_UPDATE(DP_DPHY_FAST_TRAINING, 660 DPHY_RX_FAST_TRAINING_CAPABLE, 0); 661 /*In DCE 11, we are able to pre-program a Force SR register 662 * to be able to trigger SR symbol after 5 idle patterns 663 * transmitted. Upon PSR Exit, DMCU can trigger 664 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to 665 * DPHY_LOAD_BS_COUNT_START and the internal counter 666 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be 667 * replaced by SR symbol once. 668 */ 669 670 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5); 671 } 672 } 673 674 void dce110_psr_program_secondary_packet(struct link_encoder *enc, 675 unsigned int sdp_transmit_line_num_deadline) 676 { 677 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 678 679 REG_UPDATE_2(DP_SEC_CNTL1, 680 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline, 681 DP_SEC_GSP0_PRIORITY, 1); 682 } 683 684 bool dce110_is_dig_enabled(struct link_encoder *enc) 685 { 686 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 687 uint32_t value; 688 689 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); 690 return value; 691 } 692 693 static void link_encoder_disable(struct dce110_link_encoder *enc110) 694 { 695 /* reset training pattern */ 696 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0, 697 DPHY_TRAINING_PATTERN_SEL, 0); 698 699 /* reset training complete */ 700 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0); 701 702 /* reset panel mode */ 703 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT); 704 } 705 706 static void hpd_initialize( 707 struct dce110_link_encoder *enc110) 708 { 709 /* Associate HPD with DIG_BE */ 710 enum hpd_source_id hpd_source = enc110->base.hpd_source; 711 712 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source); 713 } 714 715 bool dce110_link_encoder_validate_dvi_output( 716 const struct dce110_link_encoder *enc110, 717 enum signal_type connector_signal, 718 enum signal_type signal, 719 const struct dc_crtc_timing *crtc_timing) 720 { 721 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK; 722 723 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK) 724 max_pixel_clock *= 2; 725 726 /* This handles the case of HDMI downgrade to DVI we don't want to 727 * we don't want to cap the pixel clock if the DDI is not DVI. 728 */ 729 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK && 730 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 731 max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock; 732 733 /* DVI only support RGB pixel encoding */ 734 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB) 735 return false; 736 737 /*connect DVI via adpater's HDMI connector*/ 738 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 739 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) && 740 signal != SIGNAL_TYPE_HDMI_TYPE_A && 741 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10)) 742 return false; 743 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) 744 return false; 745 746 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10)) 747 return false; 748 749 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */ 750 switch (crtc_timing->display_color_depth) { 751 case COLOR_DEPTH_666: 752 case COLOR_DEPTH_888: 753 break; 754 case COLOR_DEPTH_101010: 755 case COLOR_DEPTH_161616: 756 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK) 757 return false; 758 break; 759 default: 760 return false; 761 } 762 763 return true; 764 } 765 766 static bool dce110_link_encoder_validate_hdmi_output( 767 const struct dce110_link_encoder *enc110, 768 const struct dc_crtc_timing *crtc_timing, 769 int adjusted_pix_clk_khz) 770 { 771 enum dc_color_depth max_deep_color = 772 enc110->base.features.max_hdmi_deep_color; 773 774 if (max_deep_color < crtc_timing->display_color_depth) 775 return false; 776 777 if (crtc_timing->display_color_depth < COLOR_DEPTH_888) 778 return false; 779 if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK) 780 return false; 781 782 if ((adjusted_pix_clk_khz == 0) || 783 (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock)) 784 return false; 785 786 /* DCE11 HW does not support 420 */ 787 if (!enc110->base.features.hdmi_ycbcr420_supported && 788 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 789 return false; 790 791 if ((!enc110->base.features.flags.bits.HDMI_6GB_EN || 792 enc110->base.ctx->dc->debug.hdmi20_disable) && 793 adjusted_pix_clk_khz >= 300000) 794 return false; 795 if (enc110->base.ctx->dc->debug.hdmi20_disable && 796 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 797 return false; 798 return true; 799 } 800 801 bool dce110_link_encoder_validate_dp_output( 802 const struct dce110_link_encoder *enc110, 803 const struct dc_crtc_timing *crtc_timing) 804 { 805 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 806 return false; 807 808 return true; 809 } 810 811 static bool dce110_link_encoder_validate_rgb_output( 812 const struct dce110_link_encoder *enc110, 813 const struct dc_crtc_timing *crtc_timing) 814 { 815 /* When the VBIOS doesn't specify any limits, use 400 MHz. 816 * The value comes from amdgpu_atombios_get_clock_info. 817 */ 818 uint32_t max_pixel_clock_khz = 400000; 819 820 if (enc110->base.ctx->dc_bios->fw_info_valid && 821 enc110->base.ctx->dc_bios->fw_info.max_pixel_clock) { 822 max_pixel_clock_khz = 823 enc110->base.ctx->dc_bios->fw_info.max_pixel_clock; 824 } 825 826 if (crtc_timing->pix_clk_100hz > max_pixel_clock_khz * 10) 827 return false; 828 829 if (crtc_timing->display_color_depth != COLOR_DEPTH_888) 830 return false; 831 832 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB) 833 return false; 834 835 return true; 836 } 837 838 void dce110_link_encoder_construct( 839 struct dce110_link_encoder *enc110, 840 const struct encoder_init_data *init_data, 841 const struct encoder_feature_support *enc_features, 842 const struct dce110_link_enc_registers *link_regs, 843 const struct dce110_link_enc_aux_registers *aux_regs, 844 const struct dce110_link_enc_hpd_registers *hpd_regs) 845 { 846 struct bp_encoder_cap_info bp_cap_info = {0}; 847 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 848 enum bp_result result = BP_RESULT_OK; 849 850 enc110->base.funcs = &dce110_lnk_enc_funcs; 851 enc110->base.ctx = init_data->ctx; 852 enc110->base.id = init_data->encoder; 853 854 enc110->base.hpd_source = init_data->hpd_source; 855 enc110->base.connector = init_data->connector; 856 857 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 858 enc110->base.analog_engine = init_data->analog_engine; 859 860 enc110->base.features = *enc_features; 861 862 enc110->base.transmitter = init_data->transmitter; 863 864 /* set the flag to indicate whether driver poll the I2C data pin 865 * while doing the DP sink detect 866 */ 867 868 /* if (dal_adapter_service_is_feature_supported(as, 869 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 870 enc110->base.features.flags.bits. 871 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 872 873 enc110->base.output_signals = 874 SIGNAL_TYPE_DVI_SINGLE_LINK | 875 SIGNAL_TYPE_DVI_DUAL_LINK | 876 SIGNAL_TYPE_LVDS | 877 SIGNAL_TYPE_DISPLAY_PORT | 878 SIGNAL_TYPE_DISPLAY_PORT_MST | 879 SIGNAL_TYPE_EDP | 880 SIGNAL_TYPE_HDMI_TYPE_A; 881 882 if ((enc110->base.connector.id == CONNECTOR_ID_DUAL_LINK_DVII || 883 enc110->base.connector.id == CONNECTOR_ID_SINGLE_LINK_DVII) && 884 enc110->base.analog_engine != ENGINE_ID_UNKNOWN) 885 enc110->base.output_signals |= SIGNAL_TYPE_RGB; 886 887 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 888 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 889 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 890 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 891 * Prefer DIG assignment is decided by board design. 892 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 893 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 894 * By this, adding DIGG should not hurt DCE 8.0. 895 * This will let DCE 8.1 share DCE 8.0 as much as possible 896 */ 897 898 enc110->link_regs = link_regs; 899 enc110->aux_regs = aux_regs; 900 enc110->hpd_regs = hpd_regs; 901 902 switch (enc110->base.transmitter) { 903 case TRANSMITTER_UNIPHY_A: 904 enc110->base.preferred_engine = ENGINE_ID_DIGA; 905 break; 906 case TRANSMITTER_UNIPHY_B: 907 enc110->base.preferred_engine = ENGINE_ID_DIGB; 908 break; 909 case TRANSMITTER_UNIPHY_C: 910 enc110->base.preferred_engine = ENGINE_ID_DIGC; 911 break; 912 case TRANSMITTER_UNIPHY_D: 913 enc110->base.preferred_engine = ENGINE_ID_DIGD; 914 break; 915 case TRANSMITTER_UNIPHY_E: 916 enc110->base.preferred_engine = ENGINE_ID_DIGE; 917 break; 918 case TRANSMITTER_UNIPHY_F: 919 enc110->base.preferred_engine = ENGINE_ID_DIGF; 920 break; 921 case TRANSMITTER_UNIPHY_G: 922 enc110->base.preferred_engine = ENGINE_ID_DIGG; 923 break; 924 default: 925 if (init_data->analog_engine != ENGINE_ID_UNKNOWN) { 926 /* The connector is analog-only, ie. VGA */ 927 enc110->base.preferred_engine = init_data->analog_engine; 928 enc110->base.output_signals = SIGNAL_TYPE_RGB; 929 enc110->base.transmitter = TRANSMITTER_UNKNOWN; 930 break; 931 } 932 ASSERT_CRITICAL(false); 933 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 934 } 935 936 /* default to one to mirror Windows behavior */ 937 enc110->base.features.flags.bits.HDMI_6GB_EN = 1; 938 939 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios, 940 enc110->base.id, &bp_cap_info); 941 942 /* Override features with DCE-specific values */ 943 if (result == BP_RESULT_OK) { 944 enc110->base.features.flags.bits.IS_HBR2_CAPABLE = 945 bp_cap_info.DP_HBR2_EN; 946 enc110->base.features.flags.bits.IS_HBR3_CAPABLE = 947 bp_cap_info.DP_HBR3_EN; 948 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 949 } else if (result != BP_RESULT_NORECORD) { 950 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 951 __func__, 952 result); 953 } 954 if (enc110->base.ctx->dc->debug.hdmi20_disable) { 955 enc110->base.features.flags.bits.HDMI_6GB_EN = 0; 956 } 957 } 958 959 bool dce110_link_encoder_validate_output_with_stream( 960 struct link_encoder *enc, 961 const struct dc_stream_state *stream) 962 { 963 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 964 bool is_valid; 965 966 switch (stream->signal) { 967 case SIGNAL_TYPE_DVI_SINGLE_LINK: 968 case SIGNAL_TYPE_DVI_DUAL_LINK: 969 is_valid = dce110_link_encoder_validate_dvi_output( 970 enc110, 971 stream->link->connector_signal, 972 stream->signal, 973 &stream->timing); 974 break; 975 case SIGNAL_TYPE_HDMI_TYPE_A: 976 is_valid = dce110_link_encoder_validate_hdmi_output( 977 enc110, 978 &stream->timing, 979 stream->phy_pix_clk); 980 break; 981 case SIGNAL_TYPE_DISPLAY_PORT: 982 case SIGNAL_TYPE_DISPLAY_PORT_MST: 983 is_valid = dce110_link_encoder_validate_dp_output( 984 enc110, &stream->timing); 985 break; 986 case SIGNAL_TYPE_RGB: 987 is_valid = dce110_link_encoder_validate_rgb_output( 988 enc110, &stream->timing); 989 break; 990 case SIGNAL_TYPE_EDP: 991 case SIGNAL_TYPE_LVDS: 992 is_valid = stream->timing.pixel_encoding == PIXEL_ENCODING_RGB; 993 break; 994 case SIGNAL_TYPE_VIRTUAL: 995 is_valid = true; 996 break; 997 default: 998 is_valid = false; 999 break; 1000 } 1001 1002 return is_valid; 1003 } 1004 1005 void dce110_link_encoder_hw_init( 1006 struct link_encoder *enc) 1007 { 1008 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1009 struct bp_transmitter_control cntl = { 0 }; 1010 enum bp_result result; 1011 1012 cntl.action = TRANSMITTER_CONTROL_INIT; 1013 cntl.engine_id = ENGINE_ID_UNKNOWN; 1014 cntl.transmitter = enc110->base.transmitter; 1015 cntl.connector_obj_id = enc110->base.connector; 1016 cntl.lanes_number = LANE_COUNT_FOUR; 1017 cntl.coherent = false; 1018 cntl.hpd_sel = enc110->base.hpd_source; 1019 1020 /* The code below is only applicable to encoders with a digital transmitter. */ 1021 if (enc110->base.transmitter == TRANSMITTER_UNKNOWN) 1022 return; 1023 1024 if (enc110->base.connector.id == CONNECTOR_ID_EDP) 1025 cntl.signal = SIGNAL_TYPE_EDP; 1026 1027 result = link_transmitter_control(enc110, &cntl); 1028 1029 if (result != BP_RESULT_OK) { 1030 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1031 __func__); 1032 BREAK_TO_DEBUGGER(); 1033 return; 1034 } 1035 1036 if (enc110->base.connector.id == CONNECTOR_ID_LVDS) { 1037 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS; 1038 1039 result = link_transmitter_control(enc110, &cntl); 1040 1041 ASSERT(result == BP_RESULT_OK); 1042 1043 } 1044 aux_initialize(enc110); 1045 1046 /* reinitialize HPD. 1047 * hpd_initialize() will pass DIG_FE id to HW context. 1048 * All other routine within HW context will use fe_engine_offset 1049 * as DIG_FE id even caller pass DIG_FE id. 1050 * So this routine must be called first. */ 1051 hpd_initialize(enc110); 1052 } 1053 1054 void dce110_link_encoder_destroy(struct link_encoder **enc) 1055 { 1056 kfree(TO_DCE110_LINK_ENC(*enc)); 1057 *enc = NULL; 1058 } 1059 1060 void dce110_link_encoder_setup( 1061 struct link_encoder *enc, 1062 enum signal_type signal) 1063 { 1064 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1065 1066 switch (signal) { 1067 case SIGNAL_TYPE_EDP: 1068 case SIGNAL_TYPE_DISPLAY_PORT: 1069 /* DP SST */ 1070 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0); 1071 break; 1072 case SIGNAL_TYPE_LVDS: 1073 /* LVDS */ 1074 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1); 1075 break; 1076 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1077 case SIGNAL_TYPE_DVI_DUAL_LINK: 1078 /* TMDS-DVI */ 1079 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2); 1080 break; 1081 case SIGNAL_TYPE_HDMI_TYPE_A: 1082 /* TMDS-HDMI */ 1083 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3); 1084 break; 1085 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1086 /* DP MST */ 1087 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5); 1088 break; 1089 case SIGNAL_TYPE_RGB: 1090 break; 1091 default: 1092 ASSERT_CRITICAL(false); 1093 /* invalid mode ! */ 1094 break; 1095 } 1096 1097 } 1098 1099 /* TODO: still need depth or just pass in adjusted pixel clock? */ 1100 void dce110_link_encoder_enable_tmds_output( 1101 struct link_encoder *enc, 1102 enum clock_source_id clock_source, 1103 enum dc_color_depth color_depth, 1104 enum signal_type signal, 1105 uint32_t pixel_clock) 1106 { 1107 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1108 struct bp_transmitter_control cntl = { 0 }; 1109 enum bp_result result; 1110 1111 /* Enable the PHY */ 1112 cntl.connector_obj_id = enc110->base.connector; 1113 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1114 cntl.engine_id = enc->preferred_engine; 1115 cntl.transmitter = enc110->base.transmitter; 1116 cntl.pll_id = clock_source; 1117 cntl.signal = signal; 1118 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK) 1119 cntl.lanes_number = 8; 1120 else 1121 cntl.lanes_number = 4; 1122 1123 cntl.hpd_sel = enc110->base.hpd_source; 1124 1125 cntl.pixel_clock = pixel_clock; 1126 cntl.color_depth = color_depth; 1127 1128 result = link_transmitter_control(enc110, &cntl); 1129 1130 if (result != BP_RESULT_OK) { 1131 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1132 __func__); 1133 BREAK_TO_DEBUGGER(); 1134 } 1135 } 1136 1137 /* TODO: still need depth or just pass in adjusted pixel clock? */ 1138 void dce110_link_encoder_enable_lvds_output( 1139 struct link_encoder *enc, 1140 enum clock_source_id clock_source, 1141 uint32_t pixel_clock) 1142 { 1143 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1144 struct bp_transmitter_control cntl = { 0 }; 1145 enum bp_result result; 1146 1147 /* Enable the PHY */ 1148 cntl.connector_obj_id = enc110->base.connector; 1149 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1150 cntl.engine_id = enc->preferred_engine; 1151 cntl.transmitter = enc110->base.transmitter; 1152 cntl.pll_id = clock_source; 1153 cntl.signal = SIGNAL_TYPE_LVDS; 1154 cntl.lanes_number = 4; 1155 1156 cntl.hpd_sel = enc110->base.hpd_source; 1157 1158 cntl.pixel_clock = pixel_clock; 1159 1160 result = link_transmitter_control(enc110, &cntl); 1161 1162 if (result != BP_RESULT_OK) { 1163 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1164 __func__); 1165 BREAK_TO_DEBUGGER(); 1166 } 1167 } 1168 1169 /* enables DP PHY output */ 1170 void dce110_link_encoder_enable_dp_output( 1171 struct link_encoder *enc, 1172 const struct dc_link_settings *link_settings, 1173 enum clock_source_id clock_source) 1174 { 1175 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1176 struct bp_transmitter_control cntl = { 0 }; 1177 enum bp_result result; 1178 1179 /* Enable the PHY */ 1180 1181 /* number_of_lanes is used for pixel clock adjust, 1182 * but it's not passed to asic_control. 1183 * We need to set number of lanes manually. 1184 */ 1185 configure_encoder(enc110, link_settings); 1186 cntl.connector_obj_id = enc110->base.connector; 1187 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1188 cntl.engine_id = enc->preferred_engine; 1189 cntl.transmitter = enc110->base.transmitter; 1190 cntl.pll_id = clock_source; 1191 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT; 1192 cntl.lanes_number = link_settings->lane_count; 1193 cntl.hpd_sel = enc110->base.hpd_source; 1194 cntl.pixel_clock = link_settings->link_rate 1195 * LINK_RATE_REF_FREQ_IN_KHZ; 1196 /* TODO: check if undefined works */ 1197 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1198 1199 result = link_transmitter_control(enc110, &cntl); 1200 1201 if (result != BP_RESULT_OK) { 1202 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1203 __func__); 1204 BREAK_TO_DEBUGGER(); 1205 } 1206 } 1207 1208 /* enables DP PHY output in MST mode */ 1209 void dce110_link_encoder_enable_dp_mst_output( 1210 struct link_encoder *enc, 1211 const struct dc_link_settings *link_settings, 1212 enum clock_source_id clock_source) 1213 { 1214 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1215 struct bp_transmitter_control cntl = { 0 }; 1216 enum bp_result result; 1217 1218 /* Enable the PHY */ 1219 1220 /* number_of_lanes is used for pixel clock adjust, 1221 * but it's not passed to asic_control. 1222 * We need to set number of lanes manually. 1223 */ 1224 configure_encoder(enc110, link_settings); 1225 1226 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1227 cntl.engine_id = ENGINE_ID_UNKNOWN; 1228 cntl.transmitter = enc110->base.transmitter; 1229 cntl.pll_id = clock_source; 1230 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; 1231 cntl.lanes_number = link_settings->lane_count; 1232 cntl.hpd_sel = enc110->base.hpd_source; 1233 cntl.pixel_clock = link_settings->link_rate 1234 * LINK_RATE_REF_FREQ_IN_KHZ; 1235 /* TODO: check if undefined works */ 1236 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1237 1238 result = link_transmitter_control(enc110, &cntl); 1239 1240 if (result != BP_RESULT_OK) { 1241 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1242 __func__); 1243 BREAK_TO_DEBUGGER(); 1244 } 1245 } 1246 1247 #if defined(CONFIG_DRM_AMD_DC_SI) 1248 /* enables DP PHY output */ 1249 static void dce60_link_encoder_enable_dp_output( 1250 struct link_encoder *enc, 1251 const struct dc_link_settings *link_settings, 1252 enum clock_source_id clock_source) 1253 { 1254 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1255 struct bp_transmitter_control cntl = { 0 }; 1256 enum bp_result result; 1257 1258 /* Enable the PHY */ 1259 1260 /* number_of_lanes is used for pixel clock adjust, 1261 * but it's not passed to asic_control. 1262 * We need to set number of lanes manually. 1263 */ 1264 dce60_configure_encoder(enc110, link_settings); 1265 cntl.connector_obj_id = enc110->base.connector; 1266 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1267 cntl.engine_id = enc->preferred_engine; 1268 cntl.transmitter = enc110->base.transmitter; 1269 cntl.pll_id = clock_source; 1270 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT; 1271 cntl.lanes_number = link_settings->lane_count; 1272 cntl.hpd_sel = enc110->base.hpd_source; 1273 cntl.pixel_clock = link_settings->link_rate 1274 * LINK_RATE_REF_FREQ_IN_KHZ; 1275 /* TODO: check if undefined works */ 1276 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1277 1278 result = link_transmitter_control(enc110, &cntl); 1279 1280 if (result != BP_RESULT_OK) { 1281 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1282 __func__); 1283 BREAK_TO_DEBUGGER(); 1284 } 1285 } 1286 1287 /* enables DP PHY output in MST mode */ 1288 static void dce60_link_encoder_enable_dp_mst_output( 1289 struct link_encoder *enc, 1290 const struct dc_link_settings *link_settings, 1291 enum clock_source_id clock_source) 1292 { 1293 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1294 struct bp_transmitter_control cntl = { 0 }; 1295 enum bp_result result; 1296 1297 /* Enable the PHY */ 1298 1299 /* number_of_lanes is used for pixel clock adjust, 1300 * but it's not passed to asic_control. 1301 * We need to set number of lanes manually. 1302 */ 1303 dce60_configure_encoder(enc110, link_settings); 1304 1305 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1306 cntl.engine_id = ENGINE_ID_UNKNOWN; 1307 cntl.transmitter = enc110->base.transmitter; 1308 cntl.pll_id = clock_source; 1309 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; 1310 cntl.lanes_number = link_settings->lane_count; 1311 cntl.hpd_sel = enc110->base.hpd_source; 1312 cntl.pixel_clock = link_settings->link_rate 1313 * LINK_RATE_REF_FREQ_IN_KHZ; 1314 /* TODO: check if undefined works */ 1315 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1316 1317 result = link_transmitter_control(enc110, &cntl); 1318 1319 if (result != BP_RESULT_OK) { 1320 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1321 __func__); 1322 BREAK_TO_DEBUGGER(); 1323 } 1324 } 1325 #endif 1326 1327 /* 1328 * @brief 1329 * Disable transmitter and its encoder 1330 */ 1331 void dce110_link_encoder_disable_output( 1332 struct link_encoder *enc, 1333 enum signal_type signal) 1334 { 1335 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1336 struct bp_transmitter_control cntl = { 0 }; 1337 enum bp_result result; 1338 1339 switch (enc->analog_engine) { 1340 case ENGINE_ID_DACA: 1341 REG_UPDATE(DAC_ENABLE, DAC_ENABLE, 0); 1342 break; 1343 case ENGINE_ID_DACB: 1344 /* DACB doesn't seem to be present on DCE6+, 1345 * although there are references to it in the register file. 1346 */ 1347 DC_LOG_ERROR("%s DACB is unsupported\n", __func__); 1348 break; 1349 default: 1350 break; 1351 } 1352 1353 /* The code below only applies to connectors that support digital signals. */ 1354 if (enc->transmitter == TRANSMITTER_UNKNOWN) 1355 return; 1356 1357 if (!dce110_is_dig_enabled(enc)) { 1358 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ 1359 return; 1360 } 1361 /* Power-down RX and disable GPU PHY should be paired. 1362 * Disabling PHY without powering down RX may cause 1363 * symbol lock loss, on which we will get DP Sink interrupt. */ 1364 1365 /* There is a case for the DP active dongles 1366 * where we want to disable the PHY but keep RX powered, 1367 * for those we need to ignore DP Sink interrupt 1368 * by checking lane count that has been set 1369 * on the last do_enable_output(). */ 1370 1371 /* disable transmitter */ 1372 cntl.action = TRANSMITTER_CONTROL_DISABLE; 1373 cntl.transmitter = enc110->base.transmitter; 1374 cntl.hpd_sel = enc110->base.hpd_source; 1375 cntl.signal = signal; 1376 cntl.connector_obj_id = enc110->base.connector; 1377 1378 result = link_transmitter_control(enc110, &cntl); 1379 1380 if (result != BP_RESULT_OK) { 1381 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1382 __func__); 1383 BREAK_TO_DEBUGGER(); 1384 return; 1385 } 1386 1387 /* disable encoder */ 1388 if (dc_is_dp_signal(signal)) 1389 link_encoder_disable(enc110); 1390 } 1391 1392 void dce110_link_encoder_dp_set_lane_settings( 1393 struct link_encoder *enc, 1394 const struct dc_link_settings *link_settings, 1395 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) 1396 { 1397 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1398 union dpcd_training_lane_set training_lane_set = { { 0 } }; 1399 int32_t lane = 0; 1400 struct bp_transmitter_control cntl = { 0 }; 1401 1402 if (!link_settings) { 1403 BREAK_TO_DEBUGGER(); 1404 return; 1405 } 1406 1407 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS; 1408 cntl.transmitter = enc110->base.transmitter; 1409 cntl.connector_obj_id = enc110->base.connector; 1410 cntl.lanes_number = link_settings->lane_count; 1411 cntl.hpd_sel = enc110->base.hpd_source; 1412 cntl.pixel_clock = link_settings->link_rate * 1413 LINK_RATE_REF_FREQ_IN_KHZ; 1414 1415 for (lane = 0; lane < link_settings->lane_count; lane++) { 1416 /* translate lane settings */ 1417 1418 training_lane_set.bits.VOLTAGE_SWING_SET = 1419 lane_settings[lane].VOLTAGE_SWING; 1420 training_lane_set.bits.PRE_EMPHASIS_SET = 1421 lane_settings[lane].PRE_EMPHASIS; 1422 1423 /* post cursor 2 setting only applies to HBR2 link rate */ 1424 if (link_settings->link_rate == LINK_RATE_HIGH2) { 1425 /* this is passed to VBIOS 1426 * to program post cursor 2 level */ 1427 1428 training_lane_set.bits.POST_CURSOR2_SET = 1429 lane_settings[lane].POST_CURSOR2; 1430 } 1431 1432 cntl.lane_select = lane; 1433 cntl.lane_settings = training_lane_set.raw; 1434 1435 /* call VBIOS table to set voltage swing and pre-emphasis */ 1436 if (link_transmitter_control(enc110, &cntl) != BP_RESULT_OK) { 1437 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", __func__); 1438 BREAK_TO_DEBUGGER(); 1439 } 1440 } 1441 } 1442 1443 /* set DP PHY test and training patterns */ 1444 void dce110_link_encoder_dp_set_phy_pattern( 1445 struct link_encoder *enc, 1446 const struct encoder_set_dp_phy_pattern_param *param) 1447 { 1448 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1449 1450 switch (param->dp_phy_pattern) { 1451 case DP_TEST_PATTERN_TRAINING_PATTERN1: 1452 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); 1453 break; 1454 case DP_TEST_PATTERN_TRAINING_PATTERN2: 1455 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); 1456 break; 1457 case DP_TEST_PATTERN_TRAINING_PATTERN3: 1458 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); 1459 break; 1460 case DP_TEST_PATTERN_TRAINING_PATTERN4: 1461 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3); 1462 break; 1463 case DP_TEST_PATTERN_D102: 1464 set_dp_phy_pattern_d102(enc110); 1465 break; 1466 case DP_TEST_PATTERN_SYMBOL_ERROR: 1467 set_dp_phy_pattern_symbol_error(enc110); 1468 break; 1469 case DP_TEST_PATTERN_PRBS7: 1470 set_dp_phy_pattern_prbs7(enc110); 1471 break; 1472 case DP_TEST_PATTERN_80BIT_CUSTOM: 1473 set_dp_phy_pattern_80bit_custom( 1474 enc110, param->custom_pattern); 1475 break; 1476 case DP_TEST_PATTERN_CP2520_1: 1477 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1); 1478 break; 1479 case DP_TEST_PATTERN_CP2520_2: 1480 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2); 1481 break; 1482 case DP_TEST_PATTERN_CP2520_3: 1483 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3); 1484 break; 1485 case DP_TEST_PATTERN_VIDEO_MODE: { 1486 set_dp_phy_pattern_passthrough_mode( 1487 enc110, param->dp_panel_mode); 1488 break; 1489 } 1490 1491 default: 1492 /* invalid phy pattern */ 1493 ASSERT_CRITICAL(false); 1494 break; 1495 } 1496 } 1497 1498 #if defined(CONFIG_DRM_AMD_DC_SI) 1499 /* set DP PHY test and training patterns */ 1500 static void dce60_link_encoder_dp_set_phy_pattern( 1501 struct link_encoder *enc, 1502 const struct encoder_set_dp_phy_pattern_param *param) 1503 { 1504 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1505 1506 switch (param->dp_phy_pattern) { 1507 case DP_TEST_PATTERN_TRAINING_PATTERN1: 1508 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); 1509 break; 1510 case DP_TEST_PATTERN_TRAINING_PATTERN2: 1511 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); 1512 break; 1513 case DP_TEST_PATTERN_TRAINING_PATTERN3: 1514 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); 1515 break; 1516 case DP_TEST_PATTERN_TRAINING_PATTERN4: 1517 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3); 1518 break; 1519 case DP_TEST_PATTERN_D102: 1520 set_dp_phy_pattern_d102(enc110); 1521 break; 1522 case DP_TEST_PATTERN_SYMBOL_ERROR: 1523 set_dp_phy_pattern_symbol_error(enc110); 1524 break; 1525 case DP_TEST_PATTERN_PRBS7: 1526 set_dp_phy_pattern_prbs7(enc110); 1527 break; 1528 case DP_TEST_PATTERN_80BIT_CUSTOM: 1529 set_dp_phy_pattern_80bit_custom( 1530 enc110, param->custom_pattern); 1531 break; 1532 case DP_TEST_PATTERN_CP2520_1: 1533 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1); 1534 break; 1535 case DP_TEST_PATTERN_CP2520_2: 1536 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2); 1537 break; 1538 case DP_TEST_PATTERN_CP2520_3: 1539 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3); 1540 break; 1541 case DP_TEST_PATTERN_VIDEO_MODE: { 1542 dce60_set_dp_phy_pattern_passthrough_mode( 1543 enc110, param->dp_panel_mode); 1544 break; 1545 } 1546 1547 default: 1548 /* invalid phy pattern */ 1549 ASSERT_CRITICAL(false); 1550 break; 1551 } 1552 } 1553 #endif 1554 1555 static void fill_stream_allocation_row_info( 1556 const struct link_mst_stream_allocation *stream_allocation, 1557 uint32_t *src, 1558 uint32_t *slots) 1559 { 1560 const struct stream_encoder *stream_enc = stream_allocation->stream_enc; 1561 1562 if (stream_enc) { 1563 *src = stream_enc->id; 1564 *slots = stream_allocation->slot_count; 1565 } else { 1566 *src = 0; 1567 *slots = 0; 1568 } 1569 } 1570 1571 /* programs DP MST VC payload allocation */ 1572 void dce110_link_encoder_update_mst_stream_allocation_table( 1573 struct link_encoder *enc, 1574 const struct link_mst_stream_allocation_table *table) 1575 { 1576 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1577 uint32_t value1 = 0; 1578 uint32_t value2 = 0; 1579 uint32_t slots = 0; 1580 uint32_t src = 0; 1581 uint32_t retries = 0; 1582 1583 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/ 1584 1585 /* --- Set MSE Stream Attribute - 1586 * Setup VC Payload Table on Tx Side, 1587 * Issue allocation change trigger 1588 * to commit payload on both tx and rx side */ 1589 1590 /* we should clean-up table each time */ 1591 1592 if (table->stream_count >= 1) { 1593 fill_stream_allocation_row_info( 1594 &table->stream_allocations[0], 1595 &src, 1596 &slots); 1597 } else { 1598 src = 0; 1599 slots = 0; 1600 } 1601 1602 REG_UPDATE_2(DP_MSE_SAT0, 1603 DP_MSE_SAT_SRC0, src, 1604 DP_MSE_SAT_SLOT_COUNT0, slots); 1605 1606 if (table->stream_count >= 2) { 1607 fill_stream_allocation_row_info( 1608 &table->stream_allocations[1], 1609 &src, 1610 &slots); 1611 } else { 1612 src = 0; 1613 slots = 0; 1614 } 1615 1616 REG_UPDATE_2(DP_MSE_SAT0, 1617 DP_MSE_SAT_SRC1, src, 1618 DP_MSE_SAT_SLOT_COUNT1, slots); 1619 1620 if (table->stream_count >= 3) { 1621 fill_stream_allocation_row_info( 1622 &table->stream_allocations[2], 1623 &src, 1624 &slots); 1625 } else { 1626 src = 0; 1627 slots = 0; 1628 } 1629 1630 REG_UPDATE_2(DP_MSE_SAT1, 1631 DP_MSE_SAT_SRC2, src, 1632 DP_MSE_SAT_SLOT_COUNT2, slots); 1633 1634 if (table->stream_count >= 4) { 1635 fill_stream_allocation_row_info( 1636 &table->stream_allocations[3], 1637 &src, 1638 &slots); 1639 } else { 1640 src = 0; 1641 slots = 0; 1642 } 1643 1644 REG_UPDATE_2(DP_MSE_SAT1, 1645 DP_MSE_SAT_SRC3, src, 1646 DP_MSE_SAT_SLOT_COUNT3, slots); 1647 1648 /* --- wait for transaction finish */ 1649 1650 /* send allocation change trigger (ACT) ? 1651 * this step first sends the ACT, 1652 * then double buffers the SAT into the hardware 1653 * making the new allocation active on the DP MST mode link */ 1654 1655 1656 /* DP_MSE_SAT_UPDATE: 1657 * 0 - No Action 1658 * 1 - Update SAT with trigger 1659 * 2 - Update SAT without trigger */ 1660 1661 REG_UPDATE(DP_MSE_SAT_UPDATE, 1662 DP_MSE_SAT_UPDATE, 1); 1663 1664 /* wait for update to complete 1665 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0) 1666 * then wait for the transmission 1667 * of at least 16 MTP headers on immediate local link. 1668 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0 1669 * a value of 1 indicates that DP MST mode 1670 * is in the 16 MTP keepout region after a VC has been added. 1671 * MST stream bandwidth (VC rate) can be configured 1672 * after this bit is cleared */ 1673 1674 do { 1675 udelay(10); 1676 1677 REG_READ(DP_MSE_SAT_UPDATE); 1678 1679 REG_GET(DP_MSE_SAT_UPDATE, 1680 DP_MSE_SAT_UPDATE, &value1); 1681 1682 REG_GET(DP_MSE_SAT_UPDATE, 1683 DP_MSE_16_MTP_KEEPOUT, &value2); 1684 1685 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */ 1686 if (!value1 && !value2) 1687 break; 1688 ++retries; 1689 } while (retries < DP_MST_UPDATE_MAX_RETRY); 1690 } 1691 1692 void dce110_link_encoder_connect_dig_be_to_fe( 1693 struct link_encoder *enc, 1694 enum engine_id engine, 1695 bool connect) 1696 { 1697 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1698 uint32_t field; 1699 1700 if (engine != ENGINE_ID_UNKNOWN) { 1701 1702 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); 1703 1704 if (connect) 1705 field |= get_frontend_source(engine); 1706 else 1707 field &= ~get_frontend_source(engine); 1708 1709 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field); 1710 } 1711 } 1712 1713 void dce110_link_encoder_enable_hpd(struct link_encoder *enc) 1714 { 1715 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1716 struct dc_context *ctx = enc110->base.ctx; 1717 uint32_t addr = HPD_REG(DC_HPD_CONTROL); 1718 uint32_t hpd_enable = 0; 1719 uint32_t value = dm_read_reg(ctx, addr); 1720 1721 hpd_enable = get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN); 1722 1723 if (hpd_enable == 0) 1724 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN); 1725 } 1726 1727 void dce110_link_encoder_disable_hpd(struct link_encoder *enc) 1728 { 1729 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); 1730 struct dc_context *ctx = enc110->base.ctx; 1731 uint32_t addr = HPD_REG(DC_HPD_CONTROL); 1732 uint32_t value = dm_read_reg(ctx, addr); 1733 1734 set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN); 1735 } 1736 1737 void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc, 1738 struct dc_link_settings *link_settings) 1739 { 1740 /* Set Default link settings */ 1741 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, 1742 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0}; 1743 1744 /* Higher link settings based on feature supported */ 1745 if (enc->features.flags.bits.IS_HBR2_CAPABLE) 1746 max_link_cap.link_rate = LINK_RATE_HIGH2; 1747 1748 if (enc->features.flags.bits.IS_HBR3_CAPABLE) 1749 max_link_cap.link_rate = LINK_RATE_HIGH3; 1750 1751 *link_settings = max_link_cap; 1752 } 1753 1754 #if defined(CONFIG_DRM_AMD_DC_SI) 1755 static const struct link_encoder_funcs dce60_lnk_enc_funcs = { 1756 .validate_output_with_stream = 1757 dce110_link_encoder_validate_output_with_stream, 1758 .hw_init = dce110_link_encoder_hw_init, 1759 .setup = dce110_link_encoder_setup, 1760 .enable_tmds_output = dce110_link_encoder_enable_tmds_output, 1761 .enable_dp_output = dce60_link_encoder_enable_dp_output, 1762 .enable_dp_mst_output = dce60_link_encoder_enable_dp_mst_output, 1763 .enable_lvds_output = dce110_link_encoder_enable_lvds_output, 1764 .disable_output = dce110_link_encoder_disable_output, 1765 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, 1766 .dp_set_phy_pattern = dce60_link_encoder_dp_set_phy_pattern, 1767 .update_mst_stream_allocation_table = 1768 dce110_link_encoder_update_mst_stream_allocation_table, 1769 .psr_program_dp_dphy_fast_training = 1770 dce110_psr_program_dp_dphy_fast_training, 1771 .psr_program_secondary_packet = dce110_psr_program_secondary_packet, 1772 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, 1773 .enable_hpd = dce110_link_encoder_enable_hpd, 1774 .disable_hpd = dce110_link_encoder_disable_hpd, 1775 .is_dig_enabled = dce110_is_dig_enabled, 1776 .destroy = dce110_link_encoder_destroy, 1777 .get_max_link_cap = dce110_link_encoder_get_max_link_cap, 1778 .get_dig_frontend = dce110_get_dig_frontend 1779 }; 1780 1781 void dce60_link_encoder_construct( 1782 struct dce110_link_encoder *enc110, 1783 const struct encoder_init_data *init_data, 1784 const struct encoder_feature_support *enc_features, 1785 const struct dce110_link_enc_registers *link_regs, 1786 const struct dce110_link_enc_aux_registers *aux_regs, 1787 const struct dce110_link_enc_hpd_registers *hpd_regs) 1788 { 1789 struct bp_encoder_cap_info bp_cap_info = {0}; 1790 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 1791 enum bp_result result = BP_RESULT_OK; 1792 1793 enc110->base.funcs = &dce60_lnk_enc_funcs; 1794 enc110->base.ctx = init_data->ctx; 1795 enc110->base.id = init_data->encoder; 1796 1797 enc110->base.hpd_source = init_data->hpd_source; 1798 enc110->base.connector = init_data->connector; 1799 1800 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 1801 enc110->base.analog_engine = init_data->analog_engine; 1802 1803 enc110->base.features = *enc_features; 1804 1805 enc110->base.transmitter = init_data->transmitter; 1806 1807 /* set the flag to indicate whether driver poll the I2C data pin 1808 * while doing the DP sink detect 1809 */ 1810 1811 /* if (dal_adapter_service_is_feature_supported(as, 1812 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 1813 enc110->base.features.flags.bits. 1814 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 1815 1816 enc110->base.output_signals = 1817 SIGNAL_TYPE_DVI_SINGLE_LINK | 1818 SIGNAL_TYPE_DVI_DUAL_LINK | 1819 SIGNAL_TYPE_LVDS | 1820 SIGNAL_TYPE_DISPLAY_PORT | 1821 SIGNAL_TYPE_DISPLAY_PORT_MST | 1822 SIGNAL_TYPE_EDP | 1823 SIGNAL_TYPE_HDMI_TYPE_A; 1824 1825 if ((enc110->base.connector.id == CONNECTOR_ID_DUAL_LINK_DVII || 1826 enc110->base.connector.id == CONNECTOR_ID_SINGLE_LINK_DVII) && 1827 enc110->base.analog_engine != ENGINE_ID_UNKNOWN) 1828 enc110->base.output_signals |= SIGNAL_TYPE_RGB; 1829 1830 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 1831 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 1832 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 1833 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 1834 * Prefer DIG assignment is decided by board design. 1835 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 1836 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 1837 * By this, adding DIGG should not hurt DCE 8.0. 1838 * This will let DCE 8.1 share DCE 8.0 as much as possible 1839 */ 1840 1841 enc110->link_regs = link_regs; 1842 enc110->aux_regs = aux_regs; 1843 enc110->hpd_regs = hpd_regs; 1844 1845 switch (enc110->base.transmitter) { 1846 case TRANSMITTER_UNIPHY_A: 1847 enc110->base.preferred_engine = ENGINE_ID_DIGA; 1848 break; 1849 case TRANSMITTER_UNIPHY_B: 1850 enc110->base.preferred_engine = ENGINE_ID_DIGB; 1851 break; 1852 case TRANSMITTER_UNIPHY_C: 1853 enc110->base.preferred_engine = ENGINE_ID_DIGC; 1854 break; 1855 case TRANSMITTER_UNIPHY_D: 1856 enc110->base.preferred_engine = ENGINE_ID_DIGD; 1857 break; 1858 case TRANSMITTER_UNIPHY_E: 1859 enc110->base.preferred_engine = ENGINE_ID_DIGE; 1860 break; 1861 case TRANSMITTER_UNIPHY_F: 1862 enc110->base.preferred_engine = ENGINE_ID_DIGF; 1863 break; 1864 case TRANSMITTER_UNIPHY_G: 1865 enc110->base.preferred_engine = ENGINE_ID_DIGG; 1866 break; 1867 default: 1868 if (init_data->analog_engine != ENGINE_ID_UNKNOWN) { 1869 /* The connector is analog-only, ie. VGA */ 1870 enc110->base.preferred_engine = init_data->analog_engine; 1871 enc110->base.output_signals = SIGNAL_TYPE_RGB; 1872 enc110->base.transmitter = TRANSMITTER_UNKNOWN; 1873 break; 1874 } 1875 ASSERT_CRITICAL(false); 1876 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; 1877 } 1878 1879 /* default to one to mirror Windows behavior */ 1880 enc110->base.features.flags.bits.HDMI_6GB_EN = 1; 1881 1882 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios, 1883 enc110->base.id, &bp_cap_info); 1884 1885 /* Override features with DCE-specific values */ 1886 if (result == BP_RESULT_OK) { 1887 enc110->base.features.flags.bits.IS_HBR2_CAPABLE = 1888 bp_cap_info.DP_HBR2_EN; 1889 enc110->base.features.flags.bits.IS_HBR3_CAPABLE = 1890 bp_cap_info.DP_HBR3_EN; 1891 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 1892 } else if (result != BP_RESULT_NORECORD) { 1893 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 1894 __func__, 1895 result); 1896 } 1897 if (enc110->base.ctx->dc->debug.hdmi20_disable) { 1898 enc110->base.features.flags.bits.HDMI_6GB_EN = 0; 1899 } 1900 } 1901 #endif 1902